1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * camss-vfe-4-7.c 4 * 5 * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module v4.7 6 * 7 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. 8 * Copyright (C) 2015-2018 Linaro Ltd. 9 */ 10 11 #include <linux/device.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/iopoll.h> 15 16 #include "camss.h" 17 #include "camss-vfe.h" 18 #include "camss-vfe-gen1.h" 19 20 21 #define VFE_0_HW_VERSION 0x000 22 23 #define VFE_0_GLOBAL_RESET_CMD 0x018 24 #define VFE_0_GLOBAL_RESET_CMD_CORE BIT(0) 25 #define VFE_0_GLOBAL_RESET_CMD_CAMIF BIT(1) 26 #define VFE_0_GLOBAL_RESET_CMD_BUS BIT(2) 27 #define VFE_0_GLOBAL_RESET_CMD_BUS_BDG BIT(3) 28 #define VFE_0_GLOBAL_RESET_CMD_REGISTER BIT(4) 29 #define VFE_0_GLOBAL_RESET_CMD_PM BIT(5) 30 #define VFE_0_GLOBAL_RESET_CMD_BUS_MISR BIT(6) 31 #define VFE_0_GLOBAL_RESET_CMD_TESTGEN BIT(7) 32 #define VFE_0_GLOBAL_RESET_CMD_DSP BIT(8) 33 #define VFE_0_GLOBAL_RESET_CMD_IDLE_CGC BIT(9) 34 35 #define VFE_0_MODULE_LENS_EN 0x040 36 #define VFE_0_MODULE_LENS_EN_DEMUX BIT(2) 37 #define VFE_0_MODULE_LENS_EN_CHROMA_UPSAMPLE BIT(3) 38 39 #define VFE_0_MODULE_ZOOM_EN 0x04c 40 #define VFE_0_MODULE_ZOOM_EN_SCALE_ENC BIT(1) 41 #define VFE_0_MODULE_ZOOM_EN_CROP_ENC BIT(2) 42 #define VFE_0_MODULE_ZOOM_EN_REALIGN_BUF BIT(9) 43 44 #define VFE_0_CORE_CFG 0x050 45 #define VFE_0_CORE_CFG_PIXEL_PATTERN_YCBYCR 0x4 46 #define VFE_0_CORE_CFG_PIXEL_PATTERN_YCRYCB 0x5 47 #define VFE_0_CORE_CFG_PIXEL_PATTERN_CBYCRY 0x6 48 #define VFE_0_CORE_CFG_PIXEL_PATTERN_CRYCBY 0x7 49 #define VFE_0_CORE_CFG_COMPOSITE_REG_UPDATE_EN BIT(4) 50 51 #define VFE_0_IRQ_CMD 0x058 52 #define VFE_0_IRQ_CMD_GLOBAL_CLEAR BIT(0) 53 54 #define VFE_0_IRQ_MASK_0 0x05c 55 #define VFE_0_IRQ_MASK_0_CAMIF_SOF BIT(0) 56 #define VFE_0_IRQ_MASK_0_CAMIF_EOF BIT(1) 57 #define VFE_0_IRQ_MASK_0_RDIn_REG_UPDATE(n) BIT((n) + 5) 58 #define VFE_0_IRQ_MASK_0_line_n_REG_UPDATE(n) \ 59 ((n) == VFE_LINE_PIX ? BIT(4) : VFE_0_IRQ_MASK_0_RDIn_REG_UPDATE(n)) 60 #define VFE_0_IRQ_MASK_0_IMAGE_MASTER_n_PING_PONG(n) BIT((n) + 8) 61 #define VFE_0_IRQ_MASK_0_IMAGE_COMPOSITE_DONE_n(n) BIT((n) + 25) 62 #define VFE_0_IRQ_MASK_0_RESET_ACK BIT(31) 63 #define VFE_0_IRQ_MASK_1 0x060 64 #define VFE_0_IRQ_MASK_1_CAMIF_ERROR BIT(0) 65 #define VFE_0_IRQ_MASK_1_VIOLATION BIT(7) 66 #define VFE_0_IRQ_MASK_1_BUS_BDG_HALT_ACK BIT(8) 67 #define VFE_0_IRQ_MASK_1_IMAGE_MASTER_n_BUS_OVERFLOW(n) BIT((n) + 9) 68 #define VFE_0_IRQ_MASK_1_RDIn_SOF(n) BIT((n) + 29) 69 70 #define VFE_0_IRQ_CLEAR_0 0x064 71 #define VFE_0_IRQ_CLEAR_1 0x068 72 73 #define VFE_0_IRQ_STATUS_0 0x06c 74 #define VFE_0_IRQ_STATUS_0_CAMIF_SOF BIT(0) 75 #define VFE_0_IRQ_STATUS_0_RDIn_REG_UPDATE(n) BIT((n) + 5) 76 #define VFE_0_IRQ_STATUS_0_line_n_REG_UPDATE(n) \ 77 ((n) == VFE_LINE_PIX ? BIT(4) : VFE_0_IRQ_STATUS_0_RDIn_REG_UPDATE(n)) 78 #define VFE_0_IRQ_STATUS_0_IMAGE_MASTER_n_PING_PONG(n) BIT((n) + 8) 79 #define VFE_0_IRQ_STATUS_0_IMAGE_COMPOSITE_DONE_n(n) BIT((n) + 25) 80 #define VFE_0_IRQ_STATUS_0_RESET_ACK BIT(31) 81 #define VFE_0_IRQ_STATUS_1 0x070 82 #define VFE_0_IRQ_STATUS_1_VIOLATION BIT(7) 83 #define VFE_0_IRQ_STATUS_1_BUS_BDG_HALT_ACK BIT(8) 84 #define VFE_0_IRQ_STATUS_1_RDIn_SOF(n) BIT((n) + 29) 85 86 #define VFE_0_IRQ_COMPOSITE_MASK_0 0x074 87 #define VFE_0_VIOLATION_STATUS 0x07c 88 89 #define VFE_0_BUS_CMD 0x80 90 #define VFE_0_BUS_CMD_Mx_RLD_CMD(x) BIT(x) 91 92 #define VFE_0_BUS_CFG 0x084 93 94 #define VFE_0_BUS_XBAR_CFG_x(x) (0x90 + 0x4 * ((x) / 2)) 95 #define VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_EN BIT(2) 96 #define VFE_0_BUS_XBAR_CFG_x_M_REALIGN_BUF_EN BIT(3) 97 #define VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_SWAP_INTRA (0x1 << 4) 98 #define VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_SWAP_INTER (0x2 << 4) 99 #define VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_SWAP_INTER_INTRA (0x3 << 4) 100 #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT 8 101 #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_LUMA 0x0 102 #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI0 0xc 103 #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI1 0xd 104 #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI2 0xe 105 106 #define VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(n) (0x0a0 + 0x2c * (n)) 107 #define VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_WR_PATH_SHIFT 0 108 #define VFE_0_BUS_IMAGE_MASTER_n_WR_PING_ADDR(n) (0x0a4 + 0x2c * (n)) 109 #define VFE_0_BUS_IMAGE_MASTER_n_WR_PONG_ADDR(n) (0x0ac + 0x2c * (n)) 110 #define VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(n) (0x0b4 + 0x2c * (n)) 111 #define VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_BASED_SHIFT 1 112 #define VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_SHIFT 2 113 #define VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_MASK (0x1f << 2) 114 #define VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG(n) (0x0b8 + 0x2c * (n)) 115 #define VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG_OFFSET_SHIFT 16 116 #define VFE_0_BUS_IMAGE_MASTER_n_WR_IMAGE_SIZE(n) (0x0bc + 0x2c * (n)) 117 #define VFE_0_BUS_IMAGE_MASTER_n_WR_BUFFER_CFG(n) (0x0c0 + 0x2c * (n)) 118 #define VFE_0_BUS_IMAGE_MASTER_n_WR_FRAMEDROP_PATTERN(n) \ 119 (0x0c4 + 0x2c * (n)) 120 #define VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN(n) \ 121 (0x0c8 + 0x2c * (n)) 122 #define VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN_DEF 0xffffffff 123 124 #define VFE_0_BUS_PING_PONG_STATUS 0x338 125 126 #define VFE_0_BUS_BDG_CMD 0x400 127 #define VFE_0_BUS_BDG_CMD_HALT_REQ 1 128 129 #define VFE_0_BUS_BDG_QOS_CFG_0 0x404 130 #define VFE_0_BUS_BDG_QOS_CFG_0_CFG 0xaaa9aaa9 131 #define VFE_0_BUS_BDG_QOS_CFG_1 0x408 132 #define VFE_0_BUS_BDG_QOS_CFG_2 0x40c 133 #define VFE_0_BUS_BDG_QOS_CFG_3 0x410 134 #define VFE_0_BUS_BDG_QOS_CFG_4 0x414 135 #define VFE_0_BUS_BDG_QOS_CFG_5 0x418 136 #define VFE_0_BUS_BDG_QOS_CFG_6 0x41c 137 #define VFE_0_BUS_BDG_QOS_CFG_7 0x420 138 #define VFE_0_BUS_BDG_QOS_CFG_7_CFG 0x0001aaa9 139 140 #define VFE48_0_BUS_BDG_QOS_CFG_0_CFG 0xaaa5aaa5 141 #define VFE48_0_BUS_BDG_QOS_CFG_3_CFG 0xaa55aaa5 142 #define VFE48_0_BUS_BDG_QOS_CFG_4_CFG 0xaa55aa55 143 #define VFE48_0_BUS_BDG_QOS_CFG_7_CFG 0x0005aa55 144 145 #define VFE_0_BUS_BDG_DS_CFG_0 0x424 146 #define VFE_0_BUS_BDG_DS_CFG_0_CFG 0xcccc0011 147 #define VFE_0_BUS_BDG_DS_CFG_1 0x428 148 #define VFE_0_BUS_BDG_DS_CFG_2 0x42c 149 #define VFE_0_BUS_BDG_DS_CFG_3 0x430 150 #define VFE_0_BUS_BDG_DS_CFG_4 0x434 151 #define VFE_0_BUS_BDG_DS_CFG_5 0x438 152 #define VFE_0_BUS_BDG_DS_CFG_6 0x43c 153 #define VFE_0_BUS_BDG_DS_CFG_7 0x440 154 #define VFE_0_BUS_BDG_DS_CFG_8 0x444 155 #define VFE_0_BUS_BDG_DS_CFG_9 0x448 156 #define VFE_0_BUS_BDG_DS_CFG_10 0x44c 157 #define VFE_0_BUS_BDG_DS_CFG_11 0x450 158 #define VFE_0_BUS_BDG_DS_CFG_12 0x454 159 #define VFE_0_BUS_BDG_DS_CFG_13 0x458 160 #define VFE_0_BUS_BDG_DS_CFG_14 0x45c 161 #define VFE_0_BUS_BDG_DS_CFG_15 0x460 162 #define VFE_0_BUS_BDG_DS_CFG_16 0x464 163 #define VFE_0_BUS_BDG_DS_CFG_16_CFG 0x40000103 164 165 #define VFE48_0_BUS_BDG_DS_CFG_0_CFG 0xcccc1111 166 #define VFE48_0_BUS_BDG_DS_CFG_16_CFG 0x00000110 167 168 #define VFE_0_RDI_CFG_x(x) (0x46c + (0x4 * (x))) 169 #define VFE_0_RDI_CFG_x_RDI_STREAM_SEL_SHIFT 28 170 #define VFE_0_RDI_CFG_x_RDI_STREAM_SEL_MASK (0xf << 28) 171 #define VFE_0_RDI_CFG_x_RDI_M0_SEL_SHIFT 4 172 #define VFE_0_RDI_CFG_x_RDI_M0_SEL_MASK (0xf << 4) 173 #define VFE_0_RDI_CFG_x_RDI_EN_BIT BIT(2) 174 #define VFE_0_RDI_CFG_x_MIPI_EN_BITS 0x3 175 176 #define VFE_0_CAMIF_CMD 0x478 177 #define VFE_0_CAMIF_CMD_DISABLE_FRAME_BOUNDARY 0 178 #define VFE_0_CAMIF_CMD_ENABLE_FRAME_BOUNDARY 1 179 #define VFE_0_CAMIF_CMD_NO_CHANGE 3 180 #define VFE_0_CAMIF_CMD_CLEAR_CAMIF_STATUS BIT(2) 181 #define VFE_0_CAMIF_CFG 0x47c 182 #define VFE_0_CAMIF_CFG_VFE_OUTPUT_EN BIT(6) 183 #define VFE_0_CAMIF_FRAME_CFG 0x484 184 #define VFE_0_CAMIF_WINDOW_WIDTH_CFG 0x488 185 #define VFE_0_CAMIF_WINDOW_HEIGHT_CFG 0x48c 186 #define VFE_0_CAMIF_SUBSAMPLE_CFG 0x490 187 #define VFE_0_CAMIF_IRQ_FRAMEDROP_PATTERN 0x498 188 #define VFE_0_CAMIF_IRQ_SUBSAMPLE_PATTERN 0x49c 189 #define VFE_0_CAMIF_STATUS 0x4a4 190 #define VFE_0_CAMIF_STATUS_HALT BIT(31) 191 192 #define VFE_0_REG_UPDATE 0x4ac 193 #define VFE_0_REG_UPDATE_RDIn(n) BIT(1 + (n)) 194 #define VFE_0_REG_UPDATE_line_n(n) \ 195 ((n) == VFE_LINE_PIX ? 1 : VFE_0_REG_UPDATE_RDIn(n)) 196 197 #define VFE_0_DEMUX_CFG 0x560 198 #define VFE_0_DEMUX_CFG_PERIOD 0x3 199 #define VFE_0_DEMUX_GAIN_0 0x564 200 #define VFE_0_DEMUX_GAIN_0_CH0_EVEN (0x80 << 0) 201 #define VFE_0_DEMUX_GAIN_0_CH0_ODD (0x80 << 16) 202 #define VFE_0_DEMUX_GAIN_1 0x568 203 #define VFE_0_DEMUX_GAIN_1_CH1 (0x80 << 0) 204 #define VFE_0_DEMUX_GAIN_1_CH2 (0x80 << 16) 205 #define VFE_0_DEMUX_EVEN_CFG 0x574 206 #define VFE_0_DEMUX_EVEN_CFG_PATTERN_YUYV 0x9cac 207 #define VFE_0_DEMUX_EVEN_CFG_PATTERN_YVYU 0xac9c 208 #define VFE_0_DEMUX_EVEN_CFG_PATTERN_UYVY 0xc9ca 209 #define VFE_0_DEMUX_EVEN_CFG_PATTERN_VYUY 0xcac9 210 #define VFE_0_DEMUX_ODD_CFG 0x578 211 #define VFE_0_DEMUX_ODD_CFG_PATTERN_YUYV 0x9cac 212 #define VFE_0_DEMUX_ODD_CFG_PATTERN_YVYU 0xac9c 213 #define VFE_0_DEMUX_ODD_CFG_PATTERN_UYVY 0xc9ca 214 #define VFE_0_DEMUX_ODD_CFG_PATTERN_VYUY 0xcac9 215 216 #define VFE_0_SCALE_ENC_Y_CFG 0x91c 217 #define VFE_0_SCALE_ENC_Y_H_IMAGE_SIZE 0x920 218 #define VFE_0_SCALE_ENC_Y_H_PHASE 0x924 219 #define VFE_0_SCALE_ENC_Y_V_IMAGE_SIZE 0x934 220 #define VFE_0_SCALE_ENC_Y_V_PHASE 0x938 221 #define VFE_0_SCALE_ENC_CBCR_CFG 0x948 222 #define VFE_0_SCALE_ENC_CBCR_H_IMAGE_SIZE 0x94c 223 #define VFE_0_SCALE_ENC_CBCR_H_PHASE 0x950 224 #define VFE_0_SCALE_ENC_CBCR_V_IMAGE_SIZE 0x960 225 #define VFE_0_SCALE_ENC_CBCR_V_PHASE 0x964 226 227 #define VFE_0_CROP_ENC_Y_WIDTH 0x974 228 #define VFE_0_CROP_ENC_Y_HEIGHT 0x978 229 #define VFE_0_CROP_ENC_CBCR_WIDTH 0x97c 230 #define VFE_0_CROP_ENC_CBCR_HEIGHT 0x980 231 232 #define VFE_0_CLAMP_ENC_MAX_CFG 0x984 233 #define VFE_0_CLAMP_ENC_MAX_CFG_CH0 (0xff << 0) 234 #define VFE_0_CLAMP_ENC_MAX_CFG_CH1 (0xff << 8) 235 #define VFE_0_CLAMP_ENC_MAX_CFG_CH2 (0xff << 16) 236 #define VFE_0_CLAMP_ENC_MIN_CFG 0x988 237 #define VFE_0_CLAMP_ENC_MIN_CFG_CH0 (0x0 << 0) 238 #define VFE_0_CLAMP_ENC_MIN_CFG_CH1 (0x0 << 8) 239 #define VFE_0_CLAMP_ENC_MIN_CFG_CH2 (0x0 << 16) 240 241 #define VFE_0_REALIGN_BUF_CFG 0xaac 242 #define VFE_0_REALIGN_BUF_CFG_CB_ODD_PIXEL BIT(2) 243 #define VFE_0_REALIGN_BUF_CFG_CR_ODD_PIXEL BIT(3) 244 #define VFE_0_REALIGN_BUF_CFG_HSUB_ENABLE BIT(4) 245 246 #define VFE48_0_BUS_IMAGE_MASTER_CMD 0xcec 247 #define VFE48_0_BUS_IMAGE_MASTER_n_SHIFT(x) (2 * (x)) 248 249 #define CAMIF_TIMEOUT_SLEEP_US 1000 250 #define CAMIF_TIMEOUT_ALL_US 1000000 251 252 #define MSM_VFE_VFE0_UB_SIZE 2047 253 #define MSM_VFE_VFE0_UB_SIZE_RDI (MSM_VFE_VFE0_UB_SIZE / 3) 254 #define MSM_VFE_VFE1_UB_SIZE 1535 255 #define MSM_VFE_VFE1_UB_SIZE_RDI (MSM_VFE_VFE1_UB_SIZE / 3) 256 257 static u32 vfe_hw_version(struct vfe_device *vfe) 258 { 259 u32 hw_version = readl_relaxed(vfe->base + VFE_0_HW_VERSION); 260 261 dev_dbg(vfe->camss->dev, "VFE HW Version = 0x%08x\n", hw_version); 262 263 return hw_version; 264 } 265 266 static u16 vfe_get_ub_size(u8 vfe_id) 267 { 268 if (vfe_id == 0) 269 return MSM_VFE_VFE0_UB_SIZE_RDI; 270 else if (vfe_id == 1) 271 return MSM_VFE_VFE1_UB_SIZE_RDI; 272 273 return 0; 274 } 275 276 static inline void vfe_reg_clr(struct vfe_device *vfe, u32 reg, u32 clr_bits) 277 { 278 u32 bits = readl_relaxed(vfe->base + reg); 279 280 writel_relaxed(bits & ~clr_bits, vfe->base + reg); 281 } 282 283 static inline void vfe_reg_set(struct vfe_device *vfe, u32 reg, u32 set_bits) 284 { 285 u32 bits = readl_relaxed(vfe->base + reg); 286 287 writel_relaxed(bits | set_bits, vfe->base + reg); 288 } 289 290 static void vfe_global_reset(struct vfe_device *vfe) 291 { 292 u32 reset_bits = VFE_0_GLOBAL_RESET_CMD_IDLE_CGC | 293 VFE_0_GLOBAL_RESET_CMD_DSP | 294 VFE_0_GLOBAL_RESET_CMD_TESTGEN | 295 VFE_0_GLOBAL_RESET_CMD_BUS_MISR | 296 VFE_0_GLOBAL_RESET_CMD_PM | 297 VFE_0_GLOBAL_RESET_CMD_REGISTER | 298 VFE_0_GLOBAL_RESET_CMD_BUS_BDG | 299 VFE_0_GLOBAL_RESET_CMD_BUS | 300 VFE_0_GLOBAL_RESET_CMD_CAMIF | 301 VFE_0_GLOBAL_RESET_CMD_CORE; 302 303 writel_relaxed(BIT(31), vfe->base + VFE_0_IRQ_MASK_0); 304 305 /* Enforce barrier between IRQ mask setup and global reset */ 306 wmb(); 307 writel_relaxed(reset_bits, vfe->base + VFE_0_GLOBAL_RESET_CMD); 308 } 309 310 static void vfe_halt_request(struct vfe_device *vfe) 311 { 312 writel_relaxed(VFE_0_BUS_BDG_CMD_HALT_REQ, 313 vfe->base + VFE_0_BUS_BDG_CMD); 314 } 315 316 static void vfe_halt_clear(struct vfe_device *vfe) 317 { 318 writel_relaxed(0x0, vfe->base + VFE_0_BUS_BDG_CMD); 319 } 320 321 static void vfe_wm_enable(struct vfe_device *vfe, u8 wm, u8 enable) 322 { 323 if (enable) 324 vfe_reg_set(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(wm), 325 1 << VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_WR_PATH_SHIFT); 326 else 327 vfe_reg_clr(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(wm), 328 1 << VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_WR_PATH_SHIFT); 329 } 330 331 static void vfe_wm_frame_based(struct vfe_device *vfe, u8 wm, u8 enable) 332 { 333 if (enable) 334 vfe_reg_set(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(wm), 335 1 << VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_BASED_SHIFT); 336 else 337 vfe_reg_clr(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(wm), 338 1 << VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_BASED_SHIFT); 339 } 340 341 #define CALC_WORD(width, M, N) (((width) * (M) + (N) - 1) / (N)) 342 343 static int vfe_word_per_line_by_pixel(u32 format, u32 pixel_per_line) 344 { 345 int val = 0; 346 347 switch (format) { 348 case V4L2_PIX_FMT_NV12: 349 case V4L2_PIX_FMT_NV21: 350 case V4L2_PIX_FMT_NV16: 351 case V4L2_PIX_FMT_NV61: 352 val = CALC_WORD(pixel_per_line, 1, 8); 353 break; 354 case V4L2_PIX_FMT_YUYV: 355 case V4L2_PIX_FMT_YVYU: 356 case V4L2_PIX_FMT_UYVY: 357 case V4L2_PIX_FMT_VYUY: 358 val = CALC_WORD(pixel_per_line, 2, 8); 359 break; 360 } 361 362 return val; 363 } 364 365 static int vfe_word_per_line_by_bytes(u32 bytes_per_line) 366 { 367 return CALC_WORD(bytes_per_line, 1, 8); 368 } 369 370 static void vfe_get_wm_sizes(struct v4l2_pix_format_mplane *pix, u8 plane, 371 u16 *width, u16 *height, u16 *bytesperline) 372 { 373 switch (pix->pixelformat) { 374 case V4L2_PIX_FMT_NV12: 375 case V4L2_PIX_FMT_NV21: 376 *width = pix->width; 377 *height = pix->height; 378 *bytesperline = pix->plane_fmt[0].bytesperline; 379 if (plane == 1) 380 *height /= 2; 381 break; 382 case V4L2_PIX_FMT_NV16: 383 case V4L2_PIX_FMT_NV61: 384 *width = pix->width; 385 *height = pix->height; 386 *bytesperline = pix->plane_fmt[0].bytesperline; 387 break; 388 case V4L2_PIX_FMT_YUYV: 389 case V4L2_PIX_FMT_YVYU: 390 case V4L2_PIX_FMT_VYUY: 391 case V4L2_PIX_FMT_UYVY: 392 *width = pix->width; 393 *height = pix->height; 394 *bytesperline = pix->plane_fmt[plane].bytesperline; 395 break; 396 397 } 398 } 399 400 static void vfe_wm_line_based(struct vfe_device *vfe, u32 wm, 401 struct v4l2_pix_format_mplane *pix, 402 u8 plane, u32 enable) 403 { 404 u32 reg; 405 406 if (enable) { 407 u16 width = 0, height = 0, bytesperline = 0, wpl; 408 409 vfe_get_wm_sizes(pix, plane, &width, &height, &bytesperline); 410 411 wpl = vfe_word_per_line_by_pixel(pix->pixelformat, width); 412 413 reg = height - 1; 414 reg |= ((wpl + 3) / 4 - 1) << 16; 415 416 writel_relaxed(reg, vfe->base + 417 VFE_0_BUS_IMAGE_MASTER_n_WR_IMAGE_SIZE(wm)); 418 419 wpl = vfe_word_per_line_by_bytes(bytesperline); 420 421 reg = 0x3; 422 reg |= (height - 1) << 2; 423 reg |= ((wpl + 1) / 2) << 16; 424 425 writel_relaxed(reg, vfe->base + 426 VFE_0_BUS_IMAGE_MASTER_n_WR_BUFFER_CFG(wm)); 427 } else { 428 writel_relaxed(0, vfe->base + 429 VFE_0_BUS_IMAGE_MASTER_n_WR_IMAGE_SIZE(wm)); 430 writel_relaxed(0, vfe->base + 431 VFE_0_BUS_IMAGE_MASTER_n_WR_BUFFER_CFG(wm)); 432 } 433 } 434 435 static void vfe_wm_set_framedrop_period(struct vfe_device *vfe, u8 wm, u8 per) 436 { 437 u32 reg; 438 439 reg = readl_relaxed(vfe->base + 440 VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(wm)); 441 442 reg &= ~(VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_MASK); 443 444 reg |= (per << VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_SHIFT) 445 & VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_MASK; 446 447 writel_relaxed(reg, 448 vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(wm)); 449 } 450 451 static void vfe_wm_set_framedrop_pattern(struct vfe_device *vfe, u8 wm, 452 u32 pattern) 453 { 454 writel_relaxed(pattern, 455 vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_FRAMEDROP_PATTERN(wm)); 456 } 457 458 static void vfe_wm_set_ub_cfg(struct vfe_device *vfe, u8 wm, 459 u16 offset, u16 depth) 460 { 461 u32 reg; 462 463 reg = (offset << VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG_OFFSET_SHIFT) | 464 depth; 465 writel_relaxed(reg, vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG(wm)); 466 } 467 468 static void vfe_bus_reload_wm(struct vfe_device *vfe, u8 wm) 469 { 470 /* Enforce barrier between any outstanding register write */ 471 wmb(); 472 473 writel_relaxed(VFE_0_BUS_CMD_Mx_RLD_CMD(wm), vfe->base + VFE_0_BUS_CMD); 474 475 /* Use barrier to make sure bus reload is issued before anything else */ 476 wmb(); 477 } 478 479 static void vfe_wm_set_ping_addr(struct vfe_device *vfe, u8 wm, u32 addr) 480 { 481 writel_relaxed(addr, 482 vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_PING_ADDR(wm)); 483 } 484 485 static void vfe_wm_set_pong_addr(struct vfe_device *vfe, u8 wm, u32 addr) 486 { 487 writel_relaxed(addr, 488 vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_PONG_ADDR(wm)); 489 } 490 491 static int vfe_wm_get_ping_pong_status(struct vfe_device *vfe, u8 wm) 492 { 493 u32 reg; 494 495 reg = readl_relaxed(vfe->base + VFE_0_BUS_PING_PONG_STATUS); 496 497 return (reg >> wm) & 0x1; 498 } 499 500 static void vfe_bus_enable_wr_if(struct vfe_device *vfe, u8 enable) 501 { 502 if (enable) 503 writel_relaxed(0x101, vfe->base + VFE_0_BUS_CFG); 504 else 505 writel_relaxed(0, vfe->base + VFE_0_BUS_CFG); 506 } 507 508 static void vfe_bus_connect_wm_to_rdi(struct vfe_device *vfe, u8 wm, 509 enum vfe_line_id id) 510 { 511 u32 reg; 512 513 reg = VFE_0_RDI_CFG_x_MIPI_EN_BITS; 514 vfe_reg_set(vfe, VFE_0_RDI_CFG_x(0), reg); 515 516 reg = VFE_0_RDI_CFG_x_RDI_EN_BIT; 517 reg |= ((3 * id) << VFE_0_RDI_CFG_x_RDI_STREAM_SEL_SHIFT) & 518 VFE_0_RDI_CFG_x_RDI_STREAM_SEL_MASK; 519 vfe_reg_set(vfe, VFE_0_RDI_CFG_x(id), reg); 520 521 switch (id) { 522 case VFE_LINE_RDI0: 523 default: 524 reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI0 << 525 VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 526 break; 527 case VFE_LINE_RDI1: 528 reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI1 << 529 VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 530 break; 531 case VFE_LINE_RDI2: 532 reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI2 << 533 VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 534 break; 535 } 536 537 if (wm % 2 == 1) 538 reg <<= 16; 539 540 vfe_reg_set(vfe, VFE_0_BUS_XBAR_CFG_x(wm), reg); 541 } 542 543 static void vfe_wm_set_subsample(struct vfe_device *vfe, u8 wm) 544 { 545 writel_relaxed(VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN_DEF, 546 vfe->base + 547 VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN(wm)); 548 } 549 550 static void vfe_bus_disconnect_wm_from_rdi(struct vfe_device *vfe, u8 wm, 551 enum vfe_line_id id) 552 { 553 u32 reg; 554 555 reg = VFE_0_RDI_CFG_x_RDI_EN_BIT; 556 vfe_reg_clr(vfe, VFE_0_RDI_CFG_x(id), reg); 557 558 switch (id) { 559 case VFE_LINE_RDI0: 560 default: 561 reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI0 << 562 VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 563 break; 564 case VFE_LINE_RDI1: 565 reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI1 << 566 VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 567 break; 568 case VFE_LINE_RDI2: 569 reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI2 << 570 VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 571 break; 572 } 573 574 if (wm % 2 == 1) 575 reg <<= 16; 576 577 vfe_reg_clr(vfe, VFE_0_BUS_XBAR_CFG_x(wm), reg); 578 } 579 580 static void vfe_set_xbar_cfg(struct vfe_device *vfe, struct vfe_output *output, 581 u8 enable) 582 { 583 struct vfe_line *line = container_of(output, struct vfe_line, output); 584 u32 p = line->video_out.active_fmt.fmt.pix_mp.pixelformat; 585 u32 reg; 586 587 switch (p) { 588 case V4L2_PIX_FMT_NV12: 589 case V4L2_PIX_FMT_NV21: 590 case V4L2_PIX_FMT_NV16: 591 case V4L2_PIX_FMT_NV61: 592 reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_LUMA << 593 VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 594 595 if (output->wm_idx[0] % 2 == 1) 596 reg <<= 16; 597 598 if (enable) 599 vfe_reg_set(vfe, 600 VFE_0_BUS_XBAR_CFG_x(output->wm_idx[0]), 601 reg); 602 else 603 vfe_reg_clr(vfe, 604 VFE_0_BUS_XBAR_CFG_x(output->wm_idx[0]), 605 reg); 606 607 reg = VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_EN; 608 if (p == V4L2_PIX_FMT_NV12 || p == V4L2_PIX_FMT_NV16) 609 reg |= VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_SWAP_INTER_INTRA; 610 611 if (output->wm_idx[1] % 2 == 1) 612 reg <<= 16; 613 614 if (enable) 615 vfe_reg_set(vfe, 616 VFE_0_BUS_XBAR_CFG_x(output->wm_idx[1]), 617 reg); 618 else 619 vfe_reg_clr(vfe, 620 VFE_0_BUS_XBAR_CFG_x(output->wm_idx[1]), 621 reg); 622 break; 623 case V4L2_PIX_FMT_YUYV: 624 case V4L2_PIX_FMT_YVYU: 625 case V4L2_PIX_FMT_VYUY: 626 case V4L2_PIX_FMT_UYVY: 627 reg = VFE_0_BUS_XBAR_CFG_x_M_REALIGN_BUF_EN; 628 reg |= VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_EN; 629 630 if (p == V4L2_PIX_FMT_YUYV || p == V4L2_PIX_FMT_YVYU) 631 reg |= VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_SWAP_INTER_INTRA; 632 633 if (output->wm_idx[0] % 2 == 1) 634 reg <<= 16; 635 636 if (enable) 637 vfe_reg_set(vfe, 638 VFE_0_BUS_XBAR_CFG_x(output->wm_idx[0]), 639 reg); 640 else 641 vfe_reg_clr(vfe, 642 VFE_0_BUS_XBAR_CFG_x(output->wm_idx[0]), 643 reg); 644 break; 645 default: 646 break; 647 } 648 } 649 650 static void vfe_set_realign_cfg(struct vfe_device *vfe, struct vfe_line *line, 651 u8 enable) 652 { 653 u32 p = line->video_out.active_fmt.fmt.pix_mp.pixelformat; 654 u32 val = VFE_0_MODULE_ZOOM_EN_REALIGN_BUF; 655 656 if (p != V4L2_PIX_FMT_YUYV && p != V4L2_PIX_FMT_YVYU && 657 p != V4L2_PIX_FMT_VYUY && p != V4L2_PIX_FMT_UYVY) 658 return; 659 660 if (enable) { 661 vfe_reg_set(vfe, VFE_0_MODULE_ZOOM_EN, val); 662 } else { 663 vfe_reg_clr(vfe, VFE_0_MODULE_ZOOM_EN, val); 664 return; 665 } 666 667 val = VFE_0_REALIGN_BUF_CFG_HSUB_ENABLE; 668 669 if (p == V4L2_PIX_FMT_UYVY || p == V4L2_PIX_FMT_YUYV) 670 val |= VFE_0_REALIGN_BUF_CFG_CR_ODD_PIXEL; 671 else 672 val |= VFE_0_REALIGN_BUF_CFG_CB_ODD_PIXEL; 673 674 writel_relaxed(val, vfe->base + VFE_0_REALIGN_BUF_CFG); 675 } 676 677 static void vfe_set_rdi_cid(struct vfe_device *vfe, enum vfe_line_id id, u8 cid) 678 { 679 vfe_reg_clr(vfe, VFE_0_RDI_CFG_x(id), 680 VFE_0_RDI_CFG_x_RDI_M0_SEL_MASK); 681 682 vfe_reg_set(vfe, VFE_0_RDI_CFG_x(id), 683 cid << VFE_0_RDI_CFG_x_RDI_M0_SEL_SHIFT); 684 } 685 686 static void vfe_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id) 687 { 688 vfe->reg_update |= VFE_0_REG_UPDATE_line_n(line_id); 689 690 /* Enforce barrier between line update and commit */ 691 wmb(); 692 writel_relaxed(vfe->reg_update, vfe->base + VFE_0_REG_UPDATE); 693 694 /* Make sure register update is issued before further reg writes */ 695 wmb(); 696 } 697 698 static inline void vfe_reg_update_clear(struct vfe_device *vfe, 699 enum vfe_line_id line_id) 700 { 701 vfe->reg_update &= ~VFE_0_REG_UPDATE_line_n(line_id); 702 } 703 704 static void vfe_enable_irq_wm_line(struct vfe_device *vfe, u8 wm, 705 enum vfe_line_id line_id, u8 enable) 706 { 707 u32 irq_en0 = VFE_0_IRQ_MASK_0_IMAGE_MASTER_n_PING_PONG(wm) | 708 VFE_0_IRQ_MASK_0_line_n_REG_UPDATE(line_id); 709 u32 irq_en1 = VFE_0_IRQ_MASK_1_IMAGE_MASTER_n_BUS_OVERFLOW(wm) | 710 VFE_0_IRQ_MASK_1_RDIn_SOF(line_id); 711 712 if (enable) { 713 vfe_reg_set(vfe, VFE_0_IRQ_MASK_0, irq_en0); 714 vfe_reg_set(vfe, VFE_0_IRQ_MASK_1, irq_en1); 715 } else { 716 vfe_reg_clr(vfe, VFE_0_IRQ_MASK_0, irq_en0); 717 vfe_reg_clr(vfe, VFE_0_IRQ_MASK_1, irq_en1); 718 } 719 } 720 721 static void vfe_enable_irq_pix_line(struct vfe_device *vfe, u8 comp, 722 enum vfe_line_id line_id, u8 enable) 723 { 724 struct vfe_output *output = &vfe->line[line_id].output; 725 unsigned int i; 726 u32 irq_en0; 727 u32 irq_en1; 728 u32 comp_mask = 0; 729 730 irq_en0 = VFE_0_IRQ_MASK_0_CAMIF_SOF; 731 irq_en0 |= VFE_0_IRQ_MASK_0_CAMIF_EOF; 732 irq_en0 |= VFE_0_IRQ_MASK_0_IMAGE_COMPOSITE_DONE_n(comp); 733 irq_en0 |= VFE_0_IRQ_MASK_0_line_n_REG_UPDATE(line_id); 734 irq_en1 = VFE_0_IRQ_MASK_1_CAMIF_ERROR; 735 for (i = 0; i < output->wm_num; i++) { 736 irq_en1 |= VFE_0_IRQ_MASK_1_IMAGE_MASTER_n_BUS_OVERFLOW( 737 output->wm_idx[i]); 738 comp_mask |= (1 << output->wm_idx[i]) << comp * 8; 739 } 740 741 if (enable) { 742 vfe_reg_set(vfe, VFE_0_IRQ_MASK_0, irq_en0); 743 vfe_reg_set(vfe, VFE_0_IRQ_MASK_1, irq_en1); 744 vfe_reg_set(vfe, VFE_0_IRQ_COMPOSITE_MASK_0, comp_mask); 745 } else { 746 vfe_reg_clr(vfe, VFE_0_IRQ_MASK_0, irq_en0); 747 vfe_reg_clr(vfe, VFE_0_IRQ_MASK_1, irq_en1); 748 vfe_reg_clr(vfe, VFE_0_IRQ_COMPOSITE_MASK_0, comp_mask); 749 } 750 } 751 752 static void vfe_enable_irq_common(struct vfe_device *vfe) 753 { 754 u32 irq_en0 = VFE_0_IRQ_MASK_0_RESET_ACK; 755 u32 irq_en1 = VFE_0_IRQ_MASK_1_VIOLATION | 756 VFE_0_IRQ_MASK_1_BUS_BDG_HALT_ACK; 757 758 vfe_reg_set(vfe, VFE_0_IRQ_MASK_0, irq_en0); 759 vfe_reg_set(vfe, VFE_0_IRQ_MASK_1, irq_en1); 760 } 761 762 static void vfe_set_demux_cfg(struct vfe_device *vfe, struct vfe_line *line) 763 { 764 u32 val, even_cfg, odd_cfg; 765 766 writel_relaxed(VFE_0_DEMUX_CFG_PERIOD, vfe->base + VFE_0_DEMUX_CFG); 767 768 val = VFE_0_DEMUX_GAIN_0_CH0_EVEN | VFE_0_DEMUX_GAIN_0_CH0_ODD; 769 writel_relaxed(val, vfe->base + VFE_0_DEMUX_GAIN_0); 770 771 val = VFE_0_DEMUX_GAIN_1_CH1 | VFE_0_DEMUX_GAIN_1_CH2; 772 writel_relaxed(val, vfe->base + VFE_0_DEMUX_GAIN_1); 773 774 switch (line->fmt[MSM_VFE_PAD_SINK].code) { 775 case MEDIA_BUS_FMT_YUYV8_2X8: 776 even_cfg = VFE_0_DEMUX_EVEN_CFG_PATTERN_YUYV; 777 odd_cfg = VFE_0_DEMUX_ODD_CFG_PATTERN_YUYV; 778 break; 779 case MEDIA_BUS_FMT_YVYU8_2X8: 780 even_cfg = VFE_0_DEMUX_EVEN_CFG_PATTERN_YVYU; 781 odd_cfg = VFE_0_DEMUX_ODD_CFG_PATTERN_YVYU; 782 break; 783 case MEDIA_BUS_FMT_UYVY8_2X8: 784 default: 785 even_cfg = VFE_0_DEMUX_EVEN_CFG_PATTERN_UYVY; 786 odd_cfg = VFE_0_DEMUX_ODD_CFG_PATTERN_UYVY; 787 break; 788 case MEDIA_BUS_FMT_VYUY8_2X8: 789 even_cfg = VFE_0_DEMUX_EVEN_CFG_PATTERN_VYUY; 790 odd_cfg = VFE_0_DEMUX_ODD_CFG_PATTERN_VYUY; 791 break; 792 } 793 794 writel_relaxed(even_cfg, vfe->base + VFE_0_DEMUX_EVEN_CFG); 795 writel_relaxed(odd_cfg, vfe->base + VFE_0_DEMUX_ODD_CFG); 796 } 797 798 static void vfe_set_scale_cfg(struct vfe_device *vfe, struct vfe_line *line) 799 { 800 u32 p = line->video_out.active_fmt.fmt.pix_mp.pixelformat; 801 u32 reg; 802 u16 input, output; 803 u8 interp_reso; 804 u32 phase_mult; 805 806 writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_Y_CFG); 807 808 input = line->fmt[MSM_VFE_PAD_SINK].width - 1; 809 output = line->compose.width - 1; 810 reg = (output << 16) | input; 811 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_H_IMAGE_SIZE); 812 813 interp_reso = vfe_calc_interp_reso(input, output); 814 phase_mult = input * (1 << (14 + interp_reso)) / output; 815 reg = (interp_reso << 28) | phase_mult; 816 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_H_PHASE); 817 818 input = line->fmt[MSM_VFE_PAD_SINK].height - 1; 819 output = line->compose.height - 1; 820 reg = (output << 16) | input; 821 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_V_IMAGE_SIZE); 822 823 interp_reso = vfe_calc_interp_reso(input, output); 824 phase_mult = input * (1 << (14 + interp_reso)) / output; 825 reg = (interp_reso << 28) | phase_mult; 826 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_V_PHASE); 827 828 writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_CBCR_CFG); 829 830 input = line->fmt[MSM_VFE_PAD_SINK].width - 1; 831 output = line->compose.width / 2 - 1; 832 reg = (output << 16) | input; 833 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_IMAGE_SIZE); 834 835 interp_reso = vfe_calc_interp_reso(input, output); 836 phase_mult = input * (1 << (14 + interp_reso)) / output; 837 reg = (interp_reso << 28) | phase_mult; 838 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_PHASE); 839 840 input = line->fmt[MSM_VFE_PAD_SINK].height - 1; 841 output = line->compose.height - 1; 842 if (p == V4L2_PIX_FMT_NV12 || p == V4L2_PIX_FMT_NV21) 843 output = line->compose.height / 2 - 1; 844 reg = (output << 16) | input; 845 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_IMAGE_SIZE); 846 847 interp_reso = vfe_calc_interp_reso(input, output); 848 phase_mult = input * (1 << (14 + interp_reso)) / output; 849 reg = (interp_reso << 28) | phase_mult; 850 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_PHASE); 851 } 852 853 static void vfe_set_crop_cfg(struct vfe_device *vfe, struct vfe_line *line) 854 { 855 u32 p = line->video_out.active_fmt.fmt.pix_mp.pixelformat; 856 u32 reg; 857 u16 first, last; 858 859 first = line->crop.left; 860 last = line->crop.left + line->crop.width - 1; 861 reg = (first << 16) | last; 862 writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_Y_WIDTH); 863 864 first = line->crop.top; 865 last = line->crop.top + line->crop.height - 1; 866 reg = (first << 16) | last; 867 writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_Y_HEIGHT); 868 869 first = line->crop.left / 2; 870 last = line->crop.left / 2 + line->crop.width / 2 - 1; 871 reg = (first << 16) | last; 872 writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_CBCR_WIDTH); 873 874 first = line->crop.top; 875 last = line->crop.top + line->crop.height - 1; 876 if (p == V4L2_PIX_FMT_NV12 || p == V4L2_PIX_FMT_NV21) { 877 first = line->crop.top / 2; 878 last = line->crop.top / 2 + line->crop.height / 2 - 1; 879 } 880 reg = (first << 16) | last; 881 writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_CBCR_HEIGHT); 882 } 883 884 static void vfe_set_clamp_cfg(struct vfe_device *vfe) 885 { 886 u32 val = VFE_0_CLAMP_ENC_MAX_CFG_CH0 | 887 VFE_0_CLAMP_ENC_MAX_CFG_CH1 | 888 VFE_0_CLAMP_ENC_MAX_CFG_CH2; 889 890 writel_relaxed(val, vfe->base + VFE_0_CLAMP_ENC_MAX_CFG); 891 892 val = VFE_0_CLAMP_ENC_MIN_CFG_CH0 | 893 VFE_0_CLAMP_ENC_MIN_CFG_CH1 | 894 VFE_0_CLAMP_ENC_MIN_CFG_CH2; 895 896 writel_relaxed(val, vfe->base + VFE_0_CLAMP_ENC_MIN_CFG); 897 } 898 899 static void vfe_set_qos(struct vfe_device *vfe) 900 { 901 u32 val = VFE_0_BUS_BDG_QOS_CFG_0_CFG; 902 u32 val7 = VFE_0_BUS_BDG_QOS_CFG_7_CFG; 903 904 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_0); 905 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_1); 906 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_2); 907 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_3); 908 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_4); 909 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_5); 910 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_6); 911 writel_relaxed(val7, vfe->base + VFE_0_BUS_BDG_QOS_CFG_7); 912 } 913 914 static void vfe_set_ds(struct vfe_device *vfe) 915 { 916 u32 val = VFE_0_BUS_BDG_DS_CFG_0_CFG; 917 u32 val16 = VFE_0_BUS_BDG_DS_CFG_16_CFG; 918 919 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_0); 920 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_1); 921 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_2); 922 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_3); 923 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_4); 924 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_5); 925 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_6); 926 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_7); 927 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_8); 928 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_9); 929 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_10); 930 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_11); 931 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_12); 932 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_13); 933 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_14); 934 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_15); 935 writel_relaxed(val16, vfe->base + VFE_0_BUS_BDG_DS_CFG_16); 936 } 937 938 static void vfe_set_cgc_override(struct vfe_device *vfe, u8 wm, u8 enable) 939 { 940 /* empty */ 941 } 942 943 static void vfe_set_camif_cfg(struct vfe_device *vfe, struct vfe_line *line) 944 { 945 u32 val; 946 947 switch (line->fmt[MSM_VFE_PAD_SINK].code) { 948 case MEDIA_BUS_FMT_YUYV8_2X8: 949 val = VFE_0_CORE_CFG_PIXEL_PATTERN_YCBYCR; 950 break; 951 case MEDIA_BUS_FMT_YVYU8_2X8: 952 val = VFE_0_CORE_CFG_PIXEL_PATTERN_YCRYCB; 953 break; 954 case MEDIA_BUS_FMT_UYVY8_2X8: 955 default: 956 val = VFE_0_CORE_CFG_PIXEL_PATTERN_CBYCRY; 957 break; 958 case MEDIA_BUS_FMT_VYUY8_2X8: 959 val = VFE_0_CORE_CFG_PIXEL_PATTERN_CRYCBY; 960 break; 961 } 962 963 val |= VFE_0_CORE_CFG_COMPOSITE_REG_UPDATE_EN; 964 writel_relaxed(val, vfe->base + VFE_0_CORE_CFG); 965 966 val = line->fmt[MSM_VFE_PAD_SINK].width * 2 - 1; 967 val |= (line->fmt[MSM_VFE_PAD_SINK].height - 1) << 16; 968 writel_relaxed(val, vfe->base + VFE_0_CAMIF_FRAME_CFG); 969 970 val = line->fmt[MSM_VFE_PAD_SINK].width * 2 - 1; 971 writel_relaxed(val, vfe->base + VFE_0_CAMIF_WINDOW_WIDTH_CFG); 972 973 val = line->fmt[MSM_VFE_PAD_SINK].height - 1; 974 writel_relaxed(val, vfe->base + VFE_0_CAMIF_WINDOW_HEIGHT_CFG); 975 976 val = 0xffffffff; 977 writel_relaxed(val, vfe->base + VFE_0_CAMIF_SUBSAMPLE_CFG); 978 979 val = 0xffffffff; 980 writel_relaxed(val, vfe->base + VFE_0_CAMIF_IRQ_FRAMEDROP_PATTERN); 981 982 val = 0xffffffff; 983 writel_relaxed(val, vfe->base + VFE_0_CAMIF_IRQ_SUBSAMPLE_PATTERN); 984 985 val = VFE_0_RDI_CFG_x_MIPI_EN_BITS; 986 vfe_reg_set(vfe, VFE_0_RDI_CFG_x(0), val); 987 988 val = VFE_0_CAMIF_CFG_VFE_OUTPUT_EN; 989 writel_relaxed(val, vfe->base + VFE_0_CAMIF_CFG); 990 } 991 992 static void vfe_set_camif_cmd(struct vfe_device *vfe, u8 enable) 993 { 994 u32 cmd; 995 996 cmd = VFE_0_CAMIF_CMD_CLEAR_CAMIF_STATUS | VFE_0_CAMIF_CMD_NO_CHANGE; 997 writel_relaxed(cmd, vfe->base + VFE_0_CAMIF_CMD); 998 999 /* Make sure camif command is issued written before it is changed again */ 1000 wmb(); 1001 1002 if (enable) 1003 cmd = VFE_0_CAMIF_CMD_ENABLE_FRAME_BOUNDARY; 1004 else 1005 cmd = VFE_0_CAMIF_CMD_DISABLE_FRAME_BOUNDARY; 1006 1007 writel_relaxed(cmd, vfe->base + VFE_0_CAMIF_CMD); 1008 } 1009 1010 static void vfe_set_module_cfg(struct vfe_device *vfe, u8 enable) 1011 { 1012 u32 val_lens = VFE_0_MODULE_LENS_EN_DEMUX | 1013 VFE_0_MODULE_LENS_EN_CHROMA_UPSAMPLE; 1014 u32 val_zoom = VFE_0_MODULE_ZOOM_EN_SCALE_ENC | 1015 VFE_0_MODULE_ZOOM_EN_CROP_ENC; 1016 1017 if (enable) { 1018 vfe_reg_set(vfe, VFE_0_MODULE_LENS_EN, val_lens); 1019 vfe_reg_set(vfe, VFE_0_MODULE_ZOOM_EN, val_zoom); 1020 } else { 1021 vfe_reg_clr(vfe, VFE_0_MODULE_LENS_EN, val_lens); 1022 vfe_reg_clr(vfe, VFE_0_MODULE_ZOOM_EN, val_zoom); 1023 } 1024 } 1025 1026 static int vfe_camif_wait_for_stop(struct vfe_device *vfe, struct device *dev) 1027 { 1028 u32 val; 1029 int ret; 1030 1031 ret = readl_poll_timeout(vfe->base + VFE_0_CAMIF_STATUS, 1032 val, 1033 (val & VFE_0_CAMIF_STATUS_HALT), 1034 CAMIF_TIMEOUT_SLEEP_US, 1035 CAMIF_TIMEOUT_ALL_US); 1036 if (ret < 0) 1037 dev_err(dev, "%s: camif stop timeout\n", __func__); 1038 1039 return ret; 1040 } 1041 1042 1043 1044 /* 1045 * vfe_isr - VFE module interrupt handler 1046 * @irq: Interrupt line 1047 * @dev: VFE device 1048 * 1049 * Return IRQ_HANDLED on success 1050 */ 1051 static irqreturn_t vfe_isr(int irq, void *dev) 1052 { 1053 struct vfe_device *vfe = dev; 1054 u32 value0, value1; 1055 int i, j; 1056 1057 vfe->ops->isr_read(vfe, &value0, &value1); 1058 1059 dev_dbg(vfe->camss->dev, "VFE: status0 = 0x%08x, status1 = 0x%08x\n", 1060 value0, value1); 1061 1062 if (value0 & VFE_0_IRQ_STATUS_0_RESET_ACK) 1063 vfe->isr_ops.reset_ack(vfe); 1064 1065 if (value1 & VFE_0_IRQ_STATUS_1_VIOLATION) 1066 vfe->ops->violation_read(vfe); 1067 1068 if (value1 & VFE_0_IRQ_STATUS_1_BUS_BDG_HALT_ACK) 1069 vfe->isr_ops.halt_ack(vfe); 1070 1071 for (i = VFE_LINE_RDI0; i < vfe->line_num; i++) 1072 if (value0 & VFE_0_IRQ_STATUS_0_line_n_REG_UPDATE(i)) 1073 vfe->isr_ops.reg_update(vfe, i); 1074 1075 if (value0 & VFE_0_IRQ_STATUS_0_CAMIF_SOF) 1076 vfe->isr_ops.sof(vfe, VFE_LINE_PIX); 1077 1078 for (i = VFE_LINE_RDI0; i <= VFE_LINE_RDI2; i++) 1079 if (value1 & VFE_0_IRQ_STATUS_1_RDIn_SOF(i)) 1080 vfe->isr_ops.sof(vfe, i); 1081 1082 for (i = 0; i < MSM_VFE_COMPOSITE_IRQ_NUM; i++) 1083 if (value0 & VFE_0_IRQ_STATUS_0_IMAGE_COMPOSITE_DONE_n(i)) { 1084 vfe->isr_ops.comp_done(vfe, i); 1085 for (j = 0; j < ARRAY_SIZE(vfe->wm_output_map); j++) 1086 if (vfe->wm_output_map[j] == VFE_LINE_PIX) 1087 value0 &= ~VFE_0_IRQ_MASK_0_IMAGE_MASTER_n_PING_PONG(j); 1088 } 1089 1090 for (i = 0; i < MSM_VFE_IMAGE_MASTERS_NUM; i++) 1091 if (value0 & VFE_0_IRQ_STATUS_0_IMAGE_MASTER_n_PING_PONG(i)) 1092 vfe->isr_ops.wm_done(vfe, i); 1093 1094 return IRQ_HANDLED; 1095 } 1096 1097 static void vfe_isr_read(struct vfe_device *vfe, u32 *value0, u32 *value1) 1098 { 1099 *value0 = readl_relaxed(vfe->base + VFE_0_IRQ_STATUS_0); 1100 *value1 = readl_relaxed(vfe->base + VFE_0_IRQ_STATUS_1); 1101 1102 writel_relaxed(*value0, vfe->base + VFE_0_IRQ_CLEAR_0); 1103 writel_relaxed(*value1, vfe->base + VFE_0_IRQ_CLEAR_1); 1104 1105 /* Enforce barrier between local & global IRQ clear */ 1106 wmb(); 1107 writel_relaxed(VFE_0_IRQ_CMD_GLOBAL_CLEAR, vfe->base + VFE_0_IRQ_CMD); 1108 } 1109 1110 /* 1111 * vfe_pm_domain_off - Disable power domains specific to this VFE. 1112 * @vfe: VFE Device 1113 */ 1114 static void vfe_pm_domain_off(struct vfe_device *vfe) 1115 { 1116 struct camss *camss; 1117 1118 if (!vfe) 1119 return; 1120 1121 camss = vfe->camss; 1122 1123 device_link_del(camss->genpd_link[vfe->id]); 1124 } 1125 1126 /* 1127 * vfe_pm_domain_on - Enable power domains specific to this VFE. 1128 * @vfe: VFE Device 1129 */ 1130 static int vfe_pm_domain_on(struct vfe_device *vfe) 1131 { 1132 struct camss *camss = vfe->camss; 1133 enum vfe_line_id id = vfe->id; 1134 1135 camss->genpd_link[id] = device_link_add(camss->dev, camss->genpd[id], DL_FLAG_STATELESS | 1136 DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE); 1137 1138 if (!camss->genpd_link[id]) { 1139 dev_err(vfe->camss->dev, "Failed to add VFE#%d to power domain\n", id); 1140 return -EINVAL; 1141 } 1142 1143 return 0; 1144 } 1145 1146 static void vfe_violation_read(struct vfe_device *vfe) 1147 { 1148 u32 violation = readl_relaxed(vfe->base + VFE_0_VIOLATION_STATUS); 1149 1150 pr_err_ratelimited("VFE: violation = 0x%08x\n", violation); 1151 } 1152 1153 static const struct vfe_hw_ops_gen1 vfe_ops_gen1_4_7 = { 1154 .bus_connect_wm_to_rdi = vfe_bus_connect_wm_to_rdi, 1155 .bus_disconnect_wm_from_rdi = vfe_bus_disconnect_wm_from_rdi, 1156 .bus_enable_wr_if = vfe_bus_enable_wr_if, 1157 .bus_reload_wm = vfe_bus_reload_wm, 1158 .camif_wait_for_stop = vfe_camif_wait_for_stop, 1159 .enable_irq_common = vfe_enable_irq_common, 1160 .enable_irq_pix_line = vfe_enable_irq_pix_line, 1161 .enable_irq_wm_line = vfe_enable_irq_wm_line, 1162 .get_ub_size = vfe_get_ub_size, 1163 .halt_clear = vfe_halt_clear, 1164 .halt_request = vfe_halt_request, 1165 .set_camif_cfg = vfe_set_camif_cfg, 1166 .set_camif_cmd = vfe_set_camif_cmd, 1167 .set_cgc_override = vfe_set_cgc_override, 1168 .set_clamp_cfg = vfe_set_clamp_cfg, 1169 .set_crop_cfg = vfe_set_crop_cfg, 1170 .set_demux_cfg = vfe_set_demux_cfg, 1171 .set_ds = vfe_set_ds, 1172 .set_module_cfg = vfe_set_module_cfg, 1173 .set_qos = vfe_set_qos, 1174 .set_rdi_cid = vfe_set_rdi_cid, 1175 .set_realign_cfg = vfe_set_realign_cfg, 1176 .set_scale_cfg = vfe_set_scale_cfg, 1177 .set_xbar_cfg = vfe_set_xbar_cfg, 1178 .wm_enable = vfe_wm_enable, 1179 .wm_frame_based = vfe_wm_frame_based, 1180 .wm_get_ping_pong_status = vfe_wm_get_ping_pong_status, 1181 .wm_line_based = vfe_wm_line_based, 1182 .wm_set_framedrop_pattern = vfe_wm_set_framedrop_pattern, 1183 .wm_set_framedrop_period = vfe_wm_set_framedrop_period, 1184 .wm_set_ping_addr = vfe_wm_set_ping_addr, 1185 .wm_set_pong_addr = vfe_wm_set_pong_addr, 1186 .wm_set_subsample = vfe_wm_set_subsample, 1187 .wm_set_ub_cfg = vfe_wm_set_ub_cfg, 1188 }; 1189 1190 static void vfe_subdev_init(struct device *dev, struct vfe_device *vfe) 1191 { 1192 vfe->isr_ops = vfe_isr_ops_gen1; 1193 vfe->ops_gen1 = &vfe_ops_gen1_4_7; 1194 vfe->video_ops = vfe_video_ops_gen1; 1195 1196 vfe->line_num = VFE_LINE_NUM_GEN1; 1197 } 1198 1199 const struct vfe_hw_ops vfe_ops_4_7 = { 1200 .global_reset = vfe_global_reset, 1201 .hw_version = vfe_hw_version, 1202 .isr_read = vfe_isr_read, 1203 .isr = vfe_isr, 1204 .pm_domain_off = vfe_pm_domain_off, 1205 .pm_domain_on = vfe_pm_domain_on, 1206 .reg_update_clear = vfe_reg_update_clear, 1207 .reg_update = vfe_reg_update, 1208 .subdev_init = vfe_subdev_init, 1209 .vfe_disable = vfe_gen1_disable, 1210 .vfe_enable = vfe_gen1_enable, 1211 .vfe_halt = vfe_gen1_halt, 1212 .violation_read = vfe_violation_read, 1213 }; 1214