xref: /openbmc/linux/drivers/media/platform/nxp/imx8-isi/imx8-isi-gasket.c (revision c900529f3d9161bfde5cca0754f83b4d3c3e0220)
1f48498adSGuoniu.zhou // SPDX-License-Identifier: GPL-2.0
2f48498adSGuoniu.zhou /*
3f48498adSGuoniu.zhou  * Copyright 2019-2023 NXP
4f48498adSGuoniu.zhou  */
5f48498adSGuoniu.zhou 
6f48498adSGuoniu.zhou #include <linux/regmap.h>
7f48498adSGuoniu.zhou 
8f48498adSGuoniu.zhou #include <media/mipi-csi2.h>
9f48498adSGuoniu.zhou 
10f48498adSGuoniu.zhou #include "imx8-isi-core.h"
11f48498adSGuoniu.zhou 
12f48498adSGuoniu.zhou /* -----------------------------------------------------------------------------
13f48498adSGuoniu.zhou  * i.MX8MN and i.MX8MP gasket
14f48498adSGuoniu.zhou  */
15f48498adSGuoniu.zhou 
16f48498adSGuoniu.zhou #define GASKET_BASE(n)				(0x0060 + (n) * 0x30)
17f48498adSGuoniu.zhou 
18f48498adSGuoniu.zhou #define GASKET_CTRL				0x0000
19f48498adSGuoniu.zhou #define GASKET_CTRL_DATA_TYPE(dt)		((dt) << 8)
20f48498adSGuoniu.zhou #define GASKET_CTRL_DATA_TYPE_MASK		(0x3f << 8)
21f48498adSGuoniu.zhou #define GASKET_CTRL_DUAL_COMP_ENABLE		BIT(1)
22f48498adSGuoniu.zhou #define GASKET_CTRL_ENABLE			BIT(0)
23f48498adSGuoniu.zhou 
24f48498adSGuoniu.zhou #define GASKET_HSIZE				0x0004
25f48498adSGuoniu.zhou #define GASKET_VSIZE				0x0008
26f48498adSGuoniu.zhou 
mxc_imx8_gasket_enable(struct mxc_isi_dev * isi,const struct v4l2_mbus_frame_desc * fd,const struct v4l2_mbus_framefmt * fmt,const unsigned int port)27f48498adSGuoniu.zhou static void mxc_imx8_gasket_enable(struct mxc_isi_dev *isi,
28f48498adSGuoniu.zhou 				   const struct v4l2_mbus_frame_desc *fd,
29f48498adSGuoniu.zhou 				   const struct v4l2_mbus_framefmt *fmt,
30f48498adSGuoniu.zhou 				   const unsigned int port)
31f48498adSGuoniu.zhou {
32f48498adSGuoniu.zhou 	u32 val;
33f48498adSGuoniu.zhou 
34f48498adSGuoniu.zhou 	regmap_write(isi->gasket, GASKET_BASE(port) + GASKET_HSIZE, fmt->width);
35f48498adSGuoniu.zhou 	regmap_write(isi->gasket, GASKET_BASE(port) + GASKET_VSIZE, fmt->height);
36f48498adSGuoniu.zhou 
37f48498adSGuoniu.zhou 	val = GASKET_CTRL_DATA_TYPE(fd->entry[0].bus.csi2.dt);
38f48498adSGuoniu.zhou 	if (fd->entry[0].bus.csi2.dt == MIPI_CSI2_DT_YUV422_8B)
39f48498adSGuoniu.zhou 		val |= GASKET_CTRL_DUAL_COMP_ENABLE;
40f48498adSGuoniu.zhou 
41f48498adSGuoniu.zhou 	val |= GASKET_CTRL_ENABLE;
42f48498adSGuoniu.zhou 	regmap_write(isi->gasket, GASKET_BASE(port) + GASKET_CTRL, val);
43f48498adSGuoniu.zhou }
44f48498adSGuoniu.zhou 
mxc_imx8_gasket_disable(struct mxc_isi_dev * isi,const unsigned int port)45f48498adSGuoniu.zhou static void mxc_imx8_gasket_disable(struct mxc_isi_dev *isi,
46f48498adSGuoniu.zhou 				    const unsigned int port)
47f48498adSGuoniu.zhou {
48f48498adSGuoniu.zhou 	regmap_write(isi->gasket, GASKET_BASE(port) + GASKET_CTRL, 0);
49f48498adSGuoniu.zhou }
50f48498adSGuoniu.zhou 
51f48498adSGuoniu.zhou const struct mxc_gasket_ops mxc_imx8_gasket_ops = {
52f48498adSGuoniu.zhou 	.enable = mxc_imx8_gasket_enable,
53f48498adSGuoniu.zhou 	.disable = mxc_imx8_gasket_disable,
54f48498adSGuoniu.zhou };
55*12cc6da3SGuoniu.zhou 
56*12cc6da3SGuoniu.zhou /* -----------------------------------------------------------------------------
57*12cc6da3SGuoniu.zhou  * i.MX93 gasket
58*12cc6da3SGuoniu.zhou  */
59*12cc6da3SGuoniu.zhou 
60*12cc6da3SGuoniu.zhou #define DISP_MIX_CAMERA_MUX                     0x30
61*12cc6da3SGuoniu.zhou #define DISP_MIX_CAMERA_MUX_DATA_TYPE(x)        (((x) & 0x3f) << 3)
62*12cc6da3SGuoniu.zhou #define DISP_MIX_CAMERA_MUX_GASKET_ENABLE       BIT(16)
63*12cc6da3SGuoniu.zhou 
mxc_imx93_gasket_enable(struct mxc_isi_dev * isi,const struct v4l2_mbus_frame_desc * fd,const struct v4l2_mbus_framefmt * fmt,const unsigned int port)64*12cc6da3SGuoniu.zhou static void mxc_imx93_gasket_enable(struct mxc_isi_dev *isi,
65*12cc6da3SGuoniu.zhou 				    const struct v4l2_mbus_frame_desc *fd,
66*12cc6da3SGuoniu.zhou 				    const struct v4l2_mbus_framefmt *fmt,
67*12cc6da3SGuoniu.zhou 				    const unsigned int port)
68*12cc6da3SGuoniu.zhou {
69*12cc6da3SGuoniu.zhou 	u32 val;
70*12cc6da3SGuoniu.zhou 
71*12cc6da3SGuoniu.zhou 	val = DISP_MIX_CAMERA_MUX_DATA_TYPE(fd->entry[0].bus.csi2.dt);
72*12cc6da3SGuoniu.zhou 	val |= DISP_MIX_CAMERA_MUX_GASKET_ENABLE;
73*12cc6da3SGuoniu.zhou 	regmap_write(isi->gasket, DISP_MIX_CAMERA_MUX, val);
74*12cc6da3SGuoniu.zhou }
75*12cc6da3SGuoniu.zhou 
mxc_imx93_gasket_disable(struct mxc_isi_dev * isi,unsigned int port)76*12cc6da3SGuoniu.zhou static void mxc_imx93_gasket_disable(struct mxc_isi_dev *isi,
77*12cc6da3SGuoniu.zhou 				     unsigned int port)
78*12cc6da3SGuoniu.zhou {
79*12cc6da3SGuoniu.zhou 	regmap_write(isi->gasket, DISP_MIX_CAMERA_MUX, 0);
80*12cc6da3SGuoniu.zhou }
81*12cc6da3SGuoniu.zhou 
82*12cc6da3SGuoniu.zhou const struct mxc_gasket_ops mxc_imx93_gasket_ops = {
83*12cc6da3SGuoniu.zhou 	.enable = mxc_imx93_gasket_enable,
84*12cc6da3SGuoniu.zhou 	.disable = mxc_imx93_gasket_disable,
85*12cc6da3SGuoniu.zhou };
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