1*c942fddfSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 2b285192aSMauro Carvalho Chehab /* 3b285192aSMauro Carvalho Chehab * cx18 System Control Block initialization 4b285192aSMauro Carvalho Chehab * 5b285192aSMauro Carvalho Chehab * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl> 6b285192aSMauro Carvalho Chehab * Copyright (C) 2008 Andy Walls <awalls@md.metrocast.net> 7b285192aSMauro Carvalho Chehab */ 8b285192aSMauro Carvalho Chehab 9b285192aSMauro Carvalho Chehab #ifndef CX18_SCB_H 10b285192aSMauro Carvalho Chehab #define CX18_SCB_H 11b285192aSMauro Carvalho Chehab 12b285192aSMauro Carvalho Chehab #include "cx18-mailbox.h" 13b285192aSMauro Carvalho Chehab 14b285192aSMauro Carvalho Chehab /* NOTE: All ACK interrupts are in the SW2 register. All non-ACK interrupts 15b285192aSMauro Carvalho Chehab are in the SW1 register. */ 16b285192aSMauro Carvalho Chehab 17b285192aSMauro Carvalho Chehab #define IRQ_APU_TO_CPU 0x00000001 18b285192aSMauro Carvalho Chehab #define IRQ_CPU_TO_APU_ACK 0x00000001 19b285192aSMauro Carvalho Chehab #define IRQ_HPU_TO_CPU 0x00000002 20b285192aSMauro Carvalho Chehab #define IRQ_CPU_TO_HPU_ACK 0x00000002 21b285192aSMauro Carvalho Chehab #define IRQ_PPU_TO_CPU 0x00000004 22b285192aSMauro Carvalho Chehab #define IRQ_CPU_TO_PPU_ACK 0x00000004 23b285192aSMauro Carvalho Chehab #define IRQ_EPU_TO_CPU 0x00000008 24b285192aSMauro Carvalho Chehab #define IRQ_CPU_TO_EPU_ACK 0x00000008 25b285192aSMauro Carvalho Chehab 26b285192aSMauro Carvalho Chehab #define IRQ_CPU_TO_APU 0x00000010 27b285192aSMauro Carvalho Chehab #define IRQ_APU_TO_CPU_ACK 0x00000010 28b285192aSMauro Carvalho Chehab #define IRQ_HPU_TO_APU 0x00000020 29b285192aSMauro Carvalho Chehab #define IRQ_APU_TO_HPU_ACK 0x00000020 30b285192aSMauro Carvalho Chehab #define IRQ_PPU_TO_APU 0x00000040 31b285192aSMauro Carvalho Chehab #define IRQ_APU_TO_PPU_ACK 0x00000040 32b285192aSMauro Carvalho Chehab #define IRQ_EPU_TO_APU 0x00000080 33b285192aSMauro Carvalho Chehab #define IRQ_APU_TO_EPU_ACK 0x00000080 34b285192aSMauro Carvalho Chehab 35b285192aSMauro Carvalho Chehab #define IRQ_CPU_TO_HPU 0x00000100 36b285192aSMauro Carvalho Chehab #define IRQ_HPU_TO_CPU_ACK 0x00000100 37b285192aSMauro Carvalho Chehab #define IRQ_APU_TO_HPU 0x00000200 38b285192aSMauro Carvalho Chehab #define IRQ_HPU_TO_APU_ACK 0x00000200 39b285192aSMauro Carvalho Chehab #define IRQ_PPU_TO_HPU 0x00000400 40b285192aSMauro Carvalho Chehab #define IRQ_HPU_TO_PPU_ACK 0x00000400 41b285192aSMauro Carvalho Chehab #define IRQ_EPU_TO_HPU 0x00000800 42b285192aSMauro Carvalho Chehab #define IRQ_HPU_TO_EPU_ACK 0x00000800 43b285192aSMauro Carvalho Chehab 44b285192aSMauro Carvalho Chehab #define IRQ_CPU_TO_PPU 0x00001000 45b285192aSMauro Carvalho Chehab #define IRQ_PPU_TO_CPU_ACK 0x00001000 46b285192aSMauro Carvalho Chehab #define IRQ_APU_TO_PPU 0x00002000 47b285192aSMauro Carvalho Chehab #define IRQ_PPU_TO_APU_ACK 0x00002000 48b285192aSMauro Carvalho Chehab #define IRQ_HPU_TO_PPU 0x00004000 49b285192aSMauro Carvalho Chehab #define IRQ_PPU_TO_HPU_ACK 0x00004000 50b285192aSMauro Carvalho Chehab #define IRQ_EPU_TO_PPU 0x00008000 51b285192aSMauro Carvalho Chehab #define IRQ_PPU_TO_EPU_ACK 0x00008000 52b285192aSMauro Carvalho Chehab 53b285192aSMauro Carvalho Chehab #define IRQ_CPU_TO_EPU 0x00010000 54b285192aSMauro Carvalho Chehab #define IRQ_EPU_TO_CPU_ACK 0x00010000 55b285192aSMauro Carvalho Chehab #define IRQ_APU_TO_EPU 0x00020000 56b285192aSMauro Carvalho Chehab #define IRQ_EPU_TO_APU_ACK 0x00020000 57b285192aSMauro Carvalho Chehab #define IRQ_HPU_TO_EPU 0x00040000 58b285192aSMauro Carvalho Chehab #define IRQ_EPU_TO_HPU_ACK 0x00040000 59b285192aSMauro Carvalho Chehab #define IRQ_PPU_TO_EPU 0x00080000 60b285192aSMauro Carvalho Chehab #define IRQ_EPU_TO_PPU_ACK 0x00080000 61b285192aSMauro Carvalho Chehab 62b285192aSMauro Carvalho Chehab #define SCB_OFFSET 0xDC0000 63b285192aSMauro Carvalho Chehab 64b285192aSMauro Carvalho Chehab /* If Firmware uses fixed memory map, it shall not allocate the area 65b285192aSMauro Carvalho Chehab between SCB_OFFSET and SCB_OFFSET+SCB_RESERVED_SIZE-1 inclusive */ 66b285192aSMauro Carvalho Chehab #define SCB_RESERVED_SIZE 0x10000 67b285192aSMauro Carvalho Chehab 68b285192aSMauro Carvalho Chehab 69b285192aSMauro Carvalho Chehab /* This structure is used by EPU to provide memory descriptors in its memory */ 70b285192aSMauro Carvalho Chehab struct cx18_mdl_ent { 71b285192aSMauro Carvalho Chehab u32 paddr; /* Physical address of a buffer segment */ 72b285192aSMauro Carvalho Chehab u32 length; /* Length of the buffer segment */ 73b285192aSMauro Carvalho Chehab }; 74b285192aSMauro Carvalho Chehab 75b285192aSMauro Carvalho Chehab struct cx18_scb { 76b285192aSMauro Carvalho Chehab /* These fields form the System Control Block which is used at boot time 77b285192aSMauro Carvalho Chehab for localizing the IPC data as well as the code positions for all 78b285192aSMauro Carvalho Chehab processors. The offsets are from the start of this struct. */ 79b285192aSMauro Carvalho Chehab 80b285192aSMauro Carvalho Chehab /* Offset where to find the Inter-Processor Communication data */ 81b285192aSMauro Carvalho Chehab u32 ipc_offset; 82b285192aSMauro Carvalho Chehab u32 reserved01[7]; 83b285192aSMauro Carvalho Chehab /* Offset where to find the start of the CPU code */ 84b285192aSMauro Carvalho Chehab u32 cpu_code_offset; 85b285192aSMauro Carvalho Chehab u32 reserved02[3]; 86b285192aSMauro Carvalho Chehab /* Offset where to find the start of the APU code */ 87b285192aSMauro Carvalho Chehab u32 apu_code_offset; 88b285192aSMauro Carvalho Chehab u32 reserved03[3]; 89b285192aSMauro Carvalho Chehab /* Offset where to find the start of the HPU code */ 90b285192aSMauro Carvalho Chehab u32 hpu_code_offset; 91b285192aSMauro Carvalho Chehab u32 reserved04[3]; 92b285192aSMauro Carvalho Chehab /* Offset where to find the start of the PPU code */ 93b285192aSMauro Carvalho Chehab u32 ppu_code_offset; 94b285192aSMauro Carvalho Chehab u32 reserved05[3]; 95b285192aSMauro Carvalho Chehab 96b285192aSMauro Carvalho Chehab /* These fields form Inter-Processor Communication data which is used 97b285192aSMauro Carvalho Chehab by all processors to locate the information needed for communicating 98b285192aSMauro Carvalho Chehab with other processors */ 99b285192aSMauro Carvalho Chehab 100b285192aSMauro Carvalho Chehab /* Fields for CPU: */ 101b285192aSMauro Carvalho Chehab 102b285192aSMauro Carvalho Chehab /* bit 0: 1/0 processor ready/not ready. Set other bits to 0. */ 103b285192aSMauro Carvalho Chehab u32 cpu_state; 104b285192aSMauro Carvalho Chehab u32 reserved1[7]; 105b285192aSMauro Carvalho Chehab /* Offset to the mailbox used for sending commands from APU to CPU */ 106b285192aSMauro Carvalho Chehab u32 apu2cpu_mb_offset; 107b285192aSMauro Carvalho Chehab /* Value to write to register SW1 register set (0xC7003100) after the 108b285192aSMauro Carvalho Chehab command is ready */ 109b285192aSMauro Carvalho Chehab u32 apu2cpu_irq; 110b285192aSMauro Carvalho Chehab /* Value to write to register SW2 register set (0xC7003140) after the 111b285192aSMauro Carvalho Chehab command is cleared */ 112b285192aSMauro Carvalho Chehab u32 cpu2apu_irq_ack; 113b285192aSMauro Carvalho Chehab u32 reserved2[13]; 114b285192aSMauro Carvalho Chehab 115b285192aSMauro Carvalho Chehab u32 hpu2cpu_mb_offset; 116b285192aSMauro Carvalho Chehab u32 hpu2cpu_irq; 117b285192aSMauro Carvalho Chehab u32 cpu2hpu_irq_ack; 118b285192aSMauro Carvalho Chehab u32 reserved3[13]; 119b285192aSMauro Carvalho Chehab 120b285192aSMauro Carvalho Chehab u32 ppu2cpu_mb_offset; 121b285192aSMauro Carvalho Chehab u32 ppu2cpu_irq; 122b285192aSMauro Carvalho Chehab u32 cpu2ppu_irq_ack; 123b285192aSMauro Carvalho Chehab u32 reserved4[13]; 124b285192aSMauro Carvalho Chehab 125b285192aSMauro Carvalho Chehab u32 epu2cpu_mb_offset; 126b285192aSMauro Carvalho Chehab u32 epu2cpu_irq; 127b285192aSMauro Carvalho Chehab u32 cpu2epu_irq_ack; 128b285192aSMauro Carvalho Chehab u32 reserved5[13]; 129b285192aSMauro Carvalho Chehab u32 reserved6[8]; 130b285192aSMauro Carvalho Chehab 131b285192aSMauro Carvalho Chehab /* Fields for APU: */ 132b285192aSMauro Carvalho Chehab 133b285192aSMauro Carvalho Chehab u32 apu_state; 134b285192aSMauro Carvalho Chehab u32 reserved11[7]; 135b285192aSMauro Carvalho Chehab u32 cpu2apu_mb_offset; 136b285192aSMauro Carvalho Chehab u32 cpu2apu_irq; 137b285192aSMauro Carvalho Chehab u32 apu2cpu_irq_ack; 138b285192aSMauro Carvalho Chehab u32 reserved12[13]; 139b285192aSMauro Carvalho Chehab 140b285192aSMauro Carvalho Chehab u32 hpu2apu_mb_offset; 141b285192aSMauro Carvalho Chehab u32 hpu2apu_irq; 142b285192aSMauro Carvalho Chehab u32 apu2hpu_irq_ack; 143b285192aSMauro Carvalho Chehab u32 reserved13[13]; 144b285192aSMauro Carvalho Chehab 145b285192aSMauro Carvalho Chehab u32 ppu2apu_mb_offset; 146b285192aSMauro Carvalho Chehab u32 ppu2apu_irq; 147b285192aSMauro Carvalho Chehab u32 apu2ppu_irq_ack; 148b285192aSMauro Carvalho Chehab u32 reserved14[13]; 149b285192aSMauro Carvalho Chehab 150b285192aSMauro Carvalho Chehab u32 epu2apu_mb_offset; 151b285192aSMauro Carvalho Chehab u32 epu2apu_irq; 152b285192aSMauro Carvalho Chehab u32 apu2epu_irq_ack; 153b285192aSMauro Carvalho Chehab u32 reserved15[13]; 154b285192aSMauro Carvalho Chehab u32 reserved16[8]; 155b285192aSMauro Carvalho Chehab 156b285192aSMauro Carvalho Chehab /* Fields for HPU: */ 157b285192aSMauro Carvalho Chehab 158b285192aSMauro Carvalho Chehab u32 hpu_state; 159b285192aSMauro Carvalho Chehab u32 reserved21[7]; 160b285192aSMauro Carvalho Chehab u32 cpu2hpu_mb_offset; 161b285192aSMauro Carvalho Chehab u32 cpu2hpu_irq; 162b285192aSMauro Carvalho Chehab u32 hpu2cpu_irq_ack; 163b285192aSMauro Carvalho Chehab u32 reserved22[13]; 164b285192aSMauro Carvalho Chehab 165b285192aSMauro Carvalho Chehab u32 apu2hpu_mb_offset; 166b285192aSMauro Carvalho Chehab u32 apu2hpu_irq; 167b285192aSMauro Carvalho Chehab u32 hpu2apu_irq_ack; 168b285192aSMauro Carvalho Chehab u32 reserved23[13]; 169b285192aSMauro Carvalho Chehab 170b285192aSMauro Carvalho Chehab u32 ppu2hpu_mb_offset; 171b285192aSMauro Carvalho Chehab u32 ppu2hpu_irq; 172b285192aSMauro Carvalho Chehab u32 hpu2ppu_irq_ack; 173b285192aSMauro Carvalho Chehab u32 reserved24[13]; 174b285192aSMauro Carvalho Chehab 175b285192aSMauro Carvalho Chehab u32 epu2hpu_mb_offset; 176b285192aSMauro Carvalho Chehab u32 epu2hpu_irq; 177b285192aSMauro Carvalho Chehab u32 hpu2epu_irq_ack; 178b285192aSMauro Carvalho Chehab u32 reserved25[13]; 179b285192aSMauro Carvalho Chehab u32 reserved26[8]; 180b285192aSMauro Carvalho Chehab 181b285192aSMauro Carvalho Chehab /* Fields for PPU: */ 182b285192aSMauro Carvalho Chehab 183b285192aSMauro Carvalho Chehab u32 ppu_state; 184b285192aSMauro Carvalho Chehab u32 reserved31[7]; 185b285192aSMauro Carvalho Chehab u32 cpu2ppu_mb_offset; 186b285192aSMauro Carvalho Chehab u32 cpu2ppu_irq; 187b285192aSMauro Carvalho Chehab u32 ppu2cpu_irq_ack; 188b285192aSMauro Carvalho Chehab u32 reserved32[13]; 189b285192aSMauro Carvalho Chehab 190b285192aSMauro Carvalho Chehab u32 apu2ppu_mb_offset; 191b285192aSMauro Carvalho Chehab u32 apu2ppu_irq; 192b285192aSMauro Carvalho Chehab u32 ppu2apu_irq_ack; 193b285192aSMauro Carvalho Chehab u32 reserved33[13]; 194b285192aSMauro Carvalho Chehab 195b285192aSMauro Carvalho Chehab u32 hpu2ppu_mb_offset; 196b285192aSMauro Carvalho Chehab u32 hpu2ppu_irq; 197b285192aSMauro Carvalho Chehab u32 ppu2hpu_irq_ack; 198b285192aSMauro Carvalho Chehab u32 reserved34[13]; 199b285192aSMauro Carvalho Chehab 200b285192aSMauro Carvalho Chehab u32 epu2ppu_mb_offset; 201b285192aSMauro Carvalho Chehab u32 epu2ppu_irq; 202b285192aSMauro Carvalho Chehab u32 ppu2epu_irq_ack; 203b285192aSMauro Carvalho Chehab u32 reserved35[13]; 204b285192aSMauro Carvalho Chehab u32 reserved36[8]; 205b285192aSMauro Carvalho Chehab 206b285192aSMauro Carvalho Chehab /* Fields for EPU: */ 207b285192aSMauro Carvalho Chehab 208b285192aSMauro Carvalho Chehab u32 epu_state; 209b285192aSMauro Carvalho Chehab u32 reserved41[7]; 210b285192aSMauro Carvalho Chehab u32 cpu2epu_mb_offset; 211b285192aSMauro Carvalho Chehab u32 cpu2epu_irq; 212b285192aSMauro Carvalho Chehab u32 epu2cpu_irq_ack; 213b285192aSMauro Carvalho Chehab u32 reserved42[13]; 214b285192aSMauro Carvalho Chehab 215b285192aSMauro Carvalho Chehab u32 apu2epu_mb_offset; 216b285192aSMauro Carvalho Chehab u32 apu2epu_irq; 217b285192aSMauro Carvalho Chehab u32 epu2apu_irq_ack; 218b285192aSMauro Carvalho Chehab u32 reserved43[13]; 219b285192aSMauro Carvalho Chehab 220b285192aSMauro Carvalho Chehab u32 hpu2epu_mb_offset; 221b285192aSMauro Carvalho Chehab u32 hpu2epu_irq; 222b285192aSMauro Carvalho Chehab u32 epu2hpu_irq_ack; 223b285192aSMauro Carvalho Chehab u32 reserved44[13]; 224b285192aSMauro Carvalho Chehab 225b285192aSMauro Carvalho Chehab u32 ppu2epu_mb_offset; 226b285192aSMauro Carvalho Chehab u32 ppu2epu_irq; 227b285192aSMauro Carvalho Chehab u32 epu2ppu_irq_ack; 228b285192aSMauro Carvalho Chehab u32 reserved45[13]; 229b285192aSMauro Carvalho Chehab u32 reserved46[8]; 230b285192aSMauro Carvalho Chehab 231b285192aSMauro Carvalho Chehab u32 semaphores[8]; /* Semaphores */ 232b285192aSMauro Carvalho Chehab 233b285192aSMauro Carvalho Chehab u32 reserved50[32]; /* Reserved for future use */ 234b285192aSMauro Carvalho Chehab 235b285192aSMauro Carvalho Chehab struct cx18_mailbox apu2cpu_mb; 236b285192aSMauro Carvalho Chehab struct cx18_mailbox hpu2cpu_mb; 237b285192aSMauro Carvalho Chehab struct cx18_mailbox ppu2cpu_mb; 238b285192aSMauro Carvalho Chehab struct cx18_mailbox epu2cpu_mb; 239b285192aSMauro Carvalho Chehab 240b285192aSMauro Carvalho Chehab struct cx18_mailbox cpu2apu_mb; 241b285192aSMauro Carvalho Chehab struct cx18_mailbox hpu2apu_mb; 242b285192aSMauro Carvalho Chehab struct cx18_mailbox ppu2apu_mb; 243b285192aSMauro Carvalho Chehab struct cx18_mailbox epu2apu_mb; 244b285192aSMauro Carvalho Chehab 245b285192aSMauro Carvalho Chehab struct cx18_mailbox cpu2hpu_mb; 246b285192aSMauro Carvalho Chehab struct cx18_mailbox apu2hpu_mb; 247b285192aSMauro Carvalho Chehab struct cx18_mailbox ppu2hpu_mb; 248b285192aSMauro Carvalho Chehab struct cx18_mailbox epu2hpu_mb; 249b285192aSMauro Carvalho Chehab 250b285192aSMauro Carvalho Chehab struct cx18_mailbox cpu2ppu_mb; 251b285192aSMauro Carvalho Chehab struct cx18_mailbox apu2ppu_mb; 252b285192aSMauro Carvalho Chehab struct cx18_mailbox hpu2ppu_mb; 253b285192aSMauro Carvalho Chehab struct cx18_mailbox epu2ppu_mb; 254b285192aSMauro Carvalho Chehab 255b285192aSMauro Carvalho Chehab struct cx18_mailbox cpu2epu_mb; 256b285192aSMauro Carvalho Chehab struct cx18_mailbox apu2epu_mb; 257b285192aSMauro Carvalho Chehab struct cx18_mailbox hpu2epu_mb; 258b285192aSMauro Carvalho Chehab struct cx18_mailbox ppu2epu_mb; 259b285192aSMauro Carvalho Chehab 260b285192aSMauro Carvalho Chehab struct cx18_mdl_ack cpu_mdl_ack[CX18_MAX_STREAMS][CX18_MAX_MDL_ACKS]; 261b285192aSMauro Carvalho Chehab struct cx18_mdl_ent cpu_mdl[1]; 262b285192aSMauro Carvalho Chehab }; 263b285192aSMauro Carvalho Chehab 264b285192aSMauro Carvalho Chehab void cx18_init_scb(struct cx18 *cx); 265b285192aSMauro Carvalho Chehab 266b285192aSMauro Carvalho Chehab #endif 267