1*6884db3cSHans Verkuil /* SPDX-License-Identifier: GPL-2.0-only */ 285756a06SHans Verkuil /* 385756a06SHans Verkuil * Copyright 2014-2015 Cisco Systems, Inc. and/or its affiliates. 485756a06SHans Verkuil * All rights reserved. 585756a06SHans Verkuil */ 685756a06SHans Verkuil 785756a06SHans Verkuil #ifndef M00389_CVI_MEMMAP_PACKAGE_H 885756a06SHans Verkuil #define M00389_CVI_MEMMAP_PACKAGE_H 985756a06SHans Verkuil 1085756a06SHans Verkuil /******************************************************************* 1185756a06SHans Verkuil * Register Block 1285756a06SHans Verkuil * M00389_CVI_MEMMAP_PACKAGE_VHD_REGMAP 1385756a06SHans Verkuil *******************************************************************/ 1485756a06SHans Verkuil struct m00389_cvi_regmap { 1585756a06SHans Verkuil uint32_t control; /* Reg 0x0000, Default=0x0 */ 1685756a06SHans Verkuil uint32_t frame_width; /* Reg 0x0004, Default=0x10 */ 1785756a06SHans Verkuil uint32_t frame_height; /* Reg 0x0008, Default=0xc */ 1885756a06SHans Verkuil uint32_t freewheel_period; /* Reg 0x000c, Default=0x0 */ 1985756a06SHans Verkuil uint32_t error_color; /* Reg 0x0010, Default=0x0 */ 2085756a06SHans Verkuil uint32_t status; /* Reg 0x0014 */ 2185756a06SHans Verkuil }; 2285756a06SHans Verkuil 2385756a06SHans Verkuil #define M00389_CVI_REG_CONTROL_OFST 0 2485756a06SHans Verkuil #define M00389_CVI_REG_FRAME_WIDTH_OFST 4 2585756a06SHans Verkuil #define M00389_CVI_REG_FRAME_HEIGHT_OFST 8 2685756a06SHans Verkuil #define M00389_CVI_REG_FREEWHEEL_PERIOD_OFST 12 2785756a06SHans Verkuil #define M00389_CVI_REG_ERROR_COLOR_OFST 16 2885756a06SHans Verkuil #define M00389_CVI_REG_STATUS_OFST 20 2985756a06SHans Verkuil 3085756a06SHans Verkuil /******************************************************************* 3185756a06SHans Verkuil * Bit Mask for register 3285756a06SHans Verkuil * M00389_CVI_MEMMAP_PACKAGE_VHD_BITMAP 3385756a06SHans Verkuil *******************************************************************/ 3485756a06SHans Verkuil /* control [2:0] */ 3585756a06SHans Verkuil #define M00389_CONTROL_BITMAP_ENABLE_OFST (0) 3685756a06SHans Verkuil #define M00389_CONTROL_BITMAP_ENABLE_MSK (0x1 << M00389_CONTROL_BITMAP_ENABLE_OFST) 3785756a06SHans Verkuil #define M00389_CONTROL_BITMAP_HSYNC_POLARITY_LOW_OFST (1) 3885756a06SHans Verkuil #define M00389_CONTROL_BITMAP_HSYNC_POLARITY_LOW_MSK (0x1 << M00389_CONTROL_BITMAP_HSYNC_POLARITY_LOW_OFST) 3985756a06SHans Verkuil #define M00389_CONTROL_BITMAP_VSYNC_POLARITY_LOW_OFST (2) 4085756a06SHans Verkuil #define M00389_CONTROL_BITMAP_VSYNC_POLARITY_LOW_MSK (0x1 << M00389_CONTROL_BITMAP_VSYNC_POLARITY_LOW_OFST) 4185756a06SHans Verkuil /* status [1:0] */ 4285756a06SHans Verkuil #define M00389_STATUS_BITMAP_LOCK_OFST (0) 4385756a06SHans Verkuil #define M00389_STATUS_BITMAP_LOCK_MSK (0x1 << M00389_STATUS_BITMAP_LOCK_OFST) 4485756a06SHans Verkuil #define M00389_STATUS_BITMAP_ERROR_OFST (1) 4585756a06SHans Verkuil #define M00389_STATUS_BITMAP_ERROR_MSK (0x1 << M00389_STATUS_BITMAP_ERROR_OFST) 4685756a06SHans Verkuil 4785756a06SHans Verkuil #endif /*M00389_CVI_MEMMAP_PACKAGE_H*/ 48