1 /* 2 * Copyright (c) 2017 Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License version 6 * 2 as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 */ 14 15 #include <linux/acpi.h> 16 #include <linux/i2c.h> 17 #include <linux/module.h> 18 #include <linux/pm_runtime.h> 19 #include <media/v4l2-ctrls.h> 20 #include <media/v4l2-device.h> 21 22 #define OV13858_REG_VALUE_08BIT 1 23 #define OV13858_REG_VALUE_16BIT 2 24 #define OV13858_REG_VALUE_24BIT 3 25 26 #define OV13858_REG_MODE_SELECT 0x0100 27 #define OV13858_MODE_STANDBY 0x00 28 #define OV13858_MODE_STREAMING 0x01 29 30 #define OV13858_REG_SOFTWARE_RST 0x0103 31 #define OV13858_SOFTWARE_RST 0x01 32 33 /* PLL1 generates PCLK and MIPI_PHY_CLK */ 34 #define OV13858_REG_PLL1_CTRL_0 0x0300 35 #define OV13858_REG_PLL1_CTRL_1 0x0301 36 #define OV13858_REG_PLL1_CTRL_2 0x0302 37 #define OV13858_REG_PLL1_CTRL_3 0x0303 38 #define OV13858_REG_PLL1_CTRL_4 0x0304 39 #define OV13858_REG_PLL1_CTRL_5 0x0305 40 41 /* PLL2 generates DAC_CLK, SCLK and SRAM_CLK */ 42 #define OV13858_REG_PLL2_CTRL_B 0x030b 43 #define OV13858_REG_PLL2_CTRL_C 0x030c 44 #define OV13858_REG_PLL2_CTRL_D 0x030d 45 #define OV13858_REG_PLL2_CTRL_E 0x030e 46 #define OV13858_REG_PLL2_CTRL_F 0x030f 47 #define OV13858_REG_PLL2_CTRL_12 0x0312 48 #define OV13858_REG_MIPI_SC_CTRL0 0x3016 49 #define OV13858_REG_MIPI_SC_CTRL1 0x3022 50 51 /* Chip ID */ 52 #define OV13858_REG_CHIP_ID 0x300a 53 #define OV13858_CHIP_ID 0x00d855 54 55 /* V_TIMING internal */ 56 #define OV13858_REG_VTS 0x380e 57 #define OV13858_VTS_30FPS 0x0c8e /* 30 fps */ 58 #define OV13858_VTS_60FPS 0x0648 /* 60 fps */ 59 #define OV13858_VTS_MAX 0x7fff 60 61 /* HBLANK control - read only */ 62 #define OV13858_PPL_270MHZ 2244 63 #define OV13858_PPL_540MHZ 4488 64 65 /* Exposure control */ 66 #define OV13858_REG_EXPOSURE 0x3500 67 #define OV13858_EXPOSURE_MIN 4 68 #define OV13858_EXPOSURE_STEP 1 69 #define OV13858_EXPOSURE_DEFAULT 0x640 70 71 /* Analog gain control */ 72 #define OV13858_REG_ANALOG_GAIN 0x3508 73 #define OV13858_ANA_GAIN_MIN 0 74 #define OV13858_ANA_GAIN_MAX 0x1fff 75 #define OV13858_ANA_GAIN_STEP 1 76 #define OV13858_ANA_GAIN_DEFAULT 0x80 77 78 /* Digital gain control */ 79 #define OV13858_REG_B_MWB_GAIN 0x5100 80 #define OV13858_REG_G_MWB_GAIN 0x5102 81 #define OV13858_REG_R_MWB_GAIN 0x5104 82 #define OV13858_DGTL_GAIN_MIN 0 83 #define OV13858_DGTL_GAIN_MAX 16384 /* Max = 16 X */ 84 #define OV13858_DGTL_GAIN_DEFAULT 1024 /* Default gain = 1 X */ 85 #define OV13858_DGTL_GAIN_STEP 1 /* Each step = 1/1024 */ 86 87 /* Test Pattern Control */ 88 #define OV13858_REG_TEST_PATTERN 0x4503 89 #define OV13858_TEST_PATTERN_ENABLE BIT(7) 90 #define OV13858_TEST_PATTERN_MASK 0xfc 91 92 /* Number of frames to skip */ 93 #define OV13858_NUM_OF_SKIP_FRAMES 2 94 95 struct ov13858_reg { 96 u16 address; 97 u8 val; 98 }; 99 100 struct ov13858_reg_list { 101 u32 num_of_regs; 102 const struct ov13858_reg *regs; 103 }; 104 105 /* Link frequency config */ 106 struct ov13858_link_freq_config { 107 u32 pixels_per_line; 108 109 /* PLL registers for this link frequency */ 110 struct ov13858_reg_list reg_list; 111 }; 112 113 /* Mode : resolution and related config&values */ 114 struct ov13858_mode { 115 /* Frame width */ 116 u32 width; 117 /* Frame height */ 118 u32 height; 119 120 /* V-timing */ 121 u32 vts_def; 122 u32 vts_min; 123 124 /* Index of Link frequency config to be used */ 125 u32 link_freq_index; 126 /* Default register values */ 127 struct ov13858_reg_list reg_list; 128 }; 129 130 /* 4224x3136 needs 1080Mbps/lane, 4 lanes */ 131 static const struct ov13858_reg mipi_data_rate_1080mbps[] = { 132 /* PLL1 registers */ 133 {OV13858_REG_PLL1_CTRL_0, 0x07}, 134 {OV13858_REG_PLL1_CTRL_1, 0x01}, 135 {OV13858_REG_PLL1_CTRL_2, 0xc2}, 136 {OV13858_REG_PLL1_CTRL_3, 0x00}, 137 {OV13858_REG_PLL1_CTRL_4, 0x00}, 138 {OV13858_REG_PLL1_CTRL_5, 0x01}, 139 140 /* PLL2 registers */ 141 {OV13858_REG_PLL2_CTRL_B, 0x05}, 142 {OV13858_REG_PLL2_CTRL_C, 0x01}, 143 {OV13858_REG_PLL2_CTRL_D, 0x0e}, 144 {OV13858_REG_PLL2_CTRL_E, 0x05}, 145 {OV13858_REG_PLL2_CTRL_F, 0x01}, 146 {OV13858_REG_PLL2_CTRL_12, 0x01}, 147 {OV13858_REG_MIPI_SC_CTRL0, 0x72}, 148 {OV13858_REG_MIPI_SC_CTRL1, 0x01}, 149 }; 150 151 /* 152 * 2112x1568, 2112x1188, 1056x784 need 540Mbps/lane, 153 * 4 lanes 154 */ 155 static const struct ov13858_reg mipi_data_rate_540mbps[] = { 156 /* PLL1 registers */ 157 {OV13858_REG_PLL1_CTRL_0, 0x07}, 158 {OV13858_REG_PLL1_CTRL_1, 0x01}, 159 {OV13858_REG_PLL1_CTRL_2, 0xc2}, 160 {OV13858_REG_PLL1_CTRL_3, 0x01}, 161 {OV13858_REG_PLL1_CTRL_4, 0x00}, 162 {OV13858_REG_PLL1_CTRL_5, 0x01}, 163 164 /* PLL2 registers */ 165 {OV13858_REG_PLL2_CTRL_B, 0x05}, 166 {OV13858_REG_PLL2_CTRL_C, 0x01}, 167 {OV13858_REG_PLL2_CTRL_D, 0x0e}, 168 {OV13858_REG_PLL2_CTRL_E, 0x05}, 169 {OV13858_REG_PLL2_CTRL_F, 0x01}, 170 {OV13858_REG_PLL2_CTRL_12, 0x01}, 171 {OV13858_REG_MIPI_SC_CTRL0, 0x72}, 172 {OV13858_REG_MIPI_SC_CTRL1, 0x01}, 173 }; 174 175 static const struct ov13858_reg mode_4224x3136_regs[] = { 176 {0x3013, 0x32}, 177 {0x301b, 0xf0}, 178 {0x301f, 0xd0}, 179 {0x3106, 0x15}, 180 {0x3107, 0x23}, 181 {0x350a, 0x00}, 182 {0x350e, 0x00}, 183 {0x3510, 0x00}, 184 {0x3511, 0x02}, 185 {0x3512, 0x00}, 186 {0x3600, 0x2b}, 187 {0x3601, 0x52}, 188 {0x3602, 0x60}, 189 {0x3612, 0x05}, 190 {0x3613, 0xa4}, 191 {0x3620, 0x80}, 192 {0x3621, 0x10}, 193 {0x3622, 0x30}, 194 {0x3624, 0x1c}, 195 {0x3640, 0x10}, 196 {0x3641, 0x70}, 197 {0x3661, 0x80}, 198 {0x3662, 0x12}, 199 {0x3664, 0x73}, 200 {0x3665, 0xa7}, 201 {0x366e, 0xff}, 202 {0x366f, 0xf4}, 203 {0x3674, 0x00}, 204 {0x3679, 0x0c}, 205 {0x367f, 0x01}, 206 {0x3680, 0x0c}, 207 {0x3681, 0x50}, 208 {0x3682, 0x50}, 209 {0x3683, 0xa9}, 210 {0x3684, 0xa9}, 211 {0x3709, 0x5f}, 212 {0x3714, 0x24}, 213 {0x371a, 0x3e}, 214 {0x3737, 0x04}, 215 {0x3738, 0xcc}, 216 {0x3739, 0x12}, 217 {0x373d, 0x26}, 218 {0x3764, 0x20}, 219 {0x3765, 0x20}, 220 {0x37a1, 0x36}, 221 {0x37a8, 0x3b}, 222 {0x37ab, 0x31}, 223 {0x37c2, 0x04}, 224 {0x37c3, 0xf1}, 225 {0x37c5, 0x00}, 226 {0x37d8, 0x03}, 227 {0x37d9, 0x0c}, 228 {0x37da, 0xc2}, 229 {0x37dc, 0x02}, 230 {0x37e0, 0x00}, 231 {0x37e1, 0x0a}, 232 {0x37e2, 0x14}, 233 {0x37e3, 0x04}, 234 {0x37e4, 0x2a}, 235 {0x37e5, 0x03}, 236 {0x37e6, 0x04}, 237 {0x3800, 0x00}, 238 {0x3801, 0x00}, 239 {0x3802, 0x00}, 240 {0x3803, 0x00}, 241 {0x3804, 0x10}, 242 {0x3805, 0x9f}, 243 {0x3806, 0x0c}, 244 {0x3807, 0x5f}, 245 {0x3808, 0x10}, 246 {0x3809, 0x80}, 247 {0x380a, 0x0c}, 248 {0x380b, 0x40}, 249 {0x380c, 0x04}, 250 {0x380d, 0x62}, 251 {0x380e, 0x0c}, 252 {0x380f, 0x8e}, 253 {0x3811, 0x04}, 254 {0x3813, 0x05}, 255 {0x3814, 0x01}, 256 {0x3815, 0x01}, 257 {0x3816, 0x01}, 258 {0x3817, 0x01}, 259 {0x3820, 0xa8}, 260 {0x3821, 0x00}, 261 {0x3822, 0xc2}, 262 {0x3823, 0x18}, 263 {0x3826, 0x11}, 264 {0x3827, 0x1c}, 265 {0x3829, 0x03}, 266 {0x3832, 0x00}, 267 {0x3c80, 0x00}, 268 {0x3c87, 0x01}, 269 {0x3c8c, 0x19}, 270 {0x3c8d, 0x1c}, 271 {0x3c90, 0x00}, 272 {0x3c91, 0x00}, 273 {0x3c92, 0x00}, 274 {0x3c93, 0x00}, 275 {0x3c94, 0x40}, 276 {0x3c95, 0x54}, 277 {0x3c96, 0x34}, 278 {0x3c97, 0x04}, 279 {0x3c98, 0x00}, 280 {0x3d8c, 0x73}, 281 {0x3d8d, 0xc0}, 282 {0x3f00, 0x0b}, 283 {0x3f03, 0x00}, 284 {0x4001, 0xe0}, 285 {0x4008, 0x00}, 286 {0x4009, 0x0f}, 287 {0x4011, 0xf0}, 288 {0x4017, 0x08}, 289 {0x4050, 0x04}, 290 {0x4051, 0x0b}, 291 {0x4052, 0x00}, 292 {0x4053, 0x80}, 293 {0x4054, 0x00}, 294 {0x4055, 0x80}, 295 {0x4056, 0x00}, 296 {0x4057, 0x80}, 297 {0x4058, 0x00}, 298 {0x4059, 0x80}, 299 {0x405e, 0x20}, 300 {0x4500, 0x07}, 301 {0x4503, 0x00}, 302 {0x450a, 0x04}, 303 {0x4809, 0x04}, 304 {0x480c, 0x12}, 305 {0x481f, 0x30}, 306 {0x4833, 0x10}, 307 {0x4837, 0x0e}, 308 {0x4902, 0x01}, 309 {0x4d00, 0x03}, 310 {0x4d01, 0xc9}, 311 {0x4d02, 0xbc}, 312 {0x4d03, 0xd7}, 313 {0x4d04, 0xf0}, 314 {0x4d05, 0xa2}, 315 {0x5000, 0xfd}, 316 {0x5001, 0x01}, 317 {0x5040, 0x39}, 318 {0x5041, 0x10}, 319 {0x5042, 0x10}, 320 {0x5043, 0x84}, 321 {0x5044, 0x62}, 322 {0x5180, 0x00}, 323 {0x5181, 0x10}, 324 {0x5182, 0x02}, 325 {0x5183, 0x0f}, 326 {0x5200, 0x1b}, 327 {0x520b, 0x07}, 328 {0x520c, 0x0f}, 329 {0x5300, 0x04}, 330 {0x5301, 0x0c}, 331 {0x5302, 0x0c}, 332 {0x5303, 0x0f}, 333 {0x5304, 0x00}, 334 {0x5305, 0x70}, 335 {0x5306, 0x00}, 336 {0x5307, 0x80}, 337 {0x5308, 0x00}, 338 {0x5309, 0xa5}, 339 {0x530a, 0x00}, 340 {0x530b, 0xd3}, 341 {0x530c, 0x00}, 342 {0x530d, 0xf0}, 343 {0x530e, 0x01}, 344 {0x530f, 0x10}, 345 {0x5310, 0x01}, 346 {0x5311, 0x20}, 347 {0x5312, 0x01}, 348 {0x5313, 0x20}, 349 {0x5314, 0x01}, 350 {0x5315, 0x20}, 351 {0x5316, 0x08}, 352 {0x5317, 0x08}, 353 {0x5318, 0x10}, 354 {0x5319, 0x88}, 355 {0x531a, 0x88}, 356 {0x531b, 0xa9}, 357 {0x531c, 0xaa}, 358 {0x531d, 0x0a}, 359 {0x5405, 0x02}, 360 {0x5406, 0x67}, 361 {0x5407, 0x01}, 362 {0x5408, 0x4a}, 363 }; 364 365 static const struct ov13858_reg mode_2112x1568_regs[] = { 366 {0x3013, 0x32}, 367 {0x301b, 0xf0}, 368 {0x301f, 0xd0}, 369 {0x3106, 0x15}, 370 {0x3107, 0x23}, 371 {0x350a, 0x00}, 372 {0x350e, 0x00}, 373 {0x3510, 0x00}, 374 {0x3511, 0x02}, 375 {0x3512, 0x00}, 376 {0x3600, 0x2b}, 377 {0x3601, 0x52}, 378 {0x3602, 0x60}, 379 {0x3612, 0x05}, 380 {0x3613, 0xa4}, 381 {0x3620, 0x80}, 382 {0x3621, 0x10}, 383 {0x3622, 0x30}, 384 {0x3624, 0x1c}, 385 {0x3640, 0x10}, 386 {0x3641, 0x70}, 387 {0x3661, 0x80}, 388 {0x3662, 0x10}, 389 {0x3664, 0x73}, 390 {0x3665, 0xa7}, 391 {0x366e, 0xff}, 392 {0x366f, 0xf4}, 393 {0x3674, 0x00}, 394 {0x3679, 0x0c}, 395 {0x367f, 0x01}, 396 {0x3680, 0x0c}, 397 {0x3681, 0x50}, 398 {0x3682, 0x50}, 399 {0x3683, 0xa9}, 400 {0x3684, 0xa9}, 401 {0x3709, 0x5f}, 402 {0x3714, 0x28}, 403 {0x371a, 0x3e}, 404 {0x3737, 0x08}, 405 {0x3738, 0xcc}, 406 {0x3739, 0x20}, 407 {0x373d, 0x26}, 408 {0x3764, 0x20}, 409 {0x3765, 0x20}, 410 {0x37a1, 0x36}, 411 {0x37a8, 0x3b}, 412 {0x37ab, 0x31}, 413 {0x37c2, 0x14}, 414 {0x37c3, 0xf1}, 415 {0x37c5, 0x00}, 416 {0x37d8, 0x03}, 417 {0x37d9, 0x0c}, 418 {0x37da, 0xc2}, 419 {0x37dc, 0x02}, 420 {0x37e0, 0x00}, 421 {0x37e1, 0x0a}, 422 {0x37e2, 0x14}, 423 {0x37e3, 0x08}, 424 {0x37e4, 0x38}, 425 {0x37e5, 0x03}, 426 {0x37e6, 0x08}, 427 {0x3800, 0x00}, 428 {0x3801, 0x00}, 429 {0x3802, 0x00}, 430 {0x3803, 0x00}, 431 {0x3804, 0x10}, 432 {0x3805, 0x9f}, 433 {0x3806, 0x0c}, 434 {0x3807, 0x5f}, 435 {0x3808, 0x08}, 436 {0x3809, 0x40}, 437 {0x380a, 0x06}, 438 {0x380b, 0x20}, 439 {0x380c, 0x04}, 440 {0x380d, 0x62}, 441 {0x380e, 0x0c}, 442 {0x380f, 0x8e}, 443 {0x3811, 0x04}, 444 {0x3813, 0x05}, 445 {0x3814, 0x03}, 446 {0x3815, 0x01}, 447 {0x3816, 0x03}, 448 {0x3817, 0x01}, 449 {0x3820, 0xab}, 450 {0x3821, 0x00}, 451 {0x3822, 0xc2}, 452 {0x3823, 0x18}, 453 {0x3826, 0x04}, 454 {0x3827, 0x90}, 455 {0x3829, 0x07}, 456 {0x3832, 0x00}, 457 {0x3c80, 0x00}, 458 {0x3c87, 0x01}, 459 {0x3c8c, 0x19}, 460 {0x3c8d, 0x1c}, 461 {0x3c90, 0x00}, 462 {0x3c91, 0x00}, 463 {0x3c92, 0x00}, 464 {0x3c93, 0x00}, 465 {0x3c94, 0x40}, 466 {0x3c95, 0x54}, 467 {0x3c96, 0x34}, 468 {0x3c97, 0x04}, 469 {0x3c98, 0x00}, 470 {0x3d8c, 0x73}, 471 {0x3d8d, 0xc0}, 472 {0x3f00, 0x0b}, 473 {0x3f03, 0x00}, 474 {0x4001, 0xe0}, 475 {0x4008, 0x00}, 476 {0x4009, 0x0d}, 477 {0x4011, 0xf0}, 478 {0x4017, 0x08}, 479 {0x4050, 0x04}, 480 {0x4051, 0x0b}, 481 {0x4052, 0x00}, 482 {0x4053, 0x80}, 483 {0x4054, 0x00}, 484 {0x4055, 0x80}, 485 {0x4056, 0x00}, 486 {0x4057, 0x80}, 487 {0x4058, 0x00}, 488 {0x4059, 0x80}, 489 {0x405e, 0x20}, 490 {0x4500, 0x07}, 491 {0x4503, 0x00}, 492 {0x450a, 0x04}, 493 {0x4809, 0x04}, 494 {0x480c, 0x12}, 495 {0x481f, 0x30}, 496 {0x4833, 0x10}, 497 {0x4837, 0x1c}, 498 {0x4902, 0x01}, 499 {0x4d00, 0x03}, 500 {0x4d01, 0xc9}, 501 {0x4d02, 0xbc}, 502 {0x4d03, 0xd7}, 503 {0x4d04, 0xf0}, 504 {0x4d05, 0xa2}, 505 {0x5000, 0xfd}, 506 {0x5001, 0x01}, 507 {0x5040, 0x39}, 508 {0x5041, 0x10}, 509 {0x5042, 0x10}, 510 {0x5043, 0x84}, 511 {0x5044, 0x62}, 512 {0x5180, 0x00}, 513 {0x5181, 0x10}, 514 {0x5182, 0x02}, 515 {0x5183, 0x0f}, 516 {0x5200, 0x1b}, 517 {0x520b, 0x07}, 518 {0x520c, 0x0f}, 519 {0x5300, 0x04}, 520 {0x5301, 0x0c}, 521 {0x5302, 0x0c}, 522 {0x5303, 0x0f}, 523 {0x5304, 0x00}, 524 {0x5305, 0x70}, 525 {0x5306, 0x00}, 526 {0x5307, 0x80}, 527 {0x5308, 0x00}, 528 {0x5309, 0xa5}, 529 {0x530a, 0x00}, 530 {0x530b, 0xd3}, 531 {0x530c, 0x00}, 532 {0x530d, 0xf0}, 533 {0x530e, 0x01}, 534 {0x530f, 0x10}, 535 {0x5310, 0x01}, 536 {0x5311, 0x20}, 537 {0x5312, 0x01}, 538 {0x5313, 0x20}, 539 {0x5314, 0x01}, 540 {0x5315, 0x20}, 541 {0x5316, 0x08}, 542 {0x5317, 0x08}, 543 {0x5318, 0x10}, 544 {0x5319, 0x88}, 545 {0x531a, 0x88}, 546 {0x531b, 0xa9}, 547 {0x531c, 0xaa}, 548 {0x531d, 0x0a}, 549 {0x5405, 0x02}, 550 {0x5406, 0x67}, 551 {0x5407, 0x01}, 552 {0x5408, 0x4a}, 553 }; 554 555 static const struct ov13858_reg mode_2112x1188_regs[] = { 556 {0x3013, 0x32}, 557 {0x301b, 0xf0}, 558 {0x301f, 0xd0}, 559 {0x3106, 0x15}, 560 {0x3107, 0x23}, 561 {0x350a, 0x00}, 562 {0x350e, 0x00}, 563 {0x3510, 0x00}, 564 {0x3511, 0x02}, 565 {0x3512, 0x00}, 566 {0x3600, 0x2b}, 567 {0x3601, 0x52}, 568 {0x3602, 0x60}, 569 {0x3612, 0x05}, 570 {0x3613, 0xa4}, 571 {0x3620, 0x80}, 572 {0x3621, 0x10}, 573 {0x3622, 0x30}, 574 {0x3624, 0x1c}, 575 {0x3640, 0x10}, 576 {0x3641, 0x70}, 577 {0x3661, 0x80}, 578 {0x3662, 0x10}, 579 {0x3664, 0x73}, 580 {0x3665, 0xa7}, 581 {0x366e, 0xff}, 582 {0x366f, 0xf4}, 583 {0x3674, 0x00}, 584 {0x3679, 0x0c}, 585 {0x367f, 0x01}, 586 {0x3680, 0x0c}, 587 {0x3681, 0x50}, 588 {0x3682, 0x50}, 589 {0x3683, 0xa9}, 590 {0x3684, 0xa9}, 591 {0x3709, 0x5f}, 592 {0x3714, 0x28}, 593 {0x371a, 0x3e}, 594 {0x3737, 0x08}, 595 {0x3738, 0xcc}, 596 {0x3739, 0x20}, 597 {0x373d, 0x26}, 598 {0x3764, 0x20}, 599 {0x3765, 0x20}, 600 {0x37a1, 0x36}, 601 {0x37a8, 0x3b}, 602 {0x37ab, 0x31}, 603 {0x37c2, 0x14}, 604 {0x37c3, 0xf1}, 605 {0x37c5, 0x00}, 606 {0x37d8, 0x03}, 607 {0x37d9, 0x0c}, 608 {0x37da, 0xc2}, 609 {0x37dc, 0x02}, 610 {0x37e0, 0x00}, 611 {0x37e1, 0x0a}, 612 {0x37e2, 0x14}, 613 {0x37e3, 0x08}, 614 {0x37e4, 0x38}, 615 {0x37e5, 0x03}, 616 {0x37e6, 0x08}, 617 {0x3800, 0x00}, 618 {0x3801, 0x00}, 619 {0x3802, 0x01}, 620 {0x3803, 0x84}, 621 {0x3804, 0x10}, 622 {0x3805, 0x9f}, 623 {0x3806, 0x0a}, 624 {0x3807, 0xd3}, 625 {0x3808, 0x08}, 626 {0x3809, 0x40}, 627 {0x380a, 0x04}, 628 {0x380b, 0xa4}, 629 {0x380c, 0x04}, 630 {0x380d, 0x62}, 631 {0x380e, 0x0c}, 632 {0x380f, 0x8e}, 633 {0x3811, 0x08}, 634 {0x3813, 0x03}, 635 {0x3814, 0x03}, 636 {0x3815, 0x01}, 637 {0x3816, 0x03}, 638 {0x3817, 0x01}, 639 {0x3820, 0xab}, 640 {0x3821, 0x00}, 641 {0x3822, 0xc2}, 642 {0x3823, 0x18}, 643 {0x3826, 0x04}, 644 {0x3827, 0x90}, 645 {0x3829, 0x07}, 646 {0x3832, 0x00}, 647 {0x3c80, 0x00}, 648 {0x3c87, 0x01}, 649 {0x3c8c, 0x19}, 650 {0x3c8d, 0x1c}, 651 {0x3c90, 0x00}, 652 {0x3c91, 0x00}, 653 {0x3c92, 0x00}, 654 {0x3c93, 0x00}, 655 {0x3c94, 0x40}, 656 {0x3c95, 0x54}, 657 {0x3c96, 0x34}, 658 {0x3c97, 0x04}, 659 {0x3c98, 0x00}, 660 {0x3d8c, 0x73}, 661 {0x3d8d, 0xc0}, 662 {0x3f00, 0x0b}, 663 {0x3f03, 0x00}, 664 {0x4001, 0xe0}, 665 {0x4008, 0x00}, 666 {0x4009, 0x0d}, 667 {0x4011, 0xf0}, 668 {0x4017, 0x08}, 669 {0x4050, 0x04}, 670 {0x4051, 0x0b}, 671 {0x4052, 0x00}, 672 {0x4053, 0x80}, 673 {0x4054, 0x00}, 674 {0x4055, 0x80}, 675 {0x4056, 0x00}, 676 {0x4057, 0x80}, 677 {0x4058, 0x00}, 678 {0x4059, 0x80}, 679 {0x405e, 0x20}, 680 {0x4500, 0x07}, 681 {0x4503, 0x00}, 682 {0x450a, 0x04}, 683 {0x4809, 0x04}, 684 {0x480c, 0x12}, 685 {0x481f, 0x30}, 686 {0x4833, 0x10}, 687 {0x4837, 0x1c}, 688 {0x4902, 0x01}, 689 {0x4d00, 0x03}, 690 {0x4d01, 0xc9}, 691 {0x4d02, 0xbc}, 692 {0x4d03, 0xd7}, 693 {0x4d04, 0xf0}, 694 {0x4d05, 0xa2}, 695 {0x5000, 0xfd}, 696 {0x5001, 0x01}, 697 {0x5040, 0x39}, 698 {0x5041, 0x10}, 699 {0x5042, 0x10}, 700 {0x5043, 0x84}, 701 {0x5044, 0x62}, 702 {0x5180, 0x00}, 703 {0x5181, 0x10}, 704 {0x5182, 0x02}, 705 {0x5183, 0x0f}, 706 {0x5200, 0x1b}, 707 {0x520b, 0x07}, 708 {0x520c, 0x0f}, 709 {0x5300, 0x04}, 710 {0x5301, 0x0c}, 711 {0x5302, 0x0c}, 712 {0x5303, 0x0f}, 713 {0x5304, 0x00}, 714 {0x5305, 0x70}, 715 {0x5306, 0x00}, 716 {0x5307, 0x80}, 717 {0x5308, 0x00}, 718 {0x5309, 0xa5}, 719 {0x530a, 0x00}, 720 {0x530b, 0xd3}, 721 {0x530c, 0x00}, 722 {0x530d, 0xf0}, 723 {0x530e, 0x01}, 724 {0x530f, 0x10}, 725 {0x5310, 0x01}, 726 {0x5311, 0x20}, 727 {0x5312, 0x01}, 728 {0x5313, 0x20}, 729 {0x5314, 0x01}, 730 {0x5315, 0x20}, 731 {0x5316, 0x08}, 732 {0x5317, 0x08}, 733 {0x5318, 0x10}, 734 {0x5319, 0x88}, 735 {0x531a, 0x88}, 736 {0x531b, 0xa9}, 737 {0x531c, 0xaa}, 738 {0x531d, 0x0a}, 739 {0x5405, 0x02}, 740 {0x5406, 0x67}, 741 {0x5407, 0x01}, 742 {0x5408, 0x4a}, 743 }; 744 745 static const struct ov13858_reg mode_1056x784_regs[] = { 746 {0x3013, 0x32}, 747 {0x301b, 0xf0}, 748 {0x301f, 0xd0}, 749 {0x3106, 0x15}, 750 {0x3107, 0x23}, 751 {0x350a, 0x00}, 752 {0x350e, 0x00}, 753 {0x3510, 0x00}, 754 {0x3511, 0x02}, 755 {0x3512, 0x00}, 756 {0x3600, 0x2b}, 757 {0x3601, 0x52}, 758 {0x3602, 0x60}, 759 {0x3612, 0x05}, 760 {0x3613, 0xa4}, 761 {0x3620, 0x80}, 762 {0x3621, 0x10}, 763 {0x3622, 0x30}, 764 {0x3624, 0x1c}, 765 {0x3640, 0x10}, 766 {0x3641, 0x70}, 767 {0x3661, 0x80}, 768 {0x3662, 0x08}, 769 {0x3664, 0x73}, 770 {0x3665, 0xa7}, 771 {0x366e, 0xff}, 772 {0x366f, 0xf4}, 773 {0x3674, 0x00}, 774 {0x3679, 0x0c}, 775 {0x367f, 0x01}, 776 {0x3680, 0x0c}, 777 {0x3681, 0x50}, 778 {0x3682, 0x50}, 779 {0x3683, 0xa9}, 780 {0x3684, 0xa9}, 781 {0x3709, 0x5f}, 782 {0x3714, 0x30}, 783 {0x371a, 0x3e}, 784 {0x3737, 0x08}, 785 {0x3738, 0xcc}, 786 {0x3739, 0x20}, 787 {0x373d, 0x26}, 788 {0x3764, 0x20}, 789 {0x3765, 0x20}, 790 {0x37a1, 0x36}, 791 {0x37a8, 0x3b}, 792 {0x37ab, 0x31}, 793 {0x37c2, 0x2c}, 794 {0x37c3, 0xf1}, 795 {0x37c5, 0x00}, 796 {0x37d8, 0x03}, 797 {0x37d9, 0x06}, 798 {0x37da, 0xc2}, 799 {0x37dc, 0x02}, 800 {0x37e0, 0x00}, 801 {0x37e1, 0x0a}, 802 {0x37e2, 0x14}, 803 {0x37e3, 0x08}, 804 {0x37e4, 0x36}, 805 {0x37e5, 0x03}, 806 {0x37e6, 0x08}, 807 {0x3800, 0x00}, 808 {0x3801, 0x00}, 809 {0x3802, 0x00}, 810 {0x3803, 0x00}, 811 {0x3804, 0x10}, 812 {0x3805, 0x9f}, 813 {0x3806, 0x0c}, 814 {0x3807, 0x5f}, 815 {0x3808, 0x04}, 816 {0x3809, 0x20}, 817 {0x380a, 0x03}, 818 {0x380b, 0x10}, 819 {0x380c, 0x04}, 820 {0x380d, 0x62}, 821 {0x380e, 0x0c}, 822 {0x380f, 0x8e}, 823 {0x3811, 0x04}, 824 {0x3813, 0x05}, 825 {0x3814, 0x07}, 826 {0x3815, 0x01}, 827 {0x3816, 0x07}, 828 {0x3817, 0x01}, 829 {0x3820, 0xac}, 830 {0x3821, 0x00}, 831 {0x3822, 0xc2}, 832 {0x3823, 0x18}, 833 {0x3826, 0x04}, 834 {0x3827, 0x48}, 835 {0x3829, 0x03}, 836 {0x3832, 0x00}, 837 {0x3c80, 0x00}, 838 {0x3c87, 0x01}, 839 {0x3c8c, 0x19}, 840 {0x3c8d, 0x1c}, 841 {0x3c90, 0x00}, 842 {0x3c91, 0x00}, 843 {0x3c92, 0x00}, 844 {0x3c93, 0x00}, 845 {0x3c94, 0x40}, 846 {0x3c95, 0x54}, 847 {0x3c96, 0x34}, 848 {0x3c97, 0x04}, 849 {0x3c98, 0x00}, 850 {0x3d8c, 0x73}, 851 {0x3d8d, 0xc0}, 852 {0x3f00, 0x0b}, 853 {0x3f03, 0x00}, 854 {0x4001, 0xe0}, 855 {0x4008, 0x00}, 856 {0x4009, 0x05}, 857 {0x4011, 0xf0}, 858 {0x4017, 0x08}, 859 {0x4050, 0x02}, 860 {0x4051, 0x05}, 861 {0x4052, 0x00}, 862 {0x4053, 0x80}, 863 {0x4054, 0x00}, 864 {0x4055, 0x80}, 865 {0x4056, 0x00}, 866 {0x4057, 0x80}, 867 {0x4058, 0x00}, 868 {0x4059, 0x80}, 869 {0x405e, 0x20}, 870 {0x4500, 0x07}, 871 {0x4503, 0x00}, 872 {0x450a, 0x04}, 873 {0x4809, 0x04}, 874 {0x480c, 0x12}, 875 {0x481f, 0x30}, 876 {0x4833, 0x10}, 877 {0x4837, 0x1e}, 878 {0x4902, 0x02}, 879 {0x4d00, 0x03}, 880 {0x4d01, 0xc9}, 881 {0x4d02, 0xbc}, 882 {0x4d03, 0xd7}, 883 {0x4d04, 0xf0}, 884 {0x4d05, 0xa2}, 885 {0x5000, 0xfd}, 886 {0x5001, 0x01}, 887 {0x5040, 0x39}, 888 {0x5041, 0x10}, 889 {0x5042, 0x10}, 890 {0x5043, 0x84}, 891 {0x5044, 0x62}, 892 {0x5180, 0x00}, 893 {0x5181, 0x10}, 894 {0x5182, 0x02}, 895 {0x5183, 0x0f}, 896 {0x5200, 0x1b}, 897 {0x520b, 0x07}, 898 {0x520c, 0x0f}, 899 {0x5300, 0x04}, 900 {0x5301, 0x0c}, 901 {0x5302, 0x0c}, 902 {0x5303, 0x0f}, 903 {0x5304, 0x00}, 904 {0x5305, 0x70}, 905 {0x5306, 0x00}, 906 {0x5307, 0x80}, 907 {0x5308, 0x00}, 908 {0x5309, 0xa5}, 909 {0x530a, 0x00}, 910 {0x530b, 0xd3}, 911 {0x530c, 0x00}, 912 {0x530d, 0xf0}, 913 {0x530e, 0x01}, 914 {0x530f, 0x10}, 915 {0x5310, 0x01}, 916 {0x5311, 0x20}, 917 {0x5312, 0x01}, 918 {0x5313, 0x20}, 919 {0x5314, 0x01}, 920 {0x5315, 0x20}, 921 {0x5316, 0x08}, 922 {0x5317, 0x08}, 923 {0x5318, 0x10}, 924 {0x5319, 0x88}, 925 {0x531a, 0x88}, 926 {0x531b, 0xa9}, 927 {0x531c, 0xaa}, 928 {0x531d, 0x0a}, 929 {0x5405, 0x02}, 930 {0x5406, 0x67}, 931 {0x5407, 0x01}, 932 {0x5408, 0x4a}, 933 }; 934 935 static const char * const ov13858_test_pattern_menu[] = { 936 "Disabled", 937 "Vertical Color Bar Type 1", 938 "Vertical Color Bar Type 2", 939 "Vertical Color Bar Type 3", 940 "Vertical Color Bar Type 4" 941 }; 942 943 /* Configurations for supported link frequencies */ 944 #define OV13858_NUM_OF_LINK_FREQS 2 945 #define OV13858_LINK_FREQ_540MHZ 540000000ULL 946 #define OV13858_LINK_FREQ_270MHZ 270000000ULL 947 #define OV13858_LINK_FREQ_INDEX_0 0 948 #define OV13858_LINK_FREQ_INDEX_1 1 949 950 /* 951 * pixel_rate = link_freq * data-rate * nr_of_lanes / bits_per_sample 952 * data rate => double data rate; number of lanes => 4; bits per pixel => 10 953 */ 954 #define LINK_FREQ_TO_PIXEL_RATE(f) (((f) * 2 * 4) / 10) 955 956 /* Menu items for LINK_FREQ V4L2 control */ 957 static const s64 link_freq_menu_items[OV13858_NUM_OF_LINK_FREQS] = { 958 OV13858_LINK_FREQ_540MHZ, 959 OV13858_LINK_FREQ_270MHZ 960 }; 961 962 /* Link frequency configs */ 963 static const struct ov13858_link_freq_config 964 link_freq_configs[OV13858_NUM_OF_LINK_FREQS] = { 965 { 966 .pixels_per_line = OV13858_PPL_540MHZ, 967 .reg_list = { 968 .num_of_regs = ARRAY_SIZE(mipi_data_rate_1080mbps), 969 .regs = mipi_data_rate_1080mbps, 970 } 971 }, 972 { 973 .pixels_per_line = OV13858_PPL_270MHZ, 974 .reg_list = { 975 .num_of_regs = ARRAY_SIZE(mipi_data_rate_540mbps), 976 .regs = mipi_data_rate_540mbps, 977 } 978 } 979 }; 980 981 /* Mode configs */ 982 static const struct ov13858_mode supported_modes[] = { 983 { 984 .width = 4224, 985 .height = 3136, 986 .vts_def = OV13858_VTS_30FPS, 987 .vts_min = OV13858_VTS_30FPS, 988 .reg_list = { 989 .num_of_regs = ARRAY_SIZE(mode_4224x3136_regs), 990 .regs = mode_4224x3136_regs, 991 }, 992 .link_freq_index = OV13858_LINK_FREQ_INDEX_0, 993 }, 994 { 995 .width = 2112, 996 .height = 1568, 997 .vts_def = OV13858_VTS_30FPS, 998 .vts_min = 1608, 999 .reg_list = { 1000 .num_of_regs = ARRAY_SIZE(mode_2112x1568_regs), 1001 .regs = mode_2112x1568_regs, 1002 }, 1003 .link_freq_index = OV13858_LINK_FREQ_INDEX_1, 1004 }, 1005 { 1006 .width = 2112, 1007 .height = 1188, 1008 .vts_def = OV13858_VTS_30FPS, 1009 .vts_min = 1608, 1010 .reg_list = { 1011 .num_of_regs = ARRAY_SIZE(mode_2112x1188_regs), 1012 .regs = mode_2112x1188_regs, 1013 }, 1014 .link_freq_index = OV13858_LINK_FREQ_INDEX_1, 1015 }, 1016 { 1017 .width = 1056, 1018 .height = 784, 1019 .vts_def = OV13858_VTS_30FPS, 1020 .vts_min = 804, 1021 .reg_list = { 1022 .num_of_regs = ARRAY_SIZE(mode_1056x784_regs), 1023 .regs = mode_1056x784_regs, 1024 }, 1025 .link_freq_index = OV13858_LINK_FREQ_INDEX_1, 1026 } 1027 }; 1028 1029 struct ov13858 { 1030 struct v4l2_subdev sd; 1031 struct media_pad pad; 1032 1033 struct v4l2_ctrl_handler ctrl_handler; 1034 /* V4L2 Controls */ 1035 struct v4l2_ctrl *link_freq; 1036 struct v4l2_ctrl *pixel_rate; 1037 struct v4l2_ctrl *vblank; 1038 struct v4l2_ctrl *hblank; 1039 struct v4l2_ctrl *exposure; 1040 1041 /* Current mode */ 1042 const struct ov13858_mode *cur_mode; 1043 1044 /* Mutex for serialized access */ 1045 struct mutex mutex; 1046 1047 /* Streaming on/off */ 1048 bool streaming; 1049 }; 1050 1051 #define to_ov13858(_sd) container_of(_sd, struct ov13858, sd) 1052 1053 /* Read registers up to 4 at a time */ 1054 static int ov13858_read_reg(struct ov13858 *ov13858, u16 reg, u32 len, u32 *val) 1055 { 1056 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd); 1057 struct i2c_msg msgs[2]; 1058 u8 *data_be_p; 1059 int ret; 1060 u32 data_be = 0; 1061 u16 reg_addr_be = cpu_to_be16(reg); 1062 1063 if (len > 4) 1064 return -EINVAL; 1065 1066 data_be_p = (u8 *)&data_be; 1067 /* Write register address */ 1068 msgs[0].addr = client->addr; 1069 msgs[0].flags = 0; 1070 msgs[0].len = 2; 1071 msgs[0].buf = (u8 *)®_addr_be; 1072 1073 /* Read data from register */ 1074 msgs[1].addr = client->addr; 1075 msgs[1].flags = I2C_M_RD; 1076 msgs[1].len = len; 1077 msgs[1].buf = &data_be_p[4 - len]; 1078 1079 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); 1080 if (ret != ARRAY_SIZE(msgs)) 1081 return -EIO; 1082 1083 *val = be32_to_cpu(data_be); 1084 1085 return 0; 1086 } 1087 1088 /* Write registers up to 4 at a time */ 1089 static int ov13858_write_reg(struct ov13858 *ov13858, u16 reg, u32 len, u32 val) 1090 { 1091 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd); 1092 int buf_i, val_i; 1093 u8 buf[6], *val_p; 1094 1095 if (len > 4) 1096 return -EINVAL; 1097 1098 buf[0] = reg >> 8; 1099 buf[1] = reg & 0xff; 1100 1101 val = cpu_to_be32(val); 1102 val_p = (u8 *)&val; 1103 buf_i = 2; 1104 val_i = 4 - len; 1105 1106 while (val_i < 4) 1107 buf[buf_i++] = val_p[val_i++]; 1108 1109 if (i2c_master_send(client, buf, len + 2) != len + 2) 1110 return -EIO; 1111 1112 return 0; 1113 } 1114 1115 /* Write a list of registers */ 1116 static int ov13858_write_regs(struct ov13858 *ov13858, 1117 const struct ov13858_reg *regs, u32 len) 1118 { 1119 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd); 1120 int ret; 1121 u32 i; 1122 1123 for (i = 0; i < len; i++) { 1124 ret = ov13858_write_reg(ov13858, regs[i].address, 1, 1125 regs[i].val); 1126 if (ret) { 1127 dev_err_ratelimited( 1128 &client->dev, 1129 "Failed to write reg 0x%4.4x. error = %d\n", 1130 regs[i].address, ret); 1131 1132 return ret; 1133 } 1134 } 1135 1136 return 0; 1137 } 1138 1139 static int ov13858_write_reg_list(struct ov13858 *ov13858, 1140 const struct ov13858_reg_list *r_list) 1141 { 1142 return ov13858_write_regs(ov13858, r_list->regs, r_list->num_of_regs); 1143 } 1144 1145 /* Open sub-device */ 1146 static int ov13858_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) 1147 { 1148 struct ov13858 *ov13858 = to_ov13858(sd); 1149 struct v4l2_mbus_framefmt *try_fmt = v4l2_subdev_get_try_format(sd, 1150 fh->pad, 1151 0); 1152 1153 mutex_lock(&ov13858->mutex); 1154 1155 /* Initialize try_fmt */ 1156 try_fmt->width = ov13858->cur_mode->width; 1157 try_fmt->height = ov13858->cur_mode->height; 1158 try_fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10; 1159 try_fmt->field = V4L2_FIELD_NONE; 1160 1161 /* No crop or compose */ 1162 mutex_unlock(&ov13858->mutex); 1163 1164 return 0; 1165 } 1166 1167 static int ov13858_update_digital_gain(struct ov13858 *ov13858, u32 d_gain) 1168 { 1169 int ret; 1170 1171 ret = ov13858_write_reg(ov13858, OV13858_REG_B_MWB_GAIN, 1172 OV13858_REG_VALUE_16BIT, d_gain); 1173 if (ret) 1174 return ret; 1175 1176 ret = ov13858_write_reg(ov13858, OV13858_REG_G_MWB_GAIN, 1177 OV13858_REG_VALUE_16BIT, d_gain); 1178 if (ret) 1179 return ret; 1180 1181 ret = ov13858_write_reg(ov13858, OV13858_REG_R_MWB_GAIN, 1182 OV13858_REG_VALUE_16BIT, d_gain); 1183 1184 return ret; 1185 } 1186 1187 static int ov13858_enable_test_pattern(struct ov13858 *ov13858, u32 pattern) 1188 { 1189 int ret; 1190 u32 val; 1191 1192 ret = ov13858_read_reg(ov13858, OV13858_REG_TEST_PATTERN, 1193 OV13858_REG_VALUE_08BIT, &val); 1194 if (ret) 1195 return ret; 1196 1197 if (pattern) { 1198 val &= OV13858_TEST_PATTERN_MASK; 1199 val |= (pattern - 1) | OV13858_TEST_PATTERN_ENABLE; 1200 } else { 1201 val &= ~OV13858_TEST_PATTERN_ENABLE; 1202 } 1203 1204 return ov13858_write_reg(ov13858, OV13858_REG_TEST_PATTERN, 1205 OV13858_REG_VALUE_08BIT, val); 1206 } 1207 1208 static int ov13858_set_ctrl(struct v4l2_ctrl *ctrl) 1209 { 1210 struct ov13858 *ov13858 = container_of(ctrl->handler, 1211 struct ov13858, ctrl_handler); 1212 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd); 1213 s64 max; 1214 int ret; 1215 1216 /* Propagate change of current control to all related controls */ 1217 switch (ctrl->id) { 1218 case V4L2_CID_VBLANK: 1219 /* Update max exposure while meeting expected vblanking */ 1220 max = ov13858->cur_mode->height + ctrl->val - 8; 1221 __v4l2_ctrl_modify_range(ov13858->exposure, 1222 ov13858->exposure->minimum, 1223 max, ov13858->exposure->step, max); 1224 break; 1225 }; 1226 1227 /* 1228 * Applying V4L2 control value only happens 1229 * when power is up for streaming 1230 */ 1231 if (pm_runtime_get_if_in_use(&client->dev) <= 0) 1232 return 0; 1233 1234 ret = 0; 1235 switch (ctrl->id) { 1236 case V4L2_CID_ANALOGUE_GAIN: 1237 ret = ov13858_write_reg(ov13858, OV13858_REG_ANALOG_GAIN, 1238 OV13858_REG_VALUE_16BIT, ctrl->val); 1239 break; 1240 case V4L2_CID_DIGITAL_GAIN: 1241 ret = ov13858_update_digital_gain(ov13858, ctrl->val); 1242 break; 1243 case V4L2_CID_EXPOSURE: 1244 ret = ov13858_write_reg(ov13858, OV13858_REG_EXPOSURE, 1245 OV13858_REG_VALUE_24BIT, 1246 ctrl->val << 4); 1247 break; 1248 case V4L2_CID_VBLANK: 1249 /* Update VTS that meets expected vertical blanking */ 1250 ret = ov13858_write_reg(ov13858, OV13858_REG_VTS, 1251 OV13858_REG_VALUE_16BIT, 1252 ov13858->cur_mode->height 1253 + ctrl->val); 1254 break; 1255 case V4L2_CID_TEST_PATTERN: 1256 ret = ov13858_enable_test_pattern(ov13858, ctrl->val); 1257 break; 1258 default: 1259 dev_info(&client->dev, 1260 "ctrl(id:0x%x,val:0x%x) is not handled\n", 1261 ctrl->id, ctrl->val); 1262 break; 1263 }; 1264 1265 pm_runtime_put(&client->dev); 1266 1267 return ret; 1268 } 1269 1270 static const struct v4l2_ctrl_ops ov13858_ctrl_ops = { 1271 .s_ctrl = ov13858_set_ctrl, 1272 }; 1273 1274 static int ov13858_enum_mbus_code(struct v4l2_subdev *sd, 1275 struct v4l2_subdev_pad_config *cfg, 1276 struct v4l2_subdev_mbus_code_enum *code) 1277 { 1278 /* Only one bayer order(GRBG) is supported */ 1279 if (code->index > 0) 1280 return -EINVAL; 1281 1282 code->code = MEDIA_BUS_FMT_SGRBG10_1X10; 1283 1284 return 0; 1285 } 1286 1287 static int ov13858_enum_frame_size(struct v4l2_subdev *sd, 1288 struct v4l2_subdev_pad_config *cfg, 1289 struct v4l2_subdev_frame_size_enum *fse) 1290 { 1291 if (fse->index >= ARRAY_SIZE(supported_modes)) 1292 return -EINVAL; 1293 1294 if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10) 1295 return -EINVAL; 1296 1297 fse->min_width = supported_modes[fse->index].width; 1298 fse->max_width = fse->min_width; 1299 fse->min_height = supported_modes[fse->index].height; 1300 fse->max_height = fse->min_height; 1301 1302 return 0; 1303 } 1304 1305 static void ov13858_update_pad_format(const struct ov13858_mode *mode, 1306 struct v4l2_subdev_format *fmt) 1307 { 1308 fmt->format.width = mode->width; 1309 fmt->format.height = mode->height; 1310 fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10; 1311 fmt->format.field = V4L2_FIELD_NONE; 1312 } 1313 1314 static int ov13858_do_get_pad_format(struct ov13858 *ov13858, 1315 struct v4l2_subdev_pad_config *cfg, 1316 struct v4l2_subdev_format *fmt) 1317 { 1318 struct v4l2_mbus_framefmt *framefmt; 1319 struct v4l2_subdev *sd = &ov13858->sd; 1320 1321 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { 1322 framefmt = v4l2_subdev_get_try_format(sd, cfg, fmt->pad); 1323 fmt->format = *framefmt; 1324 } else { 1325 ov13858_update_pad_format(ov13858->cur_mode, fmt); 1326 } 1327 1328 return 0; 1329 } 1330 1331 static int ov13858_get_pad_format(struct v4l2_subdev *sd, 1332 struct v4l2_subdev_pad_config *cfg, 1333 struct v4l2_subdev_format *fmt) 1334 { 1335 struct ov13858 *ov13858 = to_ov13858(sd); 1336 int ret; 1337 1338 mutex_lock(&ov13858->mutex); 1339 ret = ov13858_do_get_pad_format(ov13858, cfg, fmt); 1340 mutex_unlock(&ov13858->mutex); 1341 1342 return ret; 1343 } 1344 1345 /* 1346 * Calculate resolution distance 1347 */ 1348 static int 1349 ov13858_get_resolution_dist(const struct ov13858_mode *mode, 1350 struct v4l2_mbus_framefmt *framefmt) 1351 { 1352 return abs(mode->width - framefmt->width) + 1353 abs(mode->height - framefmt->height); 1354 } 1355 1356 /* 1357 * Find the closest supported resolution to the requested resolution 1358 */ 1359 static const struct ov13858_mode * 1360 ov13858_find_best_fit(struct ov13858 *ov13858, 1361 struct v4l2_subdev_format *fmt) 1362 { 1363 int i, dist, cur_best_fit = 0, cur_best_fit_dist = -1; 1364 struct v4l2_mbus_framefmt *framefmt = &fmt->format; 1365 1366 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) { 1367 dist = ov13858_get_resolution_dist(&supported_modes[i], 1368 framefmt); 1369 if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) { 1370 cur_best_fit_dist = dist; 1371 cur_best_fit = i; 1372 } 1373 } 1374 1375 return &supported_modes[cur_best_fit]; 1376 } 1377 1378 static int 1379 ov13858_set_pad_format(struct v4l2_subdev *sd, 1380 struct v4l2_subdev_pad_config *cfg, 1381 struct v4l2_subdev_format *fmt) 1382 { 1383 struct ov13858 *ov13858 = to_ov13858(sd); 1384 const struct ov13858_mode *mode; 1385 struct v4l2_mbus_framefmt *framefmt; 1386 s32 vblank_def; 1387 s32 vblank_min; 1388 s64 h_blank; 1389 s64 pixel_rate; 1390 s64 link_freq; 1391 1392 mutex_lock(&ov13858->mutex); 1393 1394 /* Only one raw bayer(GRBG) order is supported */ 1395 if (fmt->format.code != MEDIA_BUS_FMT_SGRBG10_1X10) 1396 fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10; 1397 1398 mode = ov13858_find_best_fit(ov13858, fmt); 1399 ov13858_update_pad_format(mode, fmt); 1400 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { 1401 framefmt = v4l2_subdev_get_try_format(sd, cfg, fmt->pad); 1402 *framefmt = fmt->format; 1403 } else { 1404 ov13858->cur_mode = mode; 1405 __v4l2_ctrl_s_ctrl(ov13858->link_freq, mode->link_freq_index); 1406 link_freq = link_freq_menu_items[mode->link_freq_index]; 1407 pixel_rate = LINK_FREQ_TO_PIXEL_RATE(link_freq); 1408 __v4l2_ctrl_s_ctrl_int64(ov13858->pixel_rate, pixel_rate); 1409 1410 /* Update limits and set FPS to default */ 1411 vblank_def = ov13858->cur_mode->vts_def - 1412 ov13858->cur_mode->height; 1413 vblank_min = ov13858->cur_mode->vts_min - 1414 ov13858->cur_mode->height; 1415 __v4l2_ctrl_modify_range( 1416 ov13858->vblank, vblank_min, 1417 OV13858_VTS_MAX - ov13858->cur_mode->height, 1, 1418 vblank_def); 1419 __v4l2_ctrl_s_ctrl(ov13858->vblank, vblank_def); 1420 h_blank = 1421 link_freq_configs[mode->link_freq_index].pixels_per_line 1422 - ov13858->cur_mode->width; 1423 __v4l2_ctrl_modify_range(ov13858->hblank, h_blank, 1424 h_blank, 1, h_blank); 1425 } 1426 1427 mutex_unlock(&ov13858->mutex); 1428 1429 return 0; 1430 } 1431 1432 static int ov13858_get_skip_frames(struct v4l2_subdev *sd, u32 *frames) 1433 { 1434 *frames = OV13858_NUM_OF_SKIP_FRAMES; 1435 1436 return 0; 1437 } 1438 1439 /* Start streaming */ 1440 static int ov13858_start_streaming(struct ov13858 *ov13858) 1441 { 1442 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd); 1443 const struct ov13858_reg_list *reg_list; 1444 int ret, link_freq_index; 1445 1446 /* Get out of from software reset */ 1447 ret = ov13858_write_reg(ov13858, OV13858_REG_SOFTWARE_RST, 1448 OV13858_REG_VALUE_08BIT, OV13858_SOFTWARE_RST); 1449 if (ret) { 1450 dev_err(&client->dev, "%s failed to set powerup registers\n", 1451 __func__); 1452 return ret; 1453 } 1454 1455 /* Setup PLL */ 1456 link_freq_index = ov13858->cur_mode->link_freq_index; 1457 reg_list = &link_freq_configs[link_freq_index].reg_list; 1458 ret = ov13858_write_reg_list(ov13858, reg_list); 1459 if (ret) { 1460 dev_err(&client->dev, "%s failed to set plls\n", __func__); 1461 return ret; 1462 } 1463 1464 /* Apply default values of current mode */ 1465 reg_list = &ov13858->cur_mode->reg_list; 1466 ret = ov13858_write_reg_list(ov13858, reg_list); 1467 if (ret) { 1468 dev_err(&client->dev, "%s failed to set mode\n", __func__); 1469 return ret; 1470 } 1471 1472 /* Apply customized values from user */ 1473 ret = __v4l2_ctrl_handler_setup(ov13858->sd.ctrl_handler); 1474 if (ret) 1475 return ret; 1476 1477 return ov13858_write_reg(ov13858, OV13858_REG_MODE_SELECT, 1478 OV13858_REG_VALUE_08BIT, 1479 OV13858_MODE_STREAMING); 1480 } 1481 1482 /* Stop streaming */ 1483 static int ov13858_stop_streaming(struct ov13858 *ov13858) 1484 { 1485 return ov13858_write_reg(ov13858, OV13858_REG_MODE_SELECT, 1486 OV13858_REG_VALUE_08BIT, OV13858_MODE_STANDBY); 1487 } 1488 1489 static int ov13858_set_stream(struct v4l2_subdev *sd, int enable) 1490 { 1491 struct ov13858 *ov13858 = to_ov13858(sd); 1492 struct i2c_client *client = v4l2_get_subdevdata(sd); 1493 int ret = 0; 1494 1495 mutex_lock(&ov13858->mutex); 1496 if (ov13858->streaming == enable) { 1497 mutex_unlock(&ov13858->mutex); 1498 return 0; 1499 } 1500 1501 if (enable) { 1502 ret = pm_runtime_get_sync(&client->dev); 1503 if (ret < 0) { 1504 pm_runtime_put_noidle(&client->dev); 1505 goto err_unlock; 1506 } 1507 1508 /* 1509 * Apply default & customized values 1510 * and then start streaming. 1511 */ 1512 ret = ov13858_start_streaming(ov13858); 1513 if (ret) 1514 goto err_rpm_put; 1515 } else { 1516 ov13858_stop_streaming(ov13858); 1517 pm_runtime_put(&client->dev); 1518 } 1519 1520 ov13858->streaming = enable; 1521 mutex_unlock(&ov13858->mutex); 1522 1523 return ret; 1524 1525 err_rpm_put: 1526 pm_runtime_put(&client->dev); 1527 err_unlock: 1528 mutex_unlock(&ov13858->mutex); 1529 1530 return ret; 1531 } 1532 1533 static int __maybe_unused ov13858_suspend(struct device *dev) 1534 { 1535 struct i2c_client *client = to_i2c_client(dev); 1536 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1537 struct ov13858 *ov13858 = to_ov13858(sd); 1538 1539 if (ov13858->streaming) 1540 ov13858_stop_streaming(ov13858); 1541 1542 return 0; 1543 } 1544 1545 static int __maybe_unused ov13858_resume(struct device *dev) 1546 { 1547 struct i2c_client *client = to_i2c_client(dev); 1548 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1549 struct ov13858 *ov13858 = to_ov13858(sd); 1550 int ret; 1551 1552 if (ov13858->streaming) { 1553 ret = ov13858_start_streaming(ov13858); 1554 if (ret) 1555 goto error; 1556 } 1557 1558 return 0; 1559 1560 error: 1561 ov13858_stop_streaming(ov13858); 1562 ov13858->streaming = 0; 1563 return ret; 1564 } 1565 1566 /* Verify chip ID */ 1567 static int ov13858_identify_module(struct ov13858 *ov13858) 1568 { 1569 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd); 1570 int ret; 1571 u32 val; 1572 1573 ret = ov13858_read_reg(ov13858, OV13858_REG_CHIP_ID, 1574 OV13858_REG_VALUE_24BIT, &val); 1575 if (ret) 1576 return ret; 1577 1578 if (val != OV13858_CHIP_ID) { 1579 dev_err(&client->dev, "chip id mismatch: %x!=%x\n", 1580 OV13858_CHIP_ID, val); 1581 return -EIO; 1582 } 1583 1584 return 0; 1585 } 1586 1587 static const struct v4l2_subdev_video_ops ov13858_video_ops = { 1588 .s_stream = ov13858_set_stream, 1589 }; 1590 1591 static const struct v4l2_subdev_pad_ops ov13858_pad_ops = { 1592 .enum_mbus_code = ov13858_enum_mbus_code, 1593 .get_fmt = ov13858_get_pad_format, 1594 .set_fmt = ov13858_set_pad_format, 1595 .enum_frame_size = ov13858_enum_frame_size, 1596 }; 1597 1598 static const struct v4l2_subdev_sensor_ops ov13858_sensor_ops = { 1599 .g_skip_frames = ov13858_get_skip_frames, 1600 }; 1601 1602 static const struct v4l2_subdev_ops ov13858_subdev_ops = { 1603 .video = &ov13858_video_ops, 1604 .pad = &ov13858_pad_ops, 1605 .sensor = &ov13858_sensor_ops, 1606 }; 1607 1608 static const struct media_entity_operations ov13858_subdev_entity_ops = { 1609 .link_validate = v4l2_subdev_link_validate, 1610 }; 1611 1612 static const struct v4l2_subdev_internal_ops ov13858_internal_ops = { 1613 .open = ov13858_open, 1614 }; 1615 1616 /* Initialize control handlers */ 1617 static int ov13858_init_controls(struct ov13858 *ov13858) 1618 { 1619 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd); 1620 struct v4l2_ctrl_handler *ctrl_hdlr; 1621 s64 exposure_max; 1622 s64 vblank_def; 1623 s64 vblank_min; 1624 s64 hblank; 1625 s64 pixel_rate_min; 1626 s64 pixel_rate_max; 1627 const struct ov13858_mode *mode; 1628 int ret; 1629 1630 ctrl_hdlr = &ov13858->ctrl_handler; 1631 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 8); 1632 if (ret) 1633 return ret; 1634 1635 mutex_init(&ov13858->mutex); 1636 ctrl_hdlr->lock = &ov13858->mutex; 1637 ov13858->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, 1638 &ov13858_ctrl_ops, 1639 V4L2_CID_LINK_FREQ, 1640 OV13858_NUM_OF_LINK_FREQS - 1, 1641 0, 1642 link_freq_menu_items); 1643 ov13858->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; 1644 1645 pixel_rate_max = LINK_FREQ_TO_PIXEL_RATE(link_freq_menu_items[0]); 1646 pixel_rate_min = LINK_FREQ_TO_PIXEL_RATE(link_freq_menu_items[1]); 1647 /* By default, PIXEL_RATE is read only */ 1648 ov13858->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov13858_ctrl_ops, 1649 V4L2_CID_PIXEL_RATE, 1650 pixel_rate_min, pixel_rate_max, 1651 1, pixel_rate_max); 1652 1653 mode = ov13858->cur_mode; 1654 vblank_def = mode->vts_def - mode->height; 1655 vblank_min = mode->vts_min - mode->height; 1656 ov13858->vblank = v4l2_ctrl_new_std( 1657 ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_VBLANK, 1658 vblank_min, OV13858_VTS_MAX - mode->height, 1, 1659 vblank_def); 1660 1661 hblank = link_freq_configs[mode->link_freq_index].pixels_per_line - 1662 mode->width; 1663 ov13858->hblank = v4l2_ctrl_new_std( 1664 ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_HBLANK, 1665 hblank, hblank, 1, hblank); 1666 ov13858->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; 1667 1668 exposure_max = mode->vts_def - 8; 1669 ov13858->exposure = v4l2_ctrl_new_std( 1670 ctrl_hdlr, &ov13858_ctrl_ops, 1671 V4L2_CID_EXPOSURE, OV13858_EXPOSURE_MIN, 1672 exposure_max, OV13858_EXPOSURE_STEP, 1673 OV13858_EXPOSURE_DEFAULT); 1674 1675 v4l2_ctrl_new_std(ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, 1676 OV13858_ANA_GAIN_MIN, OV13858_ANA_GAIN_MAX, 1677 OV13858_ANA_GAIN_STEP, OV13858_ANA_GAIN_DEFAULT); 1678 1679 /* Digital gain */ 1680 v4l2_ctrl_new_std(ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_DIGITAL_GAIN, 1681 OV13858_DGTL_GAIN_MIN, OV13858_DGTL_GAIN_MAX, 1682 OV13858_DGTL_GAIN_STEP, OV13858_DGTL_GAIN_DEFAULT); 1683 1684 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov13858_ctrl_ops, 1685 V4L2_CID_TEST_PATTERN, 1686 ARRAY_SIZE(ov13858_test_pattern_menu) - 1, 1687 0, 0, ov13858_test_pattern_menu); 1688 if (ctrl_hdlr->error) { 1689 ret = ctrl_hdlr->error; 1690 dev_err(&client->dev, "%s control init failed (%d)\n", 1691 __func__, ret); 1692 goto error; 1693 } 1694 1695 ov13858->sd.ctrl_handler = ctrl_hdlr; 1696 1697 return 0; 1698 1699 error: 1700 v4l2_ctrl_handler_free(ctrl_hdlr); 1701 mutex_destroy(&ov13858->mutex); 1702 1703 return ret; 1704 } 1705 1706 static void ov13858_free_controls(struct ov13858 *ov13858) 1707 { 1708 v4l2_ctrl_handler_free(ov13858->sd.ctrl_handler); 1709 mutex_destroy(&ov13858->mutex); 1710 } 1711 1712 static int ov13858_probe(struct i2c_client *client, 1713 const struct i2c_device_id *devid) 1714 { 1715 struct ov13858 *ov13858; 1716 int ret; 1717 u32 val = 0; 1718 1719 device_property_read_u32(&client->dev, "clock-frequency", &val); 1720 if (val != 19200000) 1721 return -EINVAL; 1722 1723 ov13858 = devm_kzalloc(&client->dev, sizeof(*ov13858), GFP_KERNEL); 1724 if (!ov13858) 1725 return -ENOMEM; 1726 1727 /* Initialize subdev */ 1728 v4l2_i2c_subdev_init(&ov13858->sd, client, &ov13858_subdev_ops); 1729 1730 /* Check module identity */ 1731 ret = ov13858_identify_module(ov13858); 1732 if (ret) { 1733 dev_err(&client->dev, "failed to find sensor: %d\n", ret); 1734 return ret; 1735 } 1736 1737 /* Set default mode to max resolution */ 1738 ov13858->cur_mode = &supported_modes[0]; 1739 1740 ret = ov13858_init_controls(ov13858); 1741 if (ret) 1742 return ret; 1743 1744 /* Initialize subdev */ 1745 ov13858->sd.internal_ops = &ov13858_internal_ops; 1746 ov13858->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1747 ov13858->sd.entity.ops = &ov13858_subdev_entity_ops; 1748 ov13858->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1749 1750 /* Initialize source pad */ 1751 ov13858->pad.flags = MEDIA_PAD_FL_SOURCE; 1752 ret = media_entity_pads_init(&ov13858->sd.entity, 1, &ov13858->pad); 1753 if (ret) { 1754 dev_err(&client->dev, "%s failed:%d\n", __func__, ret); 1755 goto error_handler_free; 1756 } 1757 1758 ret = v4l2_async_register_subdev(&ov13858->sd); 1759 if (ret < 0) 1760 goto error_media_entity; 1761 1762 /* 1763 * Device is already turned on by i2c-core with ACPI domain PM. 1764 * Enable runtime PM and turn off the device. 1765 */ 1766 pm_runtime_get_noresume(&client->dev); 1767 pm_runtime_set_active(&client->dev); 1768 pm_runtime_enable(&client->dev); 1769 pm_runtime_put(&client->dev); 1770 1771 return 0; 1772 1773 error_media_entity: 1774 media_entity_cleanup(&ov13858->sd.entity); 1775 1776 error_handler_free: 1777 ov13858_free_controls(ov13858); 1778 dev_err(&client->dev, "%s failed:%d\n", __func__, ret); 1779 1780 return ret; 1781 } 1782 1783 static int ov13858_remove(struct i2c_client *client) 1784 { 1785 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1786 struct ov13858 *ov13858 = to_ov13858(sd); 1787 1788 v4l2_async_unregister_subdev(sd); 1789 media_entity_cleanup(&sd->entity); 1790 ov13858_free_controls(ov13858); 1791 1792 /* 1793 * Disable runtime PM but keep the device turned on. 1794 * i2c-core with ACPI domain PM will turn off the device. 1795 */ 1796 pm_runtime_get_sync(&client->dev); 1797 pm_runtime_disable(&client->dev); 1798 pm_runtime_set_suspended(&client->dev); 1799 pm_runtime_put_noidle(&client->dev); 1800 1801 return 0; 1802 } 1803 1804 static const struct i2c_device_id ov13858_id_table[] = { 1805 {"ov13858", 0}, 1806 {}, 1807 }; 1808 1809 MODULE_DEVICE_TABLE(i2c, ov13858_id_table); 1810 1811 static const struct dev_pm_ops ov13858_pm_ops = { 1812 SET_SYSTEM_SLEEP_PM_OPS(ov13858_suspend, ov13858_resume) 1813 }; 1814 1815 #ifdef CONFIG_ACPI 1816 static const struct acpi_device_id ov13858_acpi_ids[] = { 1817 {"OVTID858"}, 1818 { /* sentinel */ } 1819 }; 1820 1821 MODULE_DEVICE_TABLE(acpi, ov13858_acpi_ids); 1822 #endif 1823 1824 static struct i2c_driver ov13858_i2c_driver = { 1825 .driver = { 1826 .name = "ov13858", 1827 .owner = THIS_MODULE, 1828 .pm = &ov13858_pm_ops, 1829 .acpi_match_table = ACPI_PTR(ov13858_acpi_ids), 1830 }, 1831 .probe = ov13858_probe, 1832 .remove = ov13858_remove, 1833 .id_table = ov13858_id_table, 1834 }; 1835 1836 module_i2c_driver(ov13858_i2c_driver); 1837 1838 MODULE_AUTHOR("Kan, Chris <chris.kan@intel.com>"); 1839 MODULE_AUTHOR("Rapolu, Chiranjeevi <chiranjeevi.rapolu@intel.com>"); 1840 MODULE_AUTHOR("Yang, Hyungwoo <hyungwoo.yang@intel.com>"); 1841 MODULE_DESCRIPTION("Omnivision ov13858 sensor driver"); 1842 MODULE_LICENSE("GPL v2"); 1843