1 /* 2 * Montage M88DS3103 demodulator driver 3 * 4 * Copyright (C) 2013 Antti Palosaari <crope@iki.fi> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, write to the Free Software Foundation, Inc., 18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 19 */ 20 21 #include "m88ds3103_priv.h" 22 23 static struct dvb_frontend_ops m88ds3103_ops; 24 25 /* write multiple registers */ 26 static int m88ds3103_wr_regs(struct m88ds3103_priv *priv, 27 u8 reg, const u8 *val, int len) 28 { 29 #define MAX_WR_LEN 32 30 #define MAX_WR_XFER_LEN (MAX_WR_LEN + 1) 31 int ret; 32 u8 buf[MAX_WR_XFER_LEN]; 33 struct i2c_msg msg[1] = { 34 { 35 .addr = priv->cfg->i2c_addr, 36 .flags = 0, 37 .len = 1 + len, 38 .buf = buf, 39 } 40 }; 41 42 if (WARN_ON(len > MAX_WR_LEN)) 43 return -EINVAL; 44 45 buf[0] = reg; 46 memcpy(&buf[1], val, len); 47 48 mutex_lock(&priv->i2c_mutex); 49 ret = i2c_transfer(priv->i2c, msg, 1); 50 mutex_unlock(&priv->i2c_mutex); 51 if (ret == 1) { 52 ret = 0; 53 } else { 54 dev_warn(&priv->i2c->dev, 55 "%s: i2c wr failed=%d reg=%02x len=%d\n", 56 KBUILD_MODNAME, ret, reg, len); 57 ret = -EREMOTEIO; 58 } 59 60 return ret; 61 } 62 63 /* read multiple registers */ 64 static int m88ds3103_rd_regs(struct m88ds3103_priv *priv, 65 u8 reg, u8 *val, int len) 66 { 67 #define MAX_RD_LEN 3 68 #define MAX_RD_XFER_LEN (MAX_RD_LEN) 69 int ret; 70 u8 buf[MAX_RD_XFER_LEN]; 71 struct i2c_msg msg[2] = { 72 { 73 .addr = priv->cfg->i2c_addr, 74 .flags = 0, 75 .len = 1, 76 .buf = ®, 77 }, { 78 .addr = priv->cfg->i2c_addr, 79 .flags = I2C_M_RD, 80 .len = len, 81 .buf = buf, 82 } 83 }; 84 85 if (WARN_ON(len > MAX_RD_LEN)) 86 return -EINVAL; 87 88 mutex_lock(&priv->i2c_mutex); 89 ret = i2c_transfer(priv->i2c, msg, 2); 90 mutex_unlock(&priv->i2c_mutex); 91 if (ret == 2) { 92 memcpy(val, buf, len); 93 ret = 0; 94 } else { 95 dev_warn(&priv->i2c->dev, 96 "%s: i2c rd failed=%d reg=%02x len=%d\n", 97 KBUILD_MODNAME, ret, reg, len); 98 ret = -EREMOTEIO; 99 } 100 101 return ret; 102 } 103 104 /* write single register */ 105 static int m88ds3103_wr_reg(struct m88ds3103_priv *priv, u8 reg, u8 val) 106 { 107 return m88ds3103_wr_regs(priv, reg, &val, 1); 108 } 109 110 /* read single register */ 111 static int m88ds3103_rd_reg(struct m88ds3103_priv *priv, u8 reg, u8 *val) 112 { 113 return m88ds3103_rd_regs(priv, reg, val, 1); 114 } 115 116 /* write single register with mask */ 117 static int m88ds3103_wr_reg_mask(struct m88ds3103_priv *priv, 118 u8 reg, u8 val, u8 mask) 119 { 120 int ret; 121 u8 u8tmp; 122 123 /* no need for read if whole reg is written */ 124 if (mask != 0xff) { 125 ret = m88ds3103_rd_regs(priv, reg, &u8tmp, 1); 126 if (ret) 127 return ret; 128 129 val &= mask; 130 u8tmp &= ~mask; 131 val |= u8tmp; 132 } 133 134 return m88ds3103_wr_regs(priv, reg, &val, 1); 135 } 136 137 /* read single register with mask */ 138 static int m88ds3103_rd_reg_mask(struct m88ds3103_priv *priv, 139 u8 reg, u8 *val, u8 mask) 140 { 141 int ret, i; 142 u8 u8tmp; 143 144 ret = m88ds3103_rd_regs(priv, reg, &u8tmp, 1); 145 if (ret) 146 return ret; 147 148 u8tmp &= mask; 149 150 /* find position of the first bit */ 151 for (i = 0; i < 8; i++) { 152 if ((mask >> i) & 0x01) 153 break; 154 } 155 *val = u8tmp >> i; 156 157 return 0; 158 } 159 160 /* write reg val table using reg addr auto increment */ 161 static int m88ds3103_wr_reg_val_tab(struct m88ds3103_priv *priv, 162 const struct m88ds3103_reg_val *tab, int tab_len) 163 { 164 int ret, i, j; 165 u8 buf[83]; 166 dev_dbg(&priv->i2c->dev, "%s: tab_len=%d\n", __func__, tab_len); 167 168 if (tab_len > 83) { 169 ret = -EINVAL; 170 goto err; 171 } 172 173 for (i = 0, j = 0; i < tab_len; i++, j++) { 174 buf[j] = tab[i].val; 175 176 if (i == tab_len - 1 || tab[i].reg != tab[i + 1].reg - 1 || 177 !((j + 1) % (priv->cfg->i2c_wr_max - 1))) { 178 ret = m88ds3103_wr_regs(priv, tab[i].reg - j, buf, j + 1); 179 if (ret) 180 goto err; 181 182 j = -1; 183 } 184 } 185 186 return 0; 187 err: 188 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); 189 return ret; 190 } 191 192 static int m88ds3103_read_status(struct dvb_frontend *fe, fe_status_t *status) 193 { 194 struct m88ds3103_priv *priv = fe->demodulator_priv; 195 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 196 int ret; 197 u8 u8tmp; 198 199 *status = 0; 200 201 if (!priv->warm) { 202 ret = -EAGAIN; 203 goto err; 204 } 205 206 switch (c->delivery_system) { 207 case SYS_DVBS: 208 ret = m88ds3103_rd_reg_mask(priv, 0xd1, &u8tmp, 0x07); 209 if (ret) 210 goto err; 211 212 if (u8tmp == 0x07) 213 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER | 214 FE_HAS_VITERBI | FE_HAS_SYNC | 215 FE_HAS_LOCK; 216 break; 217 case SYS_DVBS2: 218 ret = m88ds3103_rd_reg_mask(priv, 0x0d, &u8tmp, 0x8f); 219 if (ret) 220 goto err; 221 222 if (u8tmp == 0x8f) 223 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER | 224 FE_HAS_VITERBI | FE_HAS_SYNC | 225 FE_HAS_LOCK; 226 break; 227 default: 228 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n", 229 __func__); 230 ret = -EINVAL; 231 goto err; 232 } 233 234 priv->fe_status = *status; 235 236 dev_dbg(&priv->i2c->dev, "%s: lock=%02x status=%02x\n", 237 __func__, u8tmp, *status); 238 239 return 0; 240 err: 241 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); 242 return ret; 243 } 244 245 static int m88ds3103_set_frontend(struct dvb_frontend *fe) 246 { 247 struct m88ds3103_priv *priv = fe->demodulator_priv; 248 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 249 int ret, len; 250 const struct m88ds3103_reg_val *init; 251 u8 u8tmp, u8tmp1, u8tmp2; 252 u8 buf[2]; 253 u16 u16tmp, divide_ratio; 254 u32 tuner_frequency, target_mclk, ts_clk; 255 s32 s32tmp; 256 dev_dbg(&priv->i2c->dev, 257 "%s: delivery_system=%d modulation=%d frequency=%d symbol_rate=%d inversion=%d pilot=%d rolloff=%d\n", 258 __func__, c->delivery_system, 259 c->modulation, c->frequency, c->symbol_rate, 260 c->inversion, c->pilot, c->rolloff); 261 262 if (!priv->warm) { 263 ret = -EAGAIN; 264 goto err; 265 } 266 267 /* program tuner */ 268 if (fe->ops.tuner_ops.set_params) { 269 ret = fe->ops.tuner_ops.set_params(fe); 270 if (ret) 271 goto err; 272 } 273 274 if (fe->ops.tuner_ops.get_frequency) { 275 ret = fe->ops.tuner_ops.get_frequency(fe, &tuner_frequency); 276 if (ret) 277 goto err; 278 } 279 280 /* reset */ 281 ret = m88ds3103_wr_reg(priv, 0x07, 0x80); 282 if (ret) 283 goto err; 284 285 ret = m88ds3103_wr_reg(priv, 0x07, 0x00); 286 if (ret) 287 goto err; 288 289 ret = m88ds3103_wr_reg(priv, 0xb2, 0x01); 290 if (ret) 291 goto err; 292 293 ret = m88ds3103_wr_reg(priv, 0x00, 0x01); 294 if (ret) 295 goto err; 296 297 switch (c->delivery_system) { 298 case SYS_DVBS: 299 len = ARRAY_SIZE(m88ds3103_dvbs_init_reg_vals); 300 init = m88ds3103_dvbs_init_reg_vals; 301 target_mclk = 96000; 302 break; 303 case SYS_DVBS2: 304 len = ARRAY_SIZE(m88ds3103_dvbs2_init_reg_vals); 305 init = m88ds3103_dvbs2_init_reg_vals; 306 307 switch (priv->cfg->ts_mode) { 308 case M88DS3103_TS_SERIAL: 309 case M88DS3103_TS_SERIAL_D7: 310 if (c->symbol_rate < 18000000) 311 target_mclk = 96000; 312 else 313 target_mclk = 144000; 314 break; 315 case M88DS3103_TS_PARALLEL: 316 case M88DS3103_TS_PARALLEL_12: 317 case M88DS3103_TS_PARALLEL_16: 318 case M88DS3103_TS_PARALLEL_19_2: 319 case M88DS3103_TS_CI: 320 if (c->symbol_rate < 18000000) 321 target_mclk = 96000; 322 else if (c->symbol_rate < 28000000) 323 target_mclk = 144000; 324 else 325 target_mclk = 192000; 326 break; 327 default: 328 dev_dbg(&priv->i2c->dev, "%s: invalid ts_mode\n", 329 __func__); 330 ret = -EINVAL; 331 goto err; 332 } 333 break; 334 default: 335 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n", 336 __func__); 337 ret = -EINVAL; 338 goto err; 339 } 340 341 /* program init table */ 342 if (c->delivery_system != priv->delivery_system) { 343 ret = m88ds3103_wr_reg_val_tab(priv, init, len); 344 if (ret) 345 goto err; 346 } 347 348 u8tmp1 = 0; /* silence compiler warning */ 349 switch (priv->cfg->ts_mode) { 350 case M88DS3103_TS_SERIAL: 351 u8tmp1 = 0x00; 352 ts_clk = 0; 353 u8tmp = 0x46; 354 break; 355 case M88DS3103_TS_SERIAL_D7: 356 u8tmp1 = 0x20; 357 ts_clk = 0; 358 u8tmp = 0x46; 359 break; 360 case M88DS3103_TS_PARALLEL: 361 ts_clk = 24000; 362 u8tmp = 0x42; 363 break; 364 case M88DS3103_TS_PARALLEL_12: 365 ts_clk = 12000; 366 u8tmp = 0x42; 367 break; 368 case M88DS3103_TS_PARALLEL_16: 369 ts_clk = 16000; 370 u8tmp = 0x42; 371 break; 372 case M88DS3103_TS_PARALLEL_19_2: 373 ts_clk = 19200; 374 u8tmp = 0x42; 375 break; 376 case M88DS3103_TS_CI: 377 ts_clk = 6000; 378 u8tmp = 0x43; 379 break; 380 default: 381 dev_dbg(&priv->i2c->dev, "%s: invalid ts_mode\n", __func__); 382 ret = -EINVAL; 383 goto err; 384 } 385 386 /* TS mode */ 387 ret = m88ds3103_wr_reg(priv, 0xfd, u8tmp); 388 if (ret) 389 goto err; 390 391 switch (priv->cfg->ts_mode) { 392 case M88DS3103_TS_SERIAL: 393 case M88DS3103_TS_SERIAL_D7: 394 ret = m88ds3103_wr_reg_mask(priv, 0x29, u8tmp1, 0x20); 395 if (ret) 396 goto err; 397 } 398 399 if (ts_clk) { 400 divide_ratio = DIV_ROUND_UP(target_mclk, ts_clk); 401 u8tmp1 = divide_ratio / 2; 402 u8tmp2 = DIV_ROUND_UP(divide_ratio, 2); 403 } else { 404 divide_ratio = 0; 405 u8tmp1 = 0; 406 u8tmp2 = 0; 407 } 408 409 dev_dbg(&priv->i2c->dev, 410 "%s: target_mclk=%d ts_clk=%d divide_ratio=%d\n", 411 __func__, target_mclk, ts_clk, divide_ratio); 412 413 u8tmp1--; 414 u8tmp2--; 415 /* u8tmp1[5:2] => fe[3:0], u8tmp1[1:0] => ea[7:6] */ 416 u8tmp1 &= 0x3f; 417 /* u8tmp2[5:0] => ea[5:0] */ 418 u8tmp2 &= 0x3f; 419 420 ret = m88ds3103_rd_reg(priv, 0xfe, &u8tmp); 421 if (ret) 422 goto err; 423 424 u8tmp = ((u8tmp & 0xf0) << 0) | u8tmp1 >> 2; 425 ret = m88ds3103_wr_reg(priv, 0xfe, u8tmp); 426 if (ret) 427 goto err; 428 429 u8tmp = ((u8tmp1 & 0x03) << 6) | u8tmp2 >> 0; 430 ret = m88ds3103_wr_reg(priv, 0xea, u8tmp); 431 if (ret) 432 goto err; 433 434 switch (target_mclk) { 435 case 72000: 436 u8tmp1 = 0x00; /* 0b00 */ 437 u8tmp2 = 0x03; /* 0b11 */ 438 break; 439 case 96000: 440 u8tmp1 = 0x02; /* 0b10 */ 441 u8tmp2 = 0x01; /* 0b01 */ 442 break; 443 case 115200: 444 u8tmp1 = 0x01; /* 0b01 */ 445 u8tmp2 = 0x01; /* 0b01 */ 446 break; 447 case 144000: 448 u8tmp1 = 0x00; /* 0b00 */ 449 u8tmp2 = 0x01; /* 0b01 */ 450 break; 451 case 192000: 452 u8tmp1 = 0x03; /* 0b11 */ 453 u8tmp2 = 0x00; /* 0b00 */ 454 break; 455 default: 456 dev_dbg(&priv->i2c->dev, "%s: invalid target_mclk\n", __func__); 457 ret = -EINVAL; 458 goto err; 459 } 460 461 ret = m88ds3103_wr_reg_mask(priv, 0x22, u8tmp1 << 6, 0xc0); 462 if (ret) 463 goto err; 464 465 ret = m88ds3103_wr_reg_mask(priv, 0x24, u8tmp2 << 6, 0xc0); 466 if (ret) 467 goto err; 468 469 if (c->symbol_rate <= 3000000) 470 u8tmp = 0x20; 471 else if (c->symbol_rate <= 10000000) 472 u8tmp = 0x10; 473 else 474 u8tmp = 0x06; 475 476 ret = m88ds3103_wr_reg(priv, 0xc3, 0x08); 477 if (ret) 478 goto err; 479 480 ret = m88ds3103_wr_reg(priv, 0xc8, u8tmp); 481 if (ret) 482 goto err; 483 484 ret = m88ds3103_wr_reg(priv, 0xc4, 0x08); 485 if (ret) 486 goto err; 487 488 ret = m88ds3103_wr_reg(priv, 0xc7, 0x00); 489 if (ret) 490 goto err; 491 492 u16tmp = DIV_ROUND_CLOSEST((c->symbol_rate / 1000) << 15, M88DS3103_MCLK_KHZ / 2); 493 buf[0] = (u16tmp >> 0) & 0xff; 494 buf[1] = (u16tmp >> 8) & 0xff; 495 ret = m88ds3103_wr_regs(priv, 0x61, buf, 2); 496 if (ret) 497 goto err; 498 499 ret = m88ds3103_wr_reg_mask(priv, 0x4d, priv->cfg->spec_inv << 1, 0x02); 500 if (ret) 501 goto err; 502 503 ret = m88ds3103_wr_reg_mask(priv, 0x30, priv->cfg->agc_inv << 4, 0x10); 504 if (ret) 505 goto err; 506 507 ret = m88ds3103_wr_reg(priv, 0x33, priv->cfg->agc); 508 if (ret) 509 goto err; 510 511 dev_dbg(&priv->i2c->dev, "%s: carrier offset=%d\n", __func__, 512 (tuner_frequency - c->frequency)); 513 514 s32tmp = 0x10000 * (tuner_frequency - c->frequency); 515 s32tmp = DIV_ROUND_CLOSEST(s32tmp, M88DS3103_MCLK_KHZ); 516 if (s32tmp < 0) 517 s32tmp += 0x10000; 518 519 buf[0] = (s32tmp >> 0) & 0xff; 520 buf[1] = (s32tmp >> 8) & 0xff; 521 ret = m88ds3103_wr_regs(priv, 0x5e, buf, 2); 522 if (ret) 523 goto err; 524 525 ret = m88ds3103_wr_reg(priv, 0x00, 0x00); 526 if (ret) 527 goto err; 528 529 ret = m88ds3103_wr_reg(priv, 0xb2, 0x00); 530 if (ret) 531 goto err; 532 533 priv->delivery_system = c->delivery_system; 534 535 return 0; 536 err: 537 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); 538 return ret; 539 } 540 541 static int m88ds3103_init(struct dvb_frontend *fe) 542 { 543 struct m88ds3103_priv *priv = fe->demodulator_priv; 544 int ret, len, remaining; 545 const struct firmware *fw = NULL; 546 u8 *fw_file = M88DS3103_FIRMWARE; 547 u8 u8tmp; 548 dev_dbg(&priv->i2c->dev, "%s:\n", __func__); 549 550 /* set cold state by default */ 551 priv->warm = false; 552 553 /* wake up device from sleep */ 554 ret = m88ds3103_wr_reg_mask(priv, 0x08, 0x01, 0x01); 555 if (ret) 556 goto err; 557 558 ret = m88ds3103_wr_reg_mask(priv, 0x04, 0x00, 0x01); 559 if (ret) 560 goto err; 561 562 ret = m88ds3103_wr_reg_mask(priv, 0x23, 0x00, 0x10); 563 if (ret) 564 goto err; 565 566 /* reset */ 567 ret = m88ds3103_wr_reg(priv, 0x07, 0x60); 568 if (ret) 569 goto err; 570 571 ret = m88ds3103_wr_reg(priv, 0x07, 0x00); 572 if (ret) 573 goto err; 574 575 /* firmware status */ 576 ret = m88ds3103_rd_reg(priv, 0xb9, &u8tmp); 577 if (ret) 578 goto err; 579 580 dev_dbg(&priv->i2c->dev, "%s: firmware=%02x\n", __func__, u8tmp); 581 582 if (u8tmp) 583 goto skip_fw_download; 584 585 /* cold state - try to download firmware */ 586 dev_info(&priv->i2c->dev, "%s: found a '%s' in cold state\n", 587 KBUILD_MODNAME, m88ds3103_ops.info.name); 588 589 /* request the firmware, this will block and timeout */ 590 ret = request_firmware(&fw, fw_file, priv->i2c->dev.parent); 591 if (ret) { 592 dev_err(&priv->i2c->dev, "%s: firmare file '%s' not found\n", 593 KBUILD_MODNAME, fw_file); 594 goto err; 595 } 596 597 dev_info(&priv->i2c->dev, "%s: downloading firmware from file '%s'\n", 598 KBUILD_MODNAME, fw_file); 599 600 ret = m88ds3103_wr_reg(priv, 0xb2, 0x01); 601 if (ret) 602 goto err; 603 604 for (remaining = fw->size; remaining > 0; 605 remaining -= (priv->cfg->i2c_wr_max - 1)) { 606 len = remaining; 607 if (len > (priv->cfg->i2c_wr_max - 1)) 608 len = (priv->cfg->i2c_wr_max - 1); 609 610 ret = m88ds3103_wr_regs(priv, 0xb0, 611 &fw->data[fw->size - remaining], len); 612 if (ret) { 613 dev_err(&priv->i2c->dev, 614 "%s: firmware download failed=%d\n", 615 KBUILD_MODNAME, ret); 616 goto err; 617 } 618 } 619 620 ret = m88ds3103_wr_reg(priv, 0xb2, 0x00); 621 if (ret) 622 goto err; 623 624 release_firmware(fw); 625 fw = NULL; 626 627 ret = m88ds3103_rd_reg(priv, 0xb9, &u8tmp); 628 if (ret) 629 goto err; 630 631 if (!u8tmp) { 632 dev_info(&priv->i2c->dev, "%s: firmware did not run\n", 633 KBUILD_MODNAME); 634 ret = -EFAULT; 635 goto err; 636 } 637 638 dev_info(&priv->i2c->dev, "%s: found a '%s' in warm state\n", 639 KBUILD_MODNAME, m88ds3103_ops.info.name); 640 dev_info(&priv->i2c->dev, "%s: firmware version %X.%X\n", 641 KBUILD_MODNAME, (u8tmp >> 4) & 0xf, (u8tmp >> 0 & 0xf)); 642 643 skip_fw_download: 644 /* warm state */ 645 priv->warm = true; 646 647 return 0; 648 err: 649 if (fw) 650 release_firmware(fw); 651 652 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); 653 return ret; 654 } 655 656 static int m88ds3103_sleep(struct dvb_frontend *fe) 657 { 658 struct m88ds3103_priv *priv = fe->demodulator_priv; 659 int ret; 660 dev_dbg(&priv->i2c->dev, "%s:\n", __func__); 661 662 priv->delivery_system = SYS_UNDEFINED; 663 664 /* TS Hi-Z */ 665 ret = m88ds3103_wr_reg_mask(priv, 0x27, 0x00, 0x01); 666 if (ret) 667 goto err; 668 669 /* sleep */ 670 ret = m88ds3103_wr_reg_mask(priv, 0x08, 0x00, 0x01); 671 if (ret) 672 goto err; 673 674 ret = m88ds3103_wr_reg_mask(priv, 0x04, 0x01, 0x01); 675 if (ret) 676 goto err; 677 678 ret = m88ds3103_wr_reg_mask(priv, 0x23, 0x10, 0x10); 679 if (ret) 680 goto err; 681 682 return 0; 683 err: 684 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); 685 return ret; 686 } 687 688 static int m88ds3103_get_frontend(struct dvb_frontend *fe) 689 { 690 struct m88ds3103_priv *priv = fe->demodulator_priv; 691 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 692 int ret; 693 u8 buf[3]; 694 dev_dbg(&priv->i2c->dev, "%s:\n", __func__); 695 696 if (!priv->warm || !(priv->fe_status & FE_HAS_LOCK)) { 697 ret = -EAGAIN; 698 goto err; 699 } 700 701 switch (c->delivery_system) { 702 case SYS_DVBS: 703 ret = m88ds3103_rd_reg(priv, 0xe0, &buf[0]); 704 if (ret) 705 goto err; 706 707 ret = m88ds3103_rd_reg(priv, 0xe6, &buf[1]); 708 if (ret) 709 goto err; 710 711 switch ((buf[0] >> 2) & 0x01) { 712 case 0: 713 c->inversion = INVERSION_OFF; 714 break; 715 case 1: 716 c->inversion = INVERSION_ON; 717 break; 718 default: 719 dev_dbg(&priv->i2c->dev, "%s: invalid inversion\n", 720 __func__); 721 } 722 723 switch ((buf[1] >> 5) & 0x07) { 724 case 0: 725 c->fec_inner = FEC_7_8; 726 break; 727 case 1: 728 c->fec_inner = FEC_5_6; 729 break; 730 case 2: 731 c->fec_inner = FEC_3_4; 732 break; 733 case 3: 734 c->fec_inner = FEC_2_3; 735 break; 736 case 4: 737 c->fec_inner = FEC_1_2; 738 break; 739 default: 740 dev_dbg(&priv->i2c->dev, "%s: invalid fec_inner\n", 741 __func__); 742 } 743 744 c->modulation = QPSK; 745 746 break; 747 case SYS_DVBS2: 748 ret = m88ds3103_rd_reg(priv, 0x7e, &buf[0]); 749 if (ret) 750 goto err; 751 752 ret = m88ds3103_rd_reg(priv, 0x89, &buf[1]); 753 if (ret) 754 goto err; 755 756 ret = m88ds3103_rd_reg(priv, 0xf2, &buf[2]); 757 if (ret) 758 goto err; 759 760 switch ((buf[0] >> 0) & 0x0f) { 761 case 2: 762 c->fec_inner = FEC_2_5; 763 break; 764 case 3: 765 c->fec_inner = FEC_1_2; 766 break; 767 case 4: 768 c->fec_inner = FEC_3_5; 769 break; 770 case 5: 771 c->fec_inner = FEC_2_3; 772 break; 773 case 6: 774 c->fec_inner = FEC_3_4; 775 break; 776 case 7: 777 c->fec_inner = FEC_4_5; 778 break; 779 case 8: 780 c->fec_inner = FEC_5_6; 781 break; 782 case 9: 783 c->fec_inner = FEC_8_9; 784 break; 785 case 10: 786 c->fec_inner = FEC_9_10; 787 break; 788 default: 789 dev_dbg(&priv->i2c->dev, "%s: invalid fec_inner\n", 790 __func__); 791 } 792 793 switch ((buf[0] >> 5) & 0x01) { 794 case 0: 795 c->pilot = PILOT_OFF; 796 break; 797 case 1: 798 c->pilot = PILOT_ON; 799 break; 800 default: 801 dev_dbg(&priv->i2c->dev, "%s: invalid pilot\n", 802 __func__); 803 } 804 805 switch ((buf[0] >> 6) & 0x07) { 806 case 0: 807 c->modulation = QPSK; 808 break; 809 case 1: 810 c->modulation = PSK_8; 811 break; 812 case 2: 813 c->modulation = APSK_16; 814 break; 815 case 3: 816 c->modulation = APSK_32; 817 break; 818 default: 819 dev_dbg(&priv->i2c->dev, "%s: invalid modulation\n", 820 __func__); 821 } 822 823 switch ((buf[1] >> 7) & 0x01) { 824 case 0: 825 c->inversion = INVERSION_OFF; 826 break; 827 case 1: 828 c->inversion = INVERSION_ON; 829 break; 830 default: 831 dev_dbg(&priv->i2c->dev, "%s: invalid inversion\n", 832 __func__); 833 } 834 835 switch ((buf[2] >> 0) & 0x03) { 836 case 0: 837 c->rolloff = ROLLOFF_35; 838 break; 839 case 1: 840 c->rolloff = ROLLOFF_25; 841 break; 842 case 2: 843 c->rolloff = ROLLOFF_20; 844 break; 845 default: 846 dev_dbg(&priv->i2c->dev, "%s: invalid rolloff\n", 847 __func__); 848 } 849 break; 850 default: 851 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n", 852 __func__); 853 ret = -EINVAL; 854 goto err; 855 } 856 857 ret = m88ds3103_rd_regs(priv, 0x6d, buf, 2); 858 if (ret) 859 goto err; 860 861 c->symbol_rate = 1ull * ((buf[1] << 8) | (buf[0] << 0)) * 862 M88DS3103_MCLK_KHZ * 1000 / 0x10000; 863 864 return 0; 865 err: 866 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); 867 return ret; 868 } 869 870 static int m88ds3103_read_snr(struct dvb_frontend *fe, u16 *snr) 871 { 872 struct m88ds3103_priv *priv = fe->demodulator_priv; 873 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 874 int ret, i, tmp; 875 u8 buf[3]; 876 u16 noise, signal; 877 u32 noise_tot, signal_tot; 878 dev_dbg(&priv->i2c->dev, "%s:\n", __func__); 879 /* reports SNR in resolution of 0.1 dB */ 880 881 /* more iterations for more accurate estimation */ 882 #define M88DS3103_SNR_ITERATIONS 3 883 884 switch (c->delivery_system) { 885 case SYS_DVBS: 886 tmp = 0; 887 888 for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) { 889 ret = m88ds3103_rd_reg(priv, 0xff, &buf[0]); 890 if (ret) 891 goto err; 892 893 tmp += buf[0]; 894 } 895 896 /* use of one register limits max value to 15 dB */ 897 /* SNR(X) dB = 10 * ln(X) / ln(10) dB */ 898 tmp = DIV_ROUND_CLOSEST(tmp, 8 * M88DS3103_SNR_ITERATIONS); 899 if (tmp) 900 *snr = 100ul * intlog2(tmp) / intlog2(10); 901 else 902 *snr = 0; 903 break; 904 case SYS_DVBS2: 905 noise_tot = 0; 906 signal_tot = 0; 907 908 for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) { 909 ret = m88ds3103_rd_regs(priv, 0x8c, buf, 3); 910 if (ret) 911 goto err; 912 913 noise = buf[1] << 6; /* [13:6] */ 914 noise |= buf[0] & 0x3f; /* [5:0] */ 915 noise >>= 2; 916 signal = buf[2] * buf[2]; 917 signal >>= 1; 918 919 noise_tot += noise; 920 signal_tot += signal; 921 } 922 923 noise = noise_tot / M88DS3103_SNR_ITERATIONS; 924 signal = signal_tot / M88DS3103_SNR_ITERATIONS; 925 926 /* SNR(X) dB = 10 * log10(X) dB */ 927 if (signal > noise) { 928 tmp = signal / noise; 929 *snr = 100ul * intlog10(tmp) / (1 << 24); 930 } else 931 *snr = 0; 932 break; 933 default: 934 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n", 935 __func__); 936 ret = -EINVAL; 937 goto err; 938 } 939 940 return 0; 941 err: 942 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); 943 return ret; 944 } 945 946 947 static int m88ds3103_set_tone(struct dvb_frontend *fe, 948 fe_sec_tone_mode_t fe_sec_tone_mode) 949 { 950 struct m88ds3103_priv *priv = fe->demodulator_priv; 951 int ret; 952 u8 u8tmp, tone, reg_a1_mask; 953 dev_dbg(&priv->i2c->dev, "%s: fe_sec_tone_mode=%d\n", __func__, 954 fe_sec_tone_mode); 955 956 if (!priv->warm) { 957 ret = -EAGAIN; 958 goto err; 959 } 960 961 switch (fe_sec_tone_mode) { 962 case SEC_TONE_ON: 963 tone = 0; 964 reg_a1_mask = 0x87; 965 break; 966 case SEC_TONE_OFF: 967 tone = 1; 968 reg_a1_mask = 0x00; 969 break; 970 default: 971 dev_dbg(&priv->i2c->dev, "%s: invalid fe_sec_tone_mode\n", 972 __func__); 973 ret = -EINVAL; 974 goto err; 975 } 976 977 u8tmp = tone << 7 | priv->cfg->envelope_mode << 5; 978 ret = m88ds3103_wr_reg_mask(priv, 0xa2, u8tmp, 0xe0); 979 if (ret) 980 goto err; 981 982 u8tmp = 1 << 2; 983 ret = m88ds3103_wr_reg_mask(priv, 0xa1, u8tmp, reg_a1_mask); 984 if (ret) 985 goto err; 986 987 return 0; 988 err: 989 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); 990 return ret; 991 } 992 993 static int m88ds3103_diseqc_send_master_cmd(struct dvb_frontend *fe, 994 struct dvb_diseqc_master_cmd *diseqc_cmd) 995 { 996 struct m88ds3103_priv *priv = fe->demodulator_priv; 997 int ret, i; 998 u8 u8tmp; 999 dev_dbg(&priv->i2c->dev, "%s: msg=%*ph\n", __func__, 1000 diseqc_cmd->msg_len, diseqc_cmd->msg); 1001 1002 if (!priv->warm) { 1003 ret = -EAGAIN; 1004 goto err; 1005 } 1006 1007 if (diseqc_cmd->msg_len < 3 || diseqc_cmd->msg_len > 6) { 1008 ret = -EINVAL; 1009 goto err; 1010 } 1011 1012 u8tmp = priv->cfg->envelope_mode << 5; 1013 ret = m88ds3103_wr_reg_mask(priv, 0xa2, u8tmp, 0xe0); 1014 if (ret) 1015 goto err; 1016 1017 ret = m88ds3103_wr_regs(priv, 0xa3, diseqc_cmd->msg, 1018 diseqc_cmd->msg_len); 1019 if (ret) 1020 goto err; 1021 1022 ret = m88ds3103_wr_reg(priv, 0xa1, 1023 (diseqc_cmd->msg_len - 1) << 3 | 0x07); 1024 if (ret) 1025 goto err; 1026 1027 /* DiSEqC message typical period is 54 ms */ 1028 usleep_range(40000, 60000); 1029 1030 /* wait DiSEqC TX ready */ 1031 for (i = 20, u8tmp = 1; i && u8tmp; i--) { 1032 usleep_range(5000, 10000); 1033 1034 ret = m88ds3103_rd_reg_mask(priv, 0xa1, &u8tmp, 0x40); 1035 if (ret) 1036 goto err; 1037 } 1038 1039 dev_dbg(&priv->i2c->dev, "%s: loop=%d\n", __func__, i); 1040 1041 if (i == 0) { 1042 dev_dbg(&priv->i2c->dev, "%s: diseqc tx timeout\n", __func__); 1043 1044 ret = m88ds3103_wr_reg_mask(priv, 0xa1, 0x40, 0xc0); 1045 if (ret) 1046 goto err; 1047 } 1048 1049 ret = m88ds3103_wr_reg_mask(priv, 0xa2, 0x80, 0xc0); 1050 if (ret) 1051 goto err; 1052 1053 if (i == 0) { 1054 ret = -ETIMEDOUT; 1055 goto err; 1056 } 1057 1058 return 0; 1059 err: 1060 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); 1061 return ret; 1062 } 1063 1064 static int m88ds3103_diseqc_send_burst(struct dvb_frontend *fe, 1065 fe_sec_mini_cmd_t fe_sec_mini_cmd) 1066 { 1067 struct m88ds3103_priv *priv = fe->demodulator_priv; 1068 int ret, i; 1069 u8 u8tmp, burst; 1070 dev_dbg(&priv->i2c->dev, "%s: fe_sec_mini_cmd=%d\n", __func__, 1071 fe_sec_mini_cmd); 1072 1073 if (!priv->warm) { 1074 ret = -EAGAIN; 1075 goto err; 1076 } 1077 1078 u8tmp = priv->cfg->envelope_mode << 5; 1079 ret = m88ds3103_wr_reg_mask(priv, 0xa2, u8tmp, 0xe0); 1080 if (ret) 1081 goto err; 1082 1083 switch (fe_sec_mini_cmd) { 1084 case SEC_MINI_A: 1085 burst = 0x02; 1086 break; 1087 case SEC_MINI_B: 1088 burst = 0x01; 1089 break; 1090 default: 1091 dev_dbg(&priv->i2c->dev, "%s: invalid fe_sec_mini_cmd\n", 1092 __func__); 1093 ret = -EINVAL; 1094 goto err; 1095 } 1096 1097 ret = m88ds3103_wr_reg(priv, 0xa1, burst); 1098 if (ret) 1099 goto err; 1100 1101 /* DiSEqC ToneBurst period is 12.5 ms */ 1102 usleep_range(11000, 20000); 1103 1104 /* wait DiSEqC TX ready */ 1105 for (i = 5, u8tmp = 1; i && u8tmp; i--) { 1106 usleep_range(800, 2000); 1107 1108 ret = m88ds3103_rd_reg_mask(priv, 0xa1, &u8tmp, 0x40); 1109 if (ret) 1110 goto err; 1111 } 1112 1113 dev_dbg(&priv->i2c->dev, "%s: loop=%d\n", __func__, i); 1114 1115 ret = m88ds3103_wr_reg_mask(priv, 0xa2, 0x80, 0xc0); 1116 if (ret) 1117 goto err; 1118 1119 if (i == 0) { 1120 dev_dbg(&priv->i2c->dev, "%s: diseqc tx timeout\n", __func__); 1121 ret = -ETIMEDOUT; 1122 goto err; 1123 } 1124 1125 return 0; 1126 err: 1127 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); 1128 return ret; 1129 } 1130 1131 static int m88ds3103_get_tune_settings(struct dvb_frontend *fe, 1132 struct dvb_frontend_tune_settings *s) 1133 { 1134 s->min_delay_ms = 3000; 1135 1136 return 0; 1137 } 1138 1139 static void m88ds3103_release(struct dvb_frontend *fe) 1140 { 1141 struct m88ds3103_priv *priv = fe->demodulator_priv; 1142 i2c_del_mux_adapter(priv->i2c_adapter); 1143 kfree(priv); 1144 } 1145 1146 static int m88ds3103_select(struct i2c_adapter *adap, void *mux_priv, u32 chan) 1147 { 1148 struct m88ds3103_priv *priv = mux_priv; 1149 int ret; 1150 struct i2c_msg gate_open_msg[1] = { 1151 { 1152 .addr = priv->cfg->i2c_addr, 1153 .flags = 0, 1154 .len = 2, 1155 .buf = "\x03\x11", 1156 } 1157 }; 1158 1159 mutex_lock(&priv->i2c_mutex); 1160 1161 /* open tuner I2C repeater for 1 xfer, closes automatically */ 1162 ret = i2c_transfer(priv->i2c, gate_open_msg, 1); 1163 if (ret != 1) { 1164 dev_warn(&priv->i2c->dev, "%s: i2c wr failed=%d\n", 1165 KBUILD_MODNAME, ret); 1166 if (ret >= 0) 1167 ret = -EREMOTEIO; 1168 1169 return ret; 1170 } 1171 1172 return 0; 1173 } 1174 1175 static int m88ds3103_deselect(struct i2c_adapter *adap, void *mux_priv, 1176 u32 chan) 1177 { 1178 struct m88ds3103_priv *priv = mux_priv; 1179 1180 mutex_unlock(&priv->i2c_mutex); 1181 1182 return 0; 1183 } 1184 1185 struct dvb_frontend *m88ds3103_attach(const struct m88ds3103_config *cfg, 1186 struct i2c_adapter *i2c, struct i2c_adapter **tuner_i2c_adapter) 1187 { 1188 int ret; 1189 struct m88ds3103_priv *priv; 1190 u8 chip_id, u8tmp; 1191 1192 /* allocate memory for the internal priv */ 1193 priv = kzalloc(sizeof(struct m88ds3103_priv), GFP_KERNEL); 1194 if (!priv) { 1195 ret = -ENOMEM; 1196 dev_err(&i2c->dev, "%s: kzalloc() failed\n", KBUILD_MODNAME); 1197 goto err; 1198 } 1199 1200 priv->cfg = cfg; 1201 priv->i2c = i2c; 1202 mutex_init(&priv->i2c_mutex); 1203 1204 ret = m88ds3103_rd_reg(priv, 0x01, &chip_id); 1205 if (ret) 1206 goto err; 1207 1208 dev_dbg(&priv->i2c->dev, "%s: chip_id=%02x\n", __func__, chip_id); 1209 1210 switch (chip_id) { 1211 case 0xd0: 1212 break; 1213 default: 1214 goto err; 1215 } 1216 1217 switch (priv->cfg->clock_out) { 1218 case M88DS3103_CLOCK_OUT_DISABLED: 1219 u8tmp = 0x80; 1220 break; 1221 case M88DS3103_CLOCK_OUT_ENABLED: 1222 u8tmp = 0x00; 1223 break; 1224 case M88DS3103_CLOCK_OUT_ENABLED_DIV2: 1225 u8tmp = 0x10; 1226 break; 1227 default: 1228 goto err; 1229 } 1230 1231 ret = m88ds3103_wr_reg(priv, 0x29, u8tmp); 1232 if (ret) 1233 goto err; 1234 1235 /* sleep */ 1236 ret = m88ds3103_wr_reg_mask(priv, 0x08, 0x00, 0x01); 1237 if (ret) 1238 goto err; 1239 1240 ret = m88ds3103_wr_reg_mask(priv, 0x04, 0x01, 0x01); 1241 if (ret) 1242 goto err; 1243 1244 ret = m88ds3103_wr_reg_mask(priv, 0x23, 0x10, 0x10); 1245 if (ret) 1246 goto err; 1247 1248 /* create mux i2c adapter for tuner */ 1249 priv->i2c_adapter = i2c_add_mux_adapter(i2c, &i2c->dev, priv, 0, 0, 0, 1250 m88ds3103_select, m88ds3103_deselect); 1251 if (priv->i2c_adapter == NULL) 1252 goto err; 1253 1254 *tuner_i2c_adapter = priv->i2c_adapter; 1255 1256 /* create dvb_frontend */ 1257 memcpy(&priv->fe.ops, &m88ds3103_ops, sizeof(struct dvb_frontend_ops)); 1258 priv->fe.demodulator_priv = priv; 1259 1260 return &priv->fe; 1261 err: 1262 dev_dbg(&i2c->dev, "%s: failed=%d\n", __func__, ret); 1263 kfree(priv); 1264 return NULL; 1265 } 1266 EXPORT_SYMBOL(m88ds3103_attach); 1267 1268 static struct dvb_frontend_ops m88ds3103_ops = { 1269 .delsys = { SYS_DVBS, SYS_DVBS2 }, 1270 .info = { 1271 .name = "Montage M88DS3103", 1272 .frequency_min = 950000, 1273 .frequency_max = 2150000, 1274 .frequency_tolerance = 5000, 1275 .symbol_rate_min = 1000000, 1276 .symbol_rate_max = 45000000, 1277 .caps = FE_CAN_INVERSION_AUTO | 1278 FE_CAN_FEC_1_2 | 1279 FE_CAN_FEC_2_3 | 1280 FE_CAN_FEC_3_4 | 1281 FE_CAN_FEC_4_5 | 1282 FE_CAN_FEC_5_6 | 1283 FE_CAN_FEC_6_7 | 1284 FE_CAN_FEC_7_8 | 1285 FE_CAN_FEC_8_9 | 1286 FE_CAN_FEC_AUTO | 1287 FE_CAN_QPSK | 1288 FE_CAN_RECOVER | 1289 FE_CAN_2G_MODULATION 1290 }, 1291 1292 .release = m88ds3103_release, 1293 1294 .get_tune_settings = m88ds3103_get_tune_settings, 1295 1296 .init = m88ds3103_init, 1297 .sleep = m88ds3103_sleep, 1298 1299 .set_frontend = m88ds3103_set_frontend, 1300 .get_frontend = m88ds3103_get_frontend, 1301 1302 .read_status = m88ds3103_read_status, 1303 .read_snr = m88ds3103_read_snr, 1304 1305 .diseqc_send_master_cmd = m88ds3103_diseqc_send_master_cmd, 1306 .diseqc_send_burst = m88ds3103_diseqc_send_burst, 1307 1308 .set_tone = m88ds3103_set_tone, 1309 }; 1310 1311 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>"); 1312 MODULE_DESCRIPTION("Montage M88DS3103 DVB-S/S2 demodulator driver"); 1313 MODULE_LICENSE("GPL"); 1314 MODULE_FIRMWARE(M88DS3103_FIRMWARE); 1315