1*b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 23764e82eSJohannes Thumshirn #ifndef __MCB_INTERNAL 33764e82eSJohannes Thumshirn #define __MCB_INTERNAL 43764e82eSJohannes Thumshirn 53764e82eSJohannes Thumshirn #include <linux/types.h> 63764e82eSJohannes Thumshirn 7b71bb863SJohannes Thumshirn #define PCI_VENDOR_ID_MEN 0x1a88 8b71bb863SJohannes Thumshirn #define PCI_DEVICE_ID_MEN_CHAMELEON 0x4d45 93764e82eSJohannes Thumshirn #define CHAMELEONV2_MAGIC 0xabce 107b7c5491SJohannes Thumshirn #define CHAM_HEADER_SIZE 0x200 113764e82eSJohannes Thumshirn 123764e82eSJohannes Thumshirn enum chameleon_descriptor_type { 133764e82eSJohannes Thumshirn CHAMELEON_DTYPE_GENERAL = 0x0, 143764e82eSJohannes Thumshirn CHAMELEON_DTYPE_BRIDGE = 0x1, 153764e82eSJohannes Thumshirn CHAMELEON_DTYPE_CPU = 0x2, 163764e82eSJohannes Thumshirn CHAMELEON_DTYPE_BAR = 0x3, 173764e82eSJohannes Thumshirn CHAMELEON_DTYPE_END = 0xf, 183764e82eSJohannes Thumshirn }; 193764e82eSJohannes Thumshirn 203764e82eSJohannes Thumshirn enum chameleon_bus_type { 213764e82eSJohannes Thumshirn CHAMELEON_BUS_WISHBONE, 223764e82eSJohannes Thumshirn CHAMELEON_BUS_AVALON, 233764e82eSJohannes Thumshirn CHAMELEON_BUS_LPC, 243764e82eSJohannes Thumshirn CHAMELEON_BUS_ISA, 253764e82eSJohannes Thumshirn }; 263764e82eSJohannes Thumshirn 273764e82eSJohannes Thumshirn /** 283764e82eSJohannes Thumshirn * struct chameleon_fpga_header 293764e82eSJohannes Thumshirn * 303764e82eSJohannes Thumshirn * @revision: Revison of Chameleon table in FPGA 313764e82eSJohannes Thumshirn * @model: Chameleon table model ASCII char 323764e82eSJohannes Thumshirn * @minor: Revision minor 333764e82eSJohannes Thumshirn * @bus_type: Bus type (usually %CHAMELEON_BUS_WISHBONE) 343764e82eSJohannes Thumshirn * @magic: Chameleon header magic number (0xabce for version 2) 353764e82eSJohannes Thumshirn * @reserved: Reserved 363764e82eSJohannes Thumshirn * @filename: Filename of FPGA bitstream 373764e82eSJohannes Thumshirn */ 383764e82eSJohannes Thumshirn struct chameleon_fpga_header { 393764e82eSJohannes Thumshirn u8 revision; 403764e82eSJohannes Thumshirn char model; 413764e82eSJohannes Thumshirn u8 minor; 423764e82eSJohannes Thumshirn u8 bus_type; 433764e82eSJohannes Thumshirn u16 magic; 443764e82eSJohannes Thumshirn u16 reserved; 453764e82eSJohannes Thumshirn /* This one has no '\0' at the end!!! */ 463764e82eSJohannes Thumshirn char filename[CHAMELEON_FILENAME_LEN]; 473764e82eSJohannes Thumshirn } __packed; 483764e82eSJohannes Thumshirn #define HEADER_MAGIC_OFFSET 0x4 493764e82eSJohannes Thumshirn 503764e82eSJohannes Thumshirn /** 513764e82eSJohannes Thumshirn * struct chameleon_gdd - Chameleon General Device Descriptor 523764e82eSJohannes Thumshirn * 533764e82eSJohannes Thumshirn * @irq: the position in the FPGA's IRQ controller vector 543764e82eSJohannes Thumshirn * @rev: the revision of the variant's implementation 553764e82eSJohannes Thumshirn * @var: the variant of the IP core 563764e82eSJohannes Thumshirn * @dev: the device the IP core is 573764e82eSJohannes Thumshirn * @dtype: device descriptor type 583764e82eSJohannes Thumshirn * @bar: BAR offset that must be added to module offset 593764e82eSJohannes Thumshirn * @inst: the instance number of the device, 0 is first instance 603764e82eSJohannes Thumshirn * @group: the group the device belongs to (0 = no group) 613764e82eSJohannes Thumshirn * @reserved: reserved 623764e82eSJohannes Thumshirn * @offset: beginning of the address window of desired module 633764e82eSJohannes Thumshirn * @size: size of the module's address window 643764e82eSJohannes Thumshirn */ 653764e82eSJohannes Thumshirn struct chameleon_gdd { 663764e82eSJohannes Thumshirn __le32 reg1; 673764e82eSJohannes Thumshirn __le32 reg2; 683764e82eSJohannes Thumshirn __le32 offset; 693764e82eSJohannes Thumshirn __le32 size; 703764e82eSJohannes Thumshirn 713764e82eSJohannes Thumshirn } __packed; 723764e82eSJohannes Thumshirn 733764e82eSJohannes Thumshirn /* GDD Register 1 fields */ 743764e82eSJohannes Thumshirn #define GDD_IRQ(x) ((x) & 0x1f) 753764e82eSJohannes Thumshirn #define GDD_REV(x) (((x) >> 5) & 0x3f) 763764e82eSJohannes Thumshirn #define GDD_VAR(x) (((x) >> 11) & 0x3f) 773764e82eSJohannes Thumshirn #define GDD_DEV(x) (((x) >> 18) & 0x3ff) 783764e82eSJohannes Thumshirn #define GDD_DTY(x) (((x) >> 28) & 0xf) 793764e82eSJohannes Thumshirn 803764e82eSJohannes Thumshirn /* GDD Register 2 fields */ 813764e82eSJohannes Thumshirn #define GDD_BAR(x) ((x) & 0x7) 823764e82eSJohannes Thumshirn #define GDD_INS(x) (((x) >> 3) & 0x3f) 833764e82eSJohannes Thumshirn #define GDD_GRP(x) (((x) >> 9) & 0x3f) 843764e82eSJohannes Thumshirn 853764e82eSJohannes Thumshirn /** 863764e82eSJohannes Thumshirn * struct chameleon_bdd - Chameleon Bridge Device Descriptor 873764e82eSJohannes Thumshirn * 883764e82eSJohannes Thumshirn * @irq: the position in the FPGA's IRQ controller vector 893764e82eSJohannes Thumshirn * @rev: the revision of the variant's implementation 903764e82eSJohannes Thumshirn * @var: the variant of the IP core 913764e82eSJohannes Thumshirn * @dev: the device the IP core is 923764e82eSJohannes Thumshirn * @dtype: device descriptor type 933764e82eSJohannes Thumshirn * @bar: BAR offset that must be added to module offset 943764e82eSJohannes Thumshirn * @inst: the instance number of the device, 0 is first instance 953764e82eSJohannes Thumshirn * @dbar: destination bar from the bus _behind_ the bridge 963764e82eSJohannes Thumshirn * @chamoff: offset within the BAR of the source bus 973764e82eSJohannes Thumshirn * @offset: 983764e82eSJohannes Thumshirn * @size: 993764e82eSJohannes Thumshirn */ 1003764e82eSJohannes Thumshirn struct chameleon_bdd { 1013764e82eSJohannes Thumshirn unsigned int irq:6; 1023764e82eSJohannes Thumshirn unsigned int rev:6; 1033764e82eSJohannes Thumshirn unsigned int var:6; 1043764e82eSJohannes Thumshirn unsigned int dev:10; 1053764e82eSJohannes Thumshirn unsigned int dtype:4; 1063764e82eSJohannes Thumshirn unsigned int bar:3; 1073764e82eSJohannes Thumshirn unsigned int inst:6; 1083764e82eSJohannes Thumshirn unsigned int dbar:3; 1093764e82eSJohannes Thumshirn unsigned int group:6; 1103764e82eSJohannes Thumshirn unsigned int reserved:14; 1113764e82eSJohannes Thumshirn u32 chamoff; 1123764e82eSJohannes Thumshirn u32 offset; 1133764e82eSJohannes Thumshirn u32 size; 1143764e82eSJohannes Thumshirn } __packed; 1153764e82eSJohannes Thumshirn 116ffc7bb38SAndreas Werner struct chameleon_bar { 117ffc7bb38SAndreas Werner u32 addr; 118ffc7bb38SAndreas Werner u32 size; 119ffc7bb38SAndreas Werner }; 120ffc7bb38SAndreas Werner 121ffc7bb38SAndreas Werner #define BAR_CNT(x) ((x) & 0x07) 122ffc7bb38SAndreas Werner #define CHAMELEON_BAR_MAX 6 123ffc7bb38SAndreas Werner #define BAR_DESC_SIZE(x) ((x) * sizeof(struct chameleon_bar) + sizeof(__le32)) 124ffc7bb38SAndreas Werner 1253764e82eSJohannes Thumshirn int chameleon_parse_cells(struct mcb_bus *bus, phys_addr_t mapbase, 1263764e82eSJohannes Thumshirn void __iomem *base); 1273764e82eSJohannes Thumshirn 1283764e82eSJohannes Thumshirn #endif 129