1 /* 2 * NETJet mISDN driver 3 * 4 * Author Karsten Keil <keil@isdn4linux.de> 5 * 6 * Copyright 2009 by Karsten Keil <keil@isdn4linux.de> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 * 21 */ 22 23 #include <linux/interrupt.h> 24 #include <linux/module.h> 25 #include <linux/pci.h> 26 #include <linux/delay.h> 27 #include <linux/mISDNhw.h> 28 #include <linux/slab.h> 29 #include "ipac.h" 30 #include "iohelper.h" 31 #include "netjet.h" 32 #include <linux/isdn/hdlc.h> 33 34 #define NETJET_REV "2.0" 35 36 enum nj_types { 37 NETJET_S_TJ300, 38 NETJET_S_TJ320, 39 ENTERNOW__TJ320, 40 }; 41 42 struct tiger_dma { 43 size_t size; 44 u32 *start; 45 int idx; 46 u32 dmastart; 47 u32 dmairq; 48 u32 dmaend; 49 u32 dmacur; 50 }; 51 52 struct tiger_hw; 53 54 struct tiger_ch { 55 struct bchannel bch; 56 struct tiger_hw *nj; 57 int idx; 58 int free; 59 int lastrx; 60 u16 rxstate; 61 u16 txstate; 62 struct isdnhdlc_vars hsend; 63 struct isdnhdlc_vars hrecv; 64 u8 *hsbuf; 65 u8 *hrbuf; 66 }; 67 68 #define TX_INIT 0x0001 69 #define TX_IDLE 0x0002 70 #define TX_RUN 0x0004 71 #define TX_UNDERRUN 0x0100 72 #define RX_OVERRUN 0x0100 73 74 #define LOG_SIZE 64 75 76 struct tiger_hw { 77 struct list_head list; 78 struct pci_dev *pdev; 79 char name[MISDN_MAX_IDLEN]; 80 enum nj_types typ; 81 int irq; 82 u32 irqcnt; 83 u32 base; 84 size_t base_s; 85 dma_addr_t dma; 86 void *dma_p; 87 spinlock_t lock; /* lock HW */ 88 struct isac_hw isac; 89 struct tiger_dma send; 90 struct tiger_dma recv; 91 struct tiger_ch bc[2]; 92 u8 ctrlreg; 93 u8 dmactrl; 94 u8 auxd; 95 u8 last_is0; 96 u8 irqmask0; 97 char log[LOG_SIZE]; 98 }; 99 100 static LIST_HEAD(Cards); 101 static DEFINE_RWLOCK(card_lock); /* protect Cards */ 102 static u32 debug; 103 static int nj_cnt; 104 105 static void 106 _set_debug(struct tiger_hw *card) 107 { 108 card->isac.dch.debug = debug; 109 card->bc[0].bch.debug = debug; 110 card->bc[1].bch.debug = debug; 111 } 112 113 static int 114 set_debug(const char *val, struct kernel_param *kp) 115 { 116 int ret; 117 struct tiger_hw *card; 118 119 ret = param_set_uint(val, kp); 120 if (!ret) { 121 read_lock(&card_lock); 122 list_for_each_entry(card, &Cards, list) 123 _set_debug(card); 124 read_unlock(&card_lock); 125 } 126 return ret; 127 } 128 129 MODULE_AUTHOR("Karsten Keil"); 130 MODULE_LICENSE("GPL v2"); 131 MODULE_VERSION(NETJET_REV); 132 module_param_call(debug, set_debug, param_get_uint, &debug, S_IRUGO | S_IWUSR); 133 MODULE_PARM_DESC(debug, "Netjet debug mask"); 134 135 static void 136 nj_disable_hwirq(struct tiger_hw *card) 137 { 138 outb(0, card->base + NJ_IRQMASK0); 139 outb(0, card->base + NJ_IRQMASK1); 140 } 141 142 143 static u8 144 ReadISAC_nj(void *p, u8 offset) 145 { 146 struct tiger_hw *card = p; 147 u8 ret; 148 149 card->auxd &= 0xfc; 150 card->auxd |= (offset >> 4) & 3; 151 outb(card->auxd, card->base + NJ_AUXDATA); 152 ret = inb(card->base + NJ_ISAC_OFF + ((offset & 0x0f) << 2)); 153 return ret; 154 } 155 156 static void 157 WriteISAC_nj(void *p, u8 offset, u8 value) 158 { 159 struct tiger_hw *card = p; 160 161 card->auxd &= 0xfc; 162 card->auxd |= (offset >> 4) & 3; 163 outb(card->auxd, card->base + NJ_AUXDATA); 164 outb(value, card->base + NJ_ISAC_OFF + ((offset & 0x0f) << 2)); 165 } 166 167 static void 168 ReadFiFoISAC_nj(void *p, u8 offset, u8 *data, int size) 169 { 170 struct tiger_hw *card = p; 171 172 card->auxd &= 0xfc; 173 outb(card->auxd, card->base + NJ_AUXDATA); 174 insb(card->base + NJ_ISAC_OFF, data, size); 175 } 176 177 static void 178 WriteFiFoISAC_nj(void *p, u8 offset, u8 *data, int size) 179 { 180 struct tiger_hw *card = p; 181 182 card->auxd &= 0xfc; 183 outb(card->auxd, card->base + NJ_AUXDATA); 184 outsb(card->base + NJ_ISAC_OFF, data, size); 185 } 186 187 static void 188 fill_mem(struct tiger_ch *bc, u32 idx, u32 cnt, u32 fill) 189 { 190 struct tiger_hw *card = bc->bch.hw; 191 u32 mask = 0xff, val; 192 193 pr_debug("%s: B%1d fill %02x len %d idx %d/%d\n", card->name, 194 bc->bch.nr, fill, cnt, idx, card->send.idx); 195 if (bc->bch.nr & 2) { 196 fill <<= 8; 197 mask <<= 8; 198 } 199 mask ^= 0xffffffff; 200 while (cnt--) { 201 val = card->send.start[idx]; 202 val &= mask; 203 val |= fill; 204 card->send.start[idx++] = val; 205 if (idx >= card->send.size) 206 idx = 0; 207 } 208 } 209 210 static int 211 mode_tiger(struct tiger_ch *bc, u32 protocol) 212 { 213 struct tiger_hw *card = bc->bch.hw; 214 215 pr_debug("%s: B%1d protocol %x-->%x\n", card->name, 216 bc->bch.nr, bc->bch.state, protocol); 217 switch (protocol) { 218 case ISDN_P_NONE: 219 if (bc->bch.state == ISDN_P_NONE) 220 break; 221 fill_mem(bc, 0, card->send.size, 0xff); 222 bc->bch.state = protocol; 223 /* only stop dma and interrupts if both channels NULL */ 224 if ((card->bc[0].bch.state == ISDN_P_NONE) && 225 (card->bc[1].bch.state == ISDN_P_NONE)) { 226 card->dmactrl = 0; 227 outb(card->dmactrl, card->base + NJ_DMACTRL); 228 outb(0, card->base + NJ_IRQMASK0); 229 } 230 test_and_clear_bit(FLG_HDLC, &bc->bch.Flags); 231 test_and_clear_bit(FLG_TRANSPARENT, &bc->bch.Flags); 232 bc->txstate = 0; 233 bc->rxstate = 0; 234 bc->lastrx = -1; 235 break; 236 case ISDN_P_B_RAW: 237 test_and_set_bit(FLG_TRANSPARENT, &bc->bch.Flags); 238 bc->bch.state = protocol; 239 bc->idx = 0; 240 bc->free = card->send.size / 2; 241 bc->rxstate = 0; 242 bc->txstate = TX_INIT | TX_IDLE; 243 bc->lastrx = -1; 244 if (!card->dmactrl) { 245 card->dmactrl = 1; 246 outb(card->dmactrl, card->base + NJ_DMACTRL); 247 outb(0x0f, card->base + NJ_IRQMASK0); 248 } 249 break; 250 case ISDN_P_B_HDLC: 251 test_and_set_bit(FLG_HDLC, &bc->bch.Flags); 252 bc->bch.state = protocol; 253 bc->idx = 0; 254 bc->free = card->send.size / 2; 255 bc->rxstate = 0; 256 bc->txstate = TX_INIT | TX_IDLE; 257 isdnhdlc_rcv_init(&bc->hrecv, 0); 258 isdnhdlc_out_init(&bc->hsend, 0); 259 bc->lastrx = -1; 260 if (!card->dmactrl) { 261 card->dmactrl = 1; 262 outb(card->dmactrl, card->base + NJ_DMACTRL); 263 outb(0x0f, card->base + NJ_IRQMASK0); 264 } 265 break; 266 default: 267 pr_info("%s: %s protocol %x not handled\n", card->name, 268 __func__, protocol); 269 return -ENOPROTOOPT; 270 } 271 card->send.dmacur = inl(card->base + NJ_DMA_READ_ADR); 272 card->recv.dmacur = inl(card->base + NJ_DMA_WRITE_ADR); 273 card->send.idx = (card->send.dmacur - card->send.dmastart) >> 2; 274 card->recv.idx = (card->recv.dmacur - card->recv.dmastart) >> 2; 275 pr_debug("%s: %s ctrl %x irq %02x/%02x idx %d/%d\n", 276 card->name, __func__, 277 inb(card->base + NJ_DMACTRL), 278 inb(card->base + NJ_IRQMASK0), 279 inb(card->base + NJ_IRQSTAT0), 280 card->send.idx, 281 card->recv.idx); 282 return 0; 283 } 284 285 static void 286 nj_reset(struct tiger_hw *card) 287 { 288 outb(0xff, card->base + NJ_CTRL); /* Reset On */ 289 mdelay(1); 290 291 /* now edge triggered for TJ320 GE 13/07/00 */ 292 /* see comment in IRQ function */ 293 if (card->typ == NETJET_S_TJ320) /* TJ320 */ 294 card->ctrlreg = 0x40; /* Reset Off and status read clear */ 295 else 296 card->ctrlreg = 0x00; /* Reset Off and status read clear */ 297 outb(card->ctrlreg, card->base + NJ_CTRL); 298 mdelay(10); 299 300 /* configure AUX pins (all output except ISAC IRQ pin) */ 301 card->auxd = 0; 302 card->dmactrl = 0; 303 outb(~NJ_ISACIRQ, card->base + NJ_AUXCTRL); 304 outb(NJ_ISACIRQ, card->base + NJ_IRQMASK1); 305 outb(card->auxd, card->base + NJ_AUXDATA); 306 } 307 308 static int 309 inittiger(struct tiger_hw *card) 310 { 311 int i; 312 313 card->dma_p = pci_alloc_consistent(card->pdev, NJ_DMA_SIZE, 314 &card->dma); 315 if (!card->dma_p) { 316 pr_info("%s: No DMA memory\n", card->name); 317 return -ENOMEM; 318 } 319 if ((u64)card->dma > 0xffffffff) { 320 pr_info("%s: DMA outside 32 bit\n", card->name); 321 return -ENOMEM; 322 } 323 for (i = 0; i < 2; i++) { 324 card->bc[i].hsbuf = kmalloc(NJ_DMA_TXSIZE, GFP_ATOMIC); 325 if (!card->bc[i].hsbuf) { 326 pr_info("%s: no B%d send buffer\n", card->name, i + 1); 327 return -ENOMEM; 328 } 329 card->bc[i].hrbuf = kmalloc(NJ_DMA_RXSIZE, GFP_ATOMIC); 330 if (!card->bc[i].hrbuf) { 331 pr_info("%s: no B%d recv buffer\n", card->name, i + 1); 332 return -ENOMEM; 333 } 334 } 335 memset(card->dma_p, 0xff, NJ_DMA_SIZE); 336 337 card->send.start = card->dma_p; 338 card->send.dmastart = (u32)card->dma; 339 card->send.dmaend = card->send.dmastart + 340 (4 * (NJ_DMA_TXSIZE - 1)); 341 card->send.dmairq = card->send.dmastart + 342 (4 * ((NJ_DMA_TXSIZE / 2) - 1)); 343 card->send.size = NJ_DMA_TXSIZE; 344 345 if (debug & DEBUG_HW) 346 pr_notice("%s: send buffer phy %#x - %#x - %#x virt %p" 347 " size %zu u32\n", card->name, 348 card->send.dmastart, card->send.dmairq, 349 card->send.dmaend, card->send.start, card->send.size); 350 351 outl(card->send.dmastart, card->base + NJ_DMA_READ_START); 352 outl(card->send.dmairq, card->base + NJ_DMA_READ_IRQ); 353 outl(card->send.dmaend, card->base + NJ_DMA_READ_END); 354 355 card->recv.start = card->dma_p + (NJ_DMA_SIZE / 2); 356 card->recv.dmastart = (u32)card->dma + (NJ_DMA_SIZE / 2); 357 card->recv.dmaend = card->recv.dmastart + 358 (4 * (NJ_DMA_RXSIZE - 1)); 359 card->recv.dmairq = card->recv.dmastart + 360 (4 * ((NJ_DMA_RXSIZE / 2) - 1)); 361 card->recv.size = NJ_DMA_RXSIZE; 362 363 if (debug & DEBUG_HW) 364 pr_notice("%s: recv buffer phy %#x - %#x - %#x virt %p" 365 " size %zu u32\n", card->name, 366 card->recv.dmastart, card->recv.dmairq, 367 card->recv.dmaend, card->recv.start, card->recv.size); 368 369 outl(card->recv.dmastart, card->base + NJ_DMA_WRITE_START); 370 outl(card->recv.dmairq, card->base + NJ_DMA_WRITE_IRQ); 371 outl(card->recv.dmaend, card->base + NJ_DMA_WRITE_END); 372 return 0; 373 } 374 375 static void 376 read_dma(struct tiger_ch *bc, u32 idx, int cnt) 377 { 378 struct tiger_hw *card = bc->bch.hw; 379 int i, stat; 380 u32 val; 381 u8 *p, *pn; 382 383 if (bc->lastrx == idx) { 384 bc->rxstate |= RX_OVERRUN; 385 pr_info("%s: B%1d overrun at idx %d\n", card->name, 386 bc->bch.nr, idx); 387 } 388 bc->lastrx = idx; 389 stat = bchannel_get_rxbuf(&bc->bch, cnt); 390 /* only transparent use the count here, HDLC overun is detected later */ 391 if (stat == ENOMEM) { 392 pr_warning("%s.B%d: No memory for %d bytes\n", 393 card->name, bc->bch.nr, cnt); 394 return; 395 } 396 if (test_bit(FLG_TRANSPARENT, &bc->bch.Flags)) 397 p = skb_put(bc->bch.rx_skb, cnt); 398 else 399 p = bc->hrbuf; 400 401 for (i = 0; i < cnt; i++) { 402 val = card->recv.start[idx++]; 403 if (bc->bch.nr & 2) 404 val >>= 8; 405 if (idx >= card->recv.size) 406 idx = 0; 407 p[i] = val & 0xff; 408 } 409 410 if (test_bit(FLG_TRANSPARENT, &bc->bch.Flags)) { 411 recv_Bchannel(&bc->bch, 0); 412 return; 413 } 414 415 pn = bc->hrbuf; 416 while (cnt > 0) { 417 stat = isdnhdlc_decode(&bc->hrecv, pn, cnt, &i, 418 bc->bch.rx_skb->data, bc->bch.maxlen); 419 if (stat > 0) { /* valid frame received */ 420 p = skb_put(bc->bch.rx_skb, stat); 421 if (debug & DEBUG_HW_BFIFO) { 422 snprintf(card->log, LOG_SIZE, 423 "B%1d-recv %s %d ", bc->bch.nr, 424 card->name, stat); 425 print_hex_dump_bytes(card->log, 426 DUMP_PREFIX_OFFSET, p, 427 stat); 428 } 429 recv_Bchannel(&bc->bch, 0); 430 stat = bchannel_get_rxbuf(&bc->bch, bc->bch.maxlen); 431 if (stat < 0) { 432 pr_warning("%s.B%d: No memory for %d bytes\n", 433 card->name, bc->bch.nr, cnt); 434 return; 435 } 436 } else if (stat == -HDLC_CRC_ERROR) { 437 pr_info("%s: B%1d receive frame CRC error\n", 438 card->name, bc->bch.nr); 439 } else if (stat == -HDLC_FRAMING_ERROR) { 440 pr_info("%s: B%1d receive framing error\n", 441 card->name, bc->bch.nr); 442 } else if (stat == -HDLC_LENGTH_ERROR) { 443 pr_info("%s: B%1d receive frame too long (> %d)\n", 444 card->name, bc->bch.nr, bc->bch.maxlen); 445 } 446 pn += i; 447 cnt -= i; 448 } 449 } 450 451 static void 452 recv_tiger(struct tiger_hw *card, u8 irq_stat) 453 { 454 u32 idx; 455 int cnt = card->recv.size / 2; 456 457 /* Note receive is via the WRITE DMA channel */ 458 card->last_is0 &= ~NJ_IRQM0_WR_MASK; 459 card->last_is0 |= (irq_stat & NJ_IRQM0_WR_MASK); 460 461 if (irq_stat & NJ_IRQM0_WR_END) 462 idx = cnt - 1; 463 else 464 idx = card->recv.size - 1; 465 466 if (test_bit(FLG_ACTIVE, &card->bc[0].bch.Flags)) 467 read_dma(&card->bc[0], idx, cnt); 468 if (test_bit(FLG_ACTIVE, &card->bc[1].bch.Flags)) 469 read_dma(&card->bc[1], idx, cnt); 470 } 471 472 /* sync with current DMA address at start or after exception */ 473 static void 474 resync(struct tiger_ch *bc, struct tiger_hw *card) 475 { 476 card->send.dmacur = inl(card->base | NJ_DMA_READ_ADR); 477 card->send.idx = (card->send.dmacur - card->send.dmastart) >> 2; 478 if (bc->free > card->send.size / 2) 479 bc->free = card->send.size / 2; 480 /* currently we simple sync to the next complete free area 481 * this hast the advantage that we have always maximum time to 482 * handle TX irq 483 */ 484 if (card->send.idx < ((card->send.size / 2) - 1)) 485 bc->idx = (card->recv.size / 2) - 1; 486 else 487 bc->idx = card->recv.size - 1; 488 bc->txstate = TX_RUN; 489 pr_debug("%s: %s B%1d free %d idx %d/%d\n", card->name, 490 __func__, bc->bch.nr, bc->free, bc->idx, card->send.idx); 491 } 492 493 static int bc_next_frame(struct tiger_ch *); 494 495 static void 496 fill_hdlc_flag(struct tiger_ch *bc) 497 { 498 struct tiger_hw *card = bc->bch.hw; 499 int count, i; 500 u32 m, v; 501 u8 *p; 502 503 if (bc->free == 0) 504 return; 505 pr_debug("%s: %s B%1d %d state %x idx %d/%d\n", card->name, 506 __func__, bc->bch.nr, bc->free, bc->txstate, 507 bc->idx, card->send.idx); 508 if (bc->txstate & (TX_IDLE | TX_INIT | TX_UNDERRUN)) 509 resync(bc, card); 510 count = isdnhdlc_encode(&bc->hsend, NULL, 0, &i, 511 bc->hsbuf, bc->free); 512 pr_debug("%s: B%1d hdlc encoded %d flags\n", card->name, 513 bc->bch.nr, count); 514 bc->free -= count; 515 p = bc->hsbuf; 516 m = (bc->bch.nr & 1) ? 0xffffff00 : 0xffff00ff; 517 for (i = 0; i < count; i++) { 518 if (bc->idx >= card->send.size) 519 bc->idx = 0; 520 v = card->send.start[bc->idx]; 521 v &= m; 522 v |= (bc->bch.nr & 1) ? (u32)(p[i]) : ((u32)(p[i])) << 8; 523 card->send.start[bc->idx++] = v; 524 } 525 if (debug & DEBUG_HW_BFIFO) { 526 snprintf(card->log, LOG_SIZE, "B%1d-send %s %d ", 527 bc->bch.nr, card->name, count); 528 print_hex_dump_bytes(card->log, DUMP_PREFIX_OFFSET, p, count); 529 } 530 } 531 532 static void 533 fill_dma(struct tiger_ch *bc) 534 { 535 struct tiger_hw *card = bc->bch.hw; 536 int count, i; 537 u32 m, v; 538 u8 *p; 539 540 if (bc->free == 0) 541 return; 542 count = bc->bch.tx_skb->len - bc->bch.tx_idx; 543 if (count <= 0) 544 return; 545 pr_debug("%s: %s B%1d %d/%d/%d/%d state %x idx %d/%d\n", card->name, 546 __func__, bc->bch.nr, count, bc->free, bc->bch.tx_idx, 547 bc->bch.tx_skb->len, bc->txstate, bc->idx, card->send.idx); 548 if (bc->txstate & (TX_IDLE | TX_INIT | TX_UNDERRUN)) 549 resync(bc, card); 550 p = bc->bch.tx_skb->data + bc->bch.tx_idx; 551 if (test_bit(FLG_HDLC, &bc->bch.Flags)) { 552 count = isdnhdlc_encode(&bc->hsend, p, count, &i, 553 bc->hsbuf, bc->free); 554 pr_debug("%s: B%1d hdlc encoded %d in %d\n", card->name, 555 bc->bch.nr, i, count); 556 bc->bch.tx_idx += i; 557 bc->free -= count; 558 p = bc->hsbuf; 559 } else { 560 if (count > bc->free) 561 count = bc->free; 562 bc->bch.tx_idx += count; 563 bc->free -= count; 564 } 565 m = (bc->bch.nr & 1) ? 0xffffff00 : 0xffff00ff; 566 for (i = 0; i < count; i++) { 567 if (bc->idx >= card->send.size) 568 bc->idx = 0; 569 v = card->send.start[bc->idx]; 570 v &= m; 571 v |= (bc->bch.nr & 1) ? (u32)(p[i]) : ((u32)(p[i])) << 8; 572 card->send.start[bc->idx++] = v; 573 } 574 if (debug & DEBUG_HW_BFIFO) { 575 snprintf(card->log, LOG_SIZE, "B%1d-send %s %d ", 576 bc->bch.nr, card->name, count); 577 print_hex_dump_bytes(card->log, DUMP_PREFIX_OFFSET, p, count); 578 } 579 if (bc->free) 580 bc_next_frame(bc); 581 } 582 583 584 static int 585 bc_next_frame(struct tiger_ch *bc) 586 { 587 if (bc->bch.tx_skb && bc->bch.tx_idx < bc->bch.tx_skb->len) { 588 fill_dma(bc); 589 } else { 590 if (bc->bch.tx_skb) 591 dev_kfree_skb(bc->bch.tx_skb); 592 if (get_next_bframe(&bc->bch)) 593 fill_dma(bc); 594 else 595 return 0; 596 } 597 return 1; 598 } 599 600 static void 601 send_tiger_bc(struct tiger_hw *card, struct tiger_ch *bc) 602 { 603 int ret; 604 605 bc->free += card->send.size / 2; 606 if (bc->free >= card->send.size) { 607 if (!(bc->txstate & (TX_UNDERRUN | TX_INIT))) { 608 pr_info("%s: B%1d TX underrun state %x\n", card->name, 609 bc->bch.nr, bc->txstate); 610 bc->txstate |= TX_UNDERRUN; 611 } 612 bc->free = card->send.size; 613 } 614 ret = bc_next_frame(bc); 615 if (!ret) { 616 if (test_bit(FLG_HDLC, &bc->bch.Flags)) { 617 fill_hdlc_flag(bc); 618 return; 619 } 620 pr_debug("%s: B%1d TX no data free %d idx %d/%d\n", card->name, 621 bc->bch.nr, bc->free, bc->idx, card->send.idx); 622 if (!(bc->txstate & (TX_IDLE | TX_INIT))) { 623 fill_mem(bc, bc->idx, bc->free, 0xff); 624 if (bc->free == card->send.size) 625 bc->txstate |= TX_IDLE; 626 } 627 } 628 } 629 630 static void 631 send_tiger(struct tiger_hw *card, u8 irq_stat) 632 { 633 int i; 634 635 /* Note send is via the READ DMA channel */ 636 if ((irq_stat & card->last_is0) & NJ_IRQM0_RD_MASK) { 637 pr_info("%s: tiger warn write double dma %x/%x\n", 638 card->name, irq_stat, card->last_is0); 639 return; 640 } else { 641 card->last_is0 &= ~NJ_IRQM0_RD_MASK; 642 card->last_is0 |= (irq_stat & NJ_IRQM0_RD_MASK); 643 } 644 for (i = 0; i < 2; i++) { 645 if (test_bit(FLG_ACTIVE, &card->bc[i].bch.Flags)) 646 send_tiger_bc(card, &card->bc[i]); 647 } 648 } 649 650 static irqreturn_t 651 nj_irq(int intno, void *dev_id) 652 { 653 struct tiger_hw *card = dev_id; 654 u8 val, s1val, s0val; 655 656 spin_lock(&card->lock); 657 s0val = inb(card->base | NJ_IRQSTAT0); 658 s1val = inb(card->base | NJ_IRQSTAT1); 659 if ((s1val & NJ_ISACIRQ) && (s0val == 0)) { 660 /* shared IRQ */ 661 spin_unlock(&card->lock); 662 return IRQ_NONE; 663 } 664 pr_debug("%s: IRQSTAT0 %02x IRQSTAT1 %02x\n", card->name, s0val, s1val); 665 card->irqcnt++; 666 if (!(s1val & NJ_ISACIRQ)) { 667 val = ReadISAC_nj(card, ISAC_ISTA); 668 if (val) 669 mISDNisac_irq(&card->isac, val); 670 } 671 672 if (s0val) 673 /* write to clear */ 674 outb(s0val, card->base | NJ_IRQSTAT0); 675 else 676 goto end; 677 s1val = s0val; 678 /* set bits in sval to indicate which page is free */ 679 card->recv.dmacur = inl(card->base | NJ_DMA_WRITE_ADR); 680 card->recv.idx = (card->recv.dmacur - card->recv.dmastart) >> 2; 681 if (card->recv.dmacur < card->recv.dmairq) 682 s0val = 0x08; /* the 2nd write area is free */ 683 else 684 s0val = 0x04; /* the 1st write area is free */ 685 686 card->send.dmacur = inl(card->base | NJ_DMA_READ_ADR); 687 card->send.idx = (card->send.dmacur - card->send.dmastart) >> 2; 688 if (card->send.dmacur < card->send.dmairq) 689 s0val |= 0x02; /* the 2nd read area is free */ 690 else 691 s0val |= 0x01; /* the 1st read area is free */ 692 693 pr_debug("%s: DMA Status %02x/%02x/%02x %d/%d\n", card->name, 694 s1val, s0val, card->last_is0, 695 card->recv.idx, card->send.idx); 696 /* test if we have a DMA interrupt */ 697 if (s0val != card->last_is0) { 698 if ((s0val & NJ_IRQM0_RD_MASK) != 699 (card->last_is0 & NJ_IRQM0_RD_MASK)) 700 /* got a write dma int */ 701 send_tiger(card, s0val); 702 if ((s0val & NJ_IRQM0_WR_MASK) != 703 (card->last_is0 & NJ_IRQM0_WR_MASK)) 704 /* got a read dma int */ 705 recv_tiger(card, s0val); 706 } 707 end: 708 spin_unlock(&card->lock); 709 return IRQ_HANDLED; 710 } 711 712 static int 713 nj_l2l1B(struct mISDNchannel *ch, struct sk_buff *skb) 714 { 715 int ret = -EINVAL; 716 struct bchannel *bch = container_of(ch, struct bchannel, ch); 717 struct tiger_ch *bc = container_of(bch, struct tiger_ch, bch); 718 struct tiger_hw *card = bch->hw; 719 struct mISDNhead *hh = mISDN_HEAD_P(skb); 720 unsigned long flags; 721 722 switch (hh->prim) { 723 case PH_DATA_REQ: 724 spin_lock_irqsave(&card->lock, flags); 725 ret = bchannel_senddata(bch, skb); 726 if (ret > 0) { /* direct TX */ 727 fill_dma(bc); 728 ret = 0; 729 } 730 spin_unlock_irqrestore(&card->lock, flags); 731 return ret; 732 case PH_ACTIVATE_REQ: 733 spin_lock_irqsave(&card->lock, flags); 734 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags)) 735 ret = mode_tiger(bc, ch->protocol); 736 else 737 ret = 0; 738 spin_unlock_irqrestore(&card->lock, flags); 739 if (!ret) 740 _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0, 741 NULL, GFP_KERNEL); 742 break; 743 case PH_DEACTIVATE_REQ: 744 spin_lock_irqsave(&card->lock, flags); 745 mISDN_clear_bchannel(bch); 746 mode_tiger(bc, ISDN_P_NONE); 747 spin_unlock_irqrestore(&card->lock, flags); 748 _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0, 749 NULL, GFP_KERNEL); 750 ret = 0; 751 break; 752 } 753 if (!ret) 754 dev_kfree_skb(skb); 755 return ret; 756 } 757 758 static int 759 channel_bctrl(struct tiger_ch *bc, struct mISDN_ctrl_req *cq) 760 { 761 int ret = 0; 762 struct tiger_hw *card = bc->bch.hw; 763 764 switch (cq->op) { 765 case MISDN_CTRL_GETOP: 766 cq->op = 0; 767 break; 768 /* Nothing implemented yet */ 769 case MISDN_CTRL_FILL_EMPTY: 770 default: 771 pr_info("%s: %s unknown Op %x\n", card->name, __func__, cq->op); 772 ret = -EINVAL; 773 break; 774 } 775 return ret; 776 } 777 778 static int 779 nj_bctrl(struct mISDNchannel *ch, u32 cmd, void *arg) 780 { 781 struct bchannel *bch = container_of(ch, struct bchannel, ch); 782 struct tiger_ch *bc = container_of(bch, struct tiger_ch, bch); 783 struct tiger_hw *card = bch->hw; 784 int ret = -EINVAL; 785 u_long flags; 786 787 pr_debug("%s: %s cmd:%x %p\n", card->name, __func__, cmd, arg); 788 switch (cmd) { 789 case CLOSE_CHANNEL: 790 test_and_clear_bit(FLG_OPEN, &bch->Flags); 791 spin_lock_irqsave(&card->lock, flags); 792 mISDN_freebchannel(bch); 793 mode_tiger(bc, ISDN_P_NONE); 794 spin_unlock_irqrestore(&card->lock, flags); 795 ch->protocol = ISDN_P_NONE; 796 ch->peer = NULL; 797 module_put(THIS_MODULE); 798 ret = 0; 799 break; 800 case CONTROL_CHANNEL: 801 ret = channel_bctrl(bc, arg); 802 break; 803 default: 804 pr_info("%s: %s unknown prim(%x)\n", card->name, __func__, cmd); 805 } 806 return ret; 807 } 808 809 static int 810 channel_ctrl(struct tiger_hw *card, struct mISDN_ctrl_req *cq) 811 { 812 int ret = 0; 813 814 switch (cq->op) { 815 case MISDN_CTRL_GETOP: 816 cq->op = MISDN_CTRL_LOOP | MISDN_CTRL_L1_TIMER3; 817 break; 818 case MISDN_CTRL_LOOP: 819 /* cq->channel: 0 disable, 1 B1 loop 2 B2 loop, 3 both */ 820 if (cq->channel < 0 || cq->channel > 3) { 821 ret = -EINVAL; 822 break; 823 } 824 ret = card->isac.ctrl(&card->isac, HW_TESTLOOP, cq->channel); 825 break; 826 case MISDN_CTRL_L1_TIMER3: 827 ret = card->isac.ctrl(&card->isac, HW_TIMER3_VALUE, cq->p1); 828 break; 829 default: 830 pr_info("%s: %s unknown Op %x\n", card->name, __func__, cq->op); 831 ret = -EINVAL; 832 break; 833 } 834 return ret; 835 } 836 837 static int 838 open_bchannel(struct tiger_hw *card, struct channel_req *rq) 839 { 840 struct bchannel *bch; 841 842 if (rq->adr.channel == 0 || rq->adr.channel > 2) 843 return -EINVAL; 844 if (rq->protocol == ISDN_P_NONE) 845 return -EINVAL; 846 bch = &card->bc[rq->adr.channel - 1].bch; 847 if (test_and_set_bit(FLG_OPEN, &bch->Flags)) 848 return -EBUSY; /* b-channel can be only open once */ 849 test_and_clear_bit(FLG_FILLEMPTY, &bch->Flags); 850 bch->ch.protocol = rq->protocol; 851 rq->ch = &bch->ch; 852 return 0; 853 } 854 855 /* 856 * device control function 857 */ 858 static int 859 nj_dctrl(struct mISDNchannel *ch, u32 cmd, void *arg) 860 { 861 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D); 862 struct dchannel *dch = container_of(dev, struct dchannel, dev); 863 struct tiger_hw *card = dch->hw; 864 struct channel_req *rq; 865 int err = 0; 866 867 pr_debug("%s: %s cmd:%x %p\n", card->name, __func__, cmd, arg); 868 switch (cmd) { 869 case OPEN_CHANNEL: 870 rq = arg; 871 if (rq->protocol == ISDN_P_TE_S0) 872 err = card->isac.open(&card->isac, rq); 873 else 874 err = open_bchannel(card, rq); 875 if (err) 876 break; 877 if (!try_module_get(THIS_MODULE)) 878 pr_info("%s: cannot get module\n", card->name); 879 break; 880 case CLOSE_CHANNEL: 881 pr_debug("%s: dev(%d) close from %p\n", card->name, dch->dev.id, 882 __builtin_return_address(0)); 883 module_put(THIS_MODULE); 884 break; 885 case CONTROL_CHANNEL: 886 err = channel_ctrl(card, arg); 887 break; 888 default: 889 pr_debug("%s: %s unknown command %x\n", 890 card->name, __func__, cmd); 891 return -EINVAL; 892 } 893 return err; 894 } 895 896 static int 897 nj_init_card(struct tiger_hw *card) 898 { 899 u_long flags; 900 int ret; 901 902 spin_lock_irqsave(&card->lock, flags); 903 nj_disable_hwirq(card); 904 spin_unlock_irqrestore(&card->lock, flags); 905 906 card->irq = card->pdev->irq; 907 if (request_irq(card->irq, nj_irq, IRQF_SHARED, card->name, card)) { 908 pr_info("%s: couldn't get interrupt %d\n", 909 card->name, card->irq); 910 card->irq = -1; 911 return -EIO; 912 } 913 914 spin_lock_irqsave(&card->lock, flags); 915 nj_reset(card); 916 ret = card->isac.init(&card->isac); 917 if (ret) 918 goto error; 919 ret = inittiger(card); 920 if (ret) 921 goto error; 922 mode_tiger(&card->bc[0], ISDN_P_NONE); 923 mode_tiger(&card->bc[1], ISDN_P_NONE); 924 error: 925 spin_unlock_irqrestore(&card->lock, flags); 926 return ret; 927 } 928 929 930 static void 931 nj_release(struct tiger_hw *card) 932 { 933 u_long flags; 934 int i; 935 936 if (card->base_s) { 937 spin_lock_irqsave(&card->lock, flags); 938 nj_disable_hwirq(card); 939 mode_tiger(&card->bc[0], ISDN_P_NONE); 940 mode_tiger(&card->bc[1], ISDN_P_NONE); 941 card->isac.release(&card->isac); 942 spin_unlock_irqrestore(&card->lock, flags); 943 release_region(card->base, card->base_s); 944 card->base_s = 0; 945 } 946 if (card->irq > 0) 947 free_irq(card->irq, card); 948 if (card->isac.dch.dev.dev.class) 949 mISDN_unregister_device(&card->isac.dch.dev); 950 951 for (i = 0; i < 2; i++) { 952 mISDN_freebchannel(&card->bc[i].bch); 953 kfree(card->bc[i].hsbuf); 954 kfree(card->bc[i].hrbuf); 955 } 956 if (card->dma_p) 957 pci_free_consistent(card->pdev, NJ_DMA_SIZE, 958 card->dma_p, card->dma); 959 write_lock_irqsave(&card_lock, flags); 960 list_del(&card->list); 961 write_unlock_irqrestore(&card_lock, flags); 962 pci_clear_master(card->pdev); 963 pci_disable_device(card->pdev); 964 pci_set_drvdata(card->pdev, NULL); 965 kfree(card); 966 } 967 968 969 static int 970 nj_setup(struct tiger_hw *card) 971 { 972 card->base = pci_resource_start(card->pdev, 0); 973 card->base_s = pci_resource_len(card->pdev, 0); 974 if (!request_region(card->base, card->base_s, card->name)) { 975 pr_info("%s: NETjet config port %#x-%#x already in use\n", 976 card->name, card->base, 977 (u32)(card->base + card->base_s - 1)); 978 card->base_s = 0; 979 return -EIO; 980 } 981 ASSIGN_FUNC(nj, ISAC, card->isac); 982 return 0; 983 } 984 985 986 static int __devinit 987 setup_instance(struct tiger_hw *card) 988 { 989 int i, err; 990 u_long flags; 991 992 snprintf(card->name, MISDN_MAX_IDLEN - 1, "netjet.%d", nj_cnt + 1); 993 write_lock_irqsave(&card_lock, flags); 994 list_add_tail(&card->list, &Cards); 995 write_unlock_irqrestore(&card_lock, flags); 996 997 _set_debug(card); 998 card->isac.name = card->name; 999 spin_lock_init(&card->lock); 1000 card->isac.hwlock = &card->lock; 1001 mISDNisac_init(&card->isac, card); 1002 1003 card->isac.dch.dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) | 1004 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK)); 1005 card->isac.dch.dev.D.ctrl = nj_dctrl; 1006 for (i = 0; i < 2; i++) { 1007 card->bc[i].bch.nr = i + 1; 1008 set_channelmap(i + 1, card->isac.dch.dev.channelmap); 1009 mISDN_initbchannel(&card->bc[i].bch, MAX_DATA_MEM); 1010 card->bc[i].bch.hw = card; 1011 card->bc[i].bch.ch.send = nj_l2l1B; 1012 card->bc[i].bch.ch.ctrl = nj_bctrl; 1013 card->bc[i].bch.ch.nr = i + 1; 1014 list_add(&card->bc[i].bch.ch.list, 1015 &card->isac.dch.dev.bchannels); 1016 card->bc[i].bch.hw = card; 1017 } 1018 err = nj_setup(card); 1019 if (err) 1020 goto error; 1021 err = mISDN_register_device(&card->isac.dch.dev, &card->pdev->dev, 1022 card->name); 1023 if (err) 1024 goto error; 1025 err = nj_init_card(card); 1026 if (!err) { 1027 nj_cnt++; 1028 pr_notice("Netjet %d cards installed\n", nj_cnt); 1029 return 0; 1030 } 1031 error: 1032 nj_release(card); 1033 return err; 1034 } 1035 1036 static int __devinit 1037 nj_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1038 { 1039 int err = -ENOMEM; 1040 int cfg; 1041 struct tiger_hw *card; 1042 1043 if (pdev->subsystem_vendor == 0x8086 && 1044 pdev->subsystem_device == 0x0003) { 1045 pr_notice("Netjet: Digium X100P/X101P not handled\n"); 1046 return -ENODEV; 1047 } 1048 1049 if (pdev->subsystem_vendor == 0x55 && 1050 pdev->subsystem_device == 0x02) { 1051 pr_notice("Netjet: Enter!Now not handled yet\n"); 1052 return -ENODEV; 1053 } 1054 1055 if (pdev->subsystem_vendor == 0xb100 && 1056 pdev->subsystem_device == 0x0003) { 1057 pr_notice("Netjet: Digium TDM400P not handled yet\n"); 1058 return -ENODEV; 1059 } 1060 1061 card = kzalloc(sizeof(struct tiger_hw), GFP_ATOMIC); 1062 if (!card) { 1063 pr_info("No kmem for Netjet\n"); 1064 return err; 1065 } 1066 1067 card->pdev = pdev; 1068 1069 err = pci_enable_device(pdev); 1070 if (err) { 1071 kfree(card); 1072 return err; 1073 } 1074 1075 printk(KERN_INFO "nj_probe(mISDN): found adapter at %s\n", 1076 pci_name(pdev)); 1077 1078 pci_set_master(pdev); 1079 1080 /* the TJ300 and TJ320 must be detected, the IRQ handling is different 1081 * unfortunately the chips use the same device ID, but the TJ320 has 1082 * the bit20 in status PCI cfg register set 1083 */ 1084 pci_read_config_dword(pdev, 0x04, &cfg); 1085 if (cfg & 0x00100000) 1086 card->typ = NETJET_S_TJ320; 1087 else 1088 card->typ = NETJET_S_TJ300; 1089 1090 card->base = pci_resource_start(pdev, 0); 1091 card->irq = pdev->irq; 1092 pci_set_drvdata(pdev, card); 1093 err = setup_instance(card); 1094 if (err) 1095 pci_set_drvdata(pdev, NULL); 1096 1097 return err; 1098 } 1099 1100 1101 static void __devexit nj_remove(struct pci_dev *pdev) 1102 { 1103 struct tiger_hw *card = pci_get_drvdata(pdev); 1104 1105 if (card) 1106 nj_release(card); 1107 else 1108 pr_info("%s drvdata already removed\n", __func__); 1109 } 1110 1111 /* We cannot select cards with PCI_SUB... IDs, since here are cards with 1112 * SUB IDs set to PCI_ANY_ID, so we need to match all and reject 1113 * known other cards which not work with this driver - see probe function */ 1114 static struct pci_device_id nj_pci_ids[] __devinitdata = { 1115 { PCI_VENDOR_ID_TIGERJET, PCI_DEVICE_ID_TIGERJET_300, 1116 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 1117 { } 1118 }; 1119 MODULE_DEVICE_TABLE(pci, nj_pci_ids); 1120 1121 static struct pci_driver nj_driver = { 1122 .name = "netjet", 1123 .probe = nj_probe, 1124 .remove = __devexit_p(nj_remove), 1125 .id_table = nj_pci_ids, 1126 }; 1127 1128 static int __init nj_init(void) 1129 { 1130 int err; 1131 1132 pr_notice("Netjet PCI driver Rev. %s\n", NETJET_REV); 1133 err = pci_register_driver(&nj_driver); 1134 return err; 1135 } 1136 1137 static void __exit nj_cleanup(void) 1138 { 1139 pci_unregister_driver(&nj_driver); 1140 } 1141 1142 module_init(nj_init); 1143 module_exit(nj_cleanup); 1144