1 /* 2 * avm_fritz.c low level stuff for AVM FRITZ!CARD PCI ISDN cards 3 * Thanks to AVM, Berlin for informations 4 * 5 * Author Karsten Keil <keil@isdn4linux.de> 6 * 7 * Copyright 2009 by Karsten Keil <keil@isdn4linux.de> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 * 22 */ 23 #include <linux/interrupt.h> 24 #include <linux/module.h> 25 #include <linux/pci.h> 26 #include <linux/delay.h> 27 #include <linux/mISDNhw.h> 28 #include <linux/slab.h> 29 #include <asm/unaligned.h> 30 #include "ipac.h" 31 32 33 #define AVMFRITZ_REV "2.2" 34 35 static int AVM_cnt; 36 static int debug; 37 38 enum { 39 AVM_FRITZ_PCI, 40 AVM_FRITZ_PCIV2, 41 }; 42 43 #define HDLC_FIFO 0x0 44 #define HDLC_STATUS 0x4 45 #define CHIP_WINDOW 0x10 46 47 #define CHIP_INDEX 0x4 48 #define AVM_HDLC_1 0x00 49 #define AVM_HDLC_2 0x01 50 #define AVM_ISAC_FIFO 0x02 51 #define AVM_ISAC_REG_LOW 0x04 52 #define AVM_ISAC_REG_HIGH 0x06 53 54 #define AVM_STATUS0_IRQ_ISAC 0x01 55 #define AVM_STATUS0_IRQ_HDLC 0x02 56 #define AVM_STATUS0_IRQ_TIMER 0x04 57 #define AVM_STATUS0_IRQ_MASK 0x07 58 59 #define AVM_STATUS0_RESET 0x01 60 #define AVM_STATUS0_DIS_TIMER 0x02 61 #define AVM_STATUS0_RES_TIMER 0x04 62 #define AVM_STATUS0_ENA_IRQ 0x08 63 #define AVM_STATUS0_TESTBIT 0x10 64 65 #define AVM_STATUS1_INT_SEL 0x0f 66 #define AVM_STATUS1_ENA_IOM 0x80 67 68 #define HDLC_MODE_ITF_FLG 0x01 69 #define HDLC_MODE_TRANS 0x02 70 #define HDLC_MODE_CCR_7 0x04 71 #define HDLC_MODE_CCR_16 0x08 72 #define HDLC_FIFO_SIZE_128 0x20 73 #define HDLC_MODE_TESTLOOP 0x80 74 75 #define HDLC_INT_XPR 0x80 76 #define HDLC_INT_XDU 0x40 77 #define HDLC_INT_RPR 0x20 78 #define HDLC_INT_MASK 0xE0 79 80 #define HDLC_STAT_RME 0x01 81 #define HDLC_STAT_RDO 0x10 82 #define HDLC_STAT_CRCVFRRAB 0x0E 83 #define HDLC_STAT_CRCVFR 0x06 84 #define HDLC_STAT_RML_MASK_V1 0x3f00 85 #define HDLC_STAT_RML_MASK_V2 0x7f00 86 87 #define HDLC_CMD_XRS 0x80 88 #define HDLC_CMD_XME 0x01 89 #define HDLC_CMD_RRS 0x20 90 #define HDLC_CMD_XML_MASK 0x3f00 91 92 #define HDLC_FIFO_SIZE_V1 32 93 #define HDLC_FIFO_SIZE_V2 128 94 95 /* Fritz PCI v2.0 */ 96 97 #define AVM_HDLC_FIFO_1 0x10 98 #define AVM_HDLC_FIFO_2 0x18 99 100 #define AVM_HDLC_STATUS_1 0x14 101 #define AVM_HDLC_STATUS_2 0x1c 102 103 #define AVM_ISACX_INDEX 0x04 104 #define AVM_ISACX_DATA 0x08 105 106 /* data struct */ 107 #define LOG_SIZE 63 108 109 struct hdlc_stat_reg { 110 #ifdef __BIG_ENDIAN 111 u8 fill; 112 u8 mode; 113 u8 xml; 114 u8 cmd; 115 #else 116 u8 cmd; 117 u8 xml; 118 u8 mode; 119 u8 fill; 120 #endif 121 } __attribute__((packed)); 122 123 struct hdlc_hw { 124 union { 125 u32 ctrl; 126 struct hdlc_stat_reg sr; 127 } ctrl; 128 u32 stat; 129 }; 130 131 struct fritzcard { 132 struct list_head list; 133 struct pci_dev *pdev; 134 char name[MISDN_MAX_IDLEN]; 135 u8 type; 136 u8 ctrlreg; 137 u16 irq; 138 u32 irqcnt; 139 u32 addr; 140 spinlock_t lock; /* hw lock */ 141 struct isac_hw isac; 142 struct hdlc_hw hdlc[2]; 143 struct bchannel bch[2]; 144 char log[LOG_SIZE + 1]; 145 }; 146 147 static LIST_HEAD(Cards); 148 static DEFINE_RWLOCK(card_lock); /* protect Cards */ 149 150 static void 151 _set_debug(struct fritzcard *card) 152 { 153 card->isac.dch.debug = debug; 154 card->bch[0].debug = debug; 155 card->bch[1].debug = debug; 156 } 157 158 static int 159 set_debug(const char *val, struct kernel_param *kp) 160 { 161 int ret; 162 struct fritzcard *card; 163 164 ret = param_set_uint(val, kp); 165 if (!ret) { 166 read_lock(&card_lock); 167 list_for_each_entry(card, &Cards, list) 168 _set_debug(card); 169 read_unlock(&card_lock); 170 } 171 return ret; 172 } 173 174 MODULE_AUTHOR("Karsten Keil"); 175 MODULE_LICENSE("GPL v2"); 176 MODULE_VERSION(AVMFRITZ_REV); 177 module_param_call(debug, set_debug, param_get_uint, &debug, S_IRUGO | S_IWUSR); 178 MODULE_PARM_DESC(debug, "avmfritz debug mask"); 179 180 /* Interface functions */ 181 182 static u8 183 ReadISAC_V1(void *p, u8 offset) 184 { 185 struct fritzcard *fc = p; 186 u8 idx = (offset > 0x2f) ? AVM_ISAC_REG_HIGH : AVM_ISAC_REG_LOW; 187 188 outb(idx, fc->addr + CHIP_INDEX); 189 return inb(fc->addr + CHIP_WINDOW + (offset & 0xf)); 190 } 191 192 static void 193 WriteISAC_V1(void *p, u8 offset, u8 value) 194 { 195 struct fritzcard *fc = p; 196 u8 idx = (offset > 0x2f) ? AVM_ISAC_REG_HIGH : AVM_ISAC_REG_LOW; 197 198 outb(idx, fc->addr + CHIP_INDEX); 199 outb(value, fc->addr + CHIP_WINDOW + (offset & 0xf)); 200 } 201 202 static void 203 ReadFiFoISAC_V1(void *p, u8 off, u8 *data, int size) 204 { 205 struct fritzcard *fc = p; 206 207 outb(AVM_ISAC_FIFO, fc->addr + CHIP_INDEX); 208 insb(fc->addr + CHIP_WINDOW, data, size); 209 } 210 211 static void 212 WriteFiFoISAC_V1(void *p, u8 off, u8 *data, int size) 213 { 214 struct fritzcard *fc = p; 215 216 outb(AVM_ISAC_FIFO, fc->addr + CHIP_INDEX); 217 outsb(fc->addr + CHIP_WINDOW, data, size); 218 } 219 220 static u8 221 ReadISAC_V2(void *p, u8 offset) 222 { 223 struct fritzcard *fc = p; 224 225 outl(offset, fc->addr + AVM_ISACX_INDEX); 226 return 0xff & inl(fc->addr + AVM_ISACX_DATA); 227 } 228 229 static void 230 WriteISAC_V2(void *p, u8 offset, u8 value) 231 { 232 struct fritzcard *fc = p; 233 234 outl(offset, fc->addr + AVM_ISACX_INDEX); 235 outl(value, fc->addr + AVM_ISACX_DATA); 236 } 237 238 static void 239 ReadFiFoISAC_V2(void *p, u8 off, u8 *data, int size) 240 { 241 struct fritzcard *fc = p; 242 int i; 243 244 outl(off, fc->addr + AVM_ISACX_INDEX); 245 for (i = 0; i < size; i++) 246 data[i] = 0xff & inl(fc->addr + AVM_ISACX_DATA); 247 } 248 249 static void 250 WriteFiFoISAC_V2(void *p, u8 off, u8 *data, int size) 251 { 252 struct fritzcard *fc = p; 253 int i; 254 255 outl(off, fc->addr + AVM_ISACX_INDEX); 256 for (i = 0; i < size; i++) 257 outl(data[i], fc->addr + AVM_ISACX_DATA); 258 } 259 260 static struct bchannel * 261 Sel_BCS(struct fritzcard *fc, u32 channel) 262 { 263 if (test_bit(FLG_ACTIVE, &fc->bch[0].Flags) && 264 (fc->bch[0].nr & channel)) 265 return &fc->bch[0]; 266 else if (test_bit(FLG_ACTIVE, &fc->bch[1].Flags) && 267 (fc->bch[1].nr & channel)) 268 return &fc->bch[1]; 269 else 270 return NULL; 271 } 272 273 static inline void 274 __write_ctrl_pci(struct fritzcard *fc, struct hdlc_hw *hdlc, u32 channel) { 275 u32 idx = channel == 2 ? AVM_HDLC_2 : AVM_HDLC_1; 276 277 outl(idx, fc->addr + CHIP_INDEX); 278 outl(hdlc->ctrl.ctrl, fc->addr + CHIP_WINDOW + HDLC_STATUS); 279 } 280 281 static inline void 282 __write_ctrl_pciv2(struct fritzcard *fc, struct hdlc_hw *hdlc, u32 channel) { 283 outl(hdlc->ctrl.ctrl, fc->addr + (channel == 2 ? AVM_HDLC_STATUS_2 : 284 AVM_HDLC_STATUS_1)); 285 } 286 287 void 288 write_ctrl(struct bchannel *bch, int which) { 289 struct fritzcard *fc = bch->hw; 290 struct hdlc_hw *hdlc; 291 292 hdlc = &fc->hdlc[(bch->nr - 1) & 1]; 293 pr_debug("%s: hdlc %c wr%x ctrl %x\n", fc->name, '@' + bch->nr, 294 which, hdlc->ctrl.ctrl); 295 switch (fc->type) { 296 case AVM_FRITZ_PCIV2: 297 __write_ctrl_pciv2(fc, hdlc, bch->nr); 298 break; 299 case AVM_FRITZ_PCI: 300 __write_ctrl_pci(fc, hdlc, bch->nr); 301 break; 302 } 303 } 304 305 306 static inline u32 307 __read_status_pci(u_long addr, u32 channel) 308 { 309 outl(channel == 2 ? AVM_HDLC_2 : AVM_HDLC_1, addr + CHIP_INDEX); 310 return inl(addr + CHIP_WINDOW + HDLC_STATUS); 311 } 312 313 static inline u32 314 __read_status_pciv2(u_long addr, u32 channel) 315 { 316 return inl(addr + (channel == 2 ? AVM_HDLC_STATUS_2 : 317 AVM_HDLC_STATUS_1)); 318 } 319 320 321 static u32 322 read_status(struct fritzcard *fc, u32 channel) 323 { 324 switch (fc->type) { 325 case AVM_FRITZ_PCIV2: 326 return __read_status_pciv2(fc->addr, channel); 327 case AVM_FRITZ_PCI: 328 return __read_status_pci(fc->addr, channel); 329 } 330 /* dummy */ 331 return 0; 332 } 333 334 static void 335 enable_hwirq(struct fritzcard *fc) 336 { 337 fc->ctrlreg |= AVM_STATUS0_ENA_IRQ; 338 outb(fc->ctrlreg, fc->addr + 2); 339 } 340 341 static void 342 disable_hwirq(struct fritzcard *fc) 343 { 344 fc->ctrlreg &= ~AVM_STATUS0_ENA_IRQ; 345 outb(fc->ctrlreg, fc->addr + 2); 346 } 347 348 static int 349 modehdlc(struct bchannel *bch, int protocol) 350 { 351 struct fritzcard *fc = bch->hw; 352 struct hdlc_hw *hdlc; 353 u8 mode; 354 355 hdlc = &fc->hdlc[(bch->nr - 1) & 1]; 356 pr_debug("%s: hdlc %c protocol %x-->%x ch %d\n", fc->name, 357 '@' + bch->nr, bch->state, protocol, bch->nr); 358 hdlc->ctrl.ctrl = 0; 359 mode = (fc->type == AVM_FRITZ_PCIV2) ? HDLC_FIFO_SIZE_128 : 0; 360 361 switch (protocol) { 362 case -1: /* used for init */ 363 bch->state = -1; 364 case ISDN_P_NONE: 365 if (bch->state == ISDN_P_NONE) 366 break; 367 hdlc->ctrl.sr.cmd = HDLC_CMD_XRS | HDLC_CMD_RRS; 368 hdlc->ctrl.sr.mode = mode | HDLC_MODE_TRANS; 369 write_ctrl(bch, 5); 370 bch->state = ISDN_P_NONE; 371 test_and_clear_bit(FLG_HDLC, &bch->Flags); 372 test_and_clear_bit(FLG_TRANSPARENT, &bch->Flags); 373 break; 374 case ISDN_P_B_RAW: 375 bch->state = protocol; 376 hdlc->ctrl.sr.cmd = HDLC_CMD_XRS | HDLC_CMD_RRS; 377 hdlc->ctrl.sr.mode = mode | HDLC_MODE_TRANS; 378 write_ctrl(bch, 5); 379 hdlc->ctrl.sr.cmd = HDLC_CMD_XRS; 380 write_ctrl(bch, 1); 381 hdlc->ctrl.sr.cmd = 0; 382 test_and_set_bit(FLG_TRANSPARENT, &bch->Flags); 383 break; 384 case ISDN_P_B_HDLC: 385 bch->state = protocol; 386 hdlc->ctrl.sr.cmd = HDLC_CMD_XRS | HDLC_CMD_RRS; 387 hdlc->ctrl.sr.mode = mode | HDLC_MODE_ITF_FLG; 388 write_ctrl(bch, 5); 389 hdlc->ctrl.sr.cmd = HDLC_CMD_XRS; 390 write_ctrl(bch, 1); 391 hdlc->ctrl.sr.cmd = 0; 392 test_and_set_bit(FLG_HDLC, &bch->Flags); 393 break; 394 default: 395 pr_info("%s: protocol not known %x\n", fc->name, protocol); 396 return -ENOPROTOOPT; 397 } 398 return 0; 399 } 400 401 static void 402 hdlc_empty_fifo(struct bchannel *bch, int count) 403 { 404 u32 *ptr; 405 u8 *p; 406 u32 val, addr; 407 int cnt = 0; 408 struct fritzcard *fc = bch->hw; 409 410 pr_debug("%s: %s %d\n", fc->name, __func__, count); 411 if (!bch->rx_skb) { 412 bch->rx_skb = mI_alloc_skb(bch->maxlen, GFP_ATOMIC); 413 if (!bch->rx_skb) { 414 pr_info("%s: B receive out of memory\n", 415 fc->name); 416 return; 417 } 418 } 419 if ((bch->rx_skb->len + count) > bch->maxlen) { 420 pr_debug("%s: overrun %d\n", fc->name, 421 bch->rx_skb->len + count); 422 return; 423 } 424 p = skb_put(bch->rx_skb, count); 425 ptr = (u32 *)p; 426 if (fc->type == AVM_FRITZ_PCIV2) 427 addr = fc->addr + (bch->nr == 2 ? 428 AVM_HDLC_FIFO_2 : AVM_HDLC_FIFO_1); 429 else { 430 addr = fc->addr + CHIP_WINDOW; 431 outl(bch->nr == 2 ? AVM_HDLC_2 : AVM_HDLC_1, fc->addr); 432 } 433 while (cnt < count) { 434 val = le32_to_cpu(inl(addr)); 435 put_unaligned(val, ptr); 436 ptr++; 437 cnt += 4; 438 } 439 if (debug & DEBUG_HW_BFIFO) { 440 snprintf(fc->log, LOG_SIZE, "B%1d-recv %s %d ", 441 bch->nr, fc->name, count); 442 print_hex_dump_bytes(fc->log, DUMP_PREFIX_OFFSET, p, count); 443 } 444 } 445 446 static void 447 hdlc_fill_fifo(struct bchannel *bch) 448 { 449 struct fritzcard *fc = bch->hw; 450 struct hdlc_hw *hdlc; 451 int count, fs, cnt = 0; 452 u8 *p; 453 u32 *ptr, val, addr; 454 455 hdlc = &fc->hdlc[(bch->nr - 1) & 1]; 456 if (!bch->tx_skb) 457 return; 458 count = bch->tx_skb->len - bch->tx_idx; 459 if (count <= 0) 460 return; 461 fs = (fc->type == AVM_FRITZ_PCIV2) ? 462 HDLC_FIFO_SIZE_V2 : HDLC_FIFO_SIZE_V1; 463 p = bch->tx_skb->data + bch->tx_idx; 464 hdlc->ctrl.sr.cmd &= ~HDLC_CMD_XME; 465 if (count > fs) { 466 count = fs; 467 } else { 468 if (test_bit(FLG_HDLC, &bch->Flags)) 469 hdlc->ctrl.sr.cmd |= HDLC_CMD_XME; 470 } 471 pr_debug("%s: %s %d/%d/%d", fc->name, __func__, count, 472 bch->tx_idx, bch->tx_skb->len); 473 ptr = (u32 *)p; 474 bch->tx_idx += count; 475 hdlc->ctrl.sr.xml = ((count == fs) ? 0 : count); 476 if (fc->type == AVM_FRITZ_PCIV2) { 477 __write_ctrl_pciv2(fc, hdlc, bch->nr); 478 addr = fc->addr + (bch->nr == 2 ? 479 AVM_HDLC_FIFO_2 : AVM_HDLC_FIFO_1); 480 } else { 481 __write_ctrl_pci(fc, hdlc, bch->nr); 482 addr = fc->addr + CHIP_WINDOW; 483 } 484 while (cnt < count) { 485 val = get_unaligned(ptr); 486 outl(cpu_to_le32(val), addr); 487 ptr++; 488 cnt += 4; 489 } 490 if (debug & DEBUG_HW_BFIFO) { 491 snprintf(fc->log, LOG_SIZE, "B%1d-send %s %d ", 492 bch->nr, fc->name, count); 493 print_hex_dump_bytes(fc->log, DUMP_PREFIX_OFFSET, p, count); 494 } 495 } 496 497 static void 498 HDLC_irq_xpr(struct bchannel *bch) 499 { 500 if (bch->tx_skb && bch->tx_idx < bch->tx_skb->len) { 501 hdlc_fill_fifo(bch); 502 } else { 503 if (bch->tx_skb) 504 dev_kfree_skb(bch->tx_skb); 505 if (get_next_bframe(bch)) 506 hdlc_fill_fifo(bch); 507 } 508 } 509 510 static void 511 HDLC_irq(struct bchannel *bch, u32 stat) 512 { 513 struct fritzcard *fc = bch->hw; 514 int len, fs; 515 u32 rmlMask; 516 struct hdlc_hw *hdlc; 517 518 hdlc = &fc->hdlc[(bch->nr - 1) & 1]; 519 pr_debug("%s: ch%d stat %#x\n", fc->name, bch->nr, stat); 520 if (fc->type == AVM_FRITZ_PCIV2) { 521 rmlMask = HDLC_STAT_RML_MASK_V2; 522 fs = HDLC_FIFO_SIZE_V2; 523 } else { 524 rmlMask = HDLC_STAT_RML_MASK_V1; 525 fs = HDLC_FIFO_SIZE_V1; 526 } 527 if (stat & HDLC_INT_RPR) { 528 if (stat & HDLC_STAT_RDO) { 529 pr_warning("%s: ch%d stat %x RDO\n", 530 fc->name, bch->nr, stat); 531 hdlc->ctrl.sr.xml = 0; 532 hdlc->ctrl.sr.cmd |= HDLC_CMD_RRS; 533 write_ctrl(bch, 1); 534 hdlc->ctrl.sr.cmd &= ~HDLC_CMD_RRS; 535 write_ctrl(bch, 1); 536 if (bch->rx_skb) 537 skb_trim(bch->rx_skb, 0); 538 } else { 539 len = (stat & rmlMask) >> 8; 540 if (!len) 541 len = fs; 542 hdlc_empty_fifo(bch, len); 543 if (!bch->rx_skb) 544 goto handle_tx; 545 if (test_bit(FLG_TRANSPARENT, &bch->Flags) || 546 (stat & HDLC_STAT_RME)) { 547 if (((stat & HDLC_STAT_CRCVFRRAB) == 548 HDLC_STAT_CRCVFR) || 549 test_bit(FLG_TRANSPARENT, &bch->Flags)) { 550 recv_Bchannel(bch, 0); 551 } else { 552 pr_warning("%s: got invalid frame\n", 553 fc->name); 554 skb_trim(bch->rx_skb, 0); 555 } 556 } 557 } 558 } 559 handle_tx: 560 if (stat & HDLC_INT_XDU) { 561 /* Here we lost an TX interrupt, so 562 * restart transmitting the whole frame on HDLC 563 * in transparent mode we send the next data 564 */ 565 pr_warning("%s: ch%d stat %x XDU %s\n", fc->name, bch->nr, 566 stat, bch->tx_skb ? "tx_skb" : "no tx_skb"); 567 if (bch->tx_skb && bch->tx_skb->len) { 568 if (!test_bit(FLG_TRANSPARENT, &bch->Flags)) 569 bch->tx_idx = 0; 570 } 571 hdlc->ctrl.sr.xml = 0; 572 hdlc->ctrl.sr.cmd |= HDLC_CMD_XRS; 573 write_ctrl(bch, 1); 574 hdlc->ctrl.sr.cmd &= ~HDLC_CMD_XRS; 575 HDLC_irq_xpr(bch); 576 return; 577 } else if (stat & HDLC_INT_XPR) 578 HDLC_irq_xpr(bch); 579 } 580 581 static inline void 582 HDLC_irq_main(struct fritzcard *fc) 583 { 584 u32 stat; 585 struct bchannel *bch; 586 587 stat = read_status(fc, 1); 588 if (stat & HDLC_INT_MASK) { 589 bch = Sel_BCS(fc, 1); 590 if (bch) 591 HDLC_irq(bch, stat); 592 else 593 pr_debug("%s: spurious ch1 IRQ\n", fc->name); 594 } 595 stat = read_status(fc, 2); 596 if (stat & HDLC_INT_MASK) { 597 bch = Sel_BCS(fc, 2); 598 if (bch) 599 HDLC_irq(bch, stat); 600 else 601 pr_debug("%s: spurious ch2 IRQ\n", fc->name); 602 } 603 } 604 605 static irqreturn_t 606 avm_fritz_interrupt(int intno, void *dev_id) 607 { 608 struct fritzcard *fc = dev_id; 609 u8 val; 610 u8 sval; 611 612 spin_lock(&fc->lock); 613 sval = inb(fc->addr + 2); 614 pr_debug("%s: irq stat0 %x\n", fc->name, sval); 615 if ((sval & AVM_STATUS0_IRQ_MASK) == AVM_STATUS0_IRQ_MASK) { 616 /* shared IRQ from other HW */ 617 spin_unlock(&fc->lock); 618 return IRQ_NONE; 619 } 620 fc->irqcnt++; 621 622 if (!(sval & AVM_STATUS0_IRQ_ISAC)) { 623 val = ReadISAC_V1(fc, ISAC_ISTA); 624 mISDNisac_irq(&fc->isac, val); 625 } 626 if (!(sval & AVM_STATUS0_IRQ_HDLC)) 627 HDLC_irq_main(fc); 628 spin_unlock(&fc->lock); 629 return IRQ_HANDLED; 630 } 631 632 static irqreturn_t 633 avm_fritzv2_interrupt(int intno, void *dev_id) 634 { 635 struct fritzcard *fc = dev_id; 636 u8 val; 637 u8 sval; 638 639 spin_lock(&fc->lock); 640 sval = inb(fc->addr + 2); 641 pr_debug("%s: irq stat0 %x\n", fc->name, sval); 642 if (!(sval & AVM_STATUS0_IRQ_MASK)) { 643 /* shared IRQ from other HW */ 644 spin_unlock(&fc->lock); 645 return IRQ_NONE; 646 } 647 fc->irqcnt++; 648 649 if (sval & AVM_STATUS0_IRQ_HDLC) 650 HDLC_irq_main(fc); 651 if (sval & AVM_STATUS0_IRQ_ISAC) { 652 val = ReadISAC_V2(fc, ISACX_ISTA); 653 mISDNisac_irq(&fc->isac, val); 654 } 655 if (sval & AVM_STATUS0_IRQ_TIMER) { 656 pr_debug("%s: timer irq\n", fc->name); 657 outb(fc->ctrlreg | AVM_STATUS0_RES_TIMER, fc->addr + 2); 658 udelay(1); 659 outb(fc->ctrlreg, fc->addr + 2); 660 } 661 spin_unlock(&fc->lock); 662 return IRQ_HANDLED; 663 } 664 665 static int 666 avm_l2l1B(struct mISDNchannel *ch, struct sk_buff *skb) 667 { 668 struct bchannel *bch = container_of(ch, struct bchannel, ch); 669 struct fritzcard *fc = bch->hw; 670 int ret = -EINVAL; 671 struct mISDNhead *hh = mISDN_HEAD_P(skb); 672 unsigned long flags; 673 674 switch (hh->prim) { 675 case PH_DATA_REQ: 676 spin_lock_irqsave(&fc->lock, flags); 677 ret = bchannel_senddata(bch, skb); 678 if (ret > 0) { /* direct TX */ 679 hdlc_fill_fifo(bch); 680 ret = 0; 681 } 682 spin_unlock_irqrestore(&fc->lock, flags); 683 return ret; 684 case PH_ACTIVATE_REQ: 685 spin_lock_irqsave(&fc->lock, flags); 686 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags)) 687 ret = modehdlc(bch, ch->protocol); 688 else 689 ret = 0; 690 spin_unlock_irqrestore(&fc->lock, flags); 691 if (!ret) 692 _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0, 693 NULL, GFP_KERNEL); 694 break; 695 case PH_DEACTIVATE_REQ: 696 spin_lock_irqsave(&fc->lock, flags); 697 mISDN_clear_bchannel(bch); 698 modehdlc(bch, ISDN_P_NONE); 699 spin_unlock_irqrestore(&fc->lock, flags); 700 _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0, 701 NULL, GFP_KERNEL); 702 ret = 0; 703 break; 704 } 705 if (!ret) 706 dev_kfree_skb(skb); 707 return ret; 708 } 709 710 static void 711 inithdlc(struct fritzcard *fc) 712 { 713 modehdlc(&fc->bch[0], -1); 714 modehdlc(&fc->bch[1], -1); 715 } 716 717 void 718 clear_pending_hdlc_ints(struct fritzcard *fc) 719 { 720 u32 val; 721 722 val = read_status(fc, 1); 723 pr_debug("%s: HDLC 1 STA %x\n", fc->name, val); 724 val = read_status(fc, 2); 725 pr_debug("%s: HDLC 2 STA %x\n", fc->name, val); 726 } 727 728 static void 729 reset_avm(struct fritzcard *fc) 730 { 731 switch (fc->type) { 732 case AVM_FRITZ_PCI: 733 fc->ctrlreg = AVM_STATUS0_RESET | AVM_STATUS0_DIS_TIMER; 734 break; 735 case AVM_FRITZ_PCIV2: 736 fc->ctrlreg = AVM_STATUS0_RESET; 737 break; 738 } 739 if (debug & DEBUG_HW) 740 pr_notice("%s: reset\n", fc->name); 741 disable_hwirq(fc); 742 mdelay(5); 743 switch (fc->type) { 744 case AVM_FRITZ_PCI: 745 fc->ctrlreg = AVM_STATUS0_DIS_TIMER | AVM_STATUS0_RES_TIMER; 746 disable_hwirq(fc); 747 outb(AVM_STATUS1_ENA_IOM, fc->addr + 3); 748 break; 749 case AVM_FRITZ_PCIV2: 750 fc->ctrlreg = 0; 751 disable_hwirq(fc); 752 break; 753 } 754 mdelay(1); 755 if (debug & DEBUG_HW) 756 pr_notice("%s: S0/S1 %x/%x\n", fc->name, 757 inb(fc->addr + 2), inb(fc->addr + 3)); 758 } 759 760 static int 761 init_card(struct fritzcard *fc) 762 { 763 int ret, cnt = 3; 764 u_long flags; 765 766 reset_avm(fc); /* disable IRQ */ 767 if (fc->type == AVM_FRITZ_PCIV2) 768 ret = request_irq(fc->irq, avm_fritzv2_interrupt, 769 IRQF_SHARED, fc->name, fc); 770 else 771 ret = request_irq(fc->irq, avm_fritz_interrupt, 772 IRQF_SHARED, fc->name, fc); 773 if (ret) { 774 pr_info("%s: couldn't get interrupt %d\n", 775 fc->name, fc->irq); 776 return ret; 777 } 778 while (cnt--) { 779 spin_lock_irqsave(&fc->lock, flags); 780 ret = fc->isac.init(&fc->isac); 781 if (ret) { 782 spin_unlock_irqrestore(&fc->lock, flags); 783 pr_info("%s: ISAC init failed with %d\n", 784 fc->name, ret); 785 break; 786 } 787 clear_pending_hdlc_ints(fc); 788 inithdlc(fc); 789 enable_hwirq(fc); 790 /* RESET Receiver and Transmitter */ 791 if (fc->type == AVM_FRITZ_PCIV2) { 792 WriteISAC_V2(fc, ISACX_MASK, 0); 793 WriteISAC_V2(fc, ISACX_CMDRD, 0x41); 794 } else { 795 WriteISAC_V1(fc, ISAC_MASK, 0); 796 WriteISAC_V1(fc, ISAC_CMDR, 0x41); 797 } 798 spin_unlock_irqrestore(&fc->lock, flags); 799 /* Timeout 10ms */ 800 msleep_interruptible(10); 801 if (debug & DEBUG_HW) 802 pr_notice("%s: IRQ %d count %d\n", fc->name, 803 fc->irq, fc->irqcnt); 804 if (!fc->irqcnt) { 805 pr_info("%s: IRQ(%d) getting no IRQs during init %d\n", 806 fc->name, fc->irq, 3 - cnt); 807 reset_avm(fc); 808 } else 809 return 0; 810 } 811 free_irq(fc->irq, fc); 812 return -EIO; 813 } 814 815 static int 816 channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq) 817 { 818 int ret = 0; 819 struct fritzcard *fc = bch->hw; 820 821 switch (cq->op) { 822 case MISDN_CTRL_GETOP: 823 cq->op = 0; 824 break; 825 /* Nothing implemented yet */ 826 case MISDN_CTRL_FILL_EMPTY: 827 default: 828 pr_info("%s: %s unknown Op %x\n", fc->name, __func__, cq->op); 829 ret = -EINVAL; 830 break; 831 } 832 return ret; 833 } 834 835 static int 836 avm_bctrl(struct mISDNchannel *ch, u32 cmd, void *arg) 837 { 838 struct bchannel *bch = container_of(ch, struct bchannel, ch); 839 struct fritzcard *fc = bch->hw; 840 int ret = -EINVAL; 841 u_long flags; 842 843 pr_debug("%s: %s cmd:%x %p\n", fc->name, __func__, cmd, arg); 844 switch (cmd) { 845 case CLOSE_CHANNEL: 846 test_and_clear_bit(FLG_OPEN, &bch->Flags); 847 spin_lock_irqsave(&fc->lock, flags); 848 mISDN_freebchannel(bch); 849 modehdlc(bch, ISDN_P_NONE); 850 spin_unlock_irqrestore(&fc->lock, flags); 851 ch->protocol = ISDN_P_NONE; 852 ch->peer = NULL; 853 module_put(THIS_MODULE); 854 ret = 0; 855 break; 856 case CONTROL_CHANNEL: 857 ret = channel_bctrl(bch, arg); 858 break; 859 default: 860 pr_info("%s: %s unknown prim(%x)\n", fc->name, __func__, cmd); 861 } 862 return ret; 863 } 864 865 static int 866 channel_ctrl(struct fritzcard *fc, struct mISDN_ctrl_req *cq) 867 { 868 int ret = 0; 869 870 switch (cq->op) { 871 case MISDN_CTRL_GETOP: 872 cq->op = MISDN_CTRL_LOOP | MISDN_CTRL_L1_TIMER3; 873 break; 874 case MISDN_CTRL_LOOP: 875 /* cq->channel: 0 disable, 1 B1 loop 2 B2 loop, 3 both */ 876 if (cq->channel < 0 || cq->channel > 3) { 877 ret = -EINVAL; 878 break; 879 } 880 ret = fc->isac.ctrl(&fc->isac, HW_TESTLOOP, cq->channel); 881 break; 882 case MISDN_CTRL_L1_TIMER3: 883 ret = fc->isac.ctrl(&fc->isac, HW_TIMER3_VALUE, cq->p1); 884 break; 885 default: 886 pr_info("%s: %s unknown Op %x\n", fc->name, __func__, cq->op); 887 ret = -EINVAL; 888 break; 889 } 890 return ret; 891 } 892 893 static int 894 open_bchannel(struct fritzcard *fc, struct channel_req *rq) 895 { 896 struct bchannel *bch; 897 898 if (rq->adr.channel == 0 || rq->adr.channel > 2) 899 return -EINVAL; 900 if (rq->protocol == ISDN_P_NONE) 901 return -EINVAL; 902 bch = &fc->bch[rq->adr.channel - 1]; 903 if (test_and_set_bit(FLG_OPEN, &bch->Flags)) 904 return -EBUSY; /* b-channel can be only open once */ 905 test_and_clear_bit(FLG_FILLEMPTY, &bch->Flags); 906 bch->ch.protocol = rq->protocol; 907 rq->ch = &bch->ch; 908 return 0; 909 } 910 911 /* 912 * device control function 913 */ 914 static int 915 avm_dctrl(struct mISDNchannel *ch, u32 cmd, void *arg) 916 { 917 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D); 918 struct dchannel *dch = container_of(dev, struct dchannel, dev); 919 struct fritzcard *fc = dch->hw; 920 struct channel_req *rq; 921 int err = 0; 922 923 pr_debug("%s: %s cmd:%x %p\n", fc->name, __func__, cmd, arg); 924 switch (cmd) { 925 case OPEN_CHANNEL: 926 rq = arg; 927 if (rq->protocol == ISDN_P_TE_S0) 928 err = fc->isac.open(&fc->isac, rq); 929 else 930 err = open_bchannel(fc, rq); 931 if (err) 932 break; 933 if (!try_module_get(THIS_MODULE)) 934 pr_info("%s: cannot get module\n", fc->name); 935 break; 936 case CLOSE_CHANNEL: 937 pr_debug("%s: dev(%d) close from %p\n", fc->name, dch->dev.id, 938 __builtin_return_address(0)); 939 module_put(THIS_MODULE); 940 break; 941 case CONTROL_CHANNEL: 942 err = channel_ctrl(fc, arg); 943 break; 944 default: 945 pr_debug("%s: %s unknown command %x\n", 946 fc->name, __func__, cmd); 947 return -EINVAL; 948 } 949 return err; 950 } 951 952 int 953 setup_fritz(struct fritzcard *fc) 954 { 955 u32 val, ver; 956 957 if (!request_region(fc->addr, 32, fc->name)) { 958 pr_info("%s: AVM config port %x-%x already in use\n", 959 fc->name, fc->addr, fc->addr + 31); 960 return -EIO; 961 } 962 switch (fc->type) { 963 case AVM_FRITZ_PCI: 964 val = inl(fc->addr); 965 outl(AVM_HDLC_1, fc->addr + CHIP_INDEX); 966 ver = inl(fc->addr + CHIP_WINDOW + HDLC_STATUS) >> 24; 967 if (debug & DEBUG_HW) { 968 pr_notice("%s: PCI stat %#x\n", fc->name, val); 969 pr_notice("%s: PCI Class %X Rev %d\n", fc->name, 970 val & 0xff, (val >> 8) & 0xff); 971 pr_notice("%s: HDLC version %x\n", fc->name, ver & 0xf); 972 } 973 ASSIGN_FUNC(V1, ISAC, fc->isac); 974 fc->isac.type = IPAC_TYPE_ISAC; 975 break; 976 case AVM_FRITZ_PCIV2: 977 val = inl(fc->addr); 978 ver = inl(fc->addr + AVM_HDLC_STATUS_1) >> 24; 979 if (debug & DEBUG_HW) { 980 pr_notice("%s: PCI V2 stat %#x\n", fc->name, val); 981 pr_notice("%s: PCI V2 Class %X Rev %d\n", fc->name, 982 val & 0xff, (val >> 8) & 0xff); 983 pr_notice("%s: HDLC version %x\n", fc->name, ver & 0xf); 984 } 985 ASSIGN_FUNC(V2, ISAC, fc->isac); 986 fc->isac.type = IPAC_TYPE_ISACX; 987 break; 988 default: 989 release_region(fc->addr, 32); 990 pr_info("%s: AVM unknown type %d\n", fc->name, fc->type); 991 return -ENODEV; 992 } 993 pr_notice("%s: %s config irq:%d base:0x%X\n", fc->name, 994 (fc->type == AVM_FRITZ_PCI) ? "AVM Fritz!CARD PCI" : 995 "AVM Fritz!CARD PCIv2", fc->irq, fc->addr); 996 return 0; 997 } 998 999 static void 1000 release_card(struct fritzcard *card) 1001 { 1002 u_long flags; 1003 1004 disable_hwirq(card); 1005 spin_lock_irqsave(&card->lock, flags); 1006 modehdlc(&card->bch[0], ISDN_P_NONE); 1007 modehdlc(&card->bch[1], ISDN_P_NONE); 1008 spin_unlock_irqrestore(&card->lock, flags); 1009 card->isac.release(&card->isac); 1010 free_irq(card->irq, card); 1011 mISDN_freebchannel(&card->bch[1]); 1012 mISDN_freebchannel(&card->bch[0]); 1013 mISDN_unregister_device(&card->isac.dch.dev); 1014 release_region(card->addr, 32); 1015 pci_disable_device(card->pdev); 1016 pci_set_drvdata(card->pdev, NULL); 1017 write_lock_irqsave(&card_lock, flags); 1018 list_del(&card->list); 1019 write_unlock_irqrestore(&card_lock, flags); 1020 kfree(card); 1021 AVM_cnt--; 1022 } 1023 1024 static int __devinit 1025 setup_instance(struct fritzcard *card) 1026 { 1027 int i, err; 1028 u_long flags; 1029 1030 snprintf(card->name, MISDN_MAX_IDLEN - 1, "AVM.%d", AVM_cnt + 1); 1031 write_lock_irqsave(&card_lock, flags); 1032 list_add_tail(&card->list, &Cards); 1033 write_unlock_irqrestore(&card_lock, flags); 1034 1035 _set_debug(card); 1036 card->isac.name = card->name; 1037 spin_lock_init(&card->lock); 1038 card->isac.hwlock = &card->lock; 1039 mISDNisac_init(&card->isac, card); 1040 1041 card->isac.dch.dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) | 1042 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK)); 1043 card->isac.dch.dev.D.ctrl = avm_dctrl; 1044 for (i = 0; i < 2; i++) { 1045 card->bch[i].nr = i + 1; 1046 set_channelmap(i + 1, card->isac.dch.dev.channelmap); 1047 mISDN_initbchannel(&card->bch[i], MAX_DATA_MEM); 1048 card->bch[i].hw = card; 1049 card->bch[i].ch.send = avm_l2l1B; 1050 card->bch[i].ch.ctrl = avm_bctrl; 1051 card->bch[i].ch.nr = i + 1; 1052 list_add(&card->bch[i].ch.list, &card->isac.dch.dev.bchannels); 1053 } 1054 err = setup_fritz(card); 1055 if (err) 1056 goto error; 1057 err = mISDN_register_device(&card->isac.dch.dev, &card->pdev->dev, 1058 card->name); 1059 if (err) 1060 goto error_reg; 1061 err = init_card(card); 1062 if (!err) { 1063 AVM_cnt++; 1064 pr_notice("AVM %d cards installed DEBUG\n", AVM_cnt); 1065 return 0; 1066 } 1067 mISDN_unregister_device(&card->isac.dch.dev); 1068 error_reg: 1069 release_region(card->addr, 32); 1070 error: 1071 card->isac.release(&card->isac); 1072 mISDN_freebchannel(&card->bch[1]); 1073 mISDN_freebchannel(&card->bch[0]); 1074 write_lock_irqsave(&card_lock, flags); 1075 list_del(&card->list); 1076 write_unlock_irqrestore(&card_lock, flags); 1077 kfree(card); 1078 return err; 1079 } 1080 1081 static int __devinit 1082 fritzpci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1083 { 1084 int err = -ENOMEM; 1085 struct fritzcard *card; 1086 1087 card = kzalloc(sizeof(struct fritzcard), GFP_KERNEL); 1088 if (!card) { 1089 pr_info("No kmem for fritzcard\n"); 1090 return err; 1091 } 1092 if (pdev->device == PCI_DEVICE_ID_AVM_A1_V2) 1093 card->type = AVM_FRITZ_PCIV2; 1094 else 1095 card->type = AVM_FRITZ_PCI; 1096 card->pdev = pdev; 1097 err = pci_enable_device(pdev); 1098 if (err) { 1099 kfree(card); 1100 return err; 1101 } 1102 1103 pr_notice("mISDN: found adapter %s at %s\n", 1104 (char *) ent->driver_data, pci_name(pdev)); 1105 1106 card->addr = pci_resource_start(pdev, 1); 1107 card->irq = pdev->irq; 1108 pci_set_drvdata(pdev, card); 1109 err = setup_instance(card); 1110 if (err) 1111 pci_set_drvdata(pdev, NULL); 1112 return err; 1113 } 1114 1115 static void __devexit 1116 fritz_remove_pci(struct pci_dev *pdev) 1117 { 1118 struct fritzcard *card = pci_get_drvdata(pdev); 1119 1120 if (card) 1121 release_card(card); 1122 else 1123 if (debug) 1124 pr_info("%s: drvdata already removed\n", __func__); 1125 } 1126 1127 static struct pci_device_id fcpci_ids[] __devinitdata = { 1128 { PCI_VENDOR_ID_AVM, PCI_DEVICE_ID_AVM_A1, PCI_ANY_ID, PCI_ANY_ID, 1129 0, 0, (unsigned long) "Fritz!Card PCI"}, 1130 { PCI_VENDOR_ID_AVM, PCI_DEVICE_ID_AVM_A1_V2, PCI_ANY_ID, PCI_ANY_ID, 1131 0, 0, (unsigned long) "Fritz!Card PCI v2" }, 1132 { } 1133 }; 1134 MODULE_DEVICE_TABLE(pci, fcpci_ids); 1135 1136 static struct pci_driver fcpci_driver = { 1137 .name = "fcpci", 1138 .probe = fritzpci_probe, 1139 .remove = __devexit_p(fritz_remove_pci), 1140 .id_table = fcpci_ids, 1141 }; 1142 1143 static int __init AVM_init(void) 1144 { 1145 int err; 1146 1147 pr_notice("AVM Fritz PCI driver Rev. %s\n", AVMFRITZ_REV); 1148 err = pci_register_driver(&fcpci_driver); 1149 return err; 1150 } 1151 1152 static void __exit AVM_cleanup(void) 1153 { 1154 pci_unregister_driver(&fcpci_driver); 1155 } 1156 1157 module_init(AVM_init); 1158 module_exit(AVM_cleanup); 1159