1 /* 2 * Copyright (C) 2017 Marvell 3 * 4 * Hanna Hawa <hannah@marvell.com> 5 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 6 * 7 * This file is licensed under the terms of the GNU General Public 8 * License version 2. This program is licensed "as is" without any 9 * warranty of any kind, whether express or implied. 10 */ 11 12 #include <linux/interrupt.h> 13 #include <linux/irq.h> 14 #include <linux/irqchip.h> 15 #include <linux/irqdomain.h> 16 #include <linux/jump_label.h> 17 #include <linux/kernel.h> 18 #include <linux/msi.h> 19 #include <linux/of_irq.h> 20 #include <linux/of_platform.h> 21 #include <linux/platform_device.h> 22 23 #include <dt-bindings/interrupt-controller/mvebu-icu.h> 24 25 /* ICU registers */ 26 #define ICU_SETSPI_NSR_AL 0x10 27 #define ICU_SETSPI_NSR_AH 0x14 28 #define ICU_CLRSPI_NSR_AL 0x18 29 #define ICU_CLRSPI_NSR_AH 0x1c 30 #define ICU_INT_CFG(x) (0x100 + 4 * (x)) 31 #define ICU_INT_ENABLE BIT(24) 32 #define ICU_IS_EDGE BIT(28) 33 #define ICU_GROUP_SHIFT 29 34 35 /* ICU definitions */ 36 #define ICU_MAX_IRQS 207 37 #define ICU_SATA0_ICU_ID 109 38 #define ICU_SATA1_ICU_ID 107 39 40 struct mvebu_icu { 41 struct irq_chip irq_chip; 42 void __iomem *base; 43 struct device *dev; 44 atomic_t initialized; 45 }; 46 47 struct mvebu_icu_irq_data { 48 struct mvebu_icu *icu; 49 unsigned int icu_group; 50 unsigned int type; 51 }; 52 53 DEFINE_STATIC_KEY_FALSE(legacy_bindings); 54 55 static void mvebu_icu_init(struct mvebu_icu *icu, struct msi_msg *msg) 56 { 57 if (atomic_cmpxchg(&icu->initialized, false, true)) 58 return; 59 60 /* Set Clear/Set ICU SPI message address in AP */ 61 writel_relaxed(msg[0].address_hi, icu->base + ICU_SETSPI_NSR_AH); 62 writel_relaxed(msg[0].address_lo, icu->base + ICU_SETSPI_NSR_AL); 63 writel_relaxed(msg[1].address_hi, icu->base + ICU_CLRSPI_NSR_AH); 64 writel_relaxed(msg[1].address_lo, icu->base + ICU_CLRSPI_NSR_AL); 65 } 66 67 static void mvebu_icu_write_msg(struct msi_desc *desc, struct msi_msg *msg) 68 { 69 struct irq_data *d = irq_get_irq_data(desc->irq); 70 struct mvebu_icu_irq_data *icu_irqd = d->chip_data; 71 struct mvebu_icu *icu = icu_irqd->icu; 72 unsigned int icu_int; 73 74 if (msg->address_lo || msg->address_hi) { 75 /* One off initialization */ 76 mvebu_icu_init(icu, msg); 77 /* Configure the ICU with irq number & type */ 78 icu_int = msg->data | ICU_INT_ENABLE; 79 if (icu_irqd->type & IRQ_TYPE_EDGE_RISING) 80 icu_int |= ICU_IS_EDGE; 81 icu_int |= icu_irqd->icu_group << ICU_GROUP_SHIFT; 82 } else { 83 /* De-configure the ICU */ 84 icu_int = 0; 85 } 86 87 writel_relaxed(icu_int, icu->base + ICU_INT_CFG(d->hwirq)); 88 89 /* 90 * The SATA unit has 2 ports, and a dedicated ICU entry per 91 * port. The ahci sata driver supports only one irq interrupt 92 * per SATA unit. To solve this conflict, we configure the 2 93 * SATA wired interrupts in the south bridge into 1 GIC 94 * interrupt in the north bridge. Even if only a single port 95 * is enabled, if sata node is enabled, both interrupts are 96 * configured (regardless of which port is actually in use). 97 */ 98 if (d->hwirq == ICU_SATA0_ICU_ID || d->hwirq == ICU_SATA1_ICU_ID) { 99 writel_relaxed(icu_int, 100 icu->base + ICU_INT_CFG(ICU_SATA0_ICU_ID)); 101 writel_relaxed(icu_int, 102 icu->base + ICU_INT_CFG(ICU_SATA1_ICU_ID)); 103 } 104 } 105 106 static int 107 mvebu_icu_irq_domain_translate(struct irq_domain *d, struct irq_fwspec *fwspec, 108 unsigned long *hwirq, unsigned int *type) 109 { 110 struct mvebu_icu *icu = platform_msi_get_host_data(d); 111 unsigned int param_count = static_branch_unlikely(&legacy_bindings) ? 3 : 2; 112 113 /* Check the count of the parameters in dt */ 114 if (WARN_ON(fwspec->param_count != param_count)) { 115 dev_err(icu->dev, "wrong ICU parameter count %d\n", 116 fwspec->param_count); 117 return -EINVAL; 118 } 119 120 if (static_branch_unlikely(&legacy_bindings)) { 121 *hwirq = fwspec->param[1]; 122 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; 123 if (fwspec->param[0] != ICU_GRP_NSR) { 124 dev_err(icu->dev, "wrong ICU group type %x\n", 125 fwspec->param[0]); 126 return -EINVAL; 127 } 128 } else { 129 *hwirq = fwspec->param[0]; 130 *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK; 131 } 132 133 if (*hwirq >= ICU_MAX_IRQS) { 134 dev_err(icu->dev, "invalid interrupt number %ld\n", *hwirq); 135 return -EINVAL; 136 } 137 138 return 0; 139 } 140 141 static int 142 mvebu_icu_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 143 unsigned int nr_irqs, void *args) 144 { 145 int err; 146 unsigned long hwirq; 147 struct irq_fwspec *fwspec = args; 148 struct mvebu_icu *icu = platform_msi_get_host_data(domain); 149 struct mvebu_icu_irq_data *icu_irqd; 150 151 icu_irqd = kmalloc(sizeof(*icu_irqd), GFP_KERNEL); 152 if (!icu_irqd) 153 return -ENOMEM; 154 155 err = mvebu_icu_irq_domain_translate(domain, fwspec, &hwirq, 156 &icu_irqd->type); 157 if (err) { 158 dev_err(icu->dev, "failed to translate ICU parameters\n"); 159 goto free_irqd; 160 } 161 162 if (static_branch_unlikely(&legacy_bindings)) 163 icu_irqd->icu_group = fwspec->param[0]; 164 else 165 icu_irqd->icu_group = ICU_GRP_NSR; 166 icu_irqd->icu = icu; 167 168 err = platform_msi_domain_alloc(domain, virq, nr_irqs); 169 if (err) { 170 dev_err(icu->dev, "failed to allocate ICU interrupt in parent domain\n"); 171 goto free_irqd; 172 } 173 174 /* Make sure there is no interrupt left pending by the firmware */ 175 err = irq_set_irqchip_state(virq, IRQCHIP_STATE_PENDING, false); 176 if (err) 177 goto free_msi; 178 179 err = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, 180 &icu->irq_chip, icu_irqd); 181 if (err) { 182 dev_err(icu->dev, "failed to set the data to IRQ domain\n"); 183 goto free_msi; 184 } 185 186 return 0; 187 188 free_msi: 189 platform_msi_domain_free(domain, virq, nr_irqs); 190 free_irqd: 191 kfree(icu_irqd); 192 return err; 193 } 194 195 static void 196 mvebu_icu_irq_domain_free(struct irq_domain *domain, unsigned int virq, 197 unsigned int nr_irqs) 198 { 199 struct irq_data *d = irq_get_irq_data(virq); 200 struct mvebu_icu_irq_data *icu_irqd = d->chip_data; 201 202 kfree(icu_irqd); 203 204 platform_msi_domain_free(domain, virq, nr_irqs); 205 } 206 207 static const struct irq_domain_ops mvebu_icu_domain_ops = { 208 .translate = mvebu_icu_irq_domain_translate, 209 .alloc = mvebu_icu_irq_domain_alloc, 210 .free = mvebu_icu_irq_domain_free, 211 }; 212 213 static const struct of_device_id mvebu_icu_subset_of_match[] = { 214 { 215 .compatible = "marvell,cp110-icu-nsr", 216 }, 217 {}, 218 }; 219 220 static int mvebu_icu_subset_probe(struct platform_device *pdev) 221 { 222 struct device_node *msi_parent_dn; 223 struct device *dev = &pdev->dev; 224 struct irq_domain *irq_domain; 225 struct mvebu_icu *icu; 226 227 if (static_branch_unlikely(&legacy_bindings)) 228 icu = dev_get_drvdata(dev); 229 else 230 icu = dev_get_drvdata(dev->parent); 231 232 dev->msi_domain = of_msi_get_domain(dev, dev->of_node, 233 DOMAIN_BUS_PLATFORM_MSI); 234 if (!dev->msi_domain) 235 return -EPROBE_DEFER; 236 237 msi_parent_dn = irq_domain_get_of_node(dev->msi_domain); 238 if (!msi_parent_dn) 239 return -ENODEV; 240 241 irq_domain = platform_msi_create_device_tree_domain(dev, ICU_MAX_IRQS, 242 mvebu_icu_write_msg, 243 &mvebu_icu_domain_ops, 244 icu); 245 if (!irq_domain) { 246 dev_err(dev, "Failed to create ICU MSI domain\n"); 247 return -ENOMEM; 248 } 249 250 return 0; 251 } 252 253 static struct platform_driver mvebu_icu_subset_driver = { 254 .probe = mvebu_icu_subset_probe, 255 .driver = { 256 .name = "mvebu-icu-subset", 257 .of_match_table = mvebu_icu_subset_of_match, 258 }, 259 }; 260 builtin_platform_driver(mvebu_icu_subset_driver); 261 262 static int mvebu_icu_probe(struct platform_device *pdev) 263 { 264 struct mvebu_icu *icu; 265 struct resource *res; 266 int i; 267 268 icu = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_icu), 269 GFP_KERNEL); 270 if (!icu) 271 return -ENOMEM; 272 273 icu->dev = &pdev->dev; 274 275 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 276 icu->base = devm_ioremap_resource(&pdev->dev, res); 277 if (IS_ERR(icu->base)) { 278 dev_err(&pdev->dev, "Failed to map icu base address.\n"); 279 return PTR_ERR(icu->base); 280 } 281 282 icu->irq_chip.name = devm_kasprintf(&pdev->dev, GFP_KERNEL, 283 "ICU.%x", 284 (unsigned int)res->start); 285 if (!icu->irq_chip.name) 286 return -ENOMEM; 287 288 /* 289 * Legacy bindings: ICU is one node with one MSI parent: force manually 290 * the probe of the NSR interrupts side. 291 * New bindings: ICU node has children, one per interrupt controller 292 * having its own MSI parent: call platform_populate(). 293 * All ICU instances should use the same bindings. 294 */ 295 if (!of_get_child_count(pdev->dev.of_node)) 296 static_branch_enable(&legacy_bindings); 297 298 icu->irq_chip.irq_mask = irq_chip_mask_parent; 299 icu->irq_chip.irq_unmask = irq_chip_unmask_parent; 300 icu->irq_chip.irq_eoi = irq_chip_eoi_parent; 301 icu->irq_chip.irq_set_type = irq_chip_set_type_parent; 302 #ifdef CONFIG_SMP 303 icu->irq_chip.irq_set_affinity = irq_chip_set_affinity_parent; 304 #endif 305 306 /* 307 * Clean all ICU interrupts with type SPI_NSR, required to 308 * avoid unpredictable SPI assignments done by firmware. 309 */ 310 for (i = 0 ; i < ICU_MAX_IRQS ; i++) { 311 u32 icu_int, icu_grp; 312 313 icu_int = readl_relaxed(icu->base + ICU_INT_CFG(i)); 314 icu_grp = icu_int >> ICU_GROUP_SHIFT; 315 316 if (icu_grp == ICU_GRP_NSR || 317 (icu_grp == ICU_GRP_SEI && 318 !static_branch_unlikely(&legacy_bindings))) 319 writel_relaxed(0x0, icu->base + ICU_INT_CFG(i)); 320 } 321 322 platform_set_drvdata(pdev, icu); 323 324 if (static_branch_unlikely(&legacy_bindings)) 325 return mvebu_icu_subset_probe(pdev); 326 else 327 return devm_of_platform_populate(&pdev->dev); 328 } 329 330 static const struct of_device_id mvebu_icu_of_match[] = { 331 { .compatible = "marvell,cp110-icu", }, 332 {}, 333 }; 334 335 static struct platform_driver mvebu_icu_driver = { 336 .probe = mvebu_icu_probe, 337 .driver = { 338 .name = "mvebu-icu", 339 .of_match_table = mvebu_icu_of_match, 340 }, 341 }; 342 builtin_platform_driver(mvebu_icu_driver); 343