xref: /openbmc/linux/drivers/irqchip/irq-crossbar.c (revision 8b09a45dc12f83f2312a47f0f0087ec4004ebacc)
196ca848eSSricharan R /*
296ca848eSSricharan R  *  drivers/irqchip/irq-crossbar.c
396ca848eSSricharan R  *
496ca848eSSricharan R  *  Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
596ca848eSSricharan R  *  Author: Sricharan R <r.sricharan@ti.com>
696ca848eSSricharan R  *
796ca848eSSricharan R  * This program is free software; you can redistribute it and/or modify
896ca848eSSricharan R  * it under the terms of the GNU General Public License version 2 as
996ca848eSSricharan R  * published by the Free Software Foundation.
1096ca848eSSricharan R  *
1196ca848eSSricharan R  */
1296ca848eSSricharan R #include <linux/err.h>
1396ca848eSSricharan R #include <linux/io.h>
1496ca848eSSricharan R #include <linux/of_address.h>
1596ca848eSSricharan R #include <linux/of_irq.h>
1696ca848eSSricharan R #include <linux/slab.h>
1796ca848eSSricharan R #include <linux/irqchip/arm-gic.h>
184dbf45e3SNishanth Menon #include <linux/irqchip/irq-crossbar.h>
1996ca848eSSricharan R 
2096ca848eSSricharan R #define IRQ_FREE	-1
211d50d2ceSNishanth Menon #define IRQ_RESERVED	-2
2264e0f8baSNishanth Menon #define IRQ_SKIP	-3
2396ca848eSSricharan R #define GIC_IRQ_START	32
2496ca848eSSricharan R 
25e30ef8abSNishanth Menon /**
26e30ef8abSNishanth Menon  * struct crossbar_device - crossbar device description
2796ca848eSSricharan R  * @int_max: maximum number of supported interrupts
28a35057d1SNishanth Menon  * @safe_map: safe default value to initialize the crossbar
2996ca848eSSricharan R  * @irq_map: array of interrupts to crossbar number mapping
3096ca848eSSricharan R  * @crossbar_base: crossbar base address
3196ca848eSSricharan R  * @register_offsets: offsets for each irq number
32e30ef8abSNishanth Menon  * @write: register write function pointer
3396ca848eSSricharan R  */
3496ca848eSSricharan R struct crossbar_device {
3596ca848eSSricharan R 	uint int_max;
36a35057d1SNishanth Menon 	uint safe_map;
3796ca848eSSricharan R 	uint *irq_map;
3896ca848eSSricharan R 	void __iomem *crossbar_base;
3996ca848eSSricharan R 	int *register_offsets;
4096ca848eSSricharan R 	void (*write)(int, int);
4196ca848eSSricharan R };
4296ca848eSSricharan R 
4396ca848eSSricharan R static struct crossbar_device *cb;
4496ca848eSSricharan R 
4596ca848eSSricharan R static inline void crossbar_writel(int irq_no, int cb_no)
4696ca848eSSricharan R {
4796ca848eSSricharan R 	writel(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
4896ca848eSSricharan R }
4996ca848eSSricharan R 
5096ca848eSSricharan R static inline void crossbar_writew(int irq_no, int cb_no)
5196ca848eSSricharan R {
5296ca848eSSricharan R 	writew(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
5396ca848eSSricharan R }
5496ca848eSSricharan R 
5596ca848eSSricharan R static inline void crossbar_writeb(int irq_no, int cb_no)
5696ca848eSSricharan R {
5796ca848eSSricharan R 	writeb(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
5896ca848eSSricharan R }
5996ca848eSSricharan R 
606f16fc87SNishanth Menon static inline int get_prev_map_irq(int cb_no)
616f16fc87SNishanth Menon {
626f16fc87SNishanth Menon 	int i;
636f16fc87SNishanth Menon 
64ddee0fb4SNishanth Menon 	for (i = cb->int_max - 1; i >= 0; i--)
656f16fc87SNishanth Menon 		if (cb->irq_map[i] == cb_no)
666f16fc87SNishanth Menon 			return i;
676f16fc87SNishanth Menon 
686f16fc87SNishanth Menon 	return -ENODEV;
696f16fc87SNishanth Menon }
706f16fc87SNishanth Menon 
7196ca848eSSricharan R static inline int allocate_free_irq(int cb_no)
7296ca848eSSricharan R {
7396ca848eSSricharan R 	int i;
7496ca848eSSricharan R 
75ddee0fb4SNishanth Menon 	for (i = cb->int_max - 1; i >= 0; i--) {
7696ca848eSSricharan R 		if (cb->irq_map[i] == IRQ_FREE) {
7796ca848eSSricharan R 			cb->irq_map[i] = cb_no;
7896ca848eSSricharan R 			return i;
7996ca848eSSricharan R 		}
8096ca848eSSricharan R 	}
8196ca848eSSricharan R 
8296ca848eSSricharan R 	return -ENODEV;
8396ca848eSSricharan R }
8496ca848eSSricharan R 
8596ca848eSSricharan R static int crossbar_domain_map(struct irq_domain *d, unsigned int irq,
8696ca848eSSricharan R 			       irq_hw_number_t hw)
8796ca848eSSricharan R {
8896ca848eSSricharan R 	cb->write(hw - GIC_IRQ_START, cb->irq_map[hw - GIC_IRQ_START]);
8996ca848eSSricharan R 	return 0;
9096ca848eSSricharan R }
9196ca848eSSricharan R 
92*8b09a45dSSricharan R /**
93*8b09a45dSSricharan R  * crossbar_domain_unmap - unmap a crossbar<->irq connection
94*8b09a45dSSricharan R  * @d: domain of irq to unmap
95*8b09a45dSSricharan R  * @irq: virq number
96*8b09a45dSSricharan R  *
97*8b09a45dSSricharan R  * We do not maintain a use count of total number of map/unmap
98*8b09a45dSSricharan R  * calls for a particular irq to find out if a irq can be really
99*8b09a45dSSricharan R  * unmapped. This is because unmap is called during irq_dispose_mapping(irq),
100*8b09a45dSSricharan R  * after which irq is anyways unusable. So an explicit map has to be called
101*8b09a45dSSricharan R  * after that.
102*8b09a45dSSricharan R  */
10396ca848eSSricharan R static void crossbar_domain_unmap(struct irq_domain *d, unsigned int irq)
10496ca848eSSricharan R {
10596ca848eSSricharan R 	irq_hw_number_t hw = irq_get_irq_data(irq)->hwirq;
10696ca848eSSricharan R 
107a35057d1SNishanth Menon 	if (hw > GIC_IRQ_START) {
10896ca848eSSricharan R 		cb->irq_map[hw - GIC_IRQ_START] = IRQ_FREE;
109a35057d1SNishanth Menon 		cb->write(hw - GIC_IRQ_START, cb->safe_map);
110a35057d1SNishanth Menon 	}
11196ca848eSSricharan R }
11296ca848eSSricharan R 
11396ca848eSSricharan R static int crossbar_domain_xlate(struct irq_domain *d,
11496ca848eSSricharan R 				 struct device_node *controller,
11596ca848eSSricharan R 				 const u32 *intspec, unsigned int intsize,
11696ca848eSSricharan R 				 unsigned long *out_hwirq,
11796ca848eSSricharan R 				 unsigned int *out_type)
11896ca848eSSricharan R {
119d4922a95SNishanth Menon 	int ret;
12096ca848eSSricharan R 
1216f16fc87SNishanth Menon 	ret = get_prev_map_irq(intspec[1]);
122d4922a95SNishanth Menon 	if (ret >= 0)
1236f16fc87SNishanth Menon 		goto found;
1246f16fc87SNishanth Menon 
12596ca848eSSricharan R 	ret = allocate_free_irq(intspec[1]);
12696ca848eSSricharan R 
127d4922a95SNishanth Menon 	if (ret < 0)
12896ca848eSSricharan R 		return ret;
12996ca848eSSricharan R 
1306f16fc87SNishanth Menon found:
13196ca848eSSricharan R 	*out_hwirq = ret + GIC_IRQ_START;
13296ca848eSSricharan R 	return 0;
13396ca848eSSricharan R }
13496ca848eSSricharan R 
1354dbf45e3SNishanth Menon static const struct irq_domain_ops routable_irq_domain_ops = {
13696ca848eSSricharan R 	.map = crossbar_domain_map,
13796ca848eSSricharan R 	.unmap = crossbar_domain_unmap,
13896ca848eSSricharan R 	.xlate = crossbar_domain_xlate
13996ca848eSSricharan R };
14096ca848eSSricharan R 
14196ca848eSSricharan R static int __init crossbar_of_init(struct device_node *node)
14296ca848eSSricharan R {
143edb442deSNishanth Menon 	int i, size, max = 0, reserved = 0, entry;
14496ca848eSSricharan R 	const __be32 *irqsr;
145edb442deSNishanth Menon 	int ret = -ENOMEM;
14696ca848eSSricharan R 
1473894e9e8SDan Carpenter 	cb = kzalloc(sizeof(*cb), GFP_KERNEL);
14896ca848eSSricharan R 
14996ca848eSSricharan R 	if (!cb)
150edb442deSNishanth Menon 		return ret;
15196ca848eSSricharan R 
15296ca848eSSricharan R 	cb->crossbar_base = of_iomap(node, 0);
15396ca848eSSricharan R 	if (!cb->crossbar_base)
1543c44d515SNishanth Menon 		goto err_cb;
15596ca848eSSricharan R 
15696ca848eSSricharan R 	of_property_read_u32(node, "ti,max-irqs", &max);
157edb442deSNishanth Menon 	if (!max) {
158edb442deSNishanth Menon 		pr_err("missing 'ti,max-irqs' property\n");
159edb442deSNishanth Menon 		ret = -EINVAL;
1603c44d515SNishanth Menon 		goto err_base;
161edb442deSNishanth Menon 	}
1624dbf45e3SNishanth Menon 	cb->irq_map = kcalloc(max, sizeof(int), GFP_KERNEL);
16396ca848eSSricharan R 	if (!cb->irq_map)
1643c44d515SNishanth Menon 		goto err_base;
16596ca848eSSricharan R 
16696ca848eSSricharan R 	cb->int_max = max;
16796ca848eSSricharan R 
16896ca848eSSricharan R 	for (i = 0; i < max; i++)
16996ca848eSSricharan R 		cb->irq_map[i] = IRQ_FREE;
17096ca848eSSricharan R 
17196ca848eSSricharan R 	/* Get and mark reserved irqs */
17296ca848eSSricharan R 	irqsr = of_get_property(node, "ti,irqs-reserved", &size);
17396ca848eSSricharan R 	if (irqsr) {
17496ca848eSSricharan R 		size /= sizeof(__be32);
17596ca848eSSricharan R 
17696ca848eSSricharan R 		for (i = 0; i < size; i++) {
17796ca848eSSricharan R 			of_property_read_u32_index(node,
17896ca848eSSricharan R 						   "ti,irqs-reserved",
17996ca848eSSricharan R 						   i, &entry);
18096ca848eSSricharan R 			if (entry > max) {
18196ca848eSSricharan R 				pr_err("Invalid reserved entry\n");
182edb442deSNishanth Menon 				ret = -EINVAL;
1833c44d515SNishanth Menon 				goto err_irq_map;
18496ca848eSSricharan R 			}
1851d50d2ceSNishanth Menon 			cb->irq_map[entry] = IRQ_RESERVED;
18696ca848eSSricharan R 		}
18796ca848eSSricharan R 	}
18896ca848eSSricharan R 
18964e0f8baSNishanth Menon 	/* Skip irqs hardwired to bypass the crossbar */
19064e0f8baSNishanth Menon 	irqsr = of_get_property(node, "ti,irqs-skip", &size);
19164e0f8baSNishanth Menon 	if (irqsr) {
19264e0f8baSNishanth Menon 		size /= sizeof(__be32);
19364e0f8baSNishanth Menon 
19464e0f8baSNishanth Menon 		for (i = 0; i < size; i++) {
19564e0f8baSNishanth Menon 			of_property_read_u32_index(node,
19664e0f8baSNishanth Menon 						   "ti,irqs-skip",
19764e0f8baSNishanth Menon 						   i, &entry);
19864e0f8baSNishanth Menon 			if (entry > max) {
19964e0f8baSNishanth Menon 				pr_err("Invalid skip entry\n");
20064e0f8baSNishanth Menon 				ret = -EINVAL;
2013c44d515SNishanth Menon 				goto err_irq_map;
20264e0f8baSNishanth Menon 			}
20364e0f8baSNishanth Menon 			cb->irq_map[entry] = IRQ_SKIP;
20464e0f8baSNishanth Menon 		}
20564e0f8baSNishanth Menon 	}
20664e0f8baSNishanth Menon 
20764e0f8baSNishanth Menon 
2084dbf45e3SNishanth Menon 	cb->register_offsets = kcalloc(max, sizeof(int), GFP_KERNEL);
20996ca848eSSricharan R 	if (!cb->register_offsets)
2103c44d515SNishanth Menon 		goto err_irq_map;
21196ca848eSSricharan R 
21296ca848eSSricharan R 	of_property_read_u32(node, "ti,reg-size", &size);
21396ca848eSSricharan R 
21496ca848eSSricharan R 	switch (size) {
21596ca848eSSricharan R 	case 1:
21696ca848eSSricharan R 		cb->write = crossbar_writeb;
21796ca848eSSricharan R 		break;
21896ca848eSSricharan R 	case 2:
21996ca848eSSricharan R 		cb->write = crossbar_writew;
22096ca848eSSricharan R 		break;
22196ca848eSSricharan R 	case 4:
22296ca848eSSricharan R 		cb->write = crossbar_writel;
22396ca848eSSricharan R 		break;
22496ca848eSSricharan R 	default:
22596ca848eSSricharan R 		pr_err("Invalid reg-size property\n");
226edb442deSNishanth Menon 		ret = -EINVAL;
2273c44d515SNishanth Menon 		goto err_reg_offset;
22896ca848eSSricharan R 		break;
22996ca848eSSricharan R 	}
23096ca848eSSricharan R 
23196ca848eSSricharan R 	/*
23296ca848eSSricharan R 	 * Register offsets are not linear because of the
23396ca848eSSricharan R 	 * reserved irqs. so find and store the offsets once.
23496ca848eSSricharan R 	 */
23596ca848eSSricharan R 	for (i = 0; i < max; i++) {
2361d50d2ceSNishanth Menon 		if (cb->irq_map[i] == IRQ_RESERVED)
23796ca848eSSricharan R 			continue;
23896ca848eSSricharan R 
23996ca848eSSricharan R 		cb->register_offsets[i] = reserved;
24096ca848eSSricharan R 		reserved += size;
24196ca848eSSricharan R 	}
24296ca848eSSricharan R 
243a35057d1SNishanth Menon 	of_property_read_u32(node, "ti,irqs-safe-map", &cb->safe_map);
244a35057d1SNishanth Menon 	/* Initialize the crossbar with safe map to start with */
245a35057d1SNishanth Menon 	for (i = 0; i < max; i++) {
246a35057d1SNishanth Menon 		if (cb->irq_map[i] == IRQ_RESERVED ||
247a35057d1SNishanth Menon 		    cb->irq_map[i] == IRQ_SKIP)
248a35057d1SNishanth Menon 			continue;
249a35057d1SNishanth Menon 
250a35057d1SNishanth Menon 		cb->write(i, cb->safe_map);
251a35057d1SNishanth Menon 	}
252a35057d1SNishanth Menon 
25396ca848eSSricharan R 	register_routable_domain_ops(&routable_irq_domain_ops);
25496ca848eSSricharan R 	return 0;
25596ca848eSSricharan R 
2563c44d515SNishanth Menon err_reg_offset:
25796ca848eSSricharan R 	kfree(cb->register_offsets);
2583c44d515SNishanth Menon err_irq_map:
25996ca848eSSricharan R 	kfree(cb->irq_map);
2603c44d515SNishanth Menon err_base:
26196ca848eSSricharan R 	iounmap(cb->crossbar_base);
2623c44d515SNishanth Menon err_cb:
26396ca848eSSricharan R 	kfree(cb);
26499e37d0eSSricharan R 
26599e37d0eSSricharan R 	cb = NULL;
266edb442deSNishanth Menon 	return ret;
26796ca848eSSricharan R }
26896ca848eSSricharan R 
26996ca848eSSricharan R static const struct of_device_id crossbar_match[] __initconst = {
27096ca848eSSricharan R 	{ .compatible = "ti,irq-crossbar" },
27196ca848eSSricharan R 	{}
27296ca848eSSricharan R };
27396ca848eSSricharan R 
27496ca848eSSricharan R int __init irqcrossbar_init(void)
27596ca848eSSricharan R {
27696ca848eSSricharan R 	struct device_node *np;
27796ca848eSSricharan R 	np = of_find_matching_node(NULL, crossbar_match);
27896ca848eSSricharan R 	if (!np)
27996ca848eSSricharan R 		return -ENODEV;
28096ca848eSSricharan R 
28196ca848eSSricharan R 	crossbar_of_init(np);
28296ca848eSSricharan R 	return 0;
28396ca848eSSricharan R }
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