196ca848eSSricharan R /* 296ca848eSSricharan R * drivers/irqchip/irq-crossbar.c 396ca848eSSricharan R * 496ca848eSSricharan R * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com 596ca848eSSricharan R * Author: Sricharan R <r.sricharan@ti.com> 696ca848eSSricharan R * 796ca848eSSricharan R * This program is free software; you can redistribute it and/or modify 896ca848eSSricharan R * it under the terms of the GNU General Public License version 2 as 996ca848eSSricharan R * published by the Free Software Foundation. 1096ca848eSSricharan R * 1196ca848eSSricharan R */ 1296ca848eSSricharan R #include <linux/err.h> 1396ca848eSSricharan R #include <linux/io.h> 1496ca848eSSricharan R #include <linux/of_address.h> 1596ca848eSSricharan R #include <linux/of_irq.h> 1696ca848eSSricharan R #include <linux/slab.h> 1796ca848eSSricharan R #include <linux/irqchip/arm-gic.h> 184dbf45e3SNishanth Menon #include <linux/irqchip/irq-crossbar.h> 1996ca848eSSricharan R 2096ca848eSSricharan R #define IRQ_FREE -1 211d50d2ceSNishanth Menon #define IRQ_RESERVED -2 2264e0f8baSNishanth Menon #define IRQ_SKIP -3 2396ca848eSSricharan R #define GIC_IRQ_START 32 2496ca848eSSricharan R 25e30ef8abSNishanth Menon /** 26e30ef8abSNishanth Menon * struct crossbar_device - crossbar device description 2796ca848eSSricharan R * @int_max: maximum number of supported interrupts 28a35057d1SNishanth Menon * @safe_map: safe default value to initialize the crossbar 292f7d2fb7SNishanth Menon * @max_crossbar_sources: Maximum number of crossbar sources 3096ca848eSSricharan R * @irq_map: array of interrupts to crossbar number mapping 3196ca848eSSricharan R * @crossbar_base: crossbar base address 3296ca848eSSricharan R * @register_offsets: offsets for each irq number 33e30ef8abSNishanth Menon * @write: register write function pointer 3496ca848eSSricharan R */ 3596ca848eSSricharan R struct crossbar_device { 3696ca848eSSricharan R uint int_max; 37a35057d1SNishanth Menon uint safe_map; 382f7d2fb7SNishanth Menon uint max_crossbar_sources; 3996ca848eSSricharan R uint *irq_map; 4096ca848eSSricharan R void __iomem *crossbar_base; 4196ca848eSSricharan R int *register_offsets; 4296ca848eSSricharan R void (*write)(int, int); 4396ca848eSSricharan R }; 4496ca848eSSricharan R 4596ca848eSSricharan R static struct crossbar_device *cb; 4696ca848eSSricharan R 4796ca848eSSricharan R static inline void crossbar_writel(int irq_no, int cb_no) 4896ca848eSSricharan R { 4996ca848eSSricharan R writel(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]); 5096ca848eSSricharan R } 5196ca848eSSricharan R 5296ca848eSSricharan R static inline void crossbar_writew(int irq_no, int cb_no) 5396ca848eSSricharan R { 5496ca848eSSricharan R writew(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]); 5596ca848eSSricharan R } 5696ca848eSSricharan R 5796ca848eSSricharan R static inline void crossbar_writeb(int irq_no, int cb_no) 5896ca848eSSricharan R { 5996ca848eSSricharan R writeb(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]); 6096ca848eSSricharan R } 6196ca848eSSricharan R 626f16fc87SNishanth Menon static inline int get_prev_map_irq(int cb_no) 636f16fc87SNishanth Menon { 646f16fc87SNishanth Menon int i; 656f16fc87SNishanth Menon 66ddee0fb4SNishanth Menon for (i = cb->int_max - 1; i >= 0; i--) 676f16fc87SNishanth Menon if (cb->irq_map[i] == cb_no) 686f16fc87SNishanth Menon return i; 696f16fc87SNishanth Menon 706f16fc87SNishanth Menon return -ENODEV; 716f16fc87SNishanth Menon } 726f16fc87SNishanth Menon 7396ca848eSSricharan R static inline int allocate_free_irq(int cb_no) 7496ca848eSSricharan R { 7596ca848eSSricharan R int i; 7696ca848eSSricharan R 77ddee0fb4SNishanth Menon for (i = cb->int_max - 1; i >= 0; i--) { 7896ca848eSSricharan R if (cb->irq_map[i] == IRQ_FREE) { 7996ca848eSSricharan R cb->irq_map[i] = cb_no; 8096ca848eSSricharan R return i; 8196ca848eSSricharan R } 8296ca848eSSricharan R } 8396ca848eSSricharan R 8496ca848eSSricharan R return -ENODEV; 8596ca848eSSricharan R } 8696ca848eSSricharan R 87*29918b67SNishanth Menon static inline bool needs_crossbar_write(irq_hw_number_t hw) 88*29918b67SNishanth Menon { 89*29918b67SNishanth Menon if (hw > GIC_IRQ_START) 90*29918b67SNishanth Menon return true; 91*29918b67SNishanth Menon 92*29918b67SNishanth Menon return false; 93*29918b67SNishanth Menon } 94*29918b67SNishanth Menon 9596ca848eSSricharan R static int crossbar_domain_map(struct irq_domain *d, unsigned int irq, 9696ca848eSSricharan R irq_hw_number_t hw) 9796ca848eSSricharan R { 98*29918b67SNishanth Menon if (needs_crossbar_write(hw)) 9996ca848eSSricharan R cb->write(hw - GIC_IRQ_START, cb->irq_map[hw - GIC_IRQ_START]); 100*29918b67SNishanth Menon 10196ca848eSSricharan R return 0; 10296ca848eSSricharan R } 10396ca848eSSricharan R 1048b09a45dSSricharan R /** 1058b09a45dSSricharan R * crossbar_domain_unmap - unmap a crossbar<->irq connection 1068b09a45dSSricharan R * @d: domain of irq to unmap 1078b09a45dSSricharan R * @irq: virq number 1088b09a45dSSricharan R * 1098b09a45dSSricharan R * We do not maintain a use count of total number of map/unmap 1108b09a45dSSricharan R * calls for a particular irq to find out if a irq can be really 1118b09a45dSSricharan R * unmapped. This is because unmap is called during irq_dispose_mapping(irq), 1128b09a45dSSricharan R * after which irq is anyways unusable. So an explicit map has to be called 1138b09a45dSSricharan R * after that. 1148b09a45dSSricharan R */ 11596ca848eSSricharan R static void crossbar_domain_unmap(struct irq_domain *d, unsigned int irq) 11696ca848eSSricharan R { 11796ca848eSSricharan R irq_hw_number_t hw = irq_get_irq_data(irq)->hwirq; 11896ca848eSSricharan R 119*29918b67SNishanth Menon if (needs_crossbar_write(hw)) { 12096ca848eSSricharan R cb->irq_map[hw - GIC_IRQ_START] = IRQ_FREE; 121a35057d1SNishanth Menon cb->write(hw - GIC_IRQ_START, cb->safe_map); 122a35057d1SNishanth Menon } 12396ca848eSSricharan R } 12496ca848eSSricharan R 12596ca848eSSricharan R static int crossbar_domain_xlate(struct irq_domain *d, 12696ca848eSSricharan R struct device_node *controller, 12796ca848eSSricharan R const u32 *intspec, unsigned int intsize, 12896ca848eSSricharan R unsigned long *out_hwirq, 12996ca848eSSricharan R unsigned int *out_type) 13096ca848eSSricharan R { 131d4922a95SNishanth Menon int ret; 1322f7d2fb7SNishanth Menon int req_num = intspec[1]; 13396ca848eSSricharan R 1342f7d2fb7SNishanth Menon if (req_num >= cb->max_crossbar_sources) { 1352f7d2fb7SNishanth Menon pr_err("%s: requested crossbar number %d > max %d\n", 1362f7d2fb7SNishanth Menon __func__, req_num, cb->max_crossbar_sources); 1372f7d2fb7SNishanth Menon return -EINVAL; 1382f7d2fb7SNishanth Menon } 1392f7d2fb7SNishanth Menon 1402f7d2fb7SNishanth Menon ret = get_prev_map_irq(req_num); 141d4922a95SNishanth Menon if (ret >= 0) 1426f16fc87SNishanth Menon goto found; 1436f16fc87SNishanth Menon 1442f7d2fb7SNishanth Menon ret = allocate_free_irq(req_num); 14596ca848eSSricharan R 146d4922a95SNishanth Menon if (ret < 0) 14796ca848eSSricharan R return ret; 14896ca848eSSricharan R 1496f16fc87SNishanth Menon found: 15096ca848eSSricharan R *out_hwirq = ret + GIC_IRQ_START; 15196ca848eSSricharan R return 0; 15296ca848eSSricharan R } 15396ca848eSSricharan R 1544dbf45e3SNishanth Menon static const struct irq_domain_ops routable_irq_domain_ops = { 15596ca848eSSricharan R .map = crossbar_domain_map, 15696ca848eSSricharan R .unmap = crossbar_domain_unmap, 15796ca848eSSricharan R .xlate = crossbar_domain_xlate 15896ca848eSSricharan R }; 15996ca848eSSricharan R 16096ca848eSSricharan R static int __init crossbar_of_init(struct device_node *node) 16196ca848eSSricharan R { 162edb442deSNishanth Menon int i, size, max = 0, reserved = 0, entry; 16396ca848eSSricharan R const __be32 *irqsr; 164edb442deSNishanth Menon int ret = -ENOMEM; 16596ca848eSSricharan R 1663894e9e8SDan Carpenter cb = kzalloc(sizeof(*cb), GFP_KERNEL); 16796ca848eSSricharan R 16896ca848eSSricharan R if (!cb) 169edb442deSNishanth Menon return ret; 17096ca848eSSricharan R 17196ca848eSSricharan R cb->crossbar_base = of_iomap(node, 0); 17296ca848eSSricharan R if (!cb->crossbar_base) 1733c44d515SNishanth Menon goto err_cb; 17496ca848eSSricharan R 1752f7d2fb7SNishanth Menon of_property_read_u32(node, "ti,max-crossbar-sources", 1762f7d2fb7SNishanth Menon &cb->max_crossbar_sources); 1772f7d2fb7SNishanth Menon if (!cb->max_crossbar_sources) { 1782f7d2fb7SNishanth Menon pr_err("missing 'ti,max-crossbar-sources' property\n"); 1792f7d2fb7SNishanth Menon ret = -EINVAL; 1802f7d2fb7SNishanth Menon goto err_base; 1812f7d2fb7SNishanth Menon } 1822f7d2fb7SNishanth Menon 18396ca848eSSricharan R of_property_read_u32(node, "ti,max-irqs", &max); 184edb442deSNishanth Menon if (!max) { 185edb442deSNishanth Menon pr_err("missing 'ti,max-irqs' property\n"); 186edb442deSNishanth Menon ret = -EINVAL; 1873c44d515SNishanth Menon goto err_base; 188edb442deSNishanth Menon } 1894dbf45e3SNishanth Menon cb->irq_map = kcalloc(max, sizeof(int), GFP_KERNEL); 19096ca848eSSricharan R if (!cb->irq_map) 1913c44d515SNishanth Menon goto err_base; 19296ca848eSSricharan R 19396ca848eSSricharan R cb->int_max = max; 19496ca848eSSricharan R 19596ca848eSSricharan R for (i = 0; i < max; i++) 19696ca848eSSricharan R cb->irq_map[i] = IRQ_FREE; 19796ca848eSSricharan R 19896ca848eSSricharan R /* Get and mark reserved irqs */ 19996ca848eSSricharan R irqsr = of_get_property(node, "ti,irqs-reserved", &size); 20096ca848eSSricharan R if (irqsr) { 20196ca848eSSricharan R size /= sizeof(__be32); 20296ca848eSSricharan R 20396ca848eSSricharan R for (i = 0; i < size; i++) { 20496ca848eSSricharan R of_property_read_u32_index(node, 20596ca848eSSricharan R "ti,irqs-reserved", 20696ca848eSSricharan R i, &entry); 20796ca848eSSricharan R if (entry > max) { 20896ca848eSSricharan R pr_err("Invalid reserved entry\n"); 209edb442deSNishanth Menon ret = -EINVAL; 2103c44d515SNishanth Menon goto err_irq_map; 21196ca848eSSricharan R } 2121d50d2ceSNishanth Menon cb->irq_map[entry] = IRQ_RESERVED; 21396ca848eSSricharan R } 21496ca848eSSricharan R } 21596ca848eSSricharan R 21664e0f8baSNishanth Menon /* Skip irqs hardwired to bypass the crossbar */ 21764e0f8baSNishanth Menon irqsr = of_get_property(node, "ti,irqs-skip", &size); 21864e0f8baSNishanth Menon if (irqsr) { 21964e0f8baSNishanth Menon size /= sizeof(__be32); 22064e0f8baSNishanth Menon 22164e0f8baSNishanth Menon for (i = 0; i < size; i++) { 22264e0f8baSNishanth Menon of_property_read_u32_index(node, 22364e0f8baSNishanth Menon "ti,irqs-skip", 22464e0f8baSNishanth Menon i, &entry); 22564e0f8baSNishanth Menon if (entry > max) { 22664e0f8baSNishanth Menon pr_err("Invalid skip entry\n"); 22764e0f8baSNishanth Menon ret = -EINVAL; 2283c44d515SNishanth Menon goto err_irq_map; 22964e0f8baSNishanth Menon } 23064e0f8baSNishanth Menon cb->irq_map[entry] = IRQ_SKIP; 23164e0f8baSNishanth Menon } 23264e0f8baSNishanth Menon } 23364e0f8baSNishanth Menon 23464e0f8baSNishanth Menon 2354dbf45e3SNishanth Menon cb->register_offsets = kcalloc(max, sizeof(int), GFP_KERNEL); 23696ca848eSSricharan R if (!cb->register_offsets) 2373c44d515SNishanth Menon goto err_irq_map; 23896ca848eSSricharan R 23996ca848eSSricharan R of_property_read_u32(node, "ti,reg-size", &size); 24096ca848eSSricharan R 24196ca848eSSricharan R switch (size) { 24296ca848eSSricharan R case 1: 24396ca848eSSricharan R cb->write = crossbar_writeb; 24496ca848eSSricharan R break; 24596ca848eSSricharan R case 2: 24696ca848eSSricharan R cb->write = crossbar_writew; 24796ca848eSSricharan R break; 24896ca848eSSricharan R case 4: 24996ca848eSSricharan R cb->write = crossbar_writel; 25096ca848eSSricharan R break; 25196ca848eSSricharan R default: 25296ca848eSSricharan R pr_err("Invalid reg-size property\n"); 253edb442deSNishanth Menon ret = -EINVAL; 2543c44d515SNishanth Menon goto err_reg_offset; 25596ca848eSSricharan R break; 25696ca848eSSricharan R } 25796ca848eSSricharan R 25896ca848eSSricharan R /* 25996ca848eSSricharan R * Register offsets are not linear because of the 26096ca848eSSricharan R * reserved irqs. so find and store the offsets once. 26196ca848eSSricharan R */ 26296ca848eSSricharan R for (i = 0; i < max; i++) { 2631d50d2ceSNishanth Menon if (cb->irq_map[i] == IRQ_RESERVED) 26496ca848eSSricharan R continue; 26596ca848eSSricharan R 26696ca848eSSricharan R cb->register_offsets[i] = reserved; 26796ca848eSSricharan R reserved += size; 26896ca848eSSricharan R } 26996ca848eSSricharan R 270a35057d1SNishanth Menon of_property_read_u32(node, "ti,irqs-safe-map", &cb->safe_map); 271a35057d1SNishanth Menon /* Initialize the crossbar with safe map to start with */ 272a35057d1SNishanth Menon for (i = 0; i < max; i++) { 273a35057d1SNishanth Menon if (cb->irq_map[i] == IRQ_RESERVED || 274a35057d1SNishanth Menon cb->irq_map[i] == IRQ_SKIP) 275a35057d1SNishanth Menon continue; 276a35057d1SNishanth Menon 277a35057d1SNishanth Menon cb->write(i, cb->safe_map); 278a35057d1SNishanth Menon } 279a35057d1SNishanth Menon 28096ca848eSSricharan R register_routable_domain_ops(&routable_irq_domain_ops); 28196ca848eSSricharan R return 0; 28296ca848eSSricharan R 2833c44d515SNishanth Menon err_reg_offset: 28496ca848eSSricharan R kfree(cb->register_offsets); 2853c44d515SNishanth Menon err_irq_map: 28696ca848eSSricharan R kfree(cb->irq_map); 2873c44d515SNishanth Menon err_base: 28896ca848eSSricharan R iounmap(cb->crossbar_base); 2893c44d515SNishanth Menon err_cb: 29096ca848eSSricharan R kfree(cb); 29199e37d0eSSricharan R 29299e37d0eSSricharan R cb = NULL; 293edb442deSNishanth Menon return ret; 29496ca848eSSricharan R } 29596ca848eSSricharan R 29696ca848eSSricharan R static const struct of_device_id crossbar_match[] __initconst = { 29796ca848eSSricharan R { .compatible = "ti,irq-crossbar" }, 29896ca848eSSricharan R {} 29996ca848eSSricharan R }; 30096ca848eSSricharan R 30196ca848eSSricharan R int __init irqcrossbar_init(void) 30296ca848eSSricharan R { 30396ca848eSSricharan R struct device_node *np; 30496ca848eSSricharan R np = of_find_matching_node(NULL, crossbar_match); 30596ca848eSSricharan R if (!np) 30696ca848eSSricharan R return -ENODEV; 30796ca848eSSricharan R 30896ca848eSSricharan R crossbar_of_init(np); 30996ca848eSSricharan R return 0; 31096ca848eSSricharan R } 311