1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015-2016 MediaTek Inc. 4 * Author: Yong Wu <yong.wu@mediatek.com> 5 */ 6 #include <linux/memblock.h> 7 #include <linux/bug.h> 8 #include <linux/clk.h> 9 #include <linux/component.h> 10 #include <linux/device.h> 11 #include <linux/dma-iommu.h> 12 #include <linux/err.h> 13 #include <linux/interrupt.h> 14 #include <linux/io.h> 15 #include <linux/iommu.h> 16 #include <linux/iopoll.h> 17 #include <linux/list.h> 18 #include <linux/of_address.h> 19 #include <linux/of_iommu.h> 20 #include <linux/of_irq.h> 21 #include <linux/of_platform.h> 22 #include <linux/platform_device.h> 23 #include <linux/slab.h> 24 #include <linux/spinlock.h> 25 #include <asm/barrier.h> 26 #include <soc/mediatek/smi.h> 27 28 #include "mtk_iommu.h" 29 30 #define REG_MMU_PT_BASE_ADDR 0x000 31 32 #define REG_MMU_INVALIDATE 0x020 33 #define F_ALL_INVLD 0x2 34 #define F_MMU_INV_RANGE 0x1 35 36 #define REG_MMU_INVLD_START_A 0x024 37 #define REG_MMU_INVLD_END_A 0x028 38 39 #define REG_MMU_INV_SEL 0x038 40 #define F_INVLD_EN0 BIT(0) 41 #define F_INVLD_EN1 BIT(1) 42 43 #define REG_MMU_STANDARD_AXI_MODE 0x048 44 #define REG_MMU_DCM_DIS 0x050 45 46 #define REG_MMU_CTRL_REG 0x110 47 #define F_MMU_PREFETCH_RT_REPLACE_MOD BIT(4) 48 #define F_MMU_TF_PROTECT_SEL_SHIFT(data) \ 49 ((data)->m4u_plat == M4U_MT2712 ? 4 : 5) 50 /* It's named by F_MMU_TF_PROT_SEL in mt2712. */ 51 #define F_MMU_TF_PROTECT_SEL(prot, data) \ 52 (((prot) & 0x3) << F_MMU_TF_PROTECT_SEL_SHIFT(data)) 53 54 #define REG_MMU_IVRP_PADDR 0x114 55 56 #define REG_MMU_VLD_PA_RNG 0x118 57 #define F_MMU_VLD_PA_RNG(EA, SA) (((EA) << 8) | (SA)) 58 59 #define REG_MMU_INT_CONTROL0 0x120 60 #define F_L2_MULIT_HIT_EN BIT(0) 61 #define F_TABLE_WALK_FAULT_INT_EN BIT(1) 62 #define F_PREETCH_FIFO_OVERFLOW_INT_EN BIT(2) 63 #define F_MISS_FIFO_OVERFLOW_INT_EN BIT(3) 64 #define F_PREFETCH_FIFO_ERR_INT_EN BIT(5) 65 #define F_MISS_FIFO_ERR_INT_EN BIT(6) 66 #define F_INT_CLR_BIT BIT(12) 67 68 #define REG_MMU_INT_MAIN_CONTROL 0x124 69 #define F_INT_TRANSLATION_FAULT BIT(0) 70 #define F_INT_MAIN_MULTI_HIT_FAULT BIT(1) 71 #define F_INT_INVALID_PA_FAULT BIT(2) 72 #define F_INT_ENTRY_REPLACEMENT_FAULT BIT(3) 73 #define F_INT_TLB_MISS_FAULT BIT(4) 74 #define F_INT_MISS_TRANSACTION_FIFO_FAULT BIT(5) 75 #define F_INT_PRETETCH_TRANSATION_FIFO_FAULT BIT(6) 76 77 #define REG_MMU_CPE_DONE 0x12C 78 79 #define REG_MMU_FAULT_ST1 0x134 80 81 #define REG_MMU_FAULT_VA 0x13c 82 #define F_MMU_FAULT_VA_WRITE_BIT BIT(1) 83 #define F_MMU_FAULT_VA_LAYER_BIT BIT(0) 84 85 #define REG_MMU_INVLD_PA 0x140 86 #define REG_MMU_INT_ID 0x150 87 #define F_MMU0_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7) 88 #define F_MMU0_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f) 89 90 #define MTK_PROTECT_PA_ALIGN 128 91 92 /* 93 * Get the local arbiter ID and the portid within the larb arbiter 94 * from mtk_m4u_id which is defined by MTK_M4U_ID. 95 */ 96 #define MTK_M4U_TO_LARB(id) (((id) >> 5) & 0xf) 97 #define MTK_M4U_TO_PORT(id) ((id) & 0x1f) 98 99 struct mtk_iommu_domain { 100 spinlock_t pgtlock; /* lock for page table */ 101 102 struct io_pgtable_cfg cfg; 103 struct io_pgtable_ops *iop; 104 105 struct iommu_domain domain; 106 }; 107 108 static const struct iommu_ops mtk_iommu_ops; 109 110 static LIST_HEAD(m4ulist); /* List all the M4U HWs */ 111 112 #define for_each_m4u(data) list_for_each_entry(data, &m4ulist, list) 113 114 /* 115 * There may be 1 or 2 M4U HWs, But we always expect they are in the same domain 116 * for the performance. 117 * 118 * Here always return the mtk_iommu_data of the first probed M4U where the 119 * iommu domain information is recorded. 120 */ 121 static struct mtk_iommu_data *mtk_iommu_get_m4u_data(void) 122 { 123 struct mtk_iommu_data *data; 124 125 for_each_m4u(data) 126 return data; 127 128 return NULL; 129 } 130 131 static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom) 132 { 133 return container_of(dom, struct mtk_iommu_domain, domain); 134 } 135 136 static void mtk_iommu_tlb_flush_all(void *cookie) 137 { 138 struct mtk_iommu_data *data = cookie; 139 140 for_each_m4u(data) { 141 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, 142 data->base + REG_MMU_INV_SEL); 143 writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE); 144 wmb(); /* Make sure the tlb flush all done */ 145 } 146 } 147 148 static void mtk_iommu_tlb_add_flush_nosync(unsigned long iova, size_t size, 149 size_t granule, bool leaf, 150 void *cookie) 151 { 152 struct mtk_iommu_data *data = cookie; 153 154 for_each_m4u(data) { 155 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, 156 data->base + REG_MMU_INV_SEL); 157 158 writel_relaxed(iova, data->base + REG_MMU_INVLD_START_A); 159 writel_relaxed(iova + size - 1, 160 data->base + REG_MMU_INVLD_END_A); 161 writel_relaxed(F_MMU_INV_RANGE, 162 data->base + REG_MMU_INVALIDATE); 163 data->tlb_flush_active = true; 164 } 165 } 166 167 static void mtk_iommu_tlb_sync(void *cookie) 168 { 169 struct mtk_iommu_data *data = cookie; 170 int ret; 171 u32 tmp; 172 173 for_each_m4u(data) { 174 /* Avoid timing out if there's nothing to wait for */ 175 if (!data->tlb_flush_active) 176 return; 177 178 ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE, 179 tmp, tmp != 0, 10, 100000); 180 if (ret) { 181 dev_warn(data->dev, 182 "Partial TLB flush timed out, falling back to full flush\n"); 183 mtk_iommu_tlb_flush_all(cookie); 184 } 185 /* Clear the CPE status */ 186 writel_relaxed(0, data->base + REG_MMU_CPE_DONE); 187 data->tlb_flush_active = false; 188 } 189 } 190 191 static void mtk_iommu_tlb_flush_walk(unsigned long iova, size_t size, 192 size_t granule, void *cookie) 193 { 194 mtk_iommu_tlb_add_flush_nosync(iova, size, granule, false, cookie); 195 mtk_iommu_tlb_sync(cookie); 196 } 197 198 static void mtk_iommu_tlb_flush_leaf(unsigned long iova, size_t size, 199 size_t granule, void *cookie) 200 { 201 mtk_iommu_tlb_add_flush_nosync(iova, size, granule, true, cookie); 202 mtk_iommu_tlb_sync(cookie); 203 } 204 205 static void mtk_iommu_tlb_flush_page_nosync(unsigned long iova, size_t granule, 206 void *cookie) 207 { 208 mtk_iommu_tlb_add_flush_nosync(iova, granule, granule, true, cookie); 209 } 210 211 static const struct iommu_flush_ops mtk_iommu_flush_ops = { 212 .tlb_flush_all = mtk_iommu_tlb_flush_all, 213 .tlb_flush_walk = mtk_iommu_tlb_flush_walk, 214 .tlb_flush_leaf = mtk_iommu_tlb_flush_leaf, 215 .tlb_add_page = mtk_iommu_tlb_flush_page_nosync, 216 .tlb_sync = mtk_iommu_tlb_sync, 217 }; 218 219 static irqreturn_t mtk_iommu_isr(int irq, void *dev_id) 220 { 221 struct mtk_iommu_data *data = dev_id; 222 struct mtk_iommu_domain *dom = data->m4u_dom; 223 u32 int_state, regval, fault_iova, fault_pa; 224 unsigned int fault_larb, fault_port; 225 bool layer, write; 226 227 /* Read error info from registers */ 228 int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST1); 229 fault_iova = readl_relaxed(data->base + REG_MMU_FAULT_VA); 230 layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT; 231 write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT; 232 fault_pa = readl_relaxed(data->base + REG_MMU_INVLD_PA); 233 regval = readl_relaxed(data->base + REG_MMU_INT_ID); 234 fault_larb = F_MMU0_INT_ID_LARB_ID(regval); 235 fault_port = F_MMU0_INT_ID_PORT_ID(regval); 236 237 if (report_iommu_fault(&dom->domain, data->dev, fault_iova, 238 write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) { 239 dev_err_ratelimited( 240 data->dev, 241 "fault type=0x%x iova=0x%x pa=0x%x larb=%d port=%d layer=%d %s\n", 242 int_state, fault_iova, fault_pa, fault_larb, fault_port, 243 layer, write ? "write" : "read"); 244 } 245 246 /* Interrupt clear */ 247 regval = readl_relaxed(data->base + REG_MMU_INT_CONTROL0); 248 regval |= F_INT_CLR_BIT; 249 writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0); 250 251 mtk_iommu_tlb_flush_all(data); 252 253 return IRQ_HANDLED; 254 } 255 256 static void mtk_iommu_config(struct mtk_iommu_data *data, 257 struct device *dev, bool enable) 258 { 259 struct mtk_smi_larb_iommu *larb_mmu; 260 unsigned int larbid, portid; 261 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 262 int i; 263 264 for (i = 0; i < fwspec->num_ids; ++i) { 265 larbid = MTK_M4U_TO_LARB(fwspec->ids[i]); 266 portid = MTK_M4U_TO_PORT(fwspec->ids[i]); 267 larb_mmu = &data->smi_imu.larb_imu[larbid]; 268 269 dev_dbg(dev, "%s iommu port: %d\n", 270 enable ? "enable" : "disable", portid); 271 272 if (enable) 273 larb_mmu->mmu |= MTK_SMI_MMU_EN(portid); 274 else 275 larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid); 276 } 277 } 278 279 static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom) 280 { 281 struct mtk_iommu_data *data = mtk_iommu_get_m4u_data(); 282 283 spin_lock_init(&dom->pgtlock); 284 285 dom->cfg = (struct io_pgtable_cfg) { 286 .quirks = IO_PGTABLE_QUIRK_ARM_NS | 287 IO_PGTABLE_QUIRK_NO_PERMS | 288 IO_PGTABLE_QUIRK_TLBI_ON_MAP, 289 .pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap, 290 .ias = 32, 291 .oas = 32, 292 .tlb = &mtk_iommu_flush_ops, 293 .iommu_dev = data->dev, 294 }; 295 296 if (data->enable_4GB) 297 dom->cfg.quirks |= IO_PGTABLE_QUIRK_ARM_MTK_4GB; 298 299 dom->iop = alloc_io_pgtable_ops(ARM_V7S, &dom->cfg, data); 300 if (!dom->iop) { 301 dev_err(data->dev, "Failed to alloc io pgtable\n"); 302 return -EINVAL; 303 } 304 305 /* Update our support page sizes bitmap */ 306 dom->domain.pgsize_bitmap = dom->cfg.pgsize_bitmap; 307 return 0; 308 } 309 310 static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type) 311 { 312 struct mtk_iommu_domain *dom; 313 314 if (type != IOMMU_DOMAIN_DMA) 315 return NULL; 316 317 dom = kzalloc(sizeof(*dom), GFP_KERNEL); 318 if (!dom) 319 return NULL; 320 321 if (iommu_get_dma_cookie(&dom->domain)) 322 goto free_dom; 323 324 if (mtk_iommu_domain_finalise(dom)) 325 goto put_dma_cookie; 326 327 dom->domain.geometry.aperture_start = 0; 328 dom->domain.geometry.aperture_end = DMA_BIT_MASK(32); 329 dom->domain.geometry.force_aperture = true; 330 331 return &dom->domain; 332 333 put_dma_cookie: 334 iommu_put_dma_cookie(&dom->domain); 335 free_dom: 336 kfree(dom); 337 return NULL; 338 } 339 340 static void mtk_iommu_domain_free(struct iommu_domain *domain) 341 { 342 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 343 344 free_io_pgtable_ops(dom->iop); 345 iommu_put_dma_cookie(domain); 346 kfree(to_mtk_domain(domain)); 347 } 348 349 static int mtk_iommu_attach_device(struct iommu_domain *domain, 350 struct device *dev) 351 { 352 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 353 struct mtk_iommu_data *data = dev_iommu_fwspec_get(dev)->iommu_priv; 354 355 if (!data) 356 return -ENODEV; 357 358 /* Update the pgtable base address register of the M4U HW */ 359 if (!data->m4u_dom) { 360 data->m4u_dom = dom; 361 writel(dom->cfg.arm_v7s_cfg.ttbr[0], 362 data->base + REG_MMU_PT_BASE_ADDR); 363 } 364 365 mtk_iommu_config(data, dev, true); 366 return 0; 367 } 368 369 static void mtk_iommu_detach_device(struct iommu_domain *domain, 370 struct device *dev) 371 { 372 struct mtk_iommu_data *data = dev_iommu_fwspec_get(dev)->iommu_priv; 373 374 if (!data) 375 return; 376 377 mtk_iommu_config(data, dev, false); 378 } 379 380 static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova, 381 phys_addr_t paddr, size_t size, int prot) 382 { 383 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 384 unsigned long flags; 385 int ret; 386 387 spin_lock_irqsave(&dom->pgtlock, flags); 388 ret = dom->iop->map(dom->iop, iova, paddr & DMA_BIT_MASK(32), 389 size, prot); 390 spin_unlock_irqrestore(&dom->pgtlock, flags); 391 392 return ret; 393 } 394 395 static size_t mtk_iommu_unmap(struct iommu_domain *domain, 396 unsigned long iova, size_t size, 397 struct iommu_iotlb_gather *gather) 398 { 399 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 400 unsigned long flags; 401 size_t unmapsz; 402 403 spin_lock_irqsave(&dom->pgtlock, flags); 404 unmapsz = dom->iop->unmap(dom->iop, iova, size); 405 spin_unlock_irqrestore(&dom->pgtlock, flags); 406 407 return unmapsz; 408 } 409 410 static void mtk_iommu_flush_iotlb_all(struct iommu_domain *domain) 411 { 412 mtk_iommu_tlb_sync(mtk_iommu_get_m4u_data()); 413 } 414 415 static void mtk_iommu_iotlb_sync(struct iommu_domain *domain, 416 struct iommu_iotlb_gather *gather) 417 { 418 mtk_iommu_tlb_sync(mtk_iommu_get_m4u_data()); 419 } 420 421 static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain, 422 dma_addr_t iova) 423 { 424 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 425 struct mtk_iommu_data *data = mtk_iommu_get_m4u_data(); 426 unsigned long flags; 427 phys_addr_t pa; 428 429 spin_lock_irqsave(&dom->pgtlock, flags); 430 pa = dom->iop->iova_to_phys(dom->iop, iova); 431 spin_unlock_irqrestore(&dom->pgtlock, flags); 432 433 if (data->enable_4GB) 434 pa |= BIT_ULL(32); 435 436 return pa; 437 } 438 439 static int mtk_iommu_add_device(struct device *dev) 440 { 441 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 442 struct mtk_iommu_data *data; 443 struct iommu_group *group; 444 445 if (!fwspec || fwspec->ops != &mtk_iommu_ops) 446 return -ENODEV; /* Not a iommu client device */ 447 448 data = fwspec->iommu_priv; 449 iommu_device_link(&data->iommu, dev); 450 451 group = iommu_group_get_for_dev(dev); 452 if (IS_ERR(group)) 453 return PTR_ERR(group); 454 455 iommu_group_put(group); 456 return 0; 457 } 458 459 static void mtk_iommu_remove_device(struct device *dev) 460 { 461 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 462 struct mtk_iommu_data *data; 463 464 if (!fwspec || fwspec->ops != &mtk_iommu_ops) 465 return; 466 467 data = fwspec->iommu_priv; 468 iommu_device_unlink(&data->iommu, dev); 469 470 iommu_group_remove_device(dev); 471 iommu_fwspec_free(dev); 472 } 473 474 static struct iommu_group *mtk_iommu_device_group(struct device *dev) 475 { 476 struct mtk_iommu_data *data = mtk_iommu_get_m4u_data(); 477 478 if (!data) 479 return ERR_PTR(-ENODEV); 480 481 /* All the client devices are in the same m4u iommu-group */ 482 if (!data->m4u_group) { 483 data->m4u_group = iommu_group_alloc(); 484 if (IS_ERR(data->m4u_group)) 485 dev_err(dev, "Failed to allocate M4U IOMMU group\n"); 486 } else { 487 iommu_group_ref_get(data->m4u_group); 488 } 489 return data->m4u_group; 490 } 491 492 static int mtk_iommu_of_xlate(struct device *dev, struct of_phandle_args *args) 493 { 494 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 495 struct platform_device *m4updev; 496 497 if (args->args_count != 1) { 498 dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n", 499 args->args_count); 500 return -EINVAL; 501 } 502 503 if (!fwspec->iommu_priv) { 504 /* Get the m4u device */ 505 m4updev = of_find_device_by_node(args->np); 506 if (WARN_ON(!m4updev)) 507 return -EINVAL; 508 509 fwspec->iommu_priv = platform_get_drvdata(m4updev); 510 } 511 512 return iommu_fwspec_add_ids(dev, args->args, 1); 513 } 514 515 static const struct iommu_ops mtk_iommu_ops = { 516 .domain_alloc = mtk_iommu_domain_alloc, 517 .domain_free = mtk_iommu_domain_free, 518 .attach_dev = mtk_iommu_attach_device, 519 .detach_dev = mtk_iommu_detach_device, 520 .map = mtk_iommu_map, 521 .unmap = mtk_iommu_unmap, 522 .flush_iotlb_all = mtk_iommu_flush_iotlb_all, 523 .iotlb_sync = mtk_iommu_iotlb_sync, 524 .iova_to_phys = mtk_iommu_iova_to_phys, 525 .add_device = mtk_iommu_add_device, 526 .remove_device = mtk_iommu_remove_device, 527 .device_group = mtk_iommu_device_group, 528 .of_xlate = mtk_iommu_of_xlate, 529 .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M, 530 }; 531 532 static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) 533 { 534 u32 regval; 535 int ret; 536 537 ret = clk_prepare_enable(data->bclk); 538 if (ret) { 539 dev_err(data->dev, "Failed to enable iommu bclk(%d)\n", ret); 540 return ret; 541 } 542 543 regval = F_MMU_TF_PROTECT_SEL(2, data); 544 if (data->m4u_plat == M4U_MT8173) 545 regval |= F_MMU_PREFETCH_RT_REPLACE_MOD; 546 writel_relaxed(regval, data->base + REG_MMU_CTRL_REG); 547 548 regval = F_L2_MULIT_HIT_EN | 549 F_TABLE_WALK_FAULT_INT_EN | 550 F_PREETCH_FIFO_OVERFLOW_INT_EN | 551 F_MISS_FIFO_OVERFLOW_INT_EN | 552 F_PREFETCH_FIFO_ERR_INT_EN | 553 F_MISS_FIFO_ERR_INT_EN; 554 writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0); 555 556 regval = F_INT_TRANSLATION_FAULT | 557 F_INT_MAIN_MULTI_HIT_FAULT | 558 F_INT_INVALID_PA_FAULT | 559 F_INT_ENTRY_REPLACEMENT_FAULT | 560 F_INT_TLB_MISS_FAULT | 561 F_INT_MISS_TRANSACTION_FIFO_FAULT | 562 F_INT_PRETETCH_TRANSATION_FIFO_FAULT; 563 writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL); 564 565 if (data->m4u_plat == M4U_MT8173) 566 regval = (data->protect_base >> 1) | (data->enable_4GB << 31); 567 else 568 regval = lower_32_bits(data->protect_base) | 569 upper_32_bits(data->protect_base); 570 writel_relaxed(regval, data->base + REG_MMU_IVRP_PADDR); 571 572 if (data->enable_4GB && data->m4u_plat != M4U_MT8173) { 573 /* 574 * If 4GB mode is enabled, the validate PA range is from 575 * 0x1_0000_0000 to 0x1_ffff_ffff. here record bit[32:30]. 576 */ 577 regval = F_MMU_VLD_PA_RNG(7, 4); 578 writel_relaxed(regval, data->base + REG_MMU_VLD_PA_RNG); 579 } 580 writel_relaxed(0, data->base + REG_MMU_DCM_DIS); 581 582 /* It's MISC control register whose default value is ok except mt8173.*/ 583 if (data->m4u_plat == M4U_MT8173) 584 writel_relaxed(0, data->base + REG_MMU_STANDARD_AXI_MODE); 585 586 if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0, 587 dev_name(data->dev), (void *)data)) { 588 writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR); 589 clk_disable_unprepare(data->bclk); 590 dev_err(data->dev, "Failed @ IRQ-%d Request\n", data->irq); 591 return -ENODEV; 592 } 593 594 return 0; 595 } 596 597 static const struct component_master_ops mtk_iommu_com_ops = { 598 .bind = mtk_iommu_bind, 599 .unbind = mtk_iommu_unbind, 600 }; 601 602 static int mtk_iommu_probe(struct platform_device *pdev) 603 { 604 struct mtk_iommu_data *data; 605 struct device *dev = &pdev->dev; 606 struct resource *res; 607 resource_size_t ioaddr; 608 struct component_match *match = NULL; 609 void *protect; 610 int i, larb_nr, ret; 611 612 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 613 if (!data) 614 return -ENOMEM; 615 data->dev = dev; 616 data->m4u_plat = (enum mtk_iommu_plat)of_device_get_match_data(dev); 617 618 /* Protect memory. HW will access here while translation fault.*/ 619 protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2, GFP_KERNEL); 620 if (!protect) 621 return -ENOMEM; 622 data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN); 623 624 /* Whether the current dram is over 4GB */ 625 data->enable_4GB = !!(max_pfn > (BIT_ULL(32) >> PAGE_SHIFT)); 626 627 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 628 data->base = devm_ioremap_resource(dev, res); 629 if (IS_ERR(data->base)) 630 return PTR_ERR(data->base); 631 ioaddr = res->start; 632 633 data->irq = platform_get_irq(pdev, 0); 634 if (data->irq < 0) 635 return data->irq; 636 637 data->bclk = devm_clk_get(dev, "bclk"); 638 if (IS_ERR(data->bclk)) 639 return PTR_ERR(data->bclk); 640 641 larb_nr = of_count_phandle_with_args(dev->of_node, 642 "mediatek,larbs", NULL); 643 if (larb_nr < 0) 644 return larb_nr; 645 data->smi_imu.larb_nr = larb_nr; 646 647 for (i = 0; i < larb_nr; i++) { 648 struct device_node *larbnode; 649 struct platform_device *plarbdev; 650 u32 id; 651 652 larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i); 653 if (!larbnode) 654 return -EINVAL; 655 656 if (!of_device_is_available(larbnode)) { 657 of_node_put(larbnode); 658 continue; 659 } 660 661 ret = of_property_read_u32(larbnode, "mediatek,larb-id", &id); 662 if (ret)/* The id is consecutive if there is no this property */ 663 id = i; 664 665 plarbdev = of_find_device_by_node(larbnode); 666 if (!plarbdev) { 667 of_node_put(larbnode); 668 return -EPROBE_DEFER; 669 } 670 data->smi_imu.larb_imu[id].dev = &plarbdev->dev; 671 672 component_match_add_release(dev, &match, release_of, 673 compare_of, larbnode); 674 } 675 676 platform_set_drvdata(pdev, data); 677 678 ret = mtk_iommu_hw_init(data); 679 if (ret) 680 return ret; 681 682 ret = iommu_device_sysfs_add(&data->iommu, dev, NULL, 683 "mtk-iommu.%pa", &ioaddr); 684 if (ret) 685 return ret; 686 687 iommu_device_set_ops(&data->iommu, &mtk_iommu_ops); 688 iommu_device_set_fwnode(&data->iommu, &pdev->dev.of_node->fwnode); 689 690 ret = iommu_device_register(&data->iommu); 691 if (ret) 692 return ret; 693 694 list_add_tail(&data->list, &m4ulist); 695 696 if (!iommu_present(&platform_bus_type)) 697 bus_set_iommu(&platform_bus_type, &mtk_iommu_ops); 698 699 return component_master_add_with_match(dev, &mtk_iommu_com_ops, match); 700 } 701 702 static int mtk_iommu_remove(struct platform_device *pdev) 703 { 704 struct mtk_iommu_data *data = platform_get_drvdata(pdev); 705 706 iommu_device_sysfs_remove(&data->iommu); 707 iommu_device_unregister(&data->iommu); 708 709 if (iommu_present(&platform_bus_type)) 710 bus_set_iommu(&platform_bus_type, NULL); 711 712 clk_disable_unprepare(data->bclk); 713 devm_free_irq(&pdev->dev, data->irq, data); 714 component_master_del(&pdev->dev, &mtk_iommu_com_ops); 715 return 0; 716 } 717 718 static int __maybe_unused mtk_iommu_suspend(struct device *dev) 719 { 720 struct mtk_iommu_data *data = dev_get_drvdata(dev); 721 struct mtk_iommu_suspend_reg *reg = &data->reg; 722 void __iomem *base = data->base; 723 724 reg->standard_axi_mode = readl_relaxed(base + 725 REG_MMU_STANDARD_AXI_MODE); 726 reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS); 727 reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG); 728 reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL0); 729 reg->int_main_control = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL); 730 reg->ivrp_paddr = readl_relaxed(base + REG_MMU_IVRP_PADDR); 731 clk_disable_unprepare(data->bclk); 732 return 0; 733 } 734 735 static int __maybe_unused mtk_iommu_resume(struct device *dev) 736 { 737 struct mtk_iommu_data *data = dev_get_drvdata(dev); 738 struct mtk_iommu_suspend_reg *reg = &data->reg; 739 void __iomem *base = data->base; 740 int ret; 741 742 ret = clk_prepare_enable(data->bclk); 743 if (ret) { 744 dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret); 745 return ret; 746 } 747 writel_relaxed(reg->standard_axi_mode, 748 base + REG_MMU_STANDARD_AXI_MODE); 749 writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS); 750 writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG); 751 writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL0); 752 writel_relaxed(reg->int_main_control, base + REG_MMU_INT_MAIN_CONTROL); 753 writel_relaxed(reg->ivrp_paddr, base + REG_MMU_IVRP_PADDR); 754 if (data->m4u_dom) 755 writel(data->m4u_dom->cfg.arm_v7s_cfg.ttbr[0], 756 base + REG_MMU_PT_BASE_ADDR); 757 return 0; 758 } 759 760 static const struct dev_pm_ops mtk_iommu_pm_ops = { 761 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_iommu_suspend, mtk_iommu_resume) 762 }; 763 764 static const struct of_device_id mtk_iommu_of_ids[] = { 765 { .compatible = "mediatek,mt2712-m4u", .data = (void *)M4U_MT2712}, 766 { .compatible = "mediatek,mt8173-m4u", .data = (void *)M4U_MT8173}, 767 {} 768 }; 769 770 static struct platform_driver mtk_iommu_driver = { 771 .probe = mtk_iommu_probe, 772 .remove = mtk_iommu_remove, 773 .driver = { 774 .name = "mtk-iommu", 775 .of_match_table = of_match_ptr(mtk_iommu_of_ids), 776 .pm = &mtk_iommu_pm_ops, 777 } 778 }; 779 780 static int __init mtk_iommu_init(void) 781 { 782 int ret; 783 784 ret = platform_driver_register(&mtk_iommu_driver); 785 if (ret != 0) 786 pr_err("Failed to register MTK IOMMU driver\n"); 787 788 return ret; 789 } 790 791 subsys_initcall(mtk_iommu_init) 792