1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015-2016 MediaTek Inc. 4 * Author: Yong Wu <yong.wu@mediatek.com> 5 */ 6 #include <linux/memblock.h> 7 #include <linux/bug.h> 8 #include <linux/clk.h> 9 #include <linux/component.h> 10 #include <linux/device.h> 11 #include <linux/dma-iommu.h> 12 #include <linux/err.h> 13 #include <linux/interrupt.h> 14 #include <linux/io.h> 15 #include <linux/iommu.h> 16 #include <linux/iopoll.h> 17 #include <linux/list.h> 18 #include <linux/of_address.h> 19 #include <linux/of_iommu.h> 20 #include <linux/of_irq.h> 21 #include <linux/of_platform.h> 22 #include <linux/platform_device.h> 23 #include <linux/slab.h> 24 #include <linux/spinlock.h> 25 #include <asm/barrier.h> 26 #include <soc/mediatek/smi.h> 27 28 #include "mtk_iommu.h" 29 30 #define REG_MMU_PT_BASE_ADDR 0x000 31 32 #define REG_MMU_INVALIDATE 0x020 33 #define F_ALL_INVLD 0x2 34 #define F_MMU_INV_RANGE 0x1 35 36 #define REG_MMU_INVLD_START_A 0x024 37 #define REG_MMU_INVLD_END_A 0x028 38 39 #define REG_MMU_INV_SEL 0x038 40 #define F_INVLD_EN0 BIT(0) 41 #define F_INVLD_EN1 BIT(1) 42 43 #define REG_MMU_STANDARD_AXI_MODE 0x048 44 #define REG_MMU_DCM_DIS 0x050 45 46 #define REG_MMU_CTRL_REG 0x110 47 #define F_MMU_PREFETCH_RT_REPLACE_MOD BIT(4) 48 #define F_MMU_TF_PROTECT_SEL_SHIFT(data) \ 49 ((data)->m4u_plat == M4U_MT2712 ? 4 : 5) 50 /* It's named by F_MMU_TF_PROT_SEL in mt2712. */ 51 #define F_MMU_TF_PROTECT_SEL(prot, data) \ 52 (((prot) & 0x3) << F_MMU_TF_PROTECT_SEL_SHIFT(data)) 53 54 #define REG_MMU_IVRP_PADDR 0x114 55 56 #define REG_MMU_VLD_PA_RNG 0x118 57 #define F_MMU_VLD_PA_RNG(EA, SA) (((EA) << 8) | (SA)) 58 59 #define REG_MMU_INT_CONTROL0 0x120 60 #define F_L2_MULIT_HIT_EN BIT(0) 61 #define F_TABLE_WALK_FAULT_INT_EN BIT(1) 62 #define F_PREETCH_FIFO_OVERFLOW_INT_EN BIT(2) 63 #define F_MISS_FIFO_OVERFLOW_INT_EN BIT(3) 64 #define F_PREFETCH_FIFO_ERR_INT_EN BIT(5) 65 #define F_MISS_FIFO_ERR_INT_EN BIT(6) 66 #define F_INT_CLR_BIT BIT(12) 67 68 #define REG_MMU_INT_MAIN_CONTROL 0x124 69 #define F_INT_TRANSLATION_FAULT BIT(0) 70 #define F_INT_MAIN_MULTI_HIT_FAULT BIT(1) 71 #define F_INT_INVALID_PA_FAULT BIT(2) 72 #define F_INT_ENTRY_REPLACEMENT_FAULT BIT(3) 73 #define F_INT_TLB_MISS_FAULT BIT(4) 74 #define F_INT_MISS_TRANSACTION_FIFO_FAULT BIT(5) 75 #define F_INT_PRETETCH_TRANSATION_FIFO_FAULT BIT(6) 76 77 #define REG_MMU_CPE_DONE 0x12C 78 79 #define REG_MMU_FAULT_ST1 0x134 80 81 #define REG_MMU_FAULT_VA 0x13c 82 #define F_MMU_FAULT_VA_WRITE_BIT BIT(1) 83 #define F_MMU_FAULT_VA_LAYER_BIT BIT(0) 84 85 #define REG_MMU_INVLD_PA 0x140 86 #define REG_MMU_INT_ID 0x150 87 #define F_MMU0_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7) 88 #define F_MMU0_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f) 89 90 #define MTK_PROTECT_PA_ALIGN 128 91 92 /* 93 * Get the local arbiter ID and the portid within the larb arbiter 94 * from mtk_m4u_id which is defined by MTK_M4U_ID. 95 */ 96 #define MTK_M4U_TO_LARB(id) (((id) >> 5) & 0xf) 97 #define MTK_M4U_TO_PORT(id) ((id) & 0x1f) 98 99 struct mtk_iommu_domain { 100 spinlock_t pgtlock; /* lock for page table */ 101 102 struct io_pgtable_cfg cfg; 103 struct io_pgtable_ops *iop; 104 105 struct iommu_domain domain; 106 }; 107 108 static const struct iommu_ops mtk_iommu_ops; 109 110 static LIST_HEAD(m4ulist); /* List all the M4U HWs */ 111 112 #define for_each_m4u(data) list_for_each_entry(data, &m4ulist, list) 113 114 /* 115 * There may be 1 or 2 M4U HWs, But we always expect they are in the same domain 116 * for the performance. 117 * 118 * Here always return the mtk_iommu_data of the first probed M4U where the 119 * iommu domain information is recorded. 120 */ 121 static struct mtk_iommu_data *mtk_iommu_get_m4u_data(void) 122 { 123 struct mtk_iommu_data *data; 124 125 for_each_m4u(data) 126 return data; 127 128 return NULL; 129 } 130 131 static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom) 132 { 133 return container_of(dom, struct mtk_iommu_domain, domain); 134 } 135 136 static void mtk_iommu_tlb_flush_all(void *cookie) 137 { 138 struct mtk_iommu_data *data = cookie; 139 140 for_each_m4u(data) { 141 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, 142 data->base + REG_MMU_INV_SEL); 143 writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE); 144 wmb(); /* Make sure the tlb flush all done */ 145 } 146 } 147 148 static void mtk_iommu_tlb_add_flush_nosync(unsigned long iova, size_t size, 149 size_t granule, bool leaf, 150 void *cookie) 151 { 152 struct mtk_iommu_data *data = cookie; 153 154 for_each_m4u(data) { 155 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, 156 data->base + REG_MMU_INV_SEL); 157 158 writel_relaxed(iova, data->base + REG_MMU_INVLD_START_A); 159 writel_relaxed(iova + size - 1, 160 data->base + REG_MMU_INVLD_END_A); 161 writel_relaxed(F_MMU_INV_RANGE, 162 data->base + REG_MMU_INVALIDATE); 163 data->tlb_flush_active = true; 164 } 165 } 166 167 static void mtk_iommu_tlb_sync(void *cookie) 168 { 169 struct mtk_iommu_data *data = cookie; 170 int ret; 171 u32 tmp; 172 173 for_each_m4u(data) { 174 /* Avoid timing out if there's nothing to wait for */ 175 if (!data->tlb_flush_active) 176 return; 177 178 ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE, 179 tmp, tmp != 0, 10, 100000); 180 if (ret) { 181 dev_warn(data->dev, 182 "Partial TLB flush timed out, falling back to full flush\n"); 183 mtk_iommu_tlb_flush_all(cookie); 184 } 185 /* Clear the CPE status */ 186 writel_relaxed(0, data->base + REG_MMU_CPE_DONE); 187 data->tlb_flush_active = false; 188 } 189 } 190 191 static void mtk_iommu_tlb_flush_walk(unsigned long iova, size_t size, 192 size_t granule, void *cookie) 193 { 194 mtk_iommu_tlb_add_flush_nosync(iova, size, granule, false, cookie); 195 mtk_iommu_tlb_sync(cookie); 196 } 197 198 static void mtk_iommu_tlb_flush_leaf(unsigned long iova, size_t size, 199 size_t granule, void *cookie) 200 { 201 mtk_iommu_tlb_add_flush_nosync(iova, size, granule, true, cookie); 202 mtk_iommu_tlb_sync(cookie); 203 } 204 205 static const struct iommu_flush_ops mtk_iommu_flush_ops = { 206 .tlb_flush_all = mtk_iommu_tlb_flush_all, 207 .tlb_flush_walk = mtk_iommu_tlb_flush_walk, 208 .tlb_flush_leaf = mtk_iommu_tlb_flush_leaf, 209 .tlb_add_flush = mtk_iommu_tlb_add_flush_nosync, 210 .tlb_sync = mtk_iommu_tlb_sync, 211 }; 212 213 static irqreturn_t mtk_iommu_isr(int irq, void *dev_id) 214 { 215 struct mtk_iommu_data *data = dev_id; 216 struct mtk_iommu_domain *dom = data->m4u_dom; 217 u32 int_state, regval, fault_iova, fault_pa; 218 unsigned int fault_larb, fault_port; 219 bool layer, write; 220 221 /* Read error info from registers */ 222 int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST1); 223 fault_iova = readl_relaxed(data->base + REG_MMU_FAULT_VA); 224 layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT; 225 write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT; 226 fault_pa = readl_relaxed(data->base + REG_MMU_INVLD_PA); 227 regval = readl_relaxed(data->base + REG_MMU_INT_ID); 228 fault_larb = F_MMU0_INT_ID_LARB_ID(regval); 229 fault_port = F_MMU0_INT_ID_PORT_ID(regval); 230 231 if (report_iommu_fault(&dom->domain, data->dev, fault_iova, 232 write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) { 233 dev_err_ratelimited( 234 data->dev, 235 "fault type=0x%x iova=0x%x pa=0x%x larb=%d port=%d layer=%d %s\n", 236 int_state, fault_iova, fault_pa, fault_larb, fault_port, 237 layer, write ? "write" : "read"); 238 } 239 240 /* Interrupt clear */ 241 regval = readl_relaxed(data->base + REG_MMU_INT_CONTROL0); 242 regval |= F_INT_CLR_BIT; 243 writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0); 244 245 mtk_iommu_tlb_flush_all(data); 246 247 return IRQ_HANDLED; 248 } 249 250 static void mtk_iommu_config(struct mtk_iommu_data *data, 251 struct device *dev, bool enable) 252 { 253 struct mtk_smi_larb_iommu *larb_mmu; 254 unsigned int larbid, portid; 255 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 256 int i; 257 258 for (i = 0; i < fwspec->num_ids; ++i) { 259 larbid = MTK_M4U_TO_LARB(fwspec->ids[i]); 260 portid = MTK_M4U_TO_PORT(fwspec->ids[i]); 261 larb_mmu = &data->smi_imu.larb_imu[larbid]; 262 263 dev_dbg(dev, "%s iommu port: %d\n", 264 enable ? "enable" : "disable", portid); 265 266 if (enable) 267 larb_mmu->mmu |= MTK_SMI_MMU_EN(portid); 268 else 269 larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid); 270 } 271 } 272 273 static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom) 274 { 275 struct mtk_iommu_data *data = mtk_iommu_get_m4u_data(); 276 277 spin_lock_init(&dom->pgtlock); 278 279 dom->cfg = (struct io_pgtable_cfg) { 280 .quirks = IO_PGTABLE_QUIRK_ARM_NS | 281 IO_PGTABLE_QUIRK_NO_PERMS | 282 IO_PGTABLE_QUIRK_TLBI_ON_MAP, 283 .pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap, 284 .ias = 32, 285 .oas = 32, 286 .tlb = &mtk_iommu_flush_ops, 287 .iommu_dev = data->dev, 288 }; 289 290 if (data->enable_4GB) 291 dom->cfg.quirks |= IO_PGTABLE_QUIRK_ARM_MTK_4GB; 292 293 dom->iop = alloc_io_pgtable_ops(ARM_V7S, &dom->cfg, data); 294 if (!dom->iop) { 295 dev_err(data->dev, "Failed to alloc io pgtable\n"); 296 return -EINVAL; 297 } 298 299 /* Update our support page sizes bitmap */ 300 dom->domain.pgsize_bitmap = dom->cfg.pgsize_bitmap; 301 return 0; 302 } 303 304 static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type) 305 { 306 struct mtk_iommu_domain *dom; 307 308 if (type != IOMMU_DOMAIN_DMA) 309 return NULL; 310 311 dom = kzalloc(sizeof(*dom), GFP_KERNEL); 312 if (!dom) 313 return NULL; 314 315 if (iommu_get_dma_cookie(&dom->domain)) 316 goto free_dom; 317 318 if (mtk_iommu_domain_finalise(dom)) 319 goto put_dma_cookie; 320 321 dom->domain.geometry.aperture_start = 0; 322 dom->domain.geometry.aperture_end = DMA_BIT_MASK(32); 323 dom->domain.geometry.force_aperture = true; 324 325 return &dom->domain; 326 327 put_dma_cookie: 328 iommu_put_dma_cookie(&dom->domain); 329 free_dom: 330 kfree(dom); 331 return NULL; 332 } 333 334 static void mtk_iommu_domain_free(struct iommu_domain *domain) 335 { 336 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 337 338 free_io_pgtable_ops(dom->iop); 339 iommu_put_dma_cookie(domain); 340 kfree(to_mtk_domain(domain)); 341 } 342 343 static int mtk_iommu_attach_device(struct iommu_domain *domain, 344 struct device *dev) 345 { 346 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 347 struct mtk_iommu_data *data = dev_iommu_fwspec_get(dev)->iommu_priv; 348 349 if (!data) 350 return -ENODEV; 351 352 /* Update the pgtable base address register of the M4U HW */ 353 if (!data->m4u_dom) { 354 data->m4u_dom = dom; 355 writel(dom->cfg.arm_v7s_cfg.ttbr[0], 356 data->base + REG_MMU_PT_BASE_ADDR); 357 } 358 359 mtk_iommu_config(data, dev, true); 360 return 0; 361 } 362 363 static void mtk_iommu_detach_device(struct iommu_domain *domain, 364 struct device *dev) 365 { 366 struct mtk_iommu_data *data = dev_iommu_fwspec_get(dev)->iommu_priv; 367 368 if (!data) 369 return; 370 371 mtk_iommu_config(data, dev, false); 372 } 373 374 static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova, 375 phys_addr_t paddr, size_t size, int prot) 376 { 377 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 378 unsigned long flags; 379 int ret; 380 381 spin_lock_irqsave(&dom->pgtlock, flags); 382 ret = dom->iop->map(dom->iop, iova, paddr & DMA_BIT_MASK(32), 383 size, prot); 384 spin_unlock_irqrestore(&dom->pgtlock, flags); 385 386 return ret; 387 } 388 389 static size_t mtk_iommu_unmap(struct iommu_domain *domain, 390 unsigned long iova, size_t size, 391 struct iommu_iotlb_gather *gather) 392 { 393 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 394 unsigned long flags; 395 size_t unmapsz; 396 397 spin_lock_irqsave(&dom->pgtlock, flags); 398 unmapsz = dom->iop->unmap(dom->iop, iova, size); 399 spin_unlock_irqrestore(&dom->pgtlock, flags); 400 401 return unmapsz; 402 } 403 404 static void mtk_iommu_flush_iotlb_all(struct iommu_domain *domain) 405 { 406 mtk_iommu_tlb_sync(mtk_iommu_get_m4u_data()); 407 } 408 409 static void mtk_iommu_iotlb_sync(struct iommu_domain *domain, 410 struct iommu_iotlb_gather *gather) 411 { 412 mtk_iommu_tlb_sync(mtk_iommu_get_m4u_data()); 413 } 414 415 static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain, 416 dma_addr_t iova) 417 { 418 struct mtk_iommu_domain *dom = to_mtk_domain(domain); 419 struct mtk_iommu_data *data = mtk_iommu_get_m4u_data(); 420 unsigned long flags; 421 phys_addr_t pa; 422 423 spin_lock_irqsave(&dom->pgtlock, flags); 424 pa = dom->iop->iova_to_phys(dom->iop, iova); 425 spin_unlock_irqrestore(&dom->pgtlock, flags); 426 427 if (data->enable_4GB) 428 pa |= BIT_ULL(32); 429 430 return pa; 431 } 432 433 static int mtk_iommu_add_device(struct device *dev) 434 { 435 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 436 struct mtk_iommu_data *data; 437 struct iommu_group *group; 438 439 if (!fwspec || fwspec->ops != &mtk_iommu_ops) 440 return -ENODEV; /* Not a iommu client device */ 441 442 data = fwspec->iommu_priv; 443 iommu_device_link(&data->iommu, dev); 444 445 group = iommu_group_get_for_dev(dev); 446 if (IS_ERR(group)) 447 return PTR_ERR(group); 448 449 iommu_group_put(group); 450 return 0; 451 } 452 453 static void mtk_iommu_remove_device(struct device *dev) 454 { 455 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 456 struct mtk_iommu_data *data; 457 458 if (!fwspec || fwspec->ops != &mtk_iommu_ops) 459 return; 460 461 data = fwspec->iommu_priv; 462 iommu_device_unlink(&data->iommu, dev); 463 464 iommu_group_remove_device(dev); 465 iommu_fwspec_free(dev); 466 } 467 468 static struct iommu_group *mtk_iommu_device_group(struct device *dev) 469 { 470 struct mtk_iommu_data *data = mtk_iommu_get_m4u_data(); 471 472 if (!data) 473 return ERR_PTR(-ENODEV); 474 475 /* All the client devices are in the same m4u iommu-group */ 476 if (!data->m4u_group) { 477 data->m4u_group = iommu_group_alloc(); 478 if (IS_ERR(data->m4u_group)) 479 dev_err(dev, "Failed to allocate M4U IOMMU group\n"); 480 } else { 481 iommu_group_ref_get(data->m4u_group); 482 } 483 return data->m4u_group; 484 } 485 486 static int mtk_iommu_of_xlate(struct device *dev, struct of_phandle_args *args) 487 { 488 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 489 struct platform_device *m4updev; 490 491 if (args->args_count != 1) { 492 dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n", 493 args->args_count); 494 return -EINVAL; 495 } 496 497 if (!fwspec->iommu_priv) { 498 /* Get the m4u device */ 499 m4updev = of_find_device_by_node(args->np); 500 if (WARN_ON(!m4updev)) 501 return -EINVAL; 502 503 fwspec->iommu_priv = platform_get_drvdata(m4updev); 504 } 505 506 return iommu_fwspec_add_ids(dev, args->args, 1); 507 } 508 509 static const struct iommu_ops mtk_iommu_ops = { 510 .domain_alloc = mtk_iommu_domain_alloc, 511 .domain_free = mtk_iommu_domain_free, 512 .attach_dev = mtk_iommu_attach_device, 513 .detach_dev = mtk_iommu_detach_device, 514 .map = mtk_iommu_map, 515 .unmap = mtk_iommu_unmap, 516 .flush_iotlb_all = mtk_iommu_flush_iotlb_all, 517 .iotlb_sync = mtk_iommu_iotlb_sync, 518 .iova_to_phys = mtk_iommu_iova_to_phys, 519 .add_device = mtk_iommu_add_device, 520 .remove_device = mtk_iommu_remove_device, 521 .device_group = mtk_iommu_device_group, 522 .of_xlate = mtk_iommu_of_xlate, 523 .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M, 524 }; 525 526 static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) 527 { 528 u32 regval; 529 int ret; 530 531 ret = clk_prepare_enable(data->bclk); 532 if (ret) { 533 dev_err(data->dev, "Failed to enable iommu bclk(%d)\n", ret); 534 return ret; 535 } 536 537 regval = F_MMU_TF_PROTECT_SEL(2, data); 538 if (data->m4u_plat == M4U_MT8173) 539 regval |= F_MMU_PREFETCH_RT_REPLACE_MOD; 540 writel_relaxed(regval, data->base + REG_MMU_CTRL_REG); 541 542 regval = F_L2_MULIT_HIT_EN | 543 F_TABLE_WALK_FAULT_INT_EN | 544 F_PREETCH_FIFO_OVERFLOW_INT_EN | 545 F_MISS_FIFO_OVERFLOW_INT_EN | 546 F_PREFETCH_FIFO_ERR_INT_EN | 547 F_MISS_FIFO_ERR_INT_EN; 548 writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0); 549 550 regval = F_INT_TRANSLATION_FAULT | 551 F_INT_MAIN_MULTI_HIT_FAULT | 552 F_INT_INVALID_PA_FAULT | 553 F_INT_ENTRY_REPLACEMENT_FAULT | 554 F_INT_TLB_MISS_FAULT | 555 F_INT_MISS_TRANSACTION_FIFO_FAULT | 556 F_INT_PRETETCH_TRANSATION_FIFO_FAULT; 557 writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL); 558 559 if (data->m4u_plat == M4U_MT8173) 560 regval = (data->protect_base >> 1) | (data->enable_4GB << 31); 561 else 562 regval = lower_32_bits(data->protect_base) | 563 upper_32_bits(data->protect_base); 564 writel_relaxed(regval, data->base + REG_MMU_IVRP_PADDR); 565 566 if (data->enable_4GB && data->m4u_plat != M4U_MT8173) { 567 /* 568 * If 4GB mode is enabled, the validate PA range is from 569 * 0x1_0000_0000 to 0x1_ffff_ffff. here record bit[32:30]. 570 */ 571 regval = F_MMU_VLD_PA_RNG(7, 4); 572 writel_relaxed(regval, data->base + REG_MMU_VLD_PA_RNG); 573 } 574 writel_relaxed(0, data->base + REG_MMU_DCM_DIS); 575 576 /* It's MISC control register whose default value is ok except mt8173.*/ 577 if (data->m4u_plat == M4U_MT8173) 578 writel_relaxed(0, data->base + REG_MMU_STANDARD_AXI_MODE); 579 580 if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0, 581 dev_name(data->dev), (void *)data)) { 582 writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR); 583 clk_disable_unprepare(data->bclk); 584 dev_err(data->dev, "Failed @ IRQ-%d Request\n", data->irq); 585 return -ENODEV; 586 } 587 588 return 0; 589 } 590 591 static const struct component_master_ops mtk_iommu_com_ops = { 592 .bind = mtk_iommu_bind, 593 .unbind = mtk_iommu_unbind, 594 }; 595 596 static int mtk_iommu_probe(struct platform_device *pdev) 597 { 598 struct mtk_iommu_data *data; 599 struct device *dev = &pdev->dev; 600 struct resource *res; 601 resource_size_t ioaddr; 602 struct component_match *match = NULL; 603 void *protect; 604 int i, larb_nr, ret; 605 606 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 607 if (!data) 608 return -ENOMEM; 609 data->dev = dev; 610 data->m4u_plat = (enum mtk_iommu_plat)of_device_get_match_data(dev); 611 612 /* Protect memory. HW will access here while translation fault.*/ 613 protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2, GFP_KERNEL); 614 if (!protect) 615 return -ENOMEM; 616 data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN); 617 618 /* Whether the current dram is over 4GB */ 619 data->enable_4GB = !!(max_pfn > (BIT_ULL(32) >> PAGE_SHIFT)); 620 621 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 622 data->base = devm_ioremap_resource(dev, res); 623 if (IS_ERR(data->base)) 624 return PTR_ERR(data->base); 625 ioaddr = res->start; 626 627 data->irq = platform_get_irq(pdev, 0); 628 if (data->irq < 0) 629 return data->irq; 630 631 data->bclk = devm_clk_get(dev, "bclk"); 632 if (IS_ERR(data->bclk)) 633 return PTR_ERR(data->bclk); 634 635 larb_nr = of_count_phandle_with_args(dev->of_node, 636 "mediatek,larbs", NULL); 637 if (larb_nr < 0) 638 return larb_nr; 639 data->smi_imu.larb_nr = larb_nr; 640 641 for (i = 0; i < larb_nr; i++) { 642 struct device_node *larbnode; 643 struct platform_device *plarbdev; 644 u32 id; 645 646 larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i); 647 if (!larbnode) 648 return -EINVAL; 649 650 if (!of_device_is_available(larbnode)) { 651 of_node_put(larbnode); 652 continue; 653 } 654 655 ret = of_property_read_u32(larbnode, "mediatek,larb-id", &id); 656 if (ret)/* The id is consecutive if there is no this property */ 657 id = i; 658 659 plarbdev = of_find_device_by_node(larbnode); 660 if (!plarbdev) { 661 of_node_put(larbnode); 662 return -EPROBE_DEFER; 663 } 664 data->smi_imu.larb_imu[id].dev = &plarbdev->dev; 665 666 component_match_add_release(dev, &match, release_of, 667 compare_of, larbnode); 668 } 669 670 platform_set_drvdata(pdev, data); 671 672 ret = mtk_iommu_hw_init(data); 673 if (ret) 674 return ret; 675 676 ret = iommu_device_sysfs_add(&data->iommu, dev, NULL, 677 "mtk-iommu.%pa", &ioaddr); 678 if (ret) 679 return ret; 680 681 iommu_device_set_ops(&data->iommu, &mtk_iommu_ops); 682 iommu_device_set_fwnode(&data->iommu, &pdev->dev.of_node->fwnode); 683 684 ret = iommu_device_register(&data->iommu); 685 if (ret) 686 return ret; 687 688 list_add_tail(&data->list, &m4ulist); 689 690 if (!iommu_present(&platform_bus_type)) 691 bus_set_iommu(&platform_bus_type, &mtk_iommu_ops); 692 693 return component_master_add_with_match(dev, &mtk_iommu_com_ops, match); 694 } 695 696 static int mtk_iommu_remove(struct platform_device *pdev) 697 { 698 struct mtk_iommu_data *data = platform_get_drvdata(pdev); 699 700 iommu_device_sysfs_remove(&data->iommu); 701 iommu_device_unregister(&data->iommu); 702 703 if (iommu_present(&platform_bus_type)) 704 bus_set_iommu(&platform_bus_type, NULL); 705 706 clk_disable_unprepare(data->bclk); 707 devm_free_irq(&pdev->dev, data->irq, data); 708 component_master_del(&pdev->dev, &mtk_iommu_com_ops); 709 return 0; 710 } 711 712 static int __maybe_unused mtk_iommu_suspend(struct device *dev) 713 { 714 struct mtk_iommu_data *data = dev_get_drvdata(dev); 715 struct mtk_iommu_suspend_reg *reg = &data->reg; 716 void __iomem *base = data->base; 717 718 reg->standard_axi_mode = readl_relaxed(base + 719 REG_MMU_STANDARD_AXI_MODE); 720 reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS); 721 reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG); 722 reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL0); 723 reg->int_main_control = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL); 724 reg->ivrp_paddr = readl_relaxed(base + REG_MMU_IVRP_PADDR); 725 clk_disable_unprepare(data->bclk); 726 return 0; 727 } 728 729 static int __maybe_unused mtk_iommu_resume(struct device *dev) 730 { 731 struct mtk_iommu_data *data = dev_get_drvdata(dev); 732 struct mtk_iommu_suspend_reg *reg = &data->reg; 733 void __iomem *base = data->base; 734 int ret; 735 736 ret = clk_prepare_enable(data->bclk); 737 if (ret) { 738 dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret); 739 return ret; 740 } 741 writel_relaxed(reg->standard_axi_mode, 742 base + REG_MMU_STANDARD_AXI_MODE); 743 writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS); 744 writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG); 745 writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL0); 746 writel_relaxed(reg->int_main_control, base + REG_MMU_INT_MAIN_CONTROL); 747 writel_relaxed(reg->ivrp_paddr, base + REG_MMU_IVRP_PADDR); 748 if (data->m4u_dom) 749 writel(data->m4u_dom->cfg.arm_v7s_cfg.ttbr[0], 750 base + REG_MMU_PT_BASE_ADDR); 751 return 0; 752 } 753 754 static const struct dev_pm_ops mtk_iommu_pm_ops = { 755 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_iommu_suspend, mtk_iommu_resume) 756 }; 757 758 static const struct of_device_id mtk_iommu_of_ids[] = { 759 { .compatible = "mediatek,mt2712-m4u", .data = (void *)M4U_MT2712}, 760 { .compatible = "mediatek,mt8173-m4u", .data = (void *)M4U_MT8173}, 761 {} 762 }; 763 764 static struct platform_driver mtk_iommu_driver = { 765 .probe = mtk_iommu_probe, 766 .remove = mtk_iommu_remove, 767 .driver = { 768 .name = "mtk-iommu", 769 .of_match_table = of_match_ptr(mtk_iommu_of_ids), 770 .pm = &mtk_iommu_pm_ops, 771 } 772 }; 773 774 static int __init mtk_iommu_init(void) 775 { 776 int ret; 777 778 ret = platform_driver_register(&mtk_iommu_driver); 779 if (ret != 0) 780 pr_err("Failed to register MTK IOMMU driver\n"); 781 782 return ret; 783 } 784 785 subsys_initcall(mtk_iommu_init) 786