1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved. 3 * 4 * Author: Stepan Moskovchenko <stepanm@codeaurora.org> 5 */ 6 7 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 8 #include <linux/kernel.h> 9 #include <linux/init.h> 10 #include <linux/platform_device.h> 11 #include <linux/errno.h> 12 #include <linux/io.h> 13 #include <linux/io-pgtable.h> 14 #include <linux/interrupt.h> 15 #include <linux/list.h> 16 #include <linux/spinlock.h> 17 #include <linux/slab.h> 18 #include <linux/iommu.h> 19 #include <linux/clk.h> 20 #include <linux/err.h> 21 #include <linux/of_iommu.h> 22 23 #include <asm/cacheflush.h> 24 #include <linux/sizes.h> 25 26 #include "msm_iommu_hw-8xxx.h" 27 #include "msm_iommu.h" 28 29 #define MRC(reg, processor, op1, crn, crm, op2) \ 30 __asm__ __volatile__ ( \ 31 " mrc " #processor "," #op1 ", %0," #crn "," #crm "," #op2 "\n" \ 32 : "=r" (reg)) 33 34 /* bitmap of the page sizes currently supported */ 35 #define MSM_IOMMU_PGSIZES (SZ_4K | SZ_64K | SZ_1M | SZ_16M) 36 37 DEFINE_SPINLOCK(msm_iommu_lock); 38 static LIST_HEAD(qcom_iommu_devices); 39 static struct iommu_ops msm_iommu_ops; 40 41 struct msm_priv { 42 struct list_head list_attached; 43 struct iommu_domain domain; 44 struct io_pgtable_cfg cfg; 45 struct io_pgtable_ops *iop; 46 struct device *dev; 47 spinlock_t pgtlock; /* pagetable lock */ 48 }; 49 50 static struct msm_priv *to_msm_priv(struct iommu_domain *dom) 51 { 52 return container_of(dom, struct msm_priv, domain); 53 } 54 55 static int __enable_clocks(struct msm_iommu_dev *iommu) 56 { 57 int ret; 58 59 ret = clk_enable(iommu->pclk); 60 if (ret) 61 goto fail; 62 63 if (iommu->clk) { 64 ret = clk_enable(iommu->clk); 65 if (ret) 66 clk_disable(iommu->pclk); 67 } 68 fail: 69 return ret; 70 } 71 72 static void __disable_clocks(struct msm_iommu_dev *iommu) 73 { 74 if (iommu->clk) 75 clk_disable(iommu->clk); 76 clk_disable(iommu->pclk); 77 } 78 79 static void msm_iommu_reset(void __iomem *base, int ncb) 80 { 81 int ctx; 82 83 SET_RPUE(base, 0); 84 SET_RPUEIE(base, 0); 85 SET_ESRRESTORE(base, 0); 86 SET_TBE(base, 0); 87 SET_CR(base, 0); 88 SET_SPDMBE(base, 0); 89 SET_TESTBUSCR(base, 0); 90 SET_TLBRSW(base, 0); 91 SET_GLOBAL_TLBIALL(base, 0); 92 SET_RPU_ACR(base, 0); 93 SET_TLBLKCRWE(base, 1); 94 95 for (ctx = 0; ctx < ncb; ctx++) { 96 SET_BPRCOSH(base, ctx, 0); 97 SET_BPRCISH(base, ctx, 0); 98 SET_BPRCNSH(base, ctx, 0); 99 SET_BPSHCFG(base, ctx, 0); 100 SET_BPMTCFG(base, ctx, 0); 101 SET_ACTLR(base, ctx, 0); 102 SET_SCTLR(base, ctx, 0); 103 SET_FSRRESTORE(base, ctx, 0); 104 SET_TTBR0(base, ctx, 0); 105 SET_TTBR1(base, ctx, 0); 106 SET_TTBCR(base, ctx, 0); 107 SET_BFBCR(base, ctx, 0); 108 SET_PAR(base, ctx, 0); 109 SET_FAR(base, ctx, 0); 110 SET_CTX_TLBIALL(base, ctx, 0); 111 SET_TLBFLPTER(base, ctx, 0); 112 SET_TLBSLPTER(base, ctx, 0); 113 SET_TLBLKCR(base, ctx, 0); 114 SET_CONTEXTIDR(base, ctx, 0); 115 } 116 } 117 118 static void __flush_iotlb(void *cookie) 119 { 120 struct msm_priv *priv = cookie; 121 struct msm_iommu_dev *iommu = NULL; 122 struct msm_iommu_ctx_dev *master; 123 int ret = 0; 124 125 list_for_each_entry(iommu, &priv->list_attached, dom_node) { 126 ret = __enable_clocks(iommu); 127 if (ret) 128 goto fail; 129 130 list_for_each_entry(master, &iommu->ctx_list, list) 131 SET_CTX_TLBIALL(iommu->base, master->num, 0); 132 133 __disable_clocks(iommu); 134 } 135 fail: 136 return; 137 } 138 139 static void __flush_iotlb_range(unsigned long iova, size_t size, 140 size_t granule, bool leaf, void *cookie) 141 { 142 struct msm_priv *priv = cookie; 143 struct msm_iommu_dev *iommu = NULL; 144 struct msm_iommu_ctx_dev *master; 145 int ret = 0; 146 int temp_size; 147 148 list_for_each_entry(iommu, &priv->list_attached, dom_node) { 149 ret = __enable_clocks(iommu); 150 if (ret) 151 goto fail; 152 153 list_for_each_entry(master, &iommu->ctx_list, list) { 154 temp_size = size; 155 do { 156 iova &= TLBIVA_VA; 157 iova |= GET_CONTEXTIDR_ASID(iommu->base, 158 master->num); 159 SET_TLBIVA(iommu->base, master->num, iova); 160 iova += granule; 161 } while (temp_size -= granule); 162 } 163 164 __disable_clocks(iommu); 165 } 166 167 fail: 168 return; 169 } 170 171 static void __flush_iotlb_sync(void *cookie) 172 { 173 /* 174 * Nothing is needed here, the barrier to guarantee 175 * completion of the tlb sync operation is implicitly 176 * taken care when the iommu client does a writel before 177 * kick starting the other master. 178 */ 179 } 180 181 static void __flush_iotlb_walk(unsigned long iova, size_t size, 182 size_t granule, void *cookie) 183 { 184 __flush_iotlb_range(iova, size, granule, false, cookie); 185 __flush_iotlb_sync(cookie); 186 } 187 188 static void __flush_iotlb_leaf(unsigned long iova, size_t size, 189 size_t granule, void *cookie) 190 { 191 __flush_iotlb_range(iova, size, granule, true, cookie); 192 __flush_iotlb_sync(cookie); 193 } 194 195 static void __flush_iotlb_page(unsigned long iova, size_t granule, void *cookie) 196 { 197 __flush_iotlb_range(iova, granule, granule, true, cookie); 198 } 199 200 static const struct iommu_flush_ops msm_iommu_flush_ops = { 201 .tlb_flush_all = __flush_iotlb, 202 .tlb_flush_walk = __flush_iotlb_walk, 203 .tlb_flush_leaf = __flush_iotlb_leaf, 204 .tlb_add_page = __flush_iotlb_page, 205 .tlb_sync = __flush_iotlb_sync, 206 }; 207 208 static int msm_iommu_alloc_ctx(unsigned long *map, int start, int end) 209 { 210 int idx; 211 212 do { 213 idx = find_next_zero_bit(map, end, start); 214 if (idx == end) 215 return -ENOSPC; 216 } while (test_and_set_bit(idx, map)); 217 218 return idx; 219 } 220 221 static void msm_iommu_free_ctx(unsigned long *map, int idx) 222 { 223 clear_bit(idx, map); 224 } 225 226 static void config_mids(struct msm_iommu_dev *iommu, 227 struct msm_iommu_ctx_dev *master) 228 { 229 int mid, ctx, i; 230 231 for (i = 0; i < master->num_mids; i++) { 232 mid = master->mids[i]; 233 ctx = master->num; 234 235 SET_M2VCBR_N(iommu->base, mid, 0); 236 SET_CBACR_N(iommu->base, ctx, 0); 237 238 /* Set VMID = 0 */ 239 SET_VMID(iommu->base, mid, 0); 240 241 /* Set the context number for that MID to this context */ 242 SET_CBNDX(iommu->base, mid, ctx); 243 244 /* Set MID associated with this context bank to 0*/ 245 SET_CBVMID(iommu->base, ctx, 0); 246 247 /* Set the ASID for TLB tagging for this context */ 248 SET_CONTEXTIDR_ASID(iommu->base, ctx, ctx); 249 250 /* Set security bit override to be Non-secure */ 251 SET_NSCFG(iommu->base, mid, 3); 252 } 253 } 254 255 static void __reset_context(void __iomem *base, int ctx) 256 { 257 SET_BPRCOSH(base, ctx, 0); 258 SET_BPRCISH(base, ctx, 0); 259 SET_BPRCNSH(base, ctx, 0); 260 SET_BPSHCFG(base, ctx, 0); 261 SET_BPMTCFG(base, ctx, 0); 262 SET_ACTLR(base, ctx, 0); 263 SET_SCTLR(base, ctx, 0); 264 SET_FSRRESTORE(base, ctx, 0); 265 SET_TTBR0(base, ctx, 0); 266 SET_TTBR1(base, ctx, 0); 267 SET_TTBCR(base, ctx, 0); 268 SET_BFBCR(base, ctx, 0); 269 SET_PAR(base, ctx, 0); 270 SET_FAR(base, ctx, 0); 271 SET_CTX_TLBIALL(base, ctx, 0); 272 SET_TLBFLPTER(base, ctx, 0); 273 SET_TLBSLPTER(base, ctx, 0); 274 SET_TLBLKCR(base, ctx, 0); 275 } 276 277 static void __program_context(void __iomem *base, int ctx, 278 struct msm_priv *priv) 279 { 280 __reset_context(base, ctx); 281 282 /* Turn on TEX Remap */ 283 SET_TRE(base, ctx, 1); 284 SET_AFE(base, ctx, 1); 285 286 /* Set up HTW mode */ 287 /* TLB miss configuration: perform HTW on miss */ 288 SET_TLBMCFG(base, ctx, 0x3); 289 290 /* V2P configuration: HTW for access */ 291 SET_V2PCFG(base, ctx, 0x3); 292 293 SET_TTBCR(base, ctx, priv->cfg.arm_v7s_cfg.tcr); 294 SET_TTBR0(base, ctx, priv->cfg.arm_v7s_cfg.ttbr[0]); 295 SET_TTBR1(base, ctx, priv->cfg.arm_v7s_cfg.ttbr[1]); 296 297 /* Set prrr and nmrr */ 298 SET_PRRR(base, ctx, priv->cfg.arm_v7s_cfg.prrr); 299 SET_NMRR(base, ctx, priv->cfg.arm_v7s_cfg.nmrr); 300 301 /* Invalidate the TLB for this context */ 302 SET_CTX_TLBIALL(base, ctx, 0); 303 304 /* Set interrupt number to "secure" interrupt */ 305 SET_IRPTNDX(base, ctx, 0); 306 307 /* Enable context fault interrupt */ 308 SET_CFEIE(base, ctx, 1); 309 310 /* Stall access on a context fault and let the handler deal with it */ 311 SET_CFCFG(base, ctx, 1); 312 313 /* Redirect all cacheable requests to L2 slave port. */ 314 SET_RCISH(base, ctx, 1); 315 SET_RCOSH(base, ctx, 1); 316 SET_RCNSH(base, ctx, 1); 317 318 /* Turn on BFB prefetch */ 319 SET_BFBDFE(base, ctx, 1); 320 321 /* Enable the MMU */ 322 SET_M(base, ctx, 1); 323 } 324 325 static struct iommu_domain *msm_iommu_domain_alloc(unsigned type) 326 { 327 struct msm_priv *priv; 328 329 if (type != IOMMU_DOMAIN_UNMANAGED) 330 return NULL; 331 332 priv = kzalloc(sizeof(*priv), GFP_KERNEL); 333 if (!priv) 334 goto fail_nomem; 335 336 INIT_LIST_HEAD(&priv->list_attached); 337 338 priv->domain.geometry.aperture_start = 0; 339 priv->domain.geometry.aperture_end = (1ULL << 32) - 1; 340 priv->domain.geometry.force_aperture = true; 341 342 return &priv->domain; 343 344 fail_nomem: 345 kfree(priv); 346 return NULL; 347 } 348 349 static void msm_iommu_domain_free(struct iommu_domain *domain) 350 { 351 struct msm_priv *priv; 352 unsigned long flags; 353 354 spin_lock_irqsave(&msm_iommu_lock, flags); 355 priv = to_msm_priv(domain); 356 kfree(priv); 357 spin_unlock_irqrestore(&msm_iommu_lock, flags); 358 } 359 360 static int msm_iommu_domain_config(struct msm_priv *priv) 361 { 362 spin_lock_init(&priv->pgtlock); 363 364 priv->cfg = (struct io_pgtable_cfg) { 365 .quirks = IO_PGTABLE_QUIRK_TLBI_ON_MAP, 366 .pgsize_bitmap = msm_iommu_ops.pgsize_bitmap, 367 .ias = 32, 368 .oas = 32, 369 .tlb = &msm_iommu_flush_ops, 370 .iommu_dev = priv->dev, 371 }; 372 373 priv->iop = alloc_io_pgtable_ops(ARM_V7S, &priv->cfg, priv); 374 if (!priv->iop) { 375 dev_err(priv->dev, "Failed to allocate pgtable\n"); 376 return -EINVAL; 377 } 378 379 msm_iommu_ops.pgsize_bitmap = priv->cfg.pgsize_bitmap; 380 381 return 0; 382 } 383 384 /* Must be called under msm_iommu_lock */ 385 static struct msm_iommu_dev *find_iommu_for_dev(struct device *dev) 386 { 387 struct msm_iommu_dev *iommu, *ret = NULL; 388 struct msm_iommu_ctx_dev *master; 389 390 list_for_each_entry(iommu, &qcom_iommu_devices, dev_node) { 391 master = list_first_entry(&iommu->ctx_list, 392 struct msm_iommu_ctx_dev, 393 list); 394 if (master->of_node == dev->of_node) { 395 ret = iommu; 396 break; 397 } 398 } 399 400 return ret; 401 } 402 403 static int msm_iommu_add_device(struct device *dev) 404 { 405 struct msm_iommu_dev *iommu; 406 struct iommu_group *group; 407 unsigned long flags; 408 409 spin_lock_irqsave(&msm_iommu_lock, flags); 410 iommu = find_iommu_for_dev(dev); 411 spin_unlock_irqrestore(&msm_iommu_lock, flags); 412 413 if (iommu) 414 iommu_device_link(&iommu->iommu, dev); 415 else 416 return -ENODEV; 417 418 group = iommu_group_get_for_dev(dev); 419 if (IS_ERR(group)) 420 return PTR_ERR(group); 421 422 iommu_group_put(group); 423 424 return 0; 425 } 426 427 static void msm_iommu_remove_device(struct device *dev) 428 { 429 struct msm_iommu_dev *iommu; 430 unsigned long flags; 431 432 spin_lock_irqsave(&msm_iommu_lock, flags); 433 iommu = find_iommu_for_dev(dev); 434 spin_unlock_irqrestore(&msm_iommu_lock, flags); 435 436 if (iommu) 437 iommu_device_unlink(&iommu->iommu, dev); 438 439 iommu_group_remove_device(dev); 440 } 441 442 static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) 443 { 444 int ret = 0; 445 unsigned long flags; 446 struct msm_iommu_dev *iommu; 447 struct msm_priv *priv = to_msm_priv(domain); 448 struct msm_iommu_ctx_dev *master; 449 450 priv->dev = dev; 451 msm_iommu_domain_config(priv); 452 453 spin_lock_irqsave(&msm_iommu_lock, flags); 454 list_for_each_entry(iommu, &qcom_iommu_devices, dev_node) { 455 master = list_first_entry(&iommu->ctx_list, 456 struct msm_iommu_ctx_dev, 457 list); 458 if (master->of_node == dev->of_node) { 459 ret = __enable_clocks(iommu); 460 if (ret) 461 goto fail; 462 463 list_for_each_entry(master, &iommu->ctx_list, list) { 464 if (master->num) { 465 dev_err(dev, "domain already attached"); 466 ret = -EEXIST; 467 goto fail; 468 } 469 master->num = 470 msm_iommu_alloc_ctx(iommu->context_map, 471 0, iommu->ncb); 472 if (IS_ERR_VALUE(master->num)) { 473 ret = -ENODEV; 474 goto fail; 475 } 476 config_mids(iommu, master); 477 __program_context(iommu->base, master->num, 478 priv); 479 } 480 __disable_clocks(iommu); 481 list_add(&iommu->dom_node, &priv->list_attached); 482 } 483 } 484 485 fail: 486 spin_unlock_irqrestore(&msm_iommu_lock, flags); 487 488 return ret; 489 } 490 491 static void msm_iommu_detach_dev(struct iommu_domain *domain, 492 struct device *dev) 493 { 494 struct msm_priv *priv = to_msm_priv(domain); 495 unsigned long flags; 496 struct msm_iommu_dev *iommu; 497 struct msm_iommu_ctx_dev *master; 498 int ret; 499 500 free_io_pgtable_ops(priv->iop); 501 502 spin_lock_irqsave(&msm_iommu_lock, flags); 503 list_for_each_entry(iommu, &priv->list_attached, dom_node) { 504 ret = __enable_clocks(iommu); 505 if (ret) 506 goto fail; 507 508 list_for_each_entry(master, &iommu->ctx_list, list) { 509 msm_iommu_free_ctx(iommu->context_map, master->num); 510 __reset_context(iommu->base, master->num); 511 } 512 __disable_clocks(iommu); 513 } 514 fail: 515 spin_unlock_irqrestore(&msm_iommu_lock, flags); 516 } 517 518 static int msm_iommu_map(struct iommu_domain *domain, unsigned long iova, 519 phys_addr_t pa, size_t len, int prot) 520 { 521 struct msm_priv *priv = to_msm_priv(domain); 522 unsigned long flags; 523 int ret; 524 525 spin_lock_irqsave(&priv->pgtlock, flags); 526 ret = priv->iop->map(priv->iop, iova, pa, len, prot); 527 spin_unlock_irqrestore(&priv->pgtlock, flags); 528 529 return ret; 530 } 531 532 static size_t msm_iommu_unmap(struct iommu_domain *domain, unsigned long iova, 533 size_t len, struct iommu_iotlb_gather *gather) 534 { 535 struct msm_priv *priv = to_msm_priv(domain); 536 unsigned long flags; 537 538 spin_lock_irqsave(&priv->pgtlock, flags); 539 len = priv->iop->unmap(priv->iop, iova, len); 540 spin_unlock_irqrestore(&priv->pgtlock, flags); 541 542 return len; 543 } 544 545 static phys_addr_t msm_iommu_iova_to_phys(struct iommu_domain *domain, 546 dma_addr_t va) 547 { 548 struct msm_priv *priv; 549 struct msm_iommu_dev *iommu; 550 struct msm_iommu_ctx_dev *master; 551 unsigned int par; 552 unsigned long flags; 553 phys_addr_t ret = 0; 554 555 spin_lock_irqsave(&msm_iommu_lock, flags); 556 557 priv = to_msm_priv(domain); 558 iommu = list_first_entry(&priv->list_attached, 559 struct msm_iommu_dev, dom_node); 560 561 if (list_empty(&iommu->ctx_list)) 562 goto fail; 563 564 master = list_first_entry(&iommu->ctx_list, 565 struct msm_iommu_ctx_dev, list); 566 if (!master) 567 goto fail; 568 569 ret = __enable_clocks(iommu); 570 if (ret) 571 goto fail; 572 573 /* Invalidate context TLB */ 574 SET_CTX_TLBIALL(iommu->base, master->num, 0); 575 SET_V2PPR(iommu->base, master->num, va & V2Pxx_VA); 576 577 par = GET_PAR(iommu->base, master->num); 578 579 /* We are dealing with a supersection */ 580 if (GET_NOFAULT_SS(iommu->base, master->num)) 581 ret = (par & 0xFF000000) | (va & 0x00FFFFFF); 582 else /* Upper 20 bits from PAR, lower 12 from VA */ 583 ret = (par & 0xFFFFF000) | (va & 0x00000FFF); 584 585 if (GET_FAULT(iommu->base, master->num)) 586 ret = 0; 587 588 __disable_clocks(iommu); 589 fail: 590 spin_unlock_irqrestore(&msm_iommu_lock, flags); 591 return ret; 592 } 593 594 static bool msm_iommu_capable(enum iommu_cap cap) 595 { 596 return false; 597 } 598 599 static void print_ctx_regs(void __iomem *base, int ctx) 600 { 601 unsigned int fsr = GET_FSR(base, ctx); 602 pr_err("FAR = %08x PAR = %08x\n", 603 GET_FAR(base, ctx), GET_PAR(base, ctx)); 604 pr_err("FSR = %08x [%s%s%s%s%s%s%s%s%s%s]\n", fsr, 605 (fsr & 0x02) ? "TF " : "", 606 (fsr & 0x04) ? "AFF " : "", 607 (fsr & 0x08) ? "APF " : "", 608 (fsr & 0x10) ? "TLBMF " : "", 609 (fsr & 0x20) ? "HTWDEEF " : "", 610 (fsr & 0x40) ? "HTWSEEF " : "", 611 (fsr & 0x80) ? "MHF " : "", 612 (fsr & 0x10000) ? "SL " : "", 613 (fsr & 0x40000000) ? "SS " : "", 614 (fsr & 0x80000000) ? "MULTI " : ""); 615 616 pr_err("FSYNR0 = %08x FSYNR1 = %08x\n", 617 GET_FSYNR0(base, ctx), GET_FSYNR1(base, ctx)); 618 pr_err("TTBR0 = %08x TTBR1 = %08x\n", 619 GET_TTBR0(base, ctx), GET_TTBR1(base, ctx)); 620 pr_err("SCTLR = %08x ACTLR = %08x\n", 621 GET_SCTLR(base, ctx), GET_ACTLR(base, ctx)); 622 } 623 624 static void insert_iommu_master(struct device *dev, 625 struct msm_iommu_dev **iommu, 626 struct of_phandle_args *spec) 627 { 628 struct msm_iommu_ctx_dev *master = dev->archdata.iommu; 629 int sid; 630 631 if (list_empty(&(*iommu)->ctx_list)) { 632 master = kzalloc(sizeof(*master), GFP_ATOMIC); 633 master->of_node = dev->of_node; 634 list_add(&master->list, &(*iommu)->ctx_list); 635 dev->archdata.iommu = master; 636 } 637 638 for (sid = 0; sid < master->num_mids; sid++) 639 if (master->mids[sid] == spec->args[0]) { 640 dev_warn(dev, "Stream ID 0x%hx repeated; ignoring\n", 641 sid); 642 return; 643 } 644 645 master->mids[master->num_mids++] = spec->args[0]; 646 } 647 648 static int qcom_iommu_of_xlate(struct device *dev, 649 struct of_phandle_args *spec) 650 { 651 struct msm_iommu_dev *iommu; 652 unsigned long flags; 653 int ret = 0; 654 655 spin_lock_irqsave(&msm_iommu_lock, flags); 656 list_for_each_entry(iommu, &qcom_iommu_devices, dev_node) 657 if (iommu->dev->of_node == spec->np) 658 break; 659 660 if (!iommu || iommu->dev->of_node != spec->np) { 661 ret = -ENODEV; 662 goto fail; 663 } 664 665 insert_iommu_master(dev, &iommu, spec); 666 fail: 667 spin_unlock_irqrestore(&msm_iommu_lock, flags); 668 669 return ret; 670 } 671 672 irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id) 673 { 674 struct msm_iommu_dev *iommu = dev_id; 675 unsigned int fsr; 676 int i, ret; 677 678 spin_lock(&msm_iommu_lock); 679 680 if (!iommu) { 681 pr_err("Invalid device ID in context interrupt handler\n"); 682 goto fail; 683 } 684 685 pr_err("Unexpected IOMMU page fault!\n"); 686 pr_err("base = %08x\n", (unsigned int)iommu->base); 687 688 ret = __enable_clocks(iommu); 689 if (ret) 690 goto fail; 691 692 for (i = 0; i < iommu->ncb; i++) { 693 fsr = GET_FSR(iommu->base, i); 694 if (fsr) { 695 pr_err("Fault occurred in context %d.\n", i); 696 pr_err("Interesting registers:\n"); 697 print_ctx_regs(iommu->base, i); 698 SET_FSR(iommu->base, i, 0x4000000F); 699 } 700 } 701 __disable_clocks(iommu); 702 fail: 703 spin_unlock(&msm_iommu_lock); 704 return 0; 705 } 706 707 static struct iommu_ops msm_iommu_ops = { 708 .capable = msm_iommu_capable, 709 .domain_alloc = msm_iommu_domain_alloc, 710 .domain_free = msm_iommu_domain_free, 711 .attach_dev = msm_iommu_attach_dev, 712 .detach_dev = msm_iommu_detach_dev, 713 .map = msm_iommu_map, 714 .unmap = msm_iommu_unmap, 715 .iova_to_phys = msm_iommu_iova_to_phys, 716 .add_device = msm_iommu_add_device, 717 .remove_device = msm_iommu_remove_device, 718 .device_group = generic_device_group, 719 .pgsize_bitmap = MSM_IOMMU_PGSIZES, 720 .of_xlate = qcom_iommu_of_xlate, 721 }; 722 723 static int msm_iommu_probe(struct platform_device *pdev) 724 { 725 struct resource *r; 726 resource_size_t ioaddr; 727 struct msm_iommu_dev *iommu; 728 int ret, par, val; 729 730 iommu = devm_kzalloc(&pdev->dev, sizeof(*iommu), GFP_KERNEL); 731 if (!iommu) 732 return -ENODEV; 733 734 iommu->dev = &pdev->dev; 735 INIT_LIST_HEAD(&iommu->ctx_list); 736 737 iommu->pclk = devm_clk_get(iommu->dev, "smmu_pclk"); 738 if (IS_ERR(iommu->pclk)) { 739 dev_err(iommu->dev, "could not get smmu_pclk\n"); 740 return PTR_ERR(iommu->pclk); 741 } 742 743 ret = clk_prepare(iommu->pclk); 744 if (ret) { 745 dev_err(iommu->dev, "could not prepare smmu_pclk\n"); 746 return ret; 747 } 748 749 iommu->clk = devm_clk_get(iommu->dev, "iommu_clk"); 750 if (IS_ERR(iommu->clk)) { 751 dev_err(iommu->dev, "could not get iommu_clk\n"); 752 clk_unprepare(iommu->pclk); 753 return PTR_ERR(iommu->clk); 754 } 755 756 ret = clk_prepare(iommu->clk); 757 if (ret) { 758 dev_err(iommu->dev, "could not prepare iommu_clk\n"); 759 clk_unprepare(iommu->pclk); 760 return ret; 761 } 762 763 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 764 iommu->base = devm_ioremap_resource(iommu->dev, r); 765 if (IS_ERR(iommu->base)) { 766 dev_err(iommu->dev, "could not get iommu base\n"); 767 ret = PTR_ERR(iommu->base); 768 goto fail; 769 } 770 ioaddr = r->start; 771 772 iommu->irq = platform_get_irq(pdev, 0); 773 if (iommu->irq < 0) { 774 dev_err(iommu->dev, "could not get iommu irq\n"); 775 ret = -ENODEV; 776 goto fail; 777 } 778 779 ret = of_property_read_u32(iommu->dev->of_node, "qcom,ncb", &val); 780 if (ret) { 781 dev_err(iommu->dev, "could not get ncb\n"); 782 goto fail; 783 } 784 iommu->ncb = val; 785 786 msm_iommu_reset(iommu->base, iommu->ncb); 787 SET_M(iommu->base, 0, 1); 788 SET_PAR(iommu->base, 0, 0); 789 SET_V2PCFG(iommu->base, 0, 1); 790 SET_V2PPR(iommu->base, 0, 0); 791 par = GET_PAR(iommu->base, 0); 792 SET_V2PCFG(iommu->base, 0, 0); 793 SET_M(iommu->base, 0, 0); 794 795 if (!par) { 796 pr_err("Invalid PAR value detected\n"); 797 ret = -ENODEV; 798 goto fail; 799 } 800 801 ret = devm_request_threaded_irq(iommu->dev, iommu->irq, NULL, 802 msm_iommu_fault_handler, 803 IRQF_ONESHOT | IRQF_SHARED, 804 "msm_iommu_secure_irpt_handler", 805 iommu); 806 if (ret) { 807 pr_err("Request IRQ %d failed with ret=%d\n", iommu->irq, ret); 808 goto fail; 809 } 810 811 list_add(&iommu->dev_node, &qcom_iommu_devices); 812 813 ret = iommu_device_sysfs_add(&iommu->iommu, iommu->dev, NULL, 814 "msm-smmu.%pa", &ioaddr); 815 if (ret) { 816 pr_err("Could not add msm-smmu at %pa to sysfs\n", &ioaddr); 817 goto fail; 818 } 819 820 iommu_device_set_ops(&iommu->iommu, &msm_iommu_ops); 821 iommu_device_set_fwnode(&iommu->iommu, &pdev->dev.of_node->fwnode); 822 823 ret = iommu_device_register(&iommu->iommu); 824 if (ret) { 825 pr_err("Could not register msm-smmu at %pa\n", &ioaddr); 826 goto fail; 827 } 828 829 bus_set_iommu(&platform_bus_type, &msm_iommu_ops); 830 831 pr_info("device mapped at %p, irq %d with %d ctx banks\n", 832 iommu->base, iommu->irq, iommu->ncb); 833 834 return ret; 835 fail: 836 clk_unprepare(iommu->clk); 837 clk_unprepare(iommu->pclk); 838 return ret; 839 } 840 841 static const struct of_device_id msm_iommu_dt_match[] = { 842 { .compatible = "qcom,apq8064-iommu" }, 843 {} 844 }; 845 846 static int msm_iommu_remove(struct platform_device *pdev) 847 { 848 struct msm_iommu_dev *iommu = platform_get_drvdata(pdev); 849 850 clk_unprepare(iommu->clk); 851 clk_unprepare(iommu->pclk); 852 return 0; 853 } 854 855 static struct platform_driver msm_iommu_driver = { 856 .driver = { 857 .name = "msm_iommu", 858 .of_match_table = msm_iommu_dt_match, 859 }, 860 .probe = msm_iommu_probe, 861 .remove = msm_iommu_remove, 862 }; 863 864 static int __init msm_iommu_driver_init(void) 865 { 866 int ret; 867 868 ret = platform_driver_register(&msm_iommu_driver); 869 if (ret != 0) 870 pr_err("Failed to register IOMMU driver\n"); 871 872 return ret; 873 } 874 subsys_initcall(msm_iommu_driver_init); 875 876