1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved. 3 * 4 * Author: Stepan Moskovchenko <stepanm@codeaurora.org> 5 */ 6 7 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 8 #include <linux/kernel.h> 9 #include <linux/init.h> 10 #include <linux/platform_device.h> 11 #include <linux/errno.h> 12 #include <linux/io.h> 13 #include <linux/io-pgtable.h> 14 #include <linux/interrupt.h> 15 #include <linux/list.h> 16 #include <linux/spinlock.h> 17 #include <linux/slab.h> 18 #include <linux/iommu.h> 19 #include <linux/clk.h> 20 #include <linux/err.h> 21 #include <linux/of_iommu.h> 22 23 #include <asm/cacheflush.h> 24 #include <linux/sizes.h> 25 26 #include "msm_iommu_hw-8xxx.h" 27 #include "msm_iommu.h" 28 29 #define MRC(reg, processor, op1, crn, crm, op2) \ 30 __asm__ __volatile__ ( \ 31 " mrc " #processor "," #op1 ", %0," #crn "," #crm "," #op2 "\n" \ 32 : "=r" (reg)) 33 34 /* bitmap of the page sizes currently supported */ 35 #define MSM_IOMMU_PGSIZES (SZ_4K | SZ_64K | SZ_1M | SZ_16M) 36 37 DEFINE_SPINLOCK(msm_iommu_lock); 38 static LIST_HEAD(qcom_iommu_devices); 39 static struct iommu_ops msm_iommu_ops; 40 41 struct msm_priv { 42 struct list_head list_attached; 43 struct iommu_domain domain; 44 struct io_pgtable_cfg cfg; 45 struct io_pgtable_ops *iop; 46 struct device *dev; 47 spinlock_t pgtlock; /* pagetable lock */ 48 }; 49 50 static struct msm_priv *to_msm_priv(struct iommu_domain *dom) 51 { 52 return container_of(dom, struct msm_priv, domain); 53 } 54 55 static int __enable_clocks(struct msm_iommu_dev *iommu) 56 { 57 int ret; 58 59 ret = clk_enable(iommu->pclk); 60 if (ret) 61 goto fail; 62 63 if (iommu->clk) { 64 ret = clk_enable(iommu->clk); 65 if (ret) 66 clk_disable(iommu->pclk); 67 } 68 fail: 69 return ret; 70 } 71 72 static void __disable_clocks(struct msm_iommu_dev *iommu) 73 { 74 if (iommu->clk) 75 clk_disable(iommu->clk); 76 clk_disable(iommu->pclk); 77 } 78 79 static void msm_iommu_reset(void __iomem *base, int ncb) 80 { 81 int ctx; 82 83 SET_RPUE(base, 0); 84 SET_RPUEIE(base, 0); 85 SET_ESRRESTORE(base, 0); 86 SET_TBE(base, 0); 87 SET_CR(base, 0); 88 SET_SPDMBE(base, 0); 89 SET_TESTBUSCR(base, 0); 90 SET_TLBRSW(base, 0); 91 SET_GLOBAL_TLBIALL(base, 0); 92 SET_RPU_ACR(base, 0); 93 SET_TLBLKCRWE(base, 1); 94 95 for (ctx = 0; ctx < ncb; ctx++) { 96 SET_BPRCOSH(base, ctx, 0); 97 SET_BPRCISH(base, ctx, 0); 98 SET_BPRCNSH(base, ctx, 0); 99 SET_BPSHCFG(base, ctx, 0); 100 SET_BPMTCFG(base, ctx, 0); 101 SET_ACTLR(base, ctx, 0); 102 SET_SCTLR(base, ctx, 0); 103 SET_FSRRESTORE(base, ctx, 0); 104 SET_TTBR0(base, ctx, 0); 105 SET_TTBR1(base, ctx, 0); 106 SET_TTBCR(base, ctx, 0); 107 SET_BFBCR(base, ctx, 0); 108 SET_PAR(base, ctx, 0); 109 SET_FAR(base, ctx, 0); 110 SET_CTX_TLBIALL(base, ctx, 0); 111 SET_TLBFLPTER(base, ctx, 0); 112 SET_TLBSLPTER(base, ctx, 0); 113 SET_TLBLKCR(base, ctx, 0); 114 SET_CONTEXTIDR(base, ctx, 0); 115 } 116 } 117 118 static void __flush_iotlb(void *cookie) 119 { 120 struct msm_priv *priv = cookie; 121 struct msm_iommu_dev *iommu = NULL; 122 struct msm_iommu_ctx_dev *master; 123 int ret = 0; 124 125 list_for_each_entry(iommu, &priv->list_attached, dom_node) { 126 ret = __enable_clocks(iommu); 127 if (ret) 128 goto fail; 129 130 list_for_each_entry(master, &iommu->ctx_list, list) 131 SET_CTX_TLBIALL(iommu->base, master->num, 0); 132 133 __disable_clocks(iommu); 134 } 135 fail: 136 return; 137 } 138 139 static void __flush_iotlb_range(unsigned long iova, size_t size, 140 size_t granule, bool leaf, void *cookie) 141 { 142 struct msm_priv *priv = cookie; 143 struct msm_iommu_dev *iommu = NULL; 144 struct msm_iommu_ctx_dev *master; 145 int ret = 0; 146 int temp_size; 147 148 list_for_each_entry(iommu, &priv->list_attached, dom_node) { 149 ret = __enable_clocks(iommu); 150 if (ret) 151 goto fail; 152 153 list_for_each_entry(master, &iommu->ctx_list, list) { 154 temp_size = size; 155 do { 156 iova &= TLBIVA_VA; 157 iova |= GET_CONTEXTIDR_ASID(iommu->base, 158 master->num); 159 SET_TLBIVA(iommu->base, master->num, iova); 160 iova += granule; 161 } while (temp_size -= granule); 162 } 163 164 __disable_clocks(iommu); 165 } 166 167 fail: 168 return; 169 } 170 171 static void __flush_iotlb_sync(void *cookie) 172 { 173 /* 174 * Nothing is needed here, the barrier to guarantee 175 * completion of the tlb sync operation is implicitly 176 * taken care when the iommu client does a writel before 177 * kick starting the other master. 178 */ 179 } 180 181 static void __flush_iotlb_walk(unsigned long iova, size_t size, 182 size_t granule, void *cookie) 183 { 184 __flush_iotlb_range(iova, size, granule, false, cookie); 185 __flush_iotlb_sync(cookie); 186 } 187 188 static void __flush_iotlb_leaf(unsigned long iova, size_t size, 189 size_t granule, void *cookie) 190 { 191 __flush_iotlb_range(iova, size, granule, true, cookie); 192 __flush_iotlb_sync(cookie); 193 } 194 195 static const struct iommu_flush_ops msm_iommu_flush_ops = { 196 .tlb_flush_all = __flush_iotlb, 197 .tlb_flush_walk = __flush_iotlb_walk, 198 .tlb_flush_leaf = __flush_iotlb_leaf, 199 .tlb_add_flush = __flush_iotlb_range, 200 .tlb_sync = __flush_iotlb_sync, 201 }; 202 203 static int msm_iommu_alloc_ctx(unsigned long *map, int start, int end) 204 { 205 int idx; 206 207 do { 208 idx = find_next_zero_bit(map, end, start); 209 if (idx == end) 210 return -ENOSPC; 211 } while (test_and_set_bit(idx, map)); 212 213 return idx; 214 } 215 216 static void msm_iommu_free_ctx(unsigned long *map, int idx) 217 { 218 clear_bit(idx, map); 219 } 220 221 static void config_mids(struct msm_iommu_dev *iommu, 222 struct msm_iommu_ctx_dev *master) 223 { 224 int mid, ctx, i; 225 226 for (i = 0; i < master->num_mids; i++) { 227 mid = master->mids[i]; 228 ctx = master->num; 229 230 SET_M2VCBR_N(iommu->base, mid, 0); 231 SET_CBACR_N(iommu->base, ctx, 0); 232 233 /* Set VMID = 0 */ 234 SET_VMID(iommu->base, mid, 0); 235 236 /* Set the context number for that MID to this context */ 237 SET_CBNDX(iommu->base, mid, ctx); 238 239 /* Set MID associated with this context bank to 0*/ 240 SET_CBVMID(iommu->base, ctx, 0); 241 242 /* Set the ASID for TLB tagging for this context */ 243 SET_CONTEXTIDR_ASID(iommu->base, ctx, ctx); 244 245 /* Set security bit override to be Non-secure */ 246 SET_NSCFG(iommu->base, mid, 3); 247 } 248 } 249 250 static void __reset_context(void __iomem *base, int ctx) 251 { 252 SET_BPRCOSH(base, ctx, 0); 253 SET_BPRCISH(base, ctx, 0); 254 SET_BPRCNSH(base, ctx, 0); 255 SET_BPSHCFG(base, ctx, 0); 256 SET_BPMTCFG(base, ctx, 0); 257 SET_ACTLR(base, ctx, 0); 258 SET_SCTLR(base, ctx, 0); 259 SET_FSRRESTORE(base, ctx, 0); 260 SET_TTBR0(base, ctx, 0); 261 SET_TTBR1(base, ctx, 0); 262 SET_TTBCR(base, ctx, 0); 263 SET_BFBCR(base, ctx, 0); 264 SET_PAR(base, ctx, 0); 265 SET_FAR(base, ctx, 0); 266 SET_CTX_TLBIALL(base, ctx, 0); 267 SET_TLBFLPTER(base, ctx, 0); 268 SET_TLBSLPTER(base, ctx, 0); 269 SET_TLBLKCR(base, ctx, 0); 270 } 271 272 static void __program_context(void __iomem *base, int ctx, 273 struct msm_priv *priv) 274 { 275 __reset_context(base, ctx); 276 277 /* Turn on TEX Remap */ 278 SET_TRE(base, ctx, 1); 279 SET_AFE(base, ctx, 1); 280 281 /* Set up HTW mode */ 282 /* TLB miss configuration: perform HTW on miss */ 283 SET_TLBMCFG(base, ctx, 0x3); 284 285 /* V2P configuration: HTW for access */ 286 SET_V2PCFG(base, ctx, 0x3); 287 288 SET_TTBCR(base, ctx, priv->cfg.arm_v7s_cfg.tcr); 289 SET_TTBR0(base, ctx, priv->cfg.arm_v7s_cfg.ttbr[0]); 290 SET_TTBR1(base, ctx, priv->cfg.arm_v7s_cfg.ttbr[1]); 291 292 /* Set prrr and nmrr */ 293 SET_PRRR(base, ctx, priv->cfg.arm_v7s_cfg.prrr); 294 SET_NMRR(base, ctx, priv->cfg.arm_v7s_cfg.nmrr); 295 296 /* Invalidate the TLB for this context */ 297 SET_CTX_TLBIALL(base, ctx, 0); 298 299 /* Set interrupt number to "secure" interrupt */ 300 SET_IRPTNDX(base, ctx, 0); 301 302 /* Enable context fault interrupt */ 303 SET_CFEIE(base, ctx, 1); 304 305 /* Stall access on a context fault and let the handler deal with it */ 306 SET_CFCFG(base, ctx, 1); 307 308 /* Redirect all cacheable requests to L2 slave port. */ 309 SET_RCISH(base, ctx, 1); 310 SET_RCOSH(base, ctx, 1); 311 SET_RCNSH(base, ctx, 1); 312 313 /* Turn on BFB prefetch */ 314 SET_BFBDFE(base, ctx, 1); 315 316 /* Enable the MMU */ 317 SET_M(base, ctx, 1); 318 } 319 320 static struct iommu_domain *msm_iommu_domain_alloc(unsigned type) 321 { 322 struct msm_priv *priv; 323 324 if (type != IOMMU_DOMAIN_UNMANAGED) 325 return NULL; 326 327 priv = kzalloc(sizeof(*priv), GFP_KERNEL); 328 if (!priv) 329 goto fail_nomem; 330 331 INIT_LIST_HEAD(&priv->list_attached); 332 333 priv->domain.geometry.aperture_start = 0; 334 priv->domain.geometry.aperture_end = (1ULL << 32) - 1; 335 priv->domain.geometry.force_aperture = true; 336 337 return &priv->domain; 338 339 fail_nomem: 340 kfree(priv); 341 return NULL; 342 } 343 344 static void msm_iommu_domain_free(struct iommu_domain *domain) 345 { 346 struct msm_priv *priv; 347 unsigned long flags; 348 349 spin_lock_irqsave(&msm_iommu_lock, flags); 350 priv = to_msm_priv(domain); 351 kfree(priv); 352 spin_unlock_irqrestore(&msm_iommu_lock, flags); 353 } 354 355 static int msm_iommu_domain_config(struct msm_priv *priv) 356 { 357 spin_lock_init(&priv->pgtlock); 358 359 priv->cfg = (struct io_pgtable_cfg) { 360 .quirks = IO_PGTABLE_QUIRK_TLBI_ON_MAP, 361 .pgsize_bitmap = msm_iommu_ops.pgsize_bitmap, 362 .ias = 32, 363 .oas = 32, 364 .tlb = &msm_iommu_flush_ops, 365 .iommu_dev = priv->dev, 366 }; 367 368 priv->iop = alloc_io_pgtable_ops(ARM_V7S, &priv->cfg, priv); 369 if (!priv->iop) { 370 dev_err(priv->dev, "Failed to allocate pgtable\n"); 371 return -EINVAL; 372 } 373 374 msm_iommu_ops.pgsize_bitmap = priv->cfg.pgsize_bitmap; 375 376 return 0; 377 } 378 379 /* Must be called under msm_iommu_lock */ 380 static struct msm_iommu_dev *find_iommu_for_dev(struct device *dev) 381 { 382 struct msm_iommu_dev *iommu, *ret = NULL; 383 struct msm_iommu_ctx_dev *master; 384 385 list_for_each_entry(iommu, &qcom_iommu_devices, dev_node) { 386 master = list_first_entry(&iommu->ctx_list, 387 struct msm_iommu_ctx_dev, 388 list); 389 if (master->of_node == dev->of_node) { 390 ret = iommu; 391 break; 392 } 393 } 394 395 return ret; 396 } 397 398 static int msm_iommu_add_device(struct device *dev) 399 { 400 struct msm_iommu_dev *iommu; 401 struct iommu_group *group; 402 unsigned long flags; 403 404 spin_lock_irqsave(&msm_iommu_lock, flags); 405 iommu = find_iommu_for_dev(dev); 406 spin_unlock_irqrestore(&msm_iommu_lock, flags); 407 408 if (iommu) 409 iommu_device_link(&iommu->iommu, dev); 410 else 411 return -ENODEV; 412 413 group = iommu_group_get_for_dev(dev); 414 if (IS_ERR(group)) 415 return PTR_ERR(group); 416 417 iommu_group_put(group); 418 419 return 0; 420 } 421 422 static void msm_iommu_remove_device(struct device *dev) 423 { 424 struct msm_iommu_dev *iommu; 425 unsigned long flags; 426 427 spin_lock_irqsave(&msm_iommu_lock, flags); 428 iommu = find_iommu_for_dev(dev); 429 spin_unlock_irqrestore(&msm_iommu_lock, flags); 430 431 if (iommu) 432 iommu_device_unlink(&iommu->iommu, dev); 433 434 iommu_group_remove_device(dev); 435 } 436 437 static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) 438 { 439 int ret = 0; 440 unsigned long flags; 441 struct msm_iommu_dev *iommu; 442 struct msm_priv *priv = to_msm_priv(domain); 443 struct msm_iommu_ctx_dev *master; 444 445 priv->dev = dev; 446 msm_iommu_domain_config(priv); 447 448 spin_lock_irqsave(&msm_iommu_lock, flags); 449 list_for_each_entry(iommu, &qcom_iommu_devices, dev_node) { 450 master = list_first_entry(&iommu->ctx_list, 451 struct msm_iommu_ctx_dev, 452 list); 453 if (master->of_node == dev->of_node) { 454 ret = __enable_clocks(iommu); 455 if (ret) 456 goto fail; 457 458 list_for_each_entry(master, &iommu->ctx_list, list) { 459 if (master->num) { 460 dev_err(dev, "domain already attached"); 461 ret = -EEXIST; 462 goto fail; 463 } 464 master->num = 465 msm_iommu_alloc_ctx(iommu->context_map, 466 0, iommu->ncb); 467 if (IS_ERR_VALUE(master->num)) { 468 ret = -ENODEV; 469 goto fail; 470 } 471 config_mids(iommu, master); 472 __program_context(iommu->base, master->num, 473 priv); 474 } 475 __disable_clocks(iommu); 476 list_add(&iommu->dom_node, &priv->list_attached); 477 } 478 } 479 480 fail: 481 spin_unlock_irqrestore(&msm_iommu_lock, flags); 482 483 return ret; 484 } 485 486 static void msm_iommu_detach_dev(struct iommu_domain *domain, 487 struct device *dev) 488 { 489 struct msm_priv *priv = to_msm_priv(domain); 490 unsigned long flags; 491 struct msm_iommu_dev *iommu; 492 struct msm_iommu_ctx_dev *master; 493 int ret; 494 495 free_io_pgtable_ops(priv->iop); 496 497 spin_lock_irqsave(&msm_iommu_lock, flags); 498 list_for_each_entry(iommu, &priv->list_attached, dom_node) { 499 ret = __enable_clocks(iommu); 500 if (ret) 501 goto fail; 502 503 list_for_each_entry(master, &iommu->ctx_list, list) { 504 msm_iommu_free_ctx(iommu->context_map, master->num); 505 __reset_context(iommu->base, master->num); 506 } 507 __disable_clocks(iommu); 508 } 509 fail: 510 spin_unlock_irqrestore(&msm_iommu_lock, flags); 511 } 512 513 static int msm_iommu_map(struct iommu_domain *domain, unsigned long iova, 514 phys_addr_t pa, size_t len, int prot) 515 { 516 struct msm_priv *priv = to_msm_priv(domain); 517 unsigned long flags; 518 int ret; 519 520 spin_lock_irqsave(&priv->pgtlock, flags); 521 ret = priv->iop->map(priv->iop, iova, pa, len, prot); 522 spin_unlock_irqrestore(&priv->pgtlock, flags); 523 524 return ret; 525 } 526 527 static size_t msm_iommu_unmap(struct iommu_domain *domain, unsigned long iova, 528 size_t len, struct iommu_iotlb_gather *gather) 529 { 530 struct msm_priv *priv = to_msm_priv(domain); 531 unsigned long flags; 532 533 spin_lock_irqsave(&priv->pgtlock, flags); 534 len = priv->iop->unmap(priv->iop, iova, len); 535 spin_unlock_irqrestore(&priv->pgtlock, flags); 536 537 return len; 538 } 539 540 static phys_addr_t msm_iommu_iova_to_phys(struct iommu_domain *domain, 541 dma_addr_t va) 542 { 543 struct msm_priv *priv; 544 struct msm_iommu_dev *iommu; 545 struct msm_iommu_ctx_dev *master; 546 unsigned int par; 547 unsigned long flags; 548 phys_addr_t ret = 0; 549 550 spin_lock_irqsave(&msm_iommu_lock, flags); 551 552 priv = to_msm_priv(domain); 553 iommu = list_first_entry(&priv->list_attached, 554 struct msm_iommu_dev, dom_node); 555 556 if (list_empty(&iommu->ctx_list)) 557 goto fail; 558 559 master = list_first_entry(&iommu->ctx_list, 560 struct msm_iommu_ctx_dev, list); 561 if (!master) 562 goto fail; 563 564 ret = __enable_clocks(iommu); 565 if (ret) 566 goto fail; 567 568 /* Invalidate context TLB */ 569 SET_CTX_TLBIALL(iommu->base, master->num, 0); 570 SET_V2PPR(iommu->base, master->num, va & V2Pxx_VA); 571 572 par = GET_PAR(iommu->base, master->num); 573 574 /* We are dealing with a supersection */ 575 if (GET_NOFAULT_SS(iommu->base, master->num)) 576 ret = (par & 0xFF000000) | (va & 0x00FFFFFF); 577 else /* Upper 20 bits from PAR, lower 12 from VA */ 578 ret = (par & 0xFFFFF000) | (va & 0x00000FFF); 579 580 if (GET_FAULT(iommu->base, master->num)) 581 ret = 0; 582 583 __disable_clocks(iommu); 584 fail: 585 spin_unlock_irqrestore(&msm_iommu_lock, flags); 586 return ret; 587 } 588 589 static bool msm_iommu_capable(enum iommu_cap cap) 590 { 591 return false; 592 } 593 594 static void print_ctx_regs(void __iomem *base, int ctx) 595 { 596 unsigned int fsr = GET_FSR(base, ctx); 597 pr_err("FAR = %08x PAR = %08x\n", 598 GET_FAR(base, ctx), GET_PAR(base, ctx)); 599 pr_err("FSR = %08x [%s%s%s%s%s%s%s%s%s%s]\n", fsr, 600 (fsr & 0x02) ? "TF " : "", 601 (fsr & 0x04) ? "AFF " : "", 602 (fsr & 0x08) ? "APF " : "", 603 (fsr & 0x10) ? "TLBMF " : "", 604 (fsr & 0x20) ? "HTWDEEF " : "", 605 (fsr & 0x40) ? "HTWSEEF " : "", 606 (fsr & 0x80) ? "MHF " : "", 607 (fsr & 0x10000) ? "SL " : "", 608 (fsr & 0x40000000) ? "SS " : "", 609 (fsr & 0x80000000) ? "MULTI " : ""); 610 611 pr_err("FSYNR0 = %08x FSYNR1 = %08x\n", 612 GET_FSYNR0(base, ctx), GET_FSYNR1(base, ctx)); 613 pr_err("TTBR0 = %08x TTBR1 = %08x\n", 614 GET_TTBR0(base, ctx), GET_TTBR1(base, ctx)); 615 pr_err("SCTLR = %08x ACTLR = %08x\n", 616 GET_SCTLR(base, ctx), GET_ACTLR(base, ctx)); 617 } 618 619 static void insert_iommu_master(struct device *dev, 620 struct msm_iommu_dev **iommu, 621 struct of_phandle_args *spec) 622 { 623 struct msm_iommu_ctx_dev *master = dev->archdata.iommu; 624 int sid; 625 626 if (list_empty(&(*iommu)->ctx_list)) { 627 master = kzalloc(sizeof(*master), GFP_ATOMIC); 628 master->of_node = dev->of_node; 629 list_add(&master->list, &(*iommu)->ctx_list); 630 dev->archdata.iommu = master; 631 } 632 633 for (sid = 0; sid < master->num_mids; sid++) 634 if (master->mids[sid] == spec->args[0]) { 635 dev_warn(dev, "Stream ID 0x%hx repeated; ignoring\n", 636 sid); 637 return; 638 } 639 640 master->mids[master->num_mids++] = spec->args[0]; 641 } 642 643 static int qcom_iommu_of_xlate(struct device *dev, 644 struct of_phandle_args *spec) 645 { 646 struct msm_iommu_dev *iommu; 647 unsigned long flags; 648 int ret = 0; 649 650 spin_lock_irqsave(&msm_iommu_lock, flags); 651 list_for_each_entry(iommu, &qcom_iommu_devices, dev_node) 652 if (iommu->dev->of_node == spec->np) 653 break; 654 655 if (!iommu || iommu->dev->of_node != spec->np) { 656 ret = -ENODEV; 657 goto fail; 658 } 659 660 insert_iommu_master(dev, &iommu, spec); 661 fail: 662 spin_unlock_irqrestore(&msm_iommu_lock, flags); 663 664 return ret; 665 } 666 667 irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id) 668 { 669 struct msm_iommu_dev *iommu = dev_id; 670 unsigned int fsr; 671 int i, ret; 672 673 spin_lock(&msm_iommu_lock); 674 675 if (!iommu) { 676 pr_err("Invalid device ID in context interrupt handler\n"); 677 goto fail; 678 } 679 680 pr_err("Unexpected IOMMU page fault!\n"); 681 pr_err("base = %08x\n", (unsigned int)iommu->base); 682 683 ret = __enable_clocks(iommu); 684 if (ret) 685 goto fail; 686 687 for (i = 0; i < iommu->ncb; i++) { 688 fsr = GET_FSR(iommu->base, i); 689 if (fsr) { 690 pr_err("Fault occurred in context %d.\n", i); 691 pr_err("Interesting registers:\n"); 692 print_ctx_regs(iommu->base, i); 693 SET_FSR(iommu->base, i, 0x4000000F); 694 } 695 } 696 __disable_clocks(iommu); 697 fail: 698 spin_unlock(&msm_iommu_lock); 699 return 0; 700 } 701 702 static struct iommu_ops msm_iommu_ops = { 703 .capable = msm_iommu_capable, 704 .domain_alloc = msm_iommu_domain_alloc, 705 .domain_free = msm_iommu_domain_free, 706 .attach_dev = msm_iommu_attach_dev, 707 .detach_dev = msm_iommu_detach_dev, 708 .map = msm_iommu_map, 709 .unmap = msm_iommu_unmap, 710 .iova_to_phys = msm_iommu_iova_to_phys, 711 .add_device = msm_iommu_add_device, 712 .remove_device = msm_iommu_remove_device, 713 .device_group = generic_device_group, 714 .pgsize_bitmap = MSM_IOMMU_PGSIZES, 715 .of_xlate = qcom_iommu_of_xlate, 716 }; 717 718 static int msm_iommu_probe(struct platform_device *pdev) 719 { 720 struct resource *r; 721 resource_size_t ioaddr; 722 struct msm_iommu_dev *iommu; 723 int ret, par, val; 724 725 iommu = devm_kzalloc(&pdev->dev, sizeof(*iommu), GFP_KERNEL); 726 if (!iommu) 727 return -ENODEV; 728 729 iommu->dev = &pdev->dev; 730 INIT_LIST_HEAD(&iommu->ctx_list); 731 732 iommu->pclk = devm_clk_get(iommu->dev, "smmu_pclk"); 733 if (IS_ERR(iommu->pclk)) { 734 dev_err(iommu->dev, "could not get smmu_pclk\n"); 735 return PTR_ERR(iommu->pclk); 736 } 737 738 ret = clk_prepare(iommu->pclk); 739 if (ret) { 740 dev_err(iommu->dev, "could not prepare smmu_pclk\n"); 741 return ret; 742 } 743 744 iommu->clk = devm_clk_get(iommu->dev, "iommu_clk"); 745 if (IS_ERR(iommu->clk)) { 746 dev_err(iommu->dev, "could not get iommu_clk\n"); 747 clk_unprepare(iommu->pclk); 748 return PTR_ERR(iommu->clk); 749 } 750 751 ret = clk_prepare(iommu->clk); 752 if (ret) { 753 dev_err(iommu->dev, "could not prepare iommu_clk\n"); 754 clk_unprepare(iommu->pclk); 755 return ret; 756 } 757 758 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 759 iommu->base = devm_ioremap_resource(iommu->dev, r); 760 if (IS_ERR(iommu->base)) { 761 dev_err(iommu->dev, "could not get iommu base\n"); 762 ret = PTR_ERR(iommu->base); 763 goto fail; 764 } 765 ioaddr = r->start; 766 767 iommu->irq = platform_get_irq(pdev, 0); 768 if (iommu->irq < 0) { 769 dev_err(iommu->dev, "could not get iommu irq\n"); 770 ret = -ENODEV; 771 goto fail; 772 } 773 774 ret = of_property_read_u32(iommu->dev->of_node, "qcom,ncb", &val); 775 if (ret) { 776 dev_err(iommu->dev, "could not get ncb\n"); 777 goto fail; 778 } 779 iommu->ncb = val; 780 781 msm_iommu_reset(iommu->base, iommu->ncb); 782 SET_M(iommu->base, 0, 1); 783 SET_PAR(iommu->base, 0, 0); 784 SET_V2PCFG(iommu->base, 0, 1); 785 SET_V2PPR(iommu->base, 0, 0); 786 par = GET_PAR(iommu->base, 0); 787 SET_V2PCFG(iommu->base, 0, 0); 788 SET_M(iommu->base, 0, 0); 789 790 if (!par) { 791 pr_err("Invalid PAR value detected\n"); 792 ret = -ENODEV; 793 goto fail; 794 } 795 796 ret = devm_request_threaded_irq(iommu->dev, iommu->irq, NULL, 797 msm_iommu_fault_handler, 798 IRQF_ONESHOT | IRQF_SHARED, 799 "msm_iommu_secure_irpt_handler", 800 iommu); 801 if (ret) { 802 pr_err("Request IRQ %d failed with ret=%d\n", iommu->irq, ret); 803 goto fail; 804 } 805 806 list_add(&iommu->dev_node, &qcom_iommu_devices); 807 808 ret = iommu_device_sysfs_add(&iommu->iommu, iommu->dev, NULL, 809 "msm-smmu.%pa", &ioaddr); 810 if (ret) { 811 pr_err("Could not add msm-smmu at %pa to sysfs\n", &ioaddr); 812 goto fail; 813 } 814 815 iommu_device_set_ops(&iommu->iommu, &msm_iommu_ops); 816 iommu_device_set_fwnode(&iommu->iommu, &pdev->dev.of_node->fwnode); 817 818 ret = iommu_device_register(&iommu->iommu); 819 if (ret) { 820 pr_err("Could not register msm-smmu at %pa\n", &ioaddr); 821 goto fail; 822 } 823 824 bus_set_iommu(&platform_bus_type, &msm_iommu_ops); 825 826 pr_info("device mapped at %p, irq %d with %d ctx banks\n", 827 iommu->base, iommu->irq, iommu->ncb); 828 829 return ret; 830 fail: 831 clk_unprepare(iommu->clk); 832 clk_unprepare(iommu->pclk); 833 return ret; 834 } 835 836 static const struct of_device_id msm_iommu_dt_match[] = { 837 { .compatible = "qcom,apq8064-iommu" }, 838 {} 839 }; 840 841 static int msm_iommu_remove(struct platform_device *pdev) 842 { 843 struct msm_iommu_dev *iommu = platform_get_drvdata(pdev); 844 845 clk_unprepare(iommu->clk); 846 clk_unprepare(iommu->pclk); 847 return 0; 848 } 849 850 static struct platform_driver msm_iommu_driver = { 851 .driver = { 852 .name = "msm_iommu", 853 .of_match_table = msm_iommu_dt_match, 854 }, 855 .probe = msm_iommu_probe, 856 .remove = msm_iommu_remove, 857 }; 858 859 static int __init msm_iommu_driver_init(void) 860 { 861 int ret; 862 863 ret = platform_driver_register(&msm_iommu_driver); 864 if (ret != 0) 865 pr_err("Failed to register IOMMU driver\n"); 866 867 return ret; 868 } 869 subsys_initcall(msm_iommu_driver_init); 870 871