1*7cef39ddSJean-Philippe Brucker /* SPDX-License-Identifier: GPL-2.0-only */ 2*7cef39ddSJean-Philippe Brucker #ifndef IO_PGTABLE_ARM_H_ 3*7cef39ddSJean-Philippe Brucker #define IO_PGTABLE_ARM_H_ 4*7cef39ddSJean-Philippe Brucker 5*7cef39ddSJean-Philippe Brucker #define ARM_LPAE_TCR_TG0_4K 0 6*7cef39ddSJean-Philippe Brucker #define ARM_LPAE_TCR_TG0_64K 1 7*7cef39ddSJean-Philippe Brucker #define ARM_LPAE_TCR_TG0_16K 2 8*7cef39ddSJean-Philippe Brucker 9*7cef39ddSJean-Philippe Brucker #define ARM_LPAE_TCR_TG1_16K 1 10*7cef39ddSJean-Philippe Brucker #define ARM_LPAE_TCR_TG1_4K 2 11*7cef39ddSJean-Philippe Brucker #define ARM_LPAE_TCR_TG1_64K 3 12*7cef39ddSJean-Philippe Brucker 13*7cef39ddSJean-Philippe Brucker #define ARM_LPAE_TCR_SH_NS 0 14*7cef39ddSJean-Philippe Brucker #define ARM_LPAE_TCR_SH_OS 2 15*7cef39ddSJean-Philippe Brucker #define ARM_LPAE_TCR_SH_IS 3 16*7cef39ddSJean-Philippe Brucker 17*7cef39ddSJean-Philippe Brucker #define ARM_LPAE_TCR_RGN_NC 0 18*7cef39ddSJean-Philippe Brucker #define ARM_LPAE_TCR_RGN_WBWA 1 19*7cef39ddSJean-Philippe Brucker #define ARM_LPAE_TCR_RGN_WT 2 20*7cef39ddSJean-Philippe Brucker #define ARM_LPAE_TCR_RGN_WB 3 21*7cef39ddSJean-Philippe Brucker 22*7cef39ddSJean-Philippe Brucker #define ARM_LPAE_TCR_PS_32_BIT 0x0ULL 23*7cef39ddSJean-Philippe Brucker #define ARM_LPAE_TCR_PS_36_BIT 0x1ULL 24*7cef39ddSJean-Philippe Brucker #define ARM_LPAE_TCR_PS_40_BIT 0x2ULL 25*7cef39ddSJean-Philippe Brucker #define ARM_LPAE_TCR_PS_42_BIT 0x3ULL 26*7cef39ddSJean-Philippe Brucker #define ARM_LPAE_TCR_PS_44_BIT 0x4ULL 27*7cef39ddSJean-Philippe Brucker #define ARM_LPAE_TCR_PS_48_BIT 0x5ULL 28*7cef39ddSJean-Philippe Brucker #define ARM_LPAE_TCR_PS_52_BIT 0x6ULL 29*7cef39ddSJean-Philippe Brucker 30*7cef39ddSJean-Philippe Brucker #endif /* IO_PGTABLE_ARM_H_ */ 31