1*55ee5e67SLu Baolu /* SPDX-License-Identifier: GPL-2.0 */
2*55ee5e67SLu Baolu /*
3*55ee5e67SLu Baolu * perf.h - performance monitor header
4*55ee5e67SLu Baolu *
5*55ee5e67SLu Baolu * Copyright (C) 2021 Intel Corporation
6*55ee5e67SLu Baolu *
7*55ee5e67SLu Baolu * Author: Lu Baolu <baolu.lu@linux.intel.com>
8*55ee5e67SLu Baolu */
9*55ee5e67SLu Baolu
10*55ee5e67SLu Baolu enum latency_type {
11*55ee5e67SLu Baolu DMAR_LATENCY_INV_IOTLB = 0,
12*55ee5e67SLu Baolu DMAR_LATENCY_INV_DEVTLB,
13*55ee5e67SLu Baolu DMAR_LATENCY_INV_IEC,
14*55ee5e67SLu Baolu DMAR_LATENCY_PRQ,
15*55ee5e67SLu Baolu DMAR_LATENCY_NUM
16*55ee5e67SLu Baolu };
17*55ee5e67SLu Baolu
18*55ee5e67SLu Baolu enum latency_count {
19*55ee5e67SLu Baolu COUNTS_10e2 = 0, /* < 0.1us */
20*55ee5e67SLu Baolu COUNTS_10e3, /* 0.1us ~ 1us */
21*55ee5e67SLu Baolu COUNTS_10e4, /* 1us ~ 10us */
22*55ee5e67SLu Baolu COUNTS_10e5, /* 10us ~ 100us */
23*55ee5e67SLu Baolu COUNTS_10e6, /* 100us ~ 1ms */
24*55ee5e67SLu Baolu COUNTS_10e7, /* 1ms ~ 10ms */
25*55ee5e67SLu Baolu COUNTS_10e8_plus, /* 10ms and plus*/
26*55ee5e67SLu Baolu COUNTS_MIN,
27*55ee5e67SLu Baolu COUNTS_MAX,
28*55ee5e67SLu Baolu COUNTS_SUM,
29*55ee5e67SLu Baolu COUNTS_NUM
30*55ee5e67SLu Baolu };
31*55ee5e67SLu Baolu
32*55ee5e67SLu Baolu struct latency_statistic {
33*55ee5e67SLu Baolu bool enabled;
34*55ee5e67SLu Baolu u64 counter[COUNTS_NUM];
35*55ee5e67SLu Baolu u64 samples;
36*55ee5e67SLu Baolu };
37*55ee5e67SLu Baolu
38*55ee5e67SLu Baolu #ifdef CONFIG_DMAR_PERF
39*55ee5e67SLu Baolu int dmar_latency_enable(struct intel_iommu *iommu, enum latency_type type);
40*55ee5e67SLu Baolu void dmar_latency_disable(struct intel_iommu *iommu, enum latency_type type);
41*55ee5e67SLu Baolu bool dmar_latency_enabled(struct intel_iommu *iommu, enum latency_type type);
42*55ee5e67SLu Baolu void dmar_latency_update(struct intel_iommu *iommu, enum latency_type type,
43*55ee5e67SLu Baolu u64 latency);
44*55ee5e67SLu Baolu int dmar_latency_snapshot(struct intel_iommu *iommu, char *str, size_t size);
45*55ee5e67SLu Baolu #else
46*55ee5e67SLu Baolu static inline int
dmar_latency_enable(struct intel_iommu * iommu,enum latency_type type)47*55ee5e67SLu Baolu dmar_latency_enable(struct intel_iommu *iommu, enum latency_type type)
48*55ee5e67SLu Baolu {
49*55ee5e67SLu Baolu return -EINVAL;
50*55ee5e67SLu Baolu }
51*55ee5e67SLu Baolu
52*55ee5e67SLu Baolu static inline void
dmar_latency_disable(struct intel_iommu * iommu,enum latency_type type)53*55ee5e67SLu Baolu dmar_latency_disable(struct intel_iommu *iommu, enum latency_type type)
54*55ee5e67SLu Baolu {
55*55ee5e67SLu Baolu }
56*55ee5e67SLu Baolu
57*55ee5e67SLu Baolu static inline bool
dmar_latency_enabled(struct intel_iommu * iommu,enum latency_type type)58*55ee5e67SLu Baolu dmar_latency_enabled(struct intel_iommu *iommu, enum latency_type type)
59*55ee5e67SLu Baolu {
60*55ee5e67SLu Baolu return false;
61*55ee5e67SLu Baolu }
62*55ee5e67SLu Baolu
63*55ee5e67SLu Baolu static inline void
dmar_latency_update(struct intel_iommu * iommu,enum latency_type type,u64 latency)64*55ee5e67SLu Baolu dmar_latency_update(struct intel_iommu *iommu, enum latency_type type, u64 latency)
65*55ee5e67SLu Baolu {
66*55ee5e67SLu Baolu }
67*55ee5e67SLu Baolu
68*55ee5e67SLu Baolu static inline int
dmar_latency_snapshot(struct intel_iommu * iommu,char * str,size_t size)69*55ee5e67SLu Baolu dmar_latency_snapshot(struct intel_iommu *iommu, char *str, size_t size)
70*55ee5e67SLu Baolu {
71*55ee5e67SLu Baolu return 0;
72*55ee5e67SLu Baolu }
73*55ee5e67SLu Baolu #endif /* CONFIG_DMAR_PERF */
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