1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2019, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/adreno-smmu-priv.h> 7 #include <linux/of_device.h> 8 #include <linux/qcom_scm.h> 9 10 #include "arm-smmu.h" 11 12 struct qcom_smmu { 13 struct arm_smmu_device smmu; 14 bool bypass_quirk; 15 u8 bypass_cbndx; 16 }; 17 18 static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu) 19 { 20 return container_of(smmu, struct qcom_smmu, smmu); 21 } 22 23 static void qcom_adreno_smmu_write_sctlr(struct arm_smmu_device *smmu, int idx, 24 u32 reg) 25 { 26 /* 27 * On the GPU device we want to process subsequent transactions after a 28 * fault to keep the GPU from hanging 29 */ 30 reg |= ARM_SMMU_SCTLR_HUPCF; 31 32 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg); 33 } 34 35 static void qcom_adreno_smmu_get_fault_info(const void *cookie, 36 struct adreno_smmu_fault_info *info) 37 { 38 struct arm_smmu_domain *smmu_domain = (void *)cookie; 39 struct arm_smmu_cfg *cfg = &smmu_domain->cfg; 40 struct arm_smmu_device *smmu = smmu_domain->smmu; 41 42 info->fsr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSR); 43 info->fsynr0 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR0); 44 info->fsynr1 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR1); 45 info->far = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_FAR); 46 info->cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(cfg->cbndx)); 47 info->ttbr0 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_TTBR0); 48 info->contextidr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_CONTEXTIDR); 49 } 50 51 #define QCOM_ADRENO_SMMU_GPU_SID 0 52 53 static bool qcom_adreno_smmu_is_gpu_device(struct device *dev) 54 { 55 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 56 int i; 57 58 /* 59 * The GPU will always use SID 0 so that is a handy way to uniquely 60 * identify it and configure it for per-instance pagetables 61 */ 62 for (i = 0; i < fwspec->num_ids; i++) { 63 u16 sid = FIELD_GET(ARM_SMMU_SMR_ID, fwspec->ids[i]); 64 65 if (sid == QCOM_ADRENO_SMMU_GPU_SID) 66 return true; 67 } 68 69 return false; 70 } 71 72 static const struct io_pgtable_cfg *qcom_adreno_smmu_get_ttbr1_cfg( 73 const void *cookie) 74 { 75 struct arm_smmu_domain *smmu_domain = (void *)cookie; 76 struct io_pgtable *pgtable = 77 io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops); 78 return &pgtable->cfg; 79 } 80 81 /* 82 * Local implementation to configure TTBR0 with the specified pagetable config. 83 * The GPU driver will call this to enable TTBR0 when per-instance pagetables 84 * are active 85 */ 86 87 static int qcom_adreno_smmu_set_ttbr0_cfg(const void *cookie, 88 const struct io_pgtable_cfg *pgtbl_cfg) 89 { 90 struct arm_smmu_domain *smmu_domain = (void *)cookie; 91 struct io_pgtable *pgtable = io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops); 92 struct arm_smmu_cfg *cfg = &smmu_domain->cfg; 93 struct arm_smmu_cb *cb = &smmu_domain->smmu->cbs[cfg->cbndx]; 94 95 /* The domain must have split pagetables already enabled */ 96 if (cb->tcr[0] & ARM_SMMU_TCR_EPD1) 97 return -EINVAL; 98 99 /* If the pagetable config is NULL, disable TTBR0 */ 100 if (!pgtbl_cfg) { 101 /* Do nothing if it is already disabled */ 102 if ((cb->tcr[0] & ARM_SMMU_TCR_EPD0)) 103 return -EINVAL; 104 105 /* Set TCR to the original configuration */ 106 cb->tcr[0] = arm_smmu_lpae_tcr(&pgtable->cfg); 107 cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid); 108 } else { 109 u32 tcr = cb->tcr[0]; 110 111 /* Don't call this again if TTBR0 is already enabled */ 112 if (!(cb->tcr[0] & ARM_SMMU_TCR_EPD0)) 113 return -EINVAL; 114 115 tcr |= arm_smmu_lpae_tcr(pgtbl_cfg); 116 tcr &= ~(ARM_SMMU_TCR_EPD0 | ARM_SMMU_TCR_EPD1); 117 118 cb->tcr[0] = tcr; 119 cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr; 120 cb->ttbr[0] |= FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid); 121 } 122 123 arm_smmu_write_context_bank(smmu_domain->smmu, cb->cfg->cbndx); 124 125 return 0; 126 } 127 128 static int qcom_adreno_smmu_alloc_context_bank(struct arm_smmu_domain *smmu_domain, 129 struct arm_smmu_device *smmu, 130 struct device *dev, int start) 131 { 132 int count; 133 134 /* 135 * Assign context bank 0 to the GPU device so the GPU hardware can 136 * switch pagetables 137 */ 138 if (qcom_adreno_smmu_is_gpu_device(dev)) { 139 start = 0; 140 count = 1; 141 } else { 142 start = 1; 143 count = smmu->num_context_banks; 144 } 145 146 return __arm_smmu_alloc_bitmap(smmu->context_map, start, count); 147 } 148 149 static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, 150 struct io_pgtable_cfg *pgtbl_cfg, struct device *dev) 151 { 152 struct adreno_smmu_priv *priv; 153 154 /* Only enable split pagetables for the GPU device (SID 0) */ 155 if (!qcom_adreno_smmu_is_gpu_device(dev)) 156 return 0; 157 158 /* 159 * All targets that use the qcom,adreno-smmu compatible string *should* 160 * be AARCH64 stage 1 but double check because the arm-smmu code assumes 161 * that is the case when the TTBR1 quirk is enabled 162 */ 163 if ((smmu_domain->stage == ARM_SMMU_DOMAIN_S1) && 164 (smmu_domain->cfg.fmt == ARM_SMMU_CTX_FMT_AARCH64)) 165 pgtbl_cfg->quirks |= IO_PGTABLE_QUIRK_ARM_TTBR1; 166 167 /* 168 * Initialize private interface with GPU: 169 */ 170 171 priv = dev_get_drvdata(dev); 172 priv->cookie = smmu_domain; 173 priv->get_ttbr1_cfg = qcom_adreno_smmu_get_ttbr1_cfg; 174 priv->set_ttbr0_cfg = qcom_adreno_smmu_set_ttbr0_cfg; 175 priv->get_fault_info = qcom_adreno_smmu_get_fault_info; 176 177 return 0; 178 } 179 180 static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = { 181 { .compatible = "qcom,adreno" }, 182 { .compatible = "qcom,mdp4" }, 183 { .compatible = "qcom,mdss" }, 184 { .compatible = "qcom,sc7180-mdss" }, 185 { .compatible = "qcom,sc7180-mss-pil" }, 186 { .compatible = "qcom,sc8180x-mdss" }, 187 { .compatible = "qcom,sdm845-mdss" }, 188 { .compatible = "qcom,sdm845-mss-pil" }, 189 { } 190 }; 191 192 static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu) 193 { 194 unsigned int last_s2cr = ARM_SMMU_GR0_S2CR(smmu->num_mapping_groups - 1); 195 struct qcom_smmu *qsmmu = to_qcom_smmu(smmu); 196 u32 reg; 197 u32 smr; 198 int i; 199 200 /* 201 * With some firmware versions writes to S2CR of type FAULT are 202 * ignored, and writing BYPASS will end up written as FAULT in the 203 * register. Perform a write to S2CR to detect if this is the case and 204 * if so reserve a context bank to emulate bypass streams. 205 */ 206 reg = FIELD_PREP(ARM_SMMU_S2CR_TYPE, S2CR_TYPE_BYPASS) | 207 FIELD_PREP(ARM_SMMU_S2CR_CBNDX, 0xff) | 208 FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, S2CR_PRIVCFG_DEFAULT); 209 arm_smmu_gr0_write(smmu, last_s2cr, reg); 210 reg = arm_smmu_gr0_read(smmu, last_s2cr); 211 if (FIELD_GET(ARM_SMMU_S2CR_TYPE, reg) != S2CR_TYPE_BYPASS) { 212 qsmmu->bypass_quirk = true; 213 qsmmu->bypass_cbndx = smmu->num_context_banks - 1; 214 215 set_bit(qsmmu->bypass_cbndx, smmu->context_map); 216 217 arm_smmu_cb_write(smmu, qsmmu->bypass_cbndx, ARM_SMMU_CB_SCTLR, 0); 218 219 reg = FIELD_PREP(ARM_SMMU_CBAR_TYPE, CBAR_TYPE_S1_TRANS_S2_BYPASS); 220 arm_smmu_gr1_write(smmu, ARM_SMMU_GR1_CBAR(qsmmu->bypass_cbndx), reg); 221 } 222 223 for (i = 0; i < smmu->num_mapping_groups; i++) { 224 smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(i)); 225 226 if (FIELD_GET(ARM_SMMU_SMR_VALID, smr)) { 227 /* Ignore valid bit for SMR mask extraction. */ 228 smr &= ~ARM_SMMU_SMR_VALID; 229 smmu->smrs[i].id = FIELD_GET(ARM_SMMU_SMR_ID, smr); 230 smmu->smrs[i].mask = FIELD_GET(ARM_SMMU_SMR_MASK, smr); 231 smmu->smrs[i].valid = true; 232 233 smmu->s2crs[i].type = S2CR_TYPE_BYPASS; 234 smmu->s2crs[i].privcfg = S2CR_PRIVCFG_DEFAULT; 235 smmu->s2crs[i].cbndx = 0xff; 236 } 237 } 238 239 return 0; 240 } 241 242 static void qcom_smmu_write_s2cr(struct arm_smmu_device *smmu, int idx) 243 { 244 struct arm_smmu_s2cr *s2cr = smmu->s2crs + idx; 245 struct qcom_smmu *qsmmu = to_qcom_smmu(smmu); 246 u32 cbndx = s2cr->cbndx; 247 u32 type = s2cr->type; 248 u32 reg; 249 250 if (qsmmu->bypass_quirk) { 251 if (type == S2CR_TYPE_BYPASS) { 252 /* 253 * Firmware with quirky S2CR handling will substitute 254 * BYPASS writes with FAULT, so point the stream to the 255 * reserved context bank and ask for translation on the 256 * stream 257 */ 258 type = S2CR_TYPE_TRANS; 259 cbndx = qsmmu->bypass_cbndx; 260 } else if (type == S2CR_TYPE_FAULT) { 261 /* 262 * Firmware with quirky S2CR handling will ignore FAULT 263 * writes, so trick it to write FAULT by asking for a 264 * BYPASS. 265 */ 266 type = S2CR_TYPE_BYPASS; 267 cbndx = 0xff; 268 } 269 } 270 271 reg = FIELD_PREP(ARM_SMMU_S2CR_TYPE, type) | 272 FIELD_PREP(ARM_SMMU_S2CR_CBNDX, cbndx) | 273 FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, s2cr->privcfg); 274 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_S2CR(idx), reg); 275 } 276 277 static int qcom_smmu_def_domain_type(struct device *dev) 278 { 279 const struct of_device_id *match = 280 of_match_device(qcom_smmu_client_of_match, dev); 281 282 return match ? IOMMU_DOMAIN_IDENTITY : 0; 283 } 284 285 static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu) 286 { 287 int ret; 288 289 /* 290 * To address performance degradation in non-real time clients, 291 * such as USB and UFS, turn off wait-for-safe on sdm845 based boards, 292 * such as MTP and db845, whose firmwares implement secure monitor 293 * call handlers to turn on/off the wait-for-safe logic. 294 */ 295 ret = qcom_scm_qsmmu500_wait_safe_toggle(0); 296 if (ret) 297 dev_warn(smmu->dev, "Failed to turn off SAFE logic\n"); 298 299 return ret; 300 } 301 302 static int qcom_smmu500_reset(struct arm_smmu_device *smmu) 303 { 304 const struct device_node *np = smmu->dev->of_node; 305 306 arm_mmu500_reset(smmu); 307 308 if (of_device_is_compatible(np, "qcom,sdm845-smmu-500")) 309 return qcom_sdm845_smmu500_reset(smmu); 310 311 return 0; 312 } 313 314 static const struct arm_smmu_impl qcom_smmu_impl = { 315 .cfg_probe = qcom_smmu_cfg_probe, 316 .def_domain_type = qcom_smmu_def_domain_type, 317 .reset = qcom_smmu500_reset, 318 .write_s2cr = qcom_smmu_write_s2cr, 319 }; 320 321 static const struct arm_smmu_impl qcom_adreno_smmu_impl = { 322 .init_context = qcom_adreno_smmu_init_context, 323 .def_domain_type = qcom_smmu_def_domain_type, 324 .reset = qcom_smmu500_reset, 325 .alloc_context_bank = qcom_adreno_smmu_alloc_context_bank, 326 .write_sctlr = qcom_adreno_smmu_write_sctlr, 327 }; 328 329 static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu, 330 const struct arm_smmu_impl *impl) 331 { 332 struct qcom_smmu *qsmmu; 333 334 /* Check to make sure qcom_scm has finished probing */ 335 if (!qcom_scm_is_available()) 336 return ERR_PTR(-EPROBE_DEFER); 337 338 qsmmu = devm_krealloc(smmu->dev, smmu, sizeof(*qsmmu), GFP_KERNEL); 339 if (!qsmmu) 340 return ERR_PTR(-ENOMEM); 341 342 qsmmu->smmu.impl = impl; 343 344 return &qsmmu->smmu; 345 } 346 347 static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = { 348 { .compatible = "qcom,msm8998-smmu-v2" }, 349 { .compatible = "qcom,sc7180-smmu-500" }, 350 { .compatible = "qcom,sc8180x-smmu-500" }, 351 { .compatible = "qcom,sdm630-smmu-v2" }, 352 { .compatible = "qcom,sdm845-smmu-500" }, 353 { .compatible = "qcom,sm8150-smmu-500" }, 354 { .compatible = "qcom,sm8250-smmu-500" }, 355 { .compatible = "qcom,sm8350-smmu-500" }, 356 { } 357 }; 358 359 struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu) 360 { 361 const struct device_node *np = smmu->dev->of_node; 362 363 if (of_match_node(qcom_smmu_impl_of_match, np)) 364 return qcom_smmu_create(smmu, &qcom_smmu_impl); 365 366 if (of_device_is_compatible(np, "qcom,adreno-smmu")) 367 return qcom_smmu_create(smmu, &qcom_adreno_smmu_impl); 368 369 return smmu; 370 } 371