1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2019, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/acpi.h> 7 #include <linux/adreno-smmu-priv.h> 8 #include <linux/of_device.h> 9 #include <linux/qcom_scm.h> 10 11 #include "arm-smmu.h" 12 13 struct qcom_smmu { 14 struct arm_smmu_device smmu; 15 bool bypass_quirk; 16 u8 bypass_cbndx; 17 }; 18 19 static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu) 20 { 21 return container_of(smmu, struct qcom_smmu, smmu); 22 } 23 24 static void qcom_adreno_smmu_write_sctlr(struct arm_smmu_device *smmu, int idx, 25 u32 reg) 26 { 27 /* 28 * On the GPU device we want to process subsequent transactions after a 29 * fault to keep the GPU from hanging 30 */ 31 reg |= ARM_SMMU_SCTLR_HUPCF; 32 33 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg); 34 } 35 36 #define QCOM_ADRENO_SMMU_GPU_SID 0 37 38 static bool qcom_adreno_smmu_is_gpu_device(struct device *dev) 39 { 40 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 41 int i; 42 43 /* 44 * The GPU will always use SID 0 so that is a handy way to uniquely 45 * identify it and configure it for per-instance pagetables 46 */ 47 for (i = 0; i < fwspec->num_ids; i++) { 48 u16 sid = FIELD_GET(ARM_SMMU_SMR_ID, fwspec->ids[i]); 49 50 if (sid == QCOM_ADRENO_SMMU_GPU_SID) 51 return true; 52 } 53 54 return false; 55 } 56 57 static const struct io_pgtable_cfg *qcom_adreno_smmu_get_ttbr1_cfg( 58 const void *cookie) 59 { 60 struct arm_smmu_domain *smmu_domain = (void *)cookie; 61 struct io_pgtable *pgtable = 62 io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops); 63 return &pgtable->cfg; 64 } 65 66 /* 67 * Local implementation to configure TTBR0 with the specified pagetable config. 68 * The GPU driver will call this to enable TTBR0 when per-instance pagetables 69 * are active 70 */ 71 72 static int qcom_adreno_smmu_set_ttbr0_cfg(const void *cookie, 73 const struct io_pgtable_cfg *pgtbl_cfg) 74 { 75 struct arm_smmu_domain *smmu_domain = (void *)cookie; 76 struct io_pgtable *pgtable = io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops); 77 struct arm_smmu_cfg *cfg = &smmu_domain->cfg; 78 struct arm_smmu_cb *cb = &smmu_domain->smmu->cbs[cfg->cbndx]; 79 80 /* The domain must have split pagetables already enabled */ 81 if (cb->tcr[0] & ARM_SMMU_TCR_EPD1) 82 return -EINVAL; 83 84 /* If the pagetable config is NULL, disable TTBR0 */ 85 if (!pgtbl_cfg) { 86 /* Do nothing if it is already disabled */ 87 if ((cb->tcr[0] & ARM_SMMU_TCR_EPD0)) 88 return -EINVAL; 89 90 /* Set TCR to the original configuration */ 91 cb->tcr[0] = arm_smmu_lpae_tcr(&pgtable->cfg); 92 cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid); 93 } else { 94 u32 tcr = cb->tcr[0]; 95 96 /* Don't call this again if TTBR0 is already enabled */ 97 if (!(cb->tcr[0] & ARM_SMMU_TCR_EPD0)) 98 return -EINVAL; 99 100 tcr |= arm_smmu_lpae_tcr(pgtbl_cfg); 101 tcr &= ~(ARM_SMMU_TCR_EPD0 | ARM_SMMU_TCR_EPD1); 102 103 cb->tcr[0] = tcr; 104 cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr; 105 cb->ttbr[0] |= FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid); 106 } 107 108 arm_smmu_write_context_bank(smmu_domain->smmu, cb->cfg->cbndx); 109 110 return 0; 111 } 112 113 static int qcom_adreno_smmu_alloc_context_bank(struct arm_smmu_domain *smmu_domain, 114 struct arm_smmu_device *smmu, 115 struct device *dev, int start) 116 { 117 int count; 118 119 /* 120 * Assign context bank 0 to the GPU device so the GPU hardware can 121 * switch pagetables 122 */ 123 if (qcom_adreno_smmu_is_gpu_device(dev)) { 124 start = 0; 125 count = 1; 126 } else { 127 start = 1; 128 count = smmu->num_context_banks; 129 } 130 131 return __arm_smmu_alloc_bitmap(smmu->context_map, start, count); 132 } 133 134 static bool qcom_adreno_can_do_ttbr1(struct arm_smmu_device *smmu) 135 { 136 const struct device_node *np = smmu->dev->of_node; 137 138 if (of_device_is_compatible(np, "qcom,msm8996-smmu-v2")) 139 return false; 140 141 return true; 142 } 143 144 static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, 145 struct io_pgtable_cfg *pgtbl_cfg, struct device *dev) 146 { 147 struct adreno_smmu_priv *priv; 148 149 /* Only enable split pagetables for the GPU device (SID 0) */ 150 if (!qcom_adreno_smmu_is_gpu_device(dev)) 151 return 0; 152 153 /* 154 * All targets that use the qcom,adreno-smmu compatible string *should* 155 * be AARCH64 stage 1 but double check because the arm-smmu code assumes 156 * that is the case when the TTBR1 quirk is enabled 157 */ 158 if (qcom_adreno_can_do_ttbr1(smmu_domain->smmu) && 159 (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) && 160 (smmu_domain->cfg.fmt == ARM_SMMU_CTX_FMT_AARCH64)) 161 pgtbl_cfg->quirks |= IO_PGTABLE_QUIRK_ARM_TTBR1; 162 163 /* 164 * Initialize private interface with GPU: 165 */ 166 167 priv = dev_get_drvdata(dev); 168 priv->cookie = smmu_domain; 169 priv->get_ttbr1_cfg = qcom_adreno_smmu_get_ttbr1_cfg; 170 priv->set_ttbr0_cfg = qcom_adreno_smmu_set_ttbr0_cfg; 171 172 return 0; 173 } 174 175 static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = { 176 { .compatible = "qcom,adreno" }, 177 { .compatible = "qcom,mdp4" }, 178 { .compatible = "qcom,mdss" }, 179 { .compatible = "qcom,sc7180-mdss" }, 180 { .compatible = "qcom,sc7180-mss-pil" }, 181 { .compatible = "qcom,sc7280-mdss" }, 182 { .compatible = "qcom,sc8180x-mdss" }, 183 { .compatible = "qcom,sdm845-mdss" }, 184 { .compatible = "qcom,sdm845-mss-pil" }, 185 { } 186 }; 187 188 static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu) 189 { 190 unsigned int last_s2cr = ARM_SMMU_GR0_S2CR(smmu->num_mapping_groups - 1); 191 struct qcom_smmu *qsmmu = to_qcom_smmu(smmu); 192 u32 reg; 193 u32 smr; 194 int i; 195 196 /* 197 * With some firmware versions writes to S2CR of type FAULT are 198 * ignored, and writing BYPASS will end up written as FAULT in the 199 * register. Perform a write to S2CR to detect if this is the case and 200 * if so reserve a context bank to emulate bypass streams. 201 */ 202 reg = FIELD_PREP(ARM_SMMU_S2CR_TYPE, S2CR_TYPE_BYPASS) | 203 FIELD_PREP(ARM_SMMU_S2CR_CBNDX, 0xff) | 204 FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, S2CR_PRIVCFG_DEFAULT); 205 arm_smmu_gr0_write(smmu, last_s2cr, reg); 206 reg = arm_smmu_gr0_read(smmu, last_s2cr); 207 if (FIELD_GET(ARM_SMMU_S2CR_TYPE, reg) != S2CR_TYPE_BYPASS) { 208 qsmmu->bypass_quirk = true; 209 qsmmu->bypass_cbndx = smmu->num_context_banks - 1; 210 211 set_bit(qsmmu->bypass_cbndx, smmu->context_map); 212 213 arm_smmu_cb_write(smmu, qsmmu->bypass_cbndx, ARM_SMMU_CB_SCTLR, 0); 214 215 reg = FIELD_PREP(ARM_SMMU_CBAR_TYPE, CBAR_TYPE_S1_TRANS_S2_BYPASS); 216 arm_smmu_gr1_write(smmu, ARM_SMMU_GR1_CBAR(qsmmu->bypass_cbndx), reg); 217 } 218 219 for (i = 0; i < smmu->num_mapping_groups; i++) { 220 smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(i)); 221 222 if (FIELD_GET(ARM_SMMU_SMR_VALID, smr)) { 223 /* Ignore valid bit for SMR mask extraction. */ 224 smr &= ~ARM_SMMU_SMR_VALID; 225 smmu->smrs[i].id = FIELD_GET(ARM_SMMU_SMR_ID, smr); 226 smmu->smrs[i].mask = FIELD_GET(ARM_SMMU_SMR_MASK, smr); 227 smmu->smrs[i].valid = true; 228 229 smmu->s2crs[i].type = S2CR_TYPE_BYPASS; 230 smmu->s2crs[i].privcfg = S2CR_PRIVCFG_DEFAULT; 231 smmu->s2crs[i].cbndx = 0xff; 232 } 233 } 234 235 return 0; 236 } 237 238 static void qcom_smmu_write_s2cr(struct arm_smmu_device *smmu, int idx) 239 { 240 struct arm_smmu_s2cr *s2cr = smmu->s2crs + idx; 241 struct qcom_smmu *qsmmu = to_qcom_smmu(smmu); 242 u32 cbndx = s2cr->cbndx; 243 u32 type = s2cr->type; 244 u32 reg; 245 246 if (qsmmu->bypass_quirk) { 247 if (type == S2CR_TYPE_BYPASS) { 248 /* 249 * Firmware with quirky S2CR handling will substitute 250 * BYPASS writes with FAULT, so point the stream to the 251 * reserved context bank and ask for translation on the 252 * stream 253 */ 254 type = S2CR_TYPE_TRANS; 255 cbndx = qsmmu->bypass_cbndx; 256 } else if (type == S2CR_TYPE_FAULT) { 257 /* 258 * Firmware with quirky S2CR handling will ignore FAULT 259 * writes, so trick it to write FAULT by asking for a 260 * BYPASS. 261 */ 262 type = S2CR_TYPE_BYPASS; 263 cbndx = 0xff; 264 } 265 } 266 267 reg = FIELD_PREP(ARM_SMMU_S2CR_TYPE, type) | 268 FIELD_PREP(ARM_SMMU_S2CR_CBNDX, cbndx) | 269 FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, s2cr->privcfg); 270 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_S2CR(idx), reg); 271 } 272 273 static int qcom_smmu_def_domain_type(struct device *dev) 274 { 275 const struct of_device_id *match = 276 of_match_device(qcom_smmu_client_of_match, dev); 277 278 return match ? IOMMU_DOMAIN_IDENTITY : 0; 279 } 280 281 static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu) 282 { 283 int ret; 284 285 /* 286 * To address performance degradation in non-real time clients, 287 * such as USB and UFS, turn off wait-for-safe on sdm845 based boards, 288 * such as MTP and db845, whose firmwares implement secure monitor 289 * call handlers to turn on/off the wait-for-safe logic. 290 */ 291 ret = qcom_scm_qsmmu500_wait_safe_toggle(0); 292 if (ret) 293 dev_warn(smmu->dev, "Failed to turn off SAFE logic\n"); 294 295 return ret; 296 } 297 298 static int qcom_smmu500_reset(struct arm_smmu_device *smmu) 299 { 300 const struct device_node *np = smmu->dev->of_node; 301 302 arm_mmu500_reset(smmu); 303 304 if (of_device_is_compatible(np, "qcom,sdm845-smmu-500")) 305 return qcom_sdm845_smmu500_reset(smmu); 306 307 return 0; 308 } 309 310 static const struct arm_smmu_impl qcom_smmu_impl = { 311 .cfg_probe = qcom_smmu_cfg_probe, 312 .def_domain_type = qcom_smmu_def_domain_type, 313 .reset = qcom_smmu500_reset, 314 .write_s2cr = qcom_smmu_write_s2cr, 315 }; 316 317 static const struct arm_smmu_impl qcom_adreno_smmu_impl = { 318 .init_context = qcom_adreno_smmu_init_context, 319 .def_domain_type = qcom_smmu_def_domain_type, 320 .reset = qcom_smmu500_reset, 321 .alloc_context_bank = qcom_adreno_smmu_alloc_context_bank, 322 .write_sctlr = qcom_adreno_smmu_write_sctlr, 323 }; 324 325 static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu, 326 const struct arm_smmu_impl *impl) 327 { 328 struct qcom_smmu *qsmmu; 329 330 /* Check to make sure qcom_scm has finished probing */ 331 if (!qcom_scm_is_available()) 332 return ERR_PTR(-EPROBE_DEFER); 333 334 qsmmu = devm_krealloc(smmu->dev, smmu, sizeof(*qsmmu), GFP_KERNEL); 335 if (!qsmmu) 336 return ERR_PTR(-ENOMEM); 337 338 qsmmu->smmu.impl = impl; 339 340 return &qsmmu->smmu; 341 } 342 343 static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = { 344 { .compatible = "qcom,msm8998-smmu-v2" }, 345 { .compatible = "qcom,sc7180-smmu-500" }, 346 { .compatible = "qcom,sc7280-smmu-500" }, 347 { .compatible = "qcom,sc8180x-smmu-500" }, 348 { .compatible = "qcom,sdm630-smmu-v2" }, 349 { .compatible = "qcom,sdm845-smmu-500" }, 350 { .compatible = "qcom,sm6125-smmu-500" }, 351 { .compatible = "qcom,sm8150-smmu-500" }, 352 { .compatible = "qcom,sm8250-smmu-500" }, 353 { .compatible = "qcom,sm8350-smmu-500" }, 354 { } 355 }; 356 357 #ifdef CONFIG_ACPI 358 static struct acpi_platform_list qcom_acpi_platlist[] = { 359 { "LENOVO", "CB-01 ", 0x8180, ACPI_SIG_IORT, equal, "QCOM SMMU" }, 360 { "QCOM ", "QCOMEDK2", 0x8180, ACPI_SIG_IORT, equal, "QCOM SMMU" }, 361 { } 362 }; 363 #endif 364 365 struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu) 366 { 367 const struct device_node *np = smmu->dev->of_node; 368 369 #ifdef CONFIG_ACPI 370 if (np == NULL) { 371 /* Match platform for ACPI boot */ 372 if (acpi_match_platform_list(qcom_acpi_platlist) >= 0) 373 return qcom_smmu_create(smmu, &qcom_smmu_impl); 374 } 375 #endif 376 377 /* 378 * Do not change this order of implementation, i.e., first adreno 379 * smmu impl and then apss smmu since we can have both implementing 380 * arm,mmu-500 in which case we will miss setting adreno smmu specific 381 * features if the order is changed. 382 */ 383 if (of_device_is_compatible(np, "qcom,adreno-smmu")) 384 return qcom_smmu_create(smmu, &qcom_adreno_smmu_impl); 385 386 if (of_match_node(qcom_smmu_impl_of_match, np)) 387 return qcom_smmu_create(smmu, &qcom_smmu_impl); 388 389 return smmu; 390 } 391