1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. 4 * Author: Joerg Roedel <jroedel@suse.de> 5 * Leo Duran <leo.duran@amd.com> 6 */ 7 8 #define pr_fmt(fmt) "AMD-Vi: " fmt 9 #define dev_fmt(fmt) pr_fmt(fmt) 10 11 #include <linux/pci.h> 12 #include <linux/acpi.h> 13 #include <linux/list.h> 14 #include <linux/bitmap.h> 15 #include <linux/slab.h> 16 #include <linux/syscore_ops.h> 17 #include <linux/interrupt.h> 18 #include <linux/msi.h> 19 #include <linux/irq.h> 20 #include <linux/amd-iommu.h> 21 #include <linux/export.h> 22 #include <linux/kmemleak.h> 23 #include <linux/cc_platform.h> 24 #include <linux/iopoll.h> 25 #include <asm/pci-direct.h> 26 #include <asm/iommu.h> 27 #include <asm/apic.h> 28 #include <asm/gart.h> 29 #include <asm/x86_init.h> 30 #include <asm/io_apic.h> 31 #include <asm/irq_remapping.h> 32 #include <asm/set_memory.h> 33 34 #include <linux/crash_dump.h> 35 36 #include "amd_iommu.h" 37 #include "../irq_remapping.h" 38 39 /* 40 * definitions for the ACPI scanning code 41 */ 42 #define IVRS_HEADER_LENGTH 48 43 44 #define ACPI_IVHD_TYPE_MAX_SUPPORTED 0x40 45 #define ACPI_IVMD_TYPE_ALL 0x20 46 #define ACPI_IVMD_TYPE 0x21 47 #define ACPI_IVMD_TYPE_RANGE 0x22 48 49 #define IVHD_DEV_ALL 0x01 50 #define IVHD_DEV_SELECT 0x02 51 #define IVHD_DEV_SELECT_RANGE_START 0x03 52 #define IVHD_DEV_RANGE_END 0x04 53 #define IVHD_DEV_ALIAS 0x42 54 #define IVHD_DEV_ALIAS_RANGE 0x43 55 #define IVHD_DEV_EXT_SELECT 0x46 56 #define IVHD_DEV_EXT_SELECT_RANGE 0x47 57 #define IVHD_DEV_SPECIAL 0x48 58 #define IVHD_DEV_ACPI_HID 0xf0 59 60 #define UID_NOT_PRESENT 0 61 #define UID_IS_INTEGER 1 62 #define UID_IS_CHARACTER 2 63 64 #define IVHD_SPECIAL_IOAPIC 1 65 #define IVHD_SPECIAL_HPET 2 66 67 #define IVHD_FLAG_HT_TUN_EN_MASK 0x01 68 #define IVHD_FLAG_PASSPW_EN_MASK 0x02 69 #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04 70 #define IVHD_FLAG_ISOC_EN_MASK 0x08 71 72 #define IVMD_FLAG_EXCL_RANGE 0x08 73 #define IVMD_FLAG_IW 0x04 74 #define IVMD_FLAG_IR 0x02 75 #define IVMD_FLAG_UNITY_MAP 0x01 76 77 #define ACPI_DEVFLAG_INITPASS 0x01 78 #define ACPI_DEVFLAG_EXTINT 0x02 79 #define ACPI_DEVFLAG_NMI 0x04 80 #define ACPI_DEVFLAG_SYSMGT1 0x10 81 #define ACPI_DEVFLAG_SYSMGT2 0x20 82 #define ACPI_DEVFLAG_LINT0 0x40 83 #define ACPI_DEVFLAG_LINT1 0x80 84 #define ACPI_DEVFLAG_ATSDIS 0x10000000 85 86 #define LOOP_TIMEOUT 2000000 87 /* 88 * ACPI table definitions 89 * 90 * These data structures are laid over the table to parse the important values 91 * out of it. 92 */ 93 94 extern const struct iommu_ops amd_iommu_ops; 95 96 /* 97 * structure describing one IOMMU in the ACPI table. Typically followed by one 98 * or more ivhd_entrys. 99 */ 100 struct ivhd_header { 101 u8 type; 102 u8 flags; 103 u16 length; 104 u16 devid; 105 u16 cap_ptr; 106 u64 mmio_phys; 107 u16 pci_seg; 108 u16 info; 109 u32 efr_attr; 110 111 /* Following only valid on IVHD type 11h and 40h */ 112 u64 efr_reg; /* Exact copy of MMIO_EXT_FEATURES */ 113 u64 res; 114 } __attribute__((packed)); 115 116 /* 117 * A device entry describing which devices a specific IOMMU translates and 118 * which requestor ids they use. 119 */ 120 struct ivhd_entry { 121 u8 type; 122 u16 devid; 123 u8 flags; 124 struct_group(ext_hid, 125 u32 ext; 126 u32 hidh; 127 ); 128 u64 cid; 129 u8 uidf; 130 u8 uidl; 131 u8 uid; 132 } __attribute__((packed)); 133 134 /* 135 * An AMD IOMMU memory definition structure. It defines things like exclusion 136 * ranges for devices and regions that should be unity mapped. 137 */ 138 struct ivmd_header { 139 u8 type; 140 u8 flags; 141 u16 length; 142 u16 devid; 143 u16 aux; 144 u16 pci_seg; 145 u8 resv[6]; 146 u64 range_start; 147 u64 range_length; 148 } __attribute__((packed)); 149 150 bool amd_iommu_dump; 151 bool amd_iommu_irq_remap __read_mostly; 152 153 enum io_pgtable_fmt amd_iommu_pgtable = AMD_IOMMU_V1; 154 155 int amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC; 156 static int amd_iommu_xt_mode = IRQ_REMAP_XAPIC_MODE; 157 158 static bool amd_iommu_detected; 159 static bool amd_iommu_disabled __initdata; 160 static bool amd_iommu_force_enable __initdata; 161 static int amd_iommu_target_ivhd_type; 162 163 u16 amd_iommu_last_bdf; /* largest PCI device id we have 164 to handle */ 165 166 LIST_HEAD(amd_iommu_pci_seg_list); /* list of all PCI segments */ 167 LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the 168 system */ 169 170 /* Array to assign indices to IOMMUs*/ 171 struct amd_iommu *amd_iommus[MAX_IOMMUS]; 172 173 /* Number of IOMMUs present in the system */ 174 static int amd_iommus_present; 175 176 /* IOMMUs have a non-present cache? */ 177 bool amd_iommu_np_cache __read_mostly; 178 bool amd_iommu_iotlb_sup __read_mostly = true; 179 180 u32 amd_iommu_max_pasid __read_mostly = ~0; 181 182 bool amd_iommu_v2_present __read_mostly; 183 static bool amd_iommu_pc_present __read_mostly; 184 bool amdr_ivrs_remap_support __read_mostly; 185 186 bool amd_iommu_force_isolation __read_mostly; 187 188 /* 189 * Pointer to the device table which is shared by all AMD IOMMUs 190 * it is indexed by the PCI device id or the HT unit id and contains 191 * information about the domain the device belongs to as well as the 192 * page table root pointer. 193 */ 194 struct dev_table_entry *amd_iommu_dev_table; 195 196 /* 197 * The alias table is a driver specific data structure which contains the 198 * mappings of the PCI device ids to the actual requestor ids on the IOMMU. 199 * More than one device can share the same requestor id. 200 */ 201 u16 *amd_iommu_alias_table; 202 203 /* 204 * AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap 205 * to know which ones are already in use. 206 */ 207 unsigned long *amd_iommu_pd_alloc_bitmap; 208 209 static u32 dev_table_size; /* size of the device table */ 210 static u32 alias_table_size; /* size of the alias table */ 211 212 enum iommu_init_state { 213 IOMMU_START_STATE, 214 IOMMU_IVRS_DETECTED, 215 IOMMU_ACPI_FINISHED, 216 IOMMU_ENABLED, 217 IOMMU_PCI_INIT, 218 IOMMU_INTERRUPTS_EN, 219 IOMMU_INITIALIZED, 220 IOMMU_NOT_FOUND, 221 IOMMU_INIT_ERROR, 222 IOMMU_CMDLINE_DISABLED, 223 }; 224 225 /* Early ioapic and hpet maps from kernel command line */ 226 #define EARLY_MAP_SIZE 4 227 static struct devid_map __initdata early_ioapic_map[EARLY_MAP_SIZE]; 228 static struct devid_map __initdata early_hpet_map[EARLY_MAP_SIZE]; 229 static struct acpihid_map_entry __initdata early_acpihid_map[EARLY_MAP_SIZE]; 230 231 static int __initdata early_ioapic_map_size; 232 static int __initdata early_hpet_map_size; 233 static int __initdata early_acpihid_map_size; 234 235 static bool __initdata cmdline_maps; 236 237 static enum iommu_init_state init_state = IOMMU_START_STATE; 238 239 static int amd_iommu_enable_interrupts(void); 240 static int __init iommu_go_to_state(enum iommu_init_state state); 241 static void init_device_table_dma(struct amd_iommu_pci_seg *pci_seg); 242 243 static bool amd_iommu_pre_enabled = true; 244 245 static u32 amd_iommu_ivinfo __initdata; 246 247 bool translation_pre_enabled(struct amd_iommu *iommu) 248 { 249 return (iommu->flags & AMD_IOMMU_FLAG_TRANS_PRE_ENABLED); 250 } 251 252 static void clear_translation_pre_enabled(struct amd_iommu *iommu) 253 { 254 iommu->flags &= ~AMD_IOMMU_FLAG_TRANS_PRE_ENABLED; 255 } 256 257 static void init_translation_status(struct amd_iommu *iommu) 258 { 259 u64 ctrl; 260 261 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); 262 if (ctrl & (1<<CONTROL_IOMMU_EN)) 263 iommu->flags |= AMD_IOMMU_FLAG_TRANS_PRE_ENABLED; 264 } 265 266 static inline void update_last_devid(u16 devid) 267 { 268 if (devid > amd_iommu_last_bdf) 269 amd_iommu_last_bdf = devid; 270 } 271 272 static inline unsigned long tbl_size(int entry_size) 273 { 274 unsigned shift = PAGE_SHIFT + 275 get_order(((int)amd_iommu_last_bdf + 1) * entry_size); 276 277 return 1UL << shift; 278 } 279 280 int amd_iommu_get_num_iommus(void) 281 { 282 return amd_iommus_present; 283 } 284 285 #ifdef CONFIG_IRQ_REMAP 286 static bool check_feature_on_all_iommus(u64 mask) 287 { 288 bool ret = false; 289 struct amd_iommu *iommu; 290 291 for_each_iommu(iommu) { 292 ret = iommu_feature(iommu, mask); 293 if (!ret) 294 return false; 295 } 296 297 return true; 298 } 299 #endif 300 301 /* 302 * For IVHD type 0x11/0x40, EFR is also available via IVHD. 303 * Default to IVHD EFR since it is available sooner 304 * (i.e. before PCI init). 305 */ 306 static void __init early_iommu_features_init(struct amd_iommu *iommu, 307 struct ivhd_header *h) 308 { 309 if (amd_iommu_ivinfo & IOMMU_IVINFO_EFRSUP) 310 iommu->features = h->efr_reg; 311 if (amd_iommu_ivinfo & IOMMU_IVINFO_DMA_REMAP) 312 amdr_ivrs_remap_support = true; 313 } 314 315 /* Access to l1 and l2 indexed register spaces */ 316 317 static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address) 318 { 319 u32 val; 320 321 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); 322 pci_read_config_dword(iommu->dev, 0xfc, &val); 323 return val; 324 } 325 326 static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val) 327 { 328 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31)); 329 pci_write_config_dword(iommu->dev, 0xfc, val); 330 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); 331 } 332 333 static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address) 334 { 335 u32 val; 336 337 pci_write_config_dword(iommu->dev, 0xf0, address); 338 pci_read_config_dword(iommu->dev, 0xf4, &val); 339 return val; 340 } 341 342 static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val) 343 { 344 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8)); 345 pci_write_config_dword(iommu->dev, 0xf4, val); 346 } 347 348 /**************************************************************************** 349 * 350 * AMD IOMMU MMIO register space handling functions 351 * 352 * These functions are used to program the IOMMU device registers in 353 * MMIO space required for that driver. 354 * 355 ****************************************************************************/ 356 357 /* 358 * This function set the exclusion range in the IOMMU. DMA accesses to the 359 * exclusion range are passed through untranslated 360 */ 361 static void iommu_set_exclusion_range(struct amd_iommu *iommu) 362 { 363 u64 start = iommu->exclusion_start & PAGE_MASK; 364 u64 limit = (start + iommu->exclusion_length - 1) & PAGE_MASK; 365 u64 entry; 366 367 if (!iommu->exclusion_start) 368 return; 369 370 entry = start | MMIO_EXCL_ENABLE_MASK; 371 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, 372 &entry, sizeof(entry)); 373 374 entry = limit; 375 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, 376 &entry, sizeof(entry)); 377 } 378 379 static void iommu_set_cwwb_range(struct amd_iommu *iommu) 380 { 381 u64 start = iommu_virt_to_phys((void *)iommu->cmd_sem); 382 u64 entry = start & PM_ADDR_MASK; 383 384 if (!iommu_feature(iommu, FEATURE_SNP)) 385 return; 386 387 /* Note: 388 * Re-purpose Exclusion base/limit registers for Completion wait 389 * write-back base/limit. 390 */ 391 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, 392 &entry, sizeof(entry)); 393 394 /* Note: 395 * Default to 4 Kbytes, which can be specified by setting base 396 * address equal to the limit address. 397 */ 398 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, 399 &entry, sizeof(entry)); 400 } 401 402 /* Programs the physical address of the device table into the IOMMU hardware */ 403 static void iommu_set_device_table(struct amd_iommu *iommu) 404 { 405 u64 entry; 406 u32 dev_table_size = iommu->pci_seg->dev_table_size; 407 408 BUG_ON(iommu->mmio_base == NULL); 409 410 entry = iommu_virt_to_phys(amd_iommu_dev_table); 411 entry |= (dev_table_size >> 12) - 1; 412 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET, 413 &entry, sizeof(entry)); 414 } 415 416 /* Generic functions to enable/disable certain features of the IOMMU. */ 417 static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit) 418 { 419 u64 ctrl; 420 421 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); 422 ctrl |= (1ULL << bit); 423 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); 424 } 425 426 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit) 427 { 428 u64 ctrl; 429 430 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); 431 ctrl &= ~(1ULL << bit); 432 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); 433 } 434 435 static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout) 436 { 437 u64 ctrl; 438 439 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); 440 ctrl &= ~CTRL_INV_TO_MASK; 441 ctrl |= (timeout << CONTROL_INV_TIMEOUT) & CTRL_INV_TO_MASK; 442 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); 443 } 444 445 /* Function to enable the hardware */ 446 static void iommu_enable(struct amd_iommu *iommu) 447 { 448 iommu_feature_enable(iommu, CONTROL_IOMMU_EN); 449 } 450 451 static void iommu_disable(struct amd_iommu *iommu) 452 { 453 if (!iommu->mmio_base) 454 return; 455 456 /* Disable command buffer */ 457 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); 458 459 /* Disable event logging and event interrupts */ 460 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN); 461 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); 462 463 /* Disable IOMMU GA_LOG */ 464 iommu_feature_disable(iommu, CONTROL_GALOG_EN); 465 iommu_feature_disable(iommu, CONTROL_GAINT_EN); 466 467 /* Disable IOMMU hardware itself */ 468 iommu_feature_disable(iommu, CONTROL_IOMMU_EN); 469 } 470 471 /* 472 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in 473 * the system has one. 474 */ 475 static u8 __iomem * __init iommu_map_mmio_space(u64 address, u64 end) 476 { 477 if (!request_mem_region(address, end, "amd_iommu")) { 478 pr_err("Can not reserve memory region %llx-%llx for mmio\n", 479 address, end); 480 pr_err("This is a BIOS bug. Please contact your hardware vendor\n"); 481 return NULL; 482 } 483 484 return (u8 __iomem *)ioremap(address, end); 485 } 486 487 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu) 488 { 489 if (iommu->mmio_base) 490 iounmap(iommu->mmio_base); 491 release_mem_region(iommu->mmio_phys, iommu->mmio_phys_end); 492 } 493 494 static inline u32 get_ivhd_header_size(struct ivhd_header *h) 495 { 496 u32 size = 0; 497 498 switch (h->type) { 499 case 0x10: 500 size = 24; 501 break; 502 case 0x11: 503 case 0x40: 504 size = 40; 505 break; 506 } 507 return size; 508 } 509 510 /**************************************************************************** 511 * 512 * The functions below belong to the first pass of AMD IOMMU ACPI table 513 * parsing. In this pass we try to find out the highest device id this 514 * code has to handle. Upon this information the size of the shared data 515 * structures is determined later. 516 * 517 ****************************************************************************/ 518 519 /* 520 * This function calculates the length of a given IVHD entry 521 */ 522 static inline int ivhd_entry_length(u8 *ivhd) 523 { 524 u32 type = ((struct ivhd_entry *)ivhd)->type; 525 526 if (type < 0x80) { 527 return 0x04 << (*ivhd >> 6); 528 } else if (type == IVHD_DEV_ACPI_HID) { 529 /* For ACPI_HID, offset 21 is uid len */ 530 return *((u8 *)ivhd + 21) + 22; 531 } 532 return 0; 533 } 534 535 /* 536 * After reading the highest device id from the IOMMU PCI capability header 537 * this function looks if there is a higher device id defined in the ACPI table 538 */ 539 static int __init find_last_devid_from_ivhd(struct ivhd_header *h) 540 { 541 u8 *p = (void *)h, *end = (void *)h; 542 struct ivhd_entry *dev; 543 int last_devid = -EINVAL; 544 545 u32 ivhd_size = get_ivhd_header_size(h); 546 547 if (!ivhd_size) { 548 pr_err("Unsupported IVHD type %#x\n", h->type); 549 return -EINVAL; 550 } 551 552 p += ivhd_size; 553 end += h->length; 554 555 while (p < end) { 556 dev = (struct ivhd_entry *)p; 557 switch (dev->type) { 558 case IVHD_DEV_ALL: 559 /* Use maximum BDF value for DEV_ALL */ 560 update_last_devid(0xffff); 561 return 0xffff; 562 case IVHD_DEV_SELECT: 563 case IVHD_DEV_RANGE_END: 564 case IVHD_DEV_ALIAS: 565 case IVHD_DEV_EXT_SELECT: 566 /* all the above subfield types refer to device ids */ 567 update_last_devid(dev->devid); 568 if (dev->devid > last_devid) 569 last_devid = dev->devid; 570 break; 571 default: 572 break; 573 } 574 p += ivhd_entry_length(p); 575 } 576 577 WARN_ON(p != end); 578 579 return last_devid; 580 } 581 582 static int __init check_ivrs_checksum(struct acpi_table_header *table) 583 { 584 int i; 585 u8 checksum = 0, *p = (u8 *)table; 586 587 for (i = 0; i < table->length; ++i) 588 checksum += p[i]; 589 if (checksum != 0) { 590 /* ACPI table corrupt */ 591 pr_err(FW_BUG "IVRS invalid checksum\n"); 592 return -ENODEV; 593 } 594 595 return 0; 596 } 597 598 /* 599 * Iterate over all IVHD entries in the ACPI table and find the highest device 600 * id which we need to handle. This is the first of three functions which parse 601 * the ACPI table. So we check the checksum here. 602 */ 603 static int __init find_last_devid_acpi(struct acpi_table_header *table, u16 pci_seg) 604 { 605 u8 *p = (u8 *)table, *end = (u8 *)table; 606 struct ivhd_header *h; 607 int last_devid, last_bdf = 0; 608 609 p += IVRS_HEADER_LENGTH; 610 611 end += table->length; 612 while (p < end) { 613 h = (struct ivhd_header *)p; 614 if (h->pci_seg == pci_seg && 615 h->type == amd_iommu_target_ivhd_type) { 616 last_devid = find_last_devid_from_ivhd(h); 617 618 if (last_devid < 0) 619 return -EINVAL; 620 if (last_devid > last_bdf) 621 last_bdf = last_devid; 622 } 623 p += h->length; 624 } 625 WARN_ON(p != end); 626 627 return last_bdf; 628 } 629 630 /**************************************************************************** 631 * 632 * The following functions belong to the code path which parses the ACPI table 633 * the second time. In this ACPI parsing iteration we allocate IOMMU specific 634 * data structures, initialize the per PCI segment device/alias/rlookup table 635 * and also basically initialize the hardware. 636 * 637 ****************************************************************************/ 638 639 /* Allocate per PCI segment device table */ 640 static inline int __init alloc_dev_table(struct amd_iommu_pci_seg *pci_seg) 641 { 642 pci_seg->dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO | GFP_DMA32, 643 get_order(pci_seg->dev_table_size)); 644 if (!pci_seg->dev_table) 645 return -ENOMEM; 646 647 return 0; 648 } 649 650 static inline void free_dev_table(struct amd_iommu_pci_seg *pci_seg) 651 { 652 free_pages((unsigned long)pci_seg->dev_table, 653 get_order(pci_seg->dev_table_size)); 654 pci_seg->dev_table = NULL; 655 } 656 657 /* Allocate per PCI segment IOMMU rlookup table. */ 658 static inline int __init alloc_rlookup_table(struct amd_iommu_pci_seg *pci_seg) 659 { 660 pci_seg->rlookup_table = (void *)__get_free_pages( 661 GFP_KERNEL | __GFP_ZERO, 662 get_order(pci_seg->rlookup_table_size)); 663 if (pci_seg->rlookup_table == NULL) 664 return -ENOMEM; 665 666 return 0; 667 } 668 669 static inline void free_rlookup_table(struct amd_iommu_pci_seg *pci_seg) 670 { 671 free_pages((unsigned long)pci_seg->rlookup_table, 672 get_order(pci_seg->rlookup_table_size)); 673 pci_seg->rlookup_table = NULL; 674 } 675 676 static inline int __init alloc_irq_lookup_table(struct amd_iommu_pci_seg *pci_seg) 677 { 678 pci_seg->irq_lookup_table = (void *)__get_free_pages( 679 GFP_KERNEL | __GFP_ZERO, 680 get_order(pci_seg->rlookup_table_size)); 681 kmemleak_alloc(pci_seg->irq_lookup_table, 682 pci_seg->rlookup_table_size, 1, GFP_KERNEL); 683 if (pci_seg->irq_lookup_table == NULL) 684 return -ENOMEM; 685 686 return 0; 687 } 688 689 static inline void free_irq_lookup_table(struct amd_iommu_pci_seg *pci_seg) 690 { 691 kmemleak_free(pci_seg->irq_lookup_table); 692 free_pages((unsigned long)pci_seg->irq_lookup_table, 693 get_order(pci_seg->rlookup_table_size)); 694 pci_seg->irq_lookup_table = NULL; 695 } 696 697 static int __init alloc_alias_table(struct amd_iommu_pci_seg *pci_seg) 698 { 699 int i; 700 701 pci_seg->alias_table = (void *)__get_free_pages(GFP_KERNEL, 702 get_order(pci_seg->alias_table_size)); 703 if (!pci_seg->alias_table) 704 return -ENOMEM; 705 706 /* 707 * let all alias entries point to itself 708 */ 709 for (i = 0; i <= amd_iommu_last_bdf; ++i) 710 pci_seg->alias_table[i] = i; 711 712 return 0; 713 } 714 715 static void __init free_alias_table(struct amd_iommu_pci_seg *pci_seg) 716 { 717 free_pages((unsigned long)pci_seg->alias_table, 718 get_order(pci_seg->alias_table_size)); 719 pci_seg->alias_table = NULL; 720 } 721 722 /* 723 * Allocates the command buffer. This buffer is per AMD IOMMU. We can 724 * write commands to that buffer later and the IOMMU will execute them 725 * asynchronously 726 */ 727 static int __init alloc_command_buffer(struct amd_iommu *iommu) 728 { 729 iommu->cmd_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 730 get_order(CMD_BUFFER_SIZE)); 731 732 return iommu->cmd_buf ? 0 : -ENOMEM; 733 } 734 735 /* 736 * This function restarts event logging in case the IOMMU experienced 737 * an event log buffer overflow. 738 */ 739 void amd_iommu_restart_event_logging(struct amd_iommu *iommu) 740 { 741 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); 742 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN); 743 } 744 745 /* 746 * This function resets the command buffer if the IOMMU stopped fetching 747 * commands from it. 748 */ 749 static void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu) 750 { 751 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); 752 753 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); 754 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); 755 iommu->cmd_buf_head = 0; 756 iommu->cmd_buf_tail = 0; 757 758 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN); 759 } 760 761 /* 762 * This function writes the command buffer address to the hardware and 763 * enables it. 764 */ 765 static void iommu_enable_command_buffer(struct amd_iommu *iommu) 766 { 767 u64 entry; 768 769 BUG_ON(iommu->cmd_buf == NULL); 770 771 entry = iommu_virt_to_phys(iommu->cmd_buf); 772 entry |= MMIO_CMD_SIZE_512; 773 774 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET, 775 &entry, sizeof(entry)); 776 777 amd_iommu_reset_cmd_buffer(iommu); 778 } 779 780 /* 781 * This function disables the command buffer 782 */ 783 static void iommu_disable_command_buffer(struct amd_iommu *iommu) 784 { 785 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); 786 } 787 788 static void __init free_command_buffer(struct amd_iommu *iommu) 789 { 790 free_pages((unsigned long)iommu->cmd_buf, get_order(CMD_BUFFER_SIZE)); 791 } 792 793 static void *__init iommu_alloc_4k_pages(struct amd_iommu *iommu, 794 gfp_t gfp, size_t size) 795 { 796 int order = get_order(size); 797 void *buf = (void *)__get_free_pages(gfp, order); 798 799 if (buf && 800 iommu_feature(iommu, FEATURE_SNP) && 801 set_memory_4k((unsigned long)buf, (1 << order))) { 802 free_pages((unsigned long)buf, order); 803 buf = NULL; 804 } 805 806 return buf; 807 } 808 809 /* allocates the memory where the IOMMU will log its events to */ 810 static int __init alloc_event_buffer(struct amd_iommu *iommu) 811 { 812 iommu->evt_buf = iommu_alloc_4k_pages(iommu, GFP_KERNEL | __GFP_ZERO, 813 EVT_BUFFER_SIZE); 814 815 return iommu->evt_buf ? 0 : -ENOMEM; 816 } 817 818 static void iommu_enable_event_buffer(struct amd_iommu *iommu) 819 { 820 u64 entry; 821 822 BUG_ON(iommu->evt_buf == NULL); 823 824 entry = iommu_virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK; 825 826 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET, 827 &entry, sizeof(entry)); 828 829 /* set head and tail to zero manually */ 830 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); 831 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); 832 833 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN); 834 } 835 836 /* 837 * This function disables the event log buffer 838 */ 839 static void iommu_disable_event_buffer(struct amd_iommu *iommu) 840 { 841 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); 842 } 843 844 static void __init free_event_buffer(struct amd_iommu *iommu) 845 { 846 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE)); 847 } 848 849 /* allocates the memory where the IOMMU will log its events to */ 850 static int __init alloc_ppr_log(struct amd_iommu *iommu) 851 { 852 iommu->ppr_log = iommu_alloc_4k_pages(iommu, GFP_KERNEL | __GFP_ZERO, 853 PPR_LOG_SIZE); 854 855 return iommu->ppr_log ? 0 : -ENOMEM; 856 } 857 858 static void iommu_enable_ppr_log(struct amd_iommu *iommu) 859 { 860 u64 entry; 861 862 if (iommu->ppr_log == NULL) 863 return; 864 865 entry = iommu_virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512; 866 867 memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET, 868 &entry, sizeof(entry)); 869 870 /* set head and tail to zero manually */ 871 writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); 872 writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); 873 874 iommu_feature_enable(iommu, CONTROL_PPRLOG_EN); 875 iommu_feature_enable(iommu, CONTROL_PPR_EN); 876 } 877 878 static void __init free_ppr_log(struct amd_iommu *iommu) 879 { 880 free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE)); 881 } 882 883 static void free_ga_log(struct amd_iommu *iommu) 884 { 885 #ifdef CONFIG_IRQ_REMAP 886 free_pages((unsigned long)iommu->ga_log, get_order(GA_LOG_SIZE)); 887 free_pages((unsigned long)iommu->ga_log_tail, get_order(8)); 888 #endif 889 } 890 891 static int iommu_ga_log_enable(struct amd_iommu *iommu) 892 { 893 #ifdef CONFIG_IRQ_REMAP 894 u32 status, i; 895 u64 entry; 896 897 if (!iommu->ga_log) 898 return -EINVAL; 899 900 /* Check if already running */ 901 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); 902 if (WARN_ON(status & (MMIO_STATUS_GALOG_RUN_MASK))) 903 return 0; 904 905 entry = iommu_virt_to_phys(iommu->ga_log) | GA_LOG_SIZE_512; 906 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_BASE_OFFSET, 907 &entry, sizeof(entry)); 908 entry = (iommu_virt_to_phys(iommu->ga_log_tail) & 909 (BIT_ULL(52)-1)) & ~7ULL; 910 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_TAIL_OFFSET, 911 &entry, sizeof(entry)); 912 writel(0x00, iommu->mmio_base + MMIO_GA_HEAD_OFFSET); 913 writel(0x00, iommu->mmio_base + MMIO_GA_TAIL_OFFSET); 914 915 916 iommu_feature_enable(iommu, CONTROL_GAINT_EN); 917 iommu_feature_enable(iommu, CONTROL_GALOG_EN); 918 919 for (i = 0; i < LOOP_TIMEOUT; ++i) { 920 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); 921 if (status & (MMIO_STATUS_GALOG_RUN_MASK)) 922 break; 923 udelay(10); 924 } 925 926 if (WARN_ON(i >= LOOP_TIMEOUT)) 927 return -EINVAL; 928 #endif /* CONFIG_IRQ_REMAP */ 929 return 0; 930 } 931 932 static int iommu_init_ga_log(struct amd_iommu *iommu) 933 { 934 #ifdef CONFIG_IRQ_REMAP 935 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) 936 return 0; 937 938 iommu->ga_log = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 939 get_order(GA_LOG_SIZE)); 940 if (!iommu->ga_log) 941 goto err_out; 942 943 iommu->ga_log_tail = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 944 get_order(8)); 945 if (!iommu->ga_log_tail) 946 goto err_out; 947 948 return 0; 949 err_out: 950 free_ga_log(iommu); 951 return -EINVAL; 952 #else 953 return 0; 954 #endif /* CONFIG_IRQ_REMAP */ 955 } 956 957 static int __init alloc_cwwb_sem(struct amd_iommu *iommu) 958 { 959 iommu->cmd_sem = iommu_alloc_4k_pages(iommu, GFP_KERNEL | __GFP_ZERO, 1); 960 961 return iommu->cmd_sem ? 0 : -ENOMEM; 962 } 963 964 static void __init free_cwwb_sem(struct amd_iommu *iommu) 965 { 966 if (iommu->cmd_sem) 967 free_page((unsigned long)iommu->cmd_sem); 968 } 969 970 static void iommu_enable_xt(struct amd_iommu *iommu) 971 { 972 #ifdef CONFIG_IRQ_REMAP 973 /* 974 * XT mode (32-bit APIC destination ID) requires 975 * GA mode (128-bit IRTE support) as a prerequisite. 976 */ 977 if (AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir) && 978 amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE) 979 iommu_feature_enable(iommu, CONTROL_XT_EN); 980 #endif /* CONFIG_IRQ_REMAP */ 981 } 982 983 static void iommu_enable_gt(struct amd_iommu *iommu) 984 { 985 if (!iommu_feature(iommu, FEATURE_GT)) 986 return; 987 988 iommu_feature_enable(iommu, CONTROL_GT_EN); 989 } 990 991 /* sets a specific bit in the device table entry. */ 992 static void __set_dev_entry_bit(struct dev_table_entry *dev_table, 993 u16 devid, u8 bit) 994 { 995 int i = (bit >> 6) & 0x03; 996 int _bit = bit & 0x3f; 997 998 dev_table[devid].data[i] |= (1UL << _bit); 999 } 1000 1001 static void set_dev_entry_bit(struct amd_iommu *iommu, u16 devid, u8 bit) 1002 { 1003 struct dev_table_entry *dev_table = get_dev_table(iommu); 1004 1005 return __set_dev_entry_bit(dev_table, devid, bit); 1006 } 1007 1008 static int __get_dev_entry_bit(struct dev_table_entry *dev_table, 1009 u16 devid, u8 bit) 1010 { 1011 int i = (bit >> 6) & 0x03; 1012 int _bit = bit & 0x3f; 1013 1014 return (dev_table[devid].data[i] & (1UL << _bit)) >> _bit; 1015 } 1016 1017 static int get_dev_entry_bit(struct amd_iommu *iommu, u16 devid, u8 bit) 1018 { 1019 struct dev_table_entry *dev_table = get_dev_table(iommu); 1020 1021 return __get_dev_entry_bit(dev_table, devid, bit); 1022 } 1023 1024 static bool __copy_device_table(struct amd_iommu *iommu) 1025 { 1026 u64 int_ctl, int_tab_len, entry = 0; 1027 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; 1028 struct dev_table_entry *old_devtb = NULL; 1029 u32 lo, hi, devid, old_devtb_size; 1030 phys_addr_t old_devtb_phys; 1031 u16 dom_id, dte_v, irq_v; 1032 gfp_t gfp_flag; 1033 u64 tmp; 1034 1035 /* Each IOMMU use separate device table with the same size */ 1036 lo = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET); 1037 hi = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET + 4); 1038 entry = (((u64) hi) << 32) + lo; 1039 1040 old_devtb_size = ((entry & ~PAGE_MASK) + 1) << 12; 1041 if (old_devtb_size != pci_seg->dev_table_size) { 1042 pr_err("The device table size of IOMMU:%d is not expected!\n", 1043 iommu->index); 1044 return false; 1045 } 1046 1047 /* 1048 * When SME is enabled in the first kernel, the entry includes the 1049 * memory encryption mask(sme_me_mask), we must remove the memory 1050 * encryption mask to obtain the true physical address in kdump kernel. 1051 */ 1052 old_devtb_phys = __sme_clr(entry) & PAGE_MASK; 1053 1054 if (old_devtb_phys >= 0x100000000ULL) { 1055 pr_err("The address of old device table is above 4G, not trustworthy!\n"); 1056 return false; 1057 } 1058 old_devtb = (cc_platform_has(CC_ATTR_HOST_MEM_ENCRYPT) && is_kdump_kernel()) 1059 ? (__force void *)ioremap_encrypted(old_devtb_phys, 1060 pci_seg->dev_table_size) 1061 : memremap(old_devtb_phys, pci_seg->dev_table_size, MEMREMAP_WB); 1062 1063 if (!old_devtb) 1064 return false; 1065 1066 gfp_flag = GFP_KERNEL | __GFP_ZERO | GFP_DMA32; 1067 pci_seg->old_dev_tbl_cpy = (void *)__get_free_pages(gfp_flag, 1068 get_order(pci_seg->dev_table_size)); 1069 if (pci_seg->old_dev_tbl_cpy == NULL) { 1070 pr_err("Failed to allocate memory for copying old device table!\n"); 1071 memunmap(old_devtb); 1072 return false; 1073 } 1074 1075 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) { 1076 pci_seg->old_dev_tbl_cpy[devid] = old_devtb[devid]; 1077 dom_id = old_devtb[devid].data[1] & DEV_DOMID_MASK; 1078 dte_v = old_devtb[devid].data[0] & DTE_FLAG_V; 1079 1080 if (dte_v && dom_id) { 1081 pci_seg->old_dev_tbl_cpy[devid].data[0] = old_devtb[devid].data[0]; 1082 pci_seg->old_dev_tbl_cpy[devid].data[1] = old_devtb[devid].data[1]; 1083 __set_bit(dom_id, amd_iommu_pd_alloc_bitmap); 1084 /* If gcr3 table existed, mask it out */ 1085 if (old_devtb[devid].data[0] & DTE_FLAG_GV) { 1086 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B; 1087 tmp |= DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C; 1088 pci_seg->old_dev_tbl_cpy[devid].data[1] &= ~tmp; 1089 tmp = DTE_GCR3_VAL_A(~0ULL) << DTE_GCR3_SHIFT_A; 1090 tmp |= DTE_FLAG_GV; 1091 pci_seg->old_dev_tbl_cpy[devid].data[0] &= ~tmp; 1092 } 1093 } 1094 1095 irq_v = old_devtb[devid].data[2] & DTE_IRQ_REMAP_ENABLE; 1096 int_ctl = old_devtb[devid].data[2] & DTE_IRQ_REMAP_INTCTL_MASK; 1097 int_tab_len = old_devtb[devid].data[2] & DTE_INTTABLEN_MASK; 1098 if (irq_v && (int_ctl || int_tab_len)) { 1099 if ((int_ctl != DTE_IRQ_REMAP_INTCTL) || 1100 (int_tab_len != DTE_INTTABLEN)) { 1101 pr_err("Wrong old irq remapping flag: %#x\n", devid); 1102 memunmap(old_devtb); 1103 return false; 1104 } 1105 1106 pci_seg->old_dev_tbl_cpy[devid].data[2] = old_devtb[devid].data[2]; 1107 } 1108 } 1109 memunmap(old_devtb); 1110 1111 return true; 1112 } 1113 1114 static bool copy_device_table(void) 1115 { 1116 struct amd_iommu *iommu; 1117 struct amd_iommu_pci_seg *pci_seg; 1118 1119 if (!amd_iommu_pre_enabled) 1120 return false; 1121 1122 pr_warn("Translation is already enabled - trying to copy translation structures\n"); 1123 1124 /* 1125 * All IOMMUs within PCI segment shares common device table. 1126 * Hence copy device table only once per PCI segment. 1127 */ 1128 for_each_pci_segment(pci_seg) { 1129 for_each_iommu(iommu) { 1130 if (pci_seg->id != iommu->pci_seg->id) 1131 continue; 1132 if (!__copy_device_table(iommu)) 1133 return false; 1134 break; 1135 } 1136 } 1137 1138 return true; 1139 } 1140 1141 void amd_iommu_apply_erratum_63(struct amd_iommu *iommu, u16 devid) 1142 { 1143 int sysmgt; 1144 1145 sysmgt = get_dev_entry_bit(iommu, devid, DEV_ENTRY_SYSMGT1) | 1146 (get_dev_entry_bit(iommu, devid, DEV_ENTRY_SYSMGT2) << 1); 1147 1148 if (sysmgt == 0x01) 1149 set_dev_entry_bit(iommu, devid, DEV_ENTRY_IW); 1150 } 1151 1152 /* Writes the specific IOMMU for a device into the rlookup table */ 1153 static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid) 1154 { 1155 iommu->pci_seg->rlookup_table[devid] = iommu; 1156 } 1157 1158 /* 1159 * This function takes the device specific flags read from the ACPI 1160 * table and sets up the device table entry with that information 1161 */ 1162 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu, 1163 u16 devid, u32 flags, u32 ext_flags) 1164 { 1165 if (flags & ACPI_DEVFLAG_INITPASS) 1166 set_dev_entry_bit(iommu, devid, DEV_ENTRY_INIT_PASS); 1167 if (flags & ACPI_DEVFLAG_EXTINT) 1168 set_dev_entry_bit(iommu, devid, DEV_ENTRY_EINT_PASS); 1169 if (flags & ACPI_DEVFLAG_NMI) 1170 set_dev_entry_bit(iommu, devid, DEV_ENTRY_NMI_PASS); 1171 if (flags & ACPI_DEVFLAG_SYSMGT1) 1172 set_dev_entry_bit(iommu, devid, DEV_ENTRY_SYSMGT1); 1173 if (flags & ACPI_DEVFLAG_SYSMGT2) 1174 set_dev_entry_bit(iommu, devid, DEV_ENTRY_SYSMGT2); 1175 if (flags & ACPI_DEVFLAG_LINT0) 1176 set_dev_entry_bit(iommu, devid, DEV_ENTRY_LINT0_PASS); 1177 if (flags & ACPI_DEVFLAG_LINT1) 1178 set_dev_entry_bit(iommu, devid, DEV_ENTRY_LINT1_PASS); 1179 1180 amd_iommu_apply_erratum_63(iommu, devid); 1181 1182 set_iommu_for_device(iommu, devid); 1183 } 1184 1185 int __init add_special_device(u8 type, u8 id, u16 *devid, bool cmd_line) 1186 { 1187 struct devid_map *entry; 1188 struct list_head *list; 1189 1190 if (type == IVHD_SPECIAL_IOAPIC) 1191 list = &ioapic_map; 1192 else if (type == IVHD_SPECIAL_HPET) 1193 list = &hpet_map; 1194 else 1195 return -EINVAL; 1196 1197 list_for_each_entry(entry, list, list) { 1198 if (!(entry->id == id && entry->cmd_line)) 1199 continue; 1200 1201 pr_info("Command-line override present for %s id %d - ignoring\n", 1202 type == IVHD_SPECIAL_IOAPIC ? "IOAPIC" : "HPET", id); 1203 1204 *devid = entry->devid; 1205 1206 return 0; 1207 } 1208 1209 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 1210 if (!entry) 1211 return -ENOMEM; 1212 1213 entry->id = id; 1214 entry->devid = *devid; 1215 entry->cmd_line = cmd_line; 1216 1217 list_add_tail(&entry->list, list); 1218 1219 return 0; 1220 } 1221 1222 static int __init add_acpi_hid_device(u8 *hid, u8 *uid, u16 *devid, 1223 bool cmd_line) 1224 { 1225 struct acpihid_map_entry *entry; 1226 struct list_head *list = &acpihid_map; 1227 1228 list_for_each_entry(entry, list, list) { 1229 if (strcmp(entry->hid, hid) || 1230 (*uid && *entry->uid && strcmp(entry->uid, uid)) || 1231 !entry->cmd_line) 1232 continue; 1233 1234 pr_info("Command-line override for hid:%s uid:%s\n", 1235 hid, uid); 1236 *devid = entry->devid; 1237 return 0; 1238 } 1239 1240 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 1241 if (!entry) 1242 return -ENOMEM; 1243 1244 memcpy(entry->uid, uid, strlen(uid)); 1245 memcpy(entry->hid, hid, strlen(hid)); 1246 entry->devid = *devid; 1247 entry->cmd_line = cmd_line; 1248 entry->root_devid = (entry->devid & (~0x7)); 1249 1250 pr_info("%s, add hid:%s, uid:%s, rdevid:%d\n", 1251 entry->cmd_line ? "cmd" : "ivrs", 1252 entry->hid, entry->uid, entry->root_devid); 1253 1254 list_add_tail(&entry->list, list); 1255 return 0; 1256 } 1257 1258 static int __init add_early_maps(void) 1259 { 1260 int i, ret; 1261 1262 for (i = 0; i < early_ioapic_map_size; ++i) { 1263 ret = add_special_device(IVHD_SPECIAL_IOAPIC, 1264 early_ioapic_map[i].id, 1265 &early_ioapic_map[i].devid, 1266 early_ioapic_map[i].cmd_line); 1267 if (ret) 1268 return ret; 1269 } 1270 1271 for (i = 0; i < early_hpet_map_size; ++i) { 1272 ret = add_special_device(IVHD_SPECIAL_HPET, 1273 early_hpet_map[i].id, 1274 &early_hpet_map[i].devid, 1275 early_hpet_map[i].cmd_line); 1276 if (ret) 1277 return ret; 1278 } 1279 1280 for (i = 0; i < early_acpihid_map_size; ++i) { 1281 ret = add_acpi_hid_device(early_acpihid_map[i].hid, 1282 early_acpihid_map[i].uid, 1283 &early_acpihid_map[i].devid, 1284 early_acpihid_map[i].cmd_line); 1285 if (ret) 1286 return ret; 1287 } 1288 1289 return 0; 1290 } 1291 1292 /* 1293 * Takes a pointer to an AMD IOMMU entry in the ACPI table and 1294 * initializes the hardware and our data structures with it. 1295 */ 1296 static int __init init_iommu_from_acpi(struct amd_iommu *iommu, 1297 struct ivhd_header *h) 1298 { 1299 u8 *p = (u8 *)h; 1300 u8 *end = p, flags = 0; 1301 u16 devid = 0, devid_start = 0, devid_to = 0; 1302 u32 dev_i, ext_flags = 0; 1303 bool alias = false; 1304 struct ivhd_entry *e; 1305 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; 1306 u32 ivhd_size; 1307 int ret; 1308 1309 1310 ret = add_early_maps(); 1311 if (ret) 1312 return ret; 1313 1314 amd_iommu_apply_ivrs_quirks(); 1315 1316 /* 1317 * First save the recommended feature enable bits from ACPI 1318 */ 1319 iommu->acpi_flags = h->flags; 1320 1321 /* 1322 * Done. Now parse the device entries 1323 */ 1324 ivhd_size = get_ivhd_header_size(h); 1325 if (!ivhd_size) { 1326 pr_err("Unsupported IVHD type %#x\n", h->type); 1327 return -EINVAL; 1328 } 1329 1330 p += ivhd_size; 1331 1332 end += h->length; 1333 1334 1335 while (p < end) { 1336 e = (struct ivhd_entry *)p; 1337 switch (e->type) { 1338 case IVHD_DEV_ALL: 1339 1340 DUMP_printk(" DEV_ALL\t\t\tflags: %02x\n", e->flags); 1341 1342 for (dev_i = 0; dev_i <= amd_iommu_last_bdf; ++dev_i) 1343 set_dev_entry_from_acpi(iommu, dev_i, e->flags, 0); 1344 break; 1345 case IVHD_DEV_SELECT: 1346 1347 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x " 1348 "flags: %02x\n", 1349 PCI_BUS_NUM(e->devid), 1350 PCI_SLOT(e->devid), 1351 PCI_FUNC(e->devid), 1352 e->flags); 1353 1354 devid = e->devid; 1355 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); 1356 break; 1357 case IVHD_DEV_SELECT_RANGE_START: 1358 1359 DUMP_printk(" DEV_SELECT_RANGE_START\t " 1360 "devid: %02x:%02x.%x flags: %02x\n", 1361 PCI_BUS_NUM(e->devid), 1362 PCI_SLOT(e->devid), 1363 PCI_FUNC(e->devid), 1364 e->flags); 1365 1366 devid_start = e->devid; 1367 flags = e->flags; 1368 ext_flags = 0; 1369 alias = false; 1370 break; 1371 case IVHD_DEV_ALIAS: 1372 1373 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x " 1374 "flags: %02x devid_to: %02x:%02x.%x\n", 1375 PCI_BUS_NUM(e->devid), 1376 PCI_SLOT(e->devid), 1377 PCI_FUNC(e->devid), 1378 e->flags, 1379 PCI_BUS_NUM(e->ext >> 8), 1380 PCI_SLOT(e->ext >> 8), 1381 PCI_FUNC(e->ext >> 8)); 1382 1383 devid = e->devid; 1384 devid_to = e->ext >> 8; 1385 set_dev_entry_from_acpi(iommu, devid , e->flags, 0); 1386 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0); 1387 pci_seg->alias_table[devid] = devid_to; 1388 break; 1389 case IVHD_DEV_ALIAS_RANGE: 1390 1391 DUMP_printk(" DEV_ALIAS_RANGE\t\t " 1392 "devid: %02x:%02x.%x flags: %02x " 1393 "devid_to: %02x:%02x.%x\n", 1394 PCI_BUS_NUM(e->devid), 1395 PCI_SLOT(e->devid), 1396 PCI_FUNC(e->devid), 1397 e->flags, 1398 PCI_BUS_NUM(e->ext >> 8), 1399 PCI_SLOT(e->ext >> 8), 1400 PCI_FUNC(e->ext >> 8)); 1401 1402 devid_start = e->devid; 1403 flags = e->flags; 1404 devid_to = e->ext >> 8; 1405 ext_flags = 0; 1406 alias = true; 1407 break; 1408 case IVHD_DEV_EXT_SELECT: 1409 1410 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x " 1411 "flags: %02x ext: %08x\n", 1412 PCI_BUS_NUM(e->devid), 1413 PCI_SLOT(e->devid), 1414 PCI_FUNC(e->devid), 1415 e->flags, e->ext); 1416 1417 devid = e->devid; 1418 set_dev_entry_from_acpi(iommu, devid, e->flags, 1419 e->ext); 1420 break; 1421 case IVHD_DEV_EXT_SELECT_RANGE: 1422 1423 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: " 1424 "%02x:%02x.%x flags: %02x ext: %08x\n", 1425 PCI_BUS_NUM(e->devid), 1426 PCI_SLOT(e->devid), 1427 PCI_FUNC(e->devid), 1428 e->flags, e->ext); 1429 1430 devid_start = e->devid; 1431 flags = e->flags; 1432 ext_flags = e->ext; 1433 alias = false; 1434 break; 1435 case IVHD_DEV_RANGE_END: 1436 1437 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n", 1438 PCI_BUS_NUM(e->devid), 1439 PCI_SLOT(e->devid), 1440 PCI_FUNC(e->devid)); 1441 1442 devid = e->devid; 1443 for (dev_i = devid_start; dev_i <= devid; ++dev_i) { 1444 if (alias) { 1445 pci_seg->alias_table[dev_i] = devid_to; 1446 set_dev_entry_from_acpi(iommu, 1447 devid_to, flags, ext_flags); 1448 } 1449 set_dev_entry_from_acpi(iommu, dev_i, 1450 flags, ext_flags); 1451 } 1452 break; 1453 case IVHD_DEV_SPECIAL: { 1454 u8 handle, type; 1455 const char *var; 1456 u16 devid; 1457 int ret; 1458 1459 handle = e->ext & 0xff; 1460 devid = (e->ext >> 8) & 0xffff; 1461 type = (e->ext >> 24) & 0xff; 1462 1463 if (type == IVHD_SPECIAL_IOAPIC) 1464 var = "IOAPIC"; 1465 else if (type == IVHD_SPECIAL_HPET) 1466 var = "HPET"; 1467 else 1468 var = "UNKNOWN"; 1469 1470 DUMP_printk(" DEV_SPECIAL(%s[%d])\t\tdevid: %02x:%02x.%x\n", 1471 var, (int)handle, 1472 PCI_BUS_NUM(devid), 1473 PCI_SLOT(devid), 1474 PCI_FUNC(devid)); 1475 1476 ret = add_special_device(type, handle, &devid, false); 1477 if (ret) 1478 return ret; 1479 1480 /* 1481 * add_special_device might update the devid in case a 1482 * command-line override is present. So call 1483 * set_dev_entry_from_acpi after add_special_device. 1484 */ 1485 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); 1486 1487 break; 1488 } 1489 case IVHD_DEV_ACPI_HID: { 1490 u16 devid; 1491 u8 hid[ACPIHID_HID_LEN]; 1492 u8 uid[ACPIHID_UID_LEN]; 1493 int ret; 1494 1495 if (h->type != 0x40) { 1496 pr_err(FW_BUG "Invalid IVHD device type %#x\n", 1497 e->type); 1498 break; 1499 } 1500 1501 BUILD_BUG_ON(sizeof(e->ext_hid) != ACPIHID_HID_LEN - 1); 1502 memcpy(hid, &e->ext_hid, ACPIHID_HID_LEN - 1); 1503 hid[ACPIHID_HID_LEN - 1] = '\0'; 1504 1505 if (!(*hid)) { 1506 pr_err(FW_BUG "Invalid HID.\n"); 1507 break; 1508 } 1509 1510 uid[0] = '\0'; 1511 switch (e->uidf) { 1512 case UID_NOT_PRESENT: 1513 1514 if (e->uidl != 0) 1515 pr_warn(FW_BUG "Invalid UID length.\n"); 1516 1517 break; 1518 case UID_IS_INTEGER: 1519 1520 sprintf(uid, "%d", e->uid); 1521 1522 break; 1523 case UID_IS_CHARACTER: 1524 1525 memcpy(uid, &e->uid, e->uidl); 1526 uid[e->uidl] = '\0'; 1527 1528 break; 1529 default: 1530 break; 1531 } 1532 1533 devid = e->devid; 1534 DUMP_printk(" DEV_ACPI_HID(%s[%s])\t\tdevid: %02x:%02x.%x\n", 1535 hid, uid, 1536 PCI_BUS_NUM(devid), 1537 PCI_SLOT(devid), 1538 PCI_FUNC(devid)); 1539 1540 flags = e->flags; 1541 1542 ret = add_acpi_hid_device(hid, uid, &devid, false); 1543 if (ret) 1544 return ret; 1545 1546 /* 1547 * add_special_device might update the devid in case a 1548 * command-line override is present. So call 1549 * set_dev_entry_from_acpi after add_special_device. 1550 */ 1551 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); 1552 1553 break; 1554 } 1555 default: 1556 break; 1557 } 1558 1559 p += ivhd_entry_length(p); 1560 } 1561 1562 return 0; 1563 } 1564 1565 /* Allocate PCI segment data structure */ 1566 static struct amd_iommu_pci_seg *__init alloc_pci_segment(u16 id, 1567 struct acpi_table_header *ivrs_base) 1568 { 1569 struct amd_iommu_pci_seg *pci_seg; 1570 int last_bdf; 1571 1572 /* 1573 * First parse ACPI tables to find the largest Bus/Dev/Func we need to 1574 * handle in this PCI segment. Upon this information the shared data 1575 * structures for the PCI segments in the system will be allocated. 1576 */ 1577 last_bdf = find_last_devid_acpi(ivrs_base, id); 1578 if (last_bdf < 0) 1579 return NULL; 1580 1581 pci_seg = kzalloc(sizeof(struct amd_iommu_pci_seg), GFP_KERNEL); 1582 if (pci_seg == NULL) 1583 return NULL; 1584 1585 pci_seg->last_bdf = last_bdf; 1586 DUMP_printk("PCI segment : 0x%0x, last bdf : 0x%04x\n", id, last_bdf); 1587 pci_seg->dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE); 1588 pci_seg->alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE); 1589 pci_seg->rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE); 1590 1591 pci_seg->id = id; 1592 init_llist_head(&pci_seg->dev_data_list); 1593 INIT_LIST_HEAD(&pci_seg->unity_map); 1594 list_add_tail(&pci_seg->list, &amd_iommu_pci_seg_list); 1595 1596 if (alloc_dev_table(pci_seg)) 1597 return NULL; 1598 if (alloc_alias_table(pci_seg)) 1599 return NULL; 1600 if (alloc_rlookup_table(pci_seg)) 1601 return NULL; 1602 1603 return pci_seg; 1604 } 1605 1606 static struct amd_iommu_pci_seg *__init get_pci_segment(u16 id, 1607 struct acpi_table_header *ivrs_base) 1608 { 1609 struct amd_iommu_pci_seg *pci_seg; 1610 1611 for_each_pci_segment(pci_seg) { 1612 if (pci_seg->id == id) 1613 return pci_seg; 1614 } 1615 1616 return alloc_pci_segment(id, ivrs_base); 1617 } 1618 1619 static void __init free_pci_segments(void) 1620 { 1621 struct amd_iommu_pci_seg *pci_seg, *next; 1622 1623 for_each_pci_segment_safe(pci_seg, next) { 1624 list_del(&pci_seg->list); 1625 free_irq_lookup_table(pci_seg); 1626 free_rlookup_table(pci_seg); 1627 free_alias_table(pci_seg); 1628 free_dev_table(pci_seg); 1629 kfree(pci_seg); 1630 } 1631 } 1632 1633 static void __init free_iommu_one(struct amd_iommu *iommu) 1634 { 1635 free_cwwb_sem(iommu); 1636 free_command_buffer(iommu); 1637 free_event_buffer(iommu); 1638 free_ppr_log(iommu); 1639 free_ga_log(iommu); 1640 iommu_unmap_mmio_space(iommu); 1641 } 1642 1643 static void __init free_iommu_all(void) 1644 { 1645 struct amd_iommu *iommu, *next; 1646 1647 for_each_iommu_safe(iommu, next) { 1648 list_del(&iommu->list); 1649 free_iommu_one(iommu); 1650 kfree(iommu); 1651 } 1652 } 1653 1654 /* 1655 * Family15h Model 10h-1fh erratum 746 (IOMMU Logging May Stall Translations) 1656 * Workaround: 1657 * BIOS should disable L2B micellaneous clock gating by setting 1658 * L2_L2B_CK_GATE_CONTROL[CKGateL2BMiscDisable](D0F2xF4_x90[2]) = 1b 1659 */ 1660 static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu) 1661 { 1662 u32 value; 1663 1664 if ((boot_cpu_data.x86 != 0x15) || 1665 (boot_cpu_data.x86_model < 0x10) || 1666 (boot_cpu_data.x86_model > 0x1f)) 1667 return; 1668 1669 pci_write_config_dword(iommu->dev, 0xf0, 0x90); 1670 pci_read_config_dword(iommu->dev, 0xf4, &value); 1671 1672 if (value & BIT(2)) 1673 return; 1674 1675 /* Select NB indirect register 0x90 and enable writing */ 1676 pci_write_config_dword(iommu->dev, 0xf0, 0x90 | (1 << 8)); 1677 1678 pci_write_config_dword(iommu->dev, 0xf4, value | 0x4); 1679 pci_info(iommu->dev, "Applying erratum 746 workaround\n"); 1680 1681 /* Clear the enable writing bit */ 1682 pci_write_config_dword(iommu->dev, 0xf0, 0x90); 1683 } 1684 1685 /* 1686 * Family15h Model 30h-3fh (IOMMU Mishandles ATS Write Permission) 1687 * Workaround: 1688 * BIOS should enable ATS write permission check by setting 1689 * L2_DEBUG_3[AtsIgnoreIWDis](D0F2xF4_x47[0]) = 1b 1690 */ 1691 static void amd_iommu_ats_write_check_workaround(struct amd_iommu *iommu) 1692 { 1693 u32 value; 1694 1695 if ((boot_cpu_data.x86 != 0x15) || 1696 (boot_cpu_data.x86_model < 0x30) || 1697 (boot_cpu_data.x86_model > 0x3f)) 1698 return; 1699 1700 /* Test L2_DEBUG_3[AtsIgnoreIWDis] == 1 */ 1701 value = iommu_read_l2(iommu, 0x47); 1702 1703 if (value & BIT(0)) 1704 return; 1705 1706 /* Set L2_DEBUG_3[AtsIgnoreIWDis] = 1 */ 1707 iommu_write_l2(iommu, 0x47, value | BIT(0)); 1708 1709 pci_info(iommu->dev, "Applying ATS write check workaround\n"); 1710 } 1711 1712 /* 1713 * This function glues the initialization function for one IOMMU 1714 * together and also allocates the command buffer and programs the 1715 * hardware. It does NOT enable the IOMMU. This is done afterwards. 1716 */ 1717 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h, 1718 struct acpi_table_header *ivrs_base) 1719 { 1720 struct amd_iommu_pci_seg *pci_seg; 1721 int ret; 1722 1723 pci_seg = get_pci_segment(h->pci_seg, ivrs_base); 1724 if (pci_seg == NULL) 1725 return -ENOMEM; 1726 iommu->pci_seg = pci_seg; 1727 1728 raw_spin_lock_init(&iommu->lock); 1729 iommu->cmd_sem_val = 0; 1730 1731 /* Add IOMMU to internal data structures */ 1732 list_add_tail(&iommu->list, &amd_iommu_list); 1733 iommu->index = amd_iommus_present++; 1734 1735 if (unlikely(iommu->index >= MAX_IOMMUS)) { 1736 WARN(1, "System has more IOMMUs than supported by this driver\n"); 1737 return -ENOSYS; 1738 } 1739 1740 /* Index is fine - add IOMMU to the array */ 1741 amd_iommus[iommu->index] = iommu; 1742 1743 /* 1744 * Copy data from ACPI table entry to the iommu struct 1745 */ 1746 iommu->devid = h->devid; 1747 iommu->cap_ptr = h->cap_ptr; 1748 iommu->mmio_phys = h->mmio_phys; 1749 1750 switch (h->type) { 1751 case 0x10: 1752 /* Check if IVHD EFR contains proper max banks/counters */ 1753 if ((h->efr_attr != 0) && 1754 ((h->efr_attr & (0xF << 13)) != 0) && 1755 ((h->efr_attr & (0x3F << 17)) != 0)) 1756 iommu->mmio_phys_end = MMIO_REG_END_OFFSET; 1757 else 1758 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET; 1759 1760 /* 1761 * Note: GA (128-bit IRTE) mode requires cmpxchg16b supports. 1762 * GAM also requires GA mode. Therefore, we need to 1763 * check cmpxchg16b support before enabling it. 1764 */ 1765 if (!boot_cpu_has(X86_FEATURE_CX16) || 1766 ((h->efr_attr & (0x1 << IOMMU_FEAT_GASUP_SHIFT)) == 0)) 1767 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY; 1768 break; 1769 case 0x11: 1770 case 0x40: 1771 if (h->efr_reg & (1 << 9)) 1772 iommu->mmio_phys_end = MMIO_REG_END_OFFSET; 1773 else 1774 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET; 1775 1776 /* 1777 * Note: GA (128-bit IRTE) mode requires cmpxchg16b supports. 1778 * XT, GAM also requires GA mode. Therefore, we need to 1779 * check cmpxchg16b support before enabling them. 1780 */ 1781 if (!boot_cpu_has(X86_FEATURE_CX16) || 1782 ((h->efr_reg & (0x1 << IOMMU_EFR_GASUP_SHIFT)) == 0)) { 1783 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY; 1784 break; 1785 } 1786 1787 if (h->efr_reg & BIT(IOMMU_EFR_XTSUP_SHIFT)) 1788 amd_iommu_xt_mode = IRQ_REMAP_X2APIC_MODE; 1789 1790 early_iommu_features_init(iommu, h); 1791 1792 break; 1793 default: 1794 return -EINVAL; 1795 } 1796 1797 iommu->mmio_base = iommu_map_mmio_space(iommu->mmio_phys, 1798 iommu->mmio_phys_end); 1799 if (!iommu->mmio_base) 1800 return -ENOMEM; 1801 1802 if (alloc_cwwb_sem(iommu)) 1803 return -ENOMEM; 1804 1805 if (alloc_command_buffer(iommu)) 1806 return -ENOMEM; 1807 1808 if (alloc_event_buffer(iommu)) 1809 return -ENOMEM; 1810 1811 iommu->int_enabled = false; 1812 1813 init_translation_status(iommu); 1814 if (translation_pre_enabled(iommu) && !is_kdump_kernel()) { 1815 iommu_disable(iommu); 1816 clear_translation_pre_enabled(iommu); 1817 pr_warn("Translation was enabled for IOMMU:%d but we are not in kdump mode\n", 1818 iommu->index); 1819 } 1820 if (amd_iommu_pre_enabled) 1821 amd_iommu_pre_enabled = translation_pre_enabled(iommu); 1822 1823 ret = init_iommu_from_acpi(iommu, h); 1824 if (ret) 1825 return ret; 1826 1827 if (amd_iommu_irq_remap) { 1828 ret = amd_iommu_create_irq_domain(iommu); 1829 if (ret) 1830 return ret; 1831 } 1832 1833 /* 1834 * Make sure IOMMU is not considered to translate itself. The IVRS 1835 * table tells us so, but this is a lie! 1836 */ 1837 pci_seg->rlookup_table[iommu->devid] = NULL; 1838 1839 return 0; 1840 } 1841 1842 /** 1843 * get_highest_supported_ivhd_type - Look up the appropriate IVHD type 1844 * @ivrs: Pointer to the IVRS header 1845 * 1846 * This function search through all IVDB of the maximum supported IVHD 1847 */ 1848 static u8 get_highest_supported_ivhd_type(struct acpi_table_header *ivrs) 1849 { 1850 u8 *base = (u8 *)ivrs; 1851 struct ivhd_header *ivhd = (struct ivhd_header *) 1852 (base + IVRS_HEADER_LENGTH); 1853 u8 last_type = ivhd->type; 1854 u16 devid = ivhd->devid; 1855 1856 while (((u8 *)ivhd - base < ivrs->length) && 1857 (ivhd->type <= ACPI_IVHD_TYPE_MAX_SUPPORTED)) { 1858 u8 *p = (u8 *) ivhd; 1859 1860 if (ivhd->devid == devid) 1861 last_type = ivhd->type; 1862 ivhd = (struct ivhd_header *)(p + ivhd->length); 1863 } 1864 1865 return last_type; 1866 } 1867 1868 /* 1869 * Iterates over all IOMMU entries in the ACPI table, allocates the 1870 * IOMMU structure and initializes it with init_iommu_one() 1871 */ 1872 static int __init init_iommu_all(struct acpi_table_header *table) 1873 { 1874 u8 *p = (u8 *)table, *end = (u8 *)table; 1875 struct ivhd_header *h; 1876 struct amd_iommu *iommu; 1877 int ret; 1878 1879 end += table->length; 1880 p += IVRS_HEADER_LENGTH; 1881 1882 while (p < end) { 1883 h = (struct ivhd_header *)p; 1884 if (*p == amd_iommu_target_ivhd_type) { 1885 1886 DUMP_printk("device: %02x:%02x.%01x cap: %04x " 1887 "seg: %d flags: %01x info %04x\n", 1888 PCI_BUS_NUM(h->devid), PCI_SLOT(h->devid), 1889 PCI_FUNC(h->devid), h->cap_ptr, 1890 h->pci_seg, h->flags, h->info); 1891 DUMP_printk(" mmio-addr: %016llx\n", 1892 h->mmio_phys); 1893 1894 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL); 1895 if (iommu == NULL) 1896 return -ENOMEM; 1897 1898 ret = init_iommu_one(iommu, h, table); 1899 if (ret) 1900 return ret; 1901 } 1902 p += h->length; 1903 1904 } 1905 WARN_ON(p != end); 1906 1907 return 0; 1908 } 1909 1910 static void init_iommu_perf_ctr(struct amd_iommu *iommu) 1911 { 1912 u64 val; 1913 struct pci_dev *pdev = iommu->dev; 1914 1915 if (!iommu_feature(iommu, FEATURE_PC)) 1916 return; 1917 1918 amd_iommu_pc_present = true; 1919 1920 pci_info(pdev, "IOMMU performance counters supported\n"); 1921 1922 val = readl(iommu->mmio_base + MMIO_CNTR_CONF_OFFSET); 1923 iommu->max_banks = (u8) ((val >> 12) & 0x3f); 1924 iommu->max_counters = (u8) ((val >> 7) & 0xf); 1925 1926 return; 1927 } 1928 1929 static ssize_t amd_iommu_show_cap(struct device *dev, 1930 struct device_attribute *attr, 1931 char *buf) 1932 { 1933 struct amd_iommu *iommu = dev_to_amd_iommu(dev); 1934 return sprintf(buf, "%x\n", iommu->cap); 1935 } 1936 static DEVICE_ATTR(cap, S_IRUGO, amd_iommu_show_cap, NULL); 1937 1938 static ssize_t amd_iommu_show_features(struct device *dev, 1939 struct device_attribute *attr, 1940 char *buf) 1941 { 1942 struct amd_iommu *iommu = dev_to_amd_iommu(dev); 1943 return sprintf(buf, "%llx\n", iommu->features); 1944 } 1945 static DEVICE_ATTR(features, S_IRUGO, amd_iommu_show_features, NULL); 1946 1947 static struct attribute *amd_iommu_attrs[] = { 1948 &dev_attr_cap.attr, 1949 &dev_attr_features.attr, 1950 NULL, 1951 }; 1952 1953 static struct attribute_group amd_iommu_group = { 1954 .name = "amd-iommu", 1955 .attrs = amd_iommu_attrs, 1956 }; 1957 1958 static const struct attribute_group *amd_iommu_groups[] = { 1959 &amd_iommu_group, 1960 NULL, 1961 }; 1962 1963 /* 1964 * Note: IVHD 0x11 and 0x40 also contains exact copy 1965 * of the IOMMU Extended Feature Register [MMIO Offset 0030h]. 1966 * Default to EFR in IVHD since it is available sooner (i.e. before PCI init). 1967 */ 1968 static void __init late_iommu_features_init(struct amd_iommu *iommu) 1969 { 1970 u64 features; 1971 1972 if (!(iommu->cap & (1 << IOMMU_CAP_EFR))) 1973 return; 1974 1975 /* read extended feature bits */ 1976 features = readq(iommu->mmio_base + MMIO_EXT_FEATURES); 1977 1978 if (!iommu->features) { 1979 iommu->features = features; 1980 return; 1981 } 1982 1983 /* 1984 * Sanity check and warn if EFR values from 1985 * IVHD and MMIO conflict. 1986 */ 1987 if (features != iommu->features) 1988 pr_warn(FW_WARN "EFR mismatch. Use IVHD EFR (%#llx : %#llx).\n", 1989 features, iommu->features); 1990 } 1991 1992 static int __init iommu_init_pci(struct amd_iommu *iommu) 1993 { 1994 int cap_ptr = iommu->cap_ptr; 1995 int ret; 1996 1997 iommu->dev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(iommu->devid), 1998 iommu->devid & 0xff); 1999 if (!iommu->dev) 2000 return -ENODEV; 2001 2002 /* Prevent binding other PCI device drivers to IOMMU devices */ 2003 iommu->dev->match_driver = false; 2004 2005 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET, 2006 &iommu->cap); 2007 2008 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB))) 2009 amd_iommu_iotlb_sup = false; 2010 2011 late_iommu_features_init(iommu); 2012 2013 if (iommu_feature(iommu, FEATURE_GT)) { 2014 int glxval; 2015 u32 max_pasid; 2016 u64 pasmax; 2017 2018 pasmax = iommu->features & FEATURE_PASID_MASK; 2019 pasmax >>= FEATURE_PASID_SHIFT; 2020 max_pasid = (1 << (pasmax + 1)) - 1; 2021 2022 amd_iommu_max_pasid = min(amd_iommu_max_pasid, max_pasid); 2023 2024 BUG_ON(amd_iommu_max_pasid & ~PASID_MASK); 2025 2026 glxval = iommu->features & FEATURE_GLXVAL_MASK; 2027 glxval >>= FEATURE_GLXVAL_SHIFT; 2028 2029 if (amd_iommu_max_glx_val == -1) 2030 amd_iommu_max_glx_val = glxval; 2031 else 2032 amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval); 2033 } 2034 2035 if (iommu_feature(iommu, FEATURE_GT) && 2036 iommu_feature(iommu, FEATURE_PPR)) { 2037 iommu->is_iommu_v2 = true; 2038 amd_iommu_v2_present = true; 2039 } 2040 2041 if (iommu_feature(iommu, FEATURE_PPR) && alloc_ppr_log(iommu)) 2042 return -ENOMEM; 2043 2044 ret = iommu_init_ga_log(iommu); 2045 if (ret) 2046 return ret; 2047 2048 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE)) { 2049 pr_info("Using strict mode due to virtualization\n"); 2050 iommu_set_dma_strict(); 2051 amd_iommu_np_cache = true; 2052 } 2053 2054 init_iommu_perf_ctr(iommu); 2055 2056 if (is_rd890_iommu(iommu->dev)) { 2057 int i, j; 2058 2059 iommu->root_pdev = 2060 pci_get_domain_bus_and_slot(0, iommu->dev->bus->number, 2061 PCI_DEVFN(0, 0)); 2062 2063 /* 2064 * Some rd890 systems may not be fully reconfigured by the 2065 * BIOS, so it's necessary for us to store this information so 2066 * it can be reprogrammed on resume 2067 */ 2068 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4, 2069 &iommu->stored_addr_lo); 2070 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8, 2071 &iommu->stored_addr_hi); 2072 2073 /* Low bit locks writes to configuration space */ 2074 iommu->stored_addr_lo &= ~1; 2075 2076 for (i = 0; i < 6; i++) 2077 for (j = 0; j < 0x12; j++) 2078 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j); 2079 2080 for (i = 0; i < 0x83; i++) 2081 iommu->stored_l2[i] = iommu_read_l2(iommu, i); 2082 } 2083 2084 amd_iommu_erratum_746_workaround(iommu); 2085 amd_iommu_ats_write_check_workaround(iommu); 2086 2087 ret = iommu_device_sysfs_add(&iommu->iommu, &iommu->dev->dev, 2088 amd_iommu_groups, "ivhd%d", iommu->index); 2089 if (ret) 2090 return ret; 2091 2092 iommu_device_register(&iommu->iommu, &amd_iommu_ops, NULL); 2093 2094 return pci_enable_device(iommu->dev); 2095 } 2096 2097 static void print_iommu_info(void) 2098 { 2099 static const char * const feat_str[] = { 2100 "PreF", "PPR", "X2APIC", "NX", "GT", "[5]", 2101 "IA", "GA", "HE", "PC" 2102 }; 2103 struct amd_iommu *iommu; 2104 2105 for_each_iommu(iommu) { 2106 struct pci_dev *pdev = iommu->dev; 2107 int i; 2108 2109 pci_info(pdev, "Found IOMMU cap 0x%x\n", iommu->cap_ptr); 2110 2111 if (iommu->cap & (1 << IOMMU_CAP_EFR)) { 2112 pr_info("Extended features (%#llx):", iommu->features); 2113 2114 for (i = 0; i < ARRAY_SIZE(feat_str); ++i) { 2115 if (iommu_feature(iommu, (1ULL << i))) 2116 pr_cont(" %s", feat_str[i]); 2117 } 2118 2119 if (iommu->features & FEATURE_GAM_VAPIC) 2120 pr_cont(" GA_vAPIC"); 2121 2122 pr_cont("\n"); 2123 } 2124 } 2125 if (irq_remapping_enabled) { 2126 pr_info("Interrupt remapping enabled\n"); 2127 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) 2128 pr_info("Virtual APIC enabled\n"); 2129 if (amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE) 2130 pr_info("X2APIC enabled\n"); 2131 } 2132 } 2133 2134 static int __init amd_iommu_init_pci(void) 2135 { 2136 struct amd_iommu *iommu; 2137 struct amd_iommu_pci_seg *pci_seg; 2138 int ret; 2139 2140 for_each_iommu(iommu) { 2141 ret = iommu_init_pci(iommu); 2142 if (ret) { 2143 pr_err("IOMMU%d: Failed to initialize IOMMU Hardware (error=%d)!\n", 2144 iommu->index, ret); 2145 goto out; 2146 } 2147 /* Need to setup range after PCI init */ 2148 iommu_set_cwwb_range(iommu); 2149 } 2150 2151 /* 2152 * Order is important here to make sure any unity map requirements are 2153 * fulfilled. The unity mappings are created and written to the device 2154 * table during the amd_iommu_init_api() call. 2155 * 2156 * After that we call init_device_table_dma() to make sure any 2157 * uninitialized DTE will block DMA, and in the end we flush the caches 2158 * of all IOMMUs to make sure the changes to the device table are 2159 * active. 2160 */ 2161 ret = amd_iommu_init_api(); 2162 if (ret) { 2163 pr_err("IOMMU: Failed to initialize IOMMU-API interface (error=%d)!\n", 2164 ret); 2165 goto out; 2166 } 2167 2168 for_each_pci_segment(pci_seg) 2169 init_device_table_dma(pci_seg); 2170 2171 for_each_iommu(iommu) 2172 iommu_flush_all_caches(iommu); 2173 2174 print_iommu_info(); 2175 2176 out: 2177 return ret; 2178 } 2179 2180 /**************************************************************************** 2181 * 2182 * The following functions initialize the MSI interrupts for all IOMMUs 2183 * in the system. It's a bit challenging because there could be multiple 2184 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per 2185 * pci_dev. 2186 * 2187 ****************************************************************************/ 2188 2189 static int iommu_setup_msi(struct amd_iommu *iommu) 2190 { 2191 int r; 2192 2193 r = pci_enable_msi(iommu->dev); 2194 if (r) 2195 return r; 2196 2197 r = request_threaded_irq(iommu->dev->irq, 2198 amd_iommu_int_handler, 2199 amd_iommu_int_thread, 2200 0, "AMD-Vi", 2201 iommu); 2202 2203 if (r) { 2204 pci_disable_msi(iommu->dev); 2205 return r; 2206 } 2207 2208 return 0; 2209 } 2210 2211 union intcapxt { 2212 u64 capxt; 2213 struct { 2214 u64 reserved_0 : 2, 2215 dest_mode_logical : 1, 2216 reserved_1 : 5, 2217 destid_0_23 : 24, 2218 vector : 8, 2219 reserved_2 : 16, 2220 destid_24_31 : 8; 2221 }; 2222 } __attribute__ ((packed)); 2223 2224 2225 static struct irq_chip intcapxt_controller; 2226 2227 static int intcapxt_irqdomain_activate(struct irq_domain *domain, 2228 struct irq_data *irqd, bool reserve) 2229 { 2230 return 0; 2231 } 2232 2233 static void intcapxt_irqdomain_deactivate(struct irq_domain *domain, 2234 struct irq_data *irqd) 2235 { 2236 } 2237 2238 2239 static int intcapxt_irqdomain_alloc(struct irq_domain *domain, unsigned int virq, 2240 unsigned int nr_irqs, void *arg) 2241 { 2242 struct irq_alloc_info *info = arg; 2243 int i, ret; 2244 2245 if (!info || info->type != X86_IRQ_ALLOC_TYPE_AMDVI) 2246 return -EINVAL; 2247 2248 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg); 2249 if (ret < 0) 2250 return ret; 2251 2252 for (i = virq; i < virq + nr_irqs; i++) { 2253 struct irq_data *irqd = irq_domain_get_irq_data(domain, i); 2254 2255 irqd->chip = &intcapxt_controller; 2256 irqd->chip_data = info->data; 2257 __irq_set_handler(i, handle_edge_irq, 0, "edge"); 2258 } 2259 2260 return ret; 2261 } 2262 2263 static void intcapxt_irqdomain_free(struct irq_domain *domain, unsigned int virq, 2264 unsigned int nr_irqs) 2265 { 2266 irq_domain_free_irqs_top(domain, virq, nr_irqs); 2267 } 2268 2269 2270 static void intcapxt_unmask_irq(struct irq_data *irqd) 2271 { 2272 struct amd_iommu *iommu = irqd->chip_data; 2273 struct irq_cfg *cfg = irqd_cfg(irqd); 2274 union intcapxt xt; 2275 2276 xt.capxt = 0ULL; 2277 xt.dest_mode_logical = apic->dest_mode_logical; 2278 xt.vector = cfg->vector; 2279 xt.destid_0_23 = cfg->dest_apicid & GENMASK(23, 0); 2280 xt.destid_24_31 = cfg->dest_apicid >> 24; 2281 2282 /** 2283 * Current IOMMU implementation uses the same IRQ for all 2284 * 3 IOMMU interrupts. 2285 */ 2286 writeq(xt.capxt, iommu->mmio_base + MMIO_INTCAPXT_EVT_OFFSET); 2287 writeq(xt.capxt, iommu->mmio_base + MMIO_INTCAPXT_PPR_OFFSET); 2288 writeq(xt.capxt, iommu->mmio_base + MMIO_INTCAPXT_GALOG_OFFSET); 2289 } 2290 2291 static void intcapxt_mask_irq(struct irq_data *irqd) 2292 { 2293 struct amd_iommu *iommu = irqd->chip_data; 2294 2295 writeq(0, iommu->mmio_base + MMIO_INTCAPXT_EVT_OFFSET); 2296 writeq(0, iommu->mmio_base + MMIO_INTCAPXT_PPR_OFFSET); 2297 writeq(0, iommu->mmio_base + MMIO_INTCAPXT_GALOG_OFFSET); 2298 } 2299 2300 2301 static int intcapxt_set_affinity(struct irq_data *irqd, 2302 const struct cpumask *mask, bool force) 2303 { 2304 struct irq_data *parent = irqd->parent_data; 2305 int ret; 2306 2307 ret = parent->chip->irq_set_affinity(parent, mask, force); 2308 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE) 2309 return ret; 2310 return 0; 2311 } 2312 2313 static int intcapxt_set_wake(struct irq_data *irqd, unsigned int on) 2314 { 2315 return on ? -EOPNOTSUPP : 0; 2316 } 2317 2318 static struct irq_chip intcapxt_controller = { 2319 .name = "IOMMU-MSI", 2320 .irq_unmask = intcapxt_unmask_irq, 2321 .irq_mask = intcapxt_mask_irq, 2322 .irq_ack = irq_chip_ack_parent, 2323 .irq_retrigger = irq_chip_retrigger_hierarchy, 2324 .irq_set_affinity = intcapxt_set_affinity, 2325 .irq_set_wake = intcapxt_set_wake, 2326 .flags = IRQCHIP_MASK_ON_SUSPEND, 2327 }; 2328 2329 static const struct irq_domain_ops intcapxt_domain_ops = { 2330 .alloc = intcapxt_irqdomain_alloc, 2331 .free = intcapxt_irqdomain_free, 2332 .activate = intcapxt_irqdomain_activate, 2333 .deactivate = intcapxt_irqdomain_deactivate, 2334 }; 2335 2336 2337 static struct irq_domain *iommu_irqdomain; 2338 2339 static struct irq_domain *iommu_get_irqdomain(void) 2340 { 2341 struct fwnode_handle *fn; 2342 2343 /* No need for locking here (yet) as the init is single-threaded */ 2344 if (iommu_irqdomain) 2345 return iommu_irqdomain; 2346 2347 fn = irq_domain_alloc_named_fwnode("AMD-Vi-MSI"); 2348 if (!fn) 2349 return NULL; 2350 2351 iommu_irqdomain = irq_domain_create_hierarchy(x86_vector_domain, 0, 0, 2352 fn, &intcapxt_domain_ops, 2353 NULL); 2354 if (!iommu_irqdomain) 2355 irq_domain_free_fwnode(fn); 2356 2357 return iommu_irqdomain; 2358 } 2359 2360 static int iommu_setup_intcapxt(struct amd_iommu *iommu) 2361 { 2362 struct irq_domain *domain; 2363 struct irq_alloc_info info; 2364 int irq, ret; 2365 2366 domain = iommu_get_irqdomain(); 2367 if (!domain) 2368 return -ENXIO; 2369 2370 init_irq_alloc_info(&info, NULL); 2371 info.type = X86_IRQ_ALLOC_TYPE_AMDVI; 2372 info.data = iommu; 2373 2374 irq = irq_domain_alloc_irqs(domain, 1, NUMA_NO_NODE, &info); 2375 if (irq < 0) { 2376 irq_domain_remove(domain); 2377 return irq; 2378 } 2379 2380 ret = request_threaded_irq(irq, amd_iommu_int_handler, 2381 amd_iommu_int_thread, 0, "AMD-Vi", iommu); 2382 if (ret) { 2383 irq_domain_free_irqs(irq, 1); 2384 irq_domain_remove(domain); 2385 return ret; 2386 } 2387 2388 return 0; 2389 } 2390 2391 static int iommu_init_irq(struct amd_iommu *iommu) 2392 { 2393 int ret; 2394 2395 if (iommu->int_enabled) 2396 goto enable_faults; 2397 2398 if (amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE) 2399 ret = iommu_setup_intcapxt(iommu); 2400 else if (iommu->dev->msi_cap) 2401 ret = iommu_setup_msi(iommu); 2402 else 2403 ret = -ENODEV; 2404 2405 if (ret) 2406 return ret; 2407 2408 iommu->int_enabled = true; 2409 enable_faults: 2410 2411 if (amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE) 2412 iommu_feature_enable(iommu, CONTROL_INTCAPXT_EN); 2413 2414 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN); 2415 2416 if (iommu->ppr_log != NULL) 2417 iommu_feature_enable(iommu, CONTROL_PPRINT_EN); 2418 2419 iommu_ga_log_enable(iommu); 2420 2421 return 0; 2422 } 2423 2424 /**************************************************************************** 2425 * 2426 * The next functions belong to the third pass of parsing the ACPI 2427 * table. In this last pass the memory mapping requirements are 2428 * gathered (like exclusion and unity mapping ranges). 2429 * 2430 ****************************************************************************/ 2431 2432 static void __init free_unity_maps(void) 2433 { 2434 struct unity_map_entry *entry, *next; 2435 struct amd_iommu_pci_seg *p, *pci_seg; 2436 2437 for_each_pci_segment_safe(pci_seg, p) { 2438 list_for_each_entry_safe(entry, next, &pci_seg->unity_map, list) { 2439 list_del(&entry->list); 2440 kfree(entry); 2441 } 2442 } 2443 } 2444 2445 /* called for unity map ACPI definition */ 2446 static int __init init_unity_map_range(struct ivmd_header *m, 2447 struct acpi_table_header *ivrs_base) 2448 { 2449 struct unity_map_entry *e = NULL; 2450 struct amd_iommu_pci_seg *pci_seg; 2451 char *s; 2452 2453 pci_seg = get_pci_segment(m->pci_seg, ivrs_base); 2454 if (pci_seg == NULL) 2455 return -ENOMEM; 2456 2457 e = kzalloc(sizeof(*e), GFP_KERNEL); 2458 if (e == NULL) 2459 return -ENOMEM; 2460 2461 switch (m->type) { 2462 default: 2463 kfree(e); 2464 return 0; 2465 case ACPI_IVMD_TYPE: 2466 s = "IVMD_TYPEi\t\t\t"; 2467 e->devid_start = e->devid_end = m->devid; 2468 break; 2469 case ACPI_IVMD_TYPE_ALL: 2470 s = "IVMD_TYPE_ALL\t\t"; 2471 e->devid_start = 0; 2472 e->devid_end = amd_iommu_last_bdf; 2473 break; 2474 case ACPI_IVMD_TYPE_RANGE: 2475 s = "IVMD_TYPE_RANGE\t\t"; 2476 e->devid_start = m->devid; 2477 e->devid_end = m->aux; 2478 break; 2479 } 2480 e->address_start = PAGE_ALIGN(m->range_start); 2481 e->address_end = e->address_start + PAGE_ALIGN(m->range_length); 2482 e->prot = m->flags >> 1; 2483 2484 /* 2485 * Treat per-device exclusion ranges as r/w unity-mapped regions 2486 * since some buggy BIOSes might lead to the overwritten exclusion 2487 * range (exclusion_start and exclusion_length members). This 2488 * happens when there are multiple exclusion ranges (IVMD entries) 2489 * defined in ACPI table. 2490 */ 2491 if (m->flags & IVMD_FLAG_EXCL_RANGE) 2492 e->prot = (IVMD_FLAG_IW | IVMD_FLAG_IR) >> 1; 2493 2494 DUMP_printk("%s devid_start: %04x:%02x:%02x.%x devid_end: " 2495 "%04x:%02x:%02x.%x range_start: %016llx range_end: %016llx" 2496 " flags: %x\n", s, m->pci_seg, 2497 PCI_BUS_NUM(e->devid_start), PCI_SLOT(e->devid_start), 2498 PCI_FUNC(e->devid_start), m->pci_seg, 2499 PCI_BUS_NUM(e->devid_end), 2500 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end), 2501 e->address_start, e->address_end, m->flags); 2502 2503 list_add_tail(&e->list, &pci_seg->unity_map); 2504 2505 return 0; 2506 } 2507 2508 /* iterates over all memory definitions we find in the ACPI table */ 2509 static int __init init_memory_definitions(struct acpi_table_header *table) 2510 { 2511 u8 *p = (u8 *)table, *end = (u8 *)table; 2512 struct ivmd_header *m; 2513 2514 end += table->length; 2515 p += IVRS_HEADER_LENGTH; 2516 2517 while (p < end) { 2518 m = (struct ivmd_header *)p; 2519 if (m->flags & (IVMD_FLAG_UNITY_MAP | IVMD_FLAG_EXCL_RANGE)) 2520 init_unity_map_range(m, table); 2521 2522 p += m->length; 2523 } 2524 2525 return 0; 2526 } 2527 2528 /* 2529 * Init the device table to not allow DMA access for devices 2530 */ 2531 static void init_device_table_dma(struct amd_iommu_pci_seg *pci_seg) 2532 { 2533 u32 devid; 2534 struct dev_table_entry *dev_table = pci_seg->dev_table; 2535 2536 if (dev_table == NULL) 2537 return; 2538 2539 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) { 2540 __set_dev_entry_bit(dev_table, devid, DEV_ENTRY_VALID); 2541 __set_dev_entry_bit(dev_table, devid, DEV_ENTRY_TRANSLATION); 2542 } 2543 } 2544 2545 static void __init uninit_device_table_dma(struct amd_iommu_pci_seg *pci_seg) 2546 { 2547 u32 devid; 2548 struct dev_table_entry *dev_table = pci_seg->dev_table; 2549 2550 if (dev_table == NULL) 2551 return; 2552 2553 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) { 2554 dev_table[devid].data[0] = 0ULL; 2555 dev_table[devid].data[1] = 0ULL; 2556 } 2557 } 2558 2559 static void init_device_table(void) 2560 { 2561 struct amd_iommu_pci_seg *pci_seg; 2562 u32 devid; 2563 2564 if (!amd_iommu_irq_remap) 2565 return; 2566 2567 for_each_pci_segment(pci_seg) { 2568 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) 2569 __set_dev_entry_bit(pci_seg->dev_table, 2570 devid, DEV_ENTRY_IRQ_TBL_EN); 2571 } 2572 } 2573 2574 static void iommu_init_flags(struct amd_iommu *iommu) 2575 { 2576 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ? 2577 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) : 2578 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN); 2579 2580 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ? 2581 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) : 2582 iommu_feature_disable(iommu, CONTROL_PASSPW_EN); 2583 2584 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ? 2585 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) : 2586 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN); 2587 2588 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ? 2589 iommu_feature_enable(iommu, CONTROL_ISOC_EN) : 2590 iommu_feature_disable(iommu, CONTROL_ISOC_EN); 2591 2592 /* 2593 * make IOMMU memory accesses cache coherent 2594 */ 2595 iommu_feature_enable(iommu, CONTROL_COHERENT_EN); 2596 2597 /* Set IOTLB invalidation timeout to 1s */ 2598 iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S); 2599 } 2600 2601 static void iommu_apply_resume_quirks(struct amd_iommu *iommu) 2602 { 2603 int i, j; 2604 u32 ioc_feature_control; 2605 struct pci_dev *pdev = iommu->root_pdev; 2606 2607 /* RD890 BIOSes may not have completely reconfigured the iommu */ 2608 if (!is_rd890_iommu(iommu->dev) || !pdev) 2609 return; 2610 2611 /* 2612 * First, we need to ensure that the iommu is enabled. This is 2613 * controlled by a register in the northbridge 2614 */ 2615 2616 /* Select Northbridge indirect register 0x75 and enable writing */ 2617 pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7)); 2618 pci_read_config_dword(pdev, 0x64, &ioc_feature_control); 2619 2620 /* Enable the iommu */ 2621 if (!(ioc_feature_control & 0x1)) 2622 pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1); 2623 2624 /* Restore the iommu BAR */ 2625 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, 2626 iommu->stored_addr_lo); 2627 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8, 2628 iommu->stored_addr_hi); 2629 2630 /* Restore the l1 indirect regs for each of the 6 l1s */ 2631 for (i = 0; i < 6; i++) 2632 for (j = 0; j < 0x12; j++) 2633 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]); 2634 2635 /* Restore the l2 indirect regs */ 2636 for (i = 0; i < 0x83; i++) 2637 iommu_write_l2(iommu, i, iommu->stored_l2[i]); 2638 2639 /* Lock PCI setup registers */ 2640 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, 2641 iommu->stored_addr_lo | 1); 2642 } 2643 2644 static void iommu_enable_ga(struct amd_iommu *iommu) 2645 { 2646 #ifdef CONFIG_IRQ_REMAP 2647 switch (amd_iommu_guest_ir) { 2648 case AMD_IOMMU_GUEST_IR_VAPIC: 2649 iommu_feature_enable(iommu, CONTROL_GAM_EN); 2650 fallthrough; 2651 case AMD_IOMMU_GUEST_IR_LEGACY_GA: 2652 iommu_feature_enable(iommu, CONTROL_GA_EN); 2653 iommu->irte_ops = &irte_128_ops; 2654 break; 2655 default: 2656 iommu->irte_ops = &irte_32_ops; 2657 break; 2658 } 2659 #endif 2660 } 2661 2662 static void early_enable_iommu(struct amd_iommu *iommu) 2663 { 2664 iommu_disable(iommu); 2665 iommu_init_flags(iommu); 2666 iommu_set_device_table(iommu); 2667 iommu_enable_command_buffer(iommu); 2668 iommu_enable_event_buffer(iommu); 2669 iommu_set_exclusion_range(iommu); 2670 iommu_enable_ga(iommu); 2671 iommu_enable_xt(iommu); 2672 iommu_enable(iommu); 2673 iommu_flush_all_caches(iommu); 2674 } 2675 2676 /* 2677 * This function finally enables all IOMMUs found in the system after 2678 * they have been initialized. 2679 * 2680 * Or if in kdump kernel and IOMMUs are all pre-enabled, try to copy 2681 * the old content of device table entries. Not this case or copy failed, 2682 * just continue as normal kernel does. 2683 */ 2684 static void early_enable_iommus(void) 2685 { 2686 struct amd_iommu *iommu; 2687 struct amd_iommu_pci_seg *pci_seg; 2688 2689 if (!copy_device_table()) { 2690 /* 2691 * If come here because of failure in copying device table from old 2692 * kernel with all IOMMUs enabled, print error message and try to 2693 * free allocated old_dev_tbl_cpy. 2694 */ 2695 if (amd_iommu_pre_enabled) 2696 pr_err("Failed to copy DEV table from previous kernel.\n"); 2697 2698 for_each_pci_segment(pci_seg) { 2699 if (pci_seg->old_dev_tbl_cpy != NULL) { 2700 free_pages((unsigned long)pci_seg->old_dev_tbl_cpy, 2701 get_order(pci_seg->dev_table_size)); 2702 pci_seg->old_dev_tbl_cpy = NULL; 2703 } 2704 } 2705 2706 for_each_iommu(iommu) { 2707 clear_translation_pre_enabled(iommu); 2708 early_enable_iommu(iommu); 2709 } 2710 } else { 2711 pr_info("Copied DEV table from previous kernel.\n"); 2712 2713 for_each_pci_segment(pci_seg) { 2714 free_pages((unsigned long)pci_seg->dev_table, 2715 get_order(pci_seg->dev_table_size)); 2716 pci_seg->dev_table = pci_seg->old_dev_tbl_cpy; 2717 } 2718 2719 for_each_iommu(iommu) { 2720 iommu_disable_command_buffer(iommu); 2721 iommu_disable_event_buffer(iommu); 2722 iommu_enable_command_buffer(iommu); 2723 iommu_enable_event_buffer(iommu); 2724 iommu_enable_ga(iommu); 2725 iommu_enable_xt(iommu); 2726 iommu_set_device_table(iommu); 2727 iommu_flush_all_caches(iommu); 2728 } 2729 } 2730 2731 #ifdef CONFIG_IRQ_REMAP 2732 /* 2733 * Note: We have already checked GASup from IVRS table. 2734 * Now, we need to make sure that GAMSup is set. 2735 */ 2736 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) && 2737 !check_feature_on_all_iommus(FEATURE_GAM_VAPIC)) 2738 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA; 2739 2740 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) 2741 amd_iommu_irq_ops.capability |= (1 << IRQ_POSTING_CAP); 2742 #endif 2743 } 2744 2745 static void enable_iommus_v2(void) 2746 { 2747 struct amd_iommu *iommu; 2748 2749 for_each_iommu(iommu) { 2750 iommu_enable_ppr_log(iommu); 2751 iommu_enable_gt(iommu); 2752 } 2753 } 2754 2755 static void enable_iommus(void) 2756 { 2757 early_enable_iommus(); 2758 2759 enable_iommus_v2(); 2760 } 2761 2762 static void disable_iommus(void) 2763 { 2764 struct amd_iommu *iommu; 2765 2766 for_each_iommu(iommu) 2767 iommu_disable(iommu); 2768 2769 #ifdef CONFIG_IRQ_REMAP 2770 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) 2771 amd_iommu_irq_ops.capability &= ~(1 << IRQ_POSTING_CAP); 2772 #endif 2773 } 2774 2775 /* 2776 * Suspend/Resume support 2777 * disable suspend until real resume implemented 2778 */ 2779 2780 static void amd_iommu_resume(void) 2781 { 2782 struct amd_iommu *iommu; 2783 2784 for_each_iommu(iommu) 2785 iommu_apply_resume_quirks(iommu); 2786 2787 /* re-load the hardware */ 2788 enable_iommus(); 2789 2790 amd_iommu_enable_interrupts(); 2791 } 2792 2793 static int amd_iommu_suspend(void) 2794 { 2795 /* disable IOMMUs to go out of the way for BIOS */ 2796 disable_iommus(); 2797 2798 return 0; 2799 } 2800 2801 static struct syscore_ops amd_iommu_syscore_ops = { 2802 .suspend = amd_iommu_suspend, 2803 .resume = amd_iommu_resume, 2804 }; 2805 2806 static void __init free_iommu_resources(void) 2807 { 2808 kmem_cache_destroy(amd_iommu_irq_cache); 2809 amd_iommu_irq_cache = NULL; 2810 2811 free_pages((unsigned long)amd_iommu_alias_table, 2812 get_order(alias_table_size)); 2813 amd_iommu_alias_table = NULL; 2814 2815 free_pages((unsigned long)amd_iommu_dev_table, 2816 get_order(dev_table_size)); 2817 amd_iommu_dev_table = NULL; 2818 2819 free_iommu_all(); 2820 free_pci_segments(); 2821 } 2822 2823 /* SB IOAPIC is always on this device in AMD systems */ 2824 #define IOAPIC_SB_DEVID ((0x00 << 8) | PCI_DEVFN(0x14, 0)) 2825 2826 static bool __init check_ioapic_information(void) 2827 { 2828 const char *fw_bug = FW_BUG; 2829 bool ret, has_sb_ioapic; 2830 int idx; 2831 2832 has_sb_ioapic = false; 2833 ret = false; 2834 2835 /* 2836 * If we have map overrides on the kernel command line the 2837 * messages in this function might not describe firmware bugs 2838 * anymore - so be careful 2839 */ 2840 if (cmdline_maps) 2841 fw_bug = ""; 2842 2843 for (idx = 0; idx < nr_ioapics; idx++) { 2844 int devid, id = mpc_ioapic_id(idx); 2845 2846 devid = get_ioapic_devid(id); 2847 if (devid < 0) { 2848 pr_err("%s: IOAPIC[%d] not in IVRS table\n", 2849 fw_bug, id); 2850 ret = false; 2851 } else if (devid == IOAPIC_SB_DEVID) { 2852 has_sb_ioapic = true; 2853 ret = true; 2854 } 2855 } 2856 2857 if (!has_sb_ioapic) { 2858 /* 2859 * We expect the SB IOAPIC to be listed in the IVRS 2860 * table. The system timer is connected to the SB IOAPIC 2861 * and if we don't have it in the list the system will 2862 * panic at boot time. This situation usually happens 2863 * when the BIOS is buggy and provides us the wrong 2864 * device id for the IOAPIC in the system. 2865 */ 2866 pr_err("%s: No southbridge IOAPIC found\n", fw_bug); 2867 } 2868 2869 if (!ret) 2870 pr_err("Disabling interrupt remapping\n"); 2871 2872 return ret; 2873 } 2874 2875 static void __init free_dma_resources(void) 2876 { 2877 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap, 2878 get_order(MAX_DOMAIN_ID/8)); 2879 amd_iommu_pd_alloc_bitmap = NULL; 2880 2881 free_unity_maps(); 2882 } 2883 2884 static void __init ivinfo_init(void *ivrs) 2885 { 2886 amd_iommu_ivinfo = *((u32 *)(ivrs + IOMMU_IVINFO_OFFSET)); 2887 } 2888 2889 /* 2890 * This is the hardware init function for AMD IOMMU in the system. 2891 * This function is called either from amd_iommu_init or from the interrupt 2892 * remapping setup code. 2893 * 2894 * This function basically parses the ACPI table for AMD IOMMU (IVRS) 2895 * four times: 2896 * 2897 * 1 pass) Discover the most comprehensive IVHD type to use. 2898 * 2899 * 2 pass) Find the highest PCI device id the driver has to handle. 2900 * Upon this information the size of the data structures is 2901 * determined that needs to be allocated. 2902 * 2903 * 3 pass) Initialize the data structures just allocated with the 2904 * information in the ACPI table about available AMD IOMMUs 2905 * in the system. It also maps the PCI devices in the 2906 * system to specific IOMMUs 2907 * 2908 * 4 pass) After the basic data structures are allocated and 2909 * initialized we update them with information about memory 2910 * remapping requirements parsed out of the ACPI table in 2911 * this last pass. 2912 * 2913 * After everything is set up the IOMMUs are enabled and the necessary 2914 * hotplug and suspend notifiers are registered. 2915 */ 2916 static int __init early_amd_iommu_init(void) 2917 { 2918 struct acpi_table_header *ivrs_base; 2919 int remap_cache_sz, ret; 2920 acpi_status status; 2921 2922 if (!amd_iommu_detected) 2923 return -ENODEV; 2924 2925 status = acpi_get_table("IVRS", 0, &ivrs_base); 2926 if (status == AE_NOT_FOUND) 2927 return -ENODEV; 2928 else if (ACPI_FAILURE(status)) { 2929 const char *err = acpi_format_exception(status); 2930 pr_err("IVRS table error: %s\n", err); 2931 return -EINVAL; 2932 } 2933 2934 /* 2935 * Validate checksum here so we don't need to do it when 2936 * we actually parse the table 2937 */ 2938 ret = check_ivrs_checksum(ivrs_base); 2939 if (ret) 2940 goto out; 2941 2942 ivinfo_init(ivrs_base); 2943 2944 amd_iommu_target_ivhd_type = get_highest_supported_ivhd_type(ivrs_base); 2945 DUMP_printk("Using IVHD type %#x\n", amd_iommu_target_ivhd_type); 2946 2947 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE); 2948 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE); 2949 2950 /* Device table - directly used by all IOMMUs */ 2951 ret = -ENOMEM; 2952 amd_iommu_dev_table = (void *)__get_free_pages( 2953 GFP_KERNEL | __GFP_ZERO | GFP_DMA32, 2954 get_order(dev_table_size)); 2955 if (amd_iommu_dev_table == NULL) 2956 goto out; 2957 2958 /* 2959 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the 2960 * IOMMU see for that device 2961 */ 2962 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL, 2963 get_order(alias_table_size)); 2964 if (amd_iommu_alias_table == NULL) 2965 goto out; 2966 2967 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages( 2968 GFP_KERNEL | __GFP_ZERO, 2969 get_order(MAX_DOMAIN_ID/8)); 2970 if (amd_iommu_pd_alloc_bitmap == NULL) 2971 goto out; 2972 2973 /* 2974 * never allocate domain 0 because its used as the non-allocated and 2975 * error value placeholder 2976 */ 2977 __set_bit(0, amd_iommu_pd_alloc_bitmap); 2978 2979 /* 2980 * now the data structures are allocated and basically initialized 2981 * start the real acpi table scan 2982 */ 2983 ret = init_iommu_all(ivrs_base); 2984 if (ret) 2985 goto out; 2986 2987 /* Disable any previously enabled IOMMUs */ 2988 if (!is_kdump_kernel() || amd_iommu_disabled) 2989 disable_iommus(); 2990 2991 if (amd_iommu_irq_remap) 2992 amd_iommu_irq_remap = check_ioapic_information(); 2993 2994 if (amd_iommu_irq_remap) { 2995 struct amd_iommu_pci_seg *pci_seg; 2996 /* 2997 * Interrupt remapping enabled, create kmem_cache for the 2998 * remapping tables. 2999 */ 3000 ret = -ENOMEM; 3001 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir)) 3002 remap_cache_sz = MAX_IRQS_PER_TABLE * sizeof(u32); 3003 else 3004 remap_cache_sz = MAX_IRQS_PER_TABLE * (sizeof(u64) * 2); 3005 amd_iommu_irq_cache = kmem_cache_create("irq_remap_cache", 3006 remap_cache_sz, 3007 DTE_INTTAB_ALIGNMENT, 3008 0, NULL); 3009 if (!amd_iommu_irq_cache) 3010 goto out; 3011 3012 for_each_pci_segment(pci_seg) { 3013 if (alloc_irq_lookup_table(pci_seg)) 3014 goto out; 3015 } 3016 } 3017 3018 ret = init_memory_definitions(ivrs_base); 3019 if (ret) 3020 goto out; 3021 3022 /* init the device table */ 3023 init_device_table(); 3024 3025 out: 3026 /* Don't leak any ACPI memory */ 3027 acpi_put_table(ivrs_base); 3028 3029 return ret; 3030 } 3031 3032 static int amd_iommu_enable_interrupts(void) 3033 { 3034 struct amd_iommu *iommu; 3035 int ret = 0; 3036 3037 for_each_iommu(iommu) { 3038 ret = iommu_init_irq(iommu); 3039 if (ret) 3040 goto out; 3041 } 3042 3043 out: 3044 return ret; 3045 } 3046 3047 static bool __init detect_ivrs(void) 3048 { 3049 struct acpi_table_header *ivrs_base; 3050 acpi_status status; 3051 int i; 3052 3053 status = acpi_get_table("IVRS", 0, &ivrs_base); 3054 if (status == AE_NOT_FOUND) 3055 return false; 3056 else if (ACPI_FAILURE(status)) { 3057 const char *err = acpi_format_exception(status); 3058 pr_err("IVRS table error: %s\n", err); 3059 return false; 3060 } 3061 3062 acpi_put_table(ivrs_base); 3063 3064 if (amd_iommu_force_enable) 3065 goto out; 3066 3067 /* Don't use IOMMU if there is Stoney Ridge graphics */ 3068 for (i = 0; i < 32; i++) { 3069 u32 pci_id; 3070 3071 pci_id = read_pci_config(0, i, 0, 0); 3072 if ((pci_id & 0xffff) == 0x1002 && (pci_id >> 16) == 0x98e4) { 3073 pr_info("Disable IOMMU on Stoney Ridge\n"); 3074 return false; 3075 } 3076 } 3077 3078 out: 3079 /* Make sure ACS will be enabled during PCI probe */ 3080 pci_request_acs(); 3081 3082 return true; 3083 } 3084 3085 /**************************************************************************** 3086 * 3087 * AMD IOMMU Initialization State Machine 3088 * 3089 ****************************************************************************/ 3090 3091 static int __init state_next(void) 3092 { 3093 int ret = 0; 3094 3095 switch (init_state) { 3096 case IOMMU_START_STATE: 3097 if (!detect_ivrs()) { 3098 init_state = IOMMU_NOT_FOUND; 3099 ret = -ENODEV; 3100 } else { 3101 init_state = IOMMU_IVRS_DETECTED; 3102 } 3103 break; 3104 case IOMMU_IVRS_DETECTED: 3105 if (amd_iommu_disabled) { 3106 init_state = IOMMU_CMDLINE_DISABLED; 3107 ret = -EINVAL; 3108 } else { 3109 ret = early_amd_iommu_init(); 3110 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_ACPI_FINISHED; 3111 } 3112 break; 3113 case IOMMU_ACPI_FINISHED: 3114 early_enable_iommus(); 3115 x86_platform.iommu_shutdown = disable_iommus; 3116 init_state = IOMMU_ENABLED; 3117 break; 3118 case IOMMU_ENABLED: 3119 register_syscore_ops(&amd_iommu_syscore_ops); 3120 ret = amd_iommu_init_pci(); 3121 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT; 3122 enable_iommus_v2(); 3123 break; 3124 case IOMMU_PCI_INIT: 3125 ret = amd_iommu_enable_interrupts(); 3126 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_INTERRUPTS_EN; 3127 break; 3128 case IOMMU_INTERRUPTS_EN: 3129 init_state = IOMMU_INITIALIZED; 3130 break; 3131 case IOMMU_INITIALIZED: 3132 /* Nothing to do */ 3133 break; 3134 case IOMMU_NOT_FOUND: 3135 case IOMMU_INIT_ERROR: 3136 case IOMMU_CMDLINE_DISABLED: 3137 /* Error states => do nothing */ 3138 ret = -EINVAL; 3139 break; 3140 default: 3141 /* Unknown state */ 3142 BUG(); 3143 } 3144 3145 if (ret) { 3146 free_dma_resources(); 3147 if (!irq_remapping_enabled) { 3148 disable_iommus(); 3149 free_iommu_resources(); 3150 } else { 3151 struct amd_iommu *iommu; 3152 struct amd_iommu_pci_seg *pci_seg; 3153 3154 for_each_pci_segment(pci_seg) 3155 uninit_device_table_dma(pci_seg); 3156 3157 for_each_iommu(iommu) 3158 iommu_flush_all_caches(iommu); 3159 } 3160 } 3161 return ret; 3162 } 3163 3164 static int __init iommu_go_to_state(enum iommu_init_state state) 3165 { 3166 int ret = -EINVAL; 3167 3168 while (init_state != state) { 3169 if (init_state == IOMMU_NOT_FOUND || 3170 init_state == IOMMU_INIT_ERROR || 3171 init_state == IOMMU_CMDLINE_DISABLED) 3172 break; 3173 ret = state_next(); 3174 } 3175 3176 return ret; 3177 } 3178 3179 #ifdef CONFIG_IRQ_REMAP 3180 int __init amd_iommu_prepare(void) 3181 { 3182 int ret; 3183 3184 amd_iommu_irq_remap = true; 3185 3186 ret = iommu_go_to_state(IOMMU_ACPI_FINISHED); 3187 if (ret) { 3188 amd_iommu_irq_remap = false; 3189 return ret; 3190 } 3191 3192 return amd_iommu_irq_remap ? 0 : -ENODEV; 3193 } 3194 3195 int __init amd_iommu_enable(void) 3196 { 3197 int ret; 3198 3199 ret = iommu_go_to_state(IOMMU_ENABLED); 3200 if (ret) 3201 return ret; 3202 3203 irq_remapping_enabled = 1; 3204 return amd_iommu_xt_mode; 3205 } 3206 3207 void amd_iommu_disable(void) 3208 { 3209 amd_iommu_suspend(); 3210 } 3211 3212 int amd_iommu_reenable(int mode) 3213 { 3214 amd_iommu_resume(); 3215 3216 return 0; 3217 } 3218 3219 int __init amd_iommu_enable_faulting(void) 3220 { 3221 /* We enable MSI later when PCI is initialized */ 3222 return 0; 3223 } 3224 #endif 3225 3226 /* 3227 * This is the core init function for AMD IOMMU hardware in the system. 3228 * This function is called from the generic x86 DMA layer initialization 3229 * code. 3230 */ 3231 static int __init amd_iommu_init(void) 3232 { 3233 struct amd_iommu *iommu; 3234 int ret; 3235 3236 ret = iommu_go_to_state(IOMMU_INITIALIZED); 3237 #ifdef CONFIG_GART_IOMMU 3238 if (ret && list_empty(&amd_iommu_list)) { 3239 /* 3240 * We failed to initialize the AMD IOMMU - try fallback 3241 * to GART if possible. 3242 */ 3243 gart_iommu_init(); 3244 } 3245 #endif 3246 3247 for_each_iommu(iommu) 3248 amd_iommu_debugfs_setup(iommu); 3249 3250 return ret; 3251 } 3252 3253 static bool amd_iommu_sme_check(void) 3254 { 3255 if (!cc_platform_has(CC_ATTR_HOST_MEM_ENCRYPT) || 3256 (boot_cpu_data.x86 != 0x17)) 3257 return true; 3258 3259 /* For Fam17h, a specific level of support is required */ 3260 if (boot_cpu_data.microcode >= 0x08001205) 3261 return true; 3262 3263 if ((boot_cpu_data.microcode >= 0x08001126) && 3264 (boot_cpu_data.microcode <= 0x080011ff)) 3265 return true; 3266 3267 pr_notice("IOMMU not currently supported when SME is active\n"); 3268 3269 return false; 3270 } 3271 3272 /**************************************************************************** 3273 * 3274 * Early detect code. This code runs at IOMMU detection time in the DMA 3275 * layer. It just looks if there is an IVRS ACPI table to detect AMD 3276 * IOMMUs 3277 * 3278 ****************************************************************************/ 3279 int __init amd_iommu_detect(void) 3280 { 3281 int ret; 3282 3283 if (no_iommu || (iommu_detected && !gart_iommu_aperture)) 3284 return -ENODEV; 3285 3286 if (!amd_iommu_sme_check()) 3287 return -ENODEV; 3288 3289 ret = iommu_go_to_state(IOMMU_IVRS_DETECTED); 3290 if (ret) 3291 return ret; 3292 3293 amd_iommu_detected = true; 3294 iommu_detected = 1; 3295 x86_init.iommu.iommu_init = amd_iommu_init; 3296 3297 return 1; 3298 } 3299 3300 /**************************************************************************** 3301 * 3302 * Parsing functions for the AMD IOMMU specific kernel command line 3303 * options. 3304 * 3305 ****************************************************************************/ 3306 3307 static int __init parse_amd_iommu_dump(char *str) 3308 { 3309 amd_iommu_dump = true; 3310 3311 return 1; 3312 } 3313 3314 static int __init parse_amd_iommu_intr(char *str) 3315 { 3316 for (; *str; ++str) { 3317 if (strncmp(str, "legacy", 6) == 0) { 3318 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA; 3319 break; 3320 } 3321 if (strncmp(str, "vapic", 5) == 0) { 3322 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC; 3323 break; 3324 } 3325 } 3326 return 1; 3327 } 3328 3329 static int __init parse_amd_iommu_options(char *str) 3330 { 3331 for (; *str; ++str) { 3332 if (strncmp(str, "fullflush", 9) == 0) { 3333 pr_warn("amd_iommu=fullflush deprecated; use iommu.strict=1 instead\n"); 3334 iommu_set_dma_strict(); 3335 } 3336 if (strncmp(str, "force_enable", 12) == 0) 3337 amd_iommu_force_enable = true; 3338 if (strncmp(str, "off", 3) == 0) 3339 amd_iommu_disabled = true; 3340 if (strncmp(str, "force_isolation", 15) == 0) 3341 amd_iommu_force_isolation = true; 3342 } 3343 3344 return 1; 3345 } 3346 3347 static int __init parse_ivrs_ioapic(char *str) 3348 { 3349 unsigned int bus, dev, fn; 3350 int ret, id, i; 3351 u16 devid; 3352 3353 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn); 3354 3355 if (ret != 4) { 3356 pr_err("Invalid command line: ivrs_ioapic%s\n", str); 3357 return 1; 3358 } 3359 3360 if (early_ioapic_map_size == EARLY_MAP_SIZE) { 3361 pr_err("Early IOAPIC map overflow - ignoring ivrs_ioapic%s\n", 3362 str); 3363 return 1; 3364 } 3365 3366 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7); 3367 3368 cmdline_maps = true; 3369 i = early_ioapic_map_size++; 3370 early_ioapic_map[i].id = id; 3371 early_ioapic_map[i].devid = devid; 3372 early_ioapic_map[i].cmd_line = true; 3373 3374 return 1; 3375 } 3376 3377 static int __init parse_ivrs_hpet(char *str) 3378 { 3379 unsigned int bus, dev, fn; 3380 int ret, id, i; 3381 u16 devid; 3382 3383 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn); 3384 3385 if (ret != 4) { 3386 pr_err("Invalid command line: ivrs_hpet%s\n", str); 3387 return 1; 3388 } 3389 3390 if (early_hpet_map_size == EARLY_MAP_SIZE) { 3391 pr_err("Early HPET map overflow - ignoring ivrs_hpet%s\n", 3392 str); 3393 return 1; 3394 } 3395 3396 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7); 3397 3398 cmdline_maps = true; 3399 i = early_hpet_map_size++; 3400 early_hpet_map[i].id = id; 3401 early_hpet_map[i].devid = devid; 3402 early_hpet_map[i].cmd_line = true; 3403 3404 return 1; 3405 } 3406 3407 static int __init parse_ivrs_acpihid(char *str) 3408 { 3409 u32 bus, dev, fn; 3410 char *hid, *uid, *p; 3411 char acpiid[ACPIHID_UID_LEN + ACPIHID_HID_LEN] = {0}; 3412 int ret, i; 3413 3414 ret = sscanf(str, "[%x:%x.%x]=%s", &bus, &dev, &fn, acpiid); 3415 if (ret != 4) { 3416 pr_err("Invalid command line: ivrs_acpihid(%s)\n", str); 3417 return 1; 3418 } 3419 3420 p = acpiid; 3421 hid = strsep(&p, ":"); 3422 uid = p; 3423 3424 if (!hid || !(*hid) || !uid) { 3425 pr_err("Invalid command line: hid or uid\n"); 3426 return 1; 3427 } 3428 3429 i = early_acpihid_map_size++; 3430 memcpy(early_acpihid_map[i].hid, hid, strlen(hid)); 3431 memcpy(early_acpihid_map[i].uid, uid, strlen(uid)); 3432 early_acpihid_map[i].devid = 3433 ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7); 3434 early_acpihid_map[i].cmd_line = true; 3435 3436 return 1; 3437 } 3438 3439 __setup("amd_iommu_dump", parse_amd_iommu_dump); 3440 __setup("amd_iommu=", parse_amd_iommu_options); 3441 __setup("amd_iommu_intr=", parse_amd_iommu_intr); 3442 __setup("ivrs_ioapic", parse_ivrs_ioapic); 3443 __setup("ivrs_hpet", parse_ivrs_hpet); 3444 __setup("ivrs_acpihid", parse_ivrs_acpihid); 3445 3446 bool amd_iommu_v2_supported(void) 3447 { 3448 return amd_iommu_v2_present; 3449 } 3450 EXPORT_SYMBOL(amd_iommu_v2_supported); 3451 3452 struct amd_iommu *get_amd_iommu(unsigned int idx) 3453 { 3454 unsigned int i = 0; 3455 struct amd_iommu *iommu; 3456 3457 for_each_iommu(iommu) 3458 if (i++ == idx) 3459 return iommu; 3460 return NULL; 3461 } 3462 3463 /**************************************************************************** 3464 * 3465 * IOMMU EFR Performance Counter support functionality. This code allows 3466 * access to the IOMMU PC functionality. 3467 * 3468 ****************************************************************************/ 3469 3470 u8 amd_iommu_pc_get_max_banks(unsigned int idx) 3471 { 3472 struct amd_iommu *iommu = get_amd_iommu(idx); 3473 3474 if (iommu) 3475 return iommu->max_banks; 3476 3477 return 0; 3478 } 3479 EXPORT_SYMBOL(amd_iommu_pc_get_max_banks); 3480 3481 bool amd_iommu_pc_supported(void) 3482 { 3483 return amd_iommu_pc_present; 3484 } 3485 EXPORT_SYMBOL(amd_iommu_pc_supported); 3486 3487 u8 amd_iommu_pc_get_max_counters(unsigned int idx) 3488 { 3489 struct amd_iommu *iommu = get_amd_iommu(idx); 3490 3491 if (iommu) 3492 return iommu->max_counters; 3493 3494 return 0; 3495 } 3496 EXPORT_SYMBOL(amd_iommu_pc_get_max_counters); 3497 3498 static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, 3499 u8 fxn, u64 *value, bool is_write) 3500 { 3501 u32 offset; 3502 u32 max_offset_lim; 3503 3504 /* Make sure the IOMMU PC resource is available */ 3505 if (!amd_iommu_pc_present) 3506 return -ENODEV; 3507 3508 /* Check for valid iommu and pc register indexing */ 3509 if (WARN_ON(!iommu || (fxn > 0x28) || (fxn & 7))) 3510 return -ENODEV; 3511 3512 offset = (u32)(((0x40 | bank) << 12) | (cntr << 8) | fxn); 3513 3514 /* Limit the offset to the hw defined mmio region aperture */ 3515 max_offset_lim = (u32)(((0x40 | iommu->max_banks) << 12) | 3516 (iommu->max_counters << 8) | 0x28); 3517 if ((offset < MMIO_CNTR_REG_OFFSET) || 3518 (offset > max_offset_lim)) 3519 return -EINVAL; 3520 3521 if (is_write) { 3522 u64 val = *value & GENMASK_ULL(47, 0); 3523 3524 writel((u32)val, iommu->mmio_base + offset); 3525 writel((val >> 32), iommu->mmio_base + offset + 4); 3526 } else { 3527 *value = readl(iommu->mmio_base + offset + 4); 3528 *value <<= 32; 3529 *value |= readl(iommu->mmio_base + offset); 3530 *value &= GENMASK_ULL(47, 0); 3531 } 3532 3533 return 0; 3534 } 3535 3536 int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value) 3537 { 3538 if (!iommu) 3539 return -EINVAL; 3540 3541 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, false); 3542 } 3543 3544 int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value) 3545 { 3546 if (!iommu) 3547 return -EINVAL; 3548 3549 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, true); 3550 } 3551