1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. 4 * Author: Joerg Roedel <jroedel@suse.de> 5 * Leo Duran <leo.duran@amd.com> 6 */ 7 8 #define pr_fmt(fmt) "AMD-Vi: " fmt 9 #define dev_fmt(fmt) pr_fmt(fmt) 10 11 #include <linux/pci.h> 12 #include <linux/acpi.h> 13 #include <linux/list.h> 14 #include <linux/bitmap.h> 15 #include <linux/slab.h> 16 #include <linux/syscore_ops.h> 17 #include <linux/interrupt.h> 18 #include <linux/msi.h> 19 #include <linux/irq.h> 20 #include <linux/amd-iommu.h> 21 #include <linux/export.h> 22 #include <linux/kmemleak.h> 23 #include <linux/cc_platform.h> 24 #include <linux/iopoll.h> 25 #include <asm/pci-direct.h> 26 #include <asm/iommu.h> 27 #include <asm/apic.h> 28 #include <asm/gart.h> 29 #include <asm/x86_init.h> 30 #include <asm/io_apic.h> 31 #include <asm/irq_remapping.h> 32 #include <asm/set_memory.h> 33 34 #include <linux/crash_dump.h> 35 36 #include "amd_iommu.h" 37 #include "../irq_remapping.h" 38 39 /* 40 * definitions for the ACPI scanning code 41 */ 42 #define IVRS_HEADER_LENGTH 48 43 44 #define ACPI_IVHD_TYPE_MAX_SUPPORTED 0x40 45 #define ACPI_IVMD_TYPE_ALL 0x20 46 #define ACPI_IVMD_TYPE 0x21 47 #define ACPI_IVMD_TYPE_RANGE 0x22 48 49 #define IVHD_DEV_ALL 0x01 50 #define IVHD_DEV_SELECT 0x02 51 #define IVHD_DEV_SELECT_RANGE_START 0x03 52 #define IVHD_DEV_RANGE_END 0x04 53 #define IVHD_DEV_ALIAS 0x42 54 #define IVHD_DEV_ALIAS_RANGE 0x43 55 #define IVHD_DEV_EXT_SELECT 0x46 56 #define IVHD_DEV_EXT_SELECT_RANGE 0x47 57 #define IVHD_DEV_SPECIAL 0x48 58 #define IVHD_DEV_ACPI_HID 0xf0 59 60 #define UID_NOT_PRESENT 0 61 #define UID_IS_INTEGER 1 62 #define UID_IS_CHARACTER 2 63 64 #define IVHD_SPECIAL_IOAPIC 1 65 #define IVHD_SPECIAL_HPET 2 66 67 #define IVHD_FLAG_HT_TUN_EN_MASK 0x01 68 #define IVHD_FLAG_PASSPW_EN_MASK 0x02 69 #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04 70 #define IVHD_FLAG_ISOC_EN_MASK 0x08 71 72 #define IVMD_FLAG_EXCL_RANGE 0x08 73 #define IVMD_FLAG_IW 0x04 74 #define IVMD_FLAG_IR 0x02 75 #define IVMD_FLAG_UNITY_MAP 0x01 76 77 #define ACPI_DEVFLAG_INITPASS 0x01 78 #define ACPI_DEVFLAG_EXTINT 0x02 79 #define ACPI_DEVFLAG_NMI 0x04 80 #define ACPI_DEVFLAG_SYSMGT1 0x10 81 #define ACPI_DEVFLAG_SYSMGT2 0x20 82 #define ACPI_DEVFLAG_LINT0 0x40 83 #define ACPI_DEVFLAG_LINT1 0x80 84 #define ACPI_DEVFLAG_ATSDIS 0x10000000 85 86 #define LOOP_TIMEOUT 2000000 87 /* 88 * ACPI table definitions 89 * 90 * These data structures are laid over the table to parse the important values 91 * out of it. 92 */ 93 94 extern const struct iommu_ops amd_iommu_ops; 95 96 /* 97 * structure describing one IOMMU in the ACPI table. Typically followed by one 98 * or more ivhd_entrys. 99 */ 100 struct ivhd_header { 101 u8 type; 102 u8 flags; 103 u16 length; 104 u16 devid; 105 u16 cap_ptr; 106 u64 mmio_phys; 107 u16 pci_seg; 108 u16 info; 109 u32 efr_attr; 110 111 /* Following only valid on IVHD type 11h and 40h */ 112 u64 efr_reg; /* Exact copy of MMIO_EXT_FEATURES */ 113 u64 res; 114 } __attribute__((packed)); 115 116 /* 117 * A device entry describing which devices a specific IOMMU translates and 118 * which requestor ids they use. 119 */ 120 struct ivhd_entry { 121 u8 type; 122 u16 devid; 123 u8 flags; 124 struct_group(ext_hid, 125 u32 ext; 126 u32 hidh; 127 ); 128 u64 cid; 129 u8 uidf; 130 u8 uidl; 131 u8 uid; 132 } __attribute__((packed)); 133 134 /* 135 * An AMD IOMMU memory definition structure. It defines things like exclusion 136 * ranges for devices and regions that should be unity mapped. 137 */ 138 struct ivmd_header { 139 u8 type; 140 u8 flags; 141 u16 length; 142 u16 devid; 143 u16 aux; 144 u16 pci_seg; 145 u8 resv[6]; 146 u64 range_start; 147 u64 range_length; 148 } __attribute__((packed)); 149 150 bool amd_iommu_dump; 151 bool amd_iommu_irq_remap __read_mostly; 152 153 enum io_pgtable_fmt amd_iommu_pgtable = AMD_IOMMU_V1; 154 155 int amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC; 156 static int amd_iommu_xt_mode = IRQ_REMAP_XAPIC_MODE; 157 158 static bool amd_iommu_detected; 159 static bool amd_iommu_disabled __initdata; 160 static bool amd_iommu_force_enable __initdata; 161 static int amd_iommu_target_ivhd_type; 162 163 u16 amd_iommu_last_bdf; /* largest PCI device id we have 164 to handle */ 165 166 LIST_HEAD(amd_iommu_pci_seg_list); /* list of all PCI segments */ 167 LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the 168 system */ 169 170 /* Array to assign indices to IOMMUs*/ 171 struct amd_iommu *amd_iommus[MAX_IOMMUS]; 172 173 /* Number of IOMMUs present in the system */ 174 static int amd_iommus_present; 175 176 /* IOMMUs have a non-present cache? */ 177 bool amd_iommu_np_cache __read_mostly; 178 bool amd_iommu_iotlb_sup __read_mostly = true; 179 180 u32 amd_iommu_max_pasid __read_mostly = ~0; 181 182 bool amd_iommu_v2_present __read_mostly; 183 static bool amd_iommu_pc_present __read_mostly; 184 bool amdr_ivrs_remap_support __read_mostly; 185 186 bool amd_iommu_force_isolation __read_mostly; 187 188 /* 189 * Pointer to the device table which is shared by all AMD IOMMUs 190 * it is indexed by the PCI device id or the HT unit id and contains 191 * information about the domain the device belongs to as well as the 192 * page table root pointer. 193 */ 194 struct dev_table_entry *amd_iommu_dev_table; 195 196 /* 197 * The alias table is a driver specific data structure which contains the 198 * mappings of the PCI device ids to the actual requestor ids on the IOMMU. 199 * More than one device can share the same requestor id. 200 */ 201 u16 *amd_iommu_alias_table; 202 203 /* 204 * The rlookup table is used to find the IOMMU which is responsible 205 * for a specific device. It is also indexed by the PCI device id. 206 */ 207 struct amd_iommu **amd_iommu_rlookup_table; 208 209 /* 210 * This table is used to find the irq remapping table for a given device id 211 * quickly. 212 */ 213 struct irq_remap_table **irq_lookup_table; 214 215 /* 216 * AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap 217 * to know which ones are already in use. 218 */ 219 unsigned long *amd_iommu_pd_alloc_bitmap; 220 221 static u32 dev_table_size; /* size of the device table */ 222 static u32 alias_table_size; /* size of the alias table */ 223 static u32 rlookup_table_size; /* size if the rlookup table */ 224 225 enum iommu_init_state { 226 IOMMU_START_STATE, 227 IOMMU_IVRS_DETECTED, 228 IOMMU_ACPI_FINISHED, 229 IOMMU_ENABLED, 230 IOMMU_PCI_INIT, 231 IOMMU_INTERRUPTS_EN, 232 IOMMU_INITIALIZED, 233 IOMMU_NOT_FOUND, 234 IOMMU_INIT_ERROR, 235 IOMMU_CMDLINE_DISABLED, 236 }; 237 238 /* Early ioapic and hpet maps from kernel command line */ 239 #define EARLY_MAP_SIZE 4 240 static struct devid_map __initdata early_ioapic_map[EARLY_MAP_SIZE]; 241 static struct devid_map __initdata early_hpet_map[EARLY_MAP_SIZE]; 242 static struct acpihid_map_entry __initdata early_acpihid_map[EARLY_MAP_SIZE]; 243 244 static int __initdata early_ioapic_map_size; 245 static int __initdata early_hpet_map_size; 246 static int __initdata early_acpihid_map_size; 247 248 static bool __initdata cmdline_maps; 249 250 static enum iommu_init_state init_state = IOMMU_START_STATE; 251 252 static int amd_iommu_enable_interrupts(void); 253 static int __init iommu_go_to_state(enum iommu_init_state state); 254 static void init_device_table_dma(void); 255 256 static bool amd_iommu_pre_enabled = true; 257 258 static u32 amd_iommu_ivinfo __initdata; 259 260 bool translation_pre_enabled(struct amd_iommu *iommu) 261 { 262 return (iommu->flags & AMD_IOMMU_FLAG_TRANS_PRE_ENABLED); 263 } 264 265 static void clear_translation_pre_enabled(struct amd_iommu *iommu) 266 { 267 iommu->flags &= ~AMD_IOMMU_FLAG_TRANS_PRE_ENABLED; 268 } 269 270 static void init_translation_status(struct amd_iommu *iommu) 271 { 272 u64 ctrl; 273 274 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); 275 if (ctrl & (1<<CONTROL_IOMMU_EN)) 276 iommu->flags |= AMD_IOMMU_FLAG_TRANS_PRE_ENABLED; 277 } 278 279 static inline void update_last_devid(u16 devid) 280 { 281 if (devid > amd_iommu_last_bdf) 282 amd_iommu_last_bdf = devid; 283 } 284 285 static inline unsigned long tbl_size(int entry_size) 286 { 287 unsigned shift = PAGE_SHIFT + 288 get_order(((int)amd_iommu_last_bdf + 1) * entry_size); 289 290 return 1UL << shift; 291 } 292 293 int amd_iommu_get_num_iommus(void) 294 { 295 return amd_iommus_present; 296 } 297 298 #ifdef CONFIG_IRQ_REMAP 299 static bool check_feature_on_all_iommus(u64 mask) 300 { 301 bool ret = false; 302 struct amd_iommu *iommu; 303 304 for_each_iommu(iommu) { 305 ret = iommu_feature(iommu, mask); 306 if (!ret) 307 return false; 308 } 309 310 return true; 311 } 312 #endif 313 314 /* 315 * For IVHD type 0x11/0x40, EFR is also available via IVHD. 316 * Default to IVHD EFR since it is available sooner 317 * (i.e. before PCI init). 318 */ 319 static void __init early_iommu_features_init(struct amd_iommu *iommu, 320 struct ivhd_header *h) 321 { 322 if (amd_iommu_ivinfo & IOMMU_IVINFO_EFRSUP) 323 iommu->features = h->efr_reg; 324 if (amd_iommu_ivinfo & IOMMU_IVINFO_DMA_REMAP) 325 amdr_ivrs_remap_support = true; 326 } 327 328 /* Access to l1 and l2 indexed register spaces */ 329 330 static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address) 331 { 332 u32 val; 333 334 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); 335 pci_read_config_dword(iommu->dev, 0xfc, &val); 336 return val; 337 } 338 339 static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val) 340 { 341 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31)); 342 pci_write_config_dword(iommu->dev, 0xfc, val); 343 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); 344 } 345 346 static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address) 347 { 348 u32 val; 349 350 pci_write_config_dword(iommu->dev, 0xf0, address); 351 pci_read_config_dword(iommu->dev, 0xf4, &val); 352 return val; 353 } 354 355 static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val) 356 { 357 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8)); 358 pci_write_config_dword(iommu->dev, 0xf4, val); 359 } 360 361 /**************************************************************************** 362 * 363 * AMD IOMMU MMIO register space handling functions 364 * 365 * These functions are used to program the IOMMU device registers in 366 * MMIO space required for that driver. 367 * 368 ****************************************************************************/ 369 370 /* 371 * This function set the exclusion range in the IOMMU. DMA accesses to the 372 * exclusion range are passed through untranslated 373 */ 374 static void iommu_set_exclusion_range(struct amd_iommu *iommu) 375 { 376 u64 start = iommu->exclusion_start & PAGE_MASK; 377 u64 limit = (start + iommu->exclusion_length - 1) & PAGE_MASK; 378 u64 entry; 379 380 if (!iommu->exclusion_start) 381 return; 382 383 entry = start | MMIO_EXCL_ENABLE_MASK; 384 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, 385 &entry, sizeof(entry)); 386 387 entry = limit; 388 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, 389 &entry, sizeof(entry)); 390 } 391 392 static void iommu_set_cwwb_range(struct amd_iommu *iommu) 393 { 394 u64 start = iommu_virt_to_phys((void *)iommu->cmd_sem); 395 u64 entry = start & PM_ADDR_MASK; 396 397 if (!iommu_feature(iommu, FEATURE_SNP)) 398 return; 399 400 /* Note: 401 * Re-purpose Exclusion base/limit registers for Completion wait 402 * write-back base/limit. 403 */ 404 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, 405 &entry, sizeof(entry)); 406 407 /* Note: 408 * Default to 4 Kbytes, which can be specified by setting base 409 * address equal to the limit address. 410 */ 411 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, 412 &entry, sizeof(entry)); 413 } 414 415 /* Programs the physical address of the device table into the IOMMU hardware */ 416 static void iommu_set_device_table(struct amd_iommu *iommu) 417 { 418 u64 entry; 419 420 BUG_ON(iommu->mmio_base == NULL); 421 422 entry = iommu_virt_to_phys(amd_iommu_dev_table); 423 entry |= (dev_table_size >> 12) - 1; 424 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET, 425 &entry, sizeof(entry)); 426 } 427 428 /* Generic functions to enable/disable certain features of the IOMMU. */ 429 static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit) 430 { 431 u64 ctrl; 432 433 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); 434 ctrl |= (1ULL << bit); 435 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); 436 } 437 438 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit) 439 { 440 u64 ctrl; 441 442 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); 443 ctrl &= ~(1ULL << bit); 444 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); 445 } 446 447 static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout) 448 { 449 u64 ctrl; 450 451 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); 452 ctrl &= ~CTRL_INV_TO_MASK; 453 ctrl |= (timeout << CONTROL_INV_TIMEOUT) & CTRL_INV_TO_MASK; 454 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); 455 } 456 457 /* Function to enable the hardware */ 458 static void iommu_enable(struct amd_iommu *iommu) 459 { 460 iommu_feature_enable(iommu, CONTROL_IOMMU_EN); 461 } 462 463 static void iommu_disable(struct amd_iommu *iommu) 464 { 465 if (!iommu->mmio_base) 466 return; 467 468 /* Disable command buffer */ 469 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); 470 471 /* Disable event logging and event interrupts */ 472 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN); 473 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); 474 475 /* Disable IOMMU GA_LOG */ 476 iommu_feature_disable(iommu, CONTROL_GALOG_EN); 477 iommu_feature_disable(iommu, CONTROL_GAINT_EN); 478 479 /* Disable IOMMU hardware itself */ 480 iommu_feature_disable(iommu, CONTROL_IOMMU_EN); 481 } 482 483 /* 484 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in 485 * the system has one. 486 */ 487 static u8 __iomem * __init iommu_map_mmio_space(u64 address, u64 end) 488 { 489 if (!request_mem_region(address, end, "amd_iommu")) { 490 pr_err("Can not reserve memory region %llx-%llx for mmio\n", 491 address, end); 492 pr_err("This is a BIOS bug. Please contact your hardware vendor\n"); 493 return NULL; 494 } 495 496 return (u8 __iomem *)ioremap(address, end); 497 } 498 499 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu) 500 { 501 if (iommu->mmio_base) 502 iounmap(iommu->mmio_base); 503 release_mem_region(iommu->mmio_phys, iommu->mmio_phys_end); 504 } 505 506 static inline u32 get_ivhd_header_size(struct ivhd_header *h) 507 { 508 u32 size = 0; 509 510 switch (h->type) { 511 case 0x10: 512 size = 24; 513 break; 514 case 0x11: 515 case 0x40: 516 size = 40; 517 break; 518 } 519 return size; 520 } 521 522 /**************************************************************************** 523 * 524 * The functions below belong to the first pass of AMD IOMMU ACPI table 525 * parsing. In this pass we try to find out the highest device id this 526 * code has to handle. Upon this information the size of the shared data 527 * structures is determined later. 528 * 529 ****************************************************************************/ 530 531 /* 532 * This function calculates the length of a given IVHD entry 533 */ 534 static inline int ivhd_entry_length(u8 *ivhd) 535 { 536 u32 type = ((struct ivhd_entry *)ivhd)->type; 537 538 if (type < 0x80) { 539 return 0x04 << (*ivhd >> 6); 540 } else if (type == IVHD_DEV_ACPI_HID) { 541 /* For ACPI_HID, offset 21 is uid len */ 542 return *((u8 *)ivhd + 21) + 22; 543 } 544 return 0; 545 } 546 547 /* 548 * After reading the highest device id from the IOMMU PCI capability header 549 * this function looks if there is a higher device id defined in the ACPI table 550 */ 551 static int __init find_last_devid_from_ivhd(struct ivhd_header *h) 552 { 553 u8 *p = (void *)h, *end = (void *)h; 554 struct ivhd_entry *dev; 555 int last_devid = -EINVAL; 556 557 u32 ivhd_size = get_ivhd_header_size(h); 558 559 if (!ivhd_size) { 560 pr_err("Unsupported IVHD type %#x\n", h->type); 561 return -EINVAL; 562 } 563 564 p += ivhd_size; 565 end += h->length; 566 567 while (p < end) { 568 dev = (struct ivhd_entry *)p; 569 switch (dev->type) { 570 case IVHD_DEV_ALL: 571 /* Use maximum BDF value for DEV_ALL */ 572 update_last_devid(0xffff); 573 return 0xffff; 574 case IVHD_DEV_SELECT: 575 case IVHD_DEV_RANGE_END: 576 case IVHD_DEV_ALIAS: 577 case IVHD_DEV_EXT_SELECT: 578 /* all the above subfield types refer to device ids */ 579 update_last_devid(dev->devid); 580 if (dev->devid > last_devid) 581 last_devid = dev->devid; 582 break; 583 default: 584 break; 585 } 586 p += ivhd_entry_length(p); 587 } 588 589 WARN_ON(p != end); 590 591 return last_devid; 592 } 593 594 static int __init check_ivrs_checksum(struct acpi_table_header *table) 595 { 596 int i; 597 u8 checksum = 0, *p = (u8 *)table; 598 599 for (i = 0; i < table->length; ++i) 600 checksum += p[i]; 601 if (checksum != 0) { 602 /* ACPI table corrupt */ 603 pr_err(FW_BUG "IVRS invalid checksum\n"); 604 return -ENODEV; 605 } 606 607 return 0; 608 } 609 610 /* 611 * Iterate over all IVHD entries in the ACPI table and find the highest device 612 * id which we need to handle. This is the first of three functions which parse 613 * the ACPI table. So we check the checksum here. 614 */ 615 static int __init find_last_devid_acpi(struct acpi_table_header *table, u16 pci_seg) 616 { 617 u8 *p = (u8 *)table, *end = (u8 *)table; 618 struct ivhd_header *h; 619 int last_devid, last_bdf = 0; 620 621 p += IVRS_HEADER_LENGTH; 622 623 end += table->length; 624 while (p < end) { 625 h = (struct ivhd_header *)p; 626 if (h->pci_seg == pci_seg && 627 h->type == amd_iommu_target_ivhd_type) { 628 last_devid = find_last_devid_from_ivhd(h); 629 630 if (last_devid < 0) 631 return -EINVAL; 632 if (last_devid > last_bdf) 633 last_bdf = last_devid; 634 } 635 p += h->length; 636 } 637 WARN_ON(p != end); 638 639 return last_bdf; 640 } 641 642 /**************************************************************************** 643 * 644 * The following functions belong to the code path which parses the ACPI table 645 * the second time. In this ACPI parsing iteration we allocate IOMMU specific 646 * data structures, initialize the per PCI segment device/alias/rlookup table 647 * and also basically initialize the hardware. 648 * 649 ****************************************************************************/ 650 651 /* Allocate per PCI segment device table */ 652 static inline int __init alloc_dev_table(struct amd_iommu_pci_seg *pci_seg) 653 { 654 pci_seg->dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO | GFP_DMA32, 655 get_order(dev_table_size)); 656 if (!pci_seg->dev_table) 657 return -ENOMEM; 658 659 return 0; 660 } 661 662 static inline void free_dev_table(struct amd_iommu_pci_seg *pci_seg) 663 { 664 free_pages((unsigned long)pci_seg->dev_table, 665 get_order(dev_table_size)); 666 pci_seg->dev_table = NULL; 667 } 668 669 /* Allocate per PCI segment IOMMU rlookup table. */ 670 static inline int __init alloc_rlookup_table(struct amd_iommu_pci_seg *pci_seg) 671 { 672 pci_seg->rlookup_table = (void *)__get_free_pages( 673 GFP_KERNEL | __GFP_ZERO, 674 get_order(rlookup_table_size)); 675 if (pci_seg->rlookup_table == NULL) 676 return -ENOMEM; 677 678 return 0; 679 } 680 681 static inline void free_rlookup_table(struct amd_iommu_pci_seg *pci_seg) 682 { 683 free_pages((unsigned long)pci_seg->rlookup_table, 684 get_order(rlookup_table_size)); 685 pci_seg->rlookup_table = NULL; 686 } 687 688 static inline int __init alloc_irq_lookup_table(struct amd_iommu_pci_seg *pci_seg) 689 { 690 pci_seg->irq_lookup_table = (void *)__get_free_pages( 691 GFP_KERNEL | __GFP_ZERO, 692 get_order(rlookup_table_size)); 693 kmemleak_alloc(pci_seg->irq_lookup_table, 694 rlookup_table_size, 1, GFP_KERNEL); 695 if (pci_seg->irq_lookup_table == NULL) 696 return -ENOMEM; 697 698 return 0; 699 } 700 701 static inline void free_irq_lookup_table(struct amd_iommu_pci_seg *pci_seg) 702 { 703 kmemleak_free(pci_seg->irq_lookup_table); 704 free_pages((unsigned long)pci_seg->irq_lookup_table, 705 get_order(rlookup_table_size)); 706 pci_seg->irq_lookup_table = NULL; 707 } 708 709 static int __init alloc_alias_table(struct amd_iommu_pci_seg *pci_seg) 710 { 711 int i; 712 713 pci_seg->alias_table = (void *)__get_free_pages(GFP_KERNEL, 714 get_order(alias_table_size)); 715 if (!pci_seg->alias_table) 716 return -ENOMEM; 717 718 /* 719 * let all alias entries point to itself 720 */ 721 for (i = 0; i <= amd_iommu_last_bdf; ++i) 722 pci_seg->alias_table[i] = i; 723 724 return 0; 725 } 726 727 static void __init free_alias_table(struct amd_iommu_pci_seg *pci_seg) 728 { 729 free_pages((unsigned long)pci_seg->alias_table, 730 get_order(alias_table_size)); 731 pci_seg->alias_table = NULL; 732 } 733 734 /* 735 * Allocates the command buffer. This buffer is per AMD IOMMU. We can 736 * write commands to that buffer later and the IOMMU will execute them 737 * asynchronously 738 */ 739 static int __init alloc_command_buffer(struct amd_iommu *iommu) 740 { 741 iommu->cmd_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 742 get_order(CMD_BUFFER_SIZE)); 743 744 return iommu->cmd_buf ? 0 : -ENOMEM; 745 } 746 747 /* 748 * This function restarts event logging in case the IOMMU experienced 749 * an event log buffer overflow. 750 */ 751 void amd_iommu_restart_event_logging(struct amd_iommu *iommu) 752 { 753 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); 754 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN); 755 } 756 757 /* 758 * This function resets the command buffer if the IOMMU stopped fetching 759 * commands from it. 760 */ 761 static void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu) 762 { 763 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); 764 765 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); 766 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); 767 iommu->cmd_buf_head = 0; 768 iommu->cmd_buf_tail = 0; 769 770 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN); 771 } 772 773 /* 774 * This function writes the command buffer address to the hardware and 775 * enables it. 776 */ 777 static void iommu_enable_command_buffer(struct amd_iommu *iommu) 778 { 779 u64 entry; 780 781 BUG_ON(iommu->cmd_buf == NULL); 782 783 entry = iommu_virt_to_phys(iommu->cmd_buf); 784 entry |= MMIO_CMD_SIZE_512; 785 786 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET, 787 &entry, sizeof(entry)); 788 789 amd_iommu_reset_cmd_buffer(iommu); 790 } 791 792 /* 793 * This function disables the command buffer 794 */ 795 static void iommu_disable_command_buffer(struct amd_iommu *iommu) 796 { 797 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); 798 } 799 800 static void __init free_command_buffer(struct amd_iommu *iommu) 801 { 802 free_pages((unsigned long)iommu->cmd_buf, get_order(CMD_BUFFER_SIZE)); 803 } 804 805 static void *__init iommu_alloc_4k_pages(struct amd_iommu *iommu, 806 gfp_t gfp, size_t size) 807 { 808 int order = get_order(size); 809 void *buf = (void *)__get_free_pages(gfp, order); 810 811 if (buf && 812 iommu_feature(iommu, FEATURE_SNP) && 813 set_memory_4k((unsigned long)buf, (1 << order))) { 814 free_pages((unsigned long)buf, order); 815 buf = NULL; 816 } 817 818 return buf; 819 } 820 821 /* allocates the memory where the IOMMU will log its events to */ 822 static int __init alloc_event_buffer(struct amd_iommu *iommu) 823 { 824 iommu->evt_buf = iommu_alloc_4k_pages(iommu, GFP_KERNEL | __GFP_ZERO, 825 EVT_BUFFER_SIZE); 826 827 return iommu->evt_buf ? 0 : -ENOMEM; 828 } 829 830 static void iommu_enable_event_buffer(struct amd_iommu *iommu) 831 { 832 u64 entry; 833 834 BUG_ON(iommu->evt_buf == NULL); 835 836 entry = iommu_virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK; 837 838 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET, 839 &entry, sizeof(entry)); 840 841 /* set head and tail to zero manually */ 842 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); 843 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); 844 845 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN); 846 } 847 848 /* 849 * This function disables the event log buffer 850 */ 851 static void iommu_disable_event_buffer(struct amd_iommu *iommu) 852 { 853 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); 854 } 855 856 static void __init free_event_buffer(struct amd_iommu *iommu) 857 { 858 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE)); 859 } 860 861 /* allocates the memory where the IOMMU will log its events to */ 862 static int __init alloc_ppr_log(struct amd_iommu *iommu) 863 { 864 iommu->ppr_log = iommu_alloc_4k_pages(iommu, GFP_KERNEL | __GFP_ZERO, 865 PPR_LOG_SIZE); 866 867 return iommu->ppr_log ? 0 : -ENOMEM; 868 } 869 870 static void iommu_enable_ppr_log(struct amd_iommu *iommu) 871 { 872 u64 entry; 873 874 if (iommu->ppr_log == NULL) 875 return; 876 877 entry = iommu_virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512; 878 879 memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET, 880 &entry, sizeof(entry)); 881 882 /* set head and tail to zero manually */ 883 writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); 884 writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); 885 886 iommu_feature_enable(iommu, CONTROL_PPRLOG_EN); 887 iommu_feature_enable(iommu, CONTROL_PPR_EN); 888 } 889 890 static void __init free_ppr_log(struct amd_iommu *iommu) 891 { 892 free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE)); 893 } 894 895 static void free_ga_log(struct amd_iommu *iommu) 896 { 897 #ifdef CONFIG_IRQ_REMAP 898 free_pages((unsigned long)iommu->ga_log, get_order(GA_LOG_SIZE)); 899 free_pages((unsigned long)iommu->ga_log_tail, get_order(8)); 900 #endif 901 } 902 903 static int iommu_ga_log_enable(struct amd_iommu *iommu) 904 { 905 #ifdef CONFIG_IRQ_REMAP 906 u32 status, i; 907 u64 entry; 908 909 if (!iommu->ga_log) 910 return -EINVAL; 911 912 /* Check if already running */ 913 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); 914 if (WARN_ON(status & (MMIO_STATUS_GALOG_RUN_MASK))) 915 return 0; 916 917 entry = iommu_virt_to_phys(iommu->ga_log) | GA_LOG_SIZE_512; 918 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_BASE_OFFSET, 919 &entry, sizeof(entry)); 920 entry = (iommu_virt_to_phys(iommu->ga_log_tail) & 921 (BIT_ULL(52)-1)) & ~7ULL; 922 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_TAIL_OFFSET, 923 &entry, sizeof(entry)); 924 writel(0x00, iommu->mmio_base + MMIO_GA_HEAD_OFFSET); 925 writel(0x00, iommu->mmio_base + MMIO_GA_TAIL_OFFSET); 926 927 928 iommu_feature_enable(iommu, CONTROL_GAINT_EN); 929 iommu_feature_enable(iommu, CONTROL_GALOG_EN); 930 931 for (i = 0; i < LOOP_TIMEOUT; ++i) { 932 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); 933 if (status & (MMIO_STATUS_GALOG_RUN_MASK)) 934 break; 935 udelay(10); 936 } 937 938 if (WARN_ON(i >= LOOP_TIMEOUT)) 939 return -EINVAL; 940 #endif /* CONFIG_IRQ_REMAP */ 941 return 0; 942 } 943 944 static int iommu_init_ga_log(struct amd_iommu *iommu) 945 { 946 #ifdef CONFIG_IRQ_REMAP 947 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) 948 return 0; 949 950 iommu->ga_log = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 951 get_order(GA_LOG_SIZE)); 952 if (!iommu->ga_log) 953 goto err_out; 954 955 iommu->ga_log_tail = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 956 get_order(8)); 957 if (!iommu->ga_log_tail) 958 goto err_out; 959 960 return 0; 961 err_out: 962 free_ga_log(iommu); 963 return -EINVAL; 964 #else 965 return 0; 966 #endif /* CONFIG_IRQ_REMAP */ 967 } 968 969 static int __init alloc_cwwb_sem(struct amd_iommu *iommu) 970 { 971 iommu->cmd_sem = iommu_alloc_4k_pages(iommu, GFP_KERNEL | __GFP_ZERO, 1); 972 973 return iommu->cmd_sem ? 0 : -ENOMEM; 974 } 975 976 static void __init free_cwwb_sem(struct amd_iommu *iommu) 977 { 978 if (iommu->cmd_sem) 979 free_page((unsigned long)iommu->cmd_sem); 980 } 981 982 static void iommu_enable_xt(struct amd_iommu *iommu) 983 { 984 #ifdef CONFIG_IRQ_REMAP 985 /* 986 * XT mode (32-bit APIC destination ID) requires 987 * GA mode (128-bit IRTE support) as a prerequisite. 988 */ 989 if (AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir) && 990 amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE) 991 iommu_feature_enable(iommu, CONTROL_XT_EN); 992 #endif /* CONFIG_IRQ_REMAP */ 993 } 994 995 static void iommu_enable_gt(struct amd_iommu *iommu) 996 { 997 if (!iommu_feature(iommu, FEATURE_GT)) 998 return; 999 1000 iommu_feature_enable(iommu, CONTROL_GT_EN); 1001 } 1002 1003 /* sets a specific bit in the device table entry. */ 1004 static void set_dev_entry_bit(u16 devid, u8 bit) 1005 { 1006 int i = (bit >> 6) & 0x03; 1007 int _bit = bit & 0x3f; 1008 1009 amd_iommu_dev_table[devid].data[i] |= (1UL << _bit); 1010 } 1011 1012 static int get_dev_entry_bit(u16 devid, u8 bit) 1013 { 1014 int i = (bit >> 6) & 0x03; 1015 int _bit = bit & 0x3f; 1016 1017 return (amd_iommu_dev_table[devid].data[i] & (1UL << _bit)) >> _bit; 1018 } 1019 1020 1021 static bool __copy_device_table(struct amd_iommu *iommu) 1022 { 1023 u64 int_ctl, int_tab_len, entry = 0; 1024 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; 1025 struct dev_table_entry *old_devtb = NULL; 1026 u32 lo, hi, devid, old_devtb_size; 1027 phys_addr_t old_devtb_phys; 1028 u16 dom_id, dte_v, irq_v; 1029 gfp_t gfp_flag; 1030 u64 tmp; 1031 1032 /* Each IOMMU use separate device table with the same size */ 1033 lo = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET); 1034 hi = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET + 4); 1035 entry = (((u64) hi) << 32) + lo; 1036 1037 old_devtb_size = ((entry & ~PAGE_MASK) + 1) << 12; 1038 if (old_devtb_size != dev_table_size) { 1039 pr_err("The device table size of IOMMU:%d is not expected!\n", 1040 iommu->index); 1041 return false; 1042 } 1043 1044 /* 1045 * When SME is enabled in the first kernel, the entry includes the 1046 * memory encryption mask(sme_me_mask), we must remove the memory 1047 * encryption mask to obtain the true physical address in kdump kernel. 1048 */ 1049 old_devtb_phys = __sme_clr(entry) & PAGE_MASK; 1050 1051 if (old_devtb_phys >= 0x100000000ULL) { 1052 pr_err("The address of old device table is above 4G, not trustworthy!\n"); 1053 return false; 1054 } 1055 old_devtb = (cc_platform_has(CC_ATTR_HOST_MEM_ENCRYPT) && is_kdump_kernel()) 1056 ? (__force void *)ioremap_encrypted(old_devtb_phys, 1057 dev_table_size) 1058 : memremap(old_devtb_phys, dev_table_size, MEMREMAP_WB); 1059 1060 if (!old_devtb) 1061 return false; 1062 1063 gfp_flag = GFP_KERNEL | __GFP_ZERO | GFP_DMA32; 1064 pci_seg->old_dev_tbl_cpy = (void *)__get_free_pages(gfp_flag, 1065 get_order(dev_table_size)); 1066 if (pci_seg->old_dev_tbl_cpy == NULL) { 1067 pr_err("Failed to allocate memory for copying old device table!\n"); 1068 memunmap(old_devtb); 1069 return false; 1070 } 1071 1072 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) { 1073 pci_seg->old_dev_tbl_cpy[devid] = old_devtb[devid]; 1074 dom_id = old_devtb[devid].data[1] & DEV_DOMID_MASK; 1075 dte_v = old_devtb[devid].data[0] & DTE_FLAG_V; 1076 1077 if (dte_v && dom_id) { 1078 pci_seg->old_dev_tbl_cpy[devid].data[0] = old_devtb[devid].data[0]; 1079 pci_seg->old_dev_tbl_cpy[devid].data[1] = old_devtb[devid].data[1]; 1080 __set_bit(dom_id, amd_iommu_pd_alloc_bitmap); 1081 /* If gcr3 table existed, mask it out */ 1082 if (old_devtb[devid].data[0] & DTE_FLAG_GV) { 1083 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B; 1084 tmp |= DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C; 1085 pci_seg->old_dev_tbl_cpy[devid].data[1] &= ~tmp; 1086 tmp = DTE_GCR3_VAL_A(~0ULL) << DTE_GCR3_SHIFT_A; 1087 tmp |= DTE_FLAG_GV; 1088 pci_seg->old_dev_tbl_cpy[devid].data[0] &= ~tmp; 1089 } 1090 } 1091 1092 irq_v = old_devtb[devid].data[2] & DTE_IRQ_REMAP_ENABLE; 1093 int_ctl = old_devtb[devid].data[2] & DTE_IRQ_REMAP_INTCTL_MASK; 1094 int_tab_len = old_devtb[devid].data[2] & DTE_INTTABLEN_MASK; 1095 if (irq_v && (int_ctl || int_tab_len)) { 1096 if ((int_ctl != DTE_IRQ_REMAP_INTCTL) || 1097 (int_tab_len != DTE_INTTABLEN)) { 1098 pr_err("Wrong old irq remapping flag: %#x\n", devid); 1099 memunmap(old_devtb); 1100 return false; 1101 } 1102 1103 pci_seg->old_dev_tbl_cpy[devid].data[2] = old_devtb[devid].data[2]; 1104 } 1105 } 1106 memunmap(old_devtb); 1107 1108 return true; 1109 } 1110 1111 static bool copy_device_table(void) 1112 { 1113 struct amd_iommu *iommu; 1114 struct amd_iommu_pci_seg *pci_seg; 1115 1116 if (!amd_iommu_pre_enabled) 1117 return false; 1118 1119 pr_warn("Translation is already enabled - trying to copy translation structures\n"); 1120 1121 /* 1122 * All IOMMUs within PCI segment shares common device table. 1123 * Hence copy device table only once per PCI segment. 1124 */ 1125 for_each_pci_segment(pci_seg) { 1126 for_each_iommu(iommu) { 1127 if (pci_seg->id != iommu->pci_seg->id) 1128 continue; 1129 if (!__copy_device_table(iommu)) 1130 return false; 1131 break; 1132 } 1133 } 1134 1135 return true; 1136 } 1137 1138 void amd_iommu_apply_erratum_63(u16 devid) 1139 { 1140 int sysmgt; 1141 1142 sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) | 1143 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1); 1144 1145 if (sysmgt == 0x01) 1146 set_dev_entry_bit(devid, DEV_ENTRY_IW); 1147 } 1148 1149 /* Writes the specific IOMMU for a device into the rlookup table */ 1150 static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid) 1151 { 1152 amd_iommu_rlookup_table[devid] = iommu; 1153 } 1154 1155 /* 1156 * This function takes the device specific flags read from the ACPI 1157 * table and sets up the device table entry with that information 1158 */ 1159 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu, 1160 u16 devid, u32 flags, u32 ext_flags) 1161 { 1162 if (flags & ACPI_DEVFLAG_INITPASS) 1163 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS); 1164 if (flags & ACPI_DEVFLAG_EXTINT) 1165 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS); 1166 if (flags & ACPI_DEVFLAG_NMI) 1167 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS); 1168 if (flags & ACPI_DEVFLAG_SYSMGT1) 1169 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1); 1170 if (flags & ACPI_DEVFLAG_SYSMGT2) 1171 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2); 1172 if (flags & ACPI_DEVFLAG_LINT0) 1173 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS); 1174 if (flags & ACPI_DEVFLAG_LINT1) 1175 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS); 1176 1177 amd_iommu_apply_erratum_63(devid); 1178 1179 set_iommu_for_device(iommu, devid); 1180 } 1181 1182 int __init add_special_device(u8 type, u8 id, u16 *devid, bool cmd_line) 1183 { 1184 struct devid_map *entry; 1185 struct list_head *list; 1186 1187 if (type == IVHD_SPECIAL_IOAPIC) 1188 list = &ioapic_map; 1189 else if (type == IVHD_SPECIAL_HPET) 1190 list = &hpet_map; 1191 else 1192 return -EINVAL; 1193 1194 list_for_each_entry(entry, list, list) { 1195 if (!(entry->id == id && entry->cmd_line)) 1196 continue; 1197 1198 pr_info("Command-line override present for %s id %d - ignoring\n", 1199 type == IVHD_SPECIAL_IOAPIC ? "IOAPIC" : "HPET", id); 1200 1201 *devid = entry->devid; 1202 1203 return 0; 1204 } 1205 1206 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 1207 if (!entry) 1208 return -ENOMEM; 1209 1210 entry->id = id; 1211 entry->devid = *devid; 1212 entry->cmd_line = cmd_line; 1213 1214 list_add_tail(&entry->list, list); 1215 1216 return 0; 1217 } 1218 1219 static int __init add_acpi_hid_device(u8 *hid, u8 *uid, u16 *devid, 1220 bool cmd_line) 1221 { 1222 struct acpihid_map_entry *entry; 1223 struct list_head *list = &acpihid_map; 1224 1225 list_for_each_entry(entry, list, list) { 1226 if (strcmp(entry->hid, hid) || 1227 (*uid && *entry->uid && strcmp(entry->uid, uid)) || 1228 !entry->cmd_line) 1229 continue; 1230 1231 pr_info("Command-line override for hid:%s uid:%s\n", 1232 hid, uid); 1233 *devid = entry->devid; 1234 return 0; 1235 } 1236 1237 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 1238 if (!entry) 1239 return -ENOMEM; 1240 1241 memcpy(entry->uid, uid, strlen(uid)); 1242 memcpy(entry->hid, hid, strlen(hid)); 1243 entry->devid = *devid; 1244 entry->cmd_line = cmd_line; 1245 entry->root_devid = (entry->devid & (~0x7)); 1246 1247 pr_info("%s, add hid:%s, uid:%s, rdevid:%d\n", 1248 entry->cmd_line ? "cmd" : "ivrs", 1249 entry->hid, entry->uid, entry->root_devid); 1250 1251 list_add_tail(&entry->list, list); 1252 return 0; 1253 } 1254 1255 static int __init add_early_maps(void) 1256 { 1257 int i, ret; 1258 1259 for (i = 0; i < early_ioapic_map_size; ++i) { 1260 ret = add_special_device(IVHD_SPECIAL_IOAPIC, 1261 early_ioapic_map[i].id, 1262 &early_ioapic_map[i].devid, 1263 early_ioapic_map[i].cmd_line); 1264 if (ret) 1265 return ret; 1266 } 1267 1268 for (i = 0; i < early_hpet_map_size; ++i) { 1269 ret = add_special_device(IVHD_SPECIAL_HPET, 1270 early_hpet_map[i].id, 1271 &early_hpet_map[i].devid, 1272 early_hpet_map[i].cmd_line); 1273 if (ret) 1274 return ret; 1275 } 1276 1277 for (i = 0; i < early_acpihid_map_size; ++i) { 1278 ret = add_acpi_hid_device(early_acpihid_map[i].hid, 1279 early_acpihid_map[i].uid, 1280 &early_acpihid_map[i].devid, 1281 early_acpihid_map[i].cmd_line); 1282 if (ret) 1283 return ret; 1284 } 1285 1286 return 0; 1287 } 1288 1289 /* 1290 * Takes a pointer to an AMD IOMMU entry in the ACPI table and 1291 * initializes the hardware and our data structures with it. 1292 */ 1293 static int __init init_iommu_from_acpi(struct amd_iommu *iommu, 1294 struct ivhd_header *h) 1295 { 1296 u8 *p = (u8 *)h; 1297 u8 *end = p, flags = 0; 1298 u16 devid = 0, devid_start = 0, devid_to = 0; 1299 u32 dev_i, ext_flags = 0; 1300 bool alias = false; 1301 struct ivhd_entry *e; 1302 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; 1303 u32 ivhd_size; 1304 int ret; 1305 1306 1307 ret = add_early_maps(); 1308 if (ret) 1309 return ret; 1310 1311 amd_iommu_apply_ivrs_quirks(); 1312 1313 /* 1314 * First save the recommended feature enable bits from ACPI 1315 */ 1316 iommu->acpi_flags = h->flags; 1317 1318 /* 1319 * Done. Now parse the device entries 1320 */ 1321 ivhd_size = get_ivhd_header_size(h); 1322 if (!ivhd_size) { 1323 pr_err("Unsupported IVHD type %#x\n", h->type); 1324 return -EINVAL; 1325 } 1326 1327 p += ivhd_size; 1328 1329 end += h->length; 1330 1331 1332 while (p < end) { 1333 e = (struct ivhd_entry *)p; 1334 switch (e->type) { 1335 case IVHD_DEV_ALL: 1336 1337 DUMP_printk(" DEV_ALL\t\t\tflags: %02x\n", e->flags); 1338 1339 for (dev_i = 0; dev_i <= amd_iommu_last_bdf; ++dev_i) 1340 set_dev_entry_from_acpi(iommu, dev_i, e->flags, 0); 1341 break; 1342 case IVHD_DEV_SELECT: 1343 1344 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x " 1345 "flags: %02x\n", 1346 PCI_BUS_NUM(e->devid), 1347 PCI_SLOT(e->devid), 1348 PCI_FUNC(e->devid), 1349 e->flags); 1350 1351 devid = e->devid; 1352 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); 1353 break; 1354 case IVHD_DEV_SELECT_RANGE_START: 1355 1356 DUMP_printk(" DEV_SELECT_RANGE_START\t " 1357 "devid: %02x:%02x.%x flags: %02x\n", 1358 PCI_BUS_NUM(e->devid), 1359 PCI_SLOT(e->devid), 1360 PCI_FUNC(e->devid), 1361 e->flags); 1362 1363 devid_start = e->devid; 1364 flags = e->flags; 1365 ext_flags = 0; 1366 alias = false; 1367 break; 1368 case IVHD_DEV_ALIAS: 1369 1370 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x " 1371 "flags: %02x devid_to: %02x:%02x.%x\n", 1372 PCI_BUS_NUM(e->devid), 1373 PCI_SLOT(e->devid), 1374 PCI_FUNC(e->devid), 1375 e->flags, 1376 PCI_BUS_NUM(e->ext >> 8), 1377 PCI_SLOT(e->ext >> 8), 1378 PCI_FUNC(e->ext >> 8)); 1379 1380 devid = e->devid; 1381 devid_to = e->ext >> 8; 1382 set_dev_entry_from_acpi(iommu, devid , e->flags, 0); 1383 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0); 1384 pci_seg->alias_table[devid] = devid_to; 1385 break; 1386 case IVHD_DEV_ALIAS_RANGE: 1387 1388 DUMP_printk(" DEV_ALIAS_RANGE\t\t " 1389 "devid: %02x:%02x.%x flags: %02x " 1390 "devid_to: %02x:%02x.%x\n", 1391 PCI_BUS_NUM(e->devid), 1392 PCI_SLOT(e->devid), 1393 PCI_FUNC(e->devid), 1394 e->flags, 1395 PCI_BUS_NUM(e->ext >> 8), 1396 PCI_SLOT(e->ext >> 8), 1397 PCI_FUNC(e->ext >> 8)); 1398 1399 devid_start = e->devid; 1400 flags = e->flags; 1401 devid_to = e->ext >> 8; 1402 ext_flags = 0; 1403 alias = true; 1404 break; 1405 case IVHD_DEV_EXT_SELECT: 1406 1407 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x " 1408 "flags: %02x ext: %08x\n", 1409 PCI_BUS_NUM(e->devid), 1410 PCI_SLOT(e->devid), 1411 PCI_FUNC(e->devid), 1412 e->flags, e->ext); 1413 1414 devid = e->devid; 1415 set_dev_entry_from_acpi(iommu, devid, e->flags, 1416 e->ext); 1417 break; 1418 case IVHD_DEV_EXT_SELECT_RANGE: 1419 1420 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: " 1421 "%02x:%02x.%x flags: %02x ext: %08x\n", 1422 PCI_BUS_NUM(e->devid), 1423 PCI_SLOT(e->devid), 1424 PCI_FUNC(e->devid), 1425 e->flags, e->ext); 1426 1427 devid_start = e->devid; 1428 flags = e->flags; 1429 ext_flags = e->ext; 1430 alias = false; 1431 break; 1432 case IVHD_DEV_RANGE_END: 1433 1434 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n", 1435 PCI_BUS_NUM(e->devid), 1436 PCI_SLOT(e->devid), 1437 PCI_FUNC(e->devid)); 1438 1439 devid = e->devid; 1440 for (dev_i = devid_start; dev_i <= devid; ++dev_i) { 1441 if (alias) { 1442 pci_seg->alias_table[dev_i] = devid_to; 1443 set_dev_entry_from_acpi(iommu, 1444 devid_to, flags, ext_flags); 1445 } 1446 set_dev_entry_from_acpi(iommu, dev_i, 1447 flags, ext_flags); 1448 } 1449 break; 1450 case IVHD_DEV_SPECIAL: { 1451 u8 handle, type; 1452 const char *var; 1453 u16 devid; 1454 int ret; 1455 1456 handle = e->ext & 0xff; 1457 devid = (e->ext >> 8) & 0xffff; 1458 type = (e->ext >> 24) & 0xff; 1459 1460 if (type == IVHD_SPECIAL_IOAPIC) 1461 var = "IOAPIC"; 1462 else if (type == IVHD_SPECIAL_HPET) 1463 var = "HPET"; 1464 else 1465 var = "UNKNOWN"; 1466 1467 DUMP_printk(" DEV_SPECIAL(%s[%d])\t\tdevid: %02x:%02x.%x\n", 1468 var, (int)handle, 1469 PCI_BUS_NUM(devid), 1470 PCI_SLOT(devid), 1471 PCI_FUNC(devid)); 1472 1473 ret = add_special_device(type, handle, &devid, false); 1474 if (ret) 1475 return ret; 1476 1477 /* 1478 * add_special_device might update the devid in case a 1479 * command-line override is present. So call 1480 * set_dev_entry_from_acpi after add_special_device. 1481 */ 1482 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); 1483 1484 break; 1485 } 1486 case IVHD_DEV_ACPI_HID: { 1487 u16 devid; 1488 u8 hid[ACPIHID_HID_LEN]; 1489 u8 uid[ACPIHID_UID_LEN]; 1490 int ret; 1491 1492 if (h->type != 0x40) { 1493 pr_err(FW_BUG "Invalid IVHD device type %#x\n", 1494 e->type); 1495 break; 1496 } 1497 1498 BUILD_BUG_ON(sizeof(e->ext_hid) != ACPIHID_HID_LEN - 1); 1499 memcpy(hid, &e->ext_hid, ACPIHID_HID_LEN - 1); 1500 hid[ACPIHID_HID_LEN - 1] = '\0'; 1501 1502 if (!(*hid)) { 1503 pr_err(FW_BUG "Invalid HID.\n"); 1504 break; 1505 } 1506 1507 uid[0] = '\0'; 1508 switch (e->uidf) { 1509 case UID_NOT_PRESENT: 1510 1511 if (e->uidl != 0) 1512 pr_warn(FW_BUG "Invalid UID length.\n"); 1513 1514 break; 1515 case UID_IS_INTEGER: 1516 1517 sprintf(uid, "%d", e->uid); 1518 1519 break; 1520 case UID_IS_CHARACTER: 1521 1522 memcpy(uid, &e->uid, e->uidl); 1523 uid[e->uidl] = '\0'; 1524 1525 break; 1526 default: 1527 break; 1528 } 1529 1530 devid = e->devid; 1531 DUMP_printk(" DEV_ACPI_HID(%s[%s])\t\tdevid: %02x:%02x.%x\n", 1532 hid, uid, 1533 PCI_BUS_NUM(devid), 1534 PCI_SLOT(devid), 1535 PCI_FUNC(devid)); 1536 1537 flags = e->flags; 1538 1539 ret = add_acpi_hid_device(hid, uid, &devid, false); 1540 if (ret) 1541 return ret; 1542 1543 /* 1544 * add_special_device might update the devid in case a 1545 * command-line override is present. So call 1546 * set_dev_entry_from_acpi after add_special_device. 1547 */ 1548 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); 1549 1550 break; 1551 } 1552 default: 1553 break; 1554 } 1555 1556 p += ivhd_entry_length(p); 1557 } 1558 1559 return 0; 1560 } 1561 1562 /* Allocate PCI segment data structure */ 1563 static struct amd_iommu_pci_seg *__init alloc_pci_segment(u16 id, 1564 struct acpi_table_header *ivrs_base) 1565 { 1566 struct amd_iommu_pci_seg *pci_seg; 1567 int last_bdf; 1568 1569 /* 1570 * First parse ACPI tables to find the largest Bus/Dev/Func we need to 1571 * handle in this PCI segment. Upon this information the shared data 1572 * structures for the PCI segments in the system will be allocated. 1573 */ 1574 last_bdf = find_last_devid_acpi(ivrs_base, id); 1575 if (last_bdf < 0) 1576 return NULL; 1577 1578 pci_seg = kzalloc(sizeof(struct amd_iommu_pci_seg), GFP_KERNEL); 1579 if (pci_seg == NULL) 1580 return NULL; 1581 1582 pci_seg->last_bdf = last_bdf; 1583 DUMP_printk("PCI segment : 0x%0x, last bdf : 0x%04x\n", id, last_bdf); 1584 1585 pci_seg->id = id; 1586 init_llist_head(&pci_seg->dev_data_list); 1587 INIT_LIST_HEAD(&pci_seg->unity_map); 1588 list_add_tail(&pci_seg->list, &amd_iommu_pci_seg_list); 1589 1590 if (alloc_dev_table(pci_seg)) 1591 return NULL; 1592 if (alloc_alias_table(pci_seg)) 1593 return NULL; 1594 if (alloc_rlookup_table(pci_seg)) 1595 return NULL; 1596 1597 return pci_seg; 1598 } 1599 1600 static struct amd_iommu_pci_seg *__init get_pci_segment(u16 id, 1601 struct acpi_table_header *ivrs_base) 1602 { 1603 struct amd_iommu_pci_seg *pci_seg; 1604 1605 for_each_pci_segment(pci_seg) { 1606 if (pci_seg->id == id) 1607 return pci_seg; 1608 } 1609 1610 return alloc_pci_segment(id, ivrs_base); 1611 } 1612 1613 static void __init free_pci_segments(void) 1614 { 1615 struct amd_iommu_pci_seg *pci_seg, *next; 1616 1617 for_each_pci_segment_safe(pci_seg, next) { 1618 list_del(&pci_seg->list); 1619 free_irq_lookup_table(pci_seg); 1620 free_rlookup_table(pci_seg); 1621 free_alias_table(pci_seg); 1622 free_dev_table(pci_seg); 1623 kfree(pci_seg); 1624 } 1625 } 1626 1627 static void __init free_iommu_one(struct amd_iommu *iommu) 1628 { 1629 free_cwwb_sem(iommu); 1630 free_command_buffer(iommu); 1631 free_event_buffer(iommu); 1632 free_ppr_log(iommu); 1633 free_ga_log(iommu); 1634 iommu_unmap_mmio_space(iommu); 1635 } 1636 1637 static void __init free_iommu_all(void) 1638 { 1639 struct amd_iommu *iommu, *next; 1640 1641 for_each_iommu_safe(iommu, next) { 1642 list_del(&iommu->list); 1643 free_iommu_one(iommu); 1644 kfree(iommu); 1645 } 1646 } 1647 1648 /* 1649 * Family15h Model 10h-1fh erratum 746 (IOMMU Logging May Stall Translations) 1650 * Workaround: 1651 * BIOS should disable L2B micellaneous clock gating by setting 1652 * L2_L2B_CK_GATE_CONTROL[CKGateL2BMiscDisable](D0F2xF4_x90[2]) = 1b 1653 */ 1654 static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu) 1655 { 1656 u32 value; 1657 1658 if ((boot_cpu_data.x86 != 0x15) || 1659 (boot_cpu_data.x86_model < 0x10) || 1660 (boot_cpu_data.x86_model > 0x1f)) 1661 return; 1662 1663 pci_write_config_dword(iommu->dev, 0xf0, 0x90); 1664 pci_read_config_dword(iommu->dev, 0xf4, &value); 1665 1666 if (value & BIT(2)) 1667 return; 1668 1669 /* Select NB indirect register 0x90 and enable writing */ 1670 pci_write_config_dword(iommu->dev, 0xf0, 0x90 | (1 << 8)); 1671 1672 pci_write_config_dword(iommu->dev, 0xf4, value | 0x4); 1673 pci_info(iommu->dev, "Applying erratum 746 workaround\n"); 1674 1675 /* Clear the enable writing bit */ 1676 pci_write_config_dword(iommu->dev, 0xf0, 0x90); 1677 } 1678 1679 /* 1680 * Family15h Model 30h-3fh (IOMMU Mishandles ATS Write Permission) 1681 * Workaround: 1682 * BIOS should enable ATS write permission check by setting 1683 * L2_DEBUG_3[AtsIgnoreIWDis](D0F2xF4_x47[0]) = 1b 1684 */ 1685 static void amd_iommu_ats_write_check_workaround(struct amd_iommu *iommu) 1686 { 1687 u32 value; 1688 1689 if ((boot_cpu_data.x86 != 0x15) || 1690 (boot_cpu_data.x86_model < 0x30) || 1691 (boot_cpu_data.x86_model > 0x3f)) 1692 return; 1693 1694 /* Test L2_DEBUG_3[AtsIgnoreIWDis] == 1 */ 1695 value = iommu_read_l2(iommu, 0x47); 1696 1697 if (value & BIT(0)) 1698 return; 1699 1700 /* Set L2_DEBUG_3[AtsIgnoreIWDis] = 1 */ 1701 iommu_write_l2(iommu, 0x47, value | BIT(0)); 1702 1703 pci_info(iommu->dev, "Applying ATS write check workaround\n"); 1704 } 1705 1706 /* 1707 * This function glues the initialization function for one IOMMU 1708 * together and also allocates the command buffer and programs the 1709 * hardware. It does NOT enable the IOMMU. This is done afterwards. 1710 */ 1711 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h, 1712 struct acpi_table_header *ivrs_base) 1713 { 1714 struct amd_iommu_pci_seg *pci_seg; 1715 int ret; 1716 1717 pci_seg = get_pci_segment(h->pci_seg, ivrs_base); 1718 if (pci_seg == NULL) 1719 return -ENOMEM; 1720 iommu->pci_seg = pci_seg; 1721 1722 raw_spin_lock_init(&iommu->lock); 1723 iommu->cmd_sem_val = 0; 1724 1725 /* Add IOMMU to internal data structures */ 1726 list_add_tail(&iommu->list, &amd_iommu_list); 1727 iommu->index = amd_iommus_present++; 1728 1729 if (unlikely(iommu->index >= MAX_IOMMUS)) { 1730 WARN(1, "System has more IOMMUs than supported by this driver\n"); 1731 return -ENOSYS; 1732 } 1733 1734 /* Index is fine - add IOMMU to the array */ 1735 amd_iommus[iommu->index] = iommu; 1736 1737 /* 1738 * Copy data from ACPI table entry to the iommu struct 1739 */ 1740 iommu->devid = h->devid; 1741 iommu->cap_ptr = h->cap_ptr; 1742 iommu->mmio_phys = h->mmio_phys; 1743 1744 switch (h->type) { 1745 case 0x10: 1746 /* Check if IVHD EFR contains proper max banks/counters */ 1747 if ((h->efr_attr != 0) && 1748 ((h->efr_attr & (0xF << 13)) != 0) && 1749 ((h->efr_attr & (0x3F << 17)) != 0)) 1750 iommu->mmio_phys_end = MMIO_REG_END_OFFSET; 1751 else 1752 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET; 1753 1754 /* 1755 * Note: GA (128-bit IRTE) mode requires cmpxchg16b supports. 1756 * GAM also requires GA mode. Therefore, we need to 1757 * check cmpxchg16b support before enabling it. 1758 */ 1759 if (!boot_cpu_has(X86_FEATURE_CX16) || 1760 ((h->efr_attr & (0x1 << IOMMU_FEAT_GASUP_SHIFT)) == 0)) 1761 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY; 1762 break; 1763 case 0x11: 1764 case 0x40: 1765 if (h->efr_reg & (1 << 9)) 1766 iommu->mmio_phys_end = MMIO_REG_END_OFFSET; 1767 else 1768 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET; 1769 1770 /* 1771 * Note: GA (128-bit IRTE) mode requires cmpxchg16b supports. 1772 * XT, GAM also requires GA mode. Therefore, we need to 1773 * check cmpxchg16b support before enabling them. 1774 */ 1775 if (!boot_cpu_has(X86_FEATURE_CX16) || 1776 ((h->efr_reg & (0x1 << IOMMU_EFR_GASUP_SHIFT)) == 0)) { 1777 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY; 1778 break; 1779 } 1780 1781 if (h->efr_reg & BIT(IOMMU_EFR_XTSUP_SHIFT)) 1782 amd_iommu_xt_mode = IRQ_REMAP_X2APIC_MODE; 1783 1784 early_iommu_features_init(iommu, h); 1785 1786 break; 1787 default: 1788 return -EINVAL; 1789 } 1790 1791 iommu->mmio_base = iommu_map_mmio_space(iommu->mmio_phys, 1792 iommu->mmio_phys_end); 1793 if (!iommu->mmio_base) 1794 return -ENOMEM; 1795 1796 if (alloc_cwwb_sem(iommu)) 1797 return -ENOMEM; 1798 1799 if (alloc_command_buffer(iommu)) 1800 return -ENOMEM; 1801 1802 if (alloc_event_buffer(iommu)) 1803 return -ENOMEM; 1804 1805 iommu->int_enabled = false; 1806 1807 init_translation_status(iommu); 1808 if (translation_pre_enabled(iommu) && !is_kdump_kernel()) { 1809 iommu_disable(iommu); 1810 clear_translation_pre_enabled(iommu); 1811 pr_warn("Translation was enabled for IOMMU:%d but we are not in kdump mode\n", 1812 iommu->index); 1813 } 1814 if (amd_iommu_pre_enabled) 1815 amd_iommu_pre_enabled = translation_pre_enabled(iommu); 1816 1817 ret = init_iommu_from_acpi(iommu, h); 1818 if (ret) 1819 return ret; 1820 1821 if (amd_iommu_irq_remap) { 1822 ret = amd_iommu_create_irq_domain(iommu); 1823 if (ret) 1824 return ret; 1825 } 1826 1827 /* 1828 * Make sure IOMMU is not considered to translate itself. The IVRS 1829 * table tells us so, but this is a lie! 1830 */ 1831 amd_iommu_rlookup_table[iommu->devid] = NULL; 1832 1833 return 0; 1834 } 1835 1836 /** 1837 * get_highest_supported_ivhd_type - Look up the appropriate IVHD type 1838 * @ivrs: Pointer to the IVRS header 1839 * 1840 * This function search through all IVDB of the maximum supported IVHD 1841 */ 1842 static u8 get_highest_supported_ivhd_type(struct acpi_table_header *ivrs) 1843 { 1844 u8 *base = (u8 *)ivrs; 1845 struct ivhd_header *ivhd = (struct ivhd_header *) 1846 (base + IVRS_HEADER_LENGTH); 1847 u8 last_type = ivhd->type; 1848 u16 devid = ivhd->devid; 1849 1850 while (((u8 *)ivhd - base < ivrs->length) && 1851 (ivhd->type <= ACPI_IVHD_TYPE_MAX_SUPPORTED)) { 1852 u8 *p = (u8 *) ivhd; 1853 1854 if (ivhd->devid == devid) 1855 last_type = ivhd->type; 1856 ivhd = (struct ivhd_header *)(p + ivhd->length); 1857 } 1858 1859 return last_type; 1860 } 1861 1862 /* 1863 * Iterates over all IOMMU entries in the ACPI table, allocates the 1864 * IOMMU structure and initializes it with init_iommu_one() 1865 */ 1866 static int __init init_iommu_all(struct acpi_table_header *table) 1867 { 1868 u8 *p = (u8 *)table, *end = (u8 *)table; 1869 struct ivhd_header *h; 1870 struct amd_iommu *iommu; 1871 int ret; 1872 1873 end += table->length; 1874 p += IVRS_HEADER_LENGTH; 1875 1876 while (p < end) { 1877 h = (struct ivhd_header *)p; 1878 if (*p == amd_iommu_target_ivhd_type) { 1879 1880 DUMP_printk("device: %02x:%02x.%01x cap: %04x " 1881 "seg: %d flags: %01x info %04x\n", 1882 PCI_BUS_NUM(h->devid), PCI_SLOT(h->devid), 1883 PCI_FUNC(h->devid), h->cap_ptr, 1884 h->pci_seg, h->flags, h->info); 1885 DUMP_printk(" mmio-addr: %016llx\n", 1886 h->mmio_phys); 1887 1888 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL); 1889 if (iommu == NULL) 1890 return -ENOMEM; 1891 1892 ret = init_iommu_one(iommu, h, table); 1893 if (ret) 1894 return ret; 1895 } 1896 p += h->length; 1897 1898 } 1899 WARN_ON(p != end); 1900 1901 return 0; 1902 } 1903 1904 static void init_iommu_perf_ctr(struct amd_iommu *iommu) 1905 { 1906 u64 val; 1907 struct pci_dev *pdev = iommu->dev; 1908 1909 if (!iommu_feature(iommu, FEATURE_PC)) 1910 return; 1911 1912 amd_iommu_pc_present = true; 1913 1914 pci_info(pdev, "IOMMU performance counters supported\n"); 1915 1916 val = readl(iommu->mmio_base + MMIO_CNTR_CONF_OFFSET); 1917 iommu->max_banks = (u8) ((val >> 12) & 0x3f); 1918 iommu->max_counters = (u8) ((val >> 7) & 0xf); 1919 1920 return; 1921 } 1922 1923 static ssize_t amd_iommu_show_cap(struct device *dev, 1924 struct device_attribute *attr, 1925 char *buf) 1926 { 1927 struct amd_iommu *iommu = dev_to_amd_iommu(dev); 1928 return sprintf(buf, "%x\n", iommu->cap); 1929 } 1930 static DEVICE_ATTR(cap, S_IRUGO, amd_iommu_show_cap, NULL); 1931 1932 static ssize_t amd_iommu_show_features(struct device *dev, 1933 struct device_attribute *attr, 1934 char *buf) 1935 { 1936 struct amd_iommu *iommu = dev_to_amd_iommu(dev); 1937 return sprintf(buf, "%llx\n", iommu->features); 1938 } 1939 static DEVICE_ATTR(features, S_IRUGO, amd_iommu_show_features, NULL); 1940 1941 static struct attribute *amd_iommu_attrs[] = { 1942 &dev_attr_cap.attr, 1943 &dev_attr_features.attr, 1944 NULL, 1945 }; 1946 1947 static struct attribute_group amd_iommu_group = { 1948 .name = "amd-iommu", 1949 .attrs = amd_iommu_attrs, 1950 }; 1951 1952 static const struct attribute_group *amd_iommu_groups[] = { 1953 &amd_iommu_group, 1954 NULL, 1955 }; 1956 1957 /* 1958 * Note: IVHD 0x11 and 0x40 also contains exact copy 1959 * of the IOMMU Extended Feature Register [MMIO Offset 0030h]. 1960 * Default to EFR in IVHD since it is available sooner (i.e. before PCI init). 1961 */ 1962 static void __init late_iommu_features_init(struct amd_iommu *iommu) 1963 { 1964 u64 features; 1965 1966 if (!(iommu->cap & (1 << IOMMU_CAP_EFR))) 1967 return; 1968 1969 /* read extended feature bits */ 1970 features = readq(iommu->mmio_base + MMIO_EXT_FEATURES); 1971 1972 if (!iommu->features) { 1973 iommu->features = features; 1974 return; 1975 } 1976 1977 /* 1978 * Sanity check and warn if EFR values from 1979 * IVHD and MMIO conflict. 1980 */ 1981 if (features != iommu->features) 1982 pr_warn(FW_WARN "EFR mismatch. Use IVHD EFR (%#llx : %#llx).\n", 1983 features, iommu->features); 1984 } 1985 1986 static int __init iommu_init_pci(struct amd_iommu *iommu) 1987 { 1988 int cap_ptr = iommu->cap_ptr; 1989 int ret; 1990 1991 iommu->dev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(iommu->devid), 1992 iommu->devid & 0xff); 1993 if (!iommu->dev) 1994 return -ENODEV; 1995 1996 /* Prevent binding other PCI device drivers to IOMMU devices */ 1997 iommu->dev->match_driver = false; 1998 1999 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET, 2000 &iommu->cap); 2001 2002 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB))) 2003 amd_iommu_iotlb_sup = false; 2004 2005 late_iommu_features_init(iommu); 2006 2007 if (iommu_feature(iommu, FEATURE_GT)) { 2008 int glxval; 2009 u32 max_pasid; 2010 u64 pasmax; 2011 2012 pasmax = iommu->features & FEATURE_PASID_MASK; 2013 pasmax >>= FEATURE_PASID_SHIFT; 2014 max_pasid = (1 << (pasmax + 1)) - 1; 2015 2016 amd_iommu_max_pasid = min(amd_iommu_max_pasid, max_pasid); 2017 2018 BUG_ON(amd_iommu_max_pasid & ~PASID_MASK); 2019 2020 glxval = iommu->features & FEATURE_GLXVAL_MASK; 2021 glxval >>= FEATURE_GLXVAL_SHIFT; 2022 2023 if (amd_iommu_max_glx_val == -1) 2024 amd_iommu_max_glx_val = glxval; 2025 else 2026 amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval); 2027 } 2028 2029 if (iommu_feature(iommu, FEATURE_GT) && 2030 iommu_feature(iommu, FEATURE_PPR)) { 2031 iommu->is_iommu_v2 = true; 2032 amd_iommu_v2_present = true; 2033 } 2034 2035 if (iommu_feature(iommu, FEATURE_PPR) && alloc_ppr_log(iommu)) 2036 return -ENOMEM; 2037 2038 ret = iommu_init_ga_log(iommu); 2039 if (ret) 2040 return ret; 2041 2042 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE)) { 2043 pr_info("Using strict mode due to virtualization\n"); 2044 iommu_set_dma_strict(); 2045 amd_iommu_np_cache = true; 2046 } 2047 2048 init_iommu_perf_ctr(iommu); 2049 2050 if (is_rd890_iommu(iommu->dev)) { 2051 int i, j; 2052 2053 iommu->root_pdev = 2054 pci_get_domain_bus_and_slot(0, iommu->dev->bus->number, 2055 PCI_DEVFN(0, 0)); 2056 2057 /* 2058 * Some rd890 systems may not be fully reconfigured by the 2059 * BIOS, so it's necessary for us to store this information so 2060 * it can be reprogrammed on resume 2061 */ 2062 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4, 2063 &iommu->stored_addr_lo); 2064 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8, 2065 &iommu->stored_addr_hi); 2066 2067 /* Low bit locks writes to configuration space */ 2068 iommu->stored_addr_lo &= ~1; 2069 2070 for (i = 0; i < 6; i++) 2071 for (j = 0; j < 0x12; j++) 2072 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j); 2073 2074 for (i = 0; i < 0x83; i++) 2075 iommu->stored_l2[i] = iommu_read_l2(iommu, i); 2076 } 2077 2078 amd_iommu_erratum_746_workaround(iommu); 2079 amd_iommu_ats_write_check_workaround(iommu); 2080 2081 ret = iommu_device_sysfs_add(&iommu->iommu, &iommu->dev->dev, 2082 amd_iommu_groups, "ivhd%d", iommu->index); 2083 if (ret) 2084 return ret; 2085 2086 iommu_device_register(&iommu->iommu, &amd_iommu_ops, NULL); 2087 2088 return pci_enable_device(iommu->dev); 2089 } 2090 2091 static void print_iommu_info(void) 2092 { 2093 static const char * const feat_str[] = { 2094 "PreF", "PPR", "X2APIC", "NX", "GT", "[5]", 2095 "IA", "GA", "HE", "PC" 2096 }; 2097 struct amd_iommu *iommu; 2098 2099 for_each_iommu(iommu) { 2100 struct pci_dev *pdev = iommu->dev; 2101 int i; 2102 2103 pci_info(pdev, "Found IOMMU cap 0x%x\n", iommu->cap_ptr); 2104 2105 if (iommu->cap & (1 << IOMMU_CAP_EFR)) { 2106 pr_info("Extended features (%#llx):", iommu->features); 2107 2108 for (i = 0; i < ARRAY_SIZE(feat_str); ++i) { 2109 if (iommu_feature(iommu, (1ULL << i))) 2110 pr_cont(" %s", feat_str[i]); 2111 } 2112 2113 if (iommu->features & FEATURE_GAM_VAPIC) 2114 pr_cont(" GA_vAPIC"); 2115 2116 pr_cont("\n"); 2117 } 2118 } 2119 if (irq_remapping_enabled) { 2120 pr_info("Interrupt remapping enabled\n"); 2121 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) 2122 pr_info("Virtual APIC enabled\n"); 2123 if (amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE) 2124 pr_info("X2APIC enabled\n"); 2125 } 2126 } 2127 2128 static int __init amd_iommu_init_pci(void) 2129 { 2130 struct amd_iommu *iommu; 2131 int ret; 2132 2133 for_each_iommu(iommu) { 2134 ret = iommu_init_pci(iommu); 2135 if (ret) { 2136 pr_err("IOMMU%d: Failed to initialize IOMMU Hardware (error=%d)!\n", 2137 iommu->index, ret); 2138 goto out; 2139 } 2140 /* Need to setup range after PCI init */ 2141 iommu_set_cwwb_range(iommu); 2142 } 2143 2144 /* 2145 * Order is important here to make sure any unity map requirements are 2146 * fulfilled. The unity mappings are created and written to the device 2147 * table during the amd_iommu_init_api() call. 2148 * 2149 * After that we call init_device_table_dma() to make sure any 2150 * uninitialized DTE will block DMA, and in the end we flush the caches 2151 * of all IOMMUs to make sure the changes to the device table are 2152 * active. 2153 */ 2154 ret = amd_iommu_init_api(); 2155 if (ret) { 2156 pr_err("IOMMU: Failed to initialize IOMMU-API interface (error=%d)!\n", 2157 ret); 2158 goto out; 2159 } 2160 2161 init_device_table_dma(); 2162 2163 for_each_iommu(iommu) 2164 iommu_flush_all_caches(iommu); 2165 2166 print_iommu_info(); 2167 2168 out: 2169 return ret; 2170 } 2171 2172 /**************************************************************************** 2173 * 2174 * The following functions initialize the MSI interrupts for all IOMMUs 2175 * in the system. It's a bit challenging because there could be multiple 2176 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per 2177 * pci_dev. 2178 * 2179 ****************************************************************************/ 2180 2181 static int iommu_setup_msi(struct amd_iommu *iommu) 2182 { 2183 int r; 2184 2185 r = pci_enable_msi(iommu->dev); 2186 if (r) 2187 return r; 2188 2189 r = request_threaded_irq(iommu->dev->irq, 2190 amd_iommu_int_handler, 2191 amd_iommu_int_thread, 2192 0, "AMD-Vi", 2193 iommu); 2194 2195 if (r) { 2196 pci_disable_msi(iommu->dev); 2197 return r; 2198 } 2199 2200 return 0; 2201 } 2202 2203 union intcapxt { 2204 u64 capxt; 2205 struct { 2206 u64 reserved_0 : 2, 2207 dest_mode_logical : 1, 2208 reserved_1 : 5, 2209 destid_0_23 : 24, 2210 vector : 8, 2211 reserved_2 : 16, 2212 destid_24_31 : 8; 2213 }; 2214 } __attribute__ ((packed)); 2215 2216 2217 static struct irq_chip intcapxt_controller; 2218 2219 static int intcapxt_irqdomain_activate(struct irq_domain *domain, 2220 struct irq_data *irqd, bool reserve) 2221 { 2222 return 0; 2223 } 2224 2225 static void intcapxt_irqdomain_deactivate(struct irq_domain *domain, 2226 struct irq_data *irqd) 2227 { 2228 } 2229 2230 2231 static int intcapxt_irqdomain_alloc(struct irq_domain *domain, unsigned int virq, 2232 unsigned int nr_irqs, void *arg) 2233 { 2234 struct irq_alloc_info *info = arg; 2235 int i, ret; 2236 2237 if (!info || info->type != X86_IRQ_ALLOC_TYPE_AMDVI) 2238 return -EINVAL; 2239 2240 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg); 2241 if (ret < 0) 2242 return ret; 2243 2244 for (i = virq; i < virq + nr_irqs; i++) { 2245 struct irq_data *irqd = irq_domain_get_irq_data(domain, i); 2246 2247 irqd->chip = &intcapxt_controller; 2248 irqd->chip_data = info->data; 2249 __irq_set_handler(i, handle_edge_irq, 0, "edge"); 2250 } 2251 2252 return ret; 2253 } 2254 2255 static void intcapxt_irqdomain_free(struct irq_domain *domain, unsigned int virq, 2256 unsigned int nr_irqs) 2257 { 2258 irq_domain_free_irqs_top(domain, virq, nr_irqs); 2259 } 2260 2261 2262 static void intcapxt_unmask_irq(struct irq_data *irqd) 2263 { 2264 struct amd_iommu *iommu = irqd->chip_data; 2265 struct irq_cfg *cfg = irqd_cfg(irqd); 2266 union intcapxt xt; 2267 2268 xt.capxt = 0ULL; 2269 xt.dest_mode_logical = apic->dest_mode_logical; 2270 xt.vector = cfg->vector; 2271 xt.destid_0_23 = cfg->dest_apicid & GENMASK(23, 0); 2272 xt.destid_24_31 = cfg->dest_apicid >> 24; 2273 2274 /** 2275 * Current IOMMU implementation uses the same IRQ for all 2276 * 3 IOMMU interrupts. 2277 */ 2278 writeq(xt.capxt, iommu->mmio_base + MMIO_INTCAPXT_EVT_OFFSET); 2279 writeq(xt.capxt, iommu->mmio_base + MMIO_INTCAPXT_PPR_OFFSET); 2280 writeq(xt.capxt, iommu->mmio_base + MMIO_INTCAPXT_GALOG_OFFSET); 2281 } 2282 2283 static void intcapxt_mask_irq(struct irq_data *irqd) 2284 { 2285 struct amd_iommu *iommu = irqd->chip_data; 2286 2287 writeq(0, iommu->mmio_base + MMIO_INTCAPXT_EVT_OFFSET); 2288 writeq(0, iommu->mmio_base + MMIO_INTCAPXT_PPR_OFFSET); 2289 writeq(0, iommu->mmio_base + MMIO_INTCAPXT_GALOG_OFFSET); 2290 } 2291 2292 2293 static int intcapxt_set_affinity(struct irq_data *irqd, 2294 const struct cpumask *mask, bool force) 2295 { 2296 struct irq_data *parent = irqd->parent_data; 2297 int ret; 2298 2299 ret = parent->chip->irq_set_affinity(parent, mask, force); 2300 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE) 2301 return ret; 2302 return 0; 2303 } 2304 2305 static int intcapxt_set_wake(struct irq_data *irqd, unsigned int on) 2306 { 2307 return on ? -EOPNOTSUPP : 0; 2308 } 2309 2310 static struct irq_chip intcapxt_controller = { 2311 .name = "IOMMU-MSI", 2312 .irq_unmask = intcapxt_unmask_irq, 2313 .irq_mask = intcapxt_mask_irq, 2314 .irq_ack = irq_chip_ack_parent, 2315 .irq_retrigger = irq_chip_retrigger_hierarchy, 2316 .irq_set_affinity = intcapxt_set_affinity, 2317 .irq_set_wake = intcapxt_set_wake, 2318 .flags = IRQCHIP_MASK_ON_SUSPEND, 2319 }; 2320 2321 static const struct irq_domain_ops intcapxt_domain_ops = { 2322 .alloc = intcapxt_irqdomain_alloc, 2323 .free = intcapxt_irqdomain_free, 2324 .activate = intcapxt_irqdomain_activate, 2325 .deactivate = intcapxt_irqdomain_deactivate, 2326 }; 2327 2328 2329 static struct irq_domain *iommu_irqdomain; 2330 2331 static struct irq_domain *iommu_get_irqdomain(void) 2332 { 2333 struct fwnode_handle *fn; 2334 2335 /* No need for locking here (yet) as the init is single-threaded */ 2336 if (iommu_irqdomain) 2337 return iommu_irqdomain; 2338 2339 fn = irq_domain_alloc_named_fwnode("AMD-Vi-MSI"); 2340 if (!fn) 2341 return NULL; 2342 2343 iommu_irqdomain = irq_domain_create_hierarchy(x86_vector_domain, 0, 0, 2344 fn, &intcapxt_domain_ops, 2345 NULL); 2346 if (!iommu_irqdomain) 2347 irq_domain_free_fwnode(fn); 2348 2349 return iommu_irqdomain; 2350 } 2351 2352 static int iommu_setup_intcapxt(struct amd_iommu *iommu) 2353 { 2354 struct irq_domain *domain; 2355 struct irq_alloc_info info; 2356 int irq, ret; 2357 2358 domain = iommu_get_irqdomain(); 2359 if (!domain) 2360 return -ENXIO; 2361 2362 init_irq_alloc_info(&info, NULL); 2363 info.type = X86_IRQ_ALLOC_TYPE_AMDVI; 2364 info.data = iommu; 2365 2366 irq = irq_domain_alloc_irqs(domain, 1, NUMA_NO_NODE, &info); 2367 if (irq < 0) { 2368 irq_domain_remove(domain); 2369 return irq; 2370 } 2371 2372 ret = request_threaded_irq(irq, amd_iommu_int_handler, 2373 amd_iommu_int_thread, 0, "AMD-Vi", iommu); 2374 if (ret) { 2375 irq_domain_free_irqs(irq, 1); 2376 irq_domain_remove(domain); 2377 return ret; 2378 } 2379 2380 return 0; 2381 } 2382 2383 static int iommu_init_irq(struct amd_iommu *iommu) 2384 { 2385 int ret; 2386 2387 if (iommu->int_enabled) 2388 goto enable_faults; 2389 2390 if (amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE) 2391 ret = iommu_setup_intcapxt(iommu); 2392 else if (iommu->dev->msi_cap) 2393 ret = iommu_setup_msi(iommu); 2394 else 2395 ret = -ENODEV; 2396 2397 if (ret) 2398 return ret; 2399 2400 iommu->int_enabled = true; 2401 enable_faults: 2402 2403 if (amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE) 2404 iommu_feature_enable(iommu, CONTROL_INTCAPXT_EN); 2405 2406 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN); 2407 2408 if (iommu->ppr_log != NULL) 2409 iommu_feature_enable(iommu, CONTROL_PPRINT_EN); 2410 2411 iommu_ga_log_enable(iommu); 2412 2413 return 0; 2414 } 2415 2416 /**************************************************************************** 2417 * 2418 * The next functions belong to the third pass of parsing the ACPI 2419 * table. In this last pass the memory mapping requirements are 2420 * gathered (like exclusion and unity mapping ranges). 2421 * 2422 ****************************************************************************/ 2423 2424 static void __init free_unity_maps(void) 2425 { 2426 struct unity_map_entry *entry, *next; 2427 struct amd_iommu_pci_seg *p, *pci_seg; 2428 2429 for_each_pci_segment_safe(pci_seg, p) { 2430 list_for_each_entry_safe(entry, next, &pci_seg->unity_map, list) { 2431 list_del(&entry->list); 2432 kfree(entry); 2433 } 2434 } 2435 } 2436 2437 /* called for unity map ACPI definition */ 2438 static int __init init_unity_map_range(struct ivmd_header *m, 2439 struct acpi_table_header *ivrs_base) 2440 { 2441 struct unity_map_entry *e = NULL; 2442 struct amd_iommu_pci_seg *pci_seg; 2443 char *s; 2444 2445 pci_seg = get_pci_segment(m->pci_seg, ivrs_base); 2446 if (pci_seg == NULL) 2447 return -ENOMEM; 2448 2449 e = kzalloc(sizeof(*e), GFP_KERNEL); 2450 if (e == NULL) 2451 return -ENOMEM; 2452 2453 switch (m->type) { 2454 default: 2455 kfree(e); 2456 return 0; 2457 case ACPI_IVMD_TYPE: 2458 s = "IVMD_TYPEi\t\t\t"; 2459 e->devid_start = e->devid_end = m->devid; 2460 break; 2461 case ACPI_IVMD_TYPE_ALL: 2462 s = "IVMD_TYPE_ALL\t\t"; 2463 e->devid_start = 0; 2464 e->devid_end = amd_iommu_last_bdf; 2465 break; 2466 case ACPI_IVMD_TYPE_RANGE: 2467 s = "IVMD_TYPE_RANGE\t\t"; 2468 e->devid_start = m->devid; 2469 e->devid_end = m->aux; 2470 break; 2471 } 2472 e->address_start = PAGE_ALIGN(m->range_start); 2473 e->address_end = e->address_start + PAGE_ALIGN(m->range_length); 2474 e->prot = m->flags >> 1; 2475 2476 /* 2477 * Treat per-device exclusion ranges as r/w unity-mapped regions 2478 * since some buggy BIOSes might lead to the overwritten exclusion 2479 * range (exclusion_start and exclusion_length members). This 2480 * happens when there are multiple exclusion ranges (IVMD entries) 2481 * defined in ACPI table. 2482 */ 2483 if (m->flags & IVMD_FLAG_EXCL_RANGE) 2484 e->prot = (IVMD_FLAG_IW | IVMD_FLAG_IR) >> 1; 2485 2486 DUMP_printk("%s devid_start: %04x:%02x:%02x.%x devid_end: " 2487 "%04x:%02x:%02x.%x range_start: %016llx range_end: %016llx" 2488 " flags: %x\n", s, m->pci_seg, 2489 PCI_BUS_NUM(e->devid_start), PCI_SLOT(e->devid_start), 2490 PCI_FUNC(e->devid_start), m->pci_seg, 2491 PCI_BUS_NUM(e->devid_end), 2492 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end), 2493 e->address_start, e->address_end, m->flags); 2494 2495 list_add_tail(&e->list, &pci_seg->unity_map); 2496 2497 return 0; 2498 } 2499 2500 /* iterates over all memory definitions we find in the ACPI table */ 2501 static int __init init_memory_definitions(struct acpi_table_header *table) 2502 { 2503 u8 *p = (u8 *)table, *end = (u8 *)table; 2504 struct ivmd_header *m; 2505 2506 end += table->length; 2507 p += IVRS_HEADER_LENGTH; 2508 2509 while (p < end) { 2510 m = (struct ivmd_header *)p; 2511 if (m->flags & (IVMD_FLAG_UNITY_MAP | IVMD_FLAG_EXCL_RANGE)) 2512 init_unity_map_range(m, table); 2513 2514 p += m->length; 2515 } 2516 2517 return 0; 2518 } 2519 2520 /* 2521 * Init the device table to not allow DMA access for devices 2522 */ 2523 static void init_device_table_dma(void) 2524 { 2525 u32 devid; 2526 2527 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) { 2528 set_dev_entry_bit(devid, DEV_ENTRY_VALID); 2529 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION); 2530 } 2531 } 2532 2533 static void __init uninit_device_table_dma(void) 2534 { 2535 u32 devid; 2536 2537 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) { 2538 amd_iommu_dev_table[devid].data[0] = 0ULL; 2539 amd_iommu_dev_table[devid].data[1] = 0ULL; 2540 } 2541 } 2542 2543 static void init_device_table(void) 2544 { 2545 u32 devid; 2546 2547 if (!amd_iommu_irq_remap) 2548 return; 2549 2550 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) 2551 set_dev_entry_bit(devid, DEV_ENTRY_IRQ_TBL_EN); 2552 } 2553 2554 static void iommu_init_flags(struct amd_iommu *iommu) 2555 { 2556 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ? 2557 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) : 2558 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN); 2559 2560 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ? 2561 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) : 2562 iommu_feature_disable(iommu, CONTROL_PASSPW_EN); 2563 2564 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ? 2565 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) : 2566 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN); 2567 2568 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ? 2569 iommu_feature_enable(iommu, CONTROL_ISOC_EN) : 2570 iommu_feature_disable(iommu, CONTROL_ISOC_EN); 2571 2572 /* 2573 * make IOMMU memory accesses cache coherent 2574 */ 2575 iommu_feature_enable(iommu, CONTROL_COHERENT_EN); 2576 2577 /* Set IOTLB invalidation timeout to 1s */ 2578 iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S); 2579 } 2580 2581 static void iommu_apply_resume_quirks(struct amd_iommu *iommu) 2582 { 2583 int i, j; 2584 u32 ioc_feature_control; 2585 struct pci_dev *pdev = iommu->root_pdev; 2586 2587 /* RD890 BIOSes may not have completely reconfigured the iommu */ 2588 if (!is_rd890_iommu(iommu->dev) || !pdev) 2589 return; 2590 2591 /* 2592 * First, we need to ensure that the iommu is enabled. This is 2593 * controlled by a register in the northbridge 2594 */ 2595 2596 /* Select Northbridge indirect register 0x75 and enable writing */ 2597 pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7)); 2598 pci_read_config_dword(pdev, 0x64, &ioc_feature_control); 2599 2600 /* Enable the iommu */ 2601 if (!(ioc_feature_control & 0x1)) 2602 pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1); 2603 2604 /* Restore the iommu BAR */ 2605 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, 2606 iommu->stored_addr_lo); 2607 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8, 2608 iommu->stored_addr_hi); 2609 2610 /* Restore the l1 indirect regs for each of the 6 l1s */ 2611 for (i = 0; i < 6; i++) 2612 for (j = 0; j < 0x12; j++) 2613 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]); 2614 2615 /* Restore the l2 indirect regs */ 2616 for (i = 0; i < 0x83; i++) 2617 iommu_write_l2(iommu, i, iommu->stored_l2[i]); 2618 2619 /* Lock PCI setup registers */ 2620 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, 2621 iommu->stored_addr_lo | 1); 2622 } 2623 2624 static void iommu_enable_ga(struct amd_iommu *iommu) 2625 { 2626 #ifdef CONFIG_IRQ_REMAP 2627 switch (amd_iommu_guest_ir) { 2628 case AMD_IOMMU_GUEST_IR_VAPIC: 2629 iommu_feature_enable(iommu, CONTROL_GAM_EN); 2630 fallthrough; 2631 case AMD_IOMMU_GUEST_IR_LEGACY_GA: 2632 iommu_feature_enable(iommu, CONTROL_GA_EN); 2633 iommu->irte_ops = &irte_128_ops; 2634 break; 2635 default: 2636 iommu->irte_ops = &irte_32_ops; 2637 break; 2638 } 2639 #endif 2640 } 2641 2642 static void early_enable_iommu(struct amd_iommu *iommu) 2643 { 2644 iommu_disable(iommu); 2645 iommu_init_flags(iommu); 2646 iommu_set_device_table(iommu); 2647 iommu_enable_command_buffer(iommu); 2648 iommu_enable_event_buffer(iommu); 2649 iommu_set_exclusion_range(iommu); 2650 iommu_enable_ga(iommu); 2651 iommu_enable_xt(iommu); 2652 iommu_enable(iommu); 2653 iommu_flush_all_caches(iommu); 2654 } 2655 2656 /* 2657 * This function finally enables all IOMMUs found in the system after 2658 * they have been initialized. 2659 * 2660 * Or if in kdump kernel and IOMMUs are all pre-enabled, try to copy 2661 * the old content of device table entries. Not this case or copy failed, 2662 * just continue as normal kernel does. 2663 */ 2664 static void early_enable_iommus(void) 2665 { 2666 struct amd_iommu *iommu; 2667 struct amd_iommu_pci_seg *pci_seg; 2668 2669 if (!copy_device_table()) { 2670 /* 2671 * If come here because of failure in copying device table from old 2672 * kernel with all IOMMUs enabled, print error message and try to 2673 * free allocated old_dev_tbl_cpy. 2674 */ 2675 if (amd_iommu_pre_enabled) 2676 pr_err("Failed to copy DEV table from previous kernel.\n"); 2677 2678 for_each_pci_segment(pci_seg) { 2679 if (pci_seg->old_dev_tbl_cpy != NULL) { 2680 free_pages((unsigned long)pci_seg->old_dev_tbl_cpy, 2681 get_order(dev_table_size)); 2682 pci_seg->old_dev_tbl_cpy = NULL; 2683 } 2684 } 2685 2686 for_each_iommu(iommu) { 2687 clear_translation_pre_enabled(iommu); 2688 early_enable_iommu(iommu); 2689 } 2690 } else { 2691 pr_info("Copied DEV table from previous kernel.\n"); 2692 2693 for_each_pci_segment(pci_seg) { 2694 free_pages((unsigned long)pci_seg->dev_table, 2695 get_order(dev_table_size)); 2696 pci_seg->dev_table = pci_seg->old_dev_tbl_cpy; 2697 } 2698 2699 for_each_iommu(iommu) { 2700 iommu_disable_command_buffer(iommu); 2701 iommu_disable_event_buffer(iommu); 2702 iommu_enable_command_buffer(iommu); 2703 iommu_enable_event_buffer(iommu); 2704 iommu_enable_ga(iommu); 2705 iommu_enable_xt(iommu); 2706 iommu_set_device_table(iommu); 2707 iommu_flush_all_caches(iommu); 2708 } 2709 } 2710 2711 #ifdef CONFIG_IRQ_REMAP 2712 /* 2713 * Note: We have already checked GASup from IVRS table. 2714 * Now, we need to make sure that GAMSup is set. 2715 */ 2716 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) && 2717 !check_feature_on_all_iommus(FEATURE_GAM_VAPIC)) 2718 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA; 2719 2720 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) 2721 amd_iommu_irq_ops.capability |= (1 << IRQ_POSTING_CAP); 2722 #endif 2723 } 2724 2725 static void enable_iommus_v2(void) 2726 { 2727 struct amd_iommu *iommu; 2728 2729 for_each_iommu(iommu) { 2730 iommu_enable_ppr_log(iommu); 2731 iommu_enable_gt(iommu); 2732 } 2733 } 2734 2735 static void enable_iommus(void) 2736 { 2737 early_enable_iommus(); 2738 2739 enable_iommus_v2(); 2740 } 2741 2742 static void disable_iommus(void) 2743 { 2744 struct amd_iommu *iommu; 2745 2746 for_each_iommu(iommu) 2747 iommu_disable(iommu); 2748 2749 #ifdef CONFIG_IRQ_REMAP 2750 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) 2751 amd_iommu_irq_ops.capability &= ~(1 << IRQ_POSTING_CAP); 2752 #endif 2753 } 2754 2755 /* 2756 * Suspend/Resume support 2757 * disable suspend until real resume implemented 2758 */ 2759 2760 static void amd_iommu_resume(void) 2761 { 2762 struct amd_iommu *iommu; 2763 2764 for_each_iommu(iommu) 2765 iommu_apply_resume_quirks(iommu); 2766 2767 /* re-load the hardware */ 2768 enable_iommus(); 2769 2770 amd_iommu_enable_interrupts(); 2771 } 2772 2773 static int amd_iommu_suspend(void) 2774 { 2775 /* disable IOMMUs to go out of the way for BIOS */ 2776 disable_iommus(); 2777 2778 return 0; 2779 } 2780 2781 static struct syscore_ops amd_iommu_syscore_ops = { 2782 .suspend = amd_iommu_suspend, 2783 .resume = amd_iommu_resume, 2784 }; 2785 2786 static void __init free_iommu_resources(void) 2787 { 2788 kmemleak_free(irq_lookup_table); 2789 free_pages((unsigned long)irq_lookup_table, 2790 get_order(rlookup_table_size)); 2791 irq_lookup_table = NULL; 2792 2793 kmem_cache_destroy(amd_iommu_irq_cache); 2794 amd_iommu_irq_cache = NULL; 2795 2796 free_pages((unsigned long)amd_iommu_rlookup_table, 2797 get_order(rlookup_table_size)); 2798 amd_iommu_rlookup_table = NULL; 2799 2800 free_pages((unsigned long)amd_iommu_alias_table, 2801 get_order(alias_table_size)); 2802 amd_iommu_alias_table = NULL; 2803 2804 free_pages((unsigned long)amd_iommu_dev_table, 2805 get_order(dev_table_size)); 2806 amd_iommu_dev_table = NULL; 2807 2808 free_iommu_all(); 2809 free_pci_segments(); 2810 } 2811 2812 /* SB IOAPIC is always on this device in AMD systems */ 2813 #define IOAPIC_SB_DEVID ((0x00 << 8) | PCI_DEVFN(0x14, 0)) 2814 2815 static bool __init check_ioapic_information(void) 2816 { 2817 const char *fw_bug = FW_BUG; 2818 bool ret, has_sb_ioapic; 2819 int idx; 2820 2821 has_sb_ioapic = false; 2822 ret = false; 2823 2824 /* 2825 * If we have map overrides on the kernel command line the 2826 * messages in this function might not describe firmware bugs 2827 * anymore - so be careful 2828 */ 2829 if (cmdline_maps) 2830 fw_bug = ""; 2831 2832 for (idx = 0; idx < nr_ioapics; idx++) { 2833 int devid, id = mpc_ioapic_id(idx); 2834 2835 devid = get_ioapic_devid(id); 2836 if (devid < 0) { 2837 pr_err("%s: IOAPIC[%d] not in IVRS table\n", 2838 fw_bug, id); 2839 ret = false; 2840 } else if (devid == IOAPIC_SB_DEVID) { 2841 has_sb_ioapic = true; 2842 ret = true; 2843 } 2844 } 2845 2846 if (!has_sb_ioapic) { 2847 /* 2848 * We expect the SB IOAPIC to be listed in the IVRS 2849 * table. The system timer is connected to the SB IOAPIC 2850 * and if we don't have it in the list the system will 2851 * panic at boot time. This situation usually happens 2852 * when the BIOS is buggy and provides us the wrong 2853 * device id for the IOAPIC in the system. 2854 */ 2855 pr_err("%s: No southbridge IOAPIC found\n", fw_bug); 2856 } 2857 2858 if (!ret) 2859 pr_err("Disabling interrupt remapping\n"); 2860 2861 return ret; 2862 } 2863 2864 static void __init free_dma_resources(void) 2865 { 2866 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap, 2867 get_order(MAX_DOMAIN_ID/8)); 2868 amd_iommu_pd_alloc_bitmap = NULL; 2869 2870 free_unity_maps(); 2871 } 2872 2873 static void __init ivinfo_init(void *ivrs) 2874 { 2875 amd_iommu_ivinfo = *((u32 *)(ivrs + IOMMU_IVINFO_OFFSET)); 2876 } 2877 2878 /* 2879 * This is the hardware init function for AMD IOMMU in the system. 2880 * This function is called either from amd_iommu_init or from the interrupt 2881 * remapping setup code. 2882 * 2883 * This function basically parses the ACPI table for AMD IOMMU (IVRS) 2884 * four times: 2885 * 2886 * 1 pass) Discover the most comprehensive IVHD type to use. 2887 * 2888 * 2 pass) Find the highest PCI device id the driver has to handle. 2889 * Upon this information the size of the data structures is 2890 * determined that needs to be allocated. 2891 * 2892 * 3 pass) Initialize the data structures just allocated with the 2893 * information in the ACPI table about available AMD IOMMUs 2894 * in the system. It also maps the PCI devices in the 2895 * system to specific IOMMUs 2896 * 2897 * 4 pass) After the basic data structures are allocated and 2898 * initialized we update them with information about memory 2899 * remapping requirements parsed out of the ACPI table in 2900 * this last pass. 2901 * 2902 * After everything is set up the IOMMUs are enabled and the necessary 2903 * hotplug and suspend notifiers are registered. 2904 */ 2905 static int __init early_amd_iommu_init(void) 2906 { 2907 struct acpi_table_header *ivrs_base; 2908 int remap_cache_sz, ret; 2909 acpi_status status; 2910 2911 if (!amd_iommu_detected) 2912 return -ENODEV; 2913 2914 status = acpi_get_table("IVRS", 0, &ivrs_base); 2915 if (status == AE_NOT_FOUND) 2916 return -ENODEV; 2917 else if (ACPI_FAILURE(status)) { 2918 const char *err = acpi_format_exception(status); 2919 pr_err("IVRS table error: %s\n", err); 2920 return -EINVAL; 2921 } 2922 2923 /* 2924 * Validate checksum here so we don't need to do it when 2925 * we actually parse the table 2926 */ 2927 ret = check_ivrs_checksum(ivrs_base); 2928 if (ret) 2929 goto out; 2930 2931 ivinfo_init(ivrs_base); 2932 2933 amd_iommu_target_ivhd_type = get_highest_supported_ivhd_type(ivrs_base); 2934 DUMP_printk("Using IVHD type %#x\n", amd_iommu_target_ivhd_type); 2935 2936 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE); 2937 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE); 2938 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE); 2939 2940 /* Device table - directly used by all IOMMUs */ 2941 ret = -ENOMEM; 2942 amd_iommu_dev_table = (void *)__get_free_pages( 2943 GFP_KERNEL | __GFP_ZERO | GFP_DMA32, 2944 get_order(dev_table_size)); 2945 if (amd_iommu_dev_table == NULL) 2946 goto out; 2947 2948 /* 2949 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the 2950 * IOMMU see for that device 2951 */ 2952 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL, 2953 get_order(alias_table_size)); 2954 if (amd_iommu_alias_table == NULL) 2955 goto out; 2956 2957 /* IOMMU rlookup table - find the IOMMU for a specific device */ 2958 amd_iommu_rlookup_table = (void *)__get_free_pages( 2959 GFP_KERNEL | __GFP_ZERO, 2960 get_order(rlookup_table_size)); 2961 if (amd_iommu_rlookup_table == NULL) 2962 goto out; 2963 2964 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages( 2965 GFP_KERNEL | __GFP_ZERO, 2966 get_order(MAX_DOMAIN_ID/8)); 2967 if (amd_iommu_pd_alloc_bitmap == NULL) 2968 goto out; 2969 2970 /* 2971 * never allocate domain 0 because its used as the non-allocated and 2972 * error value placeholder 2973 */ 2974 __set_bit(0, amd_iommu_pd_alloc_bitmap); 2975 2976 /* 2977 * now the data structures are allocated and basically initialized 2978 * start the real acpi table scan 2979 */ 2980 ret = init_iommu_all(ivrs_base); 2981 if (ret) 2982 goto out; 2983 2984 /* Disable any previously enabled IOMMUs */ 2985 if (!is_kdump_kernel() || amd_iommu_disabled) 2986 disable_iommus(); 2987 2988 if (amd_iommu_irq_remap) 2989 amd_iommu_irq_remap = check_ioapic_information(); 2990 2991 if (amd_iommu_irq_remap) { 2992 struct amd_iommu_pci_seg *pci_seg; 2993 /* 2994 * Interrupt remapping enabled, create kmem_cache for the 2995 * remapping tables. 2996 */ 2997 ret = -ENOMEM; 2998 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir)) 2999 remap_cache_sz = MAX_IRQS_PER_TABLE * sizeof(u32); 3000 else 3001 remap_cache_sz = MAX_IRQS_PER_TABLE * (sizeof(u64) * 2); 3002 amd_iommu_irq_cache = kmem_cache_create("irq_remap_cache", 3003 remap_cache_sz, 3004 DTE_INTTAB_ALIGNMENT, 3005 0, NULL); 3006 if (!amd_iommu_irq_cache) 3007 goto out; 3008 3009 for_each_pci_segment(pci_seg) { 3010 if (alloc_irq_lookup_table(pci_seg)) 3011 goto out; 3012 } 3013 3014 irq_lookup_table = (void *)__get_free_pages( 3015 GFP_KERNEL | __GFP_ZERO, 3016 get_order(rlookup_table_size)); 3017 kmemleak_alloc(irq_lookup_table, rlookup_table_size, 3018 1, GFP_KERNEL); 3019 if (!irq_lookup_table) 3020 goto out; 3021 } 3022 3023 ret = init_memory_definitions(ivrs_base); 3024 if (ret) 3025 goto out; 3026 3027 /* init the device table */ 3028 init_device_table(); 3029 3030 out: 3031 /* Don't leak any ACPI memory */ 3032 acpi_put_table(ivrs_base); 3033 3034 return ret; 3035 } 3036 3037 static int amd_iommu_enable_interrupts(void) 3038 { 3039 struct amd_iommu *iommu; 3040 int ret = 0; 3041 3042 for_each_iommu(iommu) { 3043 ret = iommu_init_irq(iommu); 3044 if (ret) 3045 goto out; 3046 } 3047 3048 out: 3049 return ret; 3050 } 3051 3052 static bool __init detect_ivrs(void) 3053 { 3054 struct acpi_table_header *ivrs_base; 3055 acpi_status status; 3056 int i; 3057 3058 status = acpi_get_table("IVRS", 0, &ivrs_base); 3059 if (status == AE_NOT_FOUND) 3060 return false; 3061 else if (ACPI_FAILURE(status)) { 3062 const char *err = acpi_format_exception(status); 3063 pr_err("IVRS table error: %s\n", err); 3064 return false; 3065 } 3066 3067 acpi_put_table(ivrs_base); 3068 3069 if (amd_iommu_force_enable) 3070 goto out; 3071 3072 /* Don't use IOMMU if there is Stoney Ridge graphics */ 3073 for (i = 0; i < 32; i++) { 3074 u32 pci_id; 3075 3076 pci_id = read_pci_config(0, i, 0, 0); 3077 if ((pci_id & 0xffff) == 0x1002 && (pci_id >> 16) == 0x98e4) { 3078 pr_info("Disable IOMMU on Stoney Ridge\n"); 3079 return false; 3080 } 3081 } 3082 3083 out: 3084 /* Make sure ACS will be enabled during PCI probe */ 3085 pci_request_acs(); 3086 3087 return true; 3088 } 3089 3090 /**************************************************************************** 3091 * 3092 * AMD IOMMU Initialization State Machine 3093 * 3094 ****************************************************************************/ 3095 3096 static int __init state_next(void) 3097 { 3098 int ret = 0; 3099 3100 switch (init_state) { 3101 case IOMMU_START_STATE: 3102 if (!detect_ivrs()) { 3103 init_state = IOMMU_NOT_FOUND; 3104 ret = -ENODEV; 3105 } else { 3106 init_state = IOMMU_IVRS_DETECTED; 3107 } 3108 break; 3109 case IOMMU_IVRS_DETECTED: 3110 if (amd_iommu_disabled) { 3111 init_state = IOMMU_CMDLINE_DISABLED; 3112 ret = -EINVAL; 3113 } else { 3114 ret = early_amd_iommu_init(); 3115 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_ACPI_FINISHED; 3116 } 3117 break; 3118 case IOMMU_ACPI_FINISHED: 3119 early_enable_iommus(); 3120 x86_platform.iommu_shutdown = disable_iommus; 3121 init_state = IOMMU_ENABLED; 3122 break; 3123 case IOMMU_ENABLED: 3124 register_syscore_ops(&amd_iommu_syscore_ops); 3125 ret = amd_iommu_init_pci(); 3126 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT; 3127 enable_iommus_v2(); 3128 break; 3129 case IOMMU_PCI_INIT: 3130 ret = amd_iommu_enable_interrupts(); 3131 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_INTERRUPTS_EN; 3132 break; 3133 case IOMMU_INTERRUPTS_EN: 3134 init_state = IOMMU_INITIALIZED; 3135 break; 3136 case IOMMU_INITIALIZED: 3137 /* Nothing to do */ 3138 break; 3139 case IOMMU_NOT_FOUND: 3140 case IOMMU_INIT_ERROR: 3141 case IOMMU_CMDLINE_DISABLED: 3142 /* Error states => do nothing */ 3143 ret = -EINVAL; 3144 break; 3145 default: 3146 /* Unknown state */ 3147 BUG(); 3148 } 3149 3150 if (ret) { 3151 free_dma_resources(); 3152 if (!irq_remapping_enabled) { 3153 disable_iommus(); 3154 free_iommu_resources(); 3155 } else { 3156 struct amd_iommu *iommu; 3157 3158 uninit_device_table_dma(); 3159 for_each_iommu(iommu) 3160 iommu_flush_all_caches(iommu); 3161 } 3162 } 3163 return ret; 3164 } 3165 3166 static int __init iommu_go_to_state(enum iommu_init_state state) 3167 { 3168 int ret = -EINVAL; 3169 3170 while (init_state != state) { 3171 if (init_state == IOMMU_NOT_FOUND || 3172 init_state == IOMMU_INIT_ERROR || 3173 init_state == IOMMU_CMDLINE_DISABLED) 3174 break; 3175 ret = state_next(); 3176 } 3177 3178 return ret; 3179 } 3180 3181 #ifdef CONFIG_IRQ_REMAP 3182 int __init amd_iommu_prepare(void) 3183 { 3184 int ret; 3185 3186 amd_iommu_irq_remap = true; 3187 3188 ret = iommu_go_to_state(IOMMU_ACPI_FINISHED); 3189 if (ret) { 3190 amd_iommu_irq_remap = false; 3191 return ret; 3192 } 3193 3194 return amd_iommu_irq_remap ? 0 : -ENODEV; 3195 } 3196 3197 int __init amd_iommu_enable(void) 3198 { 3199 int ret; 3200 3201 ret = iommu_go_to_state(IOMMU_ENABLED); 3202 if (ret) 3203 return ret; 3204 3205 irq_remapping_enabled = 1; 3206 return amd_iommu_xt_mode; 3207 } 3208 3209 void amd_iommu_disable(void) 3210 { 3211 amd_iommu_suspend(); 3212 } 3213 3214 int amd_iommu_reenable(int mode) 3215 { 3216 amd_iommu_resume(); 3217 3218 return 0; 3219 } 3220 3221 int __init amd_iommu_enable_faulting(void) 3222 { 3223 /* We enable MSI later when PCI is initialized */ 3224 return 0; 3225 } 3226 #endif 3227 3228 /* 3229 * This is the core init function for AMD IOMMU hardware in the system. 3230 * This function is called from the generic x86 DMA layer initialization 3231 * code. 3232 */ 3233 static int __init amd_iommu_init(void) 3234 { 3235 struct amd_iommu *iommu; 3236 int ret; 3237 3238 ret = iommu_go_to_state(IOMMU_INITIALIZED); 3239 #ifdef CONFIG_GART_IOMMU 3240 if (ret && list_empty(&amd_iommu_list)) { 3241 /* 3242 * We failed to initialize the AMD IOMMU - try fallback 3243 * to GART if possible. 3244 */ 3245 gart_iommu_init(); 3246 } 3247 #endif 3248 3249 for_each_iommu(iommu) 3250 amd_iommu_debugfs_setup(iommu); 3251 3252 return ret; 3253 } 3254 3255 static bool amd_iommu_sme_check(void) 3256 { 3257 if (!cc_platform_has(CC_ATTR_HOST_MEM_ENCRYPT) || 3258 (boot_cpu_data.x86 != 0x17)) 3259 return true; 3260 3261 /* For Fam17h, a specific level of support is required */ 3262 if (boot_cpu_data.microcode >= 0x08001205) 3263 return true; 3264 3265 if ((boot_cpu_data.microcode >= 0x08001126) && 3266 (boot_cpu_data.microcode <= 0x080011ff)) 3267 return true; 3268 3269 pr_notice("IOMMU not currently supported when SME is active\n"); 3270 3271 return false; 3272 } 3273 3274 /**************************************************************************** 3275 * 3276 * Early detect code. This code runs at IOMMU detection time in the DMA 3277 * layer. It just looks if there is an IVRS ACPI table to detect AMD 3278 * IOMMUs 3279 * 3280 ****************************************************************************/ 3281 int __init amd_iommu_detect(void) 3282 { 3283 int ret; 3284 3285 if (no_iommu || (iommu_detected && !gart_iommu_aperture)) 3286 return -ENODEV; 3287 3288 if (!amd_iommu_sme_check()) 3289 return -ENODEV; 3290 3291 ret = iommu_go_to_state(IOMMU_IVRS_DETECTED); 3292 if (ret) 3293 return ret; 3294 3295 amd_iommu_detected = true; 3296 iommu_detected = 1; 3297 x86_init.iommu.iommu_init = amd_iommu_init; 3298 3299 return 1; 3300 } 3301 3302 /**************************************************************************** 3303 * 3304 * Parsing functions for the AMD IOMMU specific kernel command line 3305 * options. 3306 * 3307 ****************************************************************************/ 3308 3309 static int __init parse_amd_iommu_dump(char *str) 3310 { 3311 amd_iommu_dump = true; 3312 3313 return 1; 3314 } 3315 3316 static int __init parse_amd_iommu_intr(char *str) 3317 { 3318 for (; *str; ++str) { 3319 if (strncmp(str, "legacy", 6) == 0) { 3320 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA; 3321 break; 3322 } 3323 if (strncmp(str, "vapic", 5) == 0) { 3324 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC; 3325 break; 3326 } 3327 } 3328 return 1; 3329 } 3330 3331 static int __init parse_amd_iommu_options(char *str) 3332 { 3333 for (; *str; ++str) { 3334 if (strncmp(str, "fullflush", 9) == 0) { 3335 pr_warn("amd_iommu=fullflush deprecated; use iommu.strict=1 instead\n"); 3336 iommu_set_dma_strict(); 3337 } 3338 if (strncmp(str, "force_enable", 12) == 0) 3339 amd_iommu_force_enable = true; 3340 if (strncmp(str, "off", 3) == 0) 3341 amd_iommu_disabled = true; 3342 if (strncmp(str, "force_isolation", 15) == 0) 3343 amd_iommu_force_isolation = true; 3344 } 3345 3346 return 1; 3347 } 3348 3349 static int __init parse_ivrs_ioapic(char *str) 3350 { 3351 unsigned int bus, dev, fn; 3352 int ret, id, i; 3353 u16 devid; 3354 3355 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn); 3356 3357 if (ret != 4) { 3358 pr_err("Invalid command line: ivrs_ioapic%s\n", str); 3359 return 1; 3360 } 3361 3362 if (early_ioapic_map_size == EARLY_MAP_SIZE) { 3363 pr_err("Early IOAPIC map overflow - ignoring ivrs_ioapic%s\n", 3364 str); 3365 return 1; 3366 } 3367 3368 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7); 3369 3370 cmdline_maps = true; 3371 i = early_ioapic_map_size++; 3372 early_ioapic_map[i].id = id; 3373 early_ioapic_map[i].devid = devid; 3374 early_ioapic_map[i].cmd_line = true; 3375 3376 return 1; 3377 } 3378 3379 static int __init parse_ivrs_hpet(char *str) 3380 { 3381 unsigned int bus, dev, fn; 3382 int ret, id, i; 3383 u16 devid; 3384 3385 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn); 3386 3387 if (ret != 4) { 3388 pr_err("Invalid command line: ivrs_hpet%s\n", str); 3389 return 1; 3390 } 3391 3392 if (early_hpet_map_size == EARLY_MAP_SIZE) { 3393 pr_err("Early HPET map overflow - ignoring ivrs_hpet%s\n", 3394 str); 3395 return 1; 3396 } 3397 3398 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7); 3399 3400 cmdline_maps = true; 3401 i = early_hpet_map_size++; 3402 early_hpet_map[i].id = id; 3403 early_hpet_map[i].devid = devid; 3404 early_hpet_map[i].cmd_line = true; 3405 3406 return 1; 3407 } 3408 3409 static int __init parse_ivrs_acpihid(char *str) 3410 { 3411 u32 bus, dev, fn; 3412 char *hid, *uid, *p; 3413 char acpiid[ACPIHID_UID_LEN + ACPIHID_HID_LEN] = {0}; 3414 int ret, i; 3415 3416 ret = sscanf(str, "[%x:%x.%x]=%s", &bus, &dev, &fn, acpiid); 3417 if (ret != 4) { 3418 pr_err("Invalid command line: ivrs_acpihid(%s)\n", str); 3419 return 1; 3420 } 3421 3422 p = acpiid; 3423 hid = strsep(&p, ":"); 3424 uid = p; 3425 3426 if (!hid || !(*hid) || !uid) { 3427 pr_err("Invalid command line: hid or uid\n"); 3428 return 1; 3429 } 3430 3431 i = early_acpihid_map_size++; 3432 memcpy(early_acpihid_map[i].hid, hid, strlen(hid)); 3433 memcpy(early_acpihid_map[i].uid, uid, strlen(uid)); 3434 early_acpihid_map[i].devid = 3435 ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7); 3436 early_acpihid_map[i].cmd_line = true; 3437 3438 return 1; 3439 } 3440 3441 __setup("amd_iommu_dump", parse_amd_iommu_dump); 3442 __setup("amd_iommu=", parse_amd_iommu_options); 3443 __setup("amd_iommu_intr=", parse_amd_iommu_intr); 3444 __setup("ivrs_ioapic", parse_ivrs_ioapic); 3445 __setup("ivrs_hpet", parse_ivrs_hpet); 3446 __setup("ivrs_acpihid", parse_ivrs_acpihid); 3447 3448 bool amd_iommu_v2_supported(void) 3449 { 3450 return amd_iommu_v2_present; 3451 } 3452 EXPORT_SYMBOL(amd_iommu_v2_supported); 3453 3454 struct amd_iommu *get_amd_iommu(unsigned int idx) 3455 { 3456 unsigned int i = 0; 3457 struct amd_iommu *iommu; 3458 3459 for_each_iommu(iommu) 3460 if (i++ == idx) 3461 return iommu; 3462 return NULL; 3463 } 3464 3465 /**************************************************************************** 3466 * 3467 * IOMMU EFR Performance Counter support functionality. This code allows 3468 * access to the IOMMU PC functionality. 3469 * 3470 ****************************************************************************/ 3471 3472 u8 amd_iommu_pc_get_max_banks(unsigned int idx) 3473 { 3474 struct amd_iommu *iommu = get_amd_iommu(idx); 3475 3476 if (iommu) 3477 return iommu->max_banks; 3478 3479 return 0; 3480 } 3481 EXPORT_SYMBOL(amd_iommu_pc_get_max_banks); 3482 3483 bool amd_iommu_pc_supported(void) 3484 { 3485 return amd_iommu_pc_present; 3486 } 3487 EXPORT_SYMBOL(amd_iommu_pc_supported); 3488 3489 u8 amd_iommu_pc_get_max_counters(unsigned int idx) 3490 { 3491 struct amd_iommu *iommu = get_amd_iommu(idx); 3492 3493 if (iommu) 3494 return iommu->max_counters; 3495 3496 return 0; 3497 } 3498 EXPORT_SYMBOL(amd_iommu_pc_get_max_counters); 3499 3500 static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, 3501 u8 fxn, u64 *value, bool is_write) 3502 { 3503 u32 offset; 3504 u32 max_offset_lim; 3505 3506 /* Make sure the IOMMU PC resource is available */ 3507 if (!amd_iommu_pc_present) 3508 return -ENODEV; 3509 3510 /* Check for valid iommu and pc register indexing */ 3511 if (WARN_ON(!iommu || (fxn > 0x28) || (fxn & 7))) 3512 return -ENODEV; 3513 3514 offset = (u32)(((0x40 | bank) << 12) | (cntr << 8) | fxn); 3515 3516 /* Limit the offset to the hw defined mmio region aperture */ 3517 max_offset_lim = (u32)(((0x40 | iommu->max_banks) << 12) | 3518 (iommu->max_counters << 8) | 0x28); 3519 if ((offset < MMIO_CNTR_REG_OFFSET) || 3520 (offset > max_offset_lim)) 3521 return -EINVAL; 3522 3523 if (is_write) { 3524 u64 val = *value & GENMASK_ULL(47, 0); 3525 3526 writel((u32)val, iommu->mmio_base + offset); 3527 writel((val >> 32), iommu->mmio_base + offset + 4); 3528 } else { 3529 *value = readl(iommu->mmio_base + offset + 4); 3530 *value <<= 32; 3531 *value |= readl(iommu->mmio_base + offset); 3532 *value &= GENMASK_ULL(47, 0); 3533 } 3534 3535 return 0; 3536 } 3537 3538 int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value) 3539 { 3540 if (!iommu) 3541 return -EINVAL; 3542 3543 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, false); 3544 } 3545 3546 int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value) 3547 { 3548 if (!iommu) 3549 return -EINVAL; 3550 3551 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, true); 3552 } 3553