1*39a53928SRohit Agarwal /* SPDX-License-Identifier: GPL-2.0-only */ 2*39a53928SRohit Agarwal /* 3*39a53928SRohit Agarwal * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 4*39a53928SRohit Agarwal */ 5*39a53928SRohit Agarwal 6*39a53928SRohit Agarwal #ifndef __DRIVERS_INTERCONNECT_QCOM_SDX65_H 7*39a53928SRohit Agarwal #define __DRIVERS_INTERCONNECT_QCOM_SDX65_H 8*39a53928SRohit Agarwal 9*39a53928SRohit Agarwal #define SDX65_MASTER_TCU_0 0 10*39a53928SRohit Agarwal #define SDX65_MASTER_LLCC 1 11*39a53928SRohit Agarwal #define SDX65_MASTER_AUDIO 2 12*39a53928SRohit Agarwal #define SDX65_MASTER_BLSP_1 3 13*39a53928SRohit Agarwal #define SDX65_MASTER_QDSS_BAM 4 14*39a53928SRohit Agarwal #define SDX65_MASTER_QPIC 5 15*39a53928SRohit Agarwal #define SDX65_MASTER_SNOC_CFG 6 16*39a53928SRohit Agarwal #define SDX65_MASTER_SPMI_FETCHER 7 17*39a53928SRohit Agarwal #define SDX65_MASTER_ANOC_SNOC 8 18*39a53928SRohit Agarwal #define SDX65_MASTER_IPA 9 19*39a53928SRohit Agarwal #define SDX65_MASTER_MEM_NOC_SNOC 10 20*39a53928SRohit Agarwal #define SDX65_MASTER_MEM_NOC_PCIE_SNOC 11 21*39a53928SRohit Agarwal #define SDX65_MASTER_SNOC_GC_MEM_NOC 12 22*39a53928SRohit Agarwal #define SDX65_MASTER_CRYPTO 13 23*39a53928SRohit Agarwal #define SDX65_MASTER_APPSS_PROC 14 24*39a53928SRohit Agarwal #define SDX65_MASTER_IPA_PCIE 15 25*39a53928SRohit Agarwal #define SDX65_MASTER_PCIE_0 16 26*39a53928SRohit Agarwal #define SDX65_MASTER_QDSS_ETR 17 27*39a53928SRohit Agarwal #define SDX65_MASTER_SDCC_1 18 28*39a53928SRohit Agarwal #define SDX65_MASTER_USB3 19 29*39a53928SRohit Agarwal #define SDX65_SLAVE_EBI1 512 30*39a53928SRohit Agarwal #define SDX65_SLAVE_AOSS 513 31*39a53928SRohit Agarwal #define SDX65_SLAVE_APPSS 514 32*39a53928SRohit Agarwal #define SDX65_SLAVE_AUDIO 515 33*39a53928SRohit Agarwal #define SDX65_SLAVE_BLSP_1 516 34*39a53928SRohit Agarwal #define SDX65_SLAVE_CLK_CTL 517 35*39a53928SRohit Agarwal #define SDX65_SLAVE_CRYPTO_0_CFG 518 36*39a53928SRohit Agarwal #define SDX65_SLAVE_CNOC_DDRSS 519 37*39a53928SRohit Agarwal #define SDX65_SLAVE_ECC_CFG 520 38*39a53928SRohit Agarwal #define SDX65_SLAVE_IMEM_CFG 521 39*39a53928SRohit Agarwal #define SDX65_SLAVE_IPA_CFG 522 40*39a53928SRohit Agarwal #define SDX65_SLAVE_CNOC_MSS 523 41*39a53928SRohit Agarwal #define SDX65_SLAVE_PCIE_PARF 524 42*39a53928SRohit Agarwal #define SDX65_SLAVE_PDM 525 43*39a53928SRohit Agarwal #define SDX65_SLAVE_PRNG 526 44*39a53928SRohit Agarwal #define SDX65_SLAVE_QDSS_CFG 527 45*39a53928SRohit Agarwal #define SDX65_SLAVE_QPIC 528 46*39a53928SRohit Agarwal #define SDX65_SLAVE_SDCC_1 529 47*39a53928SRohit Agarwal #define SDX65_SLAVE_SNOC_CFG 530 48*39a53928SRohit Agarwal #define SDX65_SLAVE_SPMI_FETCHER 531 49*39a53928SRohit Agarwal #define SDX65_SLAVE_SPMI_VGI_COEX 532 50*39a53928SRohit Agarwal #define SDX65_SLAVE_TCSR 533 51*39a53928SRohit Agarwal #define SDX65_SLAVE_TLMM 534 52*39a53928SRohit Agarwal #define SDX65_SLAVE_USB3 535 53*39a53928SRohit Agarwal #define SDX65_SLAVE_USB3_PHY_CFG 536 54*39a53928SRohit Agarwal #define SDX65_SLAVE_ANOC_SNOC 537 55*39a53928SRohit Agarwal #define SDX65_SLAVE_LLCC 538 56*39a53928SRohit Agarwal #define SDX65_SLAVE_MEM_NOC_SNOC 539 57*39a53928SRohit Agarwal #define SDX65_SLAVE_SNOC_MEM_NOC_GC 540 58*39a53928SRohit Agarwal #define SDX65_SLAVE_MEM_NOC_PCIE_SNOC 541 59*39a53928SRohit Agarwal #define SDX65_SLAVE_IMEM 542 60*39a53928SRohit Agarwal #define SDX65_SLAVE_SERVICE_SNOC 543 61*39a53928SRohit Agarwal #define SDX65_SLAVE_PCIE_0 544 62*39a53928SRohit Agarwal #define SDX65_SLAVE_QDSS_STM 545 63*39a53928SRohit Agarwal #define SDX65_SLAVE_TCU 546 64*39a53928SRohit Agarwal 65*39a53928SRohit Agarwal #endif 66