1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Qualcomm QCM2290 Network-on-Chip (NoC) QoS driver 4 * 5 * Copyright (c) 2021, Linaro Ltd. 6 * 7 */ 8 9 #include <dt-bindings/interconnect/qcom,qcm2290.h> 10 #include <linux/device.h> 11 #include <linux/interconnect-provider.h> 12 #include <linux/io.h> 13 #include <linux/module.h> 14 #include <linux/of_device.h> 15 #include <linux/of_platform.h> 16 #include <linux/platform_device.h> 17 #include <linux/regmap.h> 18 #include <linux/slab.h> 19 20 #include "icc-rpm.h" 21 22 enum { 23 QCM2290_MASTER_APPSS_PROC = 1, 24 QCM2290_MASTER_SNOC_BIMC_RT, 25 QCM2290_MASTER_SNOC_BIMC_NRT, 26 QCM2290_MASTER_SNOC_BIMC, 27 QCM2290_MASTER_TCU_0, 28 QCM2290_MASTER_GFX3D, 29 QCM2290_MASTER_SNOC_CNOC, 30 QCM2290_MASTER_QDSS_DAP, 31 QCM2290_MASTER_CRYPTO_CORE0, 32 QCM2290_MASTER_SNOC_CFG, 33 QCM2290_MASTER_TIC, 34 QCM2290_MASTER_ANOC_SNOC, 35 QCM2290_MASTER_BIMC_SNOC, 36 QCM2290_MASTER_PIMEM, 37 QCM2290_MASTER_QDSS_BAM, 38 QCM2290_MASTER_QUP_0, 39 QCM2290_MASTER_IPA, 40 QCM2290_MASTER_QDSS_ETR, 41 QCM2290_MASTER_SDCC_1, 42 QCM2290_MASTER_SDCC_2, 43 QCM2290_MASTER_QPIC, 44 QCM2290_MASTER_USB3_0, 45 QCM2290_MASTER_QUP_CORE_0, 46 QCM2290_MASTER_CAMNOC_SF, 47 QCM2290_MASTER_VIDEO_P0, 48 QCM2290_MASTER_VIDEO_PROC, 49 QCM2290_MASTER_CAMNOC_HF, 50 QCM2290_MASTER_MDP0, 51 52 QCM2290_SLAVE_EBI1, 53 QCM2290_SLAVE_BIMC_SNOC, 54 QCM2290_SLAVE_BIMC_CFG, 55 QCM2290_SLAVE_CAMERA_NRT_THROTTLE_CFG, 56 QCM2290_SLAVE_CAMERA_RT_THROTTLE_CFG, 57 QCM2290_SLAVE_CAMERA_CFG, 58 QCM2290_SLAVE_CLK_CTL, 59 QCM2290_SLAVE_CRYPTO_0_CFG, 60 QCM2290_SLAVE_DISPLAY_CFG, 61 QCM2290_SLAVE_DISPLAY_THROTTLE_CFG, 62 QCM2290_SLAVE_GPU_CFG, 63 QCM2290_SLAVE_HWKM, 64 QCM2290_SLAVE_IMEM_CFG, 65 QCM2290_SLAVE_IPA_CFG, 66 QCM2290_SLAVE_LPASS, 67 QCM2290_SLAVE_MESSAGE_RAM, 68 QCM2290_SLAVE_PDM, 69 QCM2290_SLAVE_PIMEM_CFG, 70 QCM2290_SLAVE_PKA_WRAPPER, 71 QCM2290_SLAVE_PMIC_ARB, 72 QCM2290_SLAVE_PRNG, 73 QCM2290_SLAVE_QDSS_CFG, 74 QCM2290_SLAVE_QM_CFG, 75 QCM2290_SLAVE_QM_MPU_CFG, 76 QCM2290_SLAVE_QPIC, 77 QCM2290_SLAVE_QUP_0, 78 QCM2290_SLAVE_SDCC_1, 79 QCM2290_SLAVE_SDCC_2, 80 QCM2290_SLAVE_SNOC_CFG, 81 QCM2290_SLAVE_TCSR, 82 QCM2290_SLAVE_USB3, 83 QCM2290_SLAVE_VENUS_CFG, 84 QCM2290_SLAVE_VENUS_THROTTLE_CFG, 85 QCM2290_SLAVE_VSENSE_CTRL_CFG, 86 QCM2290_SLAVE_SERVICE_CNOC, 87 QCM2290_SLAVE_APPSS, 88 QCM2290_SLAVE_SNOC_CNOC, 89 QCM2290_SLAVE_IMEM, 90 QCM2290_SLAVE_PIMEM, 91 QCM2290_SLAVE_SNOC_BIMC, 92 QCM2290_SLAVE_SERVICE_SNOC, 93 QCM2290_SLAVE_QDSS_STM, 94 QCM2290_SLAVE_TCU, 95 QCM2290_SLAVE_ANOC_SNOC, 96 QCM2290_SLAVE_QUP_CORE_0, 97 QCM2290_SLAVE_SNOC_BIMC_NRT, 98 QCM2290_SLAVE_SNOC_BIMC_RT, 99 }; 100 101 /* Master nodes */ 102 static const u16 mas_appss_proc_links[] = { 103 QCM2290_SLAVE_EBI1, 104 QCM2290_SLAVE_BIMC_SNOC, 105 }; 106 107 static struct qcom_icc_node mas_appss_proc = { 108 .id = QCM2290_MASTER_APPSS_PROC, 109 .name = "mas_apps_proc", 110 .buswidth = 16, 111 .qos.ap_owned = true, 112 .qos.qos_port = 0, 113 .qos.qos_mode = NOC_QOS_MODE_FIXED, 114 .qos.prio_level = 0, 115 .qos.areq_prio = 0, 116 .mas_rpm_id = 0, 117 .slv_rpm_id = -1, 118 .num_links = ARRAY_SIZE(mas_appss_proc_links), 119 .links = mas_appss_proc_links, 120 }; 121 122 static const u16 mas_snoc_bimc_rt_links[] = { 123 QCM2290_SLAVE_EBI1, 124 }; 125 126 static struct qcom_icc_node mas_snoc_bimc_rt = { 127 .id = QCM2290_MASTER_SNOC_BIMC_RT, 128 .name = "mas_snoc_bimc_rt", 129 .buswidth = 16, 130 .qos.ap_owned = true, 131 .qos.qos_port = 2, 132 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 133 .mas_rpm_id = 163, 134 .slv_rpm_id = -1, 135 .num_links = ARRAY_SIZE(mas_snoc_bimc_rt_links), 136 .links = mas_snoc_bimc_rt_links, 137 }; 138 139 static const u16 mas_snoc_bimc_nrt_links[] = { 140 QCM2290_SLAVE_EBI1, 141 }; 142 143 static struct qcom_icc_node mas_snoc_bimc_nrt = { 144 .id = QCM2290_MASTER_SNOC_BIMC_NRT, 145 .name = "mas_snoc_bimc_nrt", 146 .buswidth = 16, 147 .qos.ap_owned = true, 148 .qos.qos_port = 3, 149 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 150 .mas_rpm_id = 164, 151 .slv_rpm_id = -1, 152 .num_links = ARRAY_SIZE(mas_snoc_bimc_nrt_links), 153 .links = mas_snoc_bimc_nrt_links, 154 }; 155 156 static const u16 mas_snoc_bimc_links[] = { 157 QCM2290_SLAVE_EBI1, 158 }; 159 160 static struct qcom_icc_node mas_snoc_bimc = { 161 .id = QCM2290_MASTER_SNOC_BIMC, 162 .name = "mas_snoc_bimc", 163 .buswidth = 16, 164 .qos.ap_owned = true, 165 .qos.qos_port = 2, 166 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 167 .mas_rpm_id = 164, 168 .slv_rpm_id = -1, 169 .num_links = ARRAY_SIZE(mas_snoc_bimc_links), 170 .links = mas_snoc_bimc_links, 171 }; 172 173 static const u16 mas_tcu_0_links[] = { 174 QCM2290_SLAVE_EBI1, 175 QCM2290_SLAVE_BIMC_SNOC, 176 }; 177 178 static struct qcom_icc_node mas_tcu_0 = { 179 .id = QCM2290_MASTER_TCU_0, 180 .name = "mas_tcu_0", 181 .buswidth = 8, 182 .qos.ap_owned = true, 183 .qos.qos_port = 4, 184 .qos.qos_mode = NOC_QOS_MODE_FIXED, 185 .qos.prio_level = 6, 186 .qos.areq_prio = 6, 187 .mas_rpm_id = 102, 188 .slv_rpm_id = -1, 189 .num_links = ARRAY_SIZE(mas_tcu_0_links), 190 .links = mas_tcu_0_links, 191 }; 192 193 static const u16 mas_snoc_cnoc_links[] = { 194 QCM2290_SLAVE_CAMERA_RT_THROTTLE_CFG, 195 QCM2290_SLAVE_SDCC_2, 196 QCM2290_SLAVE_SDCC_1, 197 QCM2290_SLAVE_QM_CFG, 198 QCM2290_SLAVE_BIMC_CFG, 199 QCM2290_SLAVE_USB3, 200 QCM2290_SLAVE_QM_MPU_CFG, 201 QCM2290_SLAVE_CAMERA_NRT_THROTTLE_CFG, 202 QCM2290_SLAVE_QDSS_CFG, 203 QCM2290_SLAVE_PDM, 204 QCM2290_SLAVE_IPA_CFG, 205 QCM2290_SLAVE_DISPLAY_THROTTLE_CFG, 206 QCM2290_SLAVE_TCSR, 207 QCM2290_SLAVE_MESSAGE_RAM, 208 QCM2290_SLAVE_PMIC_ARB, 209 QCM2290_SLAVE_LPASS, 210 QCM2290_SLAVE_DISPLAY_CFG, 211 QCM2290_SLAVE_VENUS_CFG, 212 QCM2290_SLAVE_GPU_CFG, 213 QCM2290_SLAVE_IMEM_CFG, 214 QCM2290_SLAVE_SNOC_CFG, 215 QCM2290_SLAVE_SERVICE_CNOC, 216 QCM2290_SLAVE_VENUS_THROTTLE_CFG, 217 QCM2290_SLAVE_PKA_WRAPPER, 218 QCM2290_SLAVE_HWKM, 219 QCM2290_SLAVE_PRNG, 220 QCM2290_SLAVE_VSENSE_CTRL_CFG, 221 QCM2290_SLAVE_CRYPTO_0_CFG, 222 QCM2290_SLAVE_PIMEM_CFG, 223 QCM2290_SLAVE_QUP_0, 224 QCM2290_SLAVE_CAMERA_CFG, 225 QCM2290_SLAVE_CLK_CTL, 226 QCM2290_SLAVE_QPIC, 227 }; 228 229 static struct qcom_icc_node mas_snoc_cnoc = { 230 .id = QCM2290_MASTER_SNOC_CNOC, 231 .name = "mas_snoc_cnoc", 232 .buswidth = 8, 233 .qos.ap_owned = true, 234 .qos.qos_mode = NOC_QOS_MODE_INVALID, 235 .mas_rpm_id = 52, 236 .slv_rpm_id = -1, 237 .num_links = ARRAY_SIZE(mas_snoc_cnoc_links), 238 .links = mas_snoc_cnoc_links, 239 }; 240 241 static const u16 mas_qdss_dap_links[] = { 242 QCM2290_SLAVE_CAMERA_RT_THROTTLE_CFG, 243 QCM2290_SLAVE_SDCC_2, 244 QCM2290_SLAVE_SDCC_1, 245 QCM2290_SLAVE_QM_CFG, 246 QCM2290_SLAVE_BIMC_CFG, 247 QCM2290_SLAVE_USB3, 248 QCM2290_SLAVE_QM_MPU_CFG, 249 QCM2290_SLAVE_CAMERA_NRT_THROTTLE_CFG, 250 QCM2290_SLAVE_QDSS_CFG, 251 QCM2290_SLAVE_PDM, 252 QCM2290_SLAVE_IPA_CFG, 253 QCM2290_SLAVE_DISPLAY_THROTTLE_CFG, 254 QCM2290_SLAVE_TCSR, 255 QCM2290_SLAVE_MESSAGE_RAM, 256 QCM2290_SLAVE_PMIC_ARB, 257 QCM2290_SLAVE_LPASS, 258 QCM2290_SLAVE_DISPLAY_CFG, 259 QCM2290_SLAVE_VENUS_CFG, 260 QCM2290_SLAVE_GPU_CFG, 261 QCM2290_SLAVE_IMEM_CFG, 262 QCM2290_SLAVE_SNOC_CFG, 263 QCM2290_SLAVE_SERVICE_CNOC, 264 QCM2290_SLAVE_VENUS_THROTTLE_CFG, 265 QCM2290_SLAVE_PKA_WRAPPER, 266 QCM2290_SLAVE_HWKM, 267 QCM2290_SLAVE_PRNG, 268 QCM2290_SLAVE_VSENSE_CTRL_CFG, 269 QCM2290_SLAVE_CRYPTO_0_CFG, 270 QCM2290_SLAVE_PIMEM_CFG, 271 QCM2290_SLAVE_QUP_0, 272 QCM2290_SLAVE_CAMERA_CFG, 273 QCM2290_SLAVE_CLK_CTL, 274 QCM2290_SLAVE_QPIC, 275 }; 276 277 static struct qcom_icc_node mas_qdss_dap = { 278 .id = QCM2290_MASTER_QDSS_DAP, 279 .name = "mas_qdss_dap", 280 .buswidth = 8, 281 .qos.ap_owned = true, 282 .qos.qos_mode = NOC_QOS_MODE_INVALID, 283 .mas_rpm_id = 49, 284 .slv_rpm_id = -1, 285 .num_links = ARRAY_SIZE(mas_qdss_dap_links), 286 .links = mas_qdss_dap_links, 287 }; 288 289 static const u16 mas_crypto_core0_links[] = { 290 QCM2290_SLAVE_ANOC_SNOC 291 }; 292 293 static struct qcom_icc_node mas_crypto_core0 = { 294 .id = QCM2290_MASTER_CRYPTO_CORE0, 295 .name = "mas_crypto_core0", 296 .buswidth = 8, 297 .qos.ap_owned = true, 298 .qos.qos_port = 22, 299 .qos.qos_mode = NOC_QOS_MODE_FIXED, 300 .qos.areq_prio = 2, 301 .mas_rpm_id = 23, 302 .slv_rpm_id = -1, 303 .num_links = ARRAY_SIZE(mas_crypto_core0_links), 304 .links = mas_crypto_core0_links, 305 }; 306 307 static const u16 mas_qup_core_0_links[] = { 308 QCM2290_SLAVE_QUP_CORE_0, 309 }; 310 311 static struct qcom_icc_node mas_qup_core_0 = { 312 .id = QCM2290_MASTER_QUP_CORE_0, 313 .name = "mas_qup_core_0", 314 .buswidth = 4, 315 .mas_rpm_id = 170, 316 .slv_rpm_id = -1, 317 .num_links = ARRAY_SIZE(mas_qup_core_0_links), 318 .links = mas_qup_core_0_links, 319 }; 320 321 static const u16 mas_camnoc_sf_links[] = { 322 QCM2290_SLAVE_SNOC_BIMC_NRT, 323 }; 324 325 static struct qcom_icc_node mas_camnoc_sf = { 326 .id = QCM2290_MASTER_CAMNOC_SF, 327 .name = "mas_camnoc_sf", 328 .buswidth = 32, 329 .qos.ap_owned = true, 330 .qos.qos_port = 4, 331 .qos.qos_mode = NOC_QOS_MODE_FIXED, 332 .qos.areq_prio = 3, 333 .mas_rpm_id = 172, 334 .slv_rpm_id = -1, 335 .num_links = ARRAY_SIZE(mas_camnoc_sf_links), 336 .links = mas_camnoc_sf_links, 337 }; 338 339 static const u16 mas_camnoc_hf_links[] = { 340 QCM2290_SLAVE_SNOC_BIMC_RT, 341 }; 342 343 static struct qcom_icc_node mas_camnoc_hf = { 344 .id = QCM2290_MASTER_CAMNOC_HF, 345 .name = "mas_camnoc_hf", 346 .buswidth = 32, 347 .qos.ap_owned = true, 348 .qos.qos_port = 10, 349 .qos.qos_mode = NOC_QOS_MODE_FIXED, 350 .qos.areq_prio = 3, 351 .qos.urg_fwd_en = true, 352 .mas_rpm_id = 173, 353 .slv_rpm_id = -1, 354 .num_links = ARRAY_SIZE(mas_camnoc_hf_links), 355 .links = mas_camnoc_hf_links, 356 }; 357 358 static const u16 mas_mdp0_links[] = { 359 QCM2290_SLAVE_SNOC_BIMC_RT, 360 }; 361 362 static struct qcom_icc_node mas_mdp0 = { 363 .id = QCM2290_MASTER_MDP0, 364 .name = "mas_mdp0", 365 .buswidth = 16, 366 .qos.ap_owned = true, 367 .qos.qos_port = 5, 368 .qos.qos_mode = NOC_QOS_MODE_FIXED, 369 .qos.areq_prio = 3, 370 .qos.urg_fwd_en = true, 371 .mas_rpm_id = 8, 372 .slv_rpm_id = -1, 373 .num_links = ARRAY_SIZE(mas_mdp0_links), 374 .links = mas_mdp0_links, 375 }; 376 377 static const u16 mas_video_p0_links[] = { 378 QCM2290_SLAVE_SNOC_BIMC_NRT, 379 }; 380 381 static struct qcom_icc_node mas_video_p0 = { 382 .id = QCM2290_MASTER_VIDEO_P0, 383 .name = "mas_video_p0", 384 .buswidth = 16, 385 .qos.ap_owned = true, 386 .qos.qos_port = 9, 387 .qos.qos_mode = NOC_QOS_MODE_FIXED, 388 .qos.areq_prio = 3, 389 .qos.urg_fwd_en = true, 390 .mas_rpm_id = 9, 391 .slv_rpm_id = -1, 392 .num_links = ARRAY_SIZE(mas_video_p0_links), 393 .links = mas_video_p0_links, 394 }; 395 396 static const u16 mas_video_proc_links[] = { 397 QCM2290_SLAVE_SNOC_BIMC_NRT, 398 }; 399 400 static struct qcom_icc_node mas_video_proc = { 401 .id = QCM2290_MASTER_VIDEO_PROC, 402 .name = "mas_video_proc", 403 .buswidth = 8, 404 .qos.ap_owned = true, 405 .qos.qos_port = 13, 406 .qos.qos_mode = NOC_QOS_MODE_FIXED, 407 .qos.areq_prio = 4, 408 .mas_rpm_id = 168, 409 .slv_rpm_id = -1, 410 .num_links = ARRAY_SIZE(mas_video_proc_links), 411 .links = mas_video_proc_links, 412 }; 413 414 static const u16 mas_snoc_cfg_links[] = { 415 QCM2290_SLAVE_SERVICE_SNOC, 416 }; 417 418 static struct qcom_icc_node mas_snoc_cfg = { 419 .id = QCM2290_MASTER_SNOC_CFG, 420 .name = "mas_snoc_cfg", 421 .buswidth = 4, 422 .qos.ap_owned = true, 423 .qos.qos_mode = NOC_QOS_MODE_INVALID, 424 .mas_rpm_id = 20, 425 .slv_rpm_id = -1, 426 .num_links = ARRAY_SIZE(mas_snoc_cfg_links), 427 .links = mas_snoc_cfg_links, 428 }; 429 430 static const u16 mas_tic_links[] = { 431 QCM2290_SLAVE_PIMEM, 432 QCM2290_SLAVE_IMEM, 433 QCM2290_SLAVE_APPSS, 434 QCM2290_SLAVE_SNOC_BIMC, 435 QCM2290_SLAVE_SNOC_CNOC, 436 QCM2290_SLAVE_TCU, 437 QCM2290_SLAVE_QDSS_STM, 438 }; 439 440 static struct qcom_icc_node mas_tic = { 441 .id = QCM2290_MASTER_TIC, 442 .name = "mas_tic", 443 .buswidth = 4, 444 .qos.ap_owned = true, 445 .qos.qos_port = 8, 446 .qos.qos_mode = NOC_QOS_MODE_FIXED, 447 .qos.areq_prio = 2, 448 .mas_rpm_id = 51, 449 .slv_rpm_id = -1, 450 .num_links = ARRAY_SIZE(mas_tic_links), 451 .links = mas_tic_links, 452 }; 453 454 static const u16 mas_anoc_snoc_links[] = { 455 QCM2290_SLAVE_PIMEM, 456 QCM2290_SLAVE_IMEM, 457 QCM2290_SLAVE_APPSS, 458 QCM2290_SLAVE_SNOC_BIMC, 459 QCM2290_SLAVE_SNOC_CNOC, 460 QCM2290_SLAVE_TCU, 461 QCM2290_SLAVE_QDSS_STM, 462 }; 463 464 static struct qcom_icc_node mas_anoc_snoc = { 465 .id = QCM2290_MASTER_ANOC_SNOC, 466 .name = "mas_anoc_snoc", 467 .buswidth = 16, 468 .mas_rpm_id = 110, 469 .slv_rpm_id = -1, 470 .num_links = ARRAY_SIZE(mas_anoc_snoc_links), 471 .links = mas_anoc_snoc_links, 472 }; 473 474 static const u16 mas_bimc_snoc_links[] = { 475 QCM2290_SLAVE_PIMEM, 476 QCM2290_SLAVE_IMEM, 477 QCM2290_SLAVE_APPSS, 478 QCM2290_SLAVE_SNOC_CNOC, 479 QCM2290_SLAVE_TCU, 480 QCM2290_SLAVE_QDSS_STM, 481 }; 482 483 static struct qcom_icc_node mas_bimc_snoc = { 484 .id = QCM2290_MASTER_BIMC_SNOC, 485 .name = "mas_bimc_snoc", 486 .buswidth = 8, 487 .mas_rpm_id = 21, 488 .slv_rpm_id = -1, 489 .num_links = ARRAY_SIZE(mas_bimc_snoc_links), 490 .links = mas_bimc_snoc_links, 491 }; 492 493 static const u16 mas_pimem_links[] = { 494 QCM2290_SLAVE_IMEM, 495 QCM2290_SLAVE_SNOC_BIMC, 496 }; 497 498 static struct qcom_icc_node mas_pimem = { 499 .id = QCM2290_MASTER_PIMEM, 500 .name = "mas_pimem", 501 .buswidth = 8, 502 .qos.ap_owned = true, 503 .qos.qos_port = 20, 504 .qos.qos_mode = NOC_QOS_MODE_FIXED, 505 .qos.areq_prio = 2, 506 .mas_rpm_id = 113, 507 .slv_rpm_id = -1, 508 .num_links = ARRAY_SIZE(mas_pimem_links), 509 .links = mas_pimem_links, 510 }; 511 512 static const u16 mas_qdss_bam_links[] = { 513 QCM2290_SLAVE_ANOC_SNOC, 514 }; 515 516 static struct qcom_icc_node mas_qdss_bam = { 517 .id = QCM2290_MASTER_QDSS_BAM, 518 .name = "mas_qdss_bam", 519 .buswidth = 4, 520 .qos.ap_owned = true, 521 .qos.qos_port = 2, 522 .qos.qos_mode = NOC_QOS_MODE_FIXED, 523 .qos.areq_prio = 2, 524 .mas_rpm_id = 19, 525 .slv_rpm_id = -1, 526 .num_links = ARRAY_SIZE(mas_qdss_bam_links), 527 .links = mas_qdss_bam_links, 528 }; 529 530 static const u16 mas_qup_0_links[] = { 531 QCM2290_SLAVE_ANOC_SNOC, 532 }; 533 534 static struct qcom_icc_node mas_qup_0 = { 535 .id = QCM2290_MASTER_QUP_0, 536 .name = "mas_qup_0", 537 .buswidth = 4, 538 .qos.ap_owned = true, 539 .qos.qos_port = 0, 540 .qos.qos_mode = NOC_QOS_MODE_FIXED, 541 .qos.areq_prio = 2, 542 .mas_rpm_id = 166, 543 .slv_rpm_id = -1, 544 .num_links = ARRAY_SIZE(mas_qup_0_links), 545 .links = mas_qup_0_links, 546 }; 547 548 static const u16 mas_ipa_links[] = { 549 QCM2290_SLAVE_ANOC_SNOC, 550 }; 551 552 static struct qcom_icc_node mas_ipa = { 553 .id = QCM2290_MASTER_IPA, 554 .name = "mas_ipa", 555 .buswidth = 8, 556 .qos.ap_owned = true, 557 .qos.qos_port = 3, 558 .qos.qos_mode = NOC_QOS_MODE_FIXED, 559 .qos.areq_prio = 2, 560 .mas_rpm_id = 59, 561 .slv_rpm_id = -1, 562 .num_links = ARRAY_SIZE(mas_ipa_links), 563 .links = mas_ipa_links, 564 }; 565 566 static const u16 mas_qdss_etr_links[] = { 567 QCM2290_SLAVE_ANOC_SNOC, 568 }; 569 570 static struct qcom_icc_node mas_qdss_etr = { 571 .id = QCM2290_MASTER_QDSS_ETR, 572 .name = "mas_qdss_etr", 573 .buswidth = 8, 574 .qos.ap_owned = true, 575 .qos.qos_port = 12, 576 .qos.qos_mode = NOC_QOS_MODE_FIXED, 577 .qos.areq_prio = 2, 578 .mas_rpm_id = 31, 579 .slv_rpm_id = -1, 580 .num_links = ARRAY_SIZE(mas_qdss_etr_links), 581 .links = mas_qdss_etr_links, 582 }; 583 584 static const u16 mas_sdcc_1_links[] = { 585 QCM2290_SLAVE_ANOC_SNOC, 586 }; 587 588 static struct qcom_icc_node mas_sdcc_1 = { 589 .id = QCM2290_MASTER_SDCC_1, 590 .name = "mas_sdcc_1", 591 .buswidth = 8, 592 .qos.ap_owned = true, 593 .qos.qos_port = 17, 594 .qos.qos_mode = NOC_QOS_MODE_FIXED, 595 .qos.areq_prio = 2, 596 .mas_rpm_id = 33, 597 .slv_rpm_id = -1, 598 .num_links = ARRAY_SIZE(mas_sdcc_1_links), 599 .links = mas_sdcc_1_links, 600 }; 601 602 static const u16 mas_sdcc_2_links[] = { 603 QCM2290_SLAVE_ANOC_SNOC, 604 }; 605 606 static struct qcom_icc_node mas_sdcc_2 = { 607 .id = QCM2290_MASTER_SDCC_2, 608 .name = "mas_sdcc_2", 609 .buswidth = 8, 610 .qos.ap_owned = true, 611 .qos.qos_port = 23, 612 .qos.qos_mode = NOC_QOS_MODE_FIXED, 613 .qos.areq_prio = 2, 614 .mas_rpm_id = 35, 615 .slv_rpm_id = -1, 616 .num_links = ARRAY_SIZE(mas_sdcc_2_links), 617 .links = mas_sdcc_2_links, 618 }; 619 620 static const u16 mas_qpic_links[] = { 621 QCM2290_SLAVE_ANOC_SNOC, 622 }; 623 624 static struct qcom_icc_node mas_qpic = { 625 .id = QCM2290_MASTER_QPIC, 626 .name = "mas_qpic", 627 .buswidth = 4, 628 .qos.ap_owned = true, 629 .qos.qos_port = 1, 630 .qos.qos_mode = NOC_QOS_MODE_FIXED, 631 .qos.areq_prio = 2, 632 .mas_rpm_id = 58, 633 .slv_rpm_id = -1, 634 .num_links = ARRAY_SIZE(mas_qpic_links), 635 .links = mas_qpic_links, 636 }; 637 638 static const u16 mas_usb3_0_links[] = { 639 QCM2290_SLAVE_ANOC_SNOC, 640 }; 641 642 static struct qcom_icc_node mas_usb3_0 = { 643 .id = QCM2290_MASTER_USB3_0, 644 .name = "mas_usb3_0", 645 .buswidth = 8, 646 .qos.ap_owned = true, 647 .qos.qos_port = 24, 648 .qos.qos_mode = NOC_QOS_MODE_FIXED, 649 .qos.areq_prio = 2, 650 .mas_rpm_id = 32, 651 .slv_rpm_id = -1, 652 .num_links = ARRAY_SIZE(mas_usb3_0_links), 653 .links = mas_usb3_0_links, 654 }; 655 656 static const u16 mas_gfx3d_links[] = { 657 QCM2290_SLAVE_EBI1, 658 }; 659 660 static struct qcom_icc_node mas_gfx3d = { 661 .id = QCM2290_MASTER_GFX3D, 662 .name = "mas_gfx3d", 663 .buswidth = 32, 664 .qos.ap_owned = true, 665 .qos.qos_port = 1, 666 .qos.qos_mode = NOC_QOS_MODE_FIXED, 667 .qos.prio_level = 0, 668 .qos.areq_prio = 0, 669 .mas_rpm_id = 6, 670 .slv_rpm_id = -1, 671 .num_links = ARRAY_SIZE(mas_gfx3d_links), 672 .links = mas_gfx3d_links, 673 }; 674 675 /* Slave nodes */ 676 static struct qcom_icc_node slv_ebi1 = { 677 .name = "slv_ebi1", 678 .id = QCM2290_SLAVE_EBI1, 679 .buswidth = 8, 680 .mas_rpm_id = -1, 681 .slv_rpm_id = 0, 682 }; 683 684 static const u16 slv_bimc_snoc_links[] = { 685 QCM2290_MASTER_BIMC_SNOC, 686 }; 687 688 static struct qcom_icc_node slv_bimc_snoc = { 689 .name = "slv_bimc_snoc", 690 .id = QCM2290_SLAVE_BIMC_SNOC, 691 .buswidth = 8, 692 .mas_rpm_id = -1, 693 .slv_rpm_id = 2, 694 .num_links = ARRAY_SIZE(slv_bimc_snoc_links), 695 .links = slv_bimc_snoc_links, 696 }; 697 698 static struct qcom_icc_node slv_bimc_cfg = { 699 .name = "slv_bimc_cfg", 700 .id = QCM2290_SLAVE_BIMC_CFG, 701 .buswidth = 4, 702 .qos.ap_owned = true, 703 .qos.qos_mode = NOC_QOS_MODE_INVALID, 704 .mas_rpm_id = -1, 705 .slv_rpm_id = 56, 706 }; 707 708 static struct qcom_icc_node slv_camera_nrt_throttle_cfg = { 709 .name = "slv_camera_nrt_throttle_cfg", 710 .id = QCM2290_SLAVE_CAMERA_NRT_THROTTLE_CFG, 711 .buswidth = 4, 712 .qos.ap_owned = true, 713 .qos.qos_mode = NOC_QOS_MODE_INVALID, 714 .mas_rpm_id = -1, 715 .slv_rpm_id = 271, 716 }; 717 718 static struct qcom_icc_node slv_camera_rt_throttle_cfg = { 719 .name = "slv_camera_rt_throttle_cfg", 720 .id = QCM2290_SLAVE_CAMERA_RT_THROTTLE_CFG, 721 .buswidth = 4, 722 .qos.ap_owned = true, 723 .qos.qos_mode = NOC_QOS_MODE_INVALID, 724 .mas_rpm_id = -1, 725 .slv_rpm_id = 279, 726 }; 727 728 static struct qcom_icc_node slv_camera_cfg = { 729 .name = "slv_camera_cfg", 730 .id = QCM2290_SLAVE_CAMERA_CFG, 731 .buswidth = 4, 732 .qos.ap_owned = true, 733 .qos.qos_mode = NOC_QOS_MODE_INVALID, 734 .mas_rpm_id = -1, 735 .slv_rpm_id = 3, 736 }; 737 738 static struct qcom_icc_node slv_clk_ctl = { 739 .name = "slv_clk_ctl", 740 .id = QCM2290_SLAVE_CLK_CTL, 741 .buswidth = 4, 742 .qos.ap_owned = true, 743 .qos.qos_mode = NOC_QOS_MODE_INVALID, 744 .mas_rpm_id = -1, 745 .slv_rpm_id = 47, 746 }; 747 748 static struct qcom_icc_node slv_crypto_0_cfg = { 749 .name = "slv_crypto_0_cfg", 750 .id = QCM2290_SLAVE_CRYPTO_0_CFG, 751 .buswidth = 4, 752 .qos.ap_owned = true, 753 .qos.qos_mode = NOC_QOS_MODE_INVALID, 754 .mas_rpm_id = -1, 755 .slv_rpm_id = 52, 756 }; 757 758 static struct qcom_icc_node slv_display_cfg = { 759 .name = "slv_display_cfg", 760 .id = QCM2290_SLAVE_DISPLAY_CFG, 761 .buswidth = 4, 762 .qos.ap_owned = true, 763 .qos.qos_mode = NOC_QOS_MODE_INVALID, 764 .mas_rpm_id = -1, 765 .slv_rpm_id = 4, 766 }; 767 768 static struct qcom_icc_node slv_display_throttle_cfg = { 769 .name = "slv_display_throttle_cfg", 770 .id = QCM2290_SLAVE_DISPLAY_THROTTLE_CFG, 771 .buswidth = 4, 772 .qos.ap_owned = true, 773 .qos.qos_mode = NOC_QOS_MODE_INVALID, 774 .mas_rpm_id = -1, 775 .slv_rpm_id = 156, 776 }; 777 778 static struct qcom_icc_node slv_gpu_cfg = { 779 .name = "slv_gpu_cfg", 780 .id = QCM2290_SLAVE_GPU_CFG, 781 .buswidth = 8, 782 .qos.ap_owned = true, 783 .qos.qos_mode = NOC_QOS_MODE_INVALID, 784 .mas_rpm_id = -1, 785 .slv_rpm_id = 275, 786 }; 787 788 static struct qcom_icc_node slv_hwkm = { 789 .name = "slv_hwkm", 790 .id = QCM2290_SLAVE_HWKM, 791 .buswidth = 4, 792 .qos.ap_owned = true, 793 .qos.qos_mode = NOC_QOS_MODE_INVALID, 794 .mas_rpm_id = -1, 795 .slv_rpm_id = 280, 796 }; 797 798 static struct qcom_icc_node slv_imem_cfg = { 799 .name = "slv_imem_cfg", 800 .id = QCM2290_SLAVE_IMEM_CFG, 801 .buswidth = 4, 802 .qos.ap_owned = true, 803 .qos.qos_mode = NOC_QOS_MODE_INVALID, 804 .mas_rpm_id = -1, 805 .slv_rpm_id = 54, 806 }; 807 808 static struct qcom_icc_node slv_ipa_cfg = { 809 .name = "slv_ipa_cfg", 810 .id = QCM2290_SLAVE_IPA_CFG, 811 .buswidth = 4, 812 .qos.ap_owned = true, 813 .qos.qos_mode = NOC_QOS_MODE_INVALID, 814 .mas_rpm_id = -1, 815 .slv_rpm_id = 183, 816 }; 817 818 static struct qcom_icc_node slv_lpass = { 819 .name = "slv_lpass", 820 .id = QCM2290_SLAVE_LPASS, 821 .buswidth = 4, 822 .qos.ap_owned = true, 823 .qos.qos_mode = NOC_QOS_MODE_INVALID, 824 .mas_rpm_id = -1, 825 .slv_rpm_id = 21, 826 }; 827 828 static struct qcom_icc_node slv_message_ram = { 829 .name = "slv_message_ram", 830 .id = QCM2290_SLAVE_MESSAGE_RAM, 831 .buswidth = 4, 832 .qos.ap_owned = true, 833 .qos.qos_mode = NOC_QOS_MODE_INVALID, 834 .mas_rpm_id = -1, 835 .slv_rpm_id = 55, 836 }; 837 838 static struct qcom_icc_node slv_pdm = { 839 .name = "slv_pdm", 840 .id = QCM2290_SLAVE_PDM, 841 .buswidth = 4, 842 .qos.ap_owned = true, 843 .qos.qos_mode = NOC_QOS_MODE_INVALID, 844 .mas_rpm_id = -1, 845 .slv_rpm_id = 41, 846 }; 847 848 static struct qcom_icc_node slv_pimem_cfg = { 849 .name = "slv_pimem_cfg", 850 .id = QCM2290_SLAVE_PIMEM_CFG, 851 .buswidth = 4, 852 .qos.ap_owned = true, 853 .qos.qos_mode = NOC_QOS_MODE_INVALID, 854 .mas_rpm_id = -1, 855 .slv_rpm_id = 167, 856 }; 857 858 static struct qcom_icc_node slv_pka_wrapper = { 859 .name = "slv_pka_wrapper", 860 .id = QCM2290_SLAVE_PKA_WRAPPER, 861 .buswidth = 4, 862 .qos.ap_owned = true, 863 .qos.qos_mode = NOC_QOS_MODE_INVALID, 864 .mas_rpm_id = -1, 865 .slv_rpm_id = 281, 866 }; 867 868 static struct qcom_icc_node slv_pmic_arb = { 869 .name = "slv_pmic_arb", 870 .id = QCM2290_SLAVE_PMIC_ARB, 871 .buswidth = 4, 872 .qos.ap_owned = true, 873 .qos.qos_mode = NOC_QOS_MODE_INVALID, 874 .mas_rpm_id = -1, 875 .slv_rpm_id = 59, 876 }; 877 878 static struct qcom_icc_node slv_prng = { 879 .name = "slv_prng", 880 .id = QCM2290_SLAVE_PRNG, 881 .buswidth = 4, 882 .qos.ap_owned = true, 883 .qos.qos_mode = NOC_QOS_MODE_INVALID, 884 .mas_rpm_id = -1, 885 .slv_rpm_id = 44, 886 }; 887 888 static struct qcom_icc_node slv_qdss_cfg = { 889 .name = "slv_qdss_cfg", 890 .id = QCM2290_SLAVE_QDSS_CFG, 891 .buswidth = 4, 892 .qos.ap_owned = true, 893 .qos.qos_mode = NOC_QOS_MODE_INVALID, 894 .mas_rpm_id = -1, 895 .slv_rpm_id = 63, 896 }; 897 898 static struct qcom_icc_node slv_qm_cfg = { 899 .name = "slv_qm_cfg", 900 .id = QCM2290_SLAVE_QM_CFG, 901 .buswidth = 4, 902 .qos.ap_owned = true, 903 .qos.qos_mode = NOC_QOS_MODE_INVALID, 904 .mas_rpm_id = -1, 905 .slv_rpm_id = 212, 906 }; 907 908 static struct qcom_icc_node slv_qm_mpu_cfg = { 909 .name = "slv_qm_mpu_cfg", 910 .id = QCM2290_SLAVE_QM_MPU_CFG, 911 .buswidth = 4, 912 .qos.ap_owned = true, 913 .qos.qos_mode = NOC_QOS_MODE_INVALID, 914 .mas_rpm_id = -1, 915 .slv_rpm_id = 231, 916 }; 917 918 static struct qcom_icc_node slv_qpic = { 919 .name = "slv_qpic", 920 .id = QCM2290_SLAVE_QPIC, 921 .buswidth = 4, 922 .qos.ap_owned = true, 923 .qos.qos_mode = NOC_QOS_MODE_INVALID, 924 .mas_rpm_id = -1, 925 .slv_rpm_id = 80, 926 }; 927 928 static struct qcom_icc_node slv_qup_0 = { 929 .name = "slv_qup_0", 930 .id = QCM2290_SLAVE_QUP_0, 931 .buswidth = 4, 932 .qos.ap_owned = true, 933 .qos.qos_mode = NOC_QOS_MODE_INVALID, 934 .mas_rpm_id = -1, 935 .slv_rpm_id = 261, 936 }; 937 938 static struct qcom_icc_node slv_sdcc_1 = { 939 .name = "slv_sdcc_1", 940 .id = QCM2290_SLAVE_SDCC_1, 941 .buswidth = 4, 942 .qos.ap_owned = true, 943 .qos.qos_mode = NOC_QOS_MODE_INVALID, 944 .mas_rpm_id = -1, 945 .slv_rpm_id = 31, 946 }; 947 948 static struct qcom_icc_node slv_sdcc_2 = { 949 .name = "slv_sdcc_2", 950 .id = QCM2290_SLAVE_SDCC_2, 951 .buswidth = 4, 952 .qos.ap_owned = true, 953 .qos.qos_mode = NOC_QOS_MODE_INVALID, 954 .mas_rpm_id = -1, 955 .slv_rpm_id = 33, 956 }; 957 958 static const u16 slv_snoc_cfg_links[] = { 959 QCM2290_MASTER_SNOC_CFG, 960 }; 961 962 static struct qcom_icc_node slv_snoc_cfg = { 963 .name = "slv_snoc_cfg", 964 .id = QCM2290_SLAVE_SNOC_CFG, 965 .buswidth = 4, 966 .qos.ap_owned = true, 967 .qos.qos_mode = NOC_QOS_MODE_INVALID, 968 .mas_rpm_id = -1, 969 .slv_rpm_id = 70, 970 .num_links = ARRAY_SIZE(slv_snoc_cfg_links), 971 .links = slv_snoc_cfg_links, 972 }; 973 974 static struct qcom_icc_node slv_tcsr = { 975 .name = "slv_tcsr", 976 .id = QCM2290_SLAVE_TCSR, 977 .buswidth = 4, 978 .qos.ap_owned = true, 979 .qos.qos_mode = NOC_QOS_MODE_INVALID, 980 .mas_rpm_id = -1, 981 .slv_rpm_id = 50, 982 }; 983 984 static struct qcom_icc_node slv_usb3 = { 985 .name = "slv_usb3", 986 .id = QCM2290_SLAVE_USB3, 987 .buswidth = 4, 988 .qos.ap_owned = true, 989 .qos.qos_mode = NOC_QOS_MODE_INVALID, 990 .mas_rpm_id = -1, 991 .slv_rpm_id = 22, 992 }; 993 994 static struct qcom_icc_node slv_venus_cfg = { 995 .name = "slv_venus_cfg", 996 .id = QCM2290_SLAVE_VENUS_CFG, 997 .buswidth = 4, 998 .qos.ap_owned = true, 999 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1000 .mas_rpm_id = -1, 1001 .slv_rpm_id = 10, 1002 }; 1003 1004 static struct qcom_icc_node slv_venus_throttle_cfg = { 1005 .name = "slv_venus_throttle_cfg", 1006 .id = QCM2290_SLAVE_VENUS_THROTTLE_CFG, 1007 .buswidth = 4, 1008 .qos.ap_owned = true, 1009 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1010 .mas_rpm_id = -1, 1011 .slv_rpm_id = 178, 1012 }; 1013 1014 static struct qcom_icc_node slv_vsense_ctrl_cfg = { 1015 .name = "slv_vsense_ctrl_cfg", 1016 .id = QCM2290_SLAVE_VSENSE_CTRL_CFG, 1017 .buswidth = 4, 1018 .qos.ap_owned = true, 1019 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1020 .mas_rpm_id = -1, 1021 .slv_rpm_id = 263, 1022 }; 1023 1024 static struct qcom_icc_node slv_service_cnoc = { 1025 .name = "slv_service_cnoc", 1026 .id = QCM2290_SLAVE_SERVICE_CNOC, 1027 .buswidth = 4, 1028 .qos.ap_owned = true, 1029 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1030 .mas_rpm_id = -1, 1031 .slv_rpm_id = 76, 1032 }; 1033 1034 static struct qcom_icc_node slv_qup_core_0 = { 1035 .name = "slv_qup_core_0", 1036 .id = QCM2290_SLAVE_QUP_CORE_0, 1037 .buswidth = 4, 1038 .qos.ap_owned = true, 1039 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1040 .mas_rpm_id = -1, 1041 .slv_rpm_id = 264, 1042 }; 1043 1044 static const u16 slv_snoc_bimc_nrt_links[] = { 1045 QCM2290_MASTER_SNOC_BIMC_NRT, 1046 }; 1047 1048 static struct qcom_icc_node slv_snoc_bimc_nrt = { 1049 .name = "slv_snoc_bimc_nrt", 1050 .id = QCM2290_SLAVE_SNOC_BIMC_NRT, 1051 .buswidth = 16, 1052 .qos.ap_owned = true, 1053 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1054 .mas_rpm_id = -1, 1055 .slv_rpm_id = 259, 1056 .num_links = ARRAY_SIZE(slv_snoc_bimc_nrt_links), 1057 .links = slv_snoc_bimc_nrt_links, 1058 }; 1059 1060 static const u16 slv_snoc_bimc_rt_links[] = { 1061 QCM2290_MASTER_SNOC_BIMC_RT, 1062 }; 1063 1064 static struct qcom_icc_node slv_snoc_bimc_rt = { 1065 .name = "slv_snoc_bimc_rt", 1066 .id = QCM2290_SLAVE_SNOC_BIMC_RT, 1067 .buswidth = 16, 1068 .qos.ap_owned = true, 1069 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1070 .mas_rpm_id = -1, 1071 .slv_rpm_id = 260, 1072 .num_links = ARRAY_SIZE(slv_snoc_bimc_rt_links), 1073 .links = slv_snoc_bimc_rt_links, 1074 }; 1075 1076 static struct qcom_icc_node slv_appss = { 1077 .name = "slv_appss", 1078 .id = QCM2290_SLAVE_APPSS, 1079 .buswidth = 8, 1080 .qos.ap_owned = true, 1081 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1082 .mas_rpm_id = -1, 1083 .slv_rpm_id = 20, 1084 }; 1085 1086 static const u16 slv_snoc_cnoc_links[] = { 1087 QCM2290_MASTER_SNOC_CNOC, 1088 }; 1089 1090 static struct qcom_icc_node slv_snoc_cnoc = { 1091 .name = "slv_snoc_cnoc", 1092 .id = QCM2290_SLAVE_SNOC_CNOC, 1093 .buswidth = 8, 1094 .mas_rpm_id = -1, 1095 .slv_rpm_id = 25, 1096 .num_links = ARRAY_SIZE(slv_snoc_cnoc_links), 1097 .links = slv_snoc_cnoc_links, 1098 }; 1099 1100 static struct qcom_icc_node slv_imem = { 1101 .name = "slv_imem", 1102 .id = QCM2290_SLAVE_IMEM, 1103 .buswidth = 8, 1104 .mas_rpm_id = -1, 1105 .slv_rpm_id = 26, 1106 }; 1107 1108 static struct qcom_icc_node slv_pimem = { 1109 .name = "slv_pimem", 1110 .id = QCM2290_SLAVE_PIMEM, 1111 .buswidth = 8, 1112 .qos.ap_owned = true, 1113 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1114 .mas_rpm_id = -1, 1115 .slv_rpm_id = 166, 1116 }; 1117 1118 static const u16 slv_snoc_bimc_links[] = { 1119 QCM2290_MASTER_SNOC_BIMC, 1120 }; 1121 1122 static struct qcom_icc_node slv_snoc_bimc = { 1123 .name = "slv_snoc_bimc", 1124 .id = QCM2290_SLAVE_SNOC_BIMC, 1125 .buswidth = 16, 1126 .mas_rpm_id = -1, 1127 .slv_rpm_id = 24, 1128 .num_links = ARRAY_SIZE(slv_snoc_bimc_links), 1129 .links = slv_snoc_bimc_links, 1130 }; 1131 1132 static struct qcom_icc_node slv_service_snoc = { 1133 .name = "slv_service_snoc", 1134 .id = QCM2290_SLAVE_SERVICE_SNOC, 1135 .buswidth = 4, 1136 .qos.ap_owned = true, 1137 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1138 .mas_rpm_id = -1, 1139 .slv_rpm_id = 29, 1140 }; 1141 1142 static struct qcom_icc_node slv_qdss_stm = { 1143 .name = "slv_qdss_stm", 1144 .id = QCM2290_SLAVE_QDSS_STM, 1145 .buswidth = 4, 1146 .mas_rpm_id = -1, 1147 .slv_rpm_id = 30, 1148 }; 1149 1150 static struct qcom_icc_node slv_tcu = { 1151 .name = "slv_tcu", 1152 .id = QCM2290_SLAVE_TCU, 1153 .buswidth = 8, 1154 .qos.ap_owned = true, 1155 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1156 .mas_rpm_id = -1, 1157 .slv_rpm_id = 133, 1158 }; 1159 1160 static const u16 slv_anoc_snoc_links[] = { 1161 QCM2290_MASTER_ANOC_SNOC, 1162 }; 1163 1164 static struct qcom_icc_node slv_anoc_snoc = { 1165 .name = "slv_anoc_snoc", 1166 .id = QCM2290_SLAVE_ANOC_SNOC, 1167 .buswidth = 16, 1168 .mas_rpm_id = -1, 1169 .slv_rpm_id = 141, 1170 .num_links = ARRAY_SIZE(slv_anoc_snoc_links), 1171 .links = slv_anoc_snoc_links, 1172 }; 1173 1174 /* NoC descriptors */ 1175 static struct qcom_icc_node * const qcm2290_bimc_nodes[] = { 1176 [MASTER_APPSS_PROC] = &mas_appss_proc, 1177 [MASTER_SNOC_BIMC_RT] = &mas_snoc_bimc_rt, 1178 [MASTER_SNOC_BIMC_NRT] = &mas_snoc_bimc_nrt, 1179 [MASTER_SNOC_BIMC] = &mas_snoc_bimc, 1180 [MASTER_TCU_0] = &mas_tcu_0, 1181 [MASTER_GFX3D] = &mas_gfx3d, 1182 [SLAVE_EBI1] = &slv_ebi1, 1183 [SLAVE_BIMC_SNOC] = &slv_bimc_snoc, 1184 }; 1185 1186 static const struct regmap_config qcm2290_bimc_regmap_config = { 1187 .reg_bits = 32, 1188 .reg_stride = 4, 1189 .val_bits = 32, 1190 .max_register = 0x80000, 1191 .fast_io = true, 1192 }; 1193 1194 static const struct qcom_icc_desc qcm2290_bimc = { 1195 .type = QCOM_ICC_BIMC, 1196 .nodes = qcm2290_bimc_nodes, 1197 .num_nodes = ARRAY_SIZE(qcm2290_bimc_nodes), 1198 .bus_clk_desc = &bimc_clk, 1199 .regmap_cfg = &qcm2290_bimc_regmap_config, 1200 /* M_REG_BASE() in vendor msm_bus_bimc_adhoc driver */ 1201 .qos_offset = 0x8000, 1202 }; 1203 1204 static struct qcom_icc_node * const qcm2290_cnoc_nodes[] = { 1205 [MASTER_SNOC_CNOC] = &mas_snoc_cnoc, 1206 [MASTER_QDSS_DAP] = &mas_qdss_dap, 1207 [SLAVE_BIMC_CFG] = &slv_bimc_cfg, 1208 [SLAVE_CAMERA_NRT_THROTTLE_CFG] = &slv_camera_nrt_throttle_cfg, 1209 [SLAVE_CAMERA_RT_THROTTLE_CFG] = &slv_camera_rt_throttle_cfg, 1210 [SLAVE_CAMERA_CFG] = &slv_camera_cfg, 1211 [SLAVE_CLK_CTL] = &slv_clk_ctl, 1212 [SLAVE_CRYPTO_0_CFG] = &slv_crypto_0_cfg, 1213 [SLAVE_DISPLAY_CFG] = &slv_display_cfg, 1214 [SLAVE_DISPLAY_THROTTLE_CFG] = &slv_display_throttle_cfg, 1215 [SLAVE_GPU_CFG] = &slv_gpu_cfg, 1216 [SLAVE_HWKM] = &slv_hwkm, 1217 [SLAVE_IMEM_CFG] = &slv_imem_cfg, 1218 [SLAVE_IPA_CFG] = &slv_ipa_cfg, 1219 [SLAVE_LPASS] = &slv_lpass, 1220 [SLAVE_MESSAGE_RAM] = &slv_message_ram, 1221 [SLAVE_PDM] = &slv_pdm, 1222 [SLAVE_PIMEM_CFG] = &slv_pimem_cfg, 1223 [SLAVE_PKA_WRAPPER] = &slv_pka_wrapper, 1224 [SLAVE_PMIC_ARB] = &slv_pmic_arb, 1225 [SLAVE_PRNG] = &slv_prng, 1226 [SLAVE_QDSS_CFG] = &slv_qdss_cfg, 1227 [SLAVE_QM_CFG] = &slv_qm_cfg, 1228 [SLAVE_QM_MPU_CFG] = &slv_qm_mpu_cfg, 1229 [SLAVE_QPIC] = &slv_qpic, 1230 [SLAVE_QUP_0] = &slv_qup_0, 1231 [SLAVE_SDCC_1] = &slv_sdcc_1, 1232 [SLAVE_SDCC_2] = &slv_sdcc_2, 1233 [SLAVE_SNOC_CFG] = &slv_snoc_cfg, 1234 [SLAVE_TCSR] = &slv_tcsr, 1235 [SLAVE_USB3] = &slv_usb3, 1236 [SLAVE_VENUS_CFG] = &slv_venus_cfg, 1237 [SLAVE_VENUS_THROTTLE_CFG] = &slv_venus_throttle_cfg, 1238 [SLAVE_VSENSE_CTRL_CFG] = &slv_vsense_ctrl_cfg, 1239 [SLAVE_SERVICE_CNOC] = &slv_service_cnoc, 1240 }; 1241 1242 static const struct regmap_config qcm2290_cnoc_regmap_config = { 1243 .reg_bits = 32, 1244 .reg_stride = 4, 1245 .val_bits = 32, 1246 .max_register = 0x8200, 1247 .fast_io = true, 1248 }; 1249 1250 static const struct qcom_icc_desc qcm2290_cnoc = { 1251 .type = QCOM_ICC_NOC, 1252 .nodes = qcm2290_cnoc_nodes, 1253 .num_nodes = ARRAY_SIZE(qcm2290_cnoc_nodes), 1254 .bus_clk_desc = &bus_1_clk, 1255 .regmap_cfg = &qcm2290_cnoc_regmap_config, 1256 }; 1257 1258 static struct qcom_icc_node * const qcm2290_snoc_nodes[] = { 1259 [MASTER_CRYPTO_CORE0] = &mas_crypto_core0, 1260 [MASTER_SNOC_CFG] = &mas_snoc_cfg, 1261 [MASTER_TIC] = &mas_tic, 1262 [MASTER_ANOC_SNOC] = &mas_anoc_snoc, 1263 [MASTER_BIMC_SNOC] = &mas_bimc_snoc, 1264 [MASTER_PIMEM] = &mas_pimem, 1265 [MASTER_QDSS_BAM] = &mas_qdss_bam, 1266 [MASTER_QUP_0] = &mas_qup_0, 1267 [MASTER_IPA] = &mas_ipa, 1268 [MASTER_QDSS_ETR] = &mas_qdss_etr, 1269 [MASTER_SDCC_1] = &mas_sdcc_1, 1270 [MASTER_SDCC_2] = &mas_sdcc_2, 1271 [MASTER_QPIC] = &mas_qpic, 1272 [MASTER_USB3_0] = &mas_usb3_0, 1273 [SLAVE_APPSS] = &slv_appss, 1274 [SLAVE_SNOC_CNOC] = &slv_snoc_cnoc, 1275 [SLAVE_IMEM] = &slv_imem, 1276 [SLAVE_PIMEM] = &slv_pimem, 1277 [SLAVE_SNOC_BIMC] = &slv_snoc_bimc, 1278 [SLAVE_SERVICE_SNOC] = &slv_service_snoc, 1279 [SLAVE_QDSS_STM] = &slv_qdss_stm, 1280 [SLAVE_TCU] = &slv_tcu, 1281 [SLAVE_ANOC_SNOC] = &slv_anoc_snoc, 1282 }; 1283 1284 static const struct regmap_config qcm2290_snoc_regmap_config = { 1285 .reg_bits = 32, 1286 .reg_stride = 4, 1287 .val_bits = 32, 1288 .max_register = 0x60200, 1289 .fast_io = true, 1290 }; 1291 1292 static const struct qcom_icc_desc qcm2290_snoc = { 1293 .type = QCOM_ICC_QNOC, 1294 .nodes = qcm2290_snoc_nodes, 1295 .num_nodes = ARRAY_SIZE(qcm2290_snoc_nodes), 1296 .bus_clk_desc = &bus_2_clk, 1297 .regmap_cfg = &qcm2290_snoc_regmap_config, 1298 /* Vendor DT node fab-sys_noc property 'qcom,base-offset' */ 1299 .qos_offset = 0x15000, 1300 }; 1301 1302 static struct qcom_icc_node * const qcm2290_qup_virt_nodes[] = { 1303 [MASTER_QUP_CORE_0] = &mas_qup_core_0, 1304 [SLAVE_QUP_CORE_0] = &slv_qup_core_0 1305 }; 1306 1307 static const struct qcom_icc_desc qcm2290_qup_virt = { 1308 .type = QCOM_ICC_QNOC, 1309 .nodes = qcm2290_qup_virt_nodes, 1310 .num_nodes = ARRAY_SIZE(qcm2290_qup_virt_nodes), 1311 .bus_clk_desc = &qup_clk, 1312 }; 1313 1314 static struct qcom_icc_node * const qcm2290_mmnrt_virt_nodes[] = { 1315 [MASTER_CAMNOC_SF] = &mas_camnoc_sf, 1316 [MASTER_VIDEO_P0] = &mas_video_p0, 1317 [MASTER_VIDEO_PROC] = &mas_video_proc, 1318 [SLAVE_SNOC_BIMC_NRT] = &slv_snoc_bimc_nrt, 1319 }; 1320 1321 static const struct qcom_icc_desc qcm2290_mmnrt_virt = { 1322 .type = QCOM_ICC_QNOC, 1323 .nodes = qcm2290_mmnrt_virt_nodes, 1324 .num_nodes = ARRAY_SIZE(qcm2290_mmnrt_virt_nodes), 1325 .bus_clk_desc = &mmaxi_0_clk, 1326 .regmap_cfg = &qcm2290_snoc_regmap_config, 1327 .qos_offset = 0x15000, 1328 }; 1329 1330 static struct qcom_icc_node * const qcm2290_mmrt_virt_nodes[] = { 1331 [MASTER_CAMNOC_HF] = &mas_camnoc_hf, 1332 [MASTER_MDP0] = &mas_mdp0, 1333 [SLAVE_SNOC_BIMC_RT] = &slv_snoc_bimc_rt, 1334 }; 1335 1336 static const struct qcom_icc_desc qcm2290_mmrt_virt = { 1337 .type = QCOM_ICC_QNOC, 1338 .nodes = qcm2290_mmrt_virt_nodes, 1339 .num_nodes = ARRAY_SIZE(qcm2290_mmrt_virt_nodes), 1340 .bus_clk_desc = &mmaxi_1_clk, 1341 .regmap_cfg = &qcm2290_snoc_regmap_config, 1342 .qos_offset = 0x15000, 1343 }; 1344 1345 static const struct of_device_id qcm2290_noc_of_match[] = { 1346 { .compatible = "qcom,qcm2290-bimc", .data = &qcm2290_bimc }, 1347 { .compatible = "qcom,qcm2290-cnoc", .data = &qcm2290_cnoc }, 1348 { .compatible = "qcom,qcm2290-snoc", .data = &qcm2290_snoc }, 1349 { .compatible = "qcom,qcm2290-qup-virt", .data = &qcm2290_qup_virt }, 1350 { .compatible = "qcom,qcm2290-mmrt-virt", .data = &qcm2290_mmrt_virt }, 1351 { .compatible = "qcom,qcm2290-mmnrt-virt", .data = &qcm2290_mmnrt_virt }, 1352 { }, 1353 }; 1354 MODULE_DEVICE_TABLE(of, qcm2290_noc_of_match); 1355 1356 static struct platform_driver qcm2290_noc_driver = { 1357 .probe = qnoc_probe, 1358 .remove = qnoc_remove, 1359 .driver = { 1360 .name = "qnoc-qcm2290", 1361 .of_match_table = qcm2290_noc_of_match, 1362 }, 1363 }; 1364 module_platform_driver(qcm2290_noc_driver); 1365 1366 MODULE_DESCRIPTION("Qualcomm QCM2290 NoC driver"); 1367 MODULE_LICENSE("GPL v2"); 1368