1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012-2017 Hideep, Inc. 4 */ 5 6 #include <linux/module.h> 7 #include <linux/of.h> 8 #include <linux/firmware.h> 9 #include <linux/delay.h> 10 #include <linux/gpio/consumer.h> 11 #include <linux/i2c.h> 12 #include <linux/acpi.h> 13 #include <linux/interrupt.h> 14 #include <linux/regmap.h> 15 #include <linux/sysfs.h> 16 #include <linux/input.h> 17 #include <linux/input/mt.h> 18 #include <linux/input/touchscreen.h> 19 #include <linux/regulator/consumer.h> 20 #include <asm/unaligned.h> 21 22 #define HIDEEP_TS_NAME "HiDeep Touchscreen" 23 #define HIDEEP_I2C_NAME "hideep_ts" 24 25 #define HIDEEP_MT_MAX 10 26 #define HIDEEP_KEY_MAX 3 27 28 /* count(2) + touch data(100) + key data(6) */ 29 #define HIDEEP_MAX_EVENT 108UL 30 31 #define HIDEEP_TOUCH_EVENT_INDEX 2 32 #define HIDEEP_KEY_EVENT_INDEX 102 33 34 /* Touch & key event */ 35 #define HIDEEP_EVENT_ADDR 0x240 36 37 /* command list */ 38 #define HIDEEP_RESET_CMD 0x9800 39 40 /* event bit */ 41 #define HIDEEP_MT_RELEASED BIT(4) 42 #define HIDEEP_KEY_PRESSED BIT(7) 43 #define HIDEEP_KEY_FIRST_PRESSED BIT(8) 44 #define HIDEEP_KEY_PRESSED_MASK (HIDEEP_KEY_PRESSED | \ 45 HIDEEP_KEY_FIRST_PRESSED) 46 47 #define HIDEEP_KEY_IDX_MASK 0x0f 48 49 /* For NVM */ 50 #define HIDEEP_YRAM_BASE 0x40000000 51 #define HIDEEP_PERIPHERAL_BASE 0x50000000 52 #define HIDEEP_ESI_BASE (HIDEEP_PERIPHERAL_BASE + 0x00000000) 53 #define HIDEEP_FLASH_BASE (HIDEEP_PERIPHERAL_BASE + 0x01000000) 54 #define HIDEEP_SYSCON_BASE (HIDEEP_PERIPHERAL_BASE + 0x02000000) 55 56 #define HIDEEP_SYSCON_MOD_CON (HIDEEP_SYSCON_BASE + 0x0000) 57 #define HIDEEP_SYSCON_SPC_CON (HIDEEP_SYSCON_BASE + 0x0004) 58 #define HIDEEP_SYSCON_CLK_CON (HIDEEP_SYSCON_BASE + 0x0008) 59 #define HIDEEP_SYSCON_CLK_ENA (HIDEEP_SYSCON_BASE + 0x000C) 60 #define HIDEEP_SYSCON_RST_CON (HIDEEP_SYSCON_BASE + 0x0010) 61 #define HIDEEP_SYSCON_WDT_CON (HIDEEP_SYSCON_BASE + 0x0014) 62 #define HIDEEP_SYSCON_WDT_CNT (HIDEEP_SYSCON_BASE + 0x0018) 63 #define HIDEEP_SYSCON_PWR_CON (HIDEEP_SYSCON_BASE + 0x0020) 64 #define HIDEEP_SYSCON_PGM_ID (HIDEEP_SYSCON_BASE + 0x00F4) 65 66 #define HIDEEP_FLASH_CON (HIDEEP_FLASH_BASE + 0x0000) 67 #define HIDEEP_FLASH_STA (HIDEEP_FLASH_BASE + 0x0004) 68 #define HIDEEP_FLASH_CFG (HIDEEP_FLASH_BASE + 0x0008) 69 #define HIDEEP_FLASH_TIM (HIDEEP_FLASH_BASE + 0x000C) 70 #define HIDEEP_FLASH_CACHE_CFG (HIDEEP_FLASH_BASE + 0x0010) 71 #define HIDEEP_FLASH_PIO_SIG (HIDEEP_FLASH_BASE + 0x400000) 72 73 #define HIDEEP_ESI_TX_INVALID (HIDEEP_ESI_BASE + 0x0008) 74 75 #define HIDEEP_PERASE 0x00040000 76 #define HIDEEP_WRONLY 0x00100000 77 78 #define HIDEEP_NVM_MASK_OFS 0x0000000C 79 #define HIDEEP_NVM_DEFAULT_PAGE 0 80 #define HIDEEP_NVM_SFR_WPAGE 1 81 #define HIDEEP_NVM_SFR_RPAGE 2 82 83 #define HIDEEP_PIO_SIG 0x00400000 84 #define HIDEEP_PROT_MODE 0x03400000 85 86 #define HIDEEP_NVM_PAGE_SIZE 128 87 88 #define HIDEEP_DWZ_INFO 0x000002C0 89 90 struct hideep_event { 91 __le16 x; 92 __le16 y; 93 __le16 z; 94 u8 w; 95 u8 flag; 96 u8 type; 97 u8 index; 98 }; 99 100 struct dwz_info { 101 __be32 code_start; 102 u8 code_crc[12]; 103 104 __be32 c_code_start; 105 __be16 gen_ver; 106 __be16 c_code_len; 107 108 __be32 vr_start; 109 __be16 rsv0; 110 __be16 vr_len; 111 112 __be32 ft_start; 113 __be16 vr_version; 114 __be16 ft_len; 115 116 __be16 core_ver; 117 __be16 boot_ver; 118 119 __be16 release_ver; 120 __be16 custom_ver; 121 122 u8 factory_id; 123 u8 panel_type; 124 u8 model_name[6]; 125 126 __be16 extra_option; 127 __be16 product_code; 128 129 __be16 vendor_id; 130 __be16 product_id; 131 }; 132 133 struct pgm_packet { 134 struct { 135 u8 unused[3]; 136 u8 len; 137 __be32 addr; 138 } header; 139 __be32 payload[HIDEEP_NVM_PAGE_SIZE / sizeof(__be32)]; 140 }; 141 142 #define HIDEEP_XFER_BUF_SIZE sizeof(struct pgm_packet) 143 144 struct hideep_ts { 145 struct i2c_client *client; 146 struct input_dev *input_dev; 147 struct regmap *reg; 148 149 struct touchscreen_properties prop; 150 151 struct gpio_desc *reset_gpio; 152 153 struct regulator *vcc_vdd; 154 struct regulator *vcc_vid; 155 156 struct mutex dev_mutex; 157 158 u32 tch_count; 159 u32 lpm_count; 160 161 /* 162 * Data buffer to read packet from the device (contacts and key 163 * states). We align it on double-word boundary to keep word-sized 164 * fields in contact data and double-word-sized fields in program 165 * packet aligned. 166 */ 167 u8 xfer_buf[HIDEEP_XFER_BUF_SIZE] __aligned(4); 168 169 int key_num; 170 u32 key_codes[HIDEEP_KEY_MAX]; 171 172 struct dwz_info dwz_info; 173 174 unsigned int fw_size; 175 u32 nvm_mask; 176 }; 177 178 static int hideep_pgm_w_mem(struct hideep_ts *ts, u32 addr, 179 const __be32 *data, size_t count) 180 { 181 struct pgm_packet *packet = (void *)ts->xfer_buf; 182 size_t len = count * sizeof(*data); 183 struct i2c_msg msg = { 184 .addr = ts->client->addr, 185 .len = len + sizeof(packet->header.len) + 186 sizeof(packet->header.addr), 187 .buf = &packet->header.len, 188 }; 189 int ret; 190 191 if (len > HIDEEP_NVM_PAGE_SIZE) 192 return -EINVAL; 193 194 packet->header.len = 0x80 | (count - 1); 195 packet->header.addr = cpu_to_be32(addr); 196 memcpy(packet->payload, data, len); 197 198 ret = i2c_transfer(ts->client->adapter, &msg, 1); 199 if (ret != 1) 200 return ret < 0 ? ret : -EIO; 201 202 return 0; 203 } 204 205 static int hideep_pgm_r_mem(struct hideep_ts *ts, u32 addr, 206 __be32 *data, size_t count) 207 { 208 struct pgm_packet *packet = (void *)ts->xfer_buf; 209 size_t len = count * sizeof(*data); 210 struct i2c_msg msg[] = { 211 { 212 .addr = ts->client->addr, 213 .len = sizeof(packet->header.len) + 214 sizeof(packet->header.addr), 215 .buf = &packet->header.len, 216 }, 217 { 218 .addr = ts->client->addr, 219 .flags = I2C_M_RD, 220 .len = len, 221 .buf = (u8 *)data, 222 }, 223 }; 224 int ret; 225 226 if (len > HIDEEP_NVM_PAGE_SIZE) 227 return -EINVAL; 228 229 packet->header.len = count - 1; 230 packet->header.addr = cpu_to_be32(addr); 231 232 ret = i2c_transfer(ts->client->adapter, msg, ARRAY_SIZE(msg)); 233 if (ret != ARRAY_SIZE(msg)) 234 return ret < 0 ? ret : -EIO; 235 236 return 0; 237 } 238 239 static int hideep_pgm_r_reg(struct hideep_ts *ts, u32 addr, u32 *val) 240 { 241 __be32 data; 242 int error; 243 244 error = hideep_pgm_r_mem(ts, addr, &data, 1); 245 if (error) { 246 dev_err(&ts->client->dev, 247 "read of register %#08x failed: %d\n", 248 addr, error); 249 return error; 250 } 251 252 *val = be32_to_cpu(data); 253 return 0; 254 } 255 256 static int hideep_pgm_w_reg(struct hideep_ts *ts, u32 addr, u32 val) 257 { 258 __be32 data = cpu_to_be32(val); 259 int error; 260 261 error = hideep_pgm_w_mem(ts, addr, &data, 1); 262 if (error) { 263 dev_err(&ts->client->dev, 264 "write to register %#08x (%#08x) failed: %d\n", 265 addr, val, error); 266 return error; 267 } 268 269 return 0; 270 } 271 272 #define SW_RESET_IN_PGM(clk) \ 273 { \ 274 __be32 data = cpu_to_be32(0x01); \ 275 hideep_pgm_w_reg(ts, HIDEEP_SYSCON_WDT_CNT, (clk)); \ 276 hideep_pgm_w_reg(ts, HIDEEP_SYSCON_WDT_CON, 0x03); \ 277 /* \ 278 * The first write may already cause a reset, use a raw \ 279 * write for the second write to avoid error logging. \ 280 */ \ 281 hideep_pgm_w_mem(ts, HIDEEP_SYSCON_WDT_CON, &data, 1); \ 282 } 283 284 #define SET_FLASH_PIO(ce) \ 285 hideep_pgm_w_reg(ts, HIDEEP_FLASH_CON, \ 286 0x01 | ((ce) << 1)) 287 288 #define SET_PIO_SIG(x, y) \ 289 hideep_pgm_w_reg(ts, HIDEEP_FLASH_PIO_SIG + (x), (y)) 290 291 #define SET_FLASH_HWCONTROL() \ 292 hideep_pgm_w_reg(ts, HIDEEP_FLASH_CON, 0x00) 293 294 #define NVM_W_SFR(x, y) \ 295 { \ 296 SET_FLASH_PIO(1); \ 297 SET_PIO_SIG(x, y); \ 298 SET_FLASH_PIO(0); \ 299 } 300 301 static void hideep_pgm_set(struct hideep_ts *ts) 302 { 303 hideep_pgm_w_reg(ts, HIDEEP_SYSCON_WDT_CON, 0x00); 304 hideep_pgm_w_reg(ts, HIDEEP_SYSCON_SPC_CON, 0x00); 305 hideep_pgm_w_reg(ts, HIDEEP_SYSCON_CLK_ENA, 0xFF); 306 hideep_pgm_w_reg(ts, HIDEEP_SYSCON_CLK_CON, 0x01); 307 hideep_pgm_w_reg(ts, HIDEEP_SYSCON_PWR_CON, 0x01); 308 hideep_pgm_w_reg(ts, HIDEEP_FLASH_TIM, 0x03); 309 hideep_pgm_w_reg(ts, HIDEEP_FLASH_CACHE_CFG, 0x00); 310 } 311 312 static int hideep_pgm_get_pattern(struct hideep_ts *ts, u32 *pattern) 313 { 314 u16 p1 = 0xAF39; 315 u16 p2 = 0xDF9D; 316 int error; 317 318 error = regmap_bulk_write(ts->reg, p1, &p2, 1); 319 if (error) { 320 dev_err(&ts->client->dev, 321 "%s: regmap_bulk_write() failed with %d\n", 322 __func__, error); 323 return error; 324 } 325 326 usleep_range(1000, 1100); 327 328 /* flush invalid Tx load register */ 329 error = hideep_pgm_w_reg(ts, HIDEEP_ESI_TX_INVALID, 0x01); 330 if (error) 331 return error; 332 333 error = hideep_pgm_r_reg(ts, HIDEEP_SYSCON_PGM_ID, pattern); 334 if (error) 335 return error; 336 337 return 0; 338 } 339 340 static int hideep_enter_pgm(struct hideep_ts *ts) 341 { 342 int retry_count = 10; 343 u32 pattern; 344 int error; 345 346 while (retry_count--) { 347 error = hideep_pgm_get_pattern(ts, &pattern); 348 if (error) { 349 dev_err(&ts->client->dev, 350 "hideep_pgm_get_pattern failed: %d\n", error); 351 } else if (pattern != 0x39AF9DDF) { 352 dev_err(&ts->client->dev, "%s: bad pattern: %#08x\n", 353 __func__, pattern); 354 } else { 355 dev_dbg(&ts->client->dev, "found magic code"); 356 357 hideep_pgm_set(ts); 358 usleep_range(1000, 1100); 359 360 return 0; 361 } 362 } 363 364 dev_err(&ts->client->dev, "failed to enter pgm mode\n"); 365 SW_RESET_IN_PGM(1000); 366 return -EIO; 367 } 368 369 static int hideep_nvm_unlock(struct hideep_ts *ts) 370 { 371 u32 unmask_code; 372 int error; 373 374 hideep_pgm_w_reg(ts, HIDEEP_FLASH_CFG, HIDEEP_NVM_SFR_RPAGE); 375 error = hideep_pgm_r_reg(ts, 0x0000000C, &unmask_code); 376 hideep_pgm_w_reg(ts, HIDEEP_FLASH_CFG, HIDEEP_NVM_DEFAULT_PAGE); 377 if (error) 378 return error; 379 380 /* make it unprotected code */ 381 unmask_code &= ~HIDEEP_PROT_MODE; 382 383 /* compare unmask code */ 384 if (unmask_code != ts->nvm_mask) 385 dev_warn(&ts->client->dev, 386 "read mask code different %#08x vs %#08x", 387 unmask_code, ts->nvm_mask); 388 389 hideep_pgm_w_reg(ts, HIDEEP_FLASH_CFG, HIDEEP_NVM_SFR_WPAGE); 390 SET_FLASH_PIO(0); 391 392 NVM_W_SFR(HIDEEP_NVM_MASK_OFS, ts->nvm_mask); 393 SET_FLASH_HWCONTROL(); 394 hideep_pgm_w_reg(ts, HIDEEP_FLASH_CFG, HIDEEP_NVM_DEFAULT_PAGE); 395 396 return 0; 397 } 398 399 static int hideep_check_status(struct hideep_ts *ts) 400 { 401 int time_out = 100; 402 int status; 403 int error; 404 405 while (time_out--) { 406 error = hideep_pgm_r_reg(ts, HIDEEP_FLASH_STA, &status); 407 if (!error && status) 408 return 0; 409 410 usleep_range(1000, 1100); 411 } 412 413 return -ETIMEDOUT; 414 } 415 416 static int hideep_program_page(struct hideep_ts *ts, u32 addr, 417 const __be32 *ucode, size_t xfer_count) 418 { 419 u32 val; 420 int error; 421 422 error = hideep_check_status(ts); 423 if (error) 424 return -EBUSY; 425 426 addr &= ~(HIDEEP_NVM_PAGE_SIZE - 1); 427 428 SET_FLASH_PIO(0); 429 SET_FLASH_PIO(1); 430 431 /* erase page */ 432 SET_PIO_SIG(HIDEEP_PERASE | addr, 0xFFFFFFFF); 433 434 SET_FLASH_PIO(0); 435 436 error = hideep_check_status(ts); 437 if (error) 438 return -EBUSY; 439 440 /* write page */ 441 SET_FLASH_PIO(1); 442 443 val = be32_to_cpu(ucode[0]); 444 SET_PIO_SIG(HIDEEP_WRONLY | addr, val); 445 446 hideep_pgm_w_mem(ts, HIDEEP_FLASH_PIO_SIG | HIDEEP_WRONLY, 447 ucode, xfer_count); 448 449 val = be32_to_cpu(ucode[xfer_count - 1]); 450 SET_PIO_SIG(124, val); 451 452 SET_FLASH_PIO(0); 453 454 usleep_range(1000, 1100); 455 456 error = hideep_check_status(ts); 457 if (error) 458 return -EBUSY; 459 460 SET_FLASH_HWCONTROL(); 461 462 return 0; 463 } 464 465 static int hideep_program_nvm(struct hideep_ts *ts, 466 const __be32 *ucode, size_t ucode_len) 467 { 468 struct pgm_packet *packet_r = (void *)ts->xfer_buf; 469 __be32 *current_ucode = packet_r->payload; 470 size_t xfer_len; 471 size_t xfer_count; 472 u32 addr = 0; 473 int error; 474 475 error = hideep_nvm_unlock(ts); 476 if (error) 477 return error; 478 479 while (ucode_len > 0) { 480 xfer_len = min_t(size_t, ucode_len, HIDEEP_NVM_PAGE_SIZE); 481 xfer_count = xfer_len / sizeof(*ucode); 482 483 error = hideep_pgm_r_mem(ts, 0x00000000 + addr, 484 current_ucode, xfer_count); 485 if (error) { 486 dev_err(&ts->client->dev, 487 "%s: failed to read page at offset %#08x: %d\n", 488 __func__, addr, error); 489 return error; 490 } 491 492 /* See if the page needs updating */ 493 if (memcmp(ucode, current_ucode, xfer_len)) { 494 error = hideep_program_page(ts, addr, 495 ucode, xfer_count); 496 if (error) { 497 dev_err(&ts->client->dev, 498 "%s: iwrite failure @%#08x: %d\n", 499 __func__, addr, error); 500 return error; 501 } 502 503 usleep_range(1000, 1100); 504 } 505 506 ucode += xfer_count; 507 addr += xfer_len; 508 ucode_len -= xfer_len; 509 } 510 511 return 0; 512 } 513 514 static int hideep_verify_nvm(struct hideep_ts *ts, 515 const __be32 *ucode, size_t ucode_len) 516 { 517 struct pgm_packet *packet_r = (void *)ts->xfer_buf; 518 __be32 *current_ucode = packet_r->payload; 519 size_t xfer_len; 520 size_t xfer_count; 521 u32 addr = 0; 522 int i; 523 int error; 524 525 while (ucode_len > 0) { 526 xfer_len = min_t(size_t, ucode_len, HIDEEP_NVM_PAGE_SIZE); 527 xfer_count = xfer_len / sizeof(*ucode); 528 529 error = hideep_pgm_r_mem(ts, 0x00000000 + addr, 530 current_ucode, xfer_count); 531 if (error) { 532 dev_err(&ts->client->dev, 533 "%s: failed to read page at offset %#08x: %d\n", 534 __func__, addr, error); 535 return error; 536 } 537 538 if (memcmp(ucode, current_ucode, xfer_len)) { 539 const u8 *ucode_bytes = (const u8 *)ucode; 540 const u8 *current_bytes = (const u8 *)current_ucode; 541 542 for (i = 0; i < xfer_len; i++) 543 if (ucode_bytes[i] != current_bytes[i]) 544 dev_err(&ts->client->dev, 545 "%s: mismatch @%#08x: (%#02x vs %#02x)\n", 546 __func__, addr + i, 547 ucode_bytes[i], 548 current_bytes[i]); 549 550 return -EIO; 551 } 552 553 ucode += xfer_count; 554 addr += xfer_len; 555 ucode_len -= xfer_len; 556 } 557 558 return 0; 559 } 560 561 static int hideep_load_dwz(struct hideep_ts *ts) 562 { 563 u16 product_code; 564 int error; 565 566 error = hideep_enter_pgm(ts); 567 if (error) 568 return error; 569 570 msleep(50); 571 572 error = hideep_pgm_r_mem(ts, HIDEEP_DWZ_INFO, 573 (void *)&ts->dwz_info, 574 sizeof(ts->dwz_info) / sizeof(__be32)); 575 576 SW_RESET_IN_PGM(10); 577 msleep(50); 578 579 if (error) { 580 dev_err(&ts->client->dev, 581 "failed to fetch DWZ data: %d\n", error); 582 return error; 583 } 584 585 product_code = be16_to_cpu(ts->dwz_info.product_code); 586 587 switch (product_code & 0xF0) { 588 case 0x40: 589 dev_dbg(&ts->client->dev, "used crimson IC"); 590 ts->fw_size = 1024 * 48; 591 ts->nvm_mask = 0x00310000; 592 break; 593 case 0x60: 594 dev_dbg(&ts->client->dev, "used lime IC"); 595 ts->fw_size = 1024 * 64; 596 ts->nvm_mask = 0x0030027B; 597 break; 598 default: 599 dev_err(&ts->client->dev, "product code is wrong: %#04x", 600 product_code); 601 return -EINVAL; 602 } 603 604 dev_dbg(&ts->client->dev, "firmware release version: %#04x", 605 be16_to_cpu(ts->dwz_info.release_ver)); 606 607 return 0; 608 } 609 610 static int hideep_flash_firmware(struct hideep_ts *ts, 611 const __be32 *ucode, size_t ucode_len) 612 { 613 int retry_cnt = 3; 614 int error; 615 616 while (retry_cnt--) { 617 error = hideep_program_nvm(ts, ucode, ucode_len); 618 if (!error) { 619 error = hideep_verify_nvm(ts, ucode, ucode_len); 620 if (!error) 621 return 0; 622 } 623 } 624 625 return error; 626 } 627 628 static int hideep_update_firmware(struct hideep_ts *ts, 629 const __be32 *ucode, size_t ucode_len) 630 { 631 int error, error2; 632 633 dev_dbg(&ts->client->dev, "starting firmware update"); 634 635 /* enter program mode */ 636 error = hideep_enter_pgm(ts); 637 if (error) 638 return error; 639 640 error = hideep_flash_firmware(ts, ucode, ucode_len); 641 if (error) 642 dev_err(&ts->client->dev, 643 "firmware update failed: %d\n", error); 644 else 645 dev_dbg(&ts->client->dev, "firmware updated successfully\n"); 646 647 SW_RESET_IN_PGM(1000); 648 649 error2 = hideep_load_dwz(ts); 650 if (error2) 651 dev_err(&ts->client->dev, 652 "failed to load dwz after firmware update: %d\n", 653 error2); 654 655 return error ?: error2; 656 } 657 658 static int hideep_power_on(struct hideep_ts *ts) 659 { 660 int error = 0; 661 662 error = regulator_enable(ts->vcc_vdd); 663 if (error) 664 dev_err(&ts->client->dev, 665 "failed to enable 'vdd' regulator: %d", error); 666 667 usleep_range(999, 1000); 668 669 error = regulator_enable(ts->vcc_vid); 670 if (error) 671 dev_err(&ts->client->dev, 672 "failed to enable 'vcc_vid' regulator: %d", 673 error); 674 675 msleep(30); 676 677 if (ts->reset_gpio) { 678 gpiod_set_value_cansleep(ts->reset_gpio, 0); 679 } else { 680 error = regmap_write(ts->reg, HIDEEP_RESET_CMD, 0x01); 681 if (error) 682 dev_err(&ts->client->dev, 683 "failed to send 'reset' command: %d\n", error); 684 } 685 686 msleep(50); 687 688 return error; 689 } 690 691 static void hideep_power_off(void *data) 692 { 693 struct hideep_ts *ts = data; 694 695 if (ts->reset_gpio) 696 gpiod_set_value(ts->reset_gpio, 1); 697 698 regulator_disable(ts->vcc_vid); 699 regulator_disable(ts->vcc_vdd); 700 } 701 702 #define __GET_MT_TOOL_TYPE(type) ((type) == 0x01 ? MT_TOOL_FINGER : MT_TOOL_PEN) 703 704 static void hideep_report_slot(struct input_dev *input, 705 const struct hideep_event *event) 706 { 707 input_mt_slot(input, event->index & 0x0f); 708 input_mt_report_slot_state(input, 709 __GET_MT_TOOL_TYPE(event->type), 710 !(event->flag & HIDEEP_MT_RELEASED)); 711 if (!(event->flag & HIDEEP_MT_RELEASED)) { 712 input_report_abs(input, ABS_MT_POSITION_X, 713 le16_to_cpup(&event->x)); 714 input_report_abs(input, ABS_MT_POSITION_Y, 715 le16_to_cpup(&event->y)); 716 input_report_abs(input, ABS_MT_PRESSURE, 717 le16_to_cpup(&event->z)); 718 input_report_abs(input, ABS_MT_TOUCH_MAJOR, event->w); 719 } 720 } 721 722 static void hideep_parse_and_report(struct hideep_ts *ts) 723 { 724 const struct hideep_event *events = 725 (void *)&ts->xfer_buf[HIDEEP_TOUCH_EVENT_INDEX]; 726 const u8 *keys = &ts->xfer_buf[HIDEEP_KEY_EVENT_INDEX]; 727 int touch_count = ts->xfer_buf[0]; 728 int key_count = ts->xfer_buf[1] & 0x0f; 729 int lpm_count = ts->xfer_buf[1] & 0xf0; 730 int i; 731 732 /* get touch event count */ 733 dev_dbg(&ts->client->dev, "mt = %d, key = %d, lpm = %02x", 734 touch_count, key_count, lpm_count); 735 736 touch_count = min(touch_count, HIDEEP_MT_MAX); 737 for (i = 0; i < touch_count; i++) 738 hideep_report_slot(ts->input_dev, events + i); 739 740 key_count = min(key_count, HIDEEP_KEY_MAX); 741 for (i = 0; i < key_count; i++) { 742 u8 key_data = keys[i * 2]; 743 744 input_report_key(ts->input_dev, 745 ts->key_codes[key_data & HIDEEP_KEY_IDX_MASK], 746 key_data & HIDEEP_KEY_PRESSED_MASK); 747 } 748 749 input_mt_sync_frame(ts->input_dev); 750 input_sync(ts->input_dev); 751 } 752 753 static irqreturn_t hideep_irq(int irq, void *handle) 754 { 755 struct hideep_ts *ts = handle; 756 int error; 757 758 BUILD_BUG_ON(HIDEEP_MAX_EVENT > HIDEEP_XFER_BUF_SIZE); 759 760 error = regmap_bulk_read(ts->reg, HIDEEP_EVENT_ADDR, 761 ts->xfer_buf, HIDEEP_MAX_EVENT / 2); 762 if (error) { 763 dev_err(&ts->client->dev, "failed to read events: %d\n", error); 764 goto out; 765 } 766 767 hideep_parse_and_report(ts); 768 769 out: 770 return IRQ_HANDLED; 771 } 772 773 static int hideep_get_axis_info(struct hideep_ts *ts) 774 { 775 __le16 val[2]; 776 int error; 777 778 error = regmap_bulk_read(ts->reg, 0x28, val, ARRAY_SIZE(val)); 779 if (error) 780 return error; 781 782 ts->prop.max_x = le16_to_cpup(val); 783 ts->prop.max_y = le16_to_cpup(val + 1); 784 785 dev_dbg(&ts->client->dev, "X: %d, Y: %d", 786 ts->prop.max_x, ts->prop.max_y); 787 788 return 0; 789 } 790 791 static int hideep_init_input(struct hideep_ts *ts) 792 { 793 struct device *dev = &ts->client->dev; 794 int i; 795 int error; 796 797 ts->input_dev = devm_input_allocate_device(dev); 798 if (!ts->input_dev) { 799 dev_err(dev, "failed to allocate input device\n"); 800 return -ENOMEM; 801 } 802 803 ts->input_dev->name = HIDEEP_TS_NAME; 804 ts->input_dev->id.bustype = BUS_I2C; 805 input_set_drvdata(ts->input_dev, ts); 806 807 input_set_capability(ts->input_dev, EV_ABS, ABS_MT_POSITION_X); 808 input_set_capability(ts->input_dev, EV_ABS, ABS_MT_POSITION_Y); 809 input_set_abs_params(ts->input_dev, ABS_MT_PRESSURE, 0, 65535, 0, 0); 810 input_set_abs_params(ts->input_dev, ABS_MT_TOUCH_MAJOR, 0, 255, 0, 0); 811 input_set_abs_params(ts->input_dev, ABS_MT_TOOL_TYPE, 812 0, MT_TOOL_MAX, 0, 0); 813 touchscreen_parse_properties(ts->input_dev, true, &ts->prop); 814 815 if (ts->prop.max_x == 0 || ts->prop.max_y == 0) { 816 error = hideep_get_axis_info(ts); 817 if (error) 818 return error; 819 } 820 821 error = input_mt_init_slots(ts->input_dev, HIDEEP_MT_MAX, 822 INPUT_MT_DIRECT); 823 if (error) 824 return error; 825 826 ts->key_num = device_property_count_u32(dev, "linux,keycodes"); 827 if (ts->key_num > HIDEEP_KEY_MAX) { 828 dev_err(dev, "too many keys defined: %d\n", 829 ts->key_num); 830 return -EINVAL; 831 } 832 833 if (ts->key_num <= 0) { 834 dev_dbg(dev, 835 "missing or malformed 'linux,keycodes' property\n"); 836 } else { 837 error = device_property_read_u32_array(dev, "linux,keycodes", 838 ts->key_codes, 839 ts->key_num); 840 if (error) { 841 dev_dbg(dev, "failed to read keymap: %d", error); 842 return error; 843 } 844 845 if (ts->key_num) { 846 ts->input_dev->keycode = ts->key_codes; 847 ts->input_dev->keycodesize = sizeof(ts->key_codes[0]); 848 ts->input_dev->keycodemax = ts->key_num; 849 850 for (i = 0; i < ts->key_num; i++) 851 input_set_capability(ts->input_dev, EV_KEY, 852 ts->key_codes[i]); 853 } 854 } 855 856 error = input_register_device(ts->input_dev); 857 if (error) { 858 dev_err(dev, "failed to register input device: %d", error); 859 return error; 860 } 861 862 return 0; 863 } 864 865 static ssize_t hideep_update_fw(struct device *dev, 866 struct device_attribute *attr, 867 const char *buf, size_t count) 868 { 869 struct i2c_client *client = to_i2c_client(dev); 870 struct hideep_ts *ts = i2c_get_clientdata(client); 871 const struct firmware *fw_entry; 872 char *fw_name; 873 int mode; 874 int error; 875 876 error = kstrtoint(buf, 0, &mode); 877 if (error) 878 return error; 879 880 fw_name = kasprintf(GFP_KERNEL, "hideep_ts_%04x.bin", 881 be16_to_cpu(ts->dwz_info.product_id)); 882 if (!fw_name) 883 return -ENOMEM; 884 885 error = request_firmware(&fw_entry, fw_name, dev); 886 if (error) { 887 dev_err(dev, "failed to request firmware %s: %d", 888 fw_name, error); 889 goto out_free_fw_name; 890 } 891 892 if (fw_entry->size % sizeof(__be32)) { 893 dev_err(dev, "invalid firmware size %zu\n", fw_entry->size); 894 error = -EINVAL; 895 goto out_release_fw; 896 } 897 898 if (fw_entry->size > ts->fw_size) { 899 dev_err(dev, "fw size (%zu) is too big (memory size %d)\n", 900 fw_entry->size, ts->fw_size); 901 error = -EFBIG; 902 goto out_release_fw; 903 } 904 905 mutex_lock(&ts->dev_mutex); 906 disable_irq(client->irq); 907 908 error = hideep_update_firmware(ts, (const __be32 *)fw_entry->data, 909 fw_entry->size); 910 911 enable_irq(client->irq); 912 mutex_unlock(&ts->dev_mutex); 913 914 out_release_fw: 915 release_firmware(fw_entry); 916 out_free_fw_name: 917 kfree(fw_name); 918 919 return error ?: count; 920 } 921 922 static ssize_t hideep_fw_version_show(struct device *dev, 923 struct device_attribute *attr, char *buf) 924 { 925 struct i2c_client *client = to_i2c_client(dev); 926 struct hideep_ts *ts = i2c_get_clientdata(client); 927 ssize_t len; 928 929 mutex_lock(&ts->dev_mutex); 930 len = scnprintf(buf, PAGE_SIZE, "%04x\n", 931 be16_to_cpu(ts->dwz_info.release_ver)); 932 mutex_unlock(&ts->dev_mutex); 933 934 return len; 935 } 936 937 static ssize_t hideep_product_id_show(struct device *dev, 938 struct device_attribute *attr, char *buf) 939 { 940 struct i2c_client *client = to_i2c_client(dev); 941 struct hideep_ts *ts = i2c_get_clientdata(client); 942 ssize_t len; 943 944 mutex_lock(&ts->dev_mutex); 945 len = scnprintf(buf, PAGE_SIZE, "%04x\n", 946 be16_to_cpu(ts->dwz_info.product_id)); 947 mutex_unlock(&ts->dev_mutex); 948 949 return len; 950 } 951 952 static DEVICE_ATTR(version, 0664, hideep_fw_version_show, NULL); 953 static DEVICE_ATTR(product_id, 0664, hideep_product_id_show, NULL); 954 static DEVICE_ATTR(update_fw, 0664, NULL, hideep_update_fw); 955 956 static struct attribute *hideep_ts_sysfs_entries[] = { 957 &dev_attr_version.attr, 958 &dev_attr_product_id.attr, 959 &dev_attr_update_fw.attr, 960 NULL, 961 }; 962 963 static const struct attribute_group hideep_ts_attr_group = { 964 .attrs = hideep_ts_sysfs_entries, 965 }; 966 967 static int hideep_suspend(struct device *dev) 968 { 969 struct i2c_client *client = to_i2c_client(dev); 970 struct hideep_ts *ts = i2c_get_clientdata(client); 971 972 disable_irq(client->irq); 973 hideep_power_off(ts); 974 975 return 0; 976 } 977 978 static int hideep_resume(struct device *dev) 979 { 980 struct i2c_client *client = to_i2c_client(dev); 981 struct hideep_ts *ts = i2c_get_clientdata(client); 982 int error; 983 984 error = hideep_power_on(ts); 985 if (error) { 986 dev_err(&client->dev, "power on failed"); 987 return error; 988 } 989 990 enable_irq(client->irq); 991 992 return 0; 993 } 994 995 static DEFINE_SIMPLE_DEV_PM_OPS(hideep_pm_ops, hideep_suspend, hideep_resume); 996 997 static const struct regmap_config hideep_regmap_config = { 998 .reg_bits = 16, 999 .reg_format_endian = REGMAP_ENDIAN_LITTLE, 1000 .val_bits = 16, 1001 .val_format_endian = REGMAP_ENDIAN_LITTLE, 1002 .max_register = 0xffff, 1003 }; 1004 1005 static int hideep_probe(struct i2c_client *client) 1006 { 1007 struct hideep_ts *ts; 1008 int error; 1009 1010 /* check i2c bus */ 1011 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { 1012 dev_err(&client->dev, "check i2c device error"); 1013 return -ENODEV; 1014 } 1015 1016 if (client->irq <= 0) { 1017 dev_err(&client->dev, "missing irq: %d\n", client->irq); 1018 return -EINVAL; 1019 } 1020 1021 ts = devm_kzalloc(&client->dev, sizeof(*ts), GFP_KERNEL); 1022 if (!ts) 1023 return -ENOMEM; 1024 1025 ts->client = client; 1026 i2c_set_clientdata(client, ts); 1027 mutex_init(&ts->dev_mutex); 1028 1029 ts->reg = devm_regmap_init_i2c(client, &hideep_regmap_config); 1030 if (IS_ERR(ts->reg)) { 1031 error = PTR_ERR(ts->reg); 1032 dev_err(&client->dev, 1033 "failed to initialize regmap: %d\n", error); 1034 return error; 1035 } 1036 1037 ts->vcc_vdd = devm_regulator_get(&client->dev, "vdd"); 1038 if (IS_ERR(ts->vcc_vdd)) 1039 return PTR_ERR(ts->vcc_vdd); 1040 1041 ts->vcc_vid = devm_regulator_get(&client->dev, "vid"); 1042 if (IS_ERR(ts->vcc_vid)) 1043 return PTR_ERR(ts->vcc_vid); 1044 1045 ts->reset_gpio = devm_gpiod_get_optional(&client->dev, 1046 "reset", GPIOD_OUT_HIGH); 1047 if (IS_ERR(ts->reset_gpio)) 1048 return PTR_ERR(ts->reset_gpio); 1049 1050 error = hideep_power_on(ts); 1051 if (error) { 1052 dev_err(&client->dev, "power on failed: %d\n", error); 1053 return error; 1054 } 1055 1056 error = devm_add_action_or_reset(&client->dev, hideep_power_off, ts); 1057 if (error) 1058 return error; 1059 1060 error = hideep_load_dwz(ts); 1061 if (error) { 1062 dev_err(&client->dev, "failed to load dwz: %d", error); 1063 return error; 1064 } 1065 1066 error = hideep_init_input(ts); 1067 if (error) 1068 return error; 1069 1070 error = devm_request_threaded_irq(&client->dev, client->irq, 1071 NULL, hideep_irq, IRQF_ONESHOT, 1072 client->name, ts); 1073 if (error) { 1074 dev_err(&client->dev, "failed to request irq %d: %d\n", 1075 client->irq, error); 1076 return error; 1077 } 1078 1079 error = devm_device_add_group(&client->dev, &hideep_ts_attr_group); 1080 if (error) { 1081 dev_err(&client->dev, 1082 "failed to add sysfs attributes: %d\n", error); 1083 return error; 1084 } 1085 1086 return 0; 1087 } 1088 1089 static const struct i2c_device_id hideep_i2c_id[] = { 1090 { HIDEEP_I2C_NAME, 0 }, 1091 { } 1092 }; 1093 MODULE_DEVICE_TABLE(i2c, hideep_i2c_id); 1094 1095 #ifdef CONFIG_ACPI 1096 static const struct acpi_device_id hideep_acpi_id[] = { 1097 { "HIDP0001", 0 }, 1098 { } 1099 }; 1100 MODULE_DEVICE_TABLE(acpi, hideep_acpi_id); 1101 #endif 1102 1103 #ifdef CONFIG_OF 1104 static const struct of_device_id hideep_match_table[] = { 1105 { .compatible = "hideep,hideep-ts" }, 1106 { } 1107 }; 1108 MODULE_DEVICE_TABLE(of, hideep_match_table); 1109 #endif 1110 1111 static struct i2c_driver hideep_driver = { 1112 .driver = { 1113 .name = HIDEEP_I2C_NAME, 1114 .of_match_table = of_match_ptr(hideep_match_table), 1115 .acpi_match_table = ACPI_PTR(hideep_acpi_id), 1116 .pm = pm_sleep_ptr(&hideep_pm_ops), 1117 }, 1118 .id_table = hideep_i2c_id, 1119 .probe_new = hideep_probe, 1120 }; 1121 1122 module_i2c_driver(hideep_driver); 1123 1124 MODULE_DESCRIPTION("Driver for HiDeep Touchscreen Controller"); 1125 MODULE_AUTHOR("anthony.kim@hideep.com"); 1126 MODULE_LICENSE("GPL v2"); 1127