1 #ifndef _QIB_KERNEL_H 2 #define _QIB_KERNEL_H 3 /* 4 * Copyright (c) 2012, 2013 Intel Corporation. All rights reserved. 5 * Copyright (c) 2006 - 2012 QLogic Corporation. All rights reserved. 6 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved. 7 * 8 * This software is available to you under a choice of one of two 9 * licenses. You may choose to be licensed under the terms of the GNU 10 * General Public License (GPL) Version 2, available from the file 11 * COPYING in the main directory of this source tree, or the 12 * OpenIB.org BSD license below: 13 * 14 * Redistribution and use in source and binary forms, with or 15 * without modification, are permitted provided that the following 16 * conditions are met: 17 * 18 * - Redistributions of source code must retain the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer. 21 * 22 * - Redistributions in binary form must reproduce the above 23 * copyright notice, this list of conditions and the following 24 * disclaimer in the documentation and/or other materials 25 * provided with the distribution. 26 * 27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 34 * SOFTWARE. 35 */ 36 37 /* 38 * This header file is the base header file for qlogic_ib kernel code 39 * qib_user.h serves a similar purpose for user code. 40 */ 41 42 #include <linux/interrupt.h> 43 #include <linux/pci.h> 44 #include <linux/dma-mapping.h> 45 #include <linux/mutex.h> 46 #include <linux/list.h> 47 #include <linux/scatterlist.h> 48 #include <linux/slab.h> 49 #include <linux/io.h> 50 #include <linux/fs.h> 51 #include <linux/completion.h> 52 #include <linux/kref.h> 53 #include <linux/sched.h> 54 #include <linux/kthread.h> 55 #include <rdma/rdma_vt.h> 56 57 #include "qib_common.h" 58 #include "qib_verbs.h" 59 60 /* only s/w major version of QLogic_IB we can handle */ 61 #define QIB_CHIP_VERS_MAJ 2U 62 63 /* don't care about this except printing */ 64 #define QIB_CHIP_VERS_MIN 0U 65 66 /* The Organization Unique Identifier (Mfg code), and its position in GUID */ 67 #define QIB_OUI 0x001175 68 #define QIB_OUI_LSB 40 69 70 /* 71 * per driver stats, either not device nor port-specific, or 72 * summed over all of the devices and ports. 73 * They are described by name via ipathfs filesystem, so layout 74 * and number of elements can change without breaking compatibility. 75 * If members are added or deleted qib_statnames[] in qib_fs.c must 76 * change to match. 77 */ 78 struct qlogic_ib_stats { 79 __u64 sps_ints; /* number of interrupts handled */ 80 __u64 sps_errints; /* number of error interrupts */ 81 __u64 sps_txerrs; /* tx-related packet errors */ 82 __u64 sps_rcverrs; /* non-crc rcv packet errors */ 83 __u64 sps_hwerrs; /* hardware errors reported (parity, etc.) */ 84 __u64 sps_nopiobufs; /* no pio bufs avail from kernel */ 85 __u64 sps_ctxts; /* number of contexts currently open */ 86 __u64 sps_lenerrs; /* number of kernel packets where RHF != LRH len */ 87 __u64 sps_buffull; 88 __u64 sps_hdrfull; 89 }; 90 91 extern struct qlogic_ib_stats qib_stats; 92 extern const struct pci_error_handlers qib_pci_err_handler; 93 94 #define QIB_CHIP_SWVERSION QIB_CHIP_VERS_MAJ 95 /* 96 * First-cut critierion for "device is active" is 97 * two thousand dwords combined Tx, Rx traffic per 98 * 5-second interval. SMA packets are 64 dwords, 99 * and occur "a few per second", presumably each way. 100 */ 101 #define QIB_TRAFFIC_ACTIVE_THRESHOLD (2000) 102 103 /* 104 * Struct used to indicate which errors are logged in each of the 105 * error-counters that are logged to EEPROM. A counter is incremented 106 * _once_ (saturating at 255) for each event with any bits set in 107 * the error or hwerror register masks below. 108 */ 109 #define QIB_EEP_LOG_CNT (4) 110 struct qib_eep_log_mask { 111 u64 errs_to_log; 112 u64 hwerrs_to_log; 113 }; 114 115 /* 116 * Below contains all data related to a single context (formerly called port). 117 */ 118 119 #ifdef CONFIG_DEBUG_FS 120 struct qib_opcode_stats_perctx; 121 #endif 122 123 struct qib_ctxtdata { 124 void **rcvegrbuf; 125 dma_addr_t *rcvegrbuf_phys; 126 /* rcvhdrq base, needs mmap before useful */ 127 void *rcvhdrq; 128 /* kernel virtual address where hdrqtail is updated */ 129 void *rcvhdrtail_kvaddr; 130 /* 131 * temp buffer for expected send setup, allocated at open, instead 132 * of each setup call 133 */ 134 void *tid_pg_list; 135 /* 136 * Shared page for kernel to signal user processes that send buffers 137 * need disarming. The process should call QIB_CMD_DISARM_BUFS 138 * or QIB_CMD_ACK_EVENT with IPATH_EVENT_DISARM_BUFS set. 139 */ 140 unsigned long *user_event_mask; 141 /* when waiting for rcv or pioavail */ 142 wait_queue_head_t wait; 143 /* 144 * rcvegr bufs base, physical, must fit 145 * in 44 bits so 32 bit programs mmap64 44 bit works) 146 */ 147 dma_addr_t rcvegr_phys; 148 /* mmap of hdrq, must fit in 44 bits */ 149 dma_addr_t rcvhdrq_phys; 150 dma_addr_t rcvhdrqtailaddr_phys; 151 152 /* 153 * number of opens (including slave sub-contexts) on this instance 154 * (ignoring forks, dup, etc. for now) 155 */ 156 int cnt; 157 /* 158 * how much space to leave at start of eager TID entries for 159 * protocol use, on each TID 160 */ 161 /* instead of calculating it */ 162 unsigned ctxt; 163 /* local node of context */ 164 int node_id; 165 /* non-zero if ctxt is being shared. */ 166 u16 subctxt_cnt; 167 /* non-zero if ctxt is being shared. */ 168 u16 subctxt_id; 169 /* number of eager TID entries. */ 170 u16 rcvegrcnt; 171 /* index of first eager TID entry. */ 172 u16 rcvegr_tid_base; 173 /* number of pio bufs for this ctxt (all procs, if shared) */ 174 u32 piocnt; 175 /* first pio buffer for this ctxt */ 176 u32 pio_base; 177 /* chip offset of PIO buffers for this ctxt */ 178 u32 piobufs; 179 /* how many alloc_pages() chunks in rcvegrbuf_pages */ 180 u32 rcvegrbuf_chunks; 181 /* how many egrbufs per chunk */ 182 u16 rcvegrbufs_perchunk; 183 /* ilog2 of above */ 184 u16 rcvegrbufs_perchunk_shift; 185 /* order for rcvegrbuf_pages */ 186 size_t rcvegrbuf_size; 187 /* rcvhdrq size (for freeing) */ 188 size_t rcvhdrq_size; 189 /* per-context flags for fileops/intr communication */ 190 unsigned long flag; 191 /* next expected TID to check when looking for free */ 192 u32 tidcursor; 193 /* WAIT_RCV that timed out, no interrupt */ 194 u32 rcvwait_to; 195 /* WAIT_PIO that timed out, no interrupt */ 196 u32 piowait_to; 197 /* WAIT_RCV already happened, no wait */ 198 u32 rcvnowait; 199 /* WAIT_PIO already happened, no wait */ 200 u32 pionowait; 201 /* total number of polled urgent packets */ 202 u32 urgent; 203 /* saved total number of polled urgent packets for poll edge trigger */ 204 u32 urgent_poll; 205 /* pid of process using this ctxt */ 206 pid_t pid; 207 pid_t subpid[QLOGIC_IB_MAX_SUBCTXT]; 208 /* same size as task_struct .comm[], command that opened context */ 209 char comm[16]; 210 /* pkeys set by this use of this ctxt */ 211 u16 pkeys[4]; 212 /* so file ops can get at unit */ 213 struct qib_devdata *dd; 214 /* so funcs that need physical port can get it easily */ 215 struct qib_pportdata *ppd; 216 /* A page of memory for rcvhdrhead, rcvegrhead, rcvegrtail * N */ 217 void *subctxt_uregbase; 218 /* An array of pages for the eager receive buffers * N */ 219 void *subctxt_rcvegrbuf; 220 /* An array of pages for the eager header queue entries * N */ 221 void *subctxt_rcvhdr_base; 222 /* The version of the library which opened this ctxt */ 223 u32 userversion; 224 /* Bitmask of active slaves */ 225 u32 active_slaves; 226 /* Type of packets or conditions we want to poll for */ 227 u16 poll_type; 228 /* receive packet sequence counter */ 229 u8 seq_cnt; 230 u8 redirect_seq_cnt; 231 /* ctxt rcvhdrq head offset */ 232 u32 head; 233 /* lookaside fields */ 234 struct rvt_qp *lookaside_qp; 235 u32 lookaside_qpn; 236 /* QPs waiting for context processing */ 237 struct list_head qp_wait_list; 238 #ifdef CONFIG_DEBUG_FS 239 /* verbs stats per CTX */ 240 struct qib_opcode_stats_perctx *opstats; 241 #endif 242 }; 243 244 struct rvt_sge_state; 245 246 struct qib_sdma_txreq { 247 int flags; 248 int sg_count; 249 dma_addr_t addr; 250 void (*callback)(struct qib_sdma_txreq *, int); 251 u16 start_idx; /* sdma private */ 252 u16 next_descq_idx; /* sdma private */ 253 struct list_head list; /* sdma private */ 254 }; 255 256 struct qib_sdma_desc { 257 __le64 qw[2]; 258 }; 259 260 struct qib_verbs_txreq { 261 struct qib_sdma_txreq txreq; 262 struct rvt_qp *qp; 263 struct rvt_swqe *wqe; 264 u32 dwords; 265 u16 hdr_dwords; 266 u16 hdr_inx; 267 struct qib_pio_header *align_buf; 268 struct rvt_mregion *mr; 269 struct rvt_sge_state *ss; 270 }; 271 272 #define QIB_SDMA_TXREQ_F_USELARGEBUF 0x1 273 #define QIB_SDMA_TXREQ_F_HEADTOHOST 0x2 274 #define QIB_SDMA_TXREQ_F_INTREQ 0x4 275 #define QIB_SDMA_TXREQ_F_FREEBUF 0x8 276 #define QIB_SDMA_TXREQ_F_FREEDESC 0x10 277 278 #define QIB_SDMA_TXREQ_S_OK 0 279 #define QIB_SDMA_TXREQ_S_SENDERROR 1 280 #define QIB_SDMA_TXREQ_S_ABORTED 2 281 #define QIB_SDMA_TXREQ_S_SHUTDOWN 3 282 283 /* 284 * Get/Set IB link-level config parameters for f_get/set_ib_cfg() 285 * Mostly for MADs that set or query link parameters, also ipath 286 * config interfaces 287 */ 288 #define QIB_IB_CFG_LIDLMC 0 /* LID (LS16b) and Mask (MS16b) */ 289 #define QIB_IB_CFG_LWID_ENB 2 /* allowed Link-width */ 290 #define QIB_IB_CFG_LWID 3 /* currently active Link-width */ 291 #define QIB_IB_CFG_SPD_ENB 4 /* allowed Link speeds */ 292 #define QIB_IB_CFG_SPD 5 /* current Link spd */ 293 #define QIB_IB_CFG_RXPOL_ENB 6 /* Auto-RX-polarity enable */ 294 #define QIB_IB_CFG_LREV_ENB 7 /* Auto-Lane-reversal enable */ 295 #define QIB_IB_CFG_LINKLATENCY 8 /* Link Latency (IB1.2 only) */ 296 #define QIB_IB_CFG_HRTBT 9 /* IB heartbeat off/enable/auto; DDR/QDR only */ 297 #define QIB_IB_CFG_OP_VLS 10 /* operational VLs */ 298 #define QIB_IB_CFG_VL_HIGH_CAP 11 /* num of VL high priority weights */ 299 #define QIB_IB_CFG_VL_LOW_CAP 12 /* num of VL low priority weights */ 300 #define QIB_IB_CFG_OVERRUN_THRESH 13 /* IB overrun threshold */ 301 #define QIB_IB_CFG_PHYERR_THRESH 14 /* IB PHY error threshold */ 302 #define QIB_IB_CFG_LINKDEFAULT 15 /* IB link default (sleep/poll) */ 303 #define QIB_IB_CFG_PKEYS 16 /* update partition keys */ 304 #define QIB_IB_CFG_MTU 17 /* update MTU in IBC */ 305 #define QIB_IB_CFG_LSTATE 18 /* update linkcmd and linkinitcmd in IBC */ 306 #define QIB_IB_CFG_VL_HIGH_LIMIT 19 307 #define QIB_IB_CFG_PMA_TICKS 20 /* PMA sample tick resolution */ 308 #define QIB_IB_CFG_PORT 21 /* switch port we are connected to */ 309 310 /* 311 * for CFG_LSTATE: LINKCMD in upper 16 bits, LINKINITCMD in lower 16 312 * IB_LINKINITCMD_POLL and SLEEP are also used as set/get values for 313 * QIB_IB_CFG_LINKDEFAULT cmd 314 */ 315 #define IB_LINKCMD_DOWN (0 << 16) 316 #define IB_LINKCMD_ARMED (1 << 16) 317 #define IB_LINKCMD_ACTIVE (2 << 16) 318 #define IB_LINKINITCMD_NOP 0 319 #define IB_LINKINITCMD_POLL 1 320 #define IB_LINKINITCMD_SLEEP 2 321 #define IB_LINKINITCMD_DISABLE 3 322 323 /* 324 * valid states passed to qib_set_linkstate() user call 325 */ 326 #define QIB_IB_LINKDOWN 0 327 #define QIB_IB_LINKARM 1 328 #define QIB_IB_LINKACTIVE 2 329 #define QIB_IB_LINKDOWN_ONLY 3 330 #define QIB_IB_LINKDOWN_SLEEP 4 331 #define QIB_IB_LINKDOWN_DISABLE 5 332 333 /* 334 * These 7 values (SDR, DDR, and QDR may be ORed for auto-speed 335 * negotiation) are used for the 3rd argument to path_f_set_ib_cfg 336 * with cmd QIB_IB_CFG_SPD_ENB, by direct calls or via sysfs. They 337 * are also the the possible values for qib_link_speed_enabled and active 338 * The values were chosen to match values used within the IB spec. 339 */ 340 #define QIB_IB_SDR 1 341 #define QIB_IB_DDR 2 342 #define QIB_IB_QDR 4 343 344 #define QIB_DEFAULT_MTU 4096 345 346 /* max number of IB ports supported per HCA */ 347 #define QIB_MAX_IB_PORTS 2 348 349 /* 350 * Possible IB config parameters for f_get/set_ib_table() 351 */ 352 #define QIB_IB_TBL_VL_HIGH_ARB 1 /* Get/set VL high priority weights */ 353 #define QIB_IB_TBL_VL_LOW_ARB 2 /* Get/set VL low priority weights */ 354 355 /* 356 * Possible "operations" for f_rcvctrl(ppd, op, ctxt) 357 * these are bits so they can be combined, e.g. 358 * QIB_RCVCTRL_INTRAVAIL_ENB | QIB_RCVCTRL_CTXT_ENB 359 */ 360 #define QIB_RCVCTRL_TAILUPD_ENB 0x01 361 #define QIB_RCVCTRL_TAILUPD_DIS 0x02 362 #define QIB_RCVCTRL_CTXT_ENB 0x04 363 #define QIB_RCVCTRL_CTXT_DIS 0x08 364 #define QIB_RCVCTRL_INTRAVAIL_ENB 0x10 365 #define QIB_RCVCTRL_INTRAVAIL_DIS 0x20 366 #define QIB_RCVCTRL_PKEY_ENB 0x40 /* Note, default is enabled */ 367 #define QIB_RCVCTRL_PKEY_DIS 0x80 368 #define QIB_RCVCTRL_BP_ENB 0x0100 369 #define QIB_RCVCTRL_BP_DIS 0x0200 370 #define QIB_RCVCTRL_TIDFLOW_ENB 0x0400 371 #define QIB_RCVCTRL_TIDFLOW_DIS 0x0800 372 373 /* 374 * Possible "operations" for f_sendctrl(ppd, op, var) 375 * these are bits so they can be combined, e.g. 376 * QIB_SENDCTRL_BUFAVAIL_ENB | QIB_SENDCTRL_ENB 377 * Some operations (e.g. DISARM, ABORT) are known to 378 * be "one-shot", so do not modify shadow. 379 */ 380 #define QIB_SENDCTRL_DISARM (0x1000) 381 #define QIB_SENDCTRL_DISARM_BUF(bufn) ((bufn) | QIB_SENDCTRL_DISARM) 382 /* available (0x2000) */ 383 #define QIB_SENDCTRL_AVAIL_DIS (0x4000) 384 #define QIB_SENDCTRL_AVAIL_ENB (0x8000) 385 #define QIB_SENDCTRL_AVAIL_BLIP (0x10000) 386 #define QIB_SENDCTRL_SEND_DIS (0x20000) 387 #define QIB_SENDCTRL_SEND_ENB (0x40000) 388 #define QIB_SENDCTRL_FLUSH (0x80000) 389 #define QIB_SENDCTRL_CLEAR (0x100000) 390 #define QIB_SENDCTRL_DISARM_ALL (0x200000) 391 392 /* 393 * These are the generic indices for requesting per-port 394 * counter values via the f_portcntr function. They 395 * are always returned as 64 bit values, although most 396 * are 32 bit counters. 397 */ 398 /* send-related counters */ 399 #define QIBPORTCNTR_PKTSEND 0U 400 #define QIBPORTCNTR_WORDSEND 1U 401 #define QIBPORTCNTR_PSXMITDATA 2U 402 #define QIBPORTCNTR_PSXMITPKTS 3U 403 #define QIBPORTCNTR_PSXMITWAIT 4U 404 #define QIBPORTCNTR_SENDSTALL 5U 405 /* receive-related counters */ 406 #define QIBPORTCNTR_PKTRCV 6U 407 #define QIBPORTCNTR_PSRCVDATA 7U 408 #define QIBPORTCNTR_PSRCVPKTS 8U 409 #define QIBPORTCNTR_RCVEBP 9U 410 #define QIBPORTCNTR_RCVOVFL 10U 411 #define QIBPORTCNTR_WORDRCV 11U 412 /* IB link related error counters */ 413 #define QIBPORTCNTR_RXLOCALPHYERR 12U 414 #define QIBPORTCNTR_RXVLERR 13U 415 #define QIBPORTCNTR_ERRICRC 14U 416 #define QIBPORTCNTR_ERRVCRC 15U 417 #define QIBPORTCNTR_ERRLPCRC 16U 418 #define QIBPORTCNTR_BADFORMAT 17U 419 #define QIBPORTCNTR_ERR_RLEN 18U 420 #define QIBPORTCNTR_IBSYMBOLERR 19U 421 #define QIBPORTCNTR_INVALIDRLEN 20U 422 #define QIBPORTCNTR_UNSUPVL 21U 423 #define QIBPORTCNTR_EXCESSBUFOVFL 22U 424 #define QIBPORTCNTR_ERRLINK 23U 425 #define QIBPORTCNTR_IBLINKDOWN 24U 426 #define QIBPORTCNTR_IBLINKERRRECOV 25U 427 #define QIBPORTCNTR_LLI 26U 428 /* other error counters */ 429 #define QIBPORTCNTR_RXDROPPKT 27U 430 #define QIBPORTCNTR_VL15PKTDROP 28U 431 #define QIBPORTCNTR_ERRPKEY 29U 432 #define QIBPORTCNTR_KHDROVFL 30U 433 /* sampling counters (these are actually control registers) */ 434 #define QIBPORTCNTR_PSINTERVAL 31U 435 #define QIBPORTCNTR_PSSTART 32U 436 #define QIBPORTCNTR_PSSTAT 33U 437 438 /* how often we check for packet activity for "power on hours (in seconds) */ 439 #define ACTIVITY_TIMER 5 440 441 #define MAX_NAME_SIZE 64 442 443 #ifdef CONFIG_INFINIBAND_QIB_DCA 444 struct qib_irq_notify; 445 #endif 446 447 struct qib_msix_entry { 448 struct msix_entry msix; 449 void *arg; 450 #ifdef CONFIG_INFINIBAND_QIB_DCA 451 int dca; 452 int rcv; 453 struct qib_irq_notify *notifier; 454 #endif 455 char name[MAX_NAME_SIZE]; 456 cpumask_var_t mask; 457 }; 458 459 /* Below is an opaque struct. Each chip (device) can maintain 460 * private data needed for its operation, but not germane to the 461 * rest of the driver. For convenience, we define another that 462 * is chip-specific, per-port 463 */ 464 struct qib_chip_specific; 465 struct qib_chipport_specific; 466 467 enum qib_sdma_states { 468 qib_sdma_state_s00_hw_down, 469 qib_sdma_state_s10_hw_start_up_wait, 470 qib_sdma_state_s20_idle, 471 qib_sdma_state_s30_sw_clean_up_wait, 472 qib_sdma_state_s40_hw_clean_up_wait, 473 qib_sdma_state_s50_hw_halt_wait, 474 qib_sdma_state_s99_running, 475 }; 476 477 enum qib_sdma_events { 478 qib_sdma_event_e00_go_hw_down, 479 qib_sdma_event_e10_go_hw_start, 480 qib_sdma_event_e20_hw_started, 481 qib_sdma_event_e30_go_running, 482 qib_sdma_event_e40_sw_cleaned, 483 qib_sdma_event_e50_hw_cleaned, 484 qib_sdma_event_e60_hw_halted, 485 qib_sdma_event_e70_go_idle, 486 qib_sdma_event_e7220_err_halted, 487 qib_sdma_event_e7322_err_halted, 488 qib_sdma_event_e90_timer_tick, 489 }; 490 491 extern char *qib_sdma_state_names[]; 492 extern char *qib_sdma_event_names[]; 493 494 struct sdma_set_state_action { 495 unsigned op_enable:1; 496 unsigned op_intenable:1; 497 unsigned op_halt:1; 498 unsigned op_drain:1; 499 unsigned go_s99_running_tofalse:1; 500 unsigned go_s99_running_totrue:1; 501 }; 502 503 struct qib_sdma_state { 504 struct kref kref; 505 struct completion comp; 506 enum qib_sdma_states current_state; 507 struct sdma_set_state_action *set_state_action; 508 unsigned current_op; 509 unsigned go_s99_running; 510 unsigned first_sendbuf; 511 unsigned last_sendbuf; /* really last +1 */ 512 /* debugging/devel */ 513 enum qib_sdma_states previous_state; 514 unsigned previous_op; 515 enum qib_sdma_events last_event; 516 }; 517 518 struct xmit_wait { 519 struct timer_list timer; 520 u64 counter; 521 u8 flags; 522 struct cache { 523 u64 psxmitdata; 524 u64 psrcvdata; 525 u64 psxmitpkts; 526 u64 psrcvpkts; 527 u64 psxmitwait; 528 } counter_cache; 529 }; 530 531 /* 532 * The structure below encapsulates data relevant to a physical IB Port. 533 * Current chips support only one such port, but the separation 534 * clarifies things a bit. Note that to conform to IB conventions, 535 * port-numbers are one-based. The first or only port is port1. 536 */ 537 struct qib_pportdata { 538 struct qib_ibport ibport_data; 539 540 struct qib_devdata *dd; 541 struct qib_chippport_specific *cpspec; /* chip-specific per-port */ 542 struct kobject pport_kobj; 543 struct kobject pport_cc_kobj; 544 struct kobject sl2vl_kobj; 545 struct kobject diagc_kobj; 546 547 /* GUID for this interface, in network order */ 548 __be64 guid; 549 550 /* QIB_POLL, etc. link-state specific flags, per port */ 551 u32 lflags; 552 /* qib_lflags driver is waiting for */ 553 u32 state_wanted; 554 spinlock_t lflags_lock; 555 556 /* ref count for each pkey */ 557 atomic_t pkeyrefs[4]; 558 559 /* 560 * this address is mapped readonly into user processes so they can 561 * get status cheaply, whenever they want. One qword of status per port 562 */ 563 u64 *statusp; 564 565 /* SendDMA related entries */ 566 567 /* read mostly */ 568 struct qib_sdma_desc *sdma_descq; 569 struct workqueue_struct *qib_wq; 570 struct qib_sdma_state sdma_state; 571 dma_addr_t sdma_descq_phys; 572 volatile __le64 *sdma_head_dma; /* DMA'ed by chip */ 573 dma_addr_t sdma_head_phys; 574 u16 sdma_descq_cnt; 575 576 /* read/write using lock */ 577 spinlock_t sdma_lock ____cacheline_aligned_in_smp; 578 struct list_head sdma_activelist; 579 struct list_head sdma_userpending; 580 u64 sdma_descq_added; 581 u64 sdma_descq_removed; 582 u16 sdma_descq_tail; 583 u16 sdma_descq_head; 584 u8 sdma_generation; 585 u8 sdma_intrequest; 586 587 struct tasklet_struct sdma_sw_clean_up_task 588 ____cacheline_aligned_in_smp; 589 590 wait_queue_head_t state_wait; /* for state_wanted */ 591 592 /* HoL blocking for SMP replies */ 593 unsigned hol_state; 594 struct timer_list hol_timer; 595 596 /* 597 * Shadow copies of registers; size indicates read access size. 598 * Most of them are readonly, but some are write-only register, 599 * where we manipulate the bits in the shadow copy, and then write 600 * the shadow copy to qlogic_ib. 601 * 602 * We deliberately make most of these 32 bits, since they have 603 * restricted range. For any that we read, we won't to generate 32 604 * bit accesses, since Opteron will generate 2 separate 32 bit HT 605 * transactions for a 64 bit read, and we want to avoid unnecessary 606 * bus transactions. 607 */ 608 609 /* This is the 64 bit group */ 610 /* last ibcstatus. opaque outside chip-specific code */ 611 u64 lastibcstat; 612 613 /* these are the "32 bit" regs */ 614 615 /* 616 * the following two are 32-bit bitmasks, but {test,clear,set}_bit 617 * all expect bit fields to be "unsigned long" 618 */ 619 unsigned long p_rcvctrl; /* shadow per-port rcvctrl */ 620 unsigned long p_sendctrl; /* shadow per-port sendctrl */ 621 622 u32 ibmtu; /* The MTU programmed for this unit */ 623 /* 624 * Current max size IB packet (in bytes) including IB headers, that 625 * we can send. Changes when ibmtu changes. 626 */ 627 u32 ibmaxlen; 628 /* 629 * ibmaxlen at init time, limited by chip and by receive buffer 630 * size. Not changed after init. 631 */ 632 u32 init_ibmaxlen; 633 /* LID programmed for this instance */ 634 u16 lid; 635 /* list of pkeys programmed; 0 if not set */ 636 u16 pkeys[4]; 637 /* LID mask control */ 638 u8 lmc; 639 u8 link_width_supported; 640 u8 link_speed_supported; 641 u8 link_width_enabled; 642 u8 link_speed_enabled; 643 u8 link_width_active; 644 u8 link_speed_active; 645 u8 vls_supported; 646 u8 vls_operational; 647 /* Rx Polarity inversion (compensate for ~tx on partner) */ 648 u8 rx_pol_inv; 649 650 u8 hw_pidx; /* physical port index */ 651 u8 port; /* IB port number and index into dd->pports - 1 */ 652 653 u8 delay_mult; 654 655 /* used to override LED behavior */ 656 u8 led_override; /* Substituted for normal value, if non-zero */ 657 u16 led_override_timeoff; /* delta to next timer event */ 658 u8 led_override_vals[2]; /* Alternates per blink-frame */ 659 u8 led_override_phase; /* Just counts, LSB picks from vals[] */ 660 atomic_t led_override_timer_active; 661 /* Used to flash LEDs in override mode */ 662 struct timer_list led_override_timer; 663 struct xmit_wait cong_stats; 664 struct timer_list symerr_clear_timer; 665 666 /* Synchronize access between driver writes and sysfs reads */ 667 spinlock_t cc_shadow_lock 668 ____cacheline_aligned_in_smp; 669 670 /* Shadow copy of the congestion control table */ 671 struct cc_table_shadow *ccti_entries_shadow; 672 673 /* Shadow copy of the congestion control entries */ 674 struct ib_cc_congestion_setting_attr_shadow *congestion_entries_shadow; 675 676 /* List of congestion control table entries */ 677 struct ib_cc_table_entry_shadow *ccti_entries; 678 679 /* 16 congestion entries with each entry corresponding to a SL */ 680 struct ib_cc_congestion_entry_shadow *congestion_entries; 681 682 /* Maximum number of congestion control entries that the agent expects 683 * the manager to send. 684 */ 685 u16 cc_supported_table_entries; 686 687 /* Total number of congestion control table entries */ 688 u16 total_cct_entry; 689 690 /* Bit map identifying service level */ 691 u16 cc_sl_control_map; 692 693 /* maximum congestion control table index */ 694 u16 ccti_limit; 695 696 /* CA's max number of 64 entry units in the congestion control table */ 697 u8 cc_max_table_entries; 698 }; 699 700 /* Observers. Not to be taken lightly, possibly not to ship. */ 701 /* 702 * If a diag read or write is to (bottom <= offset <= top), 703 * the "hoook" is called, allowing, e.g. shadows to be 704 * updated in sync with the driver. struct diag_observer 705 * is the "visible" part. 706 */ 707 struct diag_observer; 708 709 typedef int (*diag_hook) (struct qib_devdata *dd, 710 const struct diag_observer *op, 711 u32 offs, u64 *data, u64 mask, int only_32); 712 713 struct diag_observer { 714 diag_hook hook; 715 u32 bottom; 716 u32 top; 717 }; 718 719 extern int qib_register_observer(struct qib_devdata *dd, 720 const struct diag_observer *op); 721 722 /* Only declared here, not defined. Private to diags */ 723 struct diag_observer_list_elt; 724 725 /* device data struct now contains only "general per-device" info. 726 * fields related to a physical IB port are in a qib_pportdata struct, 727 * described above) while fields only used by a particular chip-type are in 728 * a qib_chipdata struct, whose contents are opaque to this file. 729 */ 730 struct qib_devdata { 731 struct qib_ibdev verbs_dev; /* must be first */ 732 struct list_head list; 733 /* pointers to related structs for this device */ 734 /* pci access data structure */ 735 struct pci_dev *pcidev; 736 struct cdev *user_cdev; 737 struct cdev *diag_cdev; 738 struct device *user_device; 739 struct device *diag_device; 740 741 /* mem-mapped pointer to base of chip regs */ 742 u64 __iomem *kregbase; 743 /* end of mem-mapped chip space excluding sendbuf and user regs */ 744 u64 __iomem *kregend; 745 /* physical address of chip for io_remap, etc. */ 746 resource_size_t physaddr; 747 /* qib_cfgctxts pointers */ 748 struct qib_ctxtdata **rcd; /* Receive Context Data */ 749 750 /* qib_pportdata, points to array of (physical) port-specific 751 * data structs, indexed by pidx (0..n-1) 752 */ 753 struct qib_pportdata *pport; 754 struct qib_chip_specific *cspec; /* chip-specific */ 755 756 /* kvirt address of 1st 2k pio buffer */ 757 void __iomem *pio2kbase; 758 /* kvirt address of 1st 4k pio buffer */ 759 void __iomem *pio4kbase; 760 /* mem-mapped pointer to base of PIO buffers (if using WC PAT) */ 761 void __iomem *piobase; 762 /* mem-mapped pointer to base of user chip regs (if using WC PAT) */ 763 u64 __iomem *userbase; 764 void __iomem *piovl15base; /* base of VL15 buffers, if not WC */ 765 /* 766 * points to area where PIOavail registers will be DMA'ed. 767 * Has to be on a page of it's own, because the page will be 768 * mapped into user program space. This copy is *ONLY* ever 769 * written by DMA, not by the driver! Need a copy per device 770 * when we get to multiple devices 771 */ 772 volatile __le64 *pioavailregs_dma; /* DMA'ed by chip */ 773 /* physical address where updates occur */ 774 dma_addr_t pioavailregs_phys; 775 776 /* device-specific implementations of functions needed by 777 * common code. Contrary to previous consensus, we can't 778 * really just point to a device-specific table, because we 779 * may need to "bend", e.g. *_f_put_tid 780 */ 781 /* fallback to alternate interrupt type if possible */ 782 int (*f_intr_fallback)(struct qib_devdata *); 783 /* hard reset chip */ 784 int (*f_reset)(struct qib_devdata *); 785 void (*f_quiet_serdes)(struct qib_pportdata *); 786 int (*f_bringup_serdes)(struct qib_pportdata *); 787 int (*f_early_init)(struct qib_devdata *); 788 void (*f_clear_tids)(struct qib_devdata *, struct qib_ctxtdata *); 789 void (*f_put_tid)(struct qib_devdata *, u64 __iomem*, 790 u32, unsigned long); 791 void (*f_cleanup)(struct qib_devdata *); 792 void (*f_setextled)(struct qib_pportdata *, u32); 793 /* fill out chip-specific fields */ 794 int (*f_get_base_info)(struct qib_ctxtdata *, struct qib_base_info *); 795 /* free irq */ 796 void (*f_free_irq)(struct qib_devdata *); 797 struct qib_message_header *(*f_get_msgheader) 798 (struct qib_devdata *, __le32 *); 799 void (*f_config_ctxts)(struct qib_devdata *); 800 int (*f_get_ib_cfg)(struct qib_pportdata *, int); 801 int (*f_set_ib_cfg)(struct qib_pportdata *, int, u32); 802 int (*f_set_ib_loopback)(struct qib_pportdata *, const char *); 803 int (*f_get_ib_table)(struct qib_pportdata *, int, void *); 804 int (*f_set_ib_table)(struct qib_pportdata *, int, void *); 805 u32 (*f_iblink_state)(u64); 806 u8 (*f_ibphys_portstate)(u64); 807 void (*f_xgxs_reset)(struct qib_pportdata *); 808 /* per chip actions needed for IB Link up/down changes */ 809 int (*f_ib_updown)(struct qib_pportdata *, int, u64); 810 u32 __iomem *(*f_getsendbuf)(struct qib_pportdata *, u64, u32 *); 811 /* Read/modify/write of GPIO pins (potentially chip-specific */ 812 int (*f_gpio_mod)(struct qib_devdata *dd, u32 out, u32 dir, 813 u32 mask); 814 /* Enable writes to config EEPROM (if supported) */ 815 int (*f_eeprom_wen)(struct qib_devdata *dd, int wen); 816 /* 817 * modify rcvctrl shadow[s] and write to appropriate chip-regs. 818 * see above QIB_RCVCTRL_xxx_ENB/DIS for operations. 819 * (ctxt == -1) means "all contexts", only meaningful for 820 * clearing. Could remove if chip_spec shutdown properly done. 821 */ 822 void (*f_rcvctrl)(struct qib_pportdata *, unsigned int op, 823 int ctxt); 824 /* Read/modify/write sendctrl appropriately for op and port. */ 825 void (*f_sendctrl)(struct qib_pportdata *, u32 op); 826 void (*f_set_intr_state)(struct qib_devdata *, u32); 827 void (*f_set_armlaunch)(struct qib_devdata *, u32); 828 void (*f_wantpiobuf_intr)(struct qib_devdata *, u32); 829 int (*f_late_initreg)(struct qib_devdata *); 830 int (*f_init_sdma_regs)(struct qib_pportdata *); 831 u16 (*f_sdma_gethead)(struct qib_pportdata *); 832 int (*f_sdma_busy)(struct qib_pportdata *); 833 void (*f_sdma_update_tail)(struct qib_pportdata *, u16); 834 void (*f_sdma_set_desc_cnt)(struct qib_pportdata *, unsigned); 835 void (*f_sdma_sendctrl)(struct qib_pportdata *, unsigned); 836 void (*f_sdma_hw_clean_up)(struct qib_pportdata *); 837 void (*f_sdma_hw_start_up)(struct qib_pportdata *); 838 void (*f_sdma_init_early)(struct qib_pportdata *); 839 void (*f_set_cntr_sample)(struct qib_pportdata *, u32, u32); 840 void (*f_update_usrhead)(struct qib_ctxtdata *, u64, u32, u32, u32); 841 u32 (*f_hdrqempty)(struct qib_ctxtdata *); 842 u64 (*f_portcntr)(struct qib_pportdata *, u32); 843 u32 (*f_read_cntrs)(struct qib_devdata *, loff_t, char **, 844 u64 **); 845 u32 (*f_read_portcntrs)(struct qib_devdata *, loff_t, u32, 846 char **, u64 **); 847 u32 (*f_setpbc_control)(struct qib_pportdata *, u32, u8, u8); 848 void (*f_initvl15_bufs)(struct qib_devdata *); 849 void (*f_init_ctxt)(struct qib_ctxtdata *); 850 void (*f_txchk_change)(struct qib_devdata *, u32, u32, u32, 851 struct qib_ctxtdata *); 852 void (*f_writescratch)(struct qib_devdata *, u32); 853 int (*f_tempsense_rd)(struct qib_devdata *, int regnum); 854 #ifdef CONFIG_INFINIBAND_QIB_DCA 855 int (*f_notify_dca)(struct qib_devdata *, unsigned long event); 856 #endif 857 858 char *boardname; /* human readable board info */ 859 860 /* template for writing TIDs */ 861 u64 tidtemplate; 862 /* value to write to free TIDs */ 863 u64 tidinvalid; 864 865 /* number of registers used for pioavail */ 866 u32 pioavregs; 867 /* device (not port) flags, basically device capabilities */ 868 u32 flags; 869 /* last buffer for user use */ 870 u32 lastctxt_piobuf; 871 872 /* reset value */ 873 u64 z_int_counter; 874 /* percpu intcounter */ 875 u64 __percpu *int_counter; 876 877 /* pio bufs allocated per ctxt */ 878 u32 pbufsctxt; 879 /* if remainder on bufs/ctxt, ctxts < extrabuf get 1 extra */ 880 u32 ctxts_extrabuf; 881 /* 882 * number of ctxts configured as max; zero is set to number chip 883 * supports, less gives more pio bufs/ctxt, etc. 884 */ 885 u32 cfgctxts; 886 /* 887 * number of ctxts available for PSM open 888 */ 889 u32 freectxts; 890 891 /* 892 * hint that we should update pioavailshadow before 893 * looking for a PIO buffer 894 */ 895 u32 upd_pio_shadow; 896 897 /* internal debugging stats */ 898 u32 maxpkts_call; 899 u32 avgpkts_call; 900 u64 nopiobufs; 901 902 /* PCI Vendor ID (here for NodeInfo) */ 903 u16 vendorid; 904 /* PCI Device ID (here for NodeInfo) */ 905 u16 deviceid; 906 /* for write combining settings */ 907 int wc_cookie; 908 unsigned long wc_base; 909 unsigned long wc_len; 910 911 /* shadow copy of struct page *'s for exp tid pages */ 912 struct page **pageshadow; 913 /* shadow copy of dma handles for exp tid pages */ 914 dma_addr_t *physshadow; 915 u64 __iomem *egrtidbase; 916 spinlock_t sendctrl_lock; /* protect changes to sendctrl shadow */ 917 /* around rcd and (user ctxts) ctxt_cnt use (intr vs free) */ 918 spinlock_t uctxt_lock; /* rcd and user context changes */ 919 /* 920 * per unit status, see also portdata statusp 921 * mapped readonly into user processes so they can get unit and 922 * IB link status cheaply 923 */ 924 u64 *devstatusp; 925 char *freezemsg; /* freeze msg if hw error put chip in freeze */ 926 u32 freezelen; /* max length of freezemsg */ 927 /* timer used to prevent stats overflow, error throttling, etc. */ 928 struct timer_list stats_timer; 929 930 /* timer to verify interrupts work, and fallback if possible */ 931 struct timer_list intrchk_timer; 932 unsigned long ureg_align; /* user register alignment */ 933 934 /* 935 * Protects pioavailshadow, pioavailkernel, pio_need_disarm, and 936 * pio_writing. 937 */ 938 spinlock_t pioavail_lock; 939 /* 940 * index of last buffer to optimize search for next 941 */ 942 u32 last_pio; 943 /* 944 * min kernel pio buffer to optimize search 945 */ 946 u32 min_kernel_pio; 947 /* 948 * Shadow copies of registers; size indicates read access size. 949 * Most of them are readonly, but some are write-only register, 950 * where we manipulate the bits in the shadow copy, and then write 951 * the shadow copy to qlogic_ib. 952 * 953 * We deliberately make most of these 32 bits, since they have 954 * restricted range. For any that we read, we won't to generate 32 955 * bit accesses, since Opteron will generate 2 separate 32 bit HT 956 * transactions for a 64 bit read, and we want to avoid unnecessary 957 * bus transactions. 958 */ 959 960 /* This is the 64 bit group */ 961 962 unsigned long pioavailshadow[6]; 963 /* bitmap of send buffers available for the kernel to use with PIO. */ 964 unsigned long pioavailkernel[6]; 965 /* bitmap of send buffers which need to be disarmed. */ 966 unsigned long pio_need_disarm[3]; 967 /* bitmap of send buffers which are being written to. */ 968 unsigned long pio_writing[3]; 969 /* kr_revision shadow */ 970 u64 revision; 971 /* Base GUID for device (from eeprom, network order) */ 972 __be64 base_guid; 973 974 /* 975 * kr_sendpiobufbase value (chip offset of pio buffers), and the 976 * base of the 2KB buffer s(user processes only use 2K) 977 */ 978 u64 piobufbase; 979 u32 pio2k_bufbase; 980 981 /* these are the "32 bit" regs */ 982 983 /* number of GUIDs in the flash for this interface */ 984 u32 nguid; 985 /* 986 * the following two are 32-bit bitmasks, but {test,clear,set}_bit 987 * all expect bit fields to be "unsigned long" 988 */ 989 unsigned long rcvctrl; /* shadow per device rcvctrl */ 990 unsigned long sendctrl; /* shadow per device sendctrl */ 991 992 /* value we put in kr_rcvhdrcnt */ 993 u32 rcvhdrcnt; 994 /* value we put in kr_rcvhdrsize */ 995 u32 rcvhdrsize; 996 /* value we put in kr_rcvhdrentsize */ 997 u32 rcvhdrentsize; 998 /* kr_ctxtcnt value */ 999 u32 ctxtcnt; 1000 /* kr_pagealign value */ 1001 u32 palign; 1002 /* number of "2KB" PIO buffers */ 1003 u32 piobcnt2k; 1004 /* size in bytes of "2KB" PIO buffers */ 1005 u32 piosize2k; 1006 /* max usable size in dwords of a "2KB" PIO buffer before going "4KB" */ 1007 u32 piosize2kmax_dwords; 1008 /* number of "4KB" PIO buffers */ 1009 u32 piobcnt4k; 1010 /* size in bytes of "4KB" PIO buffers */ 1011 u32 piosize4k; 1012 /* kr_rcvegrbase value */ 1013 u32 rcvegrbase; 1014 /* kr_rcvtidbase value */ 1015 u32 rcvtidbase; 1016 /* kr_rcvtidcnt value */ 1017 u32 rcvtidcnt; 1018 /* kr_userregbase */ 1019 u32 uregbase; 1020 /* shadow the control register contents */ 1021 u32 control; 1022 1023 /* chip address space used by 4k pio buffers */ 1024 u32 align4k; 1025 /* size of each rcvegrbuffer */ 1026 u16 rcvegrbufsize; 1027 /* log2 of above */ 1028 u16 rcvegrbufsize_shift; 1029 /* localbus width (1, 2,4,8,16,32) from config space */ 1030 u32 lbus_width; 1031 /* localbus speed in MHz */ 1032 u32 lbus_speed; 1033 int unit; /* unit # of this chip */ 1034 1035 /* start of CHIP_SPEC move to chipspec, but need code changes */ 1036 /* low and high portions of MSI capability/vector */ 1037 u32 msi_lo; 1038 /* saved after PCIe init for restore after reset */ 1039 u32 msi_hi; 1040 /* MSI data (vector) saved for restore */ 1041 u16 msi_data; 1042 /* so we can rewrite it after a chip reset */ 1043 u32 pcibar0; 1044 /* so we can rewrite it after a chip reset */ 1045 u32 pcibar1; 1046 u64 rhdrhead_intr_off; 1047 1048 /* 1049 * ASCII serial number, from flash, large enough for original 1050 * all digit strings, and longer QLogic serial number format 1051 */ 1052 u8 serial[16]; 1053 /* human readable board version */ 1054 u8 boardversion[96]; 1055 u8 lbus_info[32]; /* human readable localbus info */ 1056 /* chip major rev, from qib_revision */ 1057 u8 majrev; 1058 /* chip minor rev, from qib_revision */ 1059 u8 minrev; 1060 1061 /* Misc small ints */ 1062 /* Number of physical ports available */ 1063 u8 num_pports; 1064 /* Lowest context number which can be used by user processes */ 1065 u8 first_user_ctxt; 1066 u8 n_krcv_queues; 1067 u8 qpn_mask; 1068 u8 skip_kctxt_mask; 1069 1070 u16 rhf_offset; /* offset of RHF within receive header entry */ 1071 1072 /* 1073 * GPIO pins for twsi-connected devices, and device code for eeprom 1074 */ 1075 u8 gpio_sda_num; 1076 u8 gpio_scl_num; 1077 u8 twsi_eeprom_dev; 1078 u8 board_atten; 1079 1080 /* Support (including locks) for EEPROM logging of errors and time */ 1081 /* control access to actual counters, timer */ 1082 spinlock_t eep_st_lock; 1083 /* control high-level access to EEPROM */ 1084 struct mutex eep_lock; 1085 uint64_t traffic_wds; 1086 /* 1087 * masks for which bits of errs, hwerrs that cause 1088 * each of the counters to increment. 1089 */ 1090 struct qib_eep_log_mask eep_st_masks[QIB_EEP_LOG_CNT]; 1091 struct qib_diag_client *diag_client; 1092 spinlock_t qib_diag_trans_lock; /* protect diag observer ops */ 1093 struct diag_observer_list_elt *diag_observer_list; 1094 1095 u8 psxmitwait_supported; 1096 /* cycle length of PS* counters in HW (in picoseconds) */ 1097 u16 psxmitwait_check_rate; 1098 /* high volume overflow errors defered to tasklet */ 1099 struct tasklet_struct error_tasklet; 1100 1101 int assigned_node_id; /* NUMA node closest to HCA */ 1102 }; 1103 1104 /* hol_state values */ 1105 #define QIB_HOL_UP 0 1106 #define QIB_HOL_INIT 1 1107 1108 #define QIB_SDMA_SENDCTRL_OP_ENABLE (1U << 0) 1109 #define QIB_SDMA_SENDCTRL_OP_INTENABLE (1U << 1) 1110 #define QIB_SDMA_SENDCTRL_OP_HALT (1U << 2) 1111 #define QIB_SDMA_SENDCTRL_OP_CLEANUP (1U << 3) 1112 #define QIB_SDMA_SENDCTRL_OP_DRAIN (1U << 4) 1113 1114 /* operation types for f_txchk_change() */ 1115 #define TXCHK_CHG_TYPE_DIS1 3 1116 #define TXCHK_CHG_TYPE_ENAB1 2 1117 #define TXCHK_CHG_TYPE_KERN 1 1118 #define TXCHK_CHG_TYPE_USER 0 1119 1120 #define QIB_CHASE_TIME msecs_to_jiffies(145) 1121 #define QIB_CHASE_DIS_TIME msecs_to_jiffies(160) 1122 1123 /* Private data for file operations */ 1124 struct qib_filedata { 1125 struct qib_ctxtdata *rcd; 1126 unsigned subctxt; 1127 unsigned tidcursor; 1128 struct qib_user_sdma_queue *pq; 1129 int rec_cpu_num; /* for cpu affinity; -1 if none */ 1130 }; 1131 1132 extern struct list_head qib_dev_list; 1133 extern spinlock_t qib_devs_lock; 1134 extern struct qib_devdata *qib_lookup(int unit); 1135 extern u32 qib_cpulist_count; 1136 extern unsigned long *qib_cpulist; 1137 extern u16 qpt_mask; 1138 extern unsigned qib_cc_table_size; 1139 1140 int qib_init(struct qib_devdata *, int); 1141 int init_chip_wc_pat(struct qib_devdata *dd, u32); 1142 int qib_enable_wc(struct qib_devdata *dd); 1143 void qib_disable_wc(struct qib_devdata *dd); 1144 int qib_count_units(int *npresentp, int *nupp); 1145 int qib_count_active_units(void); 1146 1147 int qib_cdev_init(int minor, const char *name, 1148 const struct file_operations *fops, 1149 struct cdev **cdevp, struct device **devp); 1150 void qib_cdev_cleanup(struct cdev **cdevp, struct device **devp); 1151 int qib_dev_init(void); 1152 void qib_dev_cleanup(void); 1153 1154 int qib_diag_add(struct qib_devdata *); 1155 void qib_diag_remove(struct qib_devdata *); 1156 void qib_handle_e_ibstatuschanged(struct qib_pportdata *, u64); 1157 void qib_sdma_update_tail(struct qib_pportdata *, u16); /* hold sdma_lock */ 1158 1159 int qib_decode_err(struct qib_devdata *dd, char *buf, size_t blen, u64 err); 1160 void qib_bad_intrstatus(struct qib_devdata *); 1161 void qib_handle_urcv(struct qib_devdata *, u64); 1162 1163 /* clean up any per-chip chip-specific stuff */ 1164 void qib_chip_cleanup(struct qib_devdata *); 1165 /* clean up any chip type-specific stuff */ 1166 void qib_chip_done(void); 1167 1168 /* check to see if we have to force ordering for write combining */ 1169 int qib_unordered_wc(void); 1170 void qib_pio_copy(void __iomem *to, const void *from, size_t count); 1171 1172 void qib_disarm_piobufs(struct qib_devdata *, unsigned, unsigned); 1173 int qib_disarm_piobufs_ifneeded(struct qib_ctxtdata *); 1174 void qib_disarm_piobufs_set(struct qib_devdata *, unsigned long *, unsigned); 1175 void qib_cancel_sends(struct qib_pportdata *); 1176 1177 int qib_create_rcvhdrq(struct qib_devdata *, struct qib_ctxtdata *); 1178 int qib_setup_eagerbufs(struct qib_ctxtdata *); 1179 void qib_set_ctxtcnt(struct qib_devdata *); 1180 int qib_create_ctxts(struct qib_devdata *dd); 1181 struct qib_ctxtdata *qib_create_ctxtdata(struct qib_pportdata *, u32, int); 1182 int qib_init_pportdata(struct qib_pportdata *, struct qib_devdata *, u8, u8); 1183 void qib_free_ctxtdata(struct qib_devdata *, struct qib_ctxtdata *); 1184 1185 u32 qib_kreceive(struct qib_ctxtdata *, u32 *, u32 *); 1186 int qib_reset_device(int); 1187 int qib_wait_linkstate(struct qib_pportdata *, u32, int); 1188 int qib_set_linkstate(struct qib_pportdata *, u8); 1189 int qib_set_mtu(struct qib_pportdata *, u16); 1190 int qib_set_lid(struct qib_pportdata *, u32, u8); 1191 void qib_hol_down(struct qib_pportdata *); 1192 void qib_hol_init(struct qib_pportdata *); 1193 void qib_hol_up(struct qib_pportdata *); 1194 void qib_hol_event(unsigned long); 1195 void qib_disable_after_error(struct qib_devdata *); 1196 int qib_set_uevent_bits(struct qib_pportdata *, const int); 1197 1198 /* for use in system calls, where we want to know device type, etc. */ 1199 #define ctxt_fp(fp) \ 1200 (((struct qib_filedata *)(fp)->private_data)->rcd) 1201 #define subctxt_fp(fp) \ 1202 (((struct qib_filedata *)(fp)->private_data)->subctxt) 1203 #define tidcursor_fp(fp) \ 1204 (((struct qib_filedata *)(fp)->private_data)->tidcursor) 1205 #define user_sdma_queue_fp(fp) \ 1206 (((struct qib_filedata *)(fp)->private_data)->pq) 1207 1208 static inline struct qib_devdata *dd_from_ppd(struct qib_pportdata *ppd) 1209 { 1210 return ppd->dd; 1211 } 1212 1213 static inline struct qib_devdata *dd_from_dev(struct qib_ibdev *dev) 1214 { 1215 return container_of(dev, struct qib_devdata, verbs_dev); 1216 } 1217 1218 static inline struct qib_devdata *dd_from_ibdev(struct ib_device *ibdev) 1219 { 1220 return dd_from_dev(to_idev(ibdev)); 1221 } 1222 1223 static inline struct qib_pportdata *ppd_from_ibp(struct qib_ibport *ibp) 1224 { 1225 return container_of(ibp, struct qib_pportdata, ibport_data); 1226 } 1227 1228 static inline struct qib_ibport *to_iport(struct ib_device *ibdev, u8 port) 1229 { 1230 struct qib_devdata *dd = dd_from_ibdev(ibdev); 1231 unsigned pidx = port - 1; /* IB number port from 1, hdw from 0 */ 1232 1233 WARN_ON(pidx >= dd->num_pports); 1234 return &dd->pport[pidx].ibport_data; 1235 } 1236 1237 /* 1238 * values for dd->flags (_device_ related flags) and 1239 */ 1240 #define QIB_HAS_LINK_LATENCY 0x1 /* supports link latency (IB 1.2) */ 1241 #define QIB_INITTED 0x2 /* chip and driver up and initted */ 1242 #define QIB_DOING_RESET 0x4 /* in the middle of doing chip reset */ 1243 #define QIB_PRESENT 0x8 /* chip accesses can be done */ 1244 #define QIB_PIO_FLUSH_WC 0x10 /* Needs Write combining flush for PIO */ 1245 #define QIB_HAS_THRESH_UPDATE 0x40 1246 #define QIB_HAS_SDMA_TIMEOUT 0x80 1247 #define QIB_USE_SPCL_TRIG 0x100 /* SpecialTrigger launch enabled */ 1248 #define QIB_NODMA_RTAIL 0x200 /* rcvhdrtail register DMA enabled */ 1249 #define QIB_HAS_INTX 0x800 /* Supports INTx interrupts */ 1250 #define QIB_HAS_SEND_DMA 0x1000 /* Supports Send DMA */ 1251 #define QIB_HAS_VLSUPP 0x2000 /* Supports multiple VLs; PBC different */ 1252 #define QIB_HAS_HDRSUPP 0x4000 /* Supports header suppression */ 1253 #define QIB_BADINTR 0x8000 /* severe interrupt problems */ 1254 #define QIB_DCA_ENABLED 0x10000 /* Direct Cache Access enabled */ 1255 #define QIB_HAS_QSFP 0x20000 /* device (card instance) has QSFP */ 1256 1257 /* 1258 * values for ppd->lflags (_ib_port_ related flags) 1259 */ 1260 #define QIBL_LINKV 0x1 /* IB link state valid */ 1261 #define QIBL_LINKDOWN 0x8 /* IB link is down */ 1262 #define QIBL_LINKINIT 0x10 /* IB link level is up */ 1263 #define QIBL_LINKARMED 0x20 /* IB link is ARMED */ 1264 #define QIBL_LINKACTIVE 0x40 /* IB link is ACTIVE */ 1265 /* leave a gap for more IB-link state */ 1266 #define QIBL_IB_AUTONEG_INPROG 0x1000 /* non-IBTA DDR/QDR neg active */ 1267 #define QIBL_IB_AUTONEG_FAILED 0x2000 /* non-IBTA DDR/QDR neg failed */ 1268 #define QIBL_IB_LINK_DISABLED 0x4000 /* Linkdown-disable forced, 1269 * Do not try to bring up */ 1270 #define QIBL_IB_FORCE_NOTIFY 0x8000 /* force notify on next ib change */ 1271 1272 /* IB dword length mask in PBC (lower 11 bits); same for all chips */ 1273 #define QIB_PBC_LENGTH_MASK ((1 << 11) - 1) 1274 1275 1276 /* ctxt_flag bit offsets */ 1277 /* waiting for a packet to arrive */ 1278 #define QIB_CTXT_WAITING_RCV 2 1279 /* master has not finished initializing */ 1280 #define QIB_CTXT_MASTER_UNINIT 4 1281 /* waiting for an urgent packet to arrive */ 1282 #define QIB_CTXT_WAITING_URG 5 1283 1284 /* free up any allocated data at closes */ 1285 void qib_free_data(struct qib_ctxtdata *dd); 1286 void qib_chg_pioavailkernel(struct qib_devdata *, unsigned, unsigned, 1287 u32, struct qib_ctxtdata *); 1288 struct qib_devdata *qib_init_iba7322_funcs(struct pci_dev *, 1289 const struct pci_device_id *); 1290 struct qib_devdata *qib_init_iba7220_funcs(struct pci_dev *, 1291 const struct pci_device_id *); 1292 struct qib_devdata *qib_init_iba6120_funcs(struct pci_dev *, 1293 const struct pci_device_id *); 1294 void qib_free_devdata(struct qib_devdata *); 1295 struct qib_devdata *qib_alloc_devdata(struct pci_dev *pdev, size_t extra); 1296 1297 #define QIB_TWSI_NO_DEV 0xFF 1298 /* Below qib_twsi_ functions must be called with eep_lock held */ 1299 int qib_twsi_reset(struct qib_devdata *dd); 1300 int qib_twsi_blk_rd(struct qib_devdata *dd, int dev, int addr, void *buffer, 1301 int len); 1302 int qib_twsi_blk_wr(struct qib_devdata *dd, int dev, int addr, 1303 const void *buffer, int len); 1304 void qib_get_eeprom_info(struct qib_devdata *); 1305 #define qib_inc_eeprom_err(dd, eidx, incr) 1306 void qib_dump_lookup_output_queue(struct qib_devdata *); 1307 void qib_force_pio_avail_update(struct qib_devdata *); 1308 void qib_clear_symerror_on_linkup(unsigned long opaque); 1309 1310 /* 1311 * Set LED override, only the two LSBs have "public" meaning, but 1312 * any non-zero value substitutes them for the Link and LinkTrain 1313 * LED states. 1314 */ 1315 #define QIB_LED_PHYS 1 /* Physical (linktraining) GREEN LED */ 1316 #define QIB_LED_LOG 2 /* Logical (link) YELLOW LED */ 1317 void qib_set_led_override(struct qib_pportdata *ppd, unsigned int val); 1318 1319 /* send dma routines */ 1320 int qib_setup_sdma(struct qib_pportdata *); 1321 void qib_teardown_sdma(struct qib_pportdata *); 1322 void __qib_sdma_intr(struct qib_pportdata *); 1323 void qib_sdma_intr(struct qib_pportdata *); 1324 void qib_user_sdma_send_desc(struct qib_pportdata *dd, 1325 struct list_head *pktlist); 1326 int qib_sdma_verbs_send(struct qib_pportdata *, struct rvt_sge_state *, 1327 u32, struct qib_verbs_txreq *); 1328 /* ppd->sdma_lock should be locked before calling this. */ 1329 int qib_sdma_make_progress(struct qib_pportdata *dd); 1330 1331 static inline int qib_sdma_empty(const struct qib_pportdata *ppd) 1332 { 1333 return ppd->sdma_descq_added == ppd->sdma_descq_removed; 1334 } 1335 1336 /* must be called under qib_sdma_lock */ 1337 static inline u16 qib_sdma_descq_freecnt(const struct qib_pportdata *ppd) 1338 { 1339 return ppd->sdma_descq_cnt - 1340 (ppd->sdma_descq_added - ppd->sdma_descq_removed) - 1; 1341 } 1342 1343 static inline int __qib_sdma_running(struct qib_pportdata *ppd) 1344 { 1345 return ppd->sdma_state.current_state == qib_sdma_state_s99_running; 1346 } 1347 int qib_sdma_running(struct qib_pportdata *); 1348 void dump_sdma_state(struct qib_pportdata *ppd); 1349 void __qib_sdma_process_event(struct qib_pportdata *, enum qib_sdma_events); 1350 void qib_sdma_process_event(struct qib_pportdata *, enum qib_sdma_events); 1351 1352 /* 1353 * number of words used for protocol header if not set by qib_userinit(); 1354 */ 1355 #define QIB_DFLT_RCVHDRSIZE 9 1356 1357 /* 1358 * We need to be able to handle an IB header of at least 24 dwords. 1359 * We need the rcvhdrq large enough to handle largest IB header, but 1360 * still have room for a 2KB MTU standard IB packet. 1361 * Additionally, some processor/memory controller combinations 1362 * benefit quite strongly from having the DMA'ed data be cacheline 1363 * aligned and a cacheline multiple, so we set the size to 32 dwords 1364 * (2 64-byte primary cachelines for pretty much all processors of 1365 * interest). The alignment hurts nothing, other than using somewhat 1366 * more memory. 1367 */ 1368 #define QIB_RCVHDR_ENTSIZE 32 1369 1370 int qib_get_user_pages(unsigned long, size_t, struct page **); 1371 void qib_release_user_pages(struct page **, size_t); 1372 int qib_eeprom_read(struct qib_devdata *, u8, void *, int); 1373 int qib_eeprom_write(struct qib_devdata *, u8, const void *, int); 1374 u32 __iomem *qib_getsendbuf_range(struct qib_devdata *, u32 *, u32, u32); 1375 void qib_sendbuf_done(struct qib_devdata *, unsigned); 1376 1377 static inline void qib_clear_rcvhdrtail(const struct qib_ctxtdata *rcd) 1378 { 1379 *((u64 *) rcd->rcvhdrtail_kvaddr) = 0ULL; 1380 } 1381 1382 static inline u32 qib_get_rcvhdrtail(const struct qib_ctxtdata *rcd) 1383 { 1384 /* 1385 * volatile because it's a DMA target from the chip, routine is 1386 * inlined, and don't want register caching or reordering. 1387 */ 1388 return (u32) le64_to_cpu( 1389 *((volatile __le64 *)rcd->rcvhdrtail_kvaddr)); /* DMA'ed */ 1390 } 1391 1392 static inline u32 qib_get_hdrqtail(const struct qib_ctxtdata *rcd) 1393 { 1394 const struct qib_devdata *dd = rcd->dd; 1395 u32 hdrqtail; 1396 1397 if (dd->flags & QIB_NODMA_RTAIL) { 1398 __le32 *rhf_addr; 1399 u32 seq; 1400 1401 rhf_addr = (__le32 *) rcd->rcvhdrq + 1402 rcd->head + dd->rhf_offset; 1403 seq = qib_hdrget_seq(rhf_addr); 1404 hdrqtail = rcd->head; 1405 if (seq == rcd->seq_cnt) 1406 hdrqtail++; 1407 } else 1408 hdrqtail = qib_get_rcvhdrtail(rcd); 1409 1410 return hdrqtail; 1411 } 1412 1413 /* 1414 * sysfs interface. 1415 */ 1416 1417 extern const char ib_qib_version[]; 1418 1419 int qib_device_create(struct qib_devdata *); 1420 void qib_device_remove(struct qib_devdata *); 1421 1422 int qib_create_port_files(struct ib_device *ibdev, u8 port_num, 1423 struct kobject *kobj); 1424 int qib_verbs_register_sysfs(struct qib_devdata *); 1425 void qib_verbs_unregister_sysfs(struct qib_devdata *); 1426 /* Hook for sysfs read of QSFP */ 1427 extern int qib_qsfp_dump(struct qib_pportdata *ppd, char *buf, int len); 1428 1429 int __init qib_init_qibfs(void); 1430 int __exit qib_exit_qibfs(void); 1431 1432 int qibfs_add(struct qib_devdata *); 1433 int qibfs_remove(struct qib_devdata *); 1434 1435 int qib_pcie_init(struct pci_dev *, const struct pci_device_id *); 1436 int qib_pcie_ddinit(struct qib_devdata *, struct pci_dev *, 1437 const struct pci_device_id *); 1438 void qib_pcie_ddcleanup(struct qib_devdata *); 1439 int qib_pcie_params(struct qib_devdata *, u32, u32 *, struct qib_msix_entry *); 1440 int qib_reinit_intr(struct qib_devdata *); 1441 void qib_enable_intx(struct pci_dev *); 1442 void qib_nomsi(struct qib_devdata *); 1443 void qib_nomsix(struct qib_devdata *); 1444 void qib_pcie_getcmd(struct qib_devdata *, u16 *, u8 *, u8 *); 1445 void qib_pcie_reenable(struct qib_devdata *, u16, u8, u8); 1446 /* interrupts for device */ 1447 u64 qib_int_counter(struct qib_devdata *); 1448 /* interrupt for all devices */ 1449 u64 qib_sps_ints(void); 1450 1451 /* 1452 * dma_addr wrappers - all 0's invalid for hw 1453 */ 1454 dma_addr_t qib_map_page(struct pci_dev *, struct page *, unsigned long, 1455 size_t, int); 1456 const char *qib_get_unit_name(int unit); 1457 const char *qib_get_card_name(struct rvt_dev_info *rdi); 1458 struct pci_dev *qib_get_pci_dev(struct rvt_dev_info *rdi); 1459 1460 /* 1461 * Flush write combining store buffers (if present) and perform a write 1462 * barrier. 1463 */ 1464 static inline void qib_flush_wc(void) 1465 { 1466 #if defined(CONFIG_X86_64) 1467 asm volatile("sfence" : : : "memory"); 1468 #else 1469 wmb(); /* no reorder around wc flush */ 1470 #endif 1471 } 1472 1473 /* global module parameter variables */ 1474 extern unsigned qib_ibmtu; 1475 extern ushort qib_cfgctxts; 1476 extern ushort qib_num_cfg_vls; 1477 extern ushort qib_mini_init; /* If set, do few (ideally 0) writes to chip */ 1478 extern unsigned qib_n_krcv_queues; 1479 extern unsigned qib_sdma_fetch_arb; 1480 extern unsigned qib_compat_ddr_negotiate; 1481 extern int qib_special_trigger; 1482 extern unsigned qib_numa_aware; 1483 1484 extern struct mutex qib_mutex; 1485 1486 /* Number of seconds before our card status check... */ 1487 #define STATUS_TIMEOUT 60 1488 1489 #define QIB_DRV_NAME "ib_qib" 1490 #define QIB_USER_MINOR_BASE 0 1491 #define QIB_TRACE_MINOR 127 1492 #define QIB_DIAGPKT_MINOR 128 1493 #define QIB_DIAG_MINOR_BASE 129 1494 #define QIB_NMINORS 255 1495 1496 #define PCI_VENDOR_ID_PATHSCALE 0x1fc1 1497 #define PCI_VENDOR_ID_QLOGIC 0x1077 1498 #define PCI_DEVICE_ID_QLOGIC_IB_6120 0x10 1499 #define PCI_DEVICE_ID_QLOGIC_IB_7220 0x7220 1500 #define PCI_DEVICE_ID_QLOGIC_IB_7322 0x7322 1501 1502 /* 1503 * qib_early_err is used (only!) to print early errors before devdata is 1504 * allocated, or when dd->pcidev may not be valid, and at the tail end of 1505 * cleanup when devdata may have been freed, etc. qib_dev_porterr is 1506 * the same as qib_dev_err, but is used when the message really needs 1507 * the IB port# to be definitive as to what's happening.. 1508 * All of these go to the trace log, and the trace log entry is done 1509 * first to avoid possible serial port delays from printk. 1510 */ 1511 #define qib_early_err(dev, fmt, ...) \ 1512 dev_err(dev, fmt, ##__VA_ARGS__) 1513 1514 #define qib_dev_err(dd, fmt, ...) \ 1515 dev_err(&(dd)->pcidev->dev, "%s: " fmt, \ 1516 qib_get_unit_name((dd)->unit), ##__VA_ARGS__) 1517 1518 #define qib_dev_warn(dd, fmt, ...) \ 1519 dev_warn(&(dd)->pcidev->dev, "%s: " fmt, \ 1520 qib_get_unit_name((dd)->unit), ##__VA_ARGS__) 1521 1522 #define qib_dev_porterr(dd, port, fmt, ...) \ 1523 dev_err(&(dd)->pcidev->dev, "%s: IB%u:%u " fmt, \ 1524 qib_get_unit_name((dd)->unit), (dd)->unit, (port), \ 1525 ##__VA_ARGS__) 1526 1527 #define qib_devinfo(pcidev, fmt, ...) \ 1528 dev_info(&(pcidev)->dev, fmt, ##__VA_ARGS__) 1529 1530 /* 1531 * this is used for formatting hw error messages... 1532 */ 1533 struct qib_hwerror_msgs { 1534 u64 mask; 1535 const char *msg; 1536 size_t sz; 1537 }; 1538 1539 #define QLOGIC_IB_HWE_MSG(a, b) { .mask = a, .msg = b } 1540 1541 /* in qib_intr.c... */ 1542 void qib_format_hwerrors(u64 hwerrs, 1543 const struct qib_hwerror_msgs *hwerrmsgs, 1544 size_t nhwerrmsgs, char *msg, size_t lmsg); 1545 #endif /* _QIB_KERNEL_H */ 1546