1 /* 2 * Copyright (c) 2004 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005 Cisco Systems. All rights reserved. 4 * Copyright (c) 2005 Mellanox Technologies. All rights reserved. 5 * Copyright (c) 2004 Voltaire, Inc. All rights reserved. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * OpenIB.org BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or 14 * without modification, are permitted provided that the following 15 * conditions are met: 16 * 17 * - Redistributions of source code must retain the above 18 * copyright notice, this list of conditions and the following 19 * disclaimer. 20 * 21 * - Redistributions in binary form must reproduce the above 22 * copyright notice, this list of conditions and the following 23 * disclaimer in the documentation and/or other materials 24 * provided with the distribution. 25 * 26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 33 * SOFTWARE. 34 * 35 * $Id: mthca_qp.c 1355 2004-12-17 15:23:43Z roland $ 36 */ 37 38 #include <linux/string.h> 39 #include <linux/slab.h> 40 #include <linux/sched.h> 41 42 #include <asm/io.h> 43 44 #include <rdma/ib_verbs.h> 45 #include <rdma/ib_cache.h> 46 #include <rdma/ib_pack.h> 47 48 #include "mthca_dev.h" 49 #include "mthca_cmd.h" 50 #include "mthca_memfree.h" 51 #include "mthca_wqe.h" 52 53 enum { 54 MTHCA_MAX_DIRECT_QP_SIZE = 4 * PAGE_SIZE, 55 MTHCA_ACK_REQ_FREQ = 10, 56 MTHCA_FLIGHT_LIMIT = 9, 57 MTHCA_UD_HEADER_SIZE = 72, /* largest UD header possible */ 58 MTHCA_INLINE_HEADER_SIZE = 4, /* data segment overhead for inline */ 59 MTHCA_INLINE_CHUNK_SIZE = 16 /* inline data segment chunk */ 60 }; 61 62 enum { 63 MTHCA_QP_STATE_RST = 0, 64 MTHCA_QP_STATE_INIT = 1, 65 MTHCA_QP_STATE_RTR = 2, 66 MTHCA_QP_STATE_RTS = 3, 67 MTHCA_QP_STATE_SQE = 4, 68 MTHCA_QP_STATE_SQD = 5, 69 MTHCA_QP_STATE_ERR = 6, 70 MTHCA_QP_STATE_DRAINING = 7 71 }; 72 73 enum { 74 MTHCA_QP_ST_RC = 0x0, 75 MTHCA_QP_ST_UC = 0x1, 76 MTHCA_QP_ST_RD = 0x2, 77 MTHCA_QP_ST_UD = 0x3, 78 MTHCA_QP_ST_MLX = 0x7 79 }; 80 81 enum { 82 MTHCA_QP_PM_MIGRATED = 0x3, 83 MTHCA_QP_PM_ARMED = 0x0, 84 MTHCA_QP_PM_REARM = 0x1 85 }; 86 87 enum { 88 /* qp_context flags */ 89 MTHCA_QP_BIT_DE = 1 << 8, 90 /* params1 */ 91 MTHCA_QP_BIT_SRE = 1 << 15, 92 MTHCA_QP_BIT_SWE = 1 << 14, 93 MTHCA_QP_BIT_SAE = 1 << 13, 94 MTHCA_QP_BIT_SIC = 1 << 4, 95 MTHCA_QP_BIT_SSC = 1 << 3, 96 /* params2 */ 97 MTHCA_QP_BIT_RRE = 1 << 15, 98 MTHCA_QP_BIT_RWE = 1 << 14, 99 MTHCA_QP_BIT_RAE = 1 << 13, 100 MTHCA_QP_BIT_RIC = 1 << 4, 101 MTHCA_QP_BIT_RSC = 1 << 3 102 }; 103 104 enum { 105 MTHCA_SEND_DOORBELL_FENCE = 1 << 5 106 }; 107 108 struct mthca_qp_path { 109 __be32 port_pkey; 110 u8 rnr_retry; 111 u8 g_mylmc; 112 __be16 rlid; 113 u8 ackto; 114 u8 mgid_index; 115 u8 static_rate; 116 u8 hop_limit; 117 __be32 sl_tclass_flowlabel; 118 u8 rgid[16]; 119 } __attribute__((packed)); 120 121 struct mthca_qp_context { 122 __be32 flags; 123 __be32 tavor_sched_queue; /* Reserved on Arbel */ 124 u8 mtu_msgmax; 125 u8 rq_size_stride; /* Reserved on Tavor */ 126 u8 sq_size_stride; /* Reserved on Tavor */ 127 u8 rlkey_arbel_sched_queue; /* Reserved on Tavor */ 128 __be32 usr_page; 129 __be32 local_qpn; 130 __be32 remote_qpn; 131 u32 reserved1[2]; 132 struct mthca_qp_path pri_path; 133 struct mthca_qp_path alt_path; 134 __be32 rdd; 135 __be32 pd; 136 __be32 wqe_base; 137 __be32 wqe_lkey; 138 __be32 params1; 139 __be32 reserved2; 140 __be32 next_send_psn; 141 __be32 cqn_snd; 142 __be32 snd_wqe_base_l; /* Next send WQE on Tavor */ 143 __be32 snd_db_index; /* (debugging only entries) */ 144 __be32 last_acked_psn; 145 __be32 ssn; 146 __be32 params2; 147 __be32 rnr_nextrecvpsn; 148 __be32 ra_buff_indx; 149 __be32 cqn_rcv; 150 __be32 rcv_wqe_base_l; /* Next recv WQE on Tavor */ 151 __be32 rcv_db_index; /* (debugging only entries) */ 152 __be32 qkey; 153 __be32 srqn; 154 __be32 rmsn; 155 __be16 rq_wqe_counter; /* reserved on Tavor */ 156 __be16 sq_wqe_counter; /* reserved on Tavor */ 157 u32 reserved3[18]; 158 } __attribute__((packed)); 159 160 struct mthca_qp_param { 161 __be32 opt_param_mask; 162 u32 reserved1; 163 struct mthca_qp_context context; 164 u32 reserved2[62]; 165 } __attribute__((packed)); 166 167 enum { 168 MTHCA_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0, 169 MTHCA_QP_OPTPAR_RRE = 1 << 1, 170 MTHCA_QP_OPTPAR_RAE = 1 << 2, 171 MTHCA_QP_OPTPAR_RWE = 1 << 3, 172 MTHCA_QP_OPTPAR_PKEY_INDEX = 1 << 4, 173 MTHCA_QP_OPTPAR_Q_KEY = 1 << 5, 174 MTHCA_QP_OPTPAR_RNR_TIMEOUT = 1 << 6, 175 MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7, 176 MTHCA_QP_OPTPAR_SRA_MAX = 1 << 8, 177 MTHCA_QP_OPTPAR_RRA_MAX = 1 << 9, 178 MTHCA_QP_OPTPAR_PM_STATE = 1 << 10, 179 MTHCA_QP_OPTPAR_PORT_NUM = 1 << 11, 180 MTHCA_QP_OPTPAR_RETRY_COUNT = 1 << 12, 181 MTHCA_QP_OPTPAR_ALT_RNR_RETRY = 1 << 13, 182 MTHCA_QP_OPTPAR_ACK_TIMEOUT = 1 << 14, 183 MTHCA_QP_OPTPAR_RNR_RETRY = 1 << 15, 184 MTHCA_QP_OPTPAR_SCHED_QUEUE = 1 << 16 185 }; 186 187 static const u8 mthca_opcode[] = { 188 [IB_WR_SEND] = MTHCA_OPCODE_SEND, 189 [IB_WR_SEND_WITH_IMM] = MTHCA_OPCODE_SEND_IMM, 190 [IB_WR_RDMA_WRITE] = MTHCA_OPCODE_RDMA_WRITE, 191 [IB_WR_RDMA_WRITE_WITH_IMM] = MTHCA_OPCODE_RDMA_WRITE_IMM, 192 [IB_WR_RDMA_READ] = MTHCA_OPCODE_RDMA_READ, 193 [IB_WR_ATOMIC_CMP_AND_SWP] = MTHCA_OPCODE_ATOMIC_CS, 194 [IB_WR_ATOMIC_FETCH_AND_ADD] = MTHCA_OPCODE_ATOMIC_FA, 195 }; 196 197 static int is_sqp(struct mthca_dev *dev, struct mthca_qp *qp) 198 { 199 return qp->qpn >= dev->qp_table.sqp_start && 200 qp->qpn <= dev->qp_table.sqp_start + 3; 201 } 202 203 static int is_qp0(struct mthca_dev *dev, struct mthca_qp *qp) 204 { 205 return qp->qpn >= dev->qp_table.sqp_start && 206 qp->qpn <= dev->qp_table.sqp_start + 1; 207 } 208 209 static void *get_recv_wqe(struct mthca_qp *qp, int n) 210 { 211 if (qp->is_direct) 212 return qp->queue.direct.buf + (n << qp->rq.wqe_shift); 213 else 214 return qp->queue.page_list[(n << qp->rq.wqe_shift) >> PAGE_SHIFT].buf + 215 ((n << qp->rq.wqe_shift) & (PAGE_SIZE - 1)); 216 } 217 218 static void *get_send_wqe(struct mthca_qp *qp, int n) 219 { 220 if (qp->is_direct) 221 return qp->queue.direct.buf + qp->send_wqe_offset + 222 (n << qp->sq.wqe_shift); 223 else 224 return qp->queue.page_list[(qp->send_wqe_offset + 225 (n << qp->sq.wqe_shift)) >> 226 PAGE_SHIFT].buf + 227 ((qp->send_wqe_offset + (n << qp->sq.wqe_shift)) & 228 (PAGE_SIZE - 1)); 229 } 230 231 static void mthca_wq_reset(struct mthca_wq *wq) 232 { 233 wq->next_ind = 0; 234 wq->last_comp = wq->max - 1; 235 wq->head = 0; 236 wq->tail = 0; 237 } 238 239 void mthca_qp_event(struct mthca_dev *dev, u32 qpn, 240 enum ib_event_type event_type) 241 { 242 struct mthca_qp *qp; 243 struct ib_event event; 244 245 spin_lock(&dev->qp_table.lock); 246 qp = mthca_array_get(&dev->qp_table.qp, qpn & (dev->limits.num_qps - 1)); 247 if (qp) 248 ++qp->refcount; 249 spin_unlock(&dev->qp_table.lock); 250 251 if (!qp) { 252 mthca_warn(dev, "Async event for bogus QP %08x\n", qpn); 253 return; 254 } 255 256 if (event_type == IB_EVENT_PATH_MIG) 257 qp->port = qp->alt_port; 258 259 event.device = &dev->ib_dev; 260 event.event = event_type; 261 event.element.qp = &qp->ibqp; 262 if (qp->ibqp.event_handler) 263 qp->ibqp.event_handler(&event, qp->ibqp.qp_context); 264 265 spin_lock(&dev->qp_table.lock); 266 if (!--qp->refcount) 267 wake_up(&qp->wait); 268 spin_unlock(&dev->qp_table.lock); 269 } 270 271 static int to_mthca_state(enum ib_qp_state ib_state) 272 { 273 switch (ib_state) { 274 case IB_QPS_RESET: return MTHCA_QP_STATE_RST; 275 case IB_QPS_INIT: return MTHCA_QP_STATE_INIT; 276 case IB_QPS_RTR: return MTHCA_QP_STATE_RTR; 277 case IB_QPS_RTS: return MTHCA_QP_STATE_RTS; 278 case IB_QPS_SQD: return MTHCA_QP_STATE_SQD; 279 case IB_QPS_SQE: return MTHCA_QP_STATE_SQE; 280 case IB_QPS_ERR: return MTHCA_QP_STATE_ERR; 281 default: return -1; 282 } 283 } 284 285 enum { RC, UC, UD, RD, RDEE, MLX, NUM_TRANS }; 286 287 static int to_mthca_st(int transport) 288 { 289 switch (transport) { 290 case RC: return MTHCA_QP_ST_RC; 291 case UC: return MTHCA_QP_ST_UC; 292 case UD: return MTHCA_QP_ST_UD; 293 case RD: return MTHCA_QP_ST_RD; 294 case MLX: return MTHCA_QP_ST_MLX; 295 default: return -1; 296 } 297 } 298 299 static void store_attrs(struct mthca_sqp *sqp, const struct ib_qp_attr *attr, 300 int attr_mask) 301 { 302 if (attr_mask & IB_QP_PKEY_INDEX) 303 sqp->pkey_index = attr->pkey_index; 304 if (attr_mask & IB_QP_QKEY) 305 sqp->qkey = attr->qkey; 306 if (attr_mask & IB_QP_SQ_PSN) 307 sqp->send_psn = attr->sq_psn; 308 } 309 310 static void init_port(struct mthca_dev *dev, int port) 311 { 312 int err; 313 u8 status; 314 struct mthca_init_ib_param param; 315 316 memset(¶m, 0, sizeof param); 317 318 param.port_width = dev->limits.port_width_cap; 319 param.vl_cap = dev->limits.vl_cap; 320 param.mtu_cap = dev->limits.mtu_cap; 321 param.gid_cap = dev->limits.gid_table_len; 322 param.pkey_cap = dev->limits.pkey_table_len; 323 324 err = mthca_INIT_IB(dev, ¶m, port, &status); 325 if (err) 326 mthca_warn(dev, "INIT_IB failed, return code %d.\n", err); 327 if (status) 328 mthca_warn(dev, "INIT_IB returned status %02x.\n", status); 329 } 330 331 static __be32 get_hw_access_flags(struct mthca_qp *qp, const struct ib_qp_attr *attr, 332 int attr_mask) 333 { 334 u8 dest_rd_atomic; 335 u32 access_flags; 336 u32 hw_access_flags = 0; 337 338 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 339 dest_rd_atomic = attr->max_dest_rd_atomic; 340 else 341 dest_rd_atomic = qp->resp_depth; 342 343 if (attr_mask & IB_QP_ACCESS_FLAGS) 344 access_flags = attr->qp_access_flags; 345 else 346 access_flags = qp->atomic_rd_en; 347 348 if (!dest_rd_atomic) 349 access_flags &= IB_ACCESS_REMOTE_WRITE; 350 351 if (access_flags & IB_ACCESS_REMOTE_READ) 352 hw_access_flags |= MTHCA_QP_BIT_RRE; 353 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) 354 hw_access_flags |= MTHCA_QP_BIT_RAE; 355 if (access_flags & IB_ACCESS_REMOTE_WRITE) 356 hw_access_flags |= MTHCA_QP_BIT_RWE; 357 358 return cpu_to_be32(hw_access_flags); 359 } 360 361 static inline enum ib_qp_state to_ib_qp_state(int mthca_state) 362 { 363 switch (mthca_state) { 364 case MTHCA_QP_STATE_RST: return IB_QPS_RESET; 365 case MTHCA_QP_STATE_INIT: return IB_QPS_INIT; 366 case MTHCA_QP_STATE_RTR: return IB_QPS_RTR; 367 case MTHCA_QP_STATE_RTS: return IB_QPS_RTS; 368 case MTHCA_QP_STATE_DRAINING: 369 case MTHCA_QP_STATE_SQD: return IB_QPS_SQD; 370 case MTHCA_QP_STATE_SQE: return IB_QPS_SQE; 371 case MTHCA_QP_STATE_ERR: return IB_QPS_ERR; 372 default: return -1; 373 } 374 } 375 376 static inline enum ib_mig_state to_ib_mig_state(int mthca_mig_state) 377 { 378 switch (mthca_mig_state) { 379 case 0: return IB_MIG_ARMED; 380 case 1: return IB_MIG_REARM; 381 case 3: return IB_MIG_MIGRATED; 382 default: return -1; 383 } 384 } 385 386 static int to_ib_qp_access_flags(int mthca_flags) 387 { 388 int ib_flags = 0; 389 390 if (mthca_flags & MTHCA_QP_BIT_RRE) 391 ib_flags |= IB_ACCESS_REMOTE_READ; 392 if (mthca_flags & MTHCA_QP_BIT_RWE) 393 ib_flags |= IB_ACCESS_REMOTE_WRITE; 394 if (mthca_flags & MTHCA_QP_BIT_RAE) 395 ib_flags |= IB_ACCESS_REMOTE_ATOMIC; 396 397 return ib_flags; 398 } 399 400 static void to_ib_ah_attr(struct mthca_dev *dev, struct ib_ah_attr *ib_ah_attr, 401 struct mthca_qp_path *path) 402 { 403 memset(ib_ah_attr, 0, sizeof *ib_ah_attr); 404 ib_ah_attr->port_num = (be32_to_cpu(path->port_pkey) >> 24) & 0x3; 405 406 if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->limits.num_ports) 407 return; 408 409 ib_ah_attr->dlid = be16_to_cpu(path->rlid); 410 ib_ah_attr->sl = be32_to_cpu(path->sl_tclass_flowlabel) >> 28; 411 ib_ah_attr->src_path_bits = path->g_mylmc & 0x7f; 412 ib_ah_attr->static_rate = mthca_rate_to_ib(dev, 413 path->static_rate & 0xf, 414 ib_ah_attr->port_num); 415 ib_ah_attr->ah_flags = (path->g_mylmc & (1 << 7)) ? IB_AH_GRH : 0; 416 if (ib_ah_attr->ah_flags) { 417 ib_ah_attr->grh.sgid_index = path->mgid_index & (dev->limits.gid_table_len - 1); 418 ib_ah_attr->grh.hop_limit = path->hop_limit; 419 ib_ah_attr->grh.traffic_class = 420 (be32_to_cpu(path->sl_tclass_flowlabel) >> 20) & 0xff; 421 ib_ah_attr->grh.flow_label = 422 be32_to_cpu(path->sl_tclass_flowlabel) & 0xfffff; 423 memcpy(ib_ah_attr->grh.dgid.raw, 424 path->rgid, sizeof ib_ah_attr->grh.dgid.raw); 425 } 426 } 427 428 int mthca_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, 429 struct ib_qp_init_attr *qp_init_attr) 430 { 431 struct mthca_dev *dev = to_mdev(ibqp->device); 432 struct mthca_qp *qp = to_mqp(ibqp); 433 int err = 0; 434 struct mthca_mailbox *mailbox = NULL; 435 struct mthca_qp_param *qp_param; 436 struct mthca_qp_context *context; 437 int mthca_state; 438 u8 status; 439 440 if (qp->state == IB_QPS_RESET) { 441 qp_attr->qp_state = IB_QPS_RESET; 442 goto done; 443 } 444 445 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 446 if (IS_ERR(mailbox)) 447 return PTR_ERR(mailbox); 448 449 err = mthca_QUERY_QP(dev, qp->qpn, 0, mailbox, &status); 450 if (err) 451 goto out; 452 if (status) { 453 mthca_warn(dev, "QUERY_QP returned status %02x\n", status); 454 err = -EINVAL; 455 goto out; 456 } 457 458 qp_param = mailbox->buf; 459 context = &qp_param->context; 460 mthca_state = be32_to_cpu(context->flags) >> 28; 461 462 qp_attr->qp_state = to_ib_qp_state(mthca_state); 463 qp_attr->path_mtu = context->mtu_msgmax >> 5; 464 qp_attr->path_mig_state = 465 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3); 466 qp_attr->qkey = be32_to_cpu(context->qkey); 467 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff; 468 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff; 469 qp_attr->dest_qp_num = be32_to_cpu(context->remote_qpn) & 0xffffff; 470 qp_attr->qp_access_flags = 471 to_ib_qp_access_flags(be32_to_cpu(context->params2)); 472 473 if (qp->transport == RC || qp->transport == UC) { 474 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path); 475 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path); 476 qp_attr->alt_pkey_index = 477 be32_to_cpu(context->alt_path.port_pkey) & 0x7f; 478 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num; 479 } 480 481 qp_attr->pkey_index = be32_to_cpu(context->pri_path.port_pkey) & 0x7f; 482 qp_attr->port_num = 483 (be32_to_cpu(context->pri_path.port_pkey) >> 24) & 0x3; 484 485 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */ 486 qp_attr->sq_draining = mthca_state == MTHCA_QP_STATE_DRAINING; 487 488 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7); 489 490 qp_attr->max_dest_rd_atomic = 491 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7); 492 qp_attr->min_rnr_timer = 493 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f; 494 qp_attr->timeout = context->pri_path.ackto >> 3; 495 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7; 496 qp_attr->rnr_retry = context->pri_path.rnr_retry >> 5; 497 qp_attr->alt_timeout = context->alt_path.ackto >> 3; 498 499 done: 500 qp_attr->cur_qp_state = qp_attr->qp_state; 501 qp_attr->cap.max_send_wr = qp->sq.max; 502 qp_attr->cap.max_recv_wr = qp->rq.max; 503 qp_attr->cap.max_send_sge = qp->sq.max_gs; 504 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 505 qp_attr->cap.max_inline_data = qp->max_inline_data; 506 507 qp_init_attr->cap = qp_attr->cap; 508 509 out: 510 mthca_free_mailbox(dev, mailbox); 511 return err; 512 } 513 514 static int mthca_path_set(struct mthca_dev *dev, const struct ib_ah_attr *ah, 515 struct mthca_qp_path *path, u8 port) 516 { 517 path->g_mylmc = ah->src_path_bits & 0x7f; 518 path->rlid = cpu_to_be16(ah->dlid); 519 path->static_rate = mthca_get_rate(dev, ah->static_rate, port); 520 521 if (ah->ah_flags & IB_AH_GRH) { 522 if (ah->grh.sgid_index >= dev->limits.gid_table_len) { 523 mthca_dbg(dev, "sgid_index (%u) too large. max is %d\n", 524 ah->grh.sgid_index, dev->limits.gid_table_len-1); 525 return -1; 526 } 527 528 path->g_mylmc |= 1 << 7; 529 path->mgid_index = ah->grh.sgid_index; 530 path->hop_limit = ah->grh.hop_limit; 531 path->sl_tclass_flowlabel = 532 cpu_to_be32((ah->sl << 28) | 533 (ah->grh.traffic_class << 20) | 534 (ah->grh.flow_label)); 535 memcpy(path->rgid, ah->grh.dgid.raw, 16); 536 } else 537 path->sl_tclass_flowlabel = cpu_to_be32(ah->sl << 28); 538 539 return 0; 540 } 541 542 static int __mthca_modify_qp(struct ib_qp *ibqp, 543 const struct ib_qp_attr *attr, int attr_mask, 544 enum ib_qp_state cur_state, enum ib_qp_state new_state) 545 { 546 struct mthca_dev *dev = to_mdev(ibqp->device); 547 struct mthca_qp *qp = to_mqp(ibqp); 548 struct mthca_mailbox *mailbox; 549 struct mthca_qp_param *qp_param; 550 struct mthca_qp_context *qp_context; 551 u32 sqd_event = 0; 552 u8 status; 553 int err = -EINVAL; 554 555 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 556 if (IS_ERR(mailbox)) { 557 err = PTR_ERR(mailbox); 558 goto out; 559 } 560 qp_param = mailbox->buf; 561 qp_context = &qp_param->context; 562 memset(qp_param, 0, sizeof *qp_param); 563 564 qp_context->flags = cpu_to_be32((to_mthca_state(new_state) << 28) | 565 (to_mthca_st(qp->transport) << 16)); 566 qp_context->flags |= cpu_to_be32(MTHCA_QP_BIT_DE); 567 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) 568 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11); 569 else { 570 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PM_STATE); 571 switch (attr->path_mig_state) { 572 case IB_MIG_MIGRATED: 573 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11); 574 break; 575 case IB_MIG_REARM: 576 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_REARM << 11); 577 break; 578 case IB_MIG_ARMED: 579 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_ARMED << 11); 580 break; 581 } 582 } 583 584 /* leave tavor_sched_queue as 0 */ 585 586 if (qp->transport == MLX || qp->transport == UD) 587 qp_context->mtu_msgmax = (IB_MTU_2048 << 5) | 11; 588 else if (attr_mask & IB_QP_PATH_MTU) { 589 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_2048) { 590 mthca_dbg(dev, "path MTU (%u) is invalid\n", 591 attr->path_mtu); 592 goto out_mailbox; 593 } 594 qp_context->mtu_msgmax = (attr->path_mtu << 5) | 31; 595 } 596 597 if (mthca_is_memfree(dev)) { 598 if (qp->rq.max) 599 qp_context->rq_size_stride = ilog2(qp->rq.max) << 3; 600 qp_context->rq_size_stride |= qp->rq.wqe_shift - 4; 601 602 if (qp->sq.max) 603 qp_context->sq_size_stride = ilog2(qp->sq.max) << 3; 604 qp_context->sq_size_stride |= qp->sq.wqe_shift - 4; 605 } 606 607 /* leave arbel_sched_queue as 0 */ 608 609 if (qp->ibqp.uobject) 610 qp_context->usr_page = 611 cpu_to_be32(to_mucontext(qp->ibqp.uobject->context)->uar.index); 612 else 613 qp_context->usr_page = cpu_to_be32(dev->driver_uar.index); 614 qp_context->local_qpn = cpu_to_be32(qp->qpn); 615 if (attr_mask & IB_QP_DEST_QPN) { 616 qp_context->remote_qpn = cpu_to_be32(attr->dest_qp_num); 617 } 618 619 if (qp->transport == MLX) 620 qp_context->pri_path.port_pkey |= 621 cpu_to_be32(qp->port << 24); 622 else { 623 if (attr_mask & IB_QP_PORT) { 624 qp_context->pri_path.port_pkey |= 625 cpu_to_be32(attr->port_num << 24); 626 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PORT_NUM); 627 } 628 } 629 630 if (attr_mask & IB_QP_PKEY_INDEX) { 631 qp_context->pri_path.port_pkey |= 632 cpu_to_be32(attr->pkey_index); 633 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PKEY_INDEX); 634 } 635 636 if (attr_mask & IB_QP_RNR_RETRY) { 637 qp_context->alt_path.rnr_retry = qp_context->pri_path.rnr_retry = 638 attr->rnr_retry << 5; 639 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_RETRY | 640 MTHCA_QP_OPTPAR_ALT_RNR_RETRY); 641 } 642 643 if (attr_mask & IB_QP_AV) { 644 if (mthca_path_set(dev, &attr->ah_attr, &qp_context->pri_path, 645 attr_mask & IB_QP_PORT ? attr->port_num : qp->port)) 646 goto out_mailbox; 647 648 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH); 649 } 650 651 if (ibqp->qp_type == IB_QPT_RC && 652 cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 653 u8 sched_queue = ibqp->uobject ? 0x2 : 0x1; 654 655 if (mthca_is_memfree(dev)) 656 qp_context->rlkey_arbel_sched_queue |= sched_queue; 657 else 658 qp_context->tavor_sched_queue |= cpu_to_be32(sched_queue); 659 660 qp_param->opt_param_mask |= 661 cpu_to_be32(MTHCA_QP_OPTPAR_SCHED_QUEUE); 662 } 663 664 if (attr_mask & IB_QP_TIMEOUT) { 665 qp_context->pri_path.ackto = attr->timeout << 3; 666 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ACK_TIMEOUT); 667 } 668 669 if (attr_mask & IB_QP_ALT_PATH) { 670 if (attr->alt_pkey_index >= dev->limits.pkey_table_len) { 671 mthca_dbg(dev, "Alternate P_Key index (%u) too large. max is %d\n", 672 attr->alt_pkey_index, dev->limits.pkey_table_len-1); 673 goto out_mailbox; 674 } 675 676 if (attr->alt_port_num == 0 || attr->alt_port_num > dev->limits.num_ports) { 677 mthca_dbg(dev, "Alternate port number (%u) is invalid\n", 678 attr->alt_port_num); 679 goto out_mailbox; 680 } 681 682 if (mthca_path_set(dev, &attr->alt_ah_attr, &qp_context->alt_path, 683 attr->alt_ah_attr.port_num)) 684 goto out_mailbox; 685 686 qp_context->alt_path.port_pkey |= cpu_to_be32(attr->alt_pkey_index | 687 attr->alt_port_num << 24); 688 qp_context->alt_path.ackto = attr->alt_timeout << 3; 689 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ALT_ADDR_PATH); 690 } 691 692 /* leave rdd as 0 */ 693 qp_context->pd = cpu_to_be32(to_mpd(ibqp->pd)->pd_num); 694 /* leave wqe_base as 0 (we always create an MR based at 0 for WQs) */ 695 qp_context->wqe_lkey = cpu_to_be32(qp->mr.ibmr.lkey); 696 qp_context->params1 = cpu_to_be32((MTHCA_ACK_REQ_FREQ << 28) | 697 (MTHCA_FLIGHT_LIMIT << 24) | 698 MTHCA_QP_BIT_SWE); 699 if (qp->sq_policy == IB_SIGNAL_ALL_WR) 700 qp_context->params1 |= cpu_to_be32(MTHCA_QP_BIT_SSC); 701 if (attr_mask & IB_QP_RETRY_CNT) { 702 qp_context->params1 |= cpu_to_be32(attr->retry_cnt << 16); 703 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RETRY_COUNT); 704 } 705 706 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 707 if (attr->max_rd_atomic) { 708 qp_context->params1 |= 709 cpu_to_be32(MTHCA_QP_BIT_SRE | 710 MTHCA_QP_BIT_SAE); 711 qp_context->params1 |= 712 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21); 713 } 714 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_SRA_MAX); 715 } 716 717 if (attr_mask & IB_QP_SQ_PSN) 718 qp_context->next_send_psn = cpu_to_be32(attr->sq_psn); 719 qp_context->cqn_snd = cpu_to_be32(to_mcq(ibqp->send_cq)->cqn); 720 721 if (mthca_is_memfree(dev)) { 722 qp_context->snd_wqe_base_l = cpu_to_be32(qp->send_wqe_offset); 723 qp_context->snd_db_index = cpu_to_be32(qp->sq.db_index); 724 } 725 726 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 727 if (attr->max_dest_rd_atomic) 728 qp_context->params2 |= 729 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21); 730 731 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RRA_MAX); 732 } 733 734 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) { 735 qp_context->params2 |= get_hw_access_flags(qp, attr, attr_mask); 736 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE | 737 MTHCA_QP_OPTPAR_RRE | 738 MTHCA_QP_OPTPAR_RAE); 739 } 740 741 qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RSC); 742 743 if (ibqp->srq) 744 qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RIC); 745 746 if (attr_mask & IB_QP_MIN_RNR_TIMER) { 747 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24); 748 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_TIMEOUT); 749 } 750 if (attr_mask & IB_QP_RQ_PSN) 751 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn); 752 753 qp_context->ra_buff_indx = 754 cpu_to_be32(dev->qp_table.rdb_base + 755 ((qp->qpn & (dev->limits.num_qps - 1)) * MTHCA_RDB_ENTRY_SIZE << 756 dev->qp_table.rdb_shift)); 757 758 qp_context->cqn_rcv = cpu_to_be32(to_mcq(ibqp->recv_cq)->cqn); 759 760 if (mthca_is_memfree(dev)) 761 qp_context->rcv_db_index = cpu_to_be32(qp->rq.db_index); 762 763 if (attr_mask & IB_QP_QKEY) { 764 qp_context->qkey = cpu_to_be32(attr->qkey); 765 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_Q_KEY); 766 } 767 768 if (ibqp->srq) 769 qp_context->srqn = cpu_to_be32(1 << 24 | 770 to_msrq(ibqp->srq)->srqn); 771 772 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD && 773 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && 774 attr->en_sqd_async_notify) 775 sqd_event = 1 << 31; 776 777 err = mthca_MODIFY_QP(dev, cur_state, new_state, qp->qpn, 0, 778 mailbox, sqd_event, &status); 779 if (err) 780 goto out_mailbox; 781 if (status) { 782 mthca_warn(dev, "modify QP %d->%d returned status %02x.\n", 783 cur_state, new_state, status); 784 err = -EINVAL; 785 goto out_mailbox; 786 } 787 788 qp->state = new_state; 789 if (attr_mask & IB_QP_ACCESS_FLAGS) 790 qp->atomic_rd_en = attr->qp_access_flags; 791 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 792 qp->resp_depth = attr->max_dest_rd_atomic; 793 if (attr_mask & IB_QP_PORT) 794 qp->port = attr->port_num; 795 if (attr_mask & IB_QP_ALT_PATH) 796 qp->alt_port = attr->alt_port_num; 797 798 if (is_sqp(dev, qp)) 799 store_attrs(to_msqp(qp), attr, attr_mask); 800 801 /* 802 * If we moved QP0 to RTR, bring the IB link up; if we moved 803 * QP0 to RESET or ERROR, bring the link back down. 804 */ 805 if (is_qp0(dev, qp)) { 806 if (cur_state != IB_QPS_RTR && 807 new_state == IB_QPS_RTR) 808 init_port(dev, qp->port); 809 810 if (cur_state != IB_QPS_RESET && 811 cur_state != IB_QPS_ERR && 812 (new_state == IB_QPS_RESET || 813 new_state == IB_QPS_ERR)) 814 mthca_CLOSE_IB(dev, qp->port, &status); 815 } 816 817 /* 818 * If we moved a kernel QP to RESET, clean up all old CQ 819 * entries and reinitialize the QP. 820 */ 821 if (new_state == IB_QPS_RESET && !qp->ibqp.uobject) { 822 mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq), qp->qpn, 823 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL); 824 if (qp->ibqp.send_cq != qp->ibqp.recv_cq) 825 mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq), qp->qpn, NULL); 826 827 mthca_wq_reset(&qp->sq); 828 qp->sq.last = get_send_wqe(qp, qp->sq.max - 1); 829 830 mthca_wq_reset(&qp->rq); 831 qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1); 832 833 if (mthca_is_memfree(dev)) { 834 *qp->sq.db = 0; 835 *qp->rq.db = 0; 836 } 837 } 838 839 out_mailbox: 840 mthca_free_mailbox(dev, mailbox); 841 out: 842 return err; 843 } 844 845 static const struct ib_qp_attr dummy_init_attr = { .port_num = 1 }; 846 static const int dummy_init_attr_mask[] = { 847 [IB_QPT_UD] = (IB_QP_PKEY_INDEX | 848 IB_QP_PORT | 849 IB_QP_QKEY), 850 [IB_QPT_UC] = (IB_QP_PKEY_INDEX | 851 IB_QP_PORT | 852 IB_QP_ACCESS_FLAGS), 853 [IB_QPT_RC] = (IB_QP_PKEY_INDEX | 854 IB_QP_PORT | 855 IB_QP_ACCESS_FLAGS), 856 [IB_QPT_SMI] = (IB_QP_PKEY_INDEX | 857 IB_QP_QKEY), 858 [IB_QPT_GSI] = (IB_QP_PKEY_INDEX | 859 IB_QP_QKEY), 860 }; 861 862 int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask, 863 struct ib_udata *udata) 864 { 865 struct mthca_dev *dev = to_mdev(ibqp->device); 866 struct mthca_qp *qp = to_mqp(ibqp); 867 enum ib_qp_state cur_state, new_state; 868 int err = -EINVAL; 869 870 mutex_lock(&qp->mutex); 871 if (attr_mask & IB_QP_CUR_STATE) { 872 cur_state = attr->cur_qp_state; 873 } else { 874 spin_lock_irq(&qp->sq.lock); 875 spin_lock(&qp->rq.lock); 876 cur_state = qp->state; 877 spin_unlock(&qp->rq.lock); 878 spin_unlock_irq(&qp->sq.lock); 879 } 880 881 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 882 883 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask)) { 884 mthca_dbg(dev, "Bad QP transition (transport %d) " 885 "%d->%d with attr 0x%08x\n", 886 qp->transport, cur_state, new_state, 887 attr_mask); 888 goto out; 889 } 890 891 if ((attr_mask & IB_QP_PKEY_INDEX) && 892 attr->pkey_index >= dev->limits.pkey_table_len) { 893 mthca_dbg(dev, "P_Key index (%u) too large. max is %d\n", 894 attr->pkey_index, dev->limits.pkey_table_len-1); 895 goto out; 896 } 897 898 if ((attr_mask & IB_QP_PORT) && 899 (attr->port_num == 0 || attr->port_num > dev->limits.num_ports)) { 900 mthca_dbg(dev, "Port number (%u) is invalid\n", attr->port_num); 901 goto out; 902 } 903 904 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 905 attr->max_rd_atomic > dev->limits.max_qp_init_rdma) { 906 mthca_dbg(dev, "Max rdma_atomic as initiator %u too large (max is %d)\n", 907 attr->max_rd_atomic, dev->limits.max_qp_init_rdma); 908 goto out; 909 } 910 911 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 912 attr->max_dest_rd_atomic > 1 << dev->qp_table.rdb_shift) { 913 mthca_dbg(dev, "Max rdma_atomic as responder %u too large (max %d)\n", 914 attr->max_dest_rd_atomic, 1 << dev->qp_table.rdb_shift); 915 goto out; 916 } 917 918 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 919 err = 0; 920 goto out; 921 } 922 923 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_ERR) { 924 err = __mthca_modify_qp(ibqp, &dummy_init_attr, 925 dummy_init_attr_mask[ibqp->qp_type], 926 IB_QPS_RESET, IB_QPS_INIT); 927 if (err) 928 goto out; 929 cur_state = IB_QPS_INIT; 930 } 931 932 err = __mthca_modify_qp(ibqp, attr, attr_mask, cur_state, new_state); 933 934 out: 935 mutex_unlock(&qp->mutex); 936 return err; 937 } 938 939 static int mthca_max_data_size(struct mthca_dev *dev, struct mthca_qp *qp, int desc_sz) 940 { 941 /* 942 * Calculate the maximum size of WQE s/g segments, excluding 943 * the next segment and other non-data segments. 944 */ 945 int max_data_size = desc_sz - sizeof (struct mthca_next_seg); 946 947 switch (qp->transport) { 948 case MLX: 949 max_data_size -= 2 * sizeof (struct mthca_data_seg); 950 break; 951 952 case UD: 953 if (mthca_is_memfree(dev)) 954 max_data_size -= sizeof (struct mthca_arbel_ud_seg); 955 else 956 max_data_size -= sizeof (struct mthca_tavor_ud_seg); 957 break; 958 959 default: 960 max_data_size -= sizeof (struct mthca_raddr_seg); 961 break; 962 } 963 964 return max_data_size; 965 } 966 967 static inline int mthca_max_inline_data(struct mthca_pd *pd, int max_data_size) 968 { 969 /* We don't support inline data for kernel QPs (yet). */ 970 return pd->ibpd.uobject ? max_data_size - MTHCA_INLINE_HEADER_SIZE : 0; 971 } 972 973 static void mthca_adjust_qp_caps(struct mthca_dev *dev, 974 struct mthca_pd *pd, 975 struct mthca_qp *qp) 976 { 977 int max_data_size = mthca_max_data_size(dev, qp, 978 min(dev->limits.max_desc_sz, 979 1 << qp->sq.wqe_shift)); 980 981 qp->max_inline_data = mthca_max_inline_data(pd, max_data_size); 982 983 qp->sq.max_gs = min_t(int, dev->limits.max_sg, 984 max_data_size / sizeof (struct mthca_data_seg)); 985 qp->rq.max_gs = min_t(int, dev->limits.max_sg, 986 (min(dev->limits.max_desc_sz, 1 << qp->rq.wqe_shift) - 987 sizeof (struct mthca_next_seg)) / 988 sizeof (struct mthca_data_seg)); 989 } 990 991 /* 992 * Allocate and register buffer for WQEs. qp->rq.max, sq.max, 993 * rq.max_gs and sq.max_gs must all be assigned. 994 * mthca_alloc_wqe_buf will calculate rq.wqe_shift and 995 * sq.wqe_shift (as well as send_wqe_offset, is_direct, and 996 * queue) 997 */ 998 static int mthca_alloc_wqe_buf(struct mthca_dev *dev, 999 struct mthca_pd *pd, 1000 struct mthca_qp *qp) 1001 { 1002 int size; 1003 int err = -ENOMEM; 1004 1005 size = sizeof (struct mthca_next_seg) + 1006 qp->rq.max_gs * sizeof (struct mthca_data_seg); 1007 1008 if (size > dev->limits.max_desc_sz) 1009 return -EINVAL; 1010 1011 for (qp->rq.wqe_shift = 6; 1 << qp->rq.wqe_shift < size; 1012 qp->rq.wqe_shift++) 1013 ; /* nothing */ 1014 1015 size = qp->sq.max_gs * sizeof (struct mthca_data_seg); 1016 switch (qp->transport) { 1017 case MLX: 1018 size += 2 * sizeof (struct mthca_data_seg); 1019 break; 1020 1021 case UD: 1022 size += mthca_is_memfree(dev) ? 1023 sizeof (struct mthca_arbel_ud_seg) : 1024 sizeof (struct mthca_tavor_ud_seg); 1025 break; 1026 1027 case UC: 1028 size += sizeof (struct mthca_raddr_seg); 1029 break; 1030 1031 case RC: 1032 size += sizeof (struct mthca_raddr_seg); 1033 /* 1034 * An atomic op will require an atomic segment, a 1035 * remote address segment and one scatter entry. 1036 */ 1037 size = max_t(int, size, 1038 sizeof (struct mthca_atomic_seg) + 1039 sizeof (struct mthca_raddr_seg) + 1040 sizeof (struct mthca_data_seg)); 1041 break; 1042 1043 default: 1044 break; 1045 } 1046 1047 /* Make sure that we have enough space for a bind request */ 1048 size = max_t(int, size, sizeof (struct mthca_bind_seg)); 1049 1050 size += sizeof (struct mthca_next_seg); 1051 1052 if (size > dev->limits.max_desc_sz) 1053 return -EINVAL; 1054 1055 for (qp->sq.wqe_shift = 6; 1 << qp->sq.wqe_shift < size; 1056 qp->sq.wqe_shift++) 1057 ; /* nothing */ 1058 1059 qp->send_wqe_offset = ALIGN(qp->rq.max << qp->rq.wqe_shift, 1060 1 << qp->sq.wqe_shift); 1061 1062 /* 1063 * If this is a userspace QP, we don't actually have to 1064 * allocate anything. All we need is to calculate the WQE 1065 * sizes and the send_wqe_offset, so we're done now. 1066 */ 1067 if (pd->ibpd.uobject) 1068 return 0; 1069 1070 size = PAGE_ALIGN(qp->send_wqe_offset + 1071 (qp->sq.max << qp->sq.wqe_shift)); 1072 1073 qp->wrid = kmalloc((qp->rq.max + qp->sq.max) * sizeof (u64), 1074 GFP_KERNEL); 1075 if (!qp->wrid) 1076 goto err_out; 1077 1078 err = mthca_buf_alloc(dev, size, MTHCA_MAX_DIRECT_QP_SIZE, 1079 &qp->queue, &qp->is_direct, pd, 0, &qp->mr); 1080 if (err) 1081 goto err_out; 1082 1083 return 0; 1084 1085 err_out: 1086 kfree(qp->wrid); 1087 return err; 1088 } 1089 1090 static void mthca_free_wqe_buf(struct mthca_dev *dev, 1091 struct mthca_qp *qp) 1092 { 1093 mthca_buf_free(dev, PAGE_ALIGN(qp->send_wqe_offset + 1094 (qp->sq.max << qp->sq.wqe_shift)), 1095 &qp->queue, qp->is_direct, &qp->mr); 1096 kfree(qp->wrid); 1097 } 1098 1099 static int mthca_map_memfree(struct mthca_dev *dev, 1100 struct mthca_qp *qp) 1101 { 1102 int ret; 1103 1104 if (mthca_is_memfree(dev)) { 1105 ret = mthca_table_get(dev, dev->qp_table.qp_table, qp->qpn); 1106 if (ret) 1107 return ret; 1108 1109 ret = mthca_table_get(dev, dev->qp_table.eqp_table, qp->qpn); 1110 if (ret) 1111 goto err_qpc; 1112 1113 ret = mthca_table_get(dev, dev->qp_table.rdb_table, 1114 qp->qpn << dev->qp_table.rdb_shift); 1115 if (ret) 1116 goto err_eqpc; 1117 1118 } 1119 1120 return 0; 1121 1122 err_eqpc: 1123 mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn); 1124 1125 err_qpc: 1126 mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn); 1127 1128 return ret; 1129 } 1130 1131 static void mthca_unmap_memfree(struct mthca_dev *dev, 1132 struct mthca_qp *qp) 1133 { 1134 mthca_table_put(dev, dev->qp_table.rdb_table, 1135 qp->qpn << dev->qp_table.rdb_shift); 1136 mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn); 1137 mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn); 1138 } 1139 1140 static int mthca_alloc_memfree(struct mthca_dev *dev, 1141 struct mthca_qp *qp) 1142 { 1143 if (mthca_is_memfree(dev)) { 1144 qp->rq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_RQ, 1145 qp->qpn, &qp->rq.db); 1146 if (qp->rq.db_index < 0) 1147 return -ENOMEM; 1148 1149 qp->sq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_SQ, 1150 qp->qpn, &qp->sq.db); 1151 if (qp->sq.db_index < 0) { 1152 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index); 1153 return -ENOMEM; 1154 } 1155 } 1156 1157 return 0; 1158 } 1159 1160 static void mthca_free_memfree(struct mthca_dev *dev, 1161 struct mthca_qp *qp) 1162 { 1163 if (mthca_is_memfree(dev)) { 1164 mthca_free_db(dev, MTHCA_DB_TYPE_SQ, qp->sq.db_index); 1165 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index); 1166 } 1167 } 1168 1169 static int mthca_alloc_qp_common(struct mthca_dev *dev, 1170 struct mthca_pd *pd, 1171 struct mthca_cq *send_cq, 1172 struct mthca_cq *recv_cq, 1173 enum ib_sig_type send_policy, 1174 struct mthca_qp *qp) 1175 { 1176 int ret; 1177 int i; 1178 1179 qp->refcount = 1; 1180 init_waitqueue_head(&qp->wait); 1181 mutex_init(&qp->mutex); 1182 qp->state = IB_QPS_RESET; 1183 qp->atomic_rd_en = 0; 1184 qp->resp_depth = 0; 1185 qp->sq_policy = send_policy; 1186 mthca_wq_reset(&qp->sq); 1187 mthca_wq_reset(&qp->rq); 1188 1189 spin_lock_init(&qp->sq.lock); 1190 spin_lock_init(&qp->rq.lock); 1191 1192 ret = mthca_map_memfree(dev, qp); 1193 if (ret) 1194 return ret; 1195 1196 ret = mthca_alloc_wqe_buf(dev, pd, qp); 1197 if (ret) { 1198 mthca_unmap_memfree(dev, qp); 1199 return ret; 1200 } 1201 1202 mthca_adjust_qp_caps(dev, pd, qp); 1203 1204 /* 1205 * If this is a userspace QP, we're done now. The doorbells 1206 * will be allocated and buffers will be initialized in 1207 * userspace. 1208 */ 1209 if (pd->ibpd.uobject) 1210 return 0; 1211 1212 ret = mthca_alloc_memfree(dev, qp); 1213 if (ret) { 1214 mthca_free_wqe_buf(dev, qp); 1215 mthca_unmap_memfree(dev, qp); 1216 return ret; 1217 } 1218 1219 if (mthca_is_memfree(dev)) { 1220 struct mthca_next_seg *next; 1221 struct mthca_data_seg *scatter; 1222 int size = (sizeof (struct mthca_next_seg) + 1223 qp->rq.max_gs * sizeof (struct mthca_data_seg)) / 16; 1224 1225 for (i = 0; i < qp->rq.max; ++i) { 1226 next = get_recv_wqe(qp, i); 1227 next->nda_op = cpu_to_be32(((i + 1) & (qp->rq.max - 1)) << 1228 qp->rq.wqe_shift); 1229 next->ee_nds = cpu_to_be32(size); 1230 1231 for (scatter = (void *) (next + 1); 1232 (void *) scatter < (void *) next + (1 << qp->rq.wqe_shift); 1233 ++scatter) 1234 scatter->lkey = cpu_to_be32(MTHCA_INVAL_LKEY); 1235 } 1236 1237 for (i = 0; i < qp->sq.max; ++i) { 1238 next = get_send_wqe(qp, i); 1239 next->nda_op = cpu_to_be32((((i + 1) & (qp->sq.max - 1)) << 1240 qp->sq.wqe_shift) + 1241 qp->send_wqe_offset); 1242 } 1243 } 1244 1245 qp->sq.last = get_send_wqe(qp, qp->sq.max - 1); 1246 qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1); 1247 1248 return 0; 1249 } 1250 1251 static int mthca_set_qp_size(struct mthca_dev *dev, struct ib_qp_cap *cap, 1252 struct mthca_pd *pd, struct mthca_qp *qp) 1253 { 1254 int max_data_size = mthca_max_data_size(dev, qp, dev->limits.max_desc_sz); 1255 1256 /* Sanity check QP size before proceeding */ 1257 if (cap->max_send_wr > dev->limits.max_wqes || 1258 cap->max_recv_wr > dev->limits.max_wqes || 1259 cap->max_send_sge > dev->limits.max_sg || 1260 cap->max_recv_sge > dev->limits.max_sg || 1261 cap->max_inline_data > mthca_max_inline_data(pd, max_data_size)) 1262 return -EINVAL; 1263 1264 /* 1265 * For MLX transport we need 2 extra S/G entries: 1266 * one for the header and one for the checksum at the end 1267 */ 1268 if (qp->transport == MLX && cap->max_recv_sge + 2 > dev->limits.max_sg) 1269 return -EINVAL; 1270 1271 if (mthca_is_memfree(dev)) { 1272 qp->rq.max = cap->max_recv_wr ? 1273 roundup_pow_of_two(cap->max_recv_wr) : 0; 1274 qp->sq.max = cap->max_send_wr ? 1275 roundup_pow_of_two(cap->max_send_wr) : 0; 1276 } else { 1277 qp->rq.max = cap->max_recv_wr; 1278 qp->sq.max = cap->max_send_wr; 1279 } 1280 1281 qp->rq.max_gs = cap->max_recv_sge; 1282 qp->sq.max_gs = max_t(int, cap->max_send_sge, 1283 ALIGN(cap->max_inline_data + MTHCA_INLINE_HEADER_SIZE, 1284 MTHCA_INLINE_CHUNK_SIZE) / 1285 sizeof (struct mthca_data_seg)); 1286 1287 return 0; 1288 } 1289 1290 int mthca_alloc_qp(struct mthca_dev *dev, 1291 struct mthca_pd *pd, 1292 struct mthca_cq *send_cq, 1293 struct mthca_cq *recv_cq, 1294 enum ib_qp_type type, 1295 enum ib_sig_type send_policy, 1296 struct ib_qp_cap *cap, 1297 struct mthca_qp *qp) 1298 { 1299 int err; 1300 1301 switch (type) { 1302 case IB_QPT_RC: qp->transport = RC; break; 1303 case IB_QPT_UC: qp->transport = UC; break; 1304 case IB_QPT_UD: qp->transport = UD; break; 1305 default: return -EINVAL; 1306 } 1307 1308 err = mthca_set_qp_size(dev, cap, pd, qp); 1309 if (err) 1310 return err; 1311 1312 qp->qpn = mthca_alloc(&dev->qp_table.alloc); 1313 if (qp->qpn == -1) 1314 return -ENOMEM; 1315 1316 /* initialize port to zero for error-catching. */ 1317 qp->port = 0; 1318 1319 err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq, 1320 send_policy, qp); 1321 if (err) { 1322 mthca_free(&dev->qp_table.alloc, qp->qpn); 1323 return err; 1324 } 1325 1326 spin_lock_irq(&dev->qp_table.lock); 1327 mthca_array_set(&dev->qp_table.qp, 1328 qp->qpn & (dev->limits.num_qps - 1), qp); 1329 spin_unlock_irq(&dev->qp_table.lock); 1330 1331 return 0; 1332 } 1333 1334 static void mthca_lock_cqs(struct mthca_cq *send_cq, struct mthca_cq *recv_cq) 1335 { 1336 if (send_cq == recv_cq) 1337 spin_lock_irq(&send_cq->lock); 1338 else if (send_cq->cqn < recv_cq->cqn) { 1339 spin_lock_irq(&send_cq->lock); 1340 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING); 1341 } else { 1342 spin_lock_irq(&recv_cq->lock); 1343 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING); 1344 } 1345 } 1346 1347 static void mthca_unlock_cqs(struct mthca_cq *send_cq, struct mthca_cq *recv_cq) 1348 { 1349 if (send_cq == recv_cq) 1350 spin_unlock_irq(&send_cq->lock); 1351 else if (send_cq->cqn < recv_cq->cqn) { 1352 spin_unlock(&recv_cq->lock); 1353 spin_unlock_irq(&send_cq->lock); 1354 } else { 1355 spin_unlock(&send_cq->lock); 1356 spin_unlock_irq(&recv_cq->lock); 1357 } 1358 } 1359 1360 int mthca_alloc_sqp(struct mthca_dev *dev, 1361 struct mthca_pd *pd, 1362 struct mthca_cq *send_cq, 1363 struct mthca_cq *recv_cq, 1364 enum ib_sig_type send_policy, 1365 struct ib_qp_cap *cap, 1366 int qpn, 1367 int port, 1368 struct mthca_sqp *sqp) 1369 { 1370 u32 mqpn = qpn * 2 + dev->qp_table.sqp_start + port - 1; 1371 int err; 1372 1373 sqp->qp.transport = MLX; 1374 err = mthca_set_qp_size(dev, cap, pd, &sqp->qp); 1375 if (err) 1376 return err; 1377 1378 sqp->header_buf_size = sqp->qp.sq.max * MTHCA_UD_HEADER_SIZE; 1379 sqp->header_buf = dma_alloc_coherent(&dev->pdev->dev, sqp->header_buf_size, 1380 &sqp->header_dma, GFP_KERNEL); 1381 if (!sqp->header_buf) 1382 return -ENOMEM; 1383 1384 spin_lock_irq(&dev->qp_table.lock); 1385 if (mthca_array_get(&dev->qp_table.qp, mqpn)) 1386 err = -EBUSY; 1387 else 1388 mthca_array_set(&dev->qp_table.qp, mqpn, sqp); 1389 spin_unlock_irq(&dev->qp_table.lock); 1390 1391 if (err) 1392 goto err_out; 1393 1394 sqp->qp.port = port; 1395 sqp->qp.qpn = mqpn; 1396 sqp->qp.transport = MLX; 1397 1398 err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq, 1399 send_policy, &sqp->qp); 1400 if (err) 1401 goto err_out_free; 1402 1403 atomic_inc(&pd->sqp_count); 1404 1405 return 0; 1406 1407 err_out_free: 1408 /* 1409 * Lock CQs here, so that CQ polling code can do QP lookup 1410 * without taking a lock. 1411 */ 1412 mthca_lock_cqs(send_cq, recv_cq); 1413 1414 spin_lock(&dev->qp_table.lock); 1415 mthca_array_clear(&dev->qp_table.qp, mqpn); 1416 spin_unlock(&dev->qp_table.lock); 1417 1418 mthca_unlock_cqs(send_cq, recv_cq); 1419 1420 err_out: 1421 dma_free_coherent(&dev->pdev->dev, sqp->header_buf_size, 1422 sqp->header_buf, sqp->header_dma); 1423 1424 return err; 1425 } 1426 1427 static inline int get_qp_refcount(struct mthca_dev *dev, struct mthca_qp *qp) 1428 { 1429 int c; 1430 1431 spin_lock_irq(&dev->qp_table.lock); 1432 c = qp->refcount; 1433 spin_unlock_irq(&dev->qp_table.lock); 1434 1435 return c; 1436 } 1437 1438 void mthca_free_qp(struct mthca_dev *dev, 1439 struct mthca_qp *qp) 1440 { 1441 u8 status; 1442 struct mthca_cq *send_cq; 1443 struct mthca_cq *recv_cq; 1444 1445 send_cq = to_mcq(qp->ibqp.send_cq); 1446 recv_cq = to_mcq(qp->ibqp.recv_cq); 1447 1448 /* 1449 * Lock CQs here, so that CQ polling code can do QP lookup 1450 * without taking a lock. 1451 */ 1452 mthca_lock_cqs(send_cq, recv_cq); 1453 1454 spin_lock(&dev->qp_table.lock); 1455 mthca_array_clear(&dev->qp_table.qp, 1456 qp->qpn & (dev->limits.num_qps - 1)); 1457 --qp->refcount; 1458 spin_unlock(&dev->qp_table.lock); 1459 1460 mthca_unlock_cqs(send_cq, recv_cq); 1461 1462 wait_event(qp->wait, !get_qp_refcount(dev, qp)); 1463 1464 if (qp->state != IB_QPS_RESET) 1465 mthca_MODIFY_QP(dev, qp->state, IB_QPS_RESET, qp->qpn, 0, 1466 NULL, 0, &status); 1467 1468 /* 1469 * If this is a userspace QP, the buffers, MR, CQs and so on 1470 * will be cleaned up in userspace, so all we have to do is 1471 * unref the mem-free tables and free the QPN in our table. 1472 */ 1473 if (!qp->ibqp.uobject) { 1474 mthca_cq_clean(dev, recv_cq, qp->qpn, 1475 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL); 1476 if (send_cq != recv_cq) 1477 mthca_cq_clean(dev, send_cq, qp->qpn, NULL); 1478 1479 mthca_free_memfree(dev, qp); 1480 mthca_free_wqe_buf(dev, qp); 1481 } 1482 1483 mthca_unmap_memfree(dev, qp); 1484 1485 if (is_sqp(dev, qp)) { 1486 atomic_dec(&(to_mpd(qp->ibqp.pd)->sqp_count)); 1487 dma_free_coherent(&dev->pdev->dev, 1488 to_msqp(qp)->header_buf_size, 1489 to_msqp(qp)->header_buf, 1490 to_msqp(qp)->header_dma); 1491 } else 1492 mthca_free(&dev->qp_table.alloc, qp->qpn); 1493 } 1494 1495 /* Create UD header for an MLX send and build a data segment for it */ 1496 static int build_mlx_header(struct mthca_dev *dev, struct mthca_sqp *sqp, 1497 int ind, struct ib_send_wr *wr, 1498 struct mthca_mlx_seg *mlx, 1499 struct mthca_data_seg *data) 1500 { 1501 int header_size; 1502 int err; 1503 u16 pkey; 1504 1505 ib_ud_header_init(256, /* assume a MAD */ 1506 mthca_ah_grh_present(to_mah(wr->wr.ud.ah)), 1507 &sqp->ud_header); 1508 1509 err = mthca_read_ah(dev, to_mah(wr->wr.ud.ah), &sqp->ud_header); 1510 if (err) 1511 return err; 1512 mlx->flags &= ~cpu_to_be32(MTHCA_NEXT_SOLICIT | 1); 1513 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MTHCA_MLX_VL15 : 0) | 1514 (sqp->ud_header.lrh.destination_lid == 1515 IB_LID_PERMISSIVE ? MTHCA_MLX_SLR : 0) | 1516 (sqp->ud_header.lrh.service_level << 8)); 1517 mlx->rlid = sqp->ud_header.lrh.destination_lid; 1518 mlx->vcrc = 0; 1519 1520 switch (wr->opcode) { 1521 case IB_WR_SEND: 1522 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY; 1523 sqp->ud_header.immediate_present = 0; 1524 break; 1525 case IB_WR_SEND_WITH_IMM: 1526 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE; 1527 sqp->ud_header.immediate_present = 1; 1528 sqp->ud_header.immediate_data = wr->imm_data; 1529 break; 1530 default: 1531 return -EINVAL; 1532 } 1533 1534 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 : 0; 1535 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE) 1536 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE; 1537 sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED); 1538 if (!sqp->qp.ibqp.qp_num) 1539 ib_get_cached_pkey(&dev->ib_dev, sqp->qp.port, 1540 sqp->pkey_index, &pkey); 1541 else 1542 ib_get_cached_pkey(&dev->ib_dev, sqp->qp.port, 1543 wr->wr.ud.pkey_index, &pkey); 1544 sqp->ud_header.bth.pkey = cpu_to_be16(pkey); 1545 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn); 1546 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1)); 1547 sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ? 1548 sqp->qkey : wr->wr.ud.remote_qkey); 1549 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num); 1550 1551 header_size = ib_ud_header_pack(&sqp->ud_header, 1552 sqp->header_buf + 1553 ind * MTHCA_UD_HEADER_SIZE); 1554 1555 data->byte_count = cpu_to_be32(header_size); 1556 data->lkey = cpu_to_be32(to_mpd(sqp->qp.ibqp.pd)->ntmr.ibmr.lkey); 1557 data->addr = cpu_to_be64(sqp->header_dma + 1558 ind * MTHCA_UD_HEADER_SIZE); 1559 1560 return 0; 1561 } 1562 1563 static inline int mthca_wq_overflow(struct mthca_wq *wq, int nreq, 1564 struct ib_cq *ib_cq) 1565 { 1566 unsigned cur; 1567 struct mthca_cq *cq; 1568 1569 cur = wq->head - wq->tail; 1570 if (likely(cur + nreq < wq->max)) 1571 return 0; 1572 1573 cq = to_mcq(ib_cq); 1574 spin_lock(&cq->lock); 1575 cur = wq->head - wq->tail; 1576 spin_unlock(&cq->lock); 1577 1578 return cur + nreq >= wq->max; 1579 } 1580 1581 static __always_inline void set_raddr_seg(struct mthca_raddr_seg *rseg, 1582 u64 remote_addr, u32 rkey) 1583 { 1584 rseg->raddr = cpu_to_be64(remote_addr); 1585 rseg->rkey = cpu_to_be32(rkey); 1586 rseg->reserved = 0; 1587 } 1588 1589 static __always_inline void set_atomic_seg(struct mthca_atomic_seg *aseg, 1590 struct ib_send_wr *wr) 1591 { 1592 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) { 1593 aseg->swap_add = cpu_to_be64(wr->wr.atomic.swap); 1594 aseg->compare = cpu_to_be64(wr->wr.atomic.compare_add); 1595 } else { 1596 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add); 1597 aseg->compare = 0; 1598 } 1599 1600 } 1601 1602 static void set_tavor_ud_seg(struct mthca_tavor_ud_seg *useg, 1603 struct ib_send_wr *wr) 1604 { 1605 useg->lkey = cpu_to_be32(to_mah(wr->wr.ud.ah)->key); 1606 useg->av_addr = cpu_to_be64(to_mah(wr->wr.ud.ah)->avdma); 1607 useg->dqpn = cpu_to_be32(wr->wr.ud.remote_qpn); 1608 useg->qkey = cpu_to_be32(wr->wr.ud.remote_qkey); 1609 1610 } 1611 1612 static void set_arbel_ud_seg(struct mthca_arbel_ud_seg *useg, 1613 struct ib_send_wr *wr) 1614 { 1615 memcpy(useg->av, to_mah(wr->wr.ud.ah)->av, MTHCA_AV_SIZE); 1616 useg->dqpn = cpu_to_be32(wr->wr.ud.remote_qpn); 1617 useg->qkey = cpu_to_be32(wr->wr.ud.remote_qkey); 1618 } 1619 1620 int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 1621 struct ib_send_wr **bad_wr) 1622 { 1623 struct mthca_dev *dev = to_mdev(ibqp->device); 1624 struct mthca_qp *qp = to_mqp(ibqp); 1625 void *wqe; 1626 void *prev_wqe; 1627 unsigned long flags; 1628 int err = 0; 1629 int nreq; 1630 int i; 1631 int size; 1632 /* 1633 * f0 and size0 are only used if nreq != 0, and they will 1634 * always be initialized the first time through the main loop 1635 * before nreq is incremented. So nreq cannot become non-zero 1636 * without initializing f0 and size0, and they are in fact 1637 * never used uninitialized. 1638 */ 1639 int uninitialized_var(size0); 1640 u32 uninitialized_var(f0); 1641 int ind; 1642 u8 op0 = 0; 1643 1644 spin_lock_irqsave(&qp->sq.lock, flags); 1645 1646 /* XXX check that state is OK to post send */ 1647 1648 ind = qp->sq.next_ind; 1649 1650 for (nreq = 0; wr; ++nreq, wr = wr->next) { 1651 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) { 1652 mthca_err(dev, "SQ %06x full (%u head, %u tail," 1653 " %d max, %d nreq)\n", qp->qpn, 1654 qp->sq.head, qp->sq.tail, 1655 qp->sq.max, nreq); 1656 err = -ENOMEM; 1657 *bad_wr = wr; 1658 goto out; 1659 } 1660 1661 wqe = get_send_wqe(qp, ind); 1662 prev_wqe = qp->sq.last; 1663 qp->sq.last = wqe; 1664 1665 ((struct mthca_next_seg *) wqe)->nda_op = 0; 1666 ((struct mthca_next_seg *) wqe)->ee_nds = 0; 1667 ((struct mthca_next_seg *) wqe)->flags = 1668 ((wr->send_flags & IB_SEND_SIGNALED) ? 1669 cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) | 1670 ((wr->send_flags & IB_SEND_SOLICITED) ? 1671 cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0) | 1672 cpu_to_be32(1); 1673 if (wr->opcode == IB_WR_SEND_WITH_IMM || 1674 wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM) 1675 ((struct mthca_next_seg *) wqe)->imm = wr->imm_data; 1676 1677 wqe += sizeof (struct mthca_next_seg); 1678 size = sizeof (struct mthca_next_seg) / 16; 1679 1680 switch (qp->transport) { 1681 case RC: 1682 switch (wr->opcode) { 1683 case IB_WR_ATOMIC_CMP_AND_SWP: 1684 case IB_WR_ATOMIC_FETCH_AND_ADD: 1685 set_raddr_seg(wqe, wr->wr.atomic.remote_addr, 1686 wr->wr.atomic.rkey); 1687 wqe += sizeof (struct mthca_raddr_seg); 1688 1689 set_atomic_seg(wqe, wr); 1690 wqe += sizeof (struct mthca_atomic_seg); 1691 size += (sizeof (struct mthca_raddr_seg) + 1692 sizeof (struct mthca_atomic_seg)) / 16; 1693 break; 1694 1695 case IB_WR_RDMA_WRITE: 1696 case IB_WR_RDMA_WRITE_WITH_IMM: 1697 case IB_WR_RDMA_READ: 1698 set_raddr_seg(wqe, wr->wr.rdma.remote_addr, 1699 wr->wr.rdma.rkey); 1700 wqe += sizeof (struct mthca_raddr_seg); 1701 size += sizeof (struct mthca_raddr_seg) / 16; 1702 break; 1703 1704 default: 1705 /* No extra segments required for sends */ 1706 break; 1707 } 1708 1709 break; 1710 1711 case UC: 1712 switch (wr->opcode) { 1713 case IB_WR_RDMA_WRITE: 1714 case IB_WR_RDMA_WRITE_WITH_IMM: 1715 set_raddr_seg(wqe, wr->wr.rdma.remote_addr, 1716 wr->wr.rdma.rkey); 1717 wqe += sizeof (struct mthca_raddr_seg); 1718 size += sizeof (struct mthca_raddr_seg) / 16; 1719 break; 1720 1721 default: 1722 /* No extra segments required for sends */ 1723 break; 1724 } 1725 1726 break; 1727 1728 case UD: 1729 set_tavor_ud_seg(wqe, wr); 1730 wqe += sizeof (struct mthca_tavor_ud_seg); 1731 size += sizeof (struct mthca_tavor_ud_seg) / 16; 1732 break; 1733 1734 case MLX: 1735 err = build_mlx_header(dev, to_msqp(qp), ind, wr, 1736 wqe - sizeof (struct mthca_next_seg), 1737 wqe); 1738 if (err) { 1739 *bad_wr = wr; 1740 goto out; 1741 } 1742 wqe += sizeof (struct mthca_data_seg); 1743 size += sizeof (struct mthca_data_seg) / 16; 1744 break; 1745 } 1746 1747 if (wr->num_sge > qp->sq.max_gs) { 1748 mthca_err(dev, "too many gathers\n"); 1749 err = -EINVAL; 1750 *bad_wr = wr; 1751 goto out; 1752 } 1753 1754 for (i = 0; i < wr->num_sge; ++i) { 1755 mthca_set_data_seg(wqe, wr->sg_list + i); 1756 wqe += sizeof (struct mthca_data_seg); 1757 size += sizeof (struct mthca_data_seg) / 16; 1758 } 1759 1760 /* Add one more inline data segment for ICRC */ 1761 if (qp->transport == MLX) { 1762 ((struct mthca_data_seg *) wqe)->byte_count = 1763 cpu_to_be32((1 << 31) | 4); 1764 ((u32 *) wqe)[1] = 0; 1765 wqe += sizeof (struct mthca_data_seg); 1766 size += sizeof (struct mthca_data_seg) / 16; 1767 } 1768 1769 qp->wrid[ind + qp->rq.max] = wr->wr_id; 1770 1771 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) { 1772 mthca_err(dev, "opcode invalid\n"); 1773 err = -EINVAL; 1774 *bad_wr = wr; 1775 goto out; 1776 } 1777 1778 ((struct mthca_next_seg *) prev_wqe)->nda_op = 1779 cpu_to_be32(((ind << qp->sq.wqe_shift) + 1780 qp->send_wqe_offset) | 1781 mthca_opcode[wr->opcode]); 1782 wmb(); 1783 ((struct mthca_next_seg *) prev_wqe)->ee_nds = 1784 cpu_to_be32((nreq ? 0 : MTHCA_NEXT_DBD) | size | 1785 ((wr->send_flags & IB_SEND_FENCE) ? 1786 MTHCA_NEXT_FENCE : 0)); 1787 1788 if (!nreq) { 1789 size0 = size; 1790 op0 = mthca_opcode[wr->opcode]; 1791 f0 = wr->send_flags & IB_SEND_FENCE ? 1792 MTHCA_SEND_DOORBELL_FENCE : 0; 1793 } 1794 1795 ++ind; 1796 if (unlikely(ind >= qp->sq.max)) 1797 ind -= qp->sq.max; 1798 } 1799 1800 out: 1801 if (likely(nreq)) { 1802 __be32 doorbell[2]; 1803 1804 doorbell[0] = cpu_to_be32(((qp->sq.next_ind << qp->sq.wqe_shift) + 1805 qp->send_wqe_offset) | f0 | op0); 1806 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0); 1807 1808 wmb(); 1809 1810 mthca_write64(doorbell, 1811 dev->kar + MTHCA_SEND_DOORBELL, 1812 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); 1813 /* 1814 * Make sure doorbells don't leak out of SQ spinlock 1815 * and reach the HCA out of order: 1816 */ 1817 mmiowb(); 1818 } 1819 1820 qp->sq.next_ind = ind; 1821 qp->sq.head += nreq; 1822 1823 spin_unlock_irqrestore(&qp->sq.lock, flags); 1824 return err; 1825 } 1826 1827 int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr, 1828 struct ib_recv_wr **bad_wr) 1829 { 1830 struct mthca_dev *dev = to_mdev(ibqp->device); 1831 struct mthca_qp *qp = to_mqp(ibqp); 1832 __be32 doorbell[2]; 1833 unsigned long flags; 1834 int err = 0; 1835 int nreq; 1836 int i; 1837 int size; 1838 /* 1839 * size0 is only used if nreq != 0, and it will always be 1840 * initialized the first time through the main loop before 1841 * nreq is incremented. So nreq cannot become non-zero 1842 * without initializing size0, and it is in fact never used 1843 * uninitialized. 1844 */ 1845 int uninitialized_var(size0); 1846 int ind; 1847 void *wqe; 1848 void *prev_wqe; 1849 1850 spin_lock_irqsave(&qp->rq.lock, flags); 1851 1852 /* XXX check that state is OK to post receive */ 1853 1854 ind = qp->rq.next_ind; 1855 1856 for (nreq = 0; wr; wr = wr->next) { 1857 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) { 1858 mthca_err(dev, "RQ %06x full (%u head, %u tail," 1859 " %d max, %d nreq)\n", qp->qpn, 1860 qp->rq.head, qp->rq.tail, 1861 qp->rq.max, nreq); 1862 err = -ENOMEM; 1863 *bad_wr = wr; 1864 goto out; 1865 } 1866 1867 wqe = get_recv_wqe(qp, ind); 1868 prev_wqe = qp->rq.last; 1869 qp->rq.last = wqe; 1870 1871 ((struct mthca_next_seg *) wqe)->nda_op = 0; 1872 ((struct mthca_next_seg *) wqe)->ee_nds = 1873 cpu_to_be32(MTHCA_NEXT_DBD); 1874 ((struct mthca_next_seg *) wqe)->flags = 0; 1875 1876 wqe += sizeof (struct mthca_next_seg); 1877 size = sizeof (struct mthca_next_seg) / 16; 1878 1879 if (unlikely(wr->num_sge > qp->rq.max_gs)) { 1880 err = -EINVAL; 1881 *bad_wr = wr; 1882 goto out; 1883 } 1884 1885 for (i = 0; i < wr->num_sge; ++i) { 1886 mthca_set_data_seg(wqe, wr->sg_list + i); 1887 wqe += sizeof (struct mthca_data_seg); 1888 size += sizeof (struct mthca_data_seg) / 16; 1889 } 1890 1891 qp->wrid[ind] = wr->wr_id; 1892 1893 ((struct mthca_next_seg *) prev_wqe)->nda_op = 1894 cpu_to_be32((ind << qp->rq.wqe_shift) | 1); 1895 wmb(); 1896 ((struct mthca_next_seg *) prev_wqe)->ee_nds = 1897 cpu_to_be32(MTHCA_NEXT_DBD | size); 1898 1899 if (!nreq) 1900 size0 = size; 1901 1902 ++ind; 1903 if (unlikely(ind >= qp->rq.max)) 1904 ind -= qp->rq.max; 1905 1906 ++nreq; 1907 if (unlikely(nreq == MTHCA_TAVOR_MAX_WQES_PER_RECV_DB)) { 1908 nreq = 0; 1909 1910 doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0); 1911 doorbell[1] = cpu_to_be32(qp->qpn << 8); 1912 1913 wmb(); 1914 1915 mthca_write64(doorbell, 1916 dev->kar + MTHCA_RECEIVE_DOORBELL, 1917 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); 1918 1919 qp->rq.next_ind = ind; 1920 qp->rq.head += MTHCA_TAVOR_MAX_WQES_PER_RECV_DB; 1921 } 1922 } 1923 1924 out: 1925 if (likely(nreq)) { 1926 doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0); 1927 doorbell[1] = cpu_to_be32((qp->qpn << 8) | nreq); 1928 1929 wmb(); 1930 1931 mthca_write64(doorbell, 1932 dev->kar + MTHCA_RECEIVE_DOORBELL, 1933 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); 1934 } 1935 1936 qp->rq.next_ind = ind; 1937 qp->rq.head += nreq; 1938 1939 /* 1940 * Make sure doorbells don't leak out of RQ spinlock and reach 1941 * the HCA out of order: 1942 */ 1943 mmiowb(); 1944 1945 spin_unlock_irqrestore(&qp->rq.lock, flags); 1946 return err; 1947 } 1948 1949 int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 1950 struct ib_send_wr **bad_wr) 1951 { 1952 struct mthca_dev *dev = to_mdev(ibqp->device); 1953 struct mthca_qp *qp = to_mqp(ibqp); 1954 __be32 doorbell[2]; 1955 void *wqe; 1956 void *prev_wqe; 1957 unsigned long flags; 1958 int err = 0; 1959 int nreq; 1960 int i; 1961 int size; 1962 /* 1963 * f0 and size0 are only used if nreq != 0, and they will 1964 * always be initialized the first time through the main loop 1965 * before nreq is incremented. So nreq cannot become non-zero 1966 * without initializing f0 and size0, and they are in fact 1967 * never used uninitialized. 1968 */ 1969 int uninitialized_var(size0); 1970 u32 uninitialized_var(f0); 1971 int ind; 1972 u8 op0 = 0; 1973 1974 spin_lock_irqsave(&qp->sq.lock, flags); 1975 1976 /* XXX check that state is OK to post send */ 1977 1978 ind = qp->sq.head & (qp->sq.max - 1); 1979 1980 for (nreq = 0; wr; ++nreq, wr = wr->next) { 1981 if (unlikely(nreq == MTHCA_ARBEL_MAX_WQES_PER_SEND_DB)) { 1982 nreq = 0; 1983 1984 doorbell[0] = cpu_to_be32((MTHCA_ARBEL_MAX_WQES_PER_SEND_DB << 24) | 1985 ((qp->sq.head & 0xffff) << 8) | 1986 f0 | op0); 1987 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0); 1988 1989 qp->sq.head += MTHCA_ARBEL_MAX_WQES_PER_SEND_DB; 1990 1991 /* 1992 * Make sure that descriptors are written before 1993 * doorbell record. 1994 */ 1995 wmb(); 1996 *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff); 1997 1998 /* 1999 * Make sure doorbell record is written before we 2000 * write MMIO send doorbell. 2001 */ 2002 wmb(); 2003 mthca_write64(doorbell, 2004 dev->kar + MTHCA_SEND_DOORBELL, 2005 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); 2006 } 2007 2008 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) { 2009 mthca_err(dev, "SQ %06x full (%u head, %u tail," 2010 " %d max, %d nreq)\n", qp->qpn, 2011 qp->sq.head, qp->sq.tail, 2012 qp->sq.max, nreq); 2013 err = -ENOMEM; 2014 *bad_wr = wr; 2015 goto out; 2016 } 2017 2018 wqe = get_send_wqe(qp, ind); 2019 prev_wqe = qp->sq.last; 2020 qp->sq.last = wqe; 2021 2022 ((struct mthca_next_seg *) wqe)->flags = 2023 ((wr->send_flags & IB_SEND_SIGNALED) ? 2024 cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) | 2025 ((wr->send_flags & IB_SEND_SOLICITED) ? 2026 cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0) | 2027 cpu_to_be32(1); 2028 if (wr->opcode == IB_WR_SEND_WITH_IMM || 2029 wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM) 2030 ((struct mthca_next_seg *) wqe)->imm = wr->imm_data; 2031 2032 wqe += sizeof (struct mthca_next_seg); 2033 size = sizeof (struct mthca_next_seg) / 16; 2034 2035 switch (qp->transport) { 2036 case RC: 2037 switch (wr->opcode) { 2038 case IB_WR_ATOMIC_CMP_AND_SWP: 2039 case IB_WR_ATOMIC_FETCH_AND_ADD: 2040 set_raddr_seg(wqe, wr->wr.atomic.remote_addr, 2041 wr->wr.atomic.rkey); 2042 wqe += sizeof (struct mthca_raddr_seg); 2043 2044 set_atomic_seg(wqe, wr); 2045 wqe += sizeof (struct mthca_atomic_seg); 2046 size += (sizeof (struct mthca_raddr_seg) + 2047 sizeof (struct mthca_atomic_seg)) / 16; 2048 break; 2049 2050 case IB_WR_RDMA_READ: 2051 case IB_WR_RDMA_WRITE: 2052 case IB_WR_RDMA_WRITE_WITH_IMM: 2053 set_raddr_seg(wqe, wr->wr.rdma.remote_addr, 2054 wr->wr.rdma.rkey); 2055 wqe += sizeof (struct mthca_raddr_seg); 2056 size += sizeof (struct mthca_raddr_seg) / 16; 2057 break; 2058 2059 default: 2060 /* No extra segments required for sends */ 2061 break; 2062 } 2063 2064 break; 2065 2066 case UC: 2067 switch (wr->opcode) { 2068 case IB_WR_RDMA_WRITE: 2069 case IB_WR_RDMA_WRITE_WITH_IMM: 2070 set_raddr_seg(wqe, wr->wr.rdma.remote_addr, 2071 wr->wr.rdma.rkey); 2072 wqe += sizeof (struct mthca_raddr_seg); 2073 size += sizeof (struct mthca_raddr_seg) / 16; 2074 break; 2075 2076 default: 2077 /* No extra segments required for sends */ 2078 break; 2079 } 2080 2081 break; 2082 2083 case UD: 2084 set_arbel_ud_seg(wqe, wr); 2085 wqe += sizeof (struct mthca_arbel_ud_seg); 2086 size += sizeof (struct mthca_arbel_ud_seg) / 16; 2087 break; 2088 2089 case MLX: 2090 err = build_mlx_header(dev, to_msqp(qp), ind, wr, 2091 wqe - sizeof (struct mthca_next_seg), 2092 wqe); 2093 if (err) { 2094 *bad_wr = wr; 2095 goto out; 2096 } 2097 wqe += sizeof (struct mthca_data_seg); 2098 size += sizeof (struct mthca_data_seg) / 16; 2099 break; 2100 } 2101 2102 if (wr->num_sge > qp->sq.max_gs) { 2103 mthca_err(dev, "too many gathers\n"); 2104 err = -EINVAL; 2105 *bad_wr = wr; 2106 goto out; 2107 } 2108 2109 for (i = 0; i < wr->num_sge; ++i) { 2110 mthca_set_data_seg(wqe, wr->sg_list + i); 2111 wqe += sizeof (struct mthca_data_seg); 2112 size += sizeof (struct mthca_data_seg) / 16; 2113 } 2114 2115 /* Add one more inline data segment for ICRC */ 2116 if (qp->transport == MLX) { 2117 ((struct mthca_data_seg *) wqe)->byte_count = 2118 cpu_to_be32((1 << 31) | 4); 2119 ((u32 *) wqe)[1] = 0; 2120 wqe += sizeof (struct mthca_data_seg); 2121 size += sizeof (struct mthca_data_seg) / 16; 2122 } 2123 2124 qp->wrid[ind + qp->rq.max] = wr->wr_id; 2125 2126 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) { 2127 mthca_err(dev, "opcode invalid\n"); 2128 err = -EINVAL; 2129 *bad_wr = wr; 2130 goto out; 2131 } 2132 2133 ((struct mthca_next_seg *) prev_wqe)->nda_op = 2134 cpu_to_be32(((ind << qp->sq.wqe_shift) + 2135 qp->send_wqe_offset) | 2136 mthca_opcode[wr->opcode]); 2137 wmb(); 2138 ((struct mthca_next_seg *) prev_wqe)->ee_nds = 2139 cpu_to_be32(MTHCA_NEXT_DBD | size | 2140 ((wr->send_flags & IB_SEND_FENCE) ? 2141 MTHCA_NEXT_FENCE : 0)); 2142 2143 if (!nreq) { 2144 size0 = size; 2145 op0 = mthca_opcode[wr->opcode]; 2146 f0 = wr->send_flags & IB_SEND_FENCE ? 2147 MTHCA_SEND_DOORBELL_FENCE : 0; 2148 } 2149 2150 ++ind; 2151 if (unlikely(ind >= qp->sq.max)) 2152 ind -= qp->sq.max; 2153 } 2154 2155 out: 2156 if (likely(nreq)) { 2157 doorbell[0] = cpu_to_be32((nreq << 24) | 2158 ((qp->sq.head & 0xffff) << 8) | 2159 f0 | op0); 2160 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0); 2161 2162 qp->sq.head += nreq; 2163 2164 /* 2165 * Make sure that descriptors are written before 2166 * doorbell record. 2167 */ 2168 wmb(); 2169 *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff); 2170 2171 /* 2172 * Make sure doorbell record is written before we 2173 * write MMIO send doorbell. 2174 */ 2175 wmb(); 2176 mthca_write64(doorbell, 2177 dev->kar + MTHCA_SEND_DOORBELL, 2178 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); 2179 } 2180 2181 /* 2182 * Make sure doorbells don't leak out of SQ spinlock and reach 2183 * the HCA out of order: 2184 */ 2185 mmiowb(); 2186 2187 spin_unlock_irqrestore(&qp->sq.lock, flags); 2188 return err; 2189 } 2190 2191 int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr, 2192 struct ib_recv_wr **bad_wr) 2193 { 2194 struct mthca_dev *dev = to_mdev(ibqp->device); 2195 struct mthca_qp *qp = to_mqp(ibqp); 2196 unsigned long flags; 2197 int err = 0; 2198 int nreq; 2199 int ind; 2200 int i; 2201 void *wqe; 2202 2203 spin_lock_irqsave(&qp->rq.lock, flags); 2204 2205 /* XXX check that state is OK to post receive */ 2206 2207 ind = qp->rq.head & (qp->rq.max - 1); 2208 2209 for (nreq = 0; wr; ++nreq, wr = wr->next) { 2210 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) { 2211 mthca_err(dev, "RQ %06x full (%u head, %u tail," 2212 " %d max, %d nreq)\n", qp->qpn, 2213 qp->rq.head, qp->rq.tail, 2214 qp->rq.max, nreq); 2215 err = -ENOMEM; 2216 *bad_wr = wr; 2217 goto out; 2218 } 2219 2220 wqe = get_recv_wqe(qp, ind); 2221 2222 ((struct mthca_next_seg *) wqe)->flags = 0; 2223 2224 wqe += sizeof (struct mthca_next_seg); 2225 2226 if (unlikely(wr->num_sge > qp->rq.max_gs)) { 2227 err = -EINVAL; 2228 *bad_wr = wr; 2229 goto out; 2230 } 2231 2232 for (i = 0; i < wr->num_sge; ++i) { 2233 mthca_set_data_seg(wqe, wr->sg_list + i); 2234 wqe += sizeof (struct mthca_data_seg); 2235 } 2236 2237 if (i < qp->rq.max_gs) 2238 mthca_set_data_seg_inval(wqe); 2239 2240 qp->wrid[ind] = wr->wr_id; 2241 2242 ++ind; 2243 if (unlikely(ind >= qp->rq.max)) 2244 ind -= qp->rq.max; 2245 } 2246 out: 2247 if (likely(nreq)) { 2248 qp->rq.head += nreq; 2249 2250 /* 2251 * Make sure that descriptors are written before 2252 * doorbell record. 2253 */ 2254 wmb(); 2255 *qp->rq.db = cpu_to_be32(qp->rq.head & 0xffff); 2256 } 2257 2258 spin_unlock_irqrestore(&qp->rq.lock, flags); 2259 return err; 2260 } 2261 2262 void mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send, 2263 int index, int *dbd, __be32 *new_wqe) 2264 { 2265 struct mthca_next_seg *next; 2266 2267 /* 2268 * For SRQs, all receive WQEs generate a CQE, so we're always 2269 * at the end of the doorbell chain. 2270 */ 2271 if (qp->ibqp.srq && !is_send) { 2272 *new_wqe = 0; 2273 return; 2274 } 2275 2276 if (is_send) 2277 next = get_send_wqe(qp, index); 2278 else 2279 next = get_recv_wqe(qp, index); 2280 2281 *dbd = !!(next->ee_nds & cpu_to_be32(MTHCA_NEXT_DBD)); 2282 if (next->ee_nds & cpu_to_be32(0x3f)) 2283 *new_wqe = (next->nda_op & cpu_to_be32(~0x3f)) | 2284 (next->ee_nds & cpu_to_be32(0x3f)); 2285 else 2286 *new_wqe = 0; 2287 } 2288 2289 int mthca_init_qp_table(struct mthca_dev *dev) 2290 { 2291 int err; 2292 u8 status; 2293 int i; 2294 2295 spin_lock_init(&dev->qp_table.lock); 2296 2297 /* 2298 * We reserve 2 extra QPs per port for the special QPs. The 2299 * special QP for port 1 has to be even, so round up. 2300 */ 2301 dev->qp_table.sqp_start = (dev->limits.reserved_qps + 1) & ~1UL; 2302 err = mthca_alloc_init(&dev->qp_table.alloc, 2303 dev->limits.num_qps, 2304 (1 << 24) - 1, 2305 dev->qp_table.sqp_start + 2306 MTHCA_MAX_PORTS * 2); 2307 if (err) 2308 return err; 2309 2310 err = mthca_array_init(&dev->qp_table.qp, 2311 dev->limits.num_qps); 2312 if (err) { 2313 mthca_alloc_cleanup(&dev->qp_table.alloc); 2314 return err; 2315 } 2316 2317 for (i = 0; i < 2; ++i) { 2318 err = mthca_CONF_SPECIAL_QP(dev, i ? IB_QPT_GSI : IB_QPT_SMI, 2319 dev->qp_table.sqp_start + i * 2, 2320 &status); 2321 if (err) 2322 goto err_out; 2323 if (status) { 2324 mthca_warn(dev, "CONF_SPECIAL_QP returned " 2325 "status %02x, aborting.\n", 2326 status); 2327 err = -EINVAL; 2328 goto err_out; 2329 } 2330 } 2331 return 0; 2332 2333 err_out: 2334 for (i = 0; i < 2; ++i) 2335 mthca_CONF_SPECIAL_QP(dev, i, 0, &status); 2336 2337 mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps); 2338 mthca_alloc_cleanup(&dev->qp_table.alloc); 2339 2340 return err; 2341 } 2342 2343 void mthca_cleanup_qp_table(struct mthca_dev *dev) 2344 { 2345 int i; 2346 u8 status; 2347 2348 for (i = 0; i < 2; ++i) 2349 mthca_CONF_SPECIAL_QP(dev, i, 0, &status); 2350 2351 mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps); 2352 mthca_alloc_cleanup(&dev->qp_table.alloc); 2353 } 2354