1 /* 2 * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/module.h> 34 #include <rdma/ib_umem.h> 35 #include "mlx5_ib.h" 36 #include "user.h" 37 38 /* not supported currently */ 39 static int wq_signature; 40 41 enum { 42 MLX5_IB_ACK_REQ_FREQ = 8, 43 }; 44 45 enum { 46 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83, 47 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, 48 MLX5_IB_LINK_TYPE_IB = 0, 49 MLX5_IB_LINK_TYPE_ETH = 1 50 }; 51 52 enum { 53 MLX5_IB_SQ_STRIDE = 6, 54 MLX5_IB_CACHE_LINE_SIZE = 64, 55 }; 56 57 static const u32 mlx5_ib_opcode[] = { 58 [IB_WR_SEND] = MLX5_OPCODE_SEND, 59 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM, 60 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE, 61 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM, 62 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ, 63 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS, 64 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA, 65 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL, 66 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR, 67 [IB_WR_FAST_REG_MR] = MLX5_OPCODE_UMR, 68 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS, 69 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA, 70 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR, 71 }; 72 73 74 static int is_qp0(enum ib_qp_type qp_type) 75 { 76 return qp_type == IB_QPT_SMI; 77 } 78 79 static int is_qp1(enum ib_qp_type qp_type) 80 { 81 return qp_type == IB_QPT_GSI; 82 } 83 84 static int is_sqp(enum ib_qp_type qp_type) 85 { 86 return is_qp0(qp_type) || is_qp1(qp_type); 87 } 88 89 static void *get_wqe(struct mlx5_ib_qp *qp, int offset) 90 { 91 return mlx5_buf_offset(&qp->buf, offset); 92 } 93 94 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n) 95 { 96 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift)); 97 } 98 99 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n) 100 { 101 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE)); 102 } 103 104 /** 105 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space. 106 * 107 * @qp: QP to copy from. 108 * @send: copy from the send queue when non-zero, use the receive queue 109 * otherwise. 110 * @wqe_index: index to start copying from. For send work queues, the 111 * wqe_index is in units of MLX5_SEND_WQE_BB. 112 * For receive work queue, it is the number of work queue 113 * element in the queue. 114 * @buffer: destination buffer. 115 * @length: maximum number of bytes to copy. 116 * 117 * Copies at least a single WQE, but may copy more data. 118 * 119 * Return: the number of bytes copied, or an error code. 120 */ 121 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index, 122 void *buffer, u32 length) 123 { 124 struct ib_device *ibdev = qp->ibqp.device; 125 struct mlx5_ib_dev *dev = to_mdev(ibdev); 126 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq; 127 size_t offset; 128 size_t wq_end; 129 struct ib_umem *umem = qp->umem; 130 u32 first_copy_length; 131 int wqe_length; 132 int ret; 133 134 if (wq->wqe_cnt == 0) { 135 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n", 136 qp->ibqp.qp_type); 137 return -EINVAL; 138 } 139 140 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift); 141 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift); 142 143 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg)) 144 return -EINVAL; 145 146 if (offset > umem->length || 147 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length)) 148 return -EINVAL; 149 150 first_copy_length = min_t(u32, offset + length, wq_end) - offset; 151 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length); 152 if (ret) 153 return ret; 154 155 if (send) { 156 struct mlx5_wqe_ctrl_seg *ctrl = buffer; 157 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; 158 159 wqe_length = ds * MLX5_WQE_DS_UNITS; 160 } else { 161 wqe_length = 1 << wq->wqe_shift; 162 } 163 164 if (wqe_length <= first_copy_length) 165 return first_copy_length; 166 167 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset, 168 wqe_length - first_copy_length); 169 if (ret) 170 return ret; 171 172 return wqe_length; 173 } 174 175 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type) 176 { 177 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; 178 struct ib_event event; 179 180 if (type == MLX5_EVENT_TYPE_PATH_MIG) 181 to_mibqp(qp)->port = to_mibqp(qp)->alt_port; 182 183 if (ibqp->event_handler) { 184 event.device = ibqp->device; 185 event.element.qp = ibqp; 186 switch (type) { 187 case MLX5_EVENT_TYPE_PATH_MIG: 188 event.event = IB_EVENT_PATH_MIG; 189 break; 190 case MLX5_EVENT_TYPE_COMM_EST: 191 event.event = IB_EVENT_COMM_EST; 192 break; 193 case MLX5_EVENT_TYPE_SQ_DRAINED: 194 event.event = IB_EVENT_SQ_DRAINED; 195 break; 196 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 197 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 198 break; 199 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 200 event.event = IB_EVENT_QP_FATAL; 201 break; 202 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 203 event.event = IB_EVENT_PATH_MIG_ERR; 204 break; 205 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 206 event.event = IB_EVENT_QP_REQ_ERR; 207 break; 208 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 209 event.event = IB_EVENT_QP_ACCESS_ERR; 210 break; 211 default: 212 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn); 213 return; 214 } 215 216 ibqp->event_handler(&event, ibqp->qp_context); 217 } 218 } 219 220 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap, 221 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd) 222 { 223 struct mlx5_general_caps *gen; 224 int wqe_size; 225 int wq_size; 226 227 gen = &dev->mdev->caps.gen; 228 /* Sanity check RQ size before proceeding */ 229 if (cap->max_recv_wr > gen->max_wqes) 230 return -EINVAL; 231 232 if (!has_rq) { 233 qp->rq.max_gs = 0; 234 qp->rq.wqe_cnt = 0; 235 qp->rq.wqe_shift = 0; 236 } else { 237 if (ucmd) { 238 qp->rq.wqe_cnt = ucmd->rq_wqe_count; 239 qp->rq.wqe_shift = ucmd->rq_wqe_shift; 240 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 241 qp->rq.max_post = qp->rq.wqe_cnt; 242 } else { 243 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0; 244 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg); 245 wqe_size = roundup_pow_of_two(wqe_size); 246 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size; 247 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB); 248 qp->rq.wqe_cnt = wq_size / wqe_size; 249 if (wqe_size > gen->max_rq_desc_sz) { 250 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n", 251 wqe_size, 252 gen->max_rq_desc_sz); 253 return -EINVAL; 254 } 255 qp->rq.wqe_shift = ilog2(wqe_size); 256 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 257 qp->rq.max_post = qp->rq.wqe_cnt; 258 } 259 } 260 261 return 0; 262 } 263 264 static int sq_overhead(enum ib_qp_type qp_type) 265 { 266 int size = 0; 267 268 switch (qp_type) { 269 case IB_QPT_XRC_INI: 270 size += sizeof(struct mlx5_wqe_xrc_seg); 271 /* fall through */ 272 case IB_QPT_RC: 273 size += sizeof(struct mlx5_wqe_ctrl_seg) + 274 sizeof(struct mlx5_wqe_atomic_seg) + 275 sizeof(struct mlx5_wqe_raddr_seg); 276 break; 277 278 case IB_QPT_XRC_TGT: 279 return 0; 280 281 case IB_QPT_UC: 282 size += sizeof(struct mlx5_wqe_ctrl_seg) + 283 sizeof(struct mlx5_wqe_raddr_seg) + 284 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 285 sizeof(struct mlx5_mkey_seg); 286 break; 287 288 case IB_QPT_UD: 289 case IB_QPT_SMI: 290 case IB_QPT_GSI: 291 size += sizeof(struct mlx5_wqe_ctrl_seg) + 292 sizeof(struct mlx5_wqe_datagram_seg); 293 break; 294 295 case MLX5_IB_QPT_REG_UMR: 296 size += sizeof(struct mlx5_wqe_ctrl_seg) + 297 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 298 sizeof(struct mlx5_mkey_seg); 299 break; 300 301 default: 302 return -EINVAL; 303 } 304 305 return size; 306 } 307 308 static int calc_send_wqe(struct ib_qp_init_attr *attr) 309 { 310 int inl_size = 0; 311 int size; 312 313 size = sq_overhead(attr->qp_type); 314 if (size < 0) 315 return size; 316 317 if (attr->cap.max_inline_data) { 318 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) + 319 attr->cap.max_inline_data; 320 } 321 322 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg); 323 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN && 324 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE) 325 return MLX5_SIG_WQE_SIZE; 326 else 327 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB); 328 } 329 330 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, 331 struct mlx5_ib_qp *qp) 332 { 333 struct mlx5_general_caps *gen; 334 int wqe_size; 335 int wq_size; 336 337 gen = &dev->mdev->caps.gen; 338 if (!attr->cap.max_send_wr) 339 return 0; 340 341 wqe_size = calc_send_wqe(attr); 342 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size); 343 if (wqe_size < 0) 344 return wqe_size; 345 346 if (wqe_size > gen->max_sq_desc_sz) { 347 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n", 348 wqe_size, gen->max_sq_desc_sz); 349 return -EINVAL; 350 } 351 352 qp->max_inline_data = wqe_size - sq_overhead(attr->qp_type) - 353 sizeof(struct mlx5_wqe_inline_seg); 354 attr->cap.max_inline_data = qp->max_inline_data; 355 356 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN) 357 qp->signature_en = true; 358 359 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size); 360 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB; 361 if (qp->sq.wqe_cnt > gen->max_wqes) { 362 mlx5_ib_dbg(dev, "wqe count(%d) exceeds limits(%d)\n", 363 qp->sq.wqe_cnt, gen->max_wqes); 364 return -ENOMEM; 365 } 366 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 367 qp->sq.max_gs = attr->cap.max_send_sge; 368 qp->sq.max_post = wq_size / wqe_size; 369 attr->cap.max_send_wr = qp->sq.max_post; 370 371 return wq_size; 372 } 373 374 static int set_user_buf_size(struct mlx5_ib_dev *dev, 375 struct mlx5_ib_qp *qp, 376 struct mlx5_ib_create_qp *ucmd) 377 { 378 struct mlx5_general_caps *gen; 379 int desc_sz = 1 << qp->sq.wqe_shift; 380 381 gen = &dev->mdev->caps.gen; 382 if (desc_sz > gen->max_sq_desc_sz) { 383 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n", 384 desc_sz, gen->max_sq_desc_sz); 385 return -EINVAL; 386 } 387 388 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) { 389 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n", 390 ucmd->sq_wqe_count, ucmd->sq_wqe_count); 391 return -EINVAL; 392 } 393 394 qp->sq.wqe_cnt = ucmd->sq_wqe_count; 395 396 if (qp->sq.wqe_cnt > gen->max_wqes) { 397 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n", 398 qp->sq.wqe_cnt, gen->max_wqes); 399 return -EINVAL; 400 } 401 402 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 403 (qp->sq.wqe_cnt << 6); 404 405 return 0; 406 } 407 408 static int qp_has_rq(struct ib_qp_init_attr *attr) 409 { 410 if (attr->qp_type == IB_QPT_XRC_INI || 411 attr->qp_type == IB_QPT_XRC_TGT || attr->srq || 412 attr->qp_type == MLX5_IB_QPT_REG_UMR || 413 !attr->cap.max_recv_wr) 414 return 0; 415 416 return 1; 417 } 418 419 static int first_med_uuar(void) 420 { 421 return 1; 422 } 423 424 static int next_uuar(int n) 425 { 426 n++; 427 428 while (((n % 4) & 2)) 429 n++; 430 431 return n; 432 } 433 434 static int num_med_uuar(struct mlx5_uuar_info *uuari) 435 { 436 int n; 437 438 n = uuari->num_uars * MLX5_NON_FP_BF_REGS_PER_PAGE - 439 uuari->num_low_latency_uuars - 1; 440 441 return n >= 0 ? n : 0; 442 } 443 444 static int max_uuari(struct mlx5_uuar_info *uuari) 445 { 446 return uuari->num_uars * 4; 447 } 448 449 static int first_hi_uuar(struct mlx5_uuar_info *uuari) 450 { 451 int med; 452 int i; 453 int t; 454 455 med = num_med_uuar(uuari); 456 for (t = 0, i = first_med_uuar();; i = next_uuar(i)) { 457 t++; 458 if (t == med) 459 return next_uuar(i); 460 } 461 462 return 0; 463 } 464 465 static int alloc_high_class_uuar(struct mlx5_uuar_info *uuari) 466 { 467 int i; 468 469 for (i = first_hi_uuar(uuari); i < max_uuari(uuari); i = next_uuar(i)) { 470 if (!test_bit(i, uuari->bitmap)) { 471 set_bit(i, uuari->bitmap); 472 uuari->count[i]++; 473 return i; 474 } 475 } 476 477 return -ENOMEM; 478 } 479 480 static int alloc_med_class_uuar(struct mlx5_uuar_info *uuari) 481 { 482 int minidx = first_med_uuar(); 483 int i; 484 485 for (i = first_med_uuar(); i < first_hi_uuar(uuari); i = next_uuar(i)) { 486 if (uuari->count[i] < uuari->count[minidx]) 487 minidx = i; 488 } 489 490 uuari->count[minidx]++; 491 return minidx; 492 } 493 494 static int alloc_uuar(struct mlx5_uuar_info *uuari, 495 enum mlx5_ib_latency_class lat) 496 { 497 int uuarn = -EINVAL; 498 499 mutex_lock(&uuari->lock); 500 switch (lat) { 501 case MLX5_IB_LATENCY_CLASS_LOW: 502 uuarn = 0; 503 uuari->count[uuarn]++; 504 break; 505 506 case MLX5_IB_LATENCY_CLASS_MEDIUM: 507 if (uuari->ver < 2) 508 uuarn = -ENOMEM; 509 else 510 uuarn = alloc_med_class_uuar(uuari); 511 break; 512 513 case MLX5_IB_LATENCY_CLASS_HIGH: 514 if (uuari->ver < 2) 515 uuarn = -ENOMEM; 516 else 517 uuarn = alloc_high_class_uuar(uuari); 518 break; 519 520 case MLX5_IB_LATENCY_CLASS_FAST_PATH: 521 uuarn = 2; 522 break; 523 } 524 mutex_unlock(&uuari->lock); 525 526 return uuarn; 527 } 528 529 static void free_med_class_uuar(struct mlx5_uuar_info *uuari, int uuarn) 530 { 531 clear_bit(uuarn, uuari->bitmap); 532 --uuari->count[uuarn]; 533 } 534 535 static void free_high_class_uuar(struct mlx5_uuar_info *uuari, int uuarn) 536 { 537 clear_bit(uuarn, uuari->bitmap); 538 --uuari->count[uuarn]; 539 } 540 541 static void free_uuar(struct mlx5_uuar_info *uuari, int uuarn) 542 { 543 int nuuars = uuari->num_uars * MLX5_BF_REGS_PER_PAGE; 544 int high_uuar = nuuars - uuari->num_low_latency_uuars; 545 546 mutex_lock(&uuari->lock); 547 if (uuarn == 0) { 548 --uuari->count[uuarn]; 549 goto out; 550 } 551 552 if (uuarn < high_uuar) { 553 free_med_class_uuar(uuari, uuarn); 554 goto out; 555 } 556 557 free_high_class_uuar(uuari, uuarn); 558 559 out: 560 mutex_unlock(&uuari->lock); 561 } 562 563 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state) 564 { 565 switch (state) { 566 case IB_QPS_RESET: return MLX5_QP_STATE_RST; 567 case IB_QPS_INIT: return MLX5_QP_STATE_INIT; 568 case IB_QPS_RTR: return MLX5_QP_STATE_RTR; 569 case IB_QPS_RTS: return MLX5_QP_STATE_RTS; 570 case IB_QPS_SQD: return MLX5_QP_STATE_SQD; 571 case IB_QPS_SQE: return MLX5_QP_STATE_SQER; 572 case IB_QPS_ERR: return MLX5_QP_STATE_ERR; 573 default: return -1; 574 } 575 } 576 577 static int to_mlx5_st(enum ib_qp_type type) 578 { 579 switch (type) { 580 case IB_QPT_RC: return MLX5_QP_ST_RC; 581 case IB_QPT_UC: return MLX5_QP_ST_UC; 582 case IB_QPT_UD: return MLX5_QP_ST_UD; 583 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR; 584 case IB_QPT_XRC_INI: 585 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC; 586 case IB_QPT_SMI: return MLX5_QP_ST_QP0; 587 case IB_QPT_GSI: return MLX5_QP_ST_QP1; 588 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6; 589 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE; 590 case IB_QPT_RAW_PACKET: 591 case IB_QPT_MAX: 592 default: return -EINVAL; 593 } 594 } 595 596 static int uuarn_to_uar_index(struct mlx5_uuar_info *uuari, int uuarn) 597 { 598 return uuari->uars[uuarn / MLX5_BF_REGS_PER_PAGE].index; 599 } 600 601 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 602 struct mlx5_ib_qp *qp, struct ib_udata *udata, 603 struct mlx5_create_qp_mbox_in **in, 604 struct mlx5_ib_create_qp_resp *resp, int *inlen) 605 { 606 struct mlx5_ib_ucontext *context; 607 struct mlx5_ib_create_qp ucmd; 608 int page_shift = 0; 609 int uar_index; 610 int npages; 611 u32 offset = 0; 612 int uuarn; 613 int ncont = 0; 614 int err; 615 616 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd)); 617 if (err) { 618 mlx5_ib_dbg(dev, "copy failed\n"); 619 return err; 620 } 621 622 context = to_mucontext(pd->uobject->context); 623 /* 624 * TBD: should come from the verbs when we have the API 625 */ 626 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_HIGH); 627 if (uuarn < 0) { 628 mlx5_ib_dbg(dev, "failed to allocate low latency UUAR\n"); 629 mlx5_ib_dbg(dev, "reverting to medium latency\n"); 630 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_MEDIUM); 631 if (uuarn < 0) { 632 mlx5_ib_dbg(dev, "failed to allocate medium latency UUAR\n"); 633 mlx5_ib_dbg(dev, "reverting to high latency\n"); 634 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_LOW); 635 if (uuarn < 0) { 636 mlx5_ib_warn(dev, "uuar allocation failed\n"); 637 return uuarn; 638 } 639 } 640 } 641 642 uar_index = uuarn_to_uar_index(&context->uuari, uuarn); 643 mlx5_ib_dbg(dev, "uuarn 0x%x, uar_index 0x%x\n", uuarn, uar_index); 644 645 qp->rq.offset = 0; 646 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 647 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 648 649 err = set_user_buf_size(dev, qp, &ucmd); 650 if (err) 651 goto err_uuar; 652 653 if (ucmd.buf_addr && qp->buf_size) { 654 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr, 655 qp->buf_size, 0, 0); 656 if (IS_ERR(qp->umem)) { 657 mlx5_ib_dbg(dev, "umem_get failed\n"); 658 err = PTR_ERR(qp->umem); 659 goto err_uuar; 660 } 661 } else { 662 qp->umem = NULL; 663 } 664 665 if (qp->umem) { 666 mlx5_ib_cont_pages(qp->umem, ucmd.buf_addr, &npages, &page_shift, 667 &ncont, NULL); 668 err = mlx5_ib_get_buf_offset(ucmd.buf_addr, page_shift, &offset); 669 if (err) { 670 mlx5_ib_warn(dev, "bad offset\n"); 671 goto err_umem; 672 } 673 mlx5_ib_dbg(dev, "addr 0x%llx, size %d, npages %d, page_shift %d, ncont %d, offset %d\n", 674 ucmd.buf_addr, qp->buf_size, npages, page_shift, ncont, offset); 675 } 676 677 *inlen = sizeof(**in) + sizeof(*(*in)->pas) * ncont; 678 *in = mlx5_vzalloc(*inlen); 679 if (!*in) { 680 err = -ENOMEM; 681 goto err_umem; 682 } 683 if (qp->umem) 684 mlx5_ib_populate_pas(dev, qp->umem, page_shift, (*in)->pas, 0); 685 (*in)->ctx.log_pg_sz_remote_qpn = 686 cpu_to_be32((page_shift - MLX5_ADAPTER_PAGE_SHIFT) << 24); 687 (*in)->ctx.params2 = cpu_to_be32(offset << 6); 688 689 (*in)->ctx.qp_counter_set_usr_page = cpu_to_be32(uar_index); 690 resp->uuar_index = uuarn; 691 qp->uuarn = uuarn; 692 693 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db); 694 if (err) { 695 mlx5_ib_dbg(dev, "map failed\n"); 696 goto err_free; 697 } 698 699 err = ib_copy_to_udata(udata, resp, sizeof(*resp)); 700 if (err) { 701 mlx5_ib_dbg(dev, "copy failed\n"); 702 goto err_unmap; 703 } 704 qp->create_type = MLX5_QP_USER; 705 706 return 0; 707 708 err_unmap: 709 mlx5_ib_db_unmap_user(context, &qp->db); 710 711 err_free: 712 kvfree(*in); 713 714 err_umem: 715 if (qp->umem) 716 ib_umem_release(qp->umem); 717 718 err_uuar: 719 free_uuar(&context->uuari, uuarn); 720 return err; 721 } 722 723 static void destroy_qp_user(struct ib_pd *pd, struct mlx5_ib_qp *qp) 724 { 725 struct mlx5_ib_ucontext *context; 726 727 context = to_mucontext(pd->uobject->context); 728 mlx5_ib_db_unmap_user(context, &qp->db); 729 if (qp->umem) 730 ib_umem_release(qp->umem); 731 free_uuar(&context->uuari, qp->uuarn); 732 } 733 734 static int create_kernel_qp(struct mlx5_ib_dev *dev, 735 struct ib_qp_init_attr *init_attr, 736 struct mlx5_ib_qp *qp, 737 struct mlx5_create_qp_mbox_in **in, int *inlen) 738 { 739 enum mlx5_ib_latency_class lc = MLX5_IB_LATENCY_CLASS_LOW; 740 struct mlx5_uuar_info *uuari; 741 int uar_index; 742 int uuarn; 743 int err; 744 745 uuari = &dev->mdev->priv.uuari; 746 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN | IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)) 747 return -EINVAL; 748 749 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR) 750 lc = MLX5_IB_LATENCY_CLASS_FAST_PATH; 751 752 uuarn = alloc_uuar(uuari, lc); 753 if (uuarn < 0) { 754 mlx5_ib_dbg(dev, "\n"); 755 return -ENOMEM; 756 } 757 758 qp->bf = &uuari->bfs[uuarn]; 759 uar_index = qp->bf->uar->index; 760 761 err = calc_sq_size(dev, init_attr, qp); 762 if (err < 0) { 763 mlx5_ib_dbg(dev, "err %d\n", err); 764 goto err_uuar; 765 } 766 767 qp->rq.offset = 0; 768 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 769 qp->buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift); 770 771 err = mlx5_buf_alloc(dev->mdev, qp->buf_size, PAGE_SIZE * 2, &qp->buf); 772 if (err) { 773 mlx5_ib_dbg(dev, "err %d\n", err); 774 goto err_uuar; 775 } 776 777 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt); 778 *inlen = sizeof(**in) + sizeof(*(*in)->pas) * qp->buf.npages; 779 *in = mlx5_vzalloc(*inlen); 780 if (!*in) { 781 err = -ENOMEM; 782 goto err_buf; 783 } 784 (*in)->ctx.qp_counter_set_usr_page = cpu_to_be32(uar_index); 785 (*in)->ctx.log_pg_sz_remote_qpn = 786 cpu_to_be32((qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT) << 24); 787 /* Set "fast registration enabled" for all kernel QPs */ 788 (*in)->ctx.params1 |= cpu_to_be32(1 << 11); 789 (*in)->ctx.sq_crq_size |= cpu_to_be16(1 << 4); 790 791 mlx5_fill_page_array(&qp->buf, (*in)->pas); 792 793 err = mlx5_db_alloc(dev->mdev, &qp->db); 794 if (err) { 795 mlx5_ib_dbg(dev, "err %d\n", err); 796 goto err_free; 797 } 798 799 qp->db.db[0] = 0; 800 qp->db.db[1] = 0; 801 802 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wrid), GFP_KERNEL); 803 qp->sq.wr_data = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wr_data), GFP_KERNEL); 804 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(*qp->rq.wrid), GFP_KERNEL); 805 qp->sq.w_list = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.w_list), GFP_KERNEL); 806 qp->sq.wqe_head = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wqe_head), GFP_KERNEL); 807 808 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid || 809 !qp->sq.w_list || !qp->sq.wqe_head) { 810 err = -ENOMEM; 811 goto err_wrid; 812 } 813 qp->create_type = MLX5_QP_KERNEL; 814 815 return 0; 816 817 err_wrid: 818 mlx5_db_free(dev->mdev, &qp->db); 819 kfree(qp->sq.wqe_head); 820 kfree(qp->sq.w_list); 821 kfree(qp->sq.wrid); 822 kfree(qp->sq.wr_data); 823 kfree(qp->rq.wrid); 824 825 err_free: 826 kvfree(*in); 827 828 err_buf: 829 mlx5_buf_free(dev->mdev, &qp->buf); 830 831 err_uuar: 832 free_uuar(&dev->mdev->priv.uuari, uuarn); 833 return err; 834 } 835 836 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 837 { 838 mlx5_db_free(dev->mdev, &qp->db); 839 kfree(qp->sq.wqe_head); 840 kfree(qp->sq.w_list); 841 kfree(qp->sq.wrid); 842 kfree(qp->sq.wr_data); 843 kfree(qp->rq.wrid); 844 mlx5_buf_free(dev->mdev, &qp->buf); 845 free_uuar(&dev->mdev->priv.uuari, qp->bf->uuarn); 846 } 847 848 static __be32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr) 849 { 850 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) || 851 (attr->qp_type == IB_QPT_XRC_INI)) 852 return cpu_to_be32(MLX5_SRQ_RQ); 853 else if (!qp->has_rq) 854 return cpu_to_be32(MLX5_ZERO_LEN_RQ); 855 else 856 return cpu_to_be32(MLX5_NON_ZERO_RQ); 857 } 858 859 static int is_connected(enum ib_qp_type qp_type) 860 { 861 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC) 862 return 1; 863 864 return 0; 865 } 866 867 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd, 868 struct ib_qp_init_attr *init_attr, 869 struct ib_udata *udata, struct mlx5_ib_qp *qp) 870 { 871 struct mlx5_ib_resources *devr = &dev->devr; 872 struct mlx5_ib_create_qp_resp resp; 873 struct mlx5_create_qp_mbox_in *in; 874 struct mlx5_general_caps *gen; 875 struct mlx5_ib_create_qp ucmd; 876 int inlen = sizeof(*in); 877 int err; 878 879 gen = &dev->mdev->caps.gen; 880 mutex_init(&qp->mutex); 881 spin_lock_init(&qp->sq.lock); 882 spin_lock_init(&qp->rq.lock); 883 884 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) { 885 if (!(gen->flags & MLX5_DEV_CAP_FLAG_BLOCK_MCAST)) { 886 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n"); 887 return -EINVAL; 888 } else { 889 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK; 890 } 891 } 892 893 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 894 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 895 896 if (pd && pd->uobject) { 897 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) { 898 mlx5_ib_dbg(dev, "copy failed\n"); 899 return -EFAULT; 900 } 901 902 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE); 903 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE); 904 } else { 905 qp->wq_sig = !!wq_signature; 906 } 907 908 qp->has_rq = qp_has_rq(init_attr); 909 err = set_rq_size(dev, &init_attr->cap, qp->has_rq, 910 qp, (pd && pd->uobject) ? &ucmd : NULL); 911 if (err) { 912 mlx5_ib_dbg(dev, "err %d\n", err); 913 return err; 914 } 915 916 if (pd) { 917 if (pd->uobject) { 918 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count); 919 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift || 920 ucmd.rq_wqe_count != qp->rq.wqe_cnt) { 921 mlx5_ib_dbg(dev, "invalid rq params\n"); 922 return -EINVAL; 923 } 924 if (ucmd.sq_wqe_count > gen->max_wqes) { 925 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n", 926 ucmd.sq_wqe_count, gen->max_wqes); 927 return -EINVAL; 928 } 929 err = create_user_qp(dev, pd, qp, udata, &in, &resp, &inlen); 930 if (err) 931 mlx5_ib_dbg(dev, "err %d\n", err); 932 } else { 933 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen); 934 if (err) 935 mlx5_ib_dbg(dev, "err %d\n", err); 936 else 937 qp->pa_lkey = to_mpd(pd)->pa_lkey; 938 } 939 940 if (err) 941 return err; 942 } else { 943 in = mlx5_vzalloc(sizeof(*in)); 944 if (!in) 945 return -ENOMEM; 946 947 qp->create_type = MLX5_QP_EMPTY; 948 } 949 950 if (is_sqp(init_attr->qp_type)) 951 qp->port = init_attr->port_num; 952 953 in->ctx.flags = cpu_to_be32(to_mlx5_st(init_attr->qp_type) << 16 | 954 MLX5_QP_PM_MIGRATED << 11); 955 956 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR) 957 in->ctx.flags_pd = cpu_to_be32(to_mpd(pd ? pd : devr->p0)->pdn); 958 else 959 in->ctx.flags_pd = cpu_to_be32(MLX5_QP_LAT_SENSITIVE); 960 961 if (qp->wq_sig) 962 in->ctx.flags_pd |= cpu_to_be32(MLX5_QP_ENABLE_SIG); 963 964 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 965 in->ctx.flags_pd |= cpu_to_be32(MLX5_QP_BLOCK_MCAST); 966 967 if (qp->scat_cqe && is_connected(init_attr->qp_type)) { 968 int rcqe_sz; 969 int scqe_sz; 970 971 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq); 972 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq); 973 974 if (rcqe_sz == 128) 975 in->ctx.cs_res = MLX5_RES_SCAT_DATA64_CQE; 976 else 977 in->ctx.cs_res = MLX5_RES_SCAT_DATA32_CQE; 978 979 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) { 980 if (scqe_sz == 128) 981 in->ctx.cs_req = MLX5_REQ_SCAT_DATA64_CQE; 982 else 983 in->ctx.cs_req = MLX5_REQ_SCAT_DATA32_CQE; 984 } 985 } 986 987 if (qp->rq.wqe_cnt) { 988 in->ctx.rq_size_stride = (qp->rq.wqe_shift - 4); 989 in->ctx.rq_size_stride |= ilog2(qp->rq.wqe_cnt) << 3; 990 } 991 992 in->ctx.rq_type_srqn = get_rx_type(qp, init_attr); 993 994 if (qp->sq.wqe_cnt) 995 in->ctx.sq_crq_size |= cpu_to_be16(ilog2(qp->sq.wqe_cnt) << 11); 996 else 997 in->ctx.sq_crq_size |= cpu_to_be16(0x8000); 998 999 /* Set default resources */ 1000 switch (init_attr->qp_type) { 1001 case IB_QPT_XRC_TGT: 1002 in->ctx.cqn_recv = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn); 1003 in->ctx.cqn_send = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn); 1004 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn); 1005 in->ctx.xrcd = cpu_to_be32(to_mxrcd(init_attr->xrcd)->xrcdn); 1006 break; 1007 case IB_QPT_XRC_INI: 1008 in->ctx.cqn_recv = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn); 1009 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x1)->xrcdn); 1010 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn); 1011 break; 1012 default: 1013 if (init_attr->srq) { 1014 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x0)->xrcdn); 1015 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(init_attr->srq)->msrq.srqn); 1016 } else { 1017 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x1)->xrcdn); 1018 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn); 1019 } 1020 } 1021 1022 if (init_attr->send_cq) 1023 in->ctx.cqn_send = cpu_to_be32(to_mcq(init_attr->send_cq)->mcq.cqn); 1024 1025 if (init_attr->recv_cq) 1026 in->ctx.cqn_recv = cpu_to_be32(to_mcq(init_attr->recv_cq)->mcq.cqn); 1027 1028 in->ctx.db_rec_addr = cpu_to_be64(qp->db.dma); 1029 1030 err = mlx5_core_create_qp(dev->mdev, &qp->mqp, in, inlen); 1031 if (err) { 1032 mlx5_ib_dbg(dev, "create qp failed\n"); 1033 goto err_create; 1034 } 1035 1036 kvfree(in); 1037 /* Hardware wants QPN written in big-endian order (after 1038 * shifting) for send doorbell. Precompute this value to save 1039 * a little bit when posting sends. 1040 */ 1041 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8); 1042 1043 qp->mqp.event = mlx5_ib_qp_event; 1044 1045 return 0; 1046 1047 err_create: 1048 if (qp->create_type == MLX5_QP_USER) 1049 destroy_qp_user(pd, qp); 1050 else if (qp->create_type == MLX5_QP_KERNEL) 1051 destroy_qp_kernel(dev, qp); 1052 1053 kvfree(in); 1054 return err; 1055 } 1056 1057 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 1058 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 1059 { 1060 if (send_cq) { 1061 if (recv_cq) { 1062 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1063 spin_lock_irq(&send_cq->lock); 1064 spin_lock_nested(&recv_cq->lock, 1065 SINGLE_DEPTH_NESTING); 1066 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 1067 spin_lock_irq(&send_cq->lock); 1068 __acquire(&recv_cq->lock); 1069 } else { 1070 spin_lock_irq(&recv_cq->lock); 1071 spin_lock_nested(&send_cq->lock, 1072 SINGLE_DEPTH_NESTING); 1073 } 1074 } else { 1075 spin_lock_irq(&send_cq->lock); 1076 __acquire(&recv_cq->lock); 1077 } 1078 } else if (recv_cq) { 1079 spin_lock_irq(&recv_cq->lock); 1080 __acquire(&send_cq->lock); 1081 } else { 1082 __acquire(&send_cq->lock); 1083 __acquire(&recv_cq->lock); 1084 } 1085 } 1086 1087 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 1088 __releases(&send_cq->lock) __releases(&recv_cq->lock) 1089 { 1090 if (send_cq) { 1091 if (recv_cq) { 1092 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1093 spin_unlock(&recv_cq->lock); 1094 spin_unlock_irq(&send_cq->lock); 1095 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 1096 __release(&recv_cq->lock); 1097 spin_unlock_irq(&send_cq->lock); 1098 } else { 1099 spin_unlock(&send_cq->lock); 1100 spin_unlock_irq(&recv_cq->lock); 1101 } 1102 } else { 1103 __release(&recv_cq->lock); 1104 spin_unlock_irq(&send_cq->lock); 1105 } 1106 } else if (recv_cq) { 1107 __release(&send_cq->lock); 1108 spin_unlock_irq(&recv_cq->lock); 1109 } else { 1110 __release(&recv_cq->lock); 1111 __release(&send_cq->lock); 1112 } 1113 } 1114 1115 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp) 1116 { 1117 return to_mpd(qp->ibqp.pd); 1118 } 1119 1120 static void get_cqs(struct mlx5_ib_qp *qp, 1121 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq) 1122 { 1123 switch (qp->ibqp.qp_type) { 1124 case IB_QPT_XRC_TGT: 1125 *send_cq = NULL; 1126 *recv_cq = NULL; 1127 break; 1128 case MLX5_IB_QPT_REG_UMR: 1129 case IB_QPT_XRC_INI: 1130 *send_cq = to_mcq(qp->ibqp.send_cq); 1131 *recv_cq = NULL; 1132 break; 1133 1134 case IB_QPT_SMI: 1135 case IB_QPT_GSI: 1136 case IB_QPT_RC: 1137 case IB_QPT_UC: 1138 case IB_QPT_UD: 1139 case IB_QPT_RAW_IPV6: 1140 case IB_QPT_RAW_ETHERTYPE: 1141 *send_cq = to_mcq(qp->ibqp.send_cq); 1142 *recv_cq = to_mcq(qp->ibqp.recv_cq); 1143 break; 1144 1145 case IB_QPT_RAW_PACKET: 1146 case IB_QPT_MAX: 1147 default: 1148 *send_cq = NULL; 1149 *recv_cq = NULL; 1150 break; 1151 } 1152 } 1153 1154 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1155 { 1156 struct mlx5_ib_cq *send_cq, *recv_cq; 1157 struct mlx5_modify_qp_mbox_in *in; 1158 int err; 1159 1160 in = kzalloc(sizeof(*in), GFP_KERNEL); 1161 if (!in) 1162 return; 1163 if (qp->state != IB_QPS_RESET) 1164 if (mlx5_core_qp_modify(dev->mdev, to_mlx5_state(qp->state), 1165 MLX5_QP_STATE_RST, in, sizeof(*in), &qp->mqp)) 1166 mlx5_ib_warn(dev, "mlx5_ib: modify QP %06x to RESET failed\n", 1167 qp->mqp.qpn); 1168 1169 get_cqs(qp, &send_cq, &recv_cq); 1170 1171 if (qp->create_type == MLX5_QP_KERNEL) { 1172 mlx5_ib_lock_cqs(send_cq, recv_cq); 1173 __mlx5_ib_cq_clean(recv_cq, qp->mqp.qpn, 1174 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL); 1175 if (send_cq != recv_cq) 1176 __mlx5_ib_cq_clean(send_cq, qp->mqp.qpn, NULL); 1177 mlx5_ib_unlock_cqs(send_cq, recv_cq); 1178 } 1179 1180 err = mlx5_core_destroy_qp(dev->mdev, &qp->mqp); 1181 if (err) 1182 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n", qp->mqp.qpn); 1183 kfree(in); 1184 1185 1186 if (qp->create_type == MLX5_QP_KERNEL) 1187 destroy_qp_kernel(dev, qp); 1188 else if (qp->create_type == MLX5_QP_USER) 1189 destroy_qp_user(&get_pd(qp)->ibpd, qp); 1190 } 1191 1192 static const char *ib_qp_type_str(enum ib_qp_type type) 1193 { 1194 switch (type) { 1195 case IB_QPT_SMI: 1196 return "IB_QPT_SMI"; 1197 case IB_QPT_GSI: 1198 return "IB_QPT_GSI"; 1199 case IB_QPT_RC: 1200 return "IB_QPT_RC"; 1201 case IB_QPT_UC: 1202 return "IB_QPT_UC"; 1203 case IB_QPT_UD: 1204 return "IB_QPT_UD"; 1205 case IB_QPT_RAW_IPV6: 1206 return "IB_QPT_RAW_IPV6"; 1207 case IB_QPT_RAW_ETHERTYPE: 1208 return "IB_QPT_RAW_ETHERTYPE"; 1209 case IB_QPT_XRC_INI: 1210 return "IB_QPT_XRC_INI"; 1211 case IB_QPT_XRC_TGT: 1212 return "IB_QPT_XRC_TGT"; 1213 case IB_QPT_RAW_PACKET: 1214 return "IB_QPT_RAW_PACKET"; 1215 case MLX5_IB_QPT_REG_UMR: 1216 return "MLX5_IB_QPT_REG_UMR"; 1217 case IB_QPT_MAX: 1218 default: 1219 return "Invalid QP type"; 1220 } 1221 } 1222 1223 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, 1224 struct ib_qp_init_attr *init_attr, 1225 struct ib_udata *udata) 1226 { 1227 struct mlx5_general_caps *gen; 1228 struct mlx5_ib_dev *dev; 1229 struct mlx5_ib_qp *qp; 1230 u16 xrcdn = 0; 1231 int err; 1232 1233 if (pd) { 1234 dev = to_mdev(pd->device); 1235 } else { 1236 /* being cautious here */ 1237 if (init_attr->qp_type != IB_QPT_XRC_TGT && 1238 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) { 1239 pr_warn("%s: no PD for transport %s\n", __func__, 1240 ib_qp_type_str(init_attr->qp_type)); 1241 return ERR_PTR(-EINVAL); 1242 } 1243 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device); 1244 } 1245 gen = &dev->mdev->caps.gen; 1246 1247 switch (init_attr->qp_type) { 1248 case IB_QPT_XRC_TGT: 1249 case IB_QPT_XRC_INI: 1250 if (!(gen->flags & MLX5_DEV_CAP_FLAG_XRC)) { 1251 mlx5_ib_dbg(dev, "XRC not supported\n"); 1252 return ERR_PTR(-ENOSYS); 1253 } 1254 init_attr->recv_cq = NULL; 1255 if (init_attr->qp_type == IB_QPT_XRC_TGT) { 1256 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn; 1257 init_attr->send_cq = NULL; 1258 } 1259 1260 /* fall through */ 1261 case IB_QPT_RC: 1262 case IB_QPT_UC: 1263 case IB_QPT_UD: 1264 case IB_QPT_SMI: 1265 case IB_QPT_GSI: 1266 case MLX5_IB_QPT_REG_UMR: 1267 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 1268 if (!qp) 1269 return ERR_PTR(-ENOMEM); 1270 1271 err = create_qp_common(dev, pd, init_attr, udata, qp); 1272 if (err) { 1273 mlx5_ib_dbg(dev, "create_qp_common failed\n"); 1274 kfree(qp); 1275 return ERR_PTR(err); 1276 } 1277 1278 if (is_qp0(init_attr->qp_type)) 1279 qp->ibqp.qp_num = 0; 1280 else if (is_qp1(init_attr->qp_type)) 1281 qp->ibqp.qp_num = 1; 1282 else 1283 qp->ibqp.qp_num = qp->mqp.qpn; 1284 1285 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n", 1286 qp->ibqp.qp_num, qp->mqp.qpn, to_mcq(init_attr->recv_cq)->mcq.cqn, 1287 to_mcq(init_attr->send_cq)->mcq.cqn); 1288 1289 qp->xrcdn = xrcdn; 1290 1291 break; 1292 1293 case IB_QPT_RAW_IPV6: 1294 case IB_QPT_RAW_ETHERTYPE: 1295 case IB_QPT_RAW_PACKET: 1296 case IB_QPT_MAX: 1297 default: 1298 mlx5_ib_dbg(dev, "unsupported qp type %d\n", 1299 init_attr->qp_type); 1300 /* Don't support raw QPs */ 1301 return ERR_PTR(-EINVAL); 1302 } 1303 1304 return &qp->ibqp; 1305 } 1306 1307 int mlx5_ib_destroy_qp(struct ib_qp *qp) 1308 { 1309 struct mlx5_ib_dev *dev = to_mdev(qp->device); 1310 struct mlx5_ib_qp *mqp = to_mqp(qp); 1311 1312 destroy_qp_common(dev, mqp); 1313 1314 kfree(mqp); 1315 1316 return 0; 1317 } 1318 1319 static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr, 1320 int attr_mask) 1321 { 1322 u32 hw_access_flags = 0; 1323 u8 dest_rd_atomic; 1324 u32 access_flags; 1325 1326 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 1327 dest_rd_atomic = attr->max_dest_rd_atomic; 1328 else 1329 dest_rd_atomic = qp->resp_depth; 1330 1331 if (attr_mask & IB_QP_ACCESS_FLAGS) 1332 access_flags = attr->qp_access_flags; 1333 else 1334 access_flags = qp->atomic_rd_en; 1335 1336 if (!dest_rd_atomic) 1337 access_flags &= IB_ACCESS_REMOTE_WRITE; 1338 1339 if (access_flags & IB_ACCESS_REMOTE_READ) 1340 hw_access_flags |= MLX5_QP_BIT_RRE; 1341 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) 1342 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX); 1343 if (access_flags & IB_ACCESS_REMOTE_WRITE) 1344 hw_access_flags |= MLX5_QP_BIT_RWE; 1345 1346 return cpu_to_be32(hw_access_flags); 1347 } 1348 1349 enum { 1350 MLX5_PATH_FLAG_FL = 1 << 0, 1351 MLX5_PATH_FLAG_FREE_AR = 1 << 1, 1352 MLX5_PATH_FLAG_COUNTER = 1 << 2, 1353 }; 1354 1355 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate) 1356 { 1357 struct mlx5_general_caps *gen; 1358 1359 gen = &dev->mdev->caps.gen; 1360 if (rate == IB_RATE_PORT_CURRENT) { 1361 return 0; 1362 } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) { 1363 return -EINVAL; 1364 } else { 1365 while (rate != IB_RATE_2_5_GBPS && 1366 !(1 << (rate + MLX5_STAT_RATE_OFFSET) & 1367 gen->stat_rate_support)) 1368 --rate; 1369 } 1370 1371 return rate + MLX5_STAT_RATE_OFFSET; 1372 } 1373 1374 static int mlx5_set_path(struct mlx5_ib_dev *dev, const struct ib_ah_attr *ah, 1375 struct mlx5_qp_path *path, u8 port, int attr_mask, 1376 u32 path_flags, const struct ib_qp_attr *attr) 1377 { 1378 struct mlx5_general_caps *gen; 1379 int err; 1380 1381 gen = &dev->mdev->caps.gen; 1382 path->fl = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0; 1383 path->free_ar = (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x80 : 0; 1384 1385 if (attr_mask & IB_QP_PKEY_INDEX) 1386 path->pkey_index = attr->pkey_index; 1387 1388 path->grh_mlid = ah->src_path_bits & 0x7f; 1389 path->rlid = cpu_to_be16(ah->dlid); 1390 1391 if (ah->ah_flags & IB_AH_GRH) { 1392 if (ah->grh.sgid_index >= gen->port[port - 1].gid_table_len) { 1393 pr_err(KERN_ERR "sgid_index (%u) too large. max is %d\n", 1394 ah->grh.sgid_index, gen->port[port - 1].gid_table_len); 1395 return -EINVAL; 1396 } 1397 path->grh_mlid |= 1 << 7; 1398 path->mgid_index = ah->grh.sgid_index; 1399 path->hop_limit = ah->grh.hop_limit; 1400 path->tclass_flowlabel = 1401 cpu_to_be32((ah->grh.traffic_class << 20) | 1402 (ah->grh.flow_label)); 1403 memcpy(path->rgid, ah->grh.dgid.raw, 16); 1404 } 1405 1406 err = ib_rate_to_mlx5(dev, ah->static_rate); 1407 if (err < 0) 1408 return err; 1409 path->static_rate = err; 1410 path->port = port; 1411 1412 if (attr_mask & IB_QP_TIMEOUT) 1413 path->ackto_lt = attr->timeout << 3; 1414 1415 path->sl = ah->sl & 0xf; 1416 1417 return 0; 1418 } 1419 1420 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = { 1421 [MLX5_QP_STATE_INIT] = { 1422 [MLX5_QP_STATE_INIT] = { 1423 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 1424 MLX5_QP_OPTPAR_RAE | 1425 MLX5_QP_OPTPAR_RWE | 1426 MLX5_QP_OPTPAR_PKEY_INDEX | 1427 MLX5_QP_OPTPAR_PRI_PORT, 1428 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 1429 MLX5_QP_OPTPAR_PKEY_INDEX | 1430 MLX5_QP_OPTPAR_PRI_PORT, 1431 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 1432 MLX5_QP_OPTPAR_Q_KEY | 1433 MLX5_QP_OPTPAR_PRI_PORT, 1434 }, 1435 [MLX5_QP_STATE_RTR] = { 1436 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 1437 MLX5_QP_OPTPAR_RRE | 1438 MLX5_QP_OPTPAR_RAE | 1439 MLX5_QP_OPTPAR_RWE | 1440 MLX5_QP_OPTPAR_PKEY_INDEX, 1441 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 1442 MLX5_QP_OPTPAR_RWE | 1443 MLX5_QP_OPTPAR_PKEY_INDEX, 1444 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 1445 MLX5_QP_OPTPAR_Q_KEY, 1446 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX | 1447 MLX5_QP_OPTPAR_Q_KEY, 1448 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 1449 MLX5_QP_OPTPAR_RRE | 1450 MLX5_QP_OPTPAR_RAE | 1451 MLX5_QP_OPTPAR_RWE | 1452 MLX5_QP_OPTPAR_PKEY_INDEX, 1453 }, 1454 }, 1455 [MLX5_QP_STATE_RTR] = { 1456 [MLX5_QP_STATE_RTS] = { 1457 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 1458 MLX5_QP_OPTPAR_RRE | 1459 MLX5_QP_OPTPAR_RAE | 1460 MLX5_QP_OPTPAR_RWE | 1461 MLX5_QP_OPTPAR_PM_STATE | 1462 MLX5_QP_OPTPAR_RNR_TIMEOUT, 1463 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 1464 MLX5_QP_OPTPAR_RWE | 1465 MLX5_QP_OPTPAR_PM_STATE, 1466 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 1467 }, 1468 }, 1469 [MLX5_QP_STATE_RTS] = { 1470 [MLX5_QP_STATE_RTS] = { 1471 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 1472 MLX5_QP_OPTPAR_RAE | 1473 MLX5_QP_OPTPAR_RWE | 1474 MLX5_QP_OPTPAR_RNR_TIMEOUT | 1475 MLX5_QP_OPTPAR_PM_STATE | 1476 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 1477 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 1478 MLX5_QP_OPTPAR_PM_STATE | 1479 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 1480 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY | 1481 MLX5_QP_OPTPAR_SRQN | 1482 MLX5_QP_OPTPAR_CQN_RCV, 1483 }, 1484 }, 1485 [MLX5_QP_STATE_SQER] = { 1486 [MLX5_QP_STATE_RTS] = { 1487 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 1488 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY, 1489 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE, 1490 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 1491 MLX5_QP_OPTPAR_RWE | 1492 MLX5_QP_OPTPAR_RAE | 1493 MLX5_QP_OPTPAR_RRE, 1494 }, 1495 }, 1496 }; 1497 1498 static int ib_nr_to_mlx5_nr(int ib_mask) 1499 { 1500 switch (ib_mask) { 1501 case IB_QP_STATE: 1502 return 0; 1503 case IB_QP_CUR_STATE: 1504 return 0; 1505 case IB_QP_EN_SQD_ASYNC_NOTIFY: 1506 return 0; 1507 case IB_QP_ACCESS_FLAGS: 1508 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE | 1509 MLX5_QP_OPTPAR_RAE; 1510 case IB_QP_PKEY_INDEX: 1511 return MLX5_QP_OPTPAR_PKEY_INDEX; 1512 case IB_QP_PORT: 1513 return MLX5_QP_OPTPAR_PRI_PORT; 1514 case IB_QP_QKEY: 1515 return MLX5_QP_OPTPAR_Q_KEY; 1516 case IB_QP_AV: 1517 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH | 1518 MLX5_QP_OPTPAR_PRI_PORT; 1519 case IB_QP_PATH_MTU: 1520 return 0; 1521 case IB_QP_TIMEOUT: 1522 return MLX5_QP_OPTPAR_ACK_TIMEOUT; 1523 case IB_QP_RETRY_CNT: 1524 return MLX5_QP_OPTPAR_RETRY_COUNT; 1525 case IB_QP_RNR_RETRY: 1526 return MLX5_QP_OPTPAR_RNR_RETRY; 1527 case IB_QP_RQ_PSN: 1528 return 0; 1529 case IB_QP_MAX_QP_RD_ATOMIC: 1530 return MLX5_QP_OPTPAR_SRA_MAX; 1531 case IB_QP_ALT_PATH: 1532 return MLX5_QP_OPTPAR_ALT_ADDR_PATH; 1533 case IB_QP_MIN_RNR_TIMER: 1534 return MLX5_QP_OPTPAR_RNR_TIMEOUT; 1535 case IB_QP_SQ_PSN: 1536 return 0; 1537 case IB_QP_MAX_DEST_RD_ATOMIC: 1538 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE | 1539 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE; 1540 case IB_QP_PATH_MIG_STATE: 1541 return MLX5_QP_OPTPAR_PM_STATE; 1542 case IB_QP_CAP: 1543 return 0; 1544 case IB_QP_DEST_QPN: 1545 return 0; 1546 } 1547 return 0; 1548 } 1549 1550 static int ib_mask_to_mlx5_opt(int ib_mask) 1551 { 1552 int result = 0; 1553 int i; 1554 1555 for (i = 0; i < 8 * sizeof(int); i++) { 1556 if ((1 << i) & ib_mask) 1557 result |= ib_nr_to_mlx5_nr(1 << i); 1558 } 1559 1560 return result; 1561 } 1562 1563 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp, 1564 const struct ib_qp_attr *attr, int attr_mask, 1565 enum ib_qp_state cur_state, enum ib_qp_state new_state) 1566 { 1567 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 1568 struct mlx5_ib_qp *qp = to_mqp(ibqp); 1569 struct mlx5_ib_cq *send_cq, *recv_cq; 1570 struct mlx5_qp_context *context; 1571 struct mlx5_general_caps *gen; 1572 struct mlx5_modify_qp_mbox_in *in; 1573 struct mlx5_ib_pd *pd; 1574 enum mlx5_qp_state mlx5_cur, mlx5_new; 1575 enum mlx5_qp_optpar optpar; 1576 int sqd_event; 1577 int mlx5_st; 1578 int err; 1579 1580 gen = &dev->mdev->caps.gen; 1581 in = kzalloc(sizeof(*in), GFP_KERNEL); 1582 if (!in) 1583 return -ENOMEM; 1584 1585 context = &in->ctx; 1586 err = to_mlx5_st(ibqp->qp_type); 1587 if (err < 0) 1588 goto out; 1589 1590 context->flags = cpu_to_be32(err << 16); 1591 1592 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) { 1593 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 1594 } else { 1595 switch (attr->path_mig_state) { 1596 case IB_MIG_MIGRATED: 1597 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 1598 break; 1599 case IB_MIG_REARM: 1600 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11); 1601 break; 1602 case IB_MIG_ARMED: 1603 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11); 1604 break; 1605 } 1606 } 1607 1608 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI) { 1609 context->mtu_msgmax = (IB_MTU_256 << 5) | 8; 1610 } else if (ibqp->qp_type == IB_QPT_UD || 1611 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) { 1612 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12; 1613 } else if (attr_mask & IB_QP_PATH_MTU) { 1614 if (attr->path_mtu < IB_MTU_256 || 1615 attr->path_mtu > IB_MTU_4096) { 1616 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu); 1617 err = -EINVAL; 1618 goto out; 1619 } 1620 context->mtu_msgmax = (attr->path_mtu << 5) | gen->log_max_msg; 1621 } 1622 1623 if (attr_mask & IB_QP_DEST_QPN) 1624 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num); 1625 1626 if (attr_mask & IB_QP_PKEY_INDEX) 1627 context->pri_path.pkey_index = attr->pkey_index; 1628 1629 /* todo implement counter_index functionality */ 1630 1631 if (is_sqp(ibqp->qp_type)) 1632 context->pri_path.port = qp->port; 1633 1634 if (attr_mask & IB_QP_PORT) 1635 context->pri_path.port = attr->port_num; 1636 1637 if (attr_mask & IB_QP_AV) { 1638 err = mlx5_set_path(dev, &attr->ah_attr, &context->pri_path, 1639 attr_mask & IB_QP_PORT ? attr->port_num : qp->port, 1640 attr_mask, 0, attr); 1641 if (err) 1642 goto out; 1643 } 1644 1645 if (attr_mask & IB_QP_TIMEOUT) 1646 context->pri_path.ackto_lt |= attr->timeout << 3; 1647 1648 if (attr_mask & IB_QP_ALT_PATH) { 1649 err = mlx5_set_path(dev, &attr->alt_ah_attr, &context->alt_path, 1650 attr->alt_port_num, attr_mask, 0, attr); 1651 if (err) 1652 goto out; 1653 } 1654 1655 pd = get_pd(qp); 1656 get_cqs(qp, &send_cq, &recv_cq); 1657 1658 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn); 1659 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0; 1660 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0; 1661 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28); 1662 1663 if (attr_mask & IB_QP_RNR_RETRY) 1664 context->params1 |= cpu_to_be32(attr->rnr_retry << 13); 1665 1666 if (attr_mask & IB_QP_RETRY_CNT) 1667 context->params1 |= cpu_to_be32(attr->retry_cnt << 16); 1668 1669 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 1670 if (attr->max_rd_atomic) 1671 context->params1 |= 1672 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21); 1673 } 1674 1675 if (attr_mask & IB_QP_SQ_PSN) 1676 context->next_send_psn = cpu_to_be32(attr->sq_psn); 1677 1678 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 1679 if (attr->max_dest_rd_atomic) 1680 context->params2 |= 1681 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21); 1682 } 1683 1684 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) 1685 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask); 1686 1687 if (attr_mask & IB_QP_MIN_RNR_TIMER) 1688 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24); 1689 1690 if (attr_mask & IB_QP_RQ_PSN) 1691 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn); 1692 1693 if (attr_mask & IB_QP_QKEY) 1694 context->qkey = cpu_to_be32(attr->qkey); 1695 1696 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 1697 context->db_rec_addr = cpu_to_be64(qp->db.dma); 1698 1699 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD && 1700 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify) 1701 sqd_event = 1; 1702 else 1703 sqd_event = 0; 1704 1705 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 1706 context->sq_crq_size |= cpu_to_be16(1 << 4); 1707 1708 1709 mlx5_cur = to_mlx5_state(cur_state); 1710 mlx5_new = to_mlx5_state(new_state); 1711 mlx5_st = to_mlx5_st(ibqp->qp_type); 1712 if (mlx5_st < 0) 1713 goto out; 1714 1715 optpar = ib_mask_to_mlx5_opt(attr_mask); 1716 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st]; 1717 in->optparam = cpu_to_be32(optpar); 1718 err = mlx5_core_qp_modify(dev->mdev, to_mlx5_state(cur_state), 1719 to_mlx5_state(new_state), in, sqd_event, 1720 &qp->mqp); 1721 if (err) 1722 goto out; 1723 1724 qp->state = new_state; 1725 1726 if (attr_mask & IB_QP_ACCESS_FLAGS) 1727 qp->atomic_rd_en = attr->qp_access_flags; 1728 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 1729 qp->resp_depth = attr->max_dest_rd_atomic; 1730 if (attr_mask & IB_QP_PORT) 1731 qp->port = attr->port_num; 1732 if (attr_mask & IB_QP_ALT_PATH) 1733 qp->alt_port = attr->alt_port_num; 1734 1735 /* 1736 * If we moved a kernel QP to RESET, clean up all old CQ 1737 * entries and reinitialize the QP. 1738 */ 1739 if (new_state == IB_QPS_RESET && !ibqp->uobject) { 1740 mlx5_ib_cq_clean(recv_cq, qp->mqp.qpn, 1741 ibqp->srq ? to_msrq(ibqp->srq) : NULL); 1742 if (send_cq != recv_cq) 1743 mlx5_ib_cq_clean(send_cq, qp->mqp.qpn, NULL); 1744 1745 qp->rq.head = 0; 1746 qp->rq.tail = 0; 1747 qp->sq.head = 0; 1748 qp->sq.tail = 0; 1749 qp->sq.cur_post = 0; 1750 qp->sq.last_poll = 0; 1751 qp->db.db[MLX5_RCV_DBR] = 0; 1752 qp->db.db[MLX5_SND_DBR] = 0; 1753 } 1754 1755 out: 1756 kfree(in); 1757 return err; 1758 } 1759 1760 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1761 int attr_mask, struct ib_udata *udata) 1762 { 1763 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 1764 struct mlx5_ib_qp *qp = to_mqp(ibqp); 1765 enum ib_qp_state cur_state, new_state; 1766 struct mlx5_general_caps *gen; 1767 int err = -EINVAL; 1768 int port; 1769 1770 gen = &dev->mdev->caps.gen; 1771 mutex_lock(&qp->mutex); 1772 1773 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; 1774 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 1775 1776 if (ibqp->qp_type != MLX5_IB_QPT_REG_UMR && 1777 !ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask, 1778 IB_LINK_LAYER_UNSPECIFIED)) 1779 goto out; 1780 1781 if ((attr_mask & IB_QP_PORT) && 1782 (attr->port_num == 0 || attr->port_num > gen->num_ports)) 1783 goto out; 1784 1785 if (attr_mask & IB_QP_PKEY_INDEX) { 1786 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 1787 if (attr->pkey_index >= gen->port[port - 1].pkey_table_len) 1788 goto out; 1789 } 1790 1791 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 1792 attr->max_rd_atomic > (1 << gen->log_max_ra_res_qp)) 1793 goto out; 1794 1795 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 1796 attr->max_dest_rd_atomic > (1 << gen->log_max_ra_req_qp)) 1797 goto out; 1798 1799 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 1800 err = 0; 1801 goto out; 1802 } 1803 1804 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state); 1805 1806 out: 1807 mutex_unlock(&qp->mutex); 1808 return err; 1809 } 1810 1811 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq) 1812 { 1813 struct mlx5_ib_cq *cq; 1814 unsigned cur; 1815 1816 cur = wq->head - wq->tail; 1817 if (likely(cur + nreq < wq->max_post)) 1818 return 0; 1819 1820 cq = to_mcq(ib_cq); 1821 spin_lock(&cq->lock); 1822 cur = wq->head - wq->tail; 1823 spin_unlock(&cq->lock); 1824 1825 return cur + nreq >= wq->max_post; 1826 } 1827 1828 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg, 1829 u64 remote_addr, u32 rkey) 1830 { 1831 rseg->raddr = cpu_to_be64(remote_addr); 1832 rseg->rkey = cpu_to_be32(rkey); 1833 rseg->reserved = 0; 1834 } 1835 1836 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg, 1837 struct ib_send_wr *wr) 1838 { 1839 memcpy(&dseg->av, &to_mah(wr->wr.ud.ah)->av, sizeof(struct mlx5_av)); 1840 dseg->av.dqp_dct = cpu_to_be32(wr->wr.ud.remote_qpn | MLX5_EXTENDED_UD_AV); 1841 dseg->av.key.qkey.qkey = cpu_to_be32(wr->wr.ud.remote_qkey); 1842 } 1843 1844 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg) 1845 { 1846 dseg->byte_count = cpu_to_be32(sg->length); 1847 dseg->lkey = cpu_to_be32(sg->lkey); 1848 dseg->addr = cpu_to_be64(sg->addr); 1849 } 1850 1851 static __be16 get_klm_octo(int npages) 1852 { 1853 return cpu_to_be16(ALIGN(npages, 8) / 2); 1854 } 1855 1856 static __be64 frwr_mkey_mask(void) 1857 { 1858 u64 result; 1859 1860 result = MLX5_MKEY_MASK_LEN | 1861 MLX5_MKEY_MASK_PAGE_SIZE | 1862 MLX5_MKEY_MASK_START_ADDR | 1863 MLX5_MKEY_MASK_EN_RINVAL | 1864 MLX5_MKEY_MASK_KEY | 1865 MLX5_MKEY_MASK_LR | 1866 MLX5_MKEY_MASK_LW | 1867 MLX5_MKEY_MASK_RR | 1868 MLX5_MKEY_MASK_RW | 1869 MLX5_MKEY_MASK_A | 1870 MLX5_MKEY_MASK_SMALL_FENCE | 1871 MLX5_MKEY_MASK_FREE; 1872 1873 return cpu_to_be64(result); 1874 } 1875 1876 static __be64 sig_mkey_mask(void) 1877 { 1878 u64 result; 1879 1880 result = MLX5_MKEY_MASK_LEN | 1881 MLX5_MKEY_MASK_PAGE_SIZE | 1882 MLX5_MKEY_MASK_START_ADDR | 1883 MLX5_MKEY_MASK_EN_SIGERR | 1884 MLX5_MKEY_MASK_EN_RINVAL | 1885 MLX5_MKEY_MASK_KEY | 1886 MLX5_MKEY_MASK_LR | 1887 MLX5_MKEY_MASK_LW | 1888 MLX5_MKEY_MASK_RR | 1889 MLX5_MKEY_MASK_RW | 1890 MLX5_MKEY_MASK_SMALL_FENCE | 1891 MLX5_MKEY_MASK_FREE | 1892 MLX5_MKEY_MASK_BSF_EN; 1893 1894 return cpu_to_be64(result); 1895 } 1896 1897 static void set_frwr_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, 1898 struct ib_send_wr *wr, int li) 1899 { 1900 memset(umr, 0, sizeof(*umr)); 1901 1902 if (li) { 1903 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE); 1904 umr->flags = 1 << 7; 1905 return; 1906 } 1907 1908 umr->flags = (1 << 5); /* fail if not free */ 1909 umr->klm_octowords = get_klm_octo(wr->wr.fast_reg.page_list_len); 1910 umr->mkey_mask = frwr_mkey_mask(); 1911 } 1912 1913 static __be64 get_umr_reg_mr_mask(void) 1914 { 1915 u64 result; 1916 1917 result = MLX5_MKEY_MASK_LEN | 1918 MLX5_MKEY_MASK_PAGE_SIZE | 1919 MLX5_MKEY_MASK_START_ADDR | 1920 MLX5_MKEY_MASK_PD | 1921 MLX5_MKEY_MASK_LR | 1922 MLX5_MKEY_MASK_LW | 1923 MLX5_MKEY_MASK_KEY | 1924 MLX5_MKEY_MASK_RR | 1925 MLX5_MKEY_MASK_RW | 1926 MLX5_MKEY_MASK_A | 1927 MLX5_MKEY_MASK_FREE; 1928 1929 return cpu_to_be64(result); 1930 } 1931 1932 static __be64 get_umr_unreg_mr_mask(void) 1933 { 1934 u64 result; 1935 1936 result = MLX5_MKEY_MASK_FREE; 1937 1938 return cpu_to_be64(result); 1939 } 1940 1941 static __be64 get_umr_update_mtt_mask(void) 1942 { 1943 u64 result; 1944 1945 result = MLX5_MKEY_MASK_FREE; 1946 1947 return cpu_to_be64(result); 1948 } 1949 1950 static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, 1951 struct ib_send_wr *wr) 1952 { 1953 struct mlx5_umr_wr *umrwr = (struct mlx5_umr_wr *)&wr->wr.fast_reg; 1954 1955 memset(umr, 0, sizeof(*umr)); 1956 1957 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE) 1958 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */ 1959 else 1960 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */ 1961 1962 if (!(wr->send_flags & MLX5_IB_SEND_UMR_UNREG)) { 1963 umr->klm_octowords = get_klm_octo(umrwr->npages); 1964 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT) { 1965 umr->mkey_mask = get_umr_update_mtt_mask(); 1966 umr->bsf_octowords = get_klm_octo(umrwr->target.offset); 1967 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN; 1968 } else { 1969 umr->mkey_mask = get_umr_reg_mr_mask(); 1970 } 1971 } else { 1972 umr->mkey_mask = get_umr_unreg_mr_mask(); 1973 } 1974 1975 if (!wr->num_sge) 1976 umr->flags |= MLX5_UMR_INLINE; 1977 } 1978 1979 static u8 get_umr_flags(int acc) 1980 { 1981 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | 1982 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | 1983 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | 1984 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | 1985 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN; 1986 } 1987 1988 static void set_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr, 1989 int li, int *writ) 1990 { 1991 memset(seg, 0, sizeof(*seg)); 1992 if (li) { 1993 seg->status = MLX5_MKEY_STATUS_FREE; 1994 return; 1995 } 1996 1997 seg->flags = get_umr_flags(wr->wr.fast_reg.access_flags) | 1998 MLX5_ACCESS_MODE_MTT; 1999 *writ = seg->flags & (MLX5_PERM_LOCAL_WRITE | IB_ACCESS_REMOTE_WRITE); 2000 seg->qpn_mkey7_0 = cpu_to_be32((wr->wr.fast_reg.rkey & 0xff) | 0xffffff00); 2001 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL); 2002 seg->start_addr = cpu_to_be64(wr->wr.fast_reg.iova_start); 2003 seg->len = cpu_to_be64(wr->wr.fast_reg.length); 2004 seg->xlt_oct_size = cpu_to_be32((wr->wr.fast_reg.page_list_len + 1) / 2); 2005 seg->log2_page_size = wr->wr.fast_reg.page_shift; 2006 } 2007 2008 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr) 2009 { 2010 struct mlx5_umr_wr *umrwr = (struct mlx5_umr_wr *)&wr->wr.fast_reg; 2011 2012 memset(seg, 0, sizeof(*seg)); 2013 if (wr->send_flags & MLX5_IB_SEND_UMR_UNREG) { 2014 seg->status = MLX5_MKEY_STATUS_FREE; 2015 return; 2016 } 2017 2018 seg->flags = convert_access(umrwr->access_flags); 2019 if (!(wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT)) { 2020 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn); 2021 seg->start_addr = cpu_to_be64(umrwr->target.virt_addr); 2022 } 2023 seg->len = cpu_to_be64(umrwr->length); 2024 seg->log2_page_size = umrwr->page_shift; 2025 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 | 2026 mlx5_mkey_variant(umrwr->mkey)); 2027 } 2028 2029 static void set_frwr_pages(struct mlx5_wqe_data_seg *dseg, 2030 struct ib_send_wr *wr, 2031 struct mlx5_core_dev *mdev, 2032 struct mlx5_ib_pd *pd, 2033 int writ) 2034 { 2035 struct mlx5_ib_fast_reg_page_list *mfrpl = to_mfrpl(wr->wr.fast_reg.page_list); 2036 u64 *page_list = wr->wr.fast_reg.page_list->page_list; 2037 u64 perm = MLX5_EN_RD | (writ ? MLX5_EN_WR : 0); 2038 int i; 2039 2040 for (i = 0; i < wr->wr.fast_reg.page_list_len; i++) 2041 mfrpl->mapped_page_list[i] = cpu_to_be64(page_list[i] | perm); 2042 dseg->addr = cpu_to_be64(mfrpl->map); 2043 dseg->byte_count = cpu_to_be32(ALIGN(sizeof(u64) * wr->wr.fast_reg.page_list_len, 64)); 2044 dseg->lkey = cpu_to_be32(pd->pa_lkey); 2045 } 2046 2047 static __be32 send_ieth(struct ib_send_wr *wr) 2048 { 2049 switch (wr->opcode) { 2050 case IB_WR_SEND_WITH_IMM: 2051 case IB_WR_RDMA_WRITE_WITH_IMM: 2052 return wr->ex.imm_data; 2053 2054 case IB_WR_SEND_WITH_INV: 2055 return cpu_to_be32(wr->ex.invalidate_rkey); 2056 2057 default: 2058 return 0; 2059 } 2060 } 2061 2062 static u8 calc_sig(void *wqe, int size) 2063 { 2064 u8 *p = wqe; 2065 u8 res = 0; 2066 int i; 2067 2068 for (i = 0; i < size; i++) 2069 res ^= p[i]; 2070 2071 return ~res; 2072 } 2073 2074 static u8 wq_sig(void *wqe) 2075 { 2076 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4); 2077 } 2078 2079 static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr, 2080 void *wqe, int *sz) 2081 { 2082 struct mlx5_wqe_inline_seg *seg; 2083 void *qend = qp->sq.qend; 2084 void *addr; 2085 int inl = 0; 2086 int copy; 2087 int len; 2088 int i; 2089 2090 seg = wqe; 2091 wqe += sizeof(*seg); 2092 for (i = 0; i < wr->num_sge; i++) { 2093 addr = (void *)(unsigned long)(wr->sg_list[i].addr); 2094 len = wr->sg_list[i].length; 2095 inl += len; 2096 2097 if (unlikely(inl > qp->max_inline_data)) 2098 return -ENOMEM; 2099 2100 if (unlikely(wqe + len > qend)) { 2101 copy = qend - wqe; 2102 memcpy(wqe, addr, copy); 2103 addr += copy; 2104 len -= copy; 2105 wqe = mlx5_get_send_wqe(qp, 0); 2106 } 2107 memcpy(wqe, addr, len); 2108 wqe += len; 2109 } 2110 2111 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG); 2112 2113 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16; 2114 2115 return 0; 2116 } 2117 2118 static u16 prot_field_size(enum ib_signature_type type) 2119 { 2120 switch (type) { 2121 case IB_SIG_TYPE_T10_DIF: 2122 return MLX5_DIF_SIZE; 2123 default: 2124 return 0; 2125 } 2126 } 2127 2128 static u8 bs_selector(int block_size) 2129 { 2130 switch (block_size) { 2131 case 512: return 0x1; 2132 case 520: return 0x2; 2133 case 4096: return 0x3; 2134 case 4160: return 0x4; 2135 case 1073741824: return 0x5; 2136 default: return 0; 2137 } 2138 } 2139 2140 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain, 2141 struct mlx5_bsf_inl *inl) 2142 { 2143 /* Valid inline section and allow BSF refresh */ 2144 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID | 2145 MLX5_BSF_REFRESH_DIF); 2146 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag); 2147 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag); 2148 /* repeating block */ 2149 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK; 2150 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ? 2151 MLX5_DIF_CRC : MLX5_DIF_IPCS; 2152 2153 if (domain->sig.dif.ref_remap) 2154 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG; 2155 2156 if (domain->sig.dif.app_escape) { 2157 if (domain->sig.dif.ref_escape) 2158 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE; 2159 else 2160 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE; 2161 } 2162 2163 inl->dif_app_bitmask_check = 2164 cpu_to_be16(domain->sig.dif.apptag_check_mask); 2165 } 2166 2167 static int mlx5_set_bsf(struct ib_mr *sig_mr, 2168 struct ib_sig_attrs *sig_attrs, 2169 struct mlx5_bsf *bsf, u32 data_size) 2170 { 2171 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig; 2172 struct mlx5_bsf_basic *basic = &bsf->basic; 2173 struct ib_sig_domain *mem = &sig_attrs->mem; 2174 struct ib_sig_domain *wire = &sig_attrs->wire; 2175 2176 memset(bsf, 0, sizeof(*bsf)); 2177 2178 /* Basic + Extended + Inline */ 2179 basic->bsf_size_sbs = 1 << 7; 2180 /* Input domain check byte mask */ 2181 basic->check_byte_mask = sig_attrs->check_mask; 2182 basic->raw_data_size = cpu_to_be32(data_size); 2183 2184 /* Memory domain */ 2185 switch (sig_attrs->mem.sig_type) { 2186 case IB_SIG_TYPE_NONE: 2187 break; 2188 case IB_SIG_TYPE_T10_DIF: 2189 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval); 2190 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx); 2191 mlx5_fill_inl_bsf(mem, &bsf->m_inl); 2192 break; 2193 default: 2194 return -EINVAL; 2195 } 2196 2197 /* Wire domain */ 2198 switch (sig_attrs->wire.sig_type) { 2199 case IB_SIG_TYPE_NONE: 2200 break; 2201 case IB_SIG_TYPE_T10_DIF: 2202 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval && 2203 mem->sig_type == wire->sig_type) { 2204 /* Same block structure */ 2205 basic->bsf_size_sbs |= 1 << 4; 2206 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type) 2207 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK; 2208 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag) 2209 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK; 2210 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag) 2211 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK; 2212 } else 2213 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval); 2214 2215 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx); 2216 mlx5_fill_inl_bsf(wire, &bsf->w_inl); 2217 break; 2218 default: 2219 return -EINVAL; 2220 } 2221 2222 return 0; 2223 } 2224 2225 static int set_sig_data_segment(struct ib_send_wr *wr, struct mlx5_ib_qp *qp, 2226 void **seg, int *size) 2227 { 2228 struct ib_sig_attrs *sig_attrs = wr->wr.sig_handover.sig_attrs; 2229 struct ib_mr *sig_mr = wr->wr.sig_handover.sig_mr; 2230 struct mlx5_bsf *bsf; 2231 u32 data_len = wr->sg_list->length; 2232 u32 data_key = wr->sg_list->lkey; 2233 u64 data_va = wr->sg_list->addr; 2234 int ret; 2235 int wqe_size; 2236 2237 if (!wr->wr.sig_handover.prot || 2238 (data_key == wr->wr.sig_handover.prot->lkey && 2239 data_va == wr->wr.sig_handover.prot->addr && 2240 data_len == wr->wr.sig_handover.prot->length)) { 2241 /** 2242 * Source domain doesn't contain signature information 2243 * or data and protection are interleaved in memory. 2244 * So need construct: 2245 * ------------------ 2246 * | data_klm | 2247 * ------------------ 2248 * | BSF | 2249 * ------------------ 2250 **/ 2251 struct mlx5_klm *data_klm = *seg; 2252 2253 data_klm->bcount = cpu_to_be32(data_len); 2254 data_klm->key = cpu_to_be32(data_key); 2255 data_klm->va = cpu_to_be64(data_va); 2256 wqe_size = ALIGN(sizeof(*data_klm), 64); 2257 } else { 2258 /** 2259 * Source domain contains signature information 2260 * So need construct a strided block format: 2261 * --------------------------- 2262 * | stride_block_ctrl | 2263 * --------------------------- 2264 * | data_klm | 2265 * --------------------------- 2266 * | prot_klm | 2267 * --------------------------- 2268 * | BSF | 2269 * --------------------------- 2270 **/ 2271 struct mlx5_stride_block_ctrl_seg *sblock_ctrl; 2272 struct mlx5_stride_block_entry *data_sentry; 2273 struct mlx5_stride_block_entry *prot_sentry; 2274 u32 prot_key = wr->wr.sig_handover.prot->lkey; 2275 u64 prot_va = wr->wr.sig_handover.prot->addr; 2276 u16 block_size = sig_attrs->mem.sig.dif.pi_interval; 2277 int prot_size; 2278 2279 sblock_ctrl = *seg; 2280 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl); 2281 prot_sentry = (void *)data_sentry + sizeof(*data_sentry); 2282 2283 prot_size = prot_field_size(sig_attrs->mem.sig_type); 2284 if (!prot_size) { 2285 pr_err("Bad block size given: %u\n", block_size); 2286 return -EINVAL; 2287 } 2288 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size + 2289 prot_size); 2290 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP); 2291 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size); 2292 sblock_ctrl->num_entries = cpu_to_be16(2); 2293 2294 data_sentry->bcount = cpu_to_be16(block_size); 2295 data_sentry->key = cpu_to_be32(data_key); 2296 data_sentry->va = cpu_to_be64(data_va); 2297 data_sentry->stride = cpu_to_be16(block_size); 2298 2299 prot_sentry->bcount = cpu_to_be16(prot_size); 2300 prot_sentry->key = cpu_to_be32(prot_key); 2301 prot_sentry->va = cpu_to_be64(prot_va); 2302 prot_sentry->stride = cpu_to_be16(prot_size); 2303 2304 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) + 2305 sizeof(*prot_sentry), 64); 2306 } 2307 2308 *seg += wqe_size; 2309 *size += wqe_size / 16; 2310 if (unlikely((*seg == qp->sq.qend))) 2311 *seg = mlx5_get_send_wqe(qp, 0); 2312 2313 bsf = *seg; 2314 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len); 2315 if (ret) 2316 return -EINVAL; 2317 2318 *seg += sizeof(*bsf); 2319 *size += sizeof(*bsf) / 16; 2320 if (unlikely((*seg == qp->sq.qend))) 2321 *seg = mlx5_get_send_wqe(qp, 0); 2322 2323 return 0; 2324 } 2325 2326 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg, 2327 struct ib_send_wr *wr, u32 nelements, 2328 u32 length, u32 pdn) 2329 { 2330 struct ib_mr *sig_mr = wr->wr.sig_handover.sig_mr; 2331 u32 sig_key = sig_mr->rkey; 2332 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1; 2333 2334 memset(seg, 0, sizeof(*seg)); 2335 2336 seg->flags = get_umr_flags(wr->wr.sig_handover.access_flags) | 2337 MLX5_ACCESS_MODE_KLM; 2338 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00); 2339 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 | 2340 MLX5_MKEY_BSF_EN | pdn); 2341 seg->len = cpu_to_be64(length); 2342 seg->xlt_oct_size = cpu_to_be32(be16_to_cpu(get_klm_octo(nelements))); 2343 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE); 2344 } 2345 2346 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, 2347 struct ib_send_wr *wr, u32 nelements) 2348 { 2349 memset(umr, 0, sizeof(*umr)); 2350 2351 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE; 2352 umr->klm_octowords = get_klm_octo(nelements); 2353 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE); 2354 umr->mkey_mask = sig_mkey_mask(); 2355 } 2356 2357 2358 static int set_sig_umr_wr(struct ib_send_wr *wr, struct mlx5_ib_qp *qp, 2359 void **seg, int *size) 2360 { 2361 struct mlx5_ib_mr *sig_mr = to_mmr(wr->wr.sig_handover.sig_mr); 2362 u32 pdn = get_pd(qp)->pdn; 2363 u32 klm_oct_size; 2364 int region_len, ret; 2365 2366 if (unlikely(wr->num_sge != 1) || 2367 unlikely(wr->wr.sig_handover.access_flags & 2368 IB_ACCESS_REMOTE_ATOMIC) || 2369 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) || 2370 unlikely(!sig_mr->sig->sig_status_checked)) 2371 return -EINVAL; 2372 2373 /* length of the protected region, data + protection */ 2374 region_len = wr->sg_list->length; 2375 if (wr->wr.sig_handover.prot && 2376 (wr->wr.sig_handover.prot->lkey != wr->sg_list->lkey || 2377 wr->wr.sig_handover.prot->addr != wr->sg_list->addr || 2378 wr->wr.sig_handover.prot->length != wr->sg_list->length)) 2379 region_len += wr->wr.sig_handover.prot->length; 2380 2381 /** 2382 * KLM octoword size - if protection was provided 2383 * then we use strided block format (3 octowords), 2384 * else we use single KLM (1 octoword) 2385 **/ 2386 klm_oct_size = wr->wr.sig_handover.prot ? 3 : 1; 2387 2388 set_sig_umr_segment(*seg, wr, klm_oct_size); 2389 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 2390 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 2391 if (unlikely((*seg == qp->sq.qend))) 2392 *seg = mlx5_get_send_wqe(qp, 0); 2393 2394 set_sig_mkey_segment(*seg, wr, klm_oct_size, region_len, pdn); 2395 *seg += sizeof(struct mlx5_mkey_seg); 2396 *size += sizeof(struct mlx5_mkey_seg) / 16; 2397 if (unlikely((*seg == qp->sq.qend))) 2398 *seg = mlx5_get_send_wqe(qp, 0); 2399 2400 ret = set_sig_data_segment(wr, qp, seg, size); 2401 if (ret) 2402 return ret; 2403 2404 sig_mr->sig->sig_status_checked = false; 2405 return 0; 2406 } 2407 2408 static int set_psv_wr(struct ib_sig_domain *domain, 2409 u32 psv_idx, void **seg, int *size) 2410 { 2411 struct mlx5_seg_set_psv *psv_seg = *seg; 2412 2413 memset(psv_seg, 0, sizeof(*psv_seg)); 2414 psv_seg->psv_num = cpu_to_be32(psv_idx); 2415 switch (domain->sig_type) { 2416 case IB_SIG_TYPE_NONE: 2417 break; 2418 case IB_SIG_TYPE_T10_DIF: 2419 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 | 2420 domain->sig.dif.app_tag); 2421 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag); 2422 break; 2423 default: 2424 pr_err("Bad signature type given.\n"); 2425 return 1; 2426 } 2427 2428 *seg += sizeof(*psv_seg); 2429 *size += sizeof(*psv_seg) / 16; 2430 2431 return 0; 2432 } 2433 2434 static int set_frwr_li_wr(void **seg, struct ib_send_wr *wr, int *size, 2435 struct mlx5_core_dev *mdev, struct mlx5_ib_pd *pd, struct mlx5_ib_qp *qp) 2436 { 2437 int writ = 0; 2438 int li; 2439 2440 li = wr->opcode == IB_WR_LOCAL_INV ? 1 : 0; 2441 if (unlikely(wr->send_flags & IB_SEND_INLINE)) 2442 return -EINVAL; 2443 2444 set_frwr_umr_segment(*seg, wr, li); 2445 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 2446 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 2447 if (unlikely((*seg == qp->sq.qend))) 2448 *seg = mlx5_get_send_wqe(qp, 0); 2449 set_mkey_segment(*seg, wr, li, &writ); 2450 *seg += sizeof(struct mlx5_mkey_seg); 2451 *size += sizeof(struct mlx5_mkey_seg) / 16; 2452 if (unlikely((*seg == qp->sq.qend))) 2453 *seg = mlx5_get_send_wqe(qp, 0); 2454 if (!li) { 2455 if (unlikely(wr->wr.fast_reg.page_list_len > 2456 wr->wr.fast_reg.page_list->max_page_list_len)) 2457 return -ENOMEM; 2458 2459 set_frwr_pages(*seg, wr, mdev, pd, writ); 2460 *seg += sizeof(struct mlx5_wqe_data_seg); 2461 *size += (sizeof(struct mlx5_wqe_data_seg) / 16); 2462 } 2463 return 0; 2464 } 2465 2466 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16) 2467 { 2468 __be32 *p = NULL; 2469 int tidx = idx; 2470 int i, j; 2471 2472 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx)); 2473 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) { 2474 if ((i & 0xf) == 0) { 2475 void *buf = mlx5_get_send_wqe(qp, tidx); 2476 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1); 2477 p = buf; 2478 j = 0; 2479 } 2480 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]), 2481 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]), 2482 be32_to_cpu(p[j + 3])); 2483 } 2484 } 2485 2486 static void mlx5_bf_copy(u64 __iomem *dst, u64 *src, 2487 unsigned bytecnt, struct mlx5_ib_qp *qp) 2488 { 2489 while (bytecnt > 0) { 2490 __iowrite64_copy(dst++, src++, 8); 2491 __iowrite64_copy(dst++, src++, 8); 2492 __iowrite64_copy(dst++, src++, 8); 2493 __iowrite64_copy(dst++, src++, 8); 2494 __iowrite64_copy(dst++, src++, 8); 2495 __iowrite64_copy(dst++, src++, 8); 2496 __iowrite64_copy(dst++, src++, 8); 2497 __iowrite64_copy(dst++, src++, 8); 2498 bytecnt -= 64; 2499 if (unlikely(src == qp->sq.qend)) 2500 src = mlx5_get_send_wqe(qp, 0); 2501 } 2502 } 2503 2504 static u8 get_fence(u8 fence, struct ib_send_wr *wr) 2505 { 2506 if (unlikely(wr->opcode == IB_WR_LOCAL_INV && 2507 wr->send_flags & IB_SEND_FENCE)) 2508 return MLX5_FENCE_MODE_STRONG_ORDERING; 2509 2510 if (unlikely(fence)) { 2511 if (wr->send_flags & IB_SEND_FENCE) 2512 return MLX5_FENCE_MODE_SMALL_AND_FENCE; 2513 else 2514 return fence; 2515 2516 } else { 2517 return 0; 2518 } 2519 } 2520 2521 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg, 2522 struct mlx5_wqe_ctrl_seg **ctrl, 2523 struct ib_send_wr *wr, unsigned *idx, 2524 int *size, int nreq) 2525 { 2526 int err = 0; 2527 2528 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq))) { 2529 err = -ENOMEM; 2530 return err; 2531 } 2532 2533 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1); 2534 *seg = mlx5_get_send_wqe(qp, *idx); 2535 *ctrl = *seg; 2536 *(uint32_t *)(*seg + 8) = 0; 2537 (*ctrl)->imm = send_ieth(wr); 2538 (*ctrl)->fm_ce_se = qp->sq_signal_bits | 2539 (wr->send_flags & IB_SEND_SIGNALED ? 2540 MLX5_WQE_CTRL_CQ_UPDATE : 0) | 2541 (wr->send_flags & IB_SEND_SOLICITED ? 2542 MLX5_WQE_CTRL_SOLICITED : 0); 2543 2544 *seg += sizeof(**ctrl); 2545 *size = sizeof(**ctrl) / 16; 2546 2547 return err; 2548 } 2549 2550 static void finish_wqe(struct mlx5_ib_qp *qp, 2551 struct mlx5_wqe_ctrl_seg *ctrl, 2552 u8 size, unsigned idx, u64 wr_id, 2553 int nreq, u8 fence, u8 next_fence, 2554 u32 mlx5_opcode) 2555 { 2556 u8 opmod = 0; 2557 2558 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) | 2559 mlx5_opcode | ((u32)opmod << 24)); 2560 ctrl->qpn_ds = cpu_to_be32(size | (qp->mqp.qpn << 8)); 2561 ctrl->fm_ce_se |= fence; 2562 qp->fm_cache = next_fence; 2563 if (unlikely(qp->wq_sig)) 2564 ctrl->signature = wq_sig(ctrl); 2565 2566 qp->sq.wrid[idx] = wr_id; 2567 qp->sq.w_list[idx].opcode = mlx5_opcode; 2568 qp->sq.wqe_head[idx] = qp->sq.head + nreq; 2569 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB); 2570 qp->sq.w_list[idx].next = qp->sq.cur_post; 2571 } 2572 2573 2574 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 2575 struct ib_send_wr **bad_wr) 2576 { 2577 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */ 2578 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2579 struct mlx5_core_dev *mdev = dev->mdev; 2580 struct mlx5_ib_qp *qp = to_mqp(ibqp); 2581 struct mlx5_ib_mr *mr; 2582 struct mlx5_wqe_data_seg *dpseg; 2583 struct mlx5_wqe_xrc_seg *xrc; 2584 struct mlx5_bf *bf = qp->bf; 2585 int uninitialized_var(size); 2586 void *qend = qp->sq.qend; 2587 unsigned long flags; 2588 unsigned idx; 2589 int err = 0; 2590 int inl = 0; 2591 int num_sge; 2592 void *seg; 2593 int nreq; 2594 int i; 2595 u8 next_fence = 0; 2596 u8 fence; 2597 2598 spin_lock_irqsave(&qp->sq.lock, flags); 2599 2600 for (nreq = 0; wr; nreq++, wr = wr->next) { 2601 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) { 2602 mlx5_ib_warn(dev, "\n"); 2603 err = -EINVAL; 2604 *bad_wr = wr; 2605 goto out; 2606 } 2607 2608 fence = qp->fm_cache; 2609 num_sge = wr->num_sge; 2610 if (unlikely(num_sge > qp->sq.max_gs)) { 2611 mlx5_ib_warn(dev, "\n"); 2612 err = -ENOMEM; 2613 *bad_wr = wr; 2614 goto out; 2615 } 2616 2617 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq); 2618 if (err) { 2619 mlx5_ib_warn(dev, "\n"); 2620 err = -ENOMEM; 2621 *bad_wr = wr; 2622 goto out; 2623 } 2624 2625 switch (ibqp->qp_type) { 2626 case IB_QPT_XRC_INI: 2627 xrc = seg; 2628 xrc->xrc_srqn = htonl(wr->xrc_remote_srq_num); 2629 seg += sizeof(*xrc); 2630 size += sizeof(*xrc) / 16; 2631 /* fall through */ 2632 case IB_QPT_RC: 2633 switch (wr->opcode) { 2634 case IB_WR_RDMA_READ: 2635 case IB_WR_RDMA_WRITE: 2636 case IB_WR_RDMA_WRITE_WITH_IMM: 2637 set_raddr_seg(seg, wr->wr.rdma.remote_addr, 2638 wr->wr.rdma.rkey); 2639 seg += sizeof(struct mlx5_wqe_raddr_seg); 2640 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 2641 break; 2642 2643 case IB_WR_ATOMIC_CMP_AND_SWP: 2644 case IB_WR_ATOMIC_FETCH_AND_ADD: 2645 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP: 2646 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n"); 2647 err = -ENOSYS; 2648 *bad_wr = wr; 2649 goto out; 2650 2651 case IB_WR_LOCAL_INV: 2652 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 2653 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV; 2654 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey); 2655 err = set_frwr_li_wr(&seg, wr, &size, mdev, to_mpd(ibqp->pd), qp); 2656 if (err) { 2657 mlx5_ib_warn(dev, "\n"); 2658 *bad_wr = wr; 2659 goto out; 2660 } 2661 num_sge = 0; 2662 break; 2663 2664 case IB_WR_FAST_REG_MR: 2665 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 2666 qp->sq.wr_data[idx] = IB_WR_FAST_REG_MR; 2667 ctrl->imm = cpu_to_be32(wr->wr.fast_reg.rkey); 2668 err = set_frwr_li_wr(&seg, wr, &size, mdev, to_mpd(ibqp->pd), qp); 2669 if (err) { 2670 mlx5_ib_warn(dev, "\n"); 2671 *bad_wr = wr; 2672 goto out; 2673 } 2674 num_sge = 0; 2675 break; 2676 2677 case IB_WR_REG_SIG_MR: 2678 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR; 2679 mr = to_mmr(wr->wr.sig_handover.sig_mr); 2680 2681 ctrl->imm = cpu_to_be32(mr->ibmr.rkey); 2682 err = set_sig_umr_wr(wr, qp, &seg, &size); 2683 if (err) { 2684 mlx5_ib_warn(dev, "\n"); 2685 *bad_wr = wr; 2686 goto out; 2687 } 2688 2689 finish_wqe(qp, ctrl, size, idx, wr->wr_id, 2690 nreq, get_fence(fence, wr), 2691 next_fence, MLX5_OPCODE_UMR); 2692 /* 2693 * SET_PSV WQEs are not signaled and solicited 2694 * on error 2695 */ 2696 wr->send_flags &= ~IB_SEND_SIGNALED; 2697 wr->send_flags |= IB_SEND_SOLICITED; 2698 err = begin_wqe(qp, &seg, &ctrl, wr, 2699 &idx, &size, nreq); 2700 if (err) { 2701 mlx5_ib_warn(dev, "\n"); 2702 err = -ENOMEM; 2703 *bad_wr = wr; 2704 goto out; 2705 } 2706 2707 err = set_psv_wr(&wr->wr.sig_handover.sig_attrs->mem, 2708 mr->sig->psv_memory.psv_idx, &seg, 2709 &size); 2710 if (err) { 2711 mlx5_ib_warn(dev, "\n"); 2712 *bad_wr = wr; 2713 goto out; 2714 } 2715 2716 finish_wqe(qp, ctrl, size, idx, wr->wr_id, 2717 nreq, get_fence(fence, wr), 2718 next_fence, MLX5_OPCODE_SET_PSV); 2719 err = begin_wqe(qp, &seg, &ctrl, wr, 2720 &idx, &size, nreq); 2721 if (err) { 2722 mlx5_ib_warn(dev, "\n"); 2723 err = -ENOMEM; 2724 *bad_wr = wr; 2725 goto out; 2726 } 2727 2728 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 2729 err = set_psv_wr(&wr->wr.sig_handover.sig_attrs->wire, 2730 mr->sig->psv_wire.psv_idx, &seg, 2731 &size); 2732 if (err) { 2733 mlx5_ib_warn(dev, "\n"); 2734 *bad_wr = wr; 2735 goto out; 2736 } 2737 2738 finish_wqe(qp, ctrl, size, idx, wr->wr_id, 2739 nreq, get_fence(fence, wr), 2740 next_fence, MLX5_OPCODE_SET_PSV); 2741 num_sge = 0; 2742 goto skip_psv; 2743 2744 default: 2745 break; 2746 } 2747 break; 2748 2749 case IB_QPT_UC: 2750 switch (wr->opcode) { 2751 case IB_WR_RDMA_WRITE: 2752 case IB_WR_RDMA_WRITE_WITH_IMM: 2753 set_raddr_seg(seg, wr->wr.rdma.remote_addr, 2754 wr->wr.rdma.rkey); 2755 seg += sizeof(struct mlx5_wqe_raddr_seg); 2756 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 2757 break; 2758 2759 default: 2760 break; 2761 } 2762 break; 2763 2764 case IB_QPT_UD: 2765 case IB_QPT_SMI: 2766 case IB_QPT_GSI: 2767 set_datagram_seg(seg, wr); 2768 seg += sizeof(struct mlx5_wqe_datagram_seg); 2769 size += sizeof(struct mlx5_wqe_datagram_seg) / 16; 2770 if (unlikely((seg == qend))) 2771 seg = mlx5_get_send_wqe(qp, 0); 2772 break; 2773 2774 case MLX5_IB_QPT_REG_UMR: 2775 if (wr->opcode != MLX5_IB_WR_UMR) { 2776 err = -EINVAL; 2777 mlx5_ib_warn(dev, "bad opcode\n"); 2778 goto out; 2779 } 2780 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR; 2781 ctrl->imm = cpu_to_be32(wr->wr.fast_reg.rkey); 2782 set_reg_umr_segment(seg, wr); 2783 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 2784 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 2785 if (unlikely((seg == qend))) 2786 seg = mlx5_get_send_wqe(qp, 0); 2787 set_reg_mkey_segment(seg, wr); 2788 seg += sizeof(struct mlx5_mkey_seg); 2789 size += sizeof(struct mlx5_mkey_seg) / 16; 2790 if (unlikely((seg == qend))) 2791 seg = mlx5_get_send_wqe(qp, 0); 2792 break; 2793 2794 default: 2795 break; 2796 } 2797 2798 if (wr->send_flags & IB_SEND_INLINE && num_sge) { 2799 int uninitialized_var(sz); 2800 2801 err = set_data_inl_seg(qp, wr, seg, &sz); 2802 if (unlikely(err)) { 2803 mlx5_ib_warn(dev, "\n"); 2804 *bad_wr = wr; 2805 goto out; 2806 } 2807 inl = 1; 2808 size += sz; 2809 } else { 2810 dpseg = seg; 2811 for (i = 0; i < num_sge; i++) { 2812 if (unlikely(dpseg == qend)) { 2813 seg = mlx5_get_send_wqe(qp, 0); 2814 dpseg = seg; 2815 } 2816 if (likely(wr->sg_list[i].length)) { 2817 set_data_ptr_seg(dpseg, wr->sg_list + i); 2818 size += sizeof(struct mlx5_wqe_data_seg) / 16; 2819 dpseg++; 2820 } 2821 } 2822 } 2823 2824 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, 2825 get_fence(fence, wr), next_fence, 2826 mlx5_ib_opcode[wr->opcode]); 2827 skip_psv: 2828 if (0) 2829 dump_wqe(qp, idx, size); 2830 } 2831 2832 out: 2833 if (likely(nreq)) { 2834 qp->sq.head += nreq; 2835 2836 /* Make sure that descriptors are written before 2837 * updating doorbell record and ringing the doorbell 2838 */ 2839 wmb(); 2840 2841 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post); 2842 2843 /* Make sure doorbell record is visible to the HCA before 2844 * we hit doorbell */ 2845 wmb(); 2846 2847 if (bf->need_lock) 2848 spin_lock(&bf->lock); 2849 else 2850 __acquire(&bf->lock); 2851 2852 /* TBD enable WC */ 2853 if (0 && nreq == 1 && bf->uuarn && inl && size > 1 && size <= bf->buf_size / 16) { 2854 mlx5_bf_copy(bf->reg + bf->offset, (u64 *)ctrl, ALIGN(size * 16, 64), qp); 2855 /* wc_wmb(); */ 2856 } else { 2857 mlx5_write64((__be32 *)ctrl, bf->regreg + bf->offset, 2858 MLX5_GET_DOORBELL_LOCK(&bf->lock32)); 2859 /* Make sure doorbells don't leak out of SQ spinlock 2860 * and reach the HCA out of order. 2861 */ 2862 mmiowb(); 2863 } 2864 bf->offset ^= bf->buf_size; 2865 if (bf->need_lock) 2866 spin_unlock(&bf->lock); 2867 else 2868 __release(&bf->lock); 2869 } 2870 2871 spin_unlock_irqrestore(&qp->sq.lock, flags); 2872 2873 return err; 2874 } 2875 2876 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size) 2877 { 2878 sig->signature = calc_sig(sig, size); 2879 } 2880 2881 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, 2882 struct ib_recv_wr **bad_wr) 2883 { 2884 struct mlx5_ib_qp *qp = to_mqp(ibqp); 2885 struct mlx5_wqe_data_seg *scat; 2886 struct mlx5_rwqe_sig *sig; 2887 unsigned long flags; 2888 int err = 0; 2889 int nreq; 2890 int ind; 2891 int i; 2892 2893 spin_lock_irqsave(&qp->rq.lock, flags); 2894 2895 ind = qp->rq.head & (qp->rq.wqe_cnt - 1); 2896 2897 for (nreq = 0; wr; nreq++, wr = wr->next) { 2898 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) { 2899 err = -ENOMEM; 2900 *bad_wr = wr; 2901 goto out; 2902 } 2903 2904 if (unlikely(wr->num_sge > qp->rq.max_gs)) { 2905 err = -EINVAL; 2906 *bad_wr = wr; 2907 goto out; 2908 } 2909 2910 scat = get_recv_wqe(qp, ind); 2911 if (qp->wq_sig) 2912 scat++; 2913 2914 for (i = 0; i < wr->num_sge; i++) 2915 set_data_ptr_seg(scat + i, wr->sg_list + i); 2916 2917 if (i < qp->rq.max_gs) { 2918 scat[i].byte_count = 0; 2919 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY); 2920 scat[i].addr = 0; 2921 } 2922 2923 if (qp->wq_sig) { 2924 sig = (struct mlx5_rwqe_sig *)scat; 2925 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2); 2926 } 2927 2928 qp->rq.wrid[ind] = wr->wr_id; 2929 2930 ind = (ind + 1) & (qp->rq.wqe_cnt - 1); 2931 } 2932 2933 out: 2934 if (likely(nreq)) { 2935 qp->rq.head += nreq; 2936 2937 /* Make sure that descriptors are written before 2938 * doorbell record. 2939 */ 2940 wmb(); 2941 2942 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff); 2943 } 2944 2945 spin_unlock_irqrestore(&qp->rq.lock, flags); 2946 2947 return err; 2948 } 2949 2950 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state) 2951 { 2952 switch (mlx5_state) { 2953 case MLX5_QP_STATE_RST: return IB_QPS_RESET; 2954 case MLX5_QP_STATE_INIT: return IB_QPS_INIT; 2955 case MLX5_QP_STATE_RTR: return IB_QPS_RTR; 2956 case MLX5_QP_STATE_RTS: return IB_QPS_RTS; 2957 case MLX5_QP_STATE_SQ_DRAINING: 2958 case MLX5_QP_STATE_SQD: return IB_QPS_SQD; 2959 case MLX5_QP_STATE_SQER: return IB_QPS_SQE; 2960 case MLX5_QP_STATE_ERR: return IB_QPS_ERR; 2961 default: return -1; 2962 } 2963 } 2964 2965 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state) 2966 { 2967 switch (mlx5_mig_state) { 2968 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED; 2969 case MLX5_QP_PM_REARM: return IB_MIG_REARM; 2970 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED; 2971 default: return -1; 2972 } 2973 } 2974 2975 static int to_ib_qp_access_flags(int mlx5_flags) 2976 { 2977 int ib_flags = 0; 2978 2979 if (mlx5_flags & MLX5_QP_BIT_RRE) 2980 ib_flags |= IB_ACCESS_REMOTE_READ; 2981 if (mlx5_flags & MLX5_QP_BIT_RWE) 2982 ib_flags |= IB_ACCESS_REMOTE_WRITE; 2983 if (mlx5_flags & MLX5_QP_BIT_RAE) 2984 ib_flags |= IB_ACCESS_REMOTE_ATOMIC; 2985 2986 return ib_flags; 2987 } 2988 2989 static void to_ib_ah_attr(struct mlx5_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr, 2990 struct mlx5_qp_path *path) 2991 { 2992 struct mlx5_core_dev *dev = ibdev->mdev; 2993 2994 memset(ib_ah_attr, 0, sizeof(*ib_ah_attr)); 2995 ib_ah_attr->port_num = path->port; 2996 2997 if (ib_ah_attr->port_num == 0 || 2998 ib_ah_attr->port_num > dev->caps.gen.num_ports) 2999 return; 3000 3001 ib_ah_attr->sl = path->sl & 0xf; 3002 3003 ib_ah_attr->dlid = be16_to_cpu(path->rlid); 3004 ib_ah_attr->src_path_bits = path->grh_mlid & 0x7f; 3005 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0; 3006 ib_ah_attr->ah_flags = (path->grh_mlid & (1 << 7)) ? IB_AH_GRH : 0; 3007 if (ib_ah_attr->ah_flags) { 3008 ib_ah_attr->grh.sgid_index = path->mgid_index; 3009 ib_ah_attr->grh.hop_limit = path->hop_limit; 3010 ib_ah_attr->grh.traffic_class = 3011 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff; 3012 ib_ah_attr->grh.flow_label = 3013 be32_to_cpu(path->tclass_flowlabel) & 0xfffff; 3014 memcpy(ib_ah_attr->grh.dgid.raw, 3015 path->rgid, sizeof(ib_ah_attr->grh.dgid.raw)); 3016 } 3017 } 3018 3019 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, 3020 struct ib_qp_init_attr *qp_init_attr) 3021 { 3022 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3023 struct mlx5_ib_qp *qp = to_mqp(ibqp); 3024 struct mlx5_query_qp_mbox_out *outb; 3025 struct mlx5_qp_context *context; 3026 int mlx5_state; 3027 int err = 0; 3028 3029 mutex_lock(&qp->mutex); 3030 outb = kzalloc(sizeof(*outb), GFP_KERNEL); 3031 if (!outb) { 3032 err = -ENOMEM; 3033 goto out; 3034 } 3035 context = &outb->ctx; 3036 err = mlx5_core_qp_query(dev->mdev, &qp->mqp, outb, sizeof(*outb)); 3037 if (err) 3038 goto out_free; 3039 3040 mlx5_state = be32_to_cpu(context->flags) >> 28; 3041 3042 qp->state = to_ib_qp_state(mlx5_state); 3043 qp_attr->qp_state = qp->state; 3044 qp_attr->path_mtu = context->mtu_msgmax >> 5; 3045 qp_attr->path_mig_state = 3046 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3); 3047 qp_attr->qkey = be32_to_cpu(context->qkey); 3048 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff; 3049 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff; 3050 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff; 3051 qp_attr->qp_access_flags = 3052 to_ib_qp_access_flags(be32_to_cpu(context->params2)); 3053 3054 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) { 3055 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path); 3056 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path); 3057 qp_attr->alt_pkey_index = context->alt_path.pkey_index & 0x7f; 3058 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num; 3059 } 3060 3061 qp_attr->pkey_index = context->pri_path.pkey_index & 0x7f; 3062 qp_attr->port_num = context->pri_path.port; 3063 3064 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */ 3065 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING; 3066 3067 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7); 3068 3069 qp_attr->max_dest_rd_atomic = 3070 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7); 3071 qp_attr->min_rnr_timer = 3072 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f; 3073 qp_attr->timeout = context->pri_path.ackto_lt >> 3; 3074 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7; 3075 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7; 3076 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3; 3077 qp_attr->cur_qp_state = qp_attr->qp_state; 3078 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; 3079 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 3080 3081 if (!ibqp->uobject) { 3082 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt; 3083 qp_attr->cap.max_send_sge = qp->sq.max_gs; 3084 } else { 3085 qp_attr->cap.max_send_wr = 0; 3086 qp_attr->cap.max_send_sge = 0; 3087 } 3088 3089 /* We don't support inline sends for kernel QPs (yet), and we 3090 * don't know what userspace's value should be. 3091 */ 3092 qp_attr->cap.max_inline_data = 0; 3093 3094 qp_init_attr->cap = qp_attr->cap; 3095 3096 qp_init_attr->create_flags = 0; 3097 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 3098 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK; 3099 3100 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ? 3101 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; 3102 3103 out_free: 3104 kfree(outb); 3105 3106 out: 3107 mutex_unlock(&qp->mutex); 3108 return err; 3109 } 3110 3111 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, 3112 struct ib_ucontext *context, 3113 struct ib_udata *udata) 3114 { 3115 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3116 struct mlx5_general_caps *gen; 3117 struct mlx5_ib_xrcd *xrcd; 3118 int err; 3119 3120 gen = &dev->mdev->caps.gen; 3121 if (!(gen->flags & MLX5_DEV_CAP_FLAG_XRC)) 3122 return ERR_PTR(-ENOSYS); 3123 3124 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL); 3125 if (!xrcd) 3126 return ERR_PTR(-ENOMEM); 3127 3128 err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn); 3129 if (err) { 3130 kfree(xrcd); 3131 return ERR_PTR(-ENOMEM); 3132 } 3133 3134 return &xrcd->ibxrcd; 3135 } 3136 3137 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd) 3138 { 3139 struct mlx5_ib_dev *dev = to_mdev(xrcd->device); 3140 u32 xrcdn = to_mxrcd(xrcd)->xrcdn; 3141 int err; 3142 3143 err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn); 3144 if (err) { 3145 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn); 3146 return err; 3147 } 3148 3149 kfree(xrcd); 3150 3151 return 0; 3152 } 3153