1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/module.h> 34 #include <rdma/ib_umem.h> 35 #include <rdma/ib_cache.h> 36 #include <rdma/ib_user_verbs.h> 37 #include <linux/mlx5/fs.h> 38 #include "mlx5_ib.h" 39 40 /* not supported currently */ 41 static int wq_signature; 42 43 enum { 44 MLX5_IB_ACK_REQ_FREQ = 8, 45 }; 46 47 enum { 48 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83, 49 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, 50 MLX5_IB_LINK_TYPE_IB = 0, 51 MLX5_IB_LINK_TYPE_ETH = 1 52 }; 53 54 enum { 55 MLX5_IB_SQ_STRIDE = 6, 56 }; 57 58 static const u32 mlx5_ib_opcode[] = { 59 [IB_WR_SEND] = MLX5_OPCODE_SEND, 60 [IB_WR_LSO] = MLX5_OPCODE_LSO, 61 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM, 62 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE, 63 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM, 64 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ, 65 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS, 66 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA, 67 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL, 68 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR, 69 [IB_WR_REG_MR] = MLX5_OPCODE_UMR, 70 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS, 71 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA, 72 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR, 73 }; 74 75 struct mlx5_wqe_eth_pad { 76 u8 rsvd0[16]; 77 }; 78 79 enum raw_qp_set_mask_map { 80 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0, 81 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1, 82 }; 83 84 struct mlx5_modify_raw_qp_param { 85 u16 operation; 86 87 u32 set_mask; /* raw_qp_set_mask_map */ 88 u32 rate_limit; 89 u8 rq_q_ctr_id; 90 }; 91 92 static void get_cqs(enum ib_qp_type qp_type, 93 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 94 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq); 95 96 static int is_qp0(enum ib_qp_type qp_type) 97 { 98 return qp_type == IB_QPT_SMI; 99 } 100 101 static int is_sqp(enum ib_qp_type qp_type) 102 { 103 return is_qp0(qp_type) || is_qp1(qp_type); 104 } 105 106 static void *get_wqe(struct mlx5_ib_qp *qp, int offset) 107 { 108 return mlx5_buf_offset(&qp->buf, offset); 109 } 110 111 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n) 112 { 113 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift)); 114 } 115 116 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n) 117 { 118 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE)); 119 } 120 121 /** 122 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space. 123 * 124 * @qp: QP to copy from. 125 * @send: copy from the send queue when non-zero, use the receive queue 126 * otherwise. 127 * @wqe_index: index to start copying from. For send work queues, the 128 * wqe_index is in units of MLX5_SEND_WQE_BB. 129 * For receive work queue, it is the number of work queue 130 * element in the queue. 131 * @buffer: destination buffer. 132 * @length: maximum number of bytes to copy. 133 * 134 * Copies at least a single WQE, but may copy more data. 135 * 136 * Return: the number of bytes copied, or an error code. 137 */ 138 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index, 139 void *buffer, u32 length, 140 struct mlx5_ib_qp_base *base) 141 { 142 struct ib_device *ibdev = qp->ibqp.device; 143 struct mlx5_ib_dev *dev = to_mdev(ibdev); 144 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq; 145 size_t offset; 146 size_t wq_end; 147 struct ib_umem *umem = base->ubuffer.umem; 148 u32 first_copy_length; 149 int wqe_length; 150 int ret; 151 152 if (wq->wqe_cnt == 0) { 153 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n", 154 qp->ibqp.qp_type); 155 return -EINVAL; 156 } 157 158 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift); 159 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift); 160 161 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg)) 162 return -EINVAL; 163 164 if (offset > umem->length || 165 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length)) 166 return -EINVAL; 167 168 first_copy_length = min_t(u32, offset + length, wq_end) - offset; 169 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length); 170 if (ret) 171 return ret; 172 173 if (send) { 174 struct mlx5_wqe_ctrl_seg *ctrl = buffer; 175 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; 176 177 wqe_length = ds * MLX5_WQE_DS_UNITS; 178 } else { 179 wqe_length = 1 << wq->wqe_shift; 180 } 181 182 if (wqe_length <= first_copy_length) 183 return first_copy_length; 184 185 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset, 186 wqe_length - first_copy_length); 187 if (ret) 188 return ret; 189 190 return wqe_length; 191 } 192 193 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type) 194 { 195 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; 196 struct ib_event event; 197 198 if (type == MLX5_EVENT_TYPE_PATH_MIG) { 199 /* This event is only valid for trans_qps */ 200 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port; 201 } 202 203 if (ibqp->event_handler) { 204 event.device = ibqp->device; 205 event.element.qp = ibqp; 206 switch (type) { 207 case MLX5_EVENT_TYPE_PATH_MIG: 208 event.event = IB_EVENT_PATH_MIG; 209 break; 210 case MLX5_EVENT_TYPE_COMM_EST: 211 event.event = IB_EVENT_COMM_EST; 212 break; 213 case MLX5_EVENT_TYPE_SQ_DRAINED: 214 event.event = IB_EVENT_SQ_DRAINED; 215 break; 216 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 217 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 218 break; 219 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 220 event.event = IB_EVENT_QP_FATAL; 221 break; 222 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 223 event.event = IB_EVENT_PATH_MIG_ERR; 224 break; 225 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 226 event.event = IB_EVENT_QP_REQ_ERR; 227 break; 228 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 229 event.event = IB_EVENT_QP_ACCESS_ERR; 230 break; 231 default: 232 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn); 233 return; 234 } 235 236 ibqp->event_handler(&event, ibqp->qp_context); 237 } 238 } 239 240 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap, 241 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd) 242 { 243 int wqe_size; 244 int wq_size; 245 246 /* Sanity check RQ size before proceeding */ 247 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) 248 return -EINVAL; 249 250 if (!has_rq) { 251 qp->rq.max_gs = 0; 252 qp->rq.wqe_cnt = 0; 253 qp->rq.wqe_shift = 0; 254 cap->max_recv_wr = 0; 255 cap->max_recv_sge = 0; 256 } else { 257 if (ucmd) { 258 qp->rq.wqe_cnt = ucmd->rq_wqe_count; 259 qp->rq.wqe_shift = ucmd->rq_wqe_shift; 260 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 261 qp->rq.max_post = qp->rq.wqe_cnt; 262 } else { 263 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0; 264 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg); 265 wqe_size = roundup_pow_of_two(wqe_size); 266 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size; 267 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB); 268 qp->rq.wqe_cnt = wq_size / wqe_size; 269 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) { 270 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n", 271 wqe_size, 272 MLX5_CAP_GEN(dev->mdev, 273 max_wqe_sz_rq)); 274 return -EINVAL; 275 } 276 qp->rq.wqe_shift = ilog2(wqe_size); 277 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 278 qp->rq.max_post = qp->rq.wqe_cnt; 279 } 280 } 281 282 return 0; 283 } 284 285 static int sq_overhead(struct ib_qp_init_attr *attr) 286 { 287 int size = 0; 288 289 switch (attr->qp_type) { 290 case IB_QPT_XRC_INI: 291 size += sizeof(struct mlx5_wqe_xrc_seg); 292 /* fall through */ 293 case IB_QPT_RC: 294 size += sizeof(struct mlx5_wqe_ctrl_seg) + 295 max(sizeof(struct mlx5_wqe_atomic_seg) + 296 sizeof(struct mlx5_wqe_raddr_seg), 297 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 298 sizeof(struct mlx5_mkey_seg)); 299 break; 300 301 case IB_QPT_XRC_TGT: 302 return 0; 303 304 case IB_QPT_UC: 305 size += sizeof(struct mlx5_wqe_ctrl_seg) + 306 max(sizeof(struct mlx5_wqe_raddr_seg), 307 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 308 sizeof(struct mlx5_mkey_seg)); 309 break; 310 311 case IB_QPT_UD: 312 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) 313 size += sizeof(struct mlx5_wqe_eth_pad) + 314 sizeof(struct mlx5_wqe_eth_seg); 315 /* fall through */ 316 case IB_QPT_SMI: 317 case MLX5_IB_QPT_HW_GSI: 318 size += sizeof(struct mlx5_wqe_ctrl_seg) + 319 sizeof(struct mlx5_wqe_datagram_seg); 320 break; 321 322 case MLX5_IB_QPT_REG_UMR: 323 size += sizeof(struct mlx5_wqe_ctrl_seg) + 324 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 325 sizeof(struct mlx5_mkey_seg); 326 break; 327 328 default: 329 return -EINVAL; 330 } 331 332 return size; 333 } 334 335 static int calc_send_wqe(struct ib_qp_init_attr *attr) 336 { 337 int inl_size = 0; 338 int size; 339 340 size = sq_overhead(attr); 341 if (size < 0) 342 return size; 343 344 if (attr->cap.max_inline_data) { 345 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) + 346 attr->cap.max_inline_data; 347 } 348 349 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg); 350 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN && 351 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE) 352 return MLX5_SIG_WQE_SIZE; 353 else 354 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB); 355 } 356 357 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size) 358 { 359 int max_sge; 360 361 if (attr->qp_type == IB_QPT_RC) 362 max_sge = (min_t(int, wqe_size, 512) - 363 sizeof(struct mlx5_wqe_ctrl_seg) - 364 sizeof(struct mlx5_wqe_raddr_seg)) / 365 sizeof(struct mlx5_wqe_data_seg); 366 else if (attr->qp_type == IB_QPT_XRC_INI) 367 max_sge = (min_t(int, wqe_size, 512) - 368 sizeof(struct mlx5_wqe_ctrl_seg) - 369 sizeof(struct mlx5_wqe_xrc_seg) - 370 sizeof(struct mlx5_wqe_raddr_seg)) / 371 sizeof(struct mlx5_wqe_data_seg); 372 else 373 max_sge = (wqe_size - sq_overhead(attr)) / 374 sizeof(struct mlx5_wqe_data_seg); 375 376 return min_t(int, max_sge, wqe_size - sq_overhead(attr) / 377 sizeof(struct mlx5_wqe_data_seg)); 378 } 379 380 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, 381 struct mlx5_ib_qp *qp) 382 { 383 int wqe_size; 384 int wq_size; 385 386 if (!attr->cap.max_send_wr) 387 return 0; 388 389 wqe_size = calc_send_wqe(attr); 390 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size); 391 if (wqe_size < 0) 392 return wqe_size; 393 394 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 395 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n", 396 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 397 return -EINVAL; 398 } 399 400 qp->max_inline_data = wqe_size - sq_overhead(attr) - 401 sizeof(struct mlx5_wqe_inline_seg); 402 attr->cap.max_inline_data = qp->max_inline_data; 403 404 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN) 405 qp->signature_en = true; 406 407 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size); 408 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB; 409 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 410 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n", 411 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB, 412 qp->sq.wqe_cnt, 413 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 414 return -ENOMEM; 415 } 416 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 417 qp->sq.max_gs = get_send_sge(attr, wqe_size); 418 if (qp->sq.max_gs < attr->cap.max_send_sge) 419 return -ENOMEM; 420 421 attr->cap.max_send_sge = qp->sq.max_gs; 422 qp->sq.max_post = wq_size / wqe_size; 423 attr->cap.max_send_wr = qp->sq.max_post; 424 425 return wq_size; 426 } 427 428 static int set_user_buf_size(struct mlx5_ib_dev *dev, 429 struct mlx5_ib_qp *qp, 430 struct mlx5_ib_create_qp *ucmd, 431 struct mlx5_ib_qp_base *base, 432 struct ib_qp_init_attr *attr) 433 { 434 int desc_sz = 1 << qp->sq.wqe_shift; 435 436 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 437 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n", 438 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 439 return -EINVAL; 440 } 441 442 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) { 443 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n", 444 ucmd->sq_wqe_count, ucmd->sq_wqe_count); 445 return -EINVAL; 446 } 447 448 qp->sq.wqe_cnt = ucmd->sq_wqe_count; 449 450 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 451 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n", 452 qp->sq.wqe_cnt, 453 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 454 return -EINVAL; 455 } 456 457 if (attr->qp_type == IB_QPT_RAW_PACKET || 458 qp->flags & MLX5_IB_QP_UNDERLAY) { 459 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift; 460 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6; 461 } else { 462 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 463 (qp->sq.wqe_cnt << 6); 464 } 465 466 return 0; 467 } 468 469 static int qp_has_rq(struct ib_qp_init_attr *attr) 470 { 471 if (attr->qp_type == IB_QPT_XRC_INI || 472 attr->qp_type == IB_QPT_XRC_TGT || attr->srq || 473 attr->qp_type == MLX5_IB_QPT_REG_UMR || 474 !attr->cap.max_recv_wr) 475 return 0; 476 477 return 1; 478 } 479 480 static int first_med_bfreg(void) 481 { 482 return 1; 483 } 484 485 enum { 486 /* this is the first blue flame register in the array of bfregs assigned 487 * to a processes. Since we do not use it for blue flame but rather 488 * regular 64 bit doorbells, we do not need a lock for maintaiing 489 * "odd/even" order 490 */ 491 NUM_NON_BLUE_FLAME_BFREGS = 1, 492 }; 493 494 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi) 495 { 496 return get_num_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR; 497 } 498 499 static int num_med_bfreg(struct mlx5_ib_dev *dev, 500 struct mlx5_bfreg_info *bfregi) 501 { 502 int n; 503 504 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs - 505 NUM_NON_BLUE_FLAME_BFREGS; 506 507 return n >= 0 ? n : 0; 508 } 509 510 static int first_hi_bfreg(struct mlx5_ib_dev *dev, 511 struct mlx5_bfreg_info *bfregi) 512 { 513 int med; 514 515 med = num_med_bfreg(dev, bfregi); 516 return ++med; 517 } 518 519 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev, 520 struct mlx5_bfreg_info *bfregi) 521 { 522 int i; 523 524 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) { 525 if (!bfregi->count[i]) { 526 bfregi->count[i]++; 527 return i; 528 } 529 } 530 531 return -ENOMEM; 532 } 533 534 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev, 535 struct mlx5_bfreg_info *bfregi) 536 { 537 int minidx = first_med_bfreg(); 538 int i; 539 540 for (i = first_med_bfreg(); i < first_hi_bfreg(dev, bfregi); i++) { 541 if (bfregi->count[i] < bfregi->count[minidx]) 542 minidx = i; 543 if (!bfregi->count[minidx]) 544 break; 545 } 546 547 bfregi->count[minidx]++; 548 return minidx; 549 } 550 551 static int alloc_bfreg(struct mlx5_ib_dev *dev, 552 struct mlx5_bfreg_info *bfregi, 553 enum mlx5_ib_latency_class lat) 554 { 555 int bfregn = -EINVAL; 556 557 mutex_lock(&bfregi->lock); 558 switch (lat) { 559 case MLX5_IB_LATENCY_CLASS_LOW: 560 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1); 561 bfregn = 0; 562 bfregi->count[bfregn]++; 563 break; 564 565 case MLX5_IB_LATENCY_CLASS_MEDIUM: 566 if (bfregi->ver < 2) 567 bfregn = -ENOMEM; 568 else 569 bfregn = alloc_med_class_bfreg(dev, bfregi); 570 break; 571 572 case MLX5_IB_LATENCY_CLASS_HIGH: 573 if (bfregi->ver < 2) 574 bfregn = -ENOMEM; 575 else 576 bfregn = alloc_high_class_bfreg(dev, bfregi); 577 break; 578 } 579 mutex_unlock(&bfregi->lock); 580 581 return bfregn; 582 } 583 584 static void free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn) 585 { 586 mutex_lock(&bfregi->lock); 587 bfregi->count[bfregn]--; 588 mutex_unlock(&bfregi->lock); 589 } 590 591 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state) 592 { 593 switch (state) { 594 case IB_QPS_RESET: return MLX5_QP_STATE_RST; 595 case IB_QPS_INIT: return MLX5_QP_STATE_INIT; 596 case IB_QPS_RTR: return MLX5_QP_STATE_RTR; 597 case IB_QPS_RTS: return MLX5_QP_STATE_RTS; 598 case IB_QPS_SQD: return MLX5_QP_STATE_SQD; 599 case IB_QPS_SQE: return MLX5_QP_STATE_SQER; 600 case IB_QPS_ERR: return MLX5_QP_STATE_ERR; 601 default: return -1; 602 } 603 } 604 605 static int to_mlx5_st(enum ib_qp_type type) 606 { 607 switch (type) { 608 case IB_QPT_RC: return MLX5_QP_ST_RC; 609 case IB_QPT_UC: return MLX5_QP_ST_UC; 610 case IB_QPT_UD: return MLX5_QP_ST_UD; 611 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR; 612 case IB_QPT_XRC_INI: 613 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC; 614 case IB_QPT_SMI: return MLX5_QP_ST_QP0; 615 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1; 616 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6; 617 case IB_QPT_RAW_PACKET: 618 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE; 619 case IB_QPT_MAX: 620 default: return -EINVAL; 621 } 622 } 623 624 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, 625 struct mlx5_ib_cq *recv_cq); 626 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, 627 struct mlx5_ib_cq *recv_cq); 628 629 static int bfregn_to_uar_index(struct mlx5_ib_dev *dev, 630 struct mlx5_bfreg_info *bfregi, int bfregn) 631 { 632 int bfregs_per_sys_page; 633 int index_of_sys_page; 634 int offset; 635 636 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * 637 MLX5_NON_FP_BFREGS_PER_UAR; 638 index_of_sys_page = bfregn / bfregs_per_sys_page; 639 640 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR; 641 642 return bfregi->sys_pages[index_of_sys_page] + offset; 643 } 644 645 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev, 646 struct ib_pd *pd, 647 unsigned long addr, size_t size, 648 struct ib_umem **umem, 649 int *npages, int *page_shift, int *ncont, 650 u32 *offset) 651 { 652 int err; 653 654 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0); 655 if (IS_ERR(*umem)) { 656 mlx5_ib_dbg(dev, "umem_get failed\n"); 657 return PTR_ERR(*umem); 658 } 659 660 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL); 661 662 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset); 663 if (err) { 664 mlx5_ib_warn(dev, "bad offset\n"); 665 goto err_umem; 666 } 667 668 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n", 669 addr, size, *npages, *page_shift, *ncont, *offset); 670 671 return 0; 672 673 err_umem: 674 ib_umem_release(*umem); 675 *umem = NULL; 676 677 return err; 678 } 679 680 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 681 struct mlx5_ib_rwq *rwq) 682 { 683 struct mlx5_ib_ucontext *context; 684 685 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP) 686 atomic_dec(&dev->delay_drop.rqs_cnt); 687 688 context = to_mucontext(pd->uobject->context); 689 mlx5_ib_db_unmap_user(context, &rwq->db); 690 if (rwq->umem) 691 ib_umem_release(rwq->umem); 692 } 693 694 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 695 struct mlx5_ib_rwq *rwq, 696 struct mlx5_ib_create_wq *ucmd) 697 { 698 struct mlx5_ib_ucontext *context; 699 int page_shift = 0; 700 int npages; 701 u32 offset = 0; 702 int ncont = 0; 703 int err; 704 705 if (!ucmd->buf_addr) 706 return -EINVAL; 707 708 context = to_mucontext(pd->uobject->context); 709 rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr, 710 rwq->buf_size, 0, 0); 711 if (IS_ERR(rwq->umem)) { 712 mlx5_ib_dbg(dev, "umem_get failed\n"); 713 err = PTR_ERR(rwq->umem); 714 return err; 715 } 716 717 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift, 718 &ncont, NULL); 719 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift, 720 &rwq->rq_page_offset); 721 if (err) { 722 mlx5_ib_warn(dev, "bad offset\n"); 723 goto err_umem; 724 } 725 726 rwq->rq_num_pas = ncont; 727 rwq->page_shift = page_shift; 728 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT; 729 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE); 730 731 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n", 732 (unsigned long long)ucmd->buf_addr, rwq->buf_size, 733 npages, page_shift, ncont, offset); 734 735 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db); 736 if (err) { 737 mlx5_ib_dbg(dev, "map failed\n"); 738 goto err_umem; 739 } 740 741 rwq->create_type = MLX5_WQ_USER; 742 return 0; 743 744 err_umem: 745 ib_umem_release(rwq->umem); 746 return err; 747 } 748 749 static int adjust_bfregn(struct mlx5_ib_dev *dev, 750 struct mlx5_bfreg_info *bfregi, int bfregn) 751 { 752 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR + 753 bfregn % MLX5_NON_FP_BFREGS_PER_UAR; 754 } 755 756 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 757 struct mlx5_ib_qp *qp, struct ib_udata *udata, 758 struct ib_qp_init_attr *attr, 759 u32 **in, 760 struct mlx5_ib_create_qp_resp *resp, int *inlen, 761 struct mlx5_ib_qp_base *base) 762 { 763 struct mlx5_ib_ucontext *context; 764 struct mlx5_ib_create_qp ucmd; 765 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer; 766 int page_shift = 0; 767 int uar_index; 768 int npages; 769 u32 offset = 0; 770 int bfregn; 771 int ncont = 0; 772 __be64 *pas; 773 void *qpc; 774 int err; 775 776 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd)); 777 if (err) { 778 mlx5_ib_dbg(dev, "copy failed\n"); 779 return err; 780 } 781 782 context = to_mucontext(pd->uobject->context); 783 /* 784 * TBD: should come from the verbs when we have the API 785 */ 786 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 787 /* In CROSS_CHANNEL CQ and QP must use the same UAR */ 788 bfregn = MLX5_CROSS_CHANNEL_BFREG; 789 else { 790 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_HIGH); 791 if (bfregn < 0) { 792 mlx5_ib_dbg(dev, "failed to allocate low latency BFREG\n"); 793 mlx5_ib_dbg(dev, "reverting to medium latency\n"); 794 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_MEDIUM); 795 if (bfregn < 0) { 796 mlx5_ib_dbg(dev, "failed to allocate medium latency BFREG\n"); 797 mlx5_ib_dbg(dev, "reverting to high latency\n"); 798 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_LOW); 799 if (bfregn < 0) { 800 mlx5_ib_warn(dev, "bfreg allocation failed\n"); 801 return bfregn; 802 } 803 } 804 } 805 } 806 807 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn); 808 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index); 809 810 qp->rq.offset = 0; 811 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 812 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 813 814 err = set_user_buf_size(dev, qp, &ucmd, base, attr); 815 if (err) 816 goto err_bfreg; 817 818 if (ucmd.buf_addr && ubuffer->buf_size) { 819 ubuffer->buf_addr = ucmd.buf_addr; 820 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, 821 ubuffer->buf_size, 822 &ubuffer->umem, &npages, &page_shift, 823 &ncont, &offset); 824 if (err) 825 goto err_bfreg; 826 } else { 827 ubuffer->umem = NULL; 828 } 829 830 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 831 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont; 832 *in = kvzalloc(*inlen, GFP_KERNEL); 833 if (!*in) { 834 err = -ENOMEM; 835 goto err_umem; 836 } 837 838 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas); 839 if (ubuffer->umem) 840 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0); 841 842 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 843 844 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT); 845 MLX5_SET(qpc, qpc, page_offset, offset); 846 847 MLX5_SET(qpc, qpc, uar_page, uar_index); 848 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn); 849 qp->bfregn = bfregn; 850 851 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db); 852 if (err) { 853 mlx5_ib_dbg(dev, "map failed\n"); 854 goto err_free; 855 } 856 857 err = ib_copy_to_udata(udata, resp, sizeof(*resp)); 858 if (err) { 859 mlx5_ib_dbg(dev, "copy failed\n"); 860 goto err_unmap; 861 } 862 qp->create_type = MLX5_QP_USER; 863 864 return 0; 865 866 err_unmap: 867 mlx5_ib_db_unmap_user(context, &qp->db); 868 869 err_free: 870 kvfree(*in); 871 872 err_umem: 873 if (ubuffer->umem) 874 ib_umem_release(ubuffer->umem); 875 876 err_bfreg: 877 free_bfreg(dev, &context->bfregi, bfregn); 878 return err; 879 } 880 881 static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd, 882 struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base) 883 { 884 struct mlx5_ib_ucontext *context; 885 886 context = to_mucontext(pd->uobject->context); 887 mlx5_ib_db_unmap_user(context, &qp->db); 888 if (base->ubuffer.umem) 889 ib_umem_release(base->ubuffer.umem); 890 free_bfreg(dev, &context->bfregi, qp->bfregn); 891 } 892 893 static int create_kernel_qp(struct mlx5_ib_dev *dev, 894 struct ib_qp_init_attr *init_attr, 895 struct mlx5_ib_qp *qp, 896 u32 **in, int *inlen, 897 struct mlx5_ib_qp_base *base) 898 { 899 int uar_index; 900 void *qpc; 901 int err; 902 903 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN | 904 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK | 905 IB_QP_CREATE_IPOIB_UD_LSO | 906 IB_QP_CREATE_NETIF_QP | 907 mlx5_ib_create_qp_sqpn_qp1())) 908 return -EINVAL; 909 910 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR) 911 qp->bf.bfreg = &dev->fp_bfreg; 912 else 913 qp->bf.bfreg = &dev->bfreg; 914 915 /* We need to divide by two since each register is comprised of 916 * two buffers of identical size, namely odd and even 917 */ 918 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2; 919 uar_index = qp->bf.bfreg->index; 920 921 err = calc_sq_size(dev, init_attr, qp); 922 if (err < 0) { 923 mlx5_ib_dbg(dev, "err %d\n", err); 924 return err; 925 } 926 927 qp->rq.offset = 0; 928 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 929 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift); 930 931 err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf); 932 if (err) { 933 mlx5_ib_dbg(dev, "err %d\n", err); 934 return err; 935 } 936 937 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt); 938 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 939 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages; 940 *in = kvzalloc(*inlen, GFP_KERNEL); 941 if (!*in) { 942 err = -ENOMEM; 943 goto err_buf; 944 } 945 946 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 947 MLX5_SET(qpc, qpc, uar_page, uar_index); 948 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT); 949 950 /* Set "fast registration enabled" for all kernel QPs */ 951 MLX5_SET(qpc, qpc, fre, 1); 952 MLX5_SET(qpc, qpc, rlky, 1); 953 954 if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) { 955 MLX5_SET(qpc, qpc, deth_sqpn, 1); 956 qp->flags |= MLX5_IB_QP_SQPN_QP1; 957 } 958 959 mlx5_fill_page_array(&qp->buf, 960 (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas)); 961 962 err = mlx5_db_alloc(dev->mdev, &qp->db); 963 if (err) { 964 mlx5_ib_dbg(dev, "err %d\n", err); 965 goto err_free; 966 } 967 968 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt, 969 sizeof(*qp->sq.wrid), GFP_KERNEL); 970 qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt, 971 sizeof(*qp->sq.wr_data), GFP_KERNEL); 972 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt, 973 sizeof(*qp->rq.wrid), GFP_KERNEL); 974 qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt, 975 sizeof(*qp->sq.w_list), GFP_KERNEL); 976 qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt, 977 sizeof(*qp->sq.wqe_head), GFP_KERNEL); 978 979 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid || 980 !qp->sq.w_list || !qp->sq.wqe_head) { 981 err = -ENOMEM; 982 goto err_wrid; 983 } 984 qp->create_type = MLX5_QP_KERNEL; 985 986 return 0; 987 988 err_wrid: 989 kvfree(qp->sq.wqe_head); 990 kvfree(qp->sq.w_list); 991 kvfree(qp->sq.wrid); 992 kvfree(qp->sq.wr_data); 993 kvfree(qp->rq.wrid); 994 mlx5_db_free(dev->mdev, &qp->db); 995 996 err_free: 997 kvfree(*in); 998 999 err_buf: 1000 mlx5_buf_free(dev->mdev, &qp->buf); 1001 return err; 1002 } 1003 1004 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1005 { 1006 kvfree(qp->sq.wqe_head); 1007 kvfree(qp->sq.w_list); 1008 kvfree(qp->sq.wrid); 1009 kvfree(qp->sq.wr_data); 1010 kvfree(qp->rq.wrid); 1011 mlx5_db_free(dev->mdev, &qp->db); 1012 mlx5_buf_free(dev->mdev, &qp->buf); 1013 } 1014 1015 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr) 1016 { 1017 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) || 1018 (attr->qp_type == IB_QPT_XRC_INI)) 1019 return MLX5_SRQ_RQ; 1020 else if (!qp->has_rq) 1021 return MLX5_ZERO_LEN_RQ; 1022 else 1023 return MLX5_NON_ZERO_RQ; 1024 } 1025 1026 static int is_connected(enum ib_qp_type qp_type) 1027 { 1028 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC) 1029 return 1; 1030 1031 return 0; 1032 } 1033 1034 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1035 struct mlx5_ib_qp *qp, 1036 struct mlx5_ib_sq *sq, u32 tdn) 1037 { 1038 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 1039 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 1040 1041 MLX5_SET(tisc, tisc, transport_domain, tdn); 1042 if (qp->flags & MLX5_IB_QP_UNDERLAY) 1043 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn); 1044 1045 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn); 1046 } 1047 1048 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1049 struct mlx5_ib_sq *sq) 1050 { 1051 mlx5_core_destroy_tis(dev->mdev, sq->tisn); 1052 } 1053 1054 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1055 struct mlx5_ib_sq *sq, void *qpin, 1056 struct ib_pd *pd) 1057 { 1058 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer; 1059 __be64 *pas; 1060 void *in; 1061 void *sqc; 1062 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1063 void *wq; 1064 int inlen; 1065 int err; 1066 int page_shift = 0; 1067 int npages; 1068 int ncont = 0; 1069 u32 offset = 0; 1070 1071 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size, 1072 &sq->ubuffer.umem, &npages, &page_shift, 1073 &ncont, &offset); 1074 if (err) 1075 return err; 1076 1077 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont; 1078 in = kvzalloc(inlen, GFP_KERNEL); 1079 if (!in) { 1080 err = -ENOMEM; 1081 goto err_umem; 1082 } 1083 1084 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 1085 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 1086 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe)) 1087 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1); 1088 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 1089 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1090 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd)); 1091 MLX5_SET(sqc, sqc, tis_lst_sz, 1); 1092 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn); 1093 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 1094 MLX5_CAP_ETH(dev->mdev, swp)) 1095 MLX5_SET(sqc, sqc, allow_swp, 1); 1096 1097 wq = MLX5_ADDR_OF(sqc, sqc, wq); 1098 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1099 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1100 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page)); 1101 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1102 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 1103 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size)); 1104 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT); 1105 MLX5_SET(wq, wq, page_offset, offset); 1106 1107 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1108 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0); 1109 1110 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp); 1111 1112 kvfree(in); 1113 1114 if (err) 1115 goto err_umem; 1116 1117 return 0; 1118 1119 err_umem: 1120 ib_umem_release(sq->ubuffer.umem); 1121 sq->ubuffer.umem = NULL; 1122 1123 return err; 1124 } 1125 1126 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1127 struct mlx5_ib_sq *sq) 1128 { 1129 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp); 1130 ib_umem_release(sq->ubuffer.umem); 1131 } 1132 1133 static int get_rq_pas_size(void *qpc) 1134 { 1135 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12; 1136 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride); 1137 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size); 1138 u32 page_offset = MLX5_GET(qpc, qpc, page_offset); 1139 u32 po_quanta = 1 << (log_page_size - 6); 1140 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride); 1141 u32 page_size = 1 << log_page_size; 1142 u32 rq_sz_po = rq_sz + (page_offset * po_quanta); 1143 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size; 1144 1145 return rq_num_pas * sizeof(u64); 1146 } 1147 1148 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1149 struct mlx5_ib_rq *rq, void *qpin) 1150 { 1151 struct mlx5_ib_qp *mqp = rq->base.container_mibqp; 1152 __be64 *pas; 1153 __be64 *qp_pas; 1154 void *in; 1155 void *rqc; 1156 void *wq; 1157 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1158 int inlen; 1159 int err; 1160 u32 rq_pas_size = get_rq_pas_size(qpc); 1161 1162 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size; 1163 in = kvzalloc(inlen, GFP_KERNEL); 1164 if (!in) 1165 return -ENOMEM; 1166 1167 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 1168 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING)) 1169 MLX5_SET(rqc, rqc, vsd, 1); 1170 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 1171 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 1172 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 1173 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1174 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv)); 1175 1176 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS) 1177 MLX5_SET(rqc, rqc, scatter_fcs, 1); 1178 1179 wq = MLX5_ADDR_OF(rqc, rqc, wq); 1180 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1181 if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING) 1182 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 1183 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset)); 1184 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1185 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1186 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4); 1187 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size)); 1188 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size)); 1189 1190 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1191 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas); 1192 memcpy(pas, qp_pas, rq_pas_size); 1193 1194 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp); 1195 1196 kvfree(in); 1197 1198 return err; 1199 } 1200 1201 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1202 struct mlx5_ib_rq *rq) 1203 { 1204 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp); 1205 } 1206 1207 static bool tunnel_offload_supported(struct mlx5_core_dev *dev) 1208 { 1209 return (MLX5_CAP_ETH(dev, tunnel_stateless_vxlan) || 1210 MLX5_CAP_ETH(dev, tunnel_stateless_gre) || 1211 MLX5_CAP_ETH(dev, tunnel_stateless_geneve_rx)); 1212 } 1213 1214 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1215 struct mlx5_ib_rq *rq, u32 tdn, 1216 bool tunnel_offload_en) 1217 { 1218 u32 *in; 1219 void *tirc; 1220 int inlen; 1221 int err; 1222 1223 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1224 in = kvzalloc(inlen, GFP_KERNEL); 1225 if (!in) 1226 return -ENOMEM; 1227 1228 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1229 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT); 1230 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn); 1231 MLX5_SET(tirc, tirc, transport_domain, tdn); 1232 if (tunnel_offload_en) 1233 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 1234 1235 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn); 1236 1237 kvfree(in); 1238 1239 return err; 1240 } 1241 1242 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1243 struct mlx5_ib_rq *rq) 1244 { 1245 mlx5_core_destroy_tir(dev->mdev, rq->tirn); 1246 } 1247 1248 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1249 u32 *in, 1250 struct ib_pd *pd) 1251 { 1252 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1253 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1254 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1255 struct ib_uobject *uobj = pd->uobject; 1256 struct ib_ucontext *ucontext = uobj->context; 1257 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext); 1258 int err; 1259 u32 tdn = mucontext->tdn; 1260 1261 if (qp->sq.wqe_cnt) { 1262 err = create_raw_packet_qp_tis(dev, qp, sq, tdn); 1263 if (err) 1264 return err; 1265 1266 err = create_raw_packet_qp_sq(dev, sq, in, pd); 1267 if (err) 1268 goto err_destroy_tis; 1269 1270 sq->base.container_mibqp = qp; 1271 sq->base.mqp.event = mlx5_ib_qp_event; 1272 } 1273 1274 if (qp->rq.wqe_cnt) { 1275 rq->base.container_mibqp = qp; 1276 1277 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING) 1278 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING; 1279 if (qp->flags & MLX5_IB_QP_PCI_WRITE_END_PADDING) 1280 rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING; 1281 err = create_raw_packet_qp_rq(dev, rq, in); 1282 if (err) 1283 goto err_destroy_sq; 1284 1285 1286 err = create_raw_packet_qp_tir(dev, rq, tdn, 1287 qp->tunnel_offload_en); 1288 if (err) 1289 goto err_destroy_rq; 1290 } 1291 1292 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn : 1293 rq->base.mqp.qpn; 1294 1295 return 0; 1296 1297 err_destroy_rq: 1298 destroy_raw_packet_qp_rq(dev, rq); 1299 err_destroy_sq: 1300 if (!qp->sq.wqe_cnt) 1301 return err; 1302 destroy_raw_packet_qp_sq(dev, sq); 1303 err_destroy_tis: 1304 destroy_raw_packet_qp_tis(dev, sq); 1305 1306 return err; 1307 } 1308 1309 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev, 1310 struct mlx5_ib_qp *qp) 1311 { 1312 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1313 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1314 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1315 1316 if (qp->rq.wqe_cnt) { 1317 destroy_raw_packet_qp_tir(dev, rq); 1318 destroy_raw_packet_qp_rq(dev, rq); 1319 } 1320 1321 if (qp->sq.wqe_cnt) { 1322 destroy_raw_packet_qp_sq(dev, sq); 1323 destroy_raw_packet_qp_tis(dev, sq); 1324 } 1325 } 1326 1327 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp, 1328 struct mlx5_ib_raw_packet_qp *raw_packet_qp) 1329 { 1330 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1331 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1332 1333 sq->sq = &qp->sq; 1334 rq->rq = &qp->rq; 1335 sq->doorbell = &qp->db; 1336 rq->doorbell = &qp->db; 1337 } 1338 1339 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1340 { 1341 mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn); 1342 } 1343 1344 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1345 struct ib_pd *pd, 1346 struct ib_qp_init_attr *init_attr, 1347 struct ib_udata *udata) 1348 { 1349 struct ib_uobject *uobj = pd->uobject; 1350 struct ib_ucontext *ucontext = uobj->context; 1351 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext); 1352 struct mlx5_ib_create_qp_resp resp = {}; 1353 int inlen; 1354 int err; 1355 u32 *in; 1356 void *tirc; 1357 void *hfso; 1358 u32 selected_fields = 0; 1359 size_t min_resp_len; 1360 u32 tdn = mucontext->tdn; 1361 struct mlx5_ib_create_qp_rss ucmd = {}; 1362 size_t required_cmd_sz; 1363 1364 if (init_attr->qp_type != IB_QPT_RAW_PACKET) 1365 return -EOPNOTSUPP; 1366 1367 if (init_attr->create_flags || init_attr->send_cq) 1368 return -EINVAL; 1369 1370 min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index); 1371 if (udata->outlen < min_resp_len) 1372 return -EINVAL; 1373 1374 required_cmd_sz = offsetof(typeof(ucmd), flags) + sizeof(ucmd.flags); 1375 if (udata->inlen < required_cmd_sz) { 1376 mlx5_ib_dbg(dev, "invalid inlen\n"); 1377 return -EINVAL; 1378 } 1379 1380 if (udata->inlen > sizeof(ucmd) && 1381 !ib_is_udata_cleared(udata, sizeof(ucmd), 1382 udata->inlen - sizeof(ucmd))) { 1383 mlx5_ib_dbg(dev, "inlen is not supported\n"); 1384 return -EOPNOTSUPP; 1385 } 1386 1387 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 1388 mlx5_ib_dbg(dev, "copy failed\n"); 1389 return -EFAULT; 1390 } 1391 1392 if (ucmd.comp_mask) { 1393 mlx5_ib_dbg(dev, "invalid comp mask\n"); 1394 return -EOPNOTSUPP; 1395 } 1396 1397 if (ucmd.flags & ~MLX5_QP_FLAG_TUNNEL_OFFLOADS) { 1398 mlx5_ib_dbg(dev, "invalid flags\n"); 1399 return -EOPNOTSUPP; 1400 } 1401 1402 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS && 1403 !tunnel_offload_supported(dev->mdev)) { 1404 mlx5_ib_dbg(dev, "tunnel offloads isn't supported\n"); 1405 return -EOPNOTSUPP; 1406 } 1407 1408 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER && 1409 !(ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) { 1410 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n"); 1411 return -EOPNOTSUPP; 1412 } 1413 1414 err = ib_copy_to_udata(udata, &resp, min_resp_len); 1415 if (err) { 1416 mlx5_ib_dbg(dev, "copy failed\n"); 1417 return -EINVAL; 1418 } 1419 1420 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1421 in = kvzalloc(inlen, GFP_KERNEL); 1422 if (!in) 1423 return -ENOMEM; 1424 1425 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1426 MLX5_SET(tirc, tirc, disp_type, 1427 MLX5_TIRC_DISP_TYPE_INDIRECT); 1428 MLX5_SET(tirc, tirc, indirect_table, 1429 init_attr->rwq_ind_tbl->ind_tbl_num); 1430 MLX5_SET(tirc, tirc, transport_domain, tdn); 1431 1432 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1433 1434 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) 1435 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 1436 1437 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER) 1438 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner); 1439 else 1440 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1441 1442 switch (ucmd.rx_hash_function) { 1443 case MLX5_RX_HASH_FUNC_TOEPLITZ: 1444 { 1445 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key); 1446 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key); 1447 1448 if (len != ucmd.rx_key_len) { 1449 err = -EINVAL; 1450 goto err; 1451 } 1452 1453 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ); 1454 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1); 1455 memcpy(rss_key, ucmd.rx_hash_key, len); 1456 break; 1457 } 1458 default: 1459 err = -EOPNOTSUPP; 1460 goto err; 1461 } 1462 1463 if (!ucmd.rx_hash_fields_mask) { 1464 /* special case when this TIR serves as steering entry without hashing */ 1465 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size) 1466 goto create_tir; 1467 err = -EINVAL; 1468 goto err; 1469 } 1470 1471 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1472 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) && 1473 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1474 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) { 1475 err = -EINVAL; 1476 goto err; 1477 } 1478 1479 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */ 1480 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1481 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) 1482 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1483 MLX5_L3_PROT_TYPE_IPV4); 1484 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1485 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1486 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1487 MLX5_L3_PROT_TYPE_IPV6); 1488 1489 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1490 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) && 1491 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1492 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))) { 1493 err = -EINVAL; 1494 goto err; 1495 } 1496 1497 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */ 1498 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1499 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) 1500 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1501 MLX5_L4_PROT_TYPE_TCP); 1502 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1503 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1504 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1505 MLX5_L4_PROT_TYPE_UDP); 1506 1507 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1508 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6)) 1509 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP; 1510 1511 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) || 1512 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1513 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP; 1514 1515 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1516 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP)) 1517 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT; 1518 1519 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) || 1520 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1521 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT; 1522 1523 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields); 1524 1525 create_tir: 1526 err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn); 1527 1528 if (err) 1529 goto err; 1530 1531 kvfree(in); 1532 /* qpn is reserved for that QP */ 1533 qp->trans_qp.base.mqp.qpn = 0; 1534 qp->flags |= MLX5_IB_QP_RSS; 1535 return 0; 1536 1537 err: 1538 kvfree(in); 1539 return err; 1540 } 1541 1542 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd, 1543 struct ib_qp_init_attr *init_attr, 1544 struct ib_udata *udata, struct mlx5_ib_qp *qp) 1545 { 1546 struct mlx5_ib_resources *devr = &dev->devr; 1547 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 1548 struct mlx5_core_dev *mdev = dev->mdev; 1549 struct mlx5_ib_create_qp_resp resp; 1550 struct mlx5_ib_cq *send_cq; 1551 struct mlx5_ib_cq *recv_cq; 1552 unsigned long flags; 1553 u32 uidx = MLX5_IB_DEFAULT_UIDX; 1554 struct mlx5_ib_create_qp ucmd; 1555 struct mlx5_ib_qp_base *base; 1556 void *qpc; 1557 u32 *in; 1558 int err; 1559 1560 mutex_init(&qp->mutex); 1561 spin_lock_init(&qp->sq.lock); 1562 spin_lock_init(&qp->rq.lock); 1563 1564 if (init_attr->rwq_ind_tbl) { 1565 if (!udata) 1566 return -ENOSYS; 1567 1568 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata); 1569 return err; 1570 } 1571 1572 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) { 1573 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) { 1574 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n"); 1575 return -EINVAL; 1576 } else { 1577 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK; 1578 } 1579 } 1580 1581 if (init_attr->create_flags & 1582 (IB_QP_CREATE_CROSS_CHANNEL | 1583 IB_QP_CREATE_MANAGED_SEND | 1584 IB_QP_CREATE_MANAGED_RECV)) { 1585 if (!MLX5_CAP_GEN(mdev, cd)) { 1586 mlx5_ib_dbg(dev, "cross-channel isn't supported\n"); 1587 return -EINVAL; 1588 } 1589 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL) 1590 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL; 1591 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND) 1592 qp->flags |= MLX5_IB_QP_MANAGED_SEND; 1593 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV) 1594 qp->flags |= MLX5_IB_QP_MANAGED_RECV; 1595 } 1596 1597 if (init_attr->qp_type == IB_QPT_UD && 1598 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) 1599 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 1600 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n"); 1601 return -EOPNOTSUPP; 1602 } 1603 1604 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) { 1605 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 1606 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs"); 1607 return -EOPNOTSUPP; 1608 } 1609 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) || 1610 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) { 1611 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n"); 1612 return -EOPNOTSUPP; 1613 } 1614 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS; 1615 } 1616 1617 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 1618 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 1619 1620 if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) { 1621 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 1622 MLX5_CAP_ETH(dev->mdev, vlan_cap)) || 1623 (init_attr->qp_type != IB_QPT_RAW_PACKET)) 1624 return -EOPNOTSUPP; 1625 qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING; 1626 } 1627 1628 if (pd && pd->uobject) { 1629 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) { 1630 mlx5_ib_dbg(dev, "copy failed\n"); 1631 return -EFAULT; 1632 } 1633 1634 err = get_qp_user_index(to_mucontext(pd->uobject->context), 1635 &ucmd, udata->inlen, &uidx); 1636 if (err) 1637 return err; 1638 1639 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE); 1640 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE); 1641 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) { 1642 if (init_attr->qp_type != IB_QPT_RAW_PACKET || 1643 !tunnel_offload_supported(mdev)) { 1644 mlx5_ib_dbg(dev, "Tunnel offload isn't supported\n"); 1645 return -EOPNOTSUPP; 1646 } 1647 qp->tunnel_offload_en = true; 1648 } 1649 1650 if (init_attr->create_flags & IB_QP_CREATE_SOURCE_QPN) { 1651 if (init_attr->qp_type != IB_QPT_UD || 1652 (MLX5_CAP_GEN(dev->mdev, port_type) != 1653 MLX5_CAP_PORT_TYPE_IB) || 1654 !mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) { 1655 mlx5_ib_dbg(dev, "Source QP option isn't supported\n"); 1656 return -EOPNOTSUPP; 1657 } 1658 1659 qp->flags |= MLX5_IB_QP_UNDERLAY; 1660 qp->underlay_qpn = init_attr->source_qpn; 1661 } 1662 } else { 1663 qp->wq_sig = !!wq_signature; 1664 } 1665 1666 base = (init_attr->qp_type == IB_QPT_RAW_PACKET || 1667 qp->flags & MLX5_IB_QP_UNDERLAY) ? 1668 &qp->raw_packet_qp.rq.base : 1669 &qp->trans_qp.base; 1670 1671 qp->has_rq = qp_has_rq(init_attr); 1672 err = set_rq_size(dev, &init_attr->cap, qp->has_rq, 1673 qp, (pd && pd->uobject) ? &ucmd : NULL); 1674 if (err) { 1675 mlx5_ib_dbg(dev, "err %d\n", err); 1676 return err; 1677 } 1678 1679 if (pd) { 1680 if (pd->uobject) { 1681 __u32 max_wqes = 1682 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 1683 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count); 1684 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift || 1685 ucmd.rq_wqe_count != qp->rq.wqe_cnt) { 1686 mlx5_ib_dbg(dev, "invalid rq params\n"); 1687 return -EINVAL; 1688 } 1689 if (ucmd.sq_wqe_count > max_wqes) { 1690 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n", 1691 ucmd.sq_wqe_count, max_wqes); 1692 return -EINVAL; 1693 } 1694 if (init_attr->create_flags & 1695 mlx5_ib_create_qp_sqpn_qp1()) { 1696 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n"); 1697 return -EINVAL; 1698 } 1699 err = create_user_qp(dev, pd, qp, udata, init_attr, &in, 1700 &resp, &inlen, base); 1701 if (err) 1702 mlx5_ib_dbg(dev, "err %d\n", err); 1703 } else { 1704 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen, 1705 base); 1706 if (err) 1707 mlx5_ib_dbg(dev, "err %d\n", err); 1708 } 1709 1710 if (err) 1711 return err; 1712 } else { 1713 in = kvzalloc(inlen, GFP_KERNEL); 1714 if (!in) 1715 return -ENOMEM; 1716 1717 qp->create_type = MLX5_QP_EMPTY; 1718 } 1719 1720 if (is_sqp(init_attr->qp_type)) 1721 qp->port = init_attr->port_num; 1722 1723 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 1724 1725 MLX5_SET(qpc, qpc, st, to_mlx5_st(init_attr->qp_type)); 1726 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 1727 1728 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR) 1729 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn); 1730 else 1731 MLX5_SET(qpc, qpc, latency_sensitive, 1); 1732 1733 1734 if (qp->wq_sig) 1735 MLX5_SET(qpc, qpc, wq_signature, 1); 1736 1737 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 1738 MLX5_SET(qpc, qpc, block_lb_mc, 1); 1739 1740 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 1741 MLX5_SET(qpc, qpc, cd_master, 1); 1742 if (qp->flags & MLX5_IB_QP_MANAGED_SEND) 1743 MLX5_SET(qpc, qpc, cd_slave_send, 1); 1744 if (qp->flags & MLX5_IB_QP_MANAGED_RECV) 1745 MLX5_SET(qpc, qpc, cd_slave_receive, 1); 1746 1747 if (qp->scat_cqe && is_connected(init_attr->qp_type)) { 1748 int rcqe_sz; 1749 int scqe_sz; 1750 1751 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq); 1752 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq); 1753 1754 if (rcqe_sz == 128) 1755 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE); 1756 else 1757 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE); 1758 1759 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) { 1760 if (scqe_sz == 128) 1761 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE); 1762 else 1763 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE); 1764 } 1765 } 1766 1767 if (qp->rq.wqe_cnt) { 1768 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); 1769 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); 1770 } 1771 1772 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr)); 1773 1774 if (qp->sq.wqe_cnt) { 1775 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); 1776 } else { 1777 MLX5_SET(qpc, qpc, no_sq, 1); 1778 if (init_attr->srq && 1779 init_attr->srq->srq_type == IB_SRQT_TM) 1780 MLX5_SET(qpc, qpc, offload_type, 1781 MLX5_QPC_OFFLOAD_TYPE_RNDV); 1782 } 1783 1784 /* Set default resources */ 1785 switch (init_attr->qp_type) { 1786 case IB_QPT_XRC_TGT: 1787 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 1788 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn); 1789 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 1790 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn); 1791 break; 1792 case IB_QPT_XRC_INI: 1793 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 1794 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn); 1795 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 1796 break; 1797 default: 1798 if (init_attr->srq) { 1799 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn); 1800 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn); 1801 } else { 1802 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn); 1803 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn); 1804 } 1805 } 1806 1807 if (init_attr->send_cq) 1808 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn); 1809 1810 if (init_attr->recv_cq) 1811 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn); 1812 1813 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 1814 1815 /* 0xffffff means we ask to work with cqe version 0 */ 1816 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 1817 MLX5_SET(qpc, qpc, user_index, uidx); 1818 1819 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */ 1820 if (init_attr->qp_type == IB_QPT_UD && 1821 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) { 1822 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1); 1823 qp->flags |= MLX5_IB_QP_LSO; 1824 } 1825 1826 if (init_attr->create_flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) { 1827 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) { 1828 mlx5_ib_dbg(dev, "scatter end padding is not supported\n"); 1829 err = -EOPNOTSUPP; 1830 goto err; 1831 } else if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 1832 MLX5_SET(qpc, qpc, end_padding_mode, 1833 MLX5_WQ_END_PAD_MODE_ALIGN); 1834 } else { 1835 qp->flags |= MLX5_IB_QP_PCI_WRITE_END_PADDING; 1836 } 1837 } 1838 1839 if (init_attr->qp_type == IB_QPT_RAW_PACKET || 1840 qp->flags & MLX5_IB_QP_UNDERLAY) { 1841 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr; 1842 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp); 1843 err = create_raw_packet_qp(dev, qp, in, pd); 1844 } else { 1845 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen); 1846 } 1847 1848 if (err) { 1849 mlx5_ib_dbg(dev, "create qp failed\n"); 1850 goto err_create; 1851 } 1852 1853 kvfree(in); 1854 1855 base->container_mibqp = qp; 1856 base->mqp.event = mlx5_ib_qp_event; 1857 1858 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq, 1859 &send_cq, &recv_cq); 1860 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 1861 mlx5_ib_lock_cqs(send_cq, recv_cq); 1862 /* Maintain device to QPs access, needed for further handling via reset 1863 * flow 1864 */ 1865 list_add_tail(&qp->qps_list, &dev->qp_list); 1866 /* Maintain CQ to QPs access, needed for further handling via reset flow 1867 */ 1868 if (send_cq) 1869 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); 1870 if (recv_cq) 1871 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); 1872 mlx5_ib_unlock_cqs(send_cq, recv_cq); 1873 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 1874 1875 return 0; 1876 1877 err_create: 1878 if (qp->create_type == MLX5_QP_USER) 1879 destroy_qp_user(dev, pd, qp, base); 1880 else if (qp->create_type == MLX5_QP_KERNEL) 1881 destroy_qp_kernel(dev, qp); 1882 1883 err: 1884 kvfree(in); 1885 return err; 1886 } 1887 1888 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 1889 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 1890 { 1891 if (send_cq) { 1892 if (recv_cq) { 1893 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1894 spin_lock(&send_cq->lock); 1895 spin_lock_nested(&recv_cq->lock, 1896 SINGLE_DEPTH_NESTING); 1897 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 1898 spin_lock(&send_cq->lock); 1899 __acquire(&recv_cq->lock); 1900 } else { 1901 spin_lock(&recv_cq->lock); 1902 spin_lock_nested(&send_cq->lock, 1903 SINGLE_DEPTH_NESTING); 1904 } 1905 } else { 1906 spin_lock(&send_cq->lock); 1907 __acquire(&recv_cq->lock); 1908 } 1909 } else if (recv_cq) { 1910 spin_lock(&recv_cq->lock); 1911 __acquire(&send_cq->lock); 1912 } else { 1913 __acquire(&send_cq->lock); 1914 __acquire(&recv_cq->lock); 1915 } 1916 } 1917 1918 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 1919 __releases(&send_cq->lock) __releases(&recv_cq->lock) 1920 { 1921 if (send_cq) { 1922 if (recv_cq) { 1923 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1924 spin_unlock(&recv_cq->lock); 1925 spin_unlock(&send_cq->lock); 1926 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 1927 __release(&recv_cq->lock); 1928 spin_unlock(&send_cq->lock); 1929 } else { 1930 spin_unlock(&send_cq->lock); 1931 spin_unlock(&recv_cq->lock); 1932 } 1933 } else { 1934 __release(&recv_cq->lock); 1935 spin_unlock(&send_cq->lock); 1936 } 1937 } else if (recv_cq) { 1938 __release(&send_cq->lock); 1939 spin_unlock(&recv_cq->lock); 1940 } else { 1941 __release(&recv_cq->lock); 1942 __release(&send_cq->lock); 1943 } 1944 } 1945 1946 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp) 1947 { 1948 return to_mpd(qp->ibqp.pd); 1949 } 1950 1951 static void get_cqs(enum ib_qp_type qp_type, 1952 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 1953 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq) 1954 { 1955 switch (qp_type) { 1956 case IB_QPT_XRC_TGT: 1957 *send_cq = NULL; 1958 *recv_cq = NULL; 1959 break; 1960 case MLX5_IB_QPT_REG_UMR: 1961 case IB_QPT_XRC_INI: 1962 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 1963 *recv_cq = NULL; 1964 break; 1965 1966 case IB_QPT_SMI: 1967 case MLX5_IB_QPT_HW_GSI: 1968 case IB_QPT_RC: 1969 case IB_QPT_UC: 1970 case IB_QPT_UD: 1971 case IB_QPT_RAW_IPV6: 1972 case IB_QPT_RAW_ETHERTYPE: 1973 case IB_QPT_RAW_PACKET: 1974 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 1975 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL; 1976 break; 1977 1978 case IB_QPT_MAX: 1979 default: 1980 *send_cq = NULL; 1981 *recv_cq = NULL; 1982 break; 1983 } 1984 } 1985 1986 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1987 const struct mlx5_modify_raw_qp_param *raw_qp_param, 1988 u8 lag_tx_affinity); 1989 1990 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1991 { 1992 struct mlx5_ib_cq *send_cq, *recv_cq; 1993 struct mlx5_ib_qp_base *base; 1994 unsigned long flags; 1995 int err; 1996 1997 if (qp->ibqp.rwq_ind_tbl) { 1998 destroy_rss_raw_qp_tir(dev, qp); 1999 return; 2000 } 2001 2002 base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 2003 qp->flags & MLX5_IB_QP_UNDERLAY) ? 2004 &qp->raw_packet_qp.rq.base : 2005 &qp->trans_qp.base; 2006 2007 if (qp->state != IB_QPS_RESET) { 2008 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET && 2009 !(qp->flags & MLX5_IB_QP_UNDERLAY)) { 2010 err = mlx5_core_qp_modify(dev->mdev, 2011 MLX5_CMD_OP_2RST_QP, 0, 2012 NULL, &base->mqp); 2013 } else { 2014 struct mlx5_modify_raw_qp_param raw_qp_param = { 2015 .operation = MLX5_CMD_OP_2RST_QP 2016 }; 2017 2018 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0); 2019 } 2020 if (err) 2021 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n", 2022 base->mqp.qpn); 2023 } 2024 2025 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 2026 &send_cq, &recv_cq); 2027 2028 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2029 mlx5_ib_lock_cqs(send_cq, recv_cq); 2030 /* del from lists under both locks above to protect reset flow paths */ 2031 list_del(&qp->qps_list); 2032 if (send_cq) 2033 list_del(&qp->cq_send_list); 2034 2035 if (recv_cq) 2036 list_del(&qp->cq_recv_list); 2037 2038 if (qp->create_type == MLX5_QP_KERNEL) { 2039 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 2040 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL); 2041 if (send_cq != recv_cq) 2042 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn, 2043 NULL); 2044 } 2045 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2046 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2047 2048 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 2049 qp->flags & MLX5_IB_QP_UNDERLAY) { 2050 destroy_raw_packet_qp(dev, qp); 2051 } else { 2052 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp); 2053 if (err) 2054 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n", 2055 base->mqp.qpn); 2056 } 2057 2058 if (qp->create_type == MLX5_QP_KERNEL) 2059 destroy_qp_kernel(dev, qp); 2060 else if (qp->create_type == MLX5_QP_USER) 2061 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base); 2062 } 2063 2064 static const char *ib_qp_type_str(enum ib_qp_type type) 2065 { 2066 switch (type) { 2067 case IB_QPT_SMI: 2068 return "IB_QPT_SMI"; 2069 case IB_QPT_GSI: 2070 return "IB_QPT_GSI"; 2071 case IB_QPT_RC: 2072 return "IB_QPT_RC"; 2073 case IB_QPT_UC: 2074 return "IB_QPT_UC"; 2075 case IB_QPT_UD: 2076 return "IB_QPT_UD"; 2077 case IB_QPT_RAW_IPV6: 2078 return "IB_QPT_RAW_IPV6"; 2079 case IB_QPT_RAW_ETHERTYPE: 2080 return "IB_QPT_RAW_ETHERTYPE"; 2081 case IB_QPT_XRC_INI: 2082 return "IB_QPT_XRC_INI"; 2083 case IB_QPT_XRC_TGT: 2084 return "IB_QPT_XRC_TGT"; 2085 case IB_QPT_RAW_PACKET: 2086 return "IB_QPT_RAW_PACKET"; 2087 case MLX5_IB_QPT_REG_UMR: 2088 return "MLX5_IB_QPT_REG_UMR"; 2089 case IB_QPT_MAX: 2090 default: 2091 return "Invalid QP type"; 2092 } 2093 } 2094 2095 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, 2096 struct ib_qp_init_attr *init_attr, 2097 struct ib_udata *udata) 2098 { 2099 struct mlx5_ib_dev *dev; 2100 struct mlx5_ib_qp *qp; 2101 u16 xrcdn = 0; 2102 int err; 2103 2104 if (pd) { 2105 dev = to_mdev(pd->device); 2106 2107 if (init_attr->qp_type == IB_QPT_RAW_PACKET) { 2108 if (!pd->uobject) { 2109 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n"); 2110 return ERR_PTR(-EINVAL); 2111 } else if (!to_mucontext(pd->uobject->context)->cqe_version) { 2112 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n"); 2113 return ERR_PTR(-EINVAL); 2114 } 2115 } 2116 } else { 2117 /* being cautious here */ 2118 if (init_attr->qp_type != IB_QPT_XRC_TGT && 2119 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) { 2120 pr_warn("%s: no PD for transport %s\n", __func__, 2121 ib_qp_type_str(init_attr->qp_type)); 2122 return ERR_PTR(-EINVAL); 2123 } 2124 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device); 2125 } 2126 2127 switch (init_attr->qp_type) { 2128 case IB_QPT_XRC_TGT: 2129 case IB_QPT_XRC_INI: 2130 if (!MLX5_CAP_GEN(dev->mdev, xrc)) { 2131 mlx5_ib_dbg(dev, "XRC not supported\n"); 2132 return ERR_PTR(-ENOSYS); 2133 } 2134 init_attr->recv_cq = NULL; 2135 if (init_attr->qp_type == IB_QPT_XRC_TGT) { 2136 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn; 2137 init_attr->send_cq = NULL; 2138 } 2139 2140 /* fall through */ 2141 case IB_QPT_RAW_PACKET: 2142 case IB_QPT_RC: 2143 case IB_QPT_UC: 2144 case IB_QPT_UD: 2145 case IB_QPT_SMI: 2146 case MLX5_IB_QPT_HW_GSI: 2147 case MLX5_IB_QPT_REG_UMR: 2148 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 2149 if (!qp) 2150 return ERR_PTR(-ENOMEM); 2151 2152 err = create_qp_common(dev, pd, init_attr, udata, qp); 2153 if (err) { 2154 mlx5_ib_dbg(dev, "create_qp_common failed\n"); 2155 kfree(qp); 2156 return ERR_PTR(err); 2157 } 2158 2159 if (is_qp0(init_attr->qp_type)) 2160 qp->ibqp.qp_num = 0; 2161 else if (is_qp1(init_attr->qp_type)) 2162 qp->ibqp.qp_num = 1; 2163 else 2164 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn; 2165 2166 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n", 2167 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn, 2168 init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1, 2169 init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1); 2170 2171 qp->trans_qp.xrcdn = xrcdn; 2172 2173 break; 2174 2175 case IB_QPT_GSI: 2176 return mlx5_ib_gsi_create_qp(pd, init_attr); 2177 2178 case IB_QPT_RAW_IPV6: 2179 case IB_QPT_RAW_ETHERTYPE: 2180 case IB_QPT_MAX: 2181 default: 2182 mlx5_ib_dbg(dev, "unsupported qp type %d\n", 2183 init_attr->qp_type); 2184 /* Don't support raw QPs */ 2185 return ERR_PTR(-EINVAL); 2186 } 2187 2188 return &qp->ibqp; 2189 } 2190 2191 int mlx5_ib_destroy_qp(struct ib_qp *qp) 2192 { 2193 struct mlx5_ib_dev *dev = to_mdev(qp->device); 2194 struct mlx5_ib_qp *mqp = to_mqp(qp); 2195 2196 if (unlikely(qp->qp_type == IB_QPT_GSI)) 2197 return mlx5_ib_gsi_destroy_qp(qp); 2198 2199 destroy_qp_common(dev, mqp); 2200 2201 kfree(mqp); 2202 2203 return 0; 2204 } 2205 2206 static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr, 2207 int attr_mask) 2208 { 2209 u32 hw_access_flags = 0; 2210 u8 dest_rd_atomic; 2211 u32 access_flags; 2212 2213 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 2214 dest_rd_atomic = attr->max_dest_rd_atomic; 2215 else 2216 dest_rd_atomic = qp->trans_qp.resp_depth; 2217 2218 if (attr_mask & IB_QP_ACCESS_FLAGS) 2219 access_flags = attr->qp_access_flags; 2220 else 2221 access_flags = qp->trans_qp.atomic_rd_en; 2222 2223 if (!dest_rd_atomic) 2224 access_flags &= IB_ACCESS_REMOTE_WRITE; 2225 2226 if (access_flags & IB_ACCESS_REMOTE_READ) 2227 hw_access_flags |= MLX5_QP_BIT_RRE; 2228 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) 2229 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX); 2230 if (access_flags & IB_ACCESS_REMOTE_WRITE) 2231 hw_access_flags |= MLX5_QP_BIT_RWE; 2232 2233 return cpu_to_be32(hw_access_flags); 2234 } 2235 2236 enum { 2237 MLX5_PATH_FLAG_FL = 1 << 0, 2238 MLX5_PATH_FLAG_FREE_AR = 1 << 1, 2239 MLX5_PATH_FLAG_COUNTER = 1 << 2, 2240 }; 2241 2242 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate) 2243 { 2244 if (rate == IB_RATE_PORT_CURRENT) { 2245 return 0; 2246 } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) { 2247 return -EINVAL; 2248 } else { 2249 while (rate != IB_RATE_2_5_GBPS && 2250 !(1 << (rate + MLX5_STAT_RATE_OFFSET) & 2251 MLX5_CAP_GEN(dev->mdev, stat_rate_support))) 2252 --rate; 2253 } 2254 2255 return rate + MLX5_STAT_RATE_OFFSET; 2256 } 2257 2258 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev, 2259 struct mlx5_ib_sq *sq, u8 sl) 2260 { 2261 void *in; 2262 void *tisc; 2263 int inlen; 2264 int err; 2265 2266 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 2267 in = kvzalloc(inlen, GFP_KERNEL); 2268 if (!in) 2269 return -ENOMEM; 2270 2271 MLX5_SET(modify_tis_in, in, bitmask.prio, 1); 2272 2273 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 2274 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1)); 2275 2276 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen); 2277 2278 kvfree(in); 2279 2280 return err; 2281 } 2282 2283 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev, 2284 struct mlx5_ib_sq *sq, u8 tx_affinity) 2285 { 2286 void *in; 2287 void *tisc; 2288 int inlen; 2289 int err; 2290 2291 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 2292 in = kvzalloc(inlen, GFP_KERNEL); 2293 if (!in) 2294 return -ENOMEM; 2295 2296 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1); 2297 2298 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 2299 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity); 2300 2301 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen); 2302 2303 kvfree(in); 2304 2305 return err; 2306 } 2307 2308 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2309 const struct rdma_ah_attr *ah, 2310 struct mlx5_qp_path *path, u8 port, int attr_mask, 2311 u32 path_flags, const struct ib_qp_attr *attr, 2312 bool alt) 2313 { 2314 const struct ib_global_route *grh = rdma_ah_read_grh(ah); 2315 int err; 2316 enum ib_gid_type gid_type; 2317 u8 ah_flags = rdma_ah_get_ah_flags(ah); 2318 u8 sl = rdma_ah_get_sl(ah); 2319 2320 if (attr_mask & IB_QP_PKEY_INDEX) 2321 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index : 2322 attr->pkey_index); 2323 2324 if (ah_flags & IB_AH_GRH) { 2325 if (grh->sgid_index >= 2326 dev->mdev->port_caps[port - 1].gid_table_len) { 2327 pr_err("sgid_index (%u) too large. max is %d\n", 2328 grh->sgid_index, 2329 dev->mdev->port_caps[port - 1].gid_table_len); 2330 return -EINVAL; 2331 } 2332 } 2333 2334 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) { 2335 if (!(ah_flags & IB_AH_GRH)) 2336 return -EINVAL; 2337 err = mlx5_get_roce_gid_type(dev, port, grh->sgid_index, 2338 &gid_type); 2339 if (err) 2340 return err; 2341 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac)); 2342 path->udp_sport = mlx5_get_roce_udp_sport(dev, port, 2343 grh->sgid_index); 2344 path->dci_cfi_prio_sl = (sl & 0x7) << 4; 2345 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) 2346 path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f; 2347 } else { 2348 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0; 2349 path->fl_free_ar |= 2350 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0; 2351 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah)); 2352 path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f; 2353 if (ah_flags & IB_AH_GRH) 2354 path->grh_mlid |= 1 << 7; 2355 path->dci_cfi_prio_sl = sl & 0xf; 2356 } 2357 2358 if (ah_flags & IB_AH_GRH) { 2359 path->mgid_index = grh->sgid_index; 2360 path->hop_limit = grh->hop_limit; 2361 path->tclass_flowlabel = 2362 cpu_to_be32((grh->traffic_class << 20) | 2363 (grh->flow_label)); 2364 memcpy(path->rgid, grh->dgid.raw, 16); 2365 } 2366 2367 err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah)); 2368 if (err < 0) 2369 return err; 2370 path->static_rate = err; 2371 path->port = port; 2372 2373 if (attr_mask & IB_QP_TIMEOUT) 2374 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3; 2375 2376 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt) 2377 return modify_raw_packet_eth_prio(dev->mdev, 2378 &qp->raw_packet_qp.sq, 2379 sl & 0xf); 2380 2381 return 0; 2382 } 2383 2384 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = { 2385 [MLX5_QP_STATE_INIT] = { 2386 [MLX5_QP_STATE_INIT] = { 2387 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 2388 MLX5_QP_OPTPAR_RAE | 2389 MLX5_QP_OPTPAR_RWE | 2390 MLX5_QP_OPTPAR_PKEY_INDEX | 2391 MLX5_QP_OPTPAR_PRI_PORT, 2392 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 2393 MLX5_QP_OPTPAR_PKEY_INDEX | 2394 MLX5_QP_OPTPAR_PRI_PORT, 2395 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 2396 MLX5_QP_OPTPAR_Q_KEY | 2397 MLX5_QP_OPTPAR_PRI_PORT, 2398 }, 2399 [MLX5_QP_STATE_RTR] = { 2400 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2401 MLX5_QP_OPTPAR_RRE | 2402 MLX5_QP_OPTPAR_RAE | 2403 MLX5_QP_OPTPAR_RWE | 2404 MLX5_QP_OPTPAR_PKEY_INDEX, 2405 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2406 MLX5_QP_OPTPAR_RWE | 2407 MLX5_QP_OPTPAR_PKEY_INDEX, 2408 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 2409 MLX5_QP_OPTPAR_Q_KEY, 2410 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX | 2411 MLX5_QP_OPTPAR_Q_KEY, 2412 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2413 MLX5_QP_OPTPAR_RRE | 2414 MLX5_QP_OPTPAR_RAE | 2415 MLX5_QP_OPTPAR_RWE | 2416 MLX5_QP_OPTPAR_PKEY_INDEX, 2417 }, 2418 }, 2419 [MLX5_QP_STATE_RTR] = { 2420 [MLX5_QP_STATE_RTS] = { 2421 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2422 MLX5_QP_OPTPAR_RRE | 2423 MLX5_QP_OPTPAR_RAE | 2424 MLX5_QP_OPTPAR_RWE | 2425 MLX5_QP_OPTPAR_PM_STATE | 2426 MLX5_QP_OPTPAR_RNR_TIMEOUT, 2427 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2428 MLX5_QP_OPTPAR_RWE | 2429 MLX5_QP_OPTPAR_PM_STATE, 2430 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 2431 }, 2432 }, 2433 [MLX5_QP_STATE_RTS] = { 2434 [MLX5_QP_STATE_RTS] = { 2435 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 2436 MLX5_QP_OPTPAR_RAE | 2437 MLX5_QP_OPTPAR_RWE | 2438 MLX5_QP_OPTPAR_RNR_TIMEOUT | 2439 MLX5_QP_OPTPAR_PM_STATE | 2440 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 2441 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 2442 MLX5_QP_OPTPAR_PM_STATE | 2443 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 2444 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY | 2445 MLX5_QP_OPTPAR_SRQN | 2446 MLX5_QP_OPTPAR_CQN_RCV, 2447 }, 2448 }, 2449 [MLX5_QP_STATE_SQER] = { 2450 [MLX5_QP_STATE_RTS] = { 2451 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 2452 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY, 2453 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE, 2454 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 2455 MLX5_QP_OPTPAR_RWE | 2456 MLX5_QP_OPTPAR_RAE | 2457 MLX5_QP_OPTPAR_RRE, 2458 }, 2459 }, 2460 }; 2461 2462 static int ib_nr_to_mlx5_nr(int ib_mask) 2463 { 2464 switch (ib_mask) { 2465 case IB_QP_STATE: 2466 return 0; 2467 case IB_QP_CUR_STATE: 2468 return 0; 2469 case IB_QP_EN_SQD_ASYNC_NOTIFY: 2470 return 0; 2471 case IB_QP_ACCESS_FLAGS: 2472 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE | 2473 MLX5_QP_OPTPAR_RAE; 2474 case IB_QP_PKEY_INDEX: 2475 return MLX5_QP_OPTPAR_PKEY_INDEX; 2476 case IB_QP_PORT: 2477 return MLX5_QP_OPTPAR_PRI_PORT; 2478 case IB_QP_QKEY: 2479 return MLX5_QP_OPTPAR_Q_KEY; 2480 case IB_QP_AV: 2481 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH | 2482 MLX5_QP_OPTPAR_PRI_PORT; 2483 case IB_QP_PATH_MTU: 2484 return 0; 2485 case IB_QP_TIMEOUT: 2486 return MLX5_QP_OPTPAR_ACK_TIMEOUT; 2487 case IB_QP_RETRY_CNT: 2488 return MLX5_QP_OPTPAR_RETRY_COUNT; 2489 case IB_QP_RNR_RETRY: 2490 return MLX5_QP_OPTPAR_RNR_RETRY; 2491 case IB_QP_RQ_PSN: 2492 return 0; 2493 case IB_QP_MAX_QP_RD_ATOMIC: 2494 return MLX5_QP_OPTPAR_SRA_MAX; 2495 case IB_QP_ALT_PATH: 2496 return MLX5_QP_OPTPAR_ALT_ADDR_PATH; 2497 case IB_QP_MIN_RNR_TIMER: 2498 return MLX5_QP_OPTPAR_RNR_TIMEOUT; 2499 case IB_QP_SQ_PSN: 2500 return 0; 2501 case IB_QP_MAX_DEST_RD_ATOMIC: 2502 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE | 2503 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE; 2504 case IB_QP_PATH_MIG_STATE: 2505 return MLX5_QP_OPTPAR_PM_STATE; 2506 case IB_QP_CAP: 2507 return 0; 2508 case IB_QP_DEST_QPN: 2509 return 0; 2510 } 2511 return 0; 2512 } 2513 2514 static int ib_mask_to_mlx5_opt(int ib_mask) 2515 { 2516 int result = 0; 2517 int i; 2518 2519 for (i = 0; i < 8 * sizeof(int); i++) { 2520 if ((1 << i) & ib_mask) 2521 result |= ib_nr_to_mlx5_nr(1 << i); 2522 } 2523 2524 return result; 2525 } 2526 2527 static int modify_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 2528 struct mlx5_ib_rq *rq, int new_state, 2529 const struct mlx5_modify_raw_qp_param *raw_qp_param) 2530 { 2531 void *in; 2532 void *rqc; 2533 int inlen; 2534 int err; 2535 2536 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 2537 in = kvzalloc(inlen, GFP_KERNEL); 2538 if (!in) 2539 return -ENOMEM; 2540 2541 MLX5_SET(modify_rq_in, in, rq_state, rq->state); 2542 2543 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 2544 MLX5_SET(rqc, rqc, state, new_state); 2545 2546 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) { 2547 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 2548 MLX5_SET64(modify_rq_in, in, modify_bitmask, 2549 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 2550 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id); 2551 } else 2552 pr_info_once("%s: RAW PACKET QP counters are not supported on current FW\n", 2553 dev->ib_dev.name); 2554 } 2555 2556 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen); 2557 if (err) 2558 goto out; 2559 2560 rq->state = new_state; 2561 2562 out: 2563 kvfree(in); 2564 return err; 2565 } 2566 2567 static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev, 2568 struct mlx5_ib_sq *sq, 2569 int new_state, 2570 const struct mlx5_modify_raw_qp_param *raw_qp_param) 2571 { 2572 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp; 2573 u32 old_rate = ibqp->rate_limit; 2574 u32 new_rate = old_rate; 2575 u16 rl_index = 0; 2576 void *in; 2577 void *sqc; 2578 int inlen; 2579 int err; 2580 2581 inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 2582 in = kvzalloc(inlen, GFP_KERNEL); 2583 if (!in) 2584 return -ENOMEM; 2585 2586 MLX5_SET(modify_sq_in, in, sq_state, sq->state); 2587 2588 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 2589 MLX5_SET(sqc, sqc, state, new_state); 2590 2591 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) { 2592 if (new_state != MLX5_SQC_STATE_RDY) 2593 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n", 2594 __func__); 2595 else 2596 new_rate = raw_qp_param->rate_limit; 2597 } 2598 2599 if (old_rate != new_rate) { 2600 if (new_rate) { 2601 err = mlx5_rl_add_rate(dev, new_rate, &rl_index); 2602 if (err) { 2603 pr_err("Failed configuring rate %u: %d\n", 2604 new_rate, err); 2605 goto out; 2606 } 2607 } 2608 2609 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1); 2610 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index); 2611 } 2612 2613 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen); 2614 if (err) { 2615 /* Remove new rate from table if failed */ 2616 if (new_rate && 2617 old_rate != new_rate) 2618 mlx5_rl_remove_rate(dev, new_rate); 2619 goto out; 2620 } 2621 2622 /* Only remove the old rate after new rate was set */ 2623 if ((old_rate && 2624 (old_rate != new_rate)) || 2625 (new_state != MLX5_SQC_STATE_RDY)) 2626 mlx5_rl_remove_rate(dev, old_rate); 2627 2628 ibqp->rate_limit = new_rate; 2629 sq->state = new_state; 2630 2631 out: 2632 kvfree(in); 2633 return err; 2634 } 2635 2636 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2637 const struct mlx5_modify_raw_qp_param *raw_qp_param, 2638 u8 tx_affinity) 2639 { 2640 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 2641 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 2642 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 2643 int modify_rq = !!qp->rq.wqe_cnt; 2644 int modify_sq = !!qp->sq.wqe_cnt; 2645 int rq_state; 2646 int sq_state; 2647 int err; 2648 2649 switch (raw_qp_param->operation) { 2650 case MLX5_CMD_OP_RST2INIT_QP: 2651 rq_state = MLX5_RQC_STATE_RDY; 2652 sq_state = MLX5_SQC_STATE_RDY; 2653 break; 2654 case MLX5_CMD_OP_2ERR_QP: 2655 rq_state = MLX5_RQC_STATE_ERR; 2656 sq_state = MLX5_SQC_STATE_ERR; 2657 break; 2658 case MLX5_CMD_OP_2RST_QP: 2659 rq_state = MLX5_RQC_STATE_RST; 2660 sq_state = MLX5_SQC_STATE_RST; 2661 break; 2662 case MLX5_CMD_OP_RTR2RTS_QP: 2663 case MLX5_CMD_OP_RTS2RTS_QP: 2664 if (raw_qp_param->set_mask == 2665 MLX5_RAW_QP_RATE_LIMIT) { 2666 modify_rq = 0; 2667 sq_state = sq->state; 2668 } else { 2669 return raw_qp_param->set_mask ? -EINVAL : 0; 2670 } 2671 break; 2672 case MLX5_CMD_OP_INIT2INIT_QP: 2673 case MLX5_CMD_OP_INIT2RTR_QP: 2674 if (raw_qp_param->set_mask) 2675 return -EINVAL; 2676 else 2677 return 0; 2678 default: 2679 WARN_ON(1); 2680 return -EINVAL; 2681 } 2682 2683 if (modify_rq) { 2684 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param); 2685 if (err) 2686 return err; 2687 } 2688 2689 if (modify_sq) { 2690 if (tx_affinity) { 2691 err = modify_raw_packet_tx_affinity(dev->mdev, sq, 2692 tx_affinity); 2693 if (err) 2694 return err; 2695 } 2696 2697 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, raw_qp_param); 2698 } 2699 2700 return 0; 2701 } 2702 2703 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp, 2704 const struct ib_qp_attr *attr, int attr_mask, 2705 enum ib_qp_state cur_state, enum ib_qp_state new_state) 2706 { 2707 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = { 2708 [MLX5_QP_STATE_RST] = { 2709 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2710 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2711 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP, 2712 }, 2713 [MLX5_QP_STATE_INIT] = { 2714 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2715 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2716 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP, 2717 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP, 2718 }, 2719 [MLX5_QP_STATE_RTR] = { 2720 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2721 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2722 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP, 2723 }, 2724 [MLX5_QP_STATE_RTS] = { 2725 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2726 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2727 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP, 2728 }, 2729 [MLX5_QP_STATE_SQD] = { 2730 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2731 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2732 }, 2733 [MLX5_QP_STATE_SQER] = { 2734 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2735 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2736 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP, 2737 }, 2738 [MLX5_QP_STATE_ERR] = { 2739 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2740 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2741 } 2742 }; 2743 2744 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2745 struct mlx5_ib_qp *qp = to_mqp(ibqp); 2746 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 2747 struct mlx5_ib_cq *send_cq, *recv_cq; 2748 struct mlx5_qp_context *context; 2749 struct mlx5_ib_pd *pd; 2750 struct mlx5_ib_port *mibport = NULL; 2751 enum mlx5_qp_state mlx5_cur, mlx5_new; 2752 enum mlx5_qp_optpar optpar; 2753 int mlx5_st; 2754 int err; 2755 u16 op; 2756 u8 tx_affinity = 0; 2757 2758 context = kzalloc(sizeof(*context), GFP_KERNEL); 2759 if (!context) 2760 return -ENOMEM; 2761 2762 err = to_mlx5_st(ibqp->qp_type); 2763 if (err < 0) { 2764 mlx5_ib_dbg(dev, "unsupported qp type %d\n", ibqp->qp_type); 2765 goto out; 2766 } 2767 2768 context->flags = cpu_to_be32(err << 16); 2769 2770 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) { 2771 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 2772 } else { 2773 switch (attr->path_mig_state) { 2774 case IB_MIG_MIGRATED: 2775 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 2776 break; 2777 case IB_MIG_REARM: 2778 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11); 2779 break; 2780 case IB_MIG_ARMED: 2781 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11); 2782 break; 2783 } 2784 } 2785 2786 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) { 2787 if ((ibqp->qp_type == IB_QPT_RC) || 2788 (ibqp->qp_type == IB_QPT_UD && 2789 !(qp->flags & MLX5_IB_QP_SQPN_QP1)) || 2790 (ibqp->qp_type == IB_QPT_UC) || 2791 (ibqp->qp_type == IB_QPT_RAW_PACKET) || 2792 (ibqp->qp_type == IB_QPT_XRC_INI) || 2793 (ibqp->qp_type == IB_QPT_XRC_TGT)) { 2794 if (mlx5_lag_is_active(dev->mdev)) { 2795 tx_affinity = (unsigned int)atomic_add_return(1, 2796 &dev->roce.next_port) % 2797 MLX5_MAX_PORTS + 1; 2798 context->flags |= cpu_to_be32(tx_affinity << 24); 2799 } 2800 } 2801 } 2802 2803 if (is_sqp(ibqp->qp_type)) { 2804 context->mtu_msgmax = (IB_MTU_256 << 5) | 8; 2805 } else if ((ibqp->qp_type == IB_QPT_UD && 2806 !(qp->flags & MLX5_IB_QP_UNDERLAY)) || 2807 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) { 2808 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12; 2809 } else if (attr_mask & IB_QP_PATH_MTU) { 2810 if (attr->path_mtu < IB_MTU_256 || 2811 attr->path_mtu > IB_MTU_4096) { 2812 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu); 2813 err = -EINVAL; 2814 goto out; 2815 } 2816 context->mtu_msgmax = (attr->path_mtu << 5) | 2817 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg); 2818 } 2819 2820 if (attr_mask & IB_QP_DEST_QPN) 2821 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num); 2822 2823 if (attr_mask & IB_QP_PKEY_INDEX) 2824 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index); 2825 2826 /* todo implement counter_index functionality */ 2827 2828 if (is_sqp(ibqp->qp_type)) 2829 context->pri_path.port = qp->port; 2830 2831 if (attr_mask & IB_QP_PORT) 2832 context->pri_path.port = attr->port_num; 2833 2834 if (attr_mask & IB_QP_AV) { 2835 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path, 2836 attr_mask & IB_QP_PORT ? attr->port_num : qp->port, 2837 attr_mask, 0, attr, false); 2838 if (err) 2839 goto out; 2840 } 2841 2842 if (attr_mask & IB_QP_TIMEOUT) 2843 context->pri_path.ackto_lt |= attr->timeout << 3; 2844 2845 if (attr_mask & IB_QP_ALT_PATH) { 2846 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr, 2847 &context->alt_path, 2848 attr->alt_port_num, 2849 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT, 2850 0, attr, true); 2851 if (err) 2852 goto out; 2853 } 2854 2855 pd = get_pd(qp); 2856 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 2857 &send_cq, &recv_cq); 2858 2859 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn); 2860 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0; 2861 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0; 2862 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28); 2863 2864 if (attr_mask & IB_QP_RNR_RETRY) 2865 context->params1 |= cpu_to_be32(attr->rnr_retry << 13); 2866 2867 if (attr_mask & IB_QP_RETRY_CNT) 2868 context->params1 |= cpu_to_be32(attr->retry_cnt << 16); 2869 2870 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 2871 if (attr->max_rd_atomic) 2872 context->params1 |= 2873 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21); 2874 } 2875 2876 if (attr_mask & IB_QP_SQ_PSN) 2877 context->next_send_psn = cpu_to_be32(attr->sq_psn); 2878 2879 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 2880 if (attr->max_dest_rd_atomic) 2881 context->params2 |= 2882 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21); 2883 } 2884 2885 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) 2886 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask); 2887 2888 if (attr_mask & IB_QP_MIN_RNR_TIMER) 2889 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24); 2890 2891 if (attr_mask & IB_QP_RQ_PSN) 2892 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn); 2893 2894 if (attr_mask & IB_QP_QKEY) 2895 context->qkey = cpu_to_be32(attr->qkey); 2896 2897 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 2898 context->db_rec_addr = cpu_to_be64(qp->db.dma); 2899 2900 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 2901 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num : 2902 qp->port) - 1; 2903 2904 /* Underlay port should be used - index 0 function per port */ 2905 if (qp->flags & MLX5_IB_QP_UNDERLAY) 2906 port_num = 0; 2907 2908 mibport = &dev->port[port_num]; 2909 context->qp_counter_set_usr_page |= 2910 cpu_to_be32((u32)(mibport->cnts.set_id) << 24); 2911 } 2912 2913 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 2914 context->sq_crq_size |= cpu_to_be16(1 << 4); 2915 2916 if (qp->flags & MLX5_IB_QP_SQPN_QP1) 2917 context->deth_sqpn = cpu_to_be32(1); 2918 2919 mlx5_cur = to_mlx5_state(cur_state); 2920 mlx5_new = to_mlx5_state(new_state); 2921 mlx5_st = to_mlx5_st(ibqp->qp_type); 2922 if (mlx5_st < 0) 2923 goto out; 2924 2925 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE || 2926 !optab[mlx5_cur][mlx5_new]) 2927 goto out; 2928 2929 op = optab[mlx5_cur][mlx5_new]; 2930 optpar = ib_mask_to_mlx5_opt(attr_mask); 2931 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st]; 2932 2933 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 2934 qp->flags & MLX5_IB_QP_UNDERLAY) { 2935 struct mlx5_modify_raw_qp_param raw_qp_param = {}; 2936 2937 raw_qp_param.operation = op; 2938 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 2939 raw_qp_param.rq_q_ctr_id = mibport->cnts.set_id; 2940 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID; 2941 } 2942 2943 if (attr_mask & IB_QP_RATE_LIMIT) { 2944 raw_qp_param.rate_limit = attr->rate_limit; 2945 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT; 2946 } 2947 2948 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity); 2949 } else { 2950 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context, 2951 &base->mqp); 2952 } 2953 2954 if (err) 2955 goto out; 2956 2957 qp->state = new_state; 2958 2959 if (attr_mask & IB_QP_ACCESS_FLAGS) 2960 qp->trans_qp.atomic_rd_en = attr->qp_access_flags; 2961 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 2962 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic; 2963 if (attr_mask & IB_QP_PORT) 2964 qp->port = attr->port_num; 2965 if (attr_mask & IB_QP_ALT_PATH) 2966 qp->trans_qp.alt_port = attr->alt_port_num; 2967 2968 /* 2969 * If we moved a kernel QP to RESET, clean up all old CQ 2970 * entries and reinitialize the QP. 2971 */ 2972 if (new_state == IB_QPS_RESET && !ibqp->uobject) { 2973 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 2974 ibqp->srq ? to_msrq(ibqp->srq) : NULL); 2975 if (send_cq != recv_cq) 2976 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL); 2977 2978 qp->rq.head = 0; 2979 qp->rq.tail = 0; 2980 qp->sq.head = 0; 2981 qp->sq.tail = 0; 2982 qp->sq.cur_post = 0; 2983 qp->sq.last_poll = 0; 2984 qp->db.db[MLX5_RCV_DBR] = 0; 2985 qp->db.db[MLX5_SND_DBR] = 0; 2986 } 2987 2988 out: 2989 kfree(context); 2990 return err; 2991 } 2992 2993 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 2994 int attr_mask, struct ib_udata *udata) 2995 { 2996 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2997 struct mlx5_ib_qp *qp = to_mqp(ibqp); 2998 enum ib_qp_type qp_type; 2999 enum ib_qp_state cur_state, new_state; 3000 int err = -EINVAL; 3001 int port; 3002 enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED; 3003 3004 if (ibqp->rwq_ind_tbl) 3005 return -ENOSYS; 3006 3007 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 3008 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask); 3009 3010 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ? 3011 IB_QPT_GSI : ibqp->qp_type; 3012 3013 mutex_lock(&qp->mutex); 3014 3015 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; 3016 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 3017 3018 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) { 3019 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 3020 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port); 3021 } 3022 3023 if (qp->flags & MLX5_IB_QP_UNDERLAY) { 3024 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) { 3025 mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n", 3026 attr_mask); 3027 goto out; 3028 } 3029 } else if (qp_type != MLX5_IB_QPT_REG_UMR && 3030 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) { 3031 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 3032 cur_state, new_state, ibqp->qp_type, attr_mask); 3033 goto out; 3034 } 3035 3036 if ((attr_mask & IB_QP_PORT) && 3037 (attr->port_num == 0 || 3038 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports))) { 3039 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 3040 attr->port_num, dev->num_ports); 3041 goto out; 3042 } 3043 3044 if (attr_mask & IB_QP_PKEY_INDEX) { 3045 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 3046 if (attr->pkey_index >= 3047 dev->mdev->port_caps[port - 1].pkey_table_len) { 3048 mlx5_ib_dbg(dev, "invalid pkey index %d\n", 3049 attr->pkey_index); 3050 goto out; 3051 } 3052 } 3053 3054 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 3055 attr->max_rd_atomic > 3056 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) { 3057 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n", 3058 attr->max_rd_atomic); 3059 goto out; 3060 } 3061 3062 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 3063 attr->max_dest_rd_atomic > 3064 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) { 3065 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n", 3066 attr->max_dest_rd_atomic); 3067 goto out; 3068 } 3069 3070 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 3071 err = 0; 3072 goto out; 3073 } 3074 3075 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state); 3076 3077 out: 3078 mutex_unlock(&qp->mutex); 3079 return err; 3080 } 3081 3082 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq) 3083 { 3084 struct mlx5_ib_cq *cq; 3085 unsigned cur; 3086 3087 cur = wq->head - wq->tail; 3088 if (likely(cur + nreq < wq->max_post)) 3089 return 0; 3090 3091 cq = to_mcq(ib_cq); 3092 spin_lock(&cq->lock); 3093 cur = wq->head - wq->tail; 3094 spin_unlock(&cq->lock); 3095 3096 return cur + nreq >= wq->max_post; 3097 } 3098 3099 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg, 3100 u64 remote_addr, u32 rkey) 3101 { 3102 rseg->raddr = cpu_to_be64(remote_addr); 3103 rseg->rkey = cpu_to_be32(rkey); 3104 rseg->reserved = 0; 3105 } 3106 3107 static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg, 3108 struct ib_send_wr *wr, void *qend, 3109 struct mlx5_ib_qp *qp, int *size) 3110 { 3111 void *seg = eseg; 3112 3113 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg)); 3114 3115 if (wr->send_flags & IB_SEND_IP_CSUM) 3116 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM | 3117 MLX5_ETH_WQE_L4_CSUM; 3118 3119 seg += sizeof(struct mlx5_wqe_eth_seg); 3120 *size += sizeof(struct mlx5_wqe_eth_seg) / 16; 3121 3122 if (wr->opcode == IB_WR_LSO) { 3123 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr); 3124 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr.start); 3125 u64 left, leftlen, copysz; 3126 void *pdata = ud_wr->header; 3127 3128 left = ud_wr->hlen; 3129 eseg->mss = cpu_to_be16(ud_wr->mss); 3130 eseg->inline_hdr.sz = cpu_to_be16(left); 3131 3132 /* 3133 * check if there is space till the end of queue, if yes, 3134 * copy all in one shot, otherwise copy till the end of queue, 3135 * rollback and than the copy the left 3136 */ 3137 leftlen = qend - (void *)eseg->inline_hdr.start; 3138 copysz = min_t(u64, leftlen, left); 3139 3140 memcpy(seg - size_of_inl_hdr_start, pdata, copysz); 3141 3142 if (likely(copysz > size_of_inl_hdr_start)) { 3143 seg += ALIGN(copysz - size_of_inl_hdr_start, 16); 3144 *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16; 3145 } 3146 3147 if (unlikely(copysz < left)) { /* the last wqe in the queue */ 3148 seg = mlx5_get_send_wqe(qp, 0); 3149 left -= copysz; 3150 pdata += copysz; 3151 memcpy(seg, pdata, left); 3152 seg += ALIGN(left, 16); 3153 *size += ALIGN(left, 16) / 16; 3154 } 3155 } 3156 3157 return seg; 3158 } 3159 3160 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg, 3161 struct ib_send_wr *wr) 3162 { 3163 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av)); 3164 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV); 3165 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey); 3166 } 3167 3168 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg) 3169 { 3170 dseg->byte_count = cpu_to_be32(sg->length); 3171 dseg->lkey = cpu_to_be32(sg->lkey); 3172 dseg->addr = cpu_to_be64(sg->addr); 3173 } 3174 3175 static u64 get_xlt_octo(u64 bytes) 3176 { 3177 return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) / 3178 MLX5_IB_UMR_OCTOWORD; 3179 } 3180 3181 static __be64 frwr_mkey_mask(void) 3182 { 3183 u64 result; 3184 3185 result = MLX5_MKEY_MASK_LEN | 3186 MLX5_MKEY_MASK_PAGE_SIZE | 3187 MLX5_MKEY_MASK_START_ADDR | 3188 MLX5_MKEY_MASK_EN_RINVAL | 3189 MLX5_MKEY_MASK_KEY | 3190 MLX5_MKEY_MASK_LR | 3191 MLX5_MKEY_MASK_LW | 3192 MLX5_MKEY_MASK_RR | 3193 MLX5_MKEY_MASK_RW | 3194 MLX5_MKEY_MASK_A | 3195 MLX5_MKEY_MASK_SMALL_FENCE | 3196 MLX5_MKEY_MASK_FREE; 3197 3198 return cpu_to_be64(result); 3199 } 3200 3201 static __be64 sig_mkey_mask(void) 3202 { 3203 u64 result; 3204 3205 result = MLX5_MKEY_MASK_LEN | 3206 MLX5_MKEY_MASK_PAGE_SIZE | 3207 MLX5_MKEY_MASK_START_ADDR | 3208 MLX5_MKEY_MASK_EN_SIGERR | 3209 MLX5_MKEY_MASK_EN_RINVAL | 3210 MLX5_MKEY_MASK_KEY | 3211 MLX5_MKEY_MASK_LR | 3212 MLX5_MKEY_MASK_LW | 3213 MLX5_MKEY_MASK_RR | 3214 MLX5_MKEY_MASK_RW | 3215 MLX5_MKEY_MASK_SMALL_FENCE | 3216 MLX5_MKEY_MASK_FREE | 3217 MLX5_MKEY_MASK_BSF_EN; 3218 3219 return cpu_to_be64(result); 3220 } 3221 3222 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr, 3223 struct mlx5_ib_mr *mr) 3224 { 3225 int size = mr->ndescs * mr->desc_size; 3226 3227 memset(umr, 0, sizeof(*umr)); 3228 3229 umr->flags = MLX5_UMR_CHECK_NOT_FREE; 3230 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size)); 3231 umr->mkey_mask = frwr_mkey_mask(); 3232 } 3233 3234 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr) 3235 { 3236 memset(umr, 0, sizeof(*umr)); 3237 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE); 3238 umr->flags = MLX5_UMR_INLINE; 3239 } 3240 3241 static __be64 get_umr_enable_mr_mask(void) 3242 { 3243 u64 result; 3244 3245 result = MLX5_MKEY_MASK_KEY | 3246 MLX5_MKEY_MASK_FREE; 3247 3248 return cpu_to_be64(result); 3249 } 3250 3251 static __be64 get_umr_disable_mr_mask(void) 3252 { 3253 u64 result; 3254 3255 result = MLX5_MKEY_MASK_FREE; 3256 3257 return cpu_to_be64(result); 3258 } 3259 3260 static __be64 get_umr_update_translation_mask(void) 3261 { 3262 u64 result; 3263 3264 result = MLX5_MKEY_MASK_LEN | 3265 MLX5_MKEY_MASK_PAGE_SIZE | 3266 MLX5_MKEY_MASK_START_ADDR; 3267 3268 return cpu_to_be64(result); 3269 } 3270 3271 static __be64 get_umr_update_access_mask(int atomic) 3272 { 3273 u64 result; 3274 3275 result = MLX5_MKEY_MASK_LR | 3276 MLX5_MKEY_MASK_LW | 3277 MLX5_MKEY_MASK_RR | 3278 MLX5_MKEY_MASK_RW; 3279 3280 if (atomic) 3281 result |= MLX5_MKEY_MASK_A; 3282 3283 return cpu_to_be64(result); 3284 } 3285 3286 static __be64 get_umr_update_pd_mask(void) 3287 { 3288 u64 result; 3289 3290 result = MLX5_MKEY_MASK_PD; 3291 3292 return cpu_to_be64(result); 3293 } 3294 3295 static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, 3296 struct ib_send_wr *wr, int atomic) 3297 { 3298 struct mlx5_umr_wr *umrwr = umr_wr(wr); 3299 3300 memset(umr, 0, sizeof(*umr)); 3301 3302 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE) 3303 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */ 3304 else 3305 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */ 3306 3307 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size)); 3308 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) { 3309 u64 offset = get_xlt_octo(umrwr->offset); 3310 3311 umr->xlt_offset = cpu_to_be16(offset & 0xffff); 3312 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16); 3313 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN; 3314 } 3315 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION) 3316 umr->mkey_mask |= get_umr_update_translation_mask(); 3317 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) { 3318 umr->mkey_mask |= get_umr_update_access_mask(atomic); 3319 umr->mkey_mask |= get_umr_update_pd_mask(); 3320 } 3321 if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR) 3322 umr->mkey_mask |= get_umr_enable_mr_mask(); 3323 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR) 3324 umr->mkey_mask |= get_umr_disable_mr_mask(); 3325 3326 if (!wr->num_sge) 3327 umr->flags |= MLX5_UMR_INLINE; 3328 } 3329 3330 static u8 get_umr_flags(int acc) 3331 { 3332 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | 3333 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | 3334 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | 3335 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | 3336 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN; 3337 } 3338 3339 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg, 3340 struct mlx5_ib_mr *mr, 3341 u32 key, int access) 3342 { 3343 int ndescs = ALIGN(mr->ndescs, 8) >> 1; 3344 3345 memset(seg, 0, sizeof(*seg)); 3346 3347 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT) 3348 seg->log2_page_size = ilog2(mr->ibmr.page_size); 3349 else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS) 3350 /* KLMs take twice the size of MTTs */ 3351 ndescs *= 2; 3352 3353 seg->flags = get_umr_flags(access) | mr->access_mode; 3354 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00); 3355 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL); 3356 seg->start_addr = cpu_to_be64(mr->ibmr.iova); 3357 seg->len = cpu_to_be64(mr->ibmr.length); 3358 seg->xlt_oct_size = cpu_to_be32(ndescs); 3359 } 3360 3361 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg) 3362 { 3363 memset(seg, 0, sizeof(*seg)); 3364 seg->status = MLX5_MKEY_STATUS_FREE; 3365 } 3366 3367 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr) 3368 { 3369 struct mlx5_umr_wr *umrwr = umr_wr(wr); 3370 3371 memset(seg, 0, sizeof(*seg)); 3372 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR) 3373 seg->status = MLX5_MKEY_STATUS_FREE; 3374 3375 seg->flags = convert_access(umrwr->access_flags); 3376 if (umrwr->pd) 3377 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn); 3378 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION && 3379 !umrwr->length) 3380 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64); 3381 3382 seg->start_addr = cpu_to_be64(umrwr->virt_addr); 3383 seg->len = cpu_to_be64(umrwr->length); 3384 seg->log2_page_size = umrwr->page_shift; 3385 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 | 3386 mlx5_mkey_variant(umrwr->mkey)); 3387 } 3388 3389 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg, 3390 struct mlx5_ib_mr *mr, 3391 struct mlx5_ib_pd *pd) 3392 { 3393 int bcount = mr->desc_size * mr->ndescs; 3394 3395 dseg->addr = cpu_to_be64(mr->desc_map); 3396 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64)); 3397 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey); 3398 } 3399 3400 static __be32 send_ieth(struct ib_send_wr *wr) 3401 { 3402 switch (wr->opcode) { 3403 case IB_WR_SEND_WITH_IMM: 3404 case IB_WR_RDMA_WRITE_WITH_IMM: 3405 return wr->ex.imm_data; 3406 3407 case IB_WR_SEND_WITH_INV: 3408 return cpu_to_be32(wr->ex.invalidate_rkey); 3409 3410 default: 3411 return 0; 3412 } 3413 } 3414 3415 static u8 calc_sig(void *wqe, int size) 3416 { 3417 u8 *p = wqe; 3418 u8 res = 0; 3419 int i; 3420 3421 for (i = 0; i < size; i++) 3422 res ^= p[i]; 3423 3424 return ~res; 3425 } 3426 3427 static u8 wq_sig(void *wqe) 3428 { 3429 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4); 3430 } 3431 3432 static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr, 3433 void *wqe, int *sz) 3434 { 3435 struct mlx5_wqe_inline_seg *seg; 3436 void *qend = qp->sq.qend; 3437 void *addr; 3438 int inl = 0; 3439 int copy; 3440 int len; 3441 int i; 3442 3443 seg = wqe; 3444 wqe += sizeof(*seg); 3445 for (i = 0; i < wr->num_sge; i++) { 3446 addr = (void *)(unsigned long)(wr->sg_list[i].addr); 3447 len = wr->sg_list[i].length; 3448 inl += len; 3449 3450 if (unlikely(inl > qp->max_inline_data)) 3451 return -ENOMEM; 3452 3453 if (unlikely(wqe + len > qend)) { 3454 copy = qend - wqe; 3455 memcpy(wqe, addr, copy); 3456 addr += copy; 3457 len -= copy; 3458 wqe = mlx5_get_send_wqe(qp, 0); 3459 } 3460 memcpy(wqe, addr, len); 3461 wqe += len; 3462 } 3463 3464 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG); 3465 3466 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16; 3467 3468 return 0; 3469 } 3470 3471 static u16 prot_field_size(enum ib_signature_type type) 3472 { 3473 switch (type) { 3474 case IB_SIG_TYPE_T10_DIF: 3475 return MLX5_DIF_SIZE; 3476 default: 3477 return 0; 3478 } 3479 } 3480 3481 static u8 bs_selector(int block_size) 3482 { 3483 switch (block_size) { 3484 case 512: return 0x1; 3485 case 520: return 0x2; 3486 case 4096: return 0x3; 3487 case 4160: return 0x4; 3488 case 1073741824: return 0x5; 3489 default: return 0; 3490 } 3491 } 3492 3493 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain, 3494 struct mlx5_bsf_inl *inl) 3495 { 3496 /* Valid inline section and allow BSF refresh */ 3497 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID | 3498 MLX5_BSF_REFRESH_DIF); 3499 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag); 3500 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag); 3501 /* repeating block */ 3502 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK; 3503 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ? 3504 MLX5_DIF_CRC : MLX5_DIF_IPCS; 3505 3506 if (domain->sig.dif.ref_remap) 3507 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG; 3508 3509 if (domain->sig.dif.app_escape) { 3510 if (domain->sig.dif.ref_escape) 3511 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE; 3512 else 3513 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE; 3514 } 3515 3516 inl->dif_app_bitmask_check = 3517 cpu_to_be16(domain->sig.dif.apptag_check_mask); 3518 } 3519 3520 static int mlx5_set_bsf(struct ib_mr *sig_mr, 3521 struct ib_sig_attrs *sig_attrs, 3522 struct mlx5_bsf *bsf, u32 data_size) 3523 { 3524 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig; 3525 struct mlx5_bsf_basic *basic = &bsf->basic; 3526 struct ib_sig_domain *mem = &sig_attrs->mem; 3527 struct ib_sig_domain *wire = &sig_attrs->wire; 3528 3529 memset(bsf, 0, sizeof(*bsf)); 3530 3531 /* Basic + Extended + Inline */ 3532 basic->bsf_size_sbs = 1 << 7; 3533 /* Input domain check byte mask */ 3534 basic->check_byte_mask = sig_attrs->check_mask; 3535 basic->raw_data_size = cpu_to_be32(data_size); 3536 3537 /* Memory domain */ 3538 switch (sig_attrs->mem.sig_type) { 3539 case IB_SIG_TYPE_NONE: 3540 break; 3541 case IB_SIG_TYPE_T10_DIF: 3542 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval); 3543 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx); 3544 mlx5_fill_inl_bsf(mem, &bsf->m_inl); 3545 break; 3546 default: 3547 return -EINVAL; 3548 } 3549 3550 /* Wire domain */ 3551 switch (sig_attrs->wire.sig_type) { 3552 case IB_SIG_TYPE_NONE: 3553 break; 3554 case IB_SIG_TYPE_T10_DIF: 3555 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval && 3556 mem->sig_type == wire->sig_type) { 3557 /* Same block structure */ 3558 basic->bsf_size_sbs |= 1 << 4; 3559 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type) 3560 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK; 3561 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag) 3562 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK; 3563 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag) 3564 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK; 3565 } else 3566 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval); 3567 3568 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx); 3569 mlx5_fill_inl_bsf(wire, &bsf->w_inl); 3570 break; 3571 default: 3572 return -EINVAL; 3573 } 3574 3575 return 0; 3576 } 3577 3578 static int set_sig_data_segment(struct ib_sig_handover_wr *wr, 3579 struct mlx5_ib_qp *qp, void **seg, int *size) 3580 { 3581 struct ib_sig_attrs *sig_attrs = wr->sig_attrs; 3582 struct ib_mr *sig_mr = wr->sig_mr; 3583 struct mlx5_bsf *bsf; 3584 u32 data_len = wr->wr.sg_list->length; 3585 u32 data_key = wr->wr.sg_list->lkey; 3586 u64 data_va = wr->wr.sg_list->addr; 3587 int ret; 3588 int wqe_size; 3589 3590 if (!wr->prot || 3591 (data_key == wr->prot->lkey && 3592 data_va == wr->prot->addr && 3593 data_len == wr->prot->length)) { 3594 /** 3595 * Source domain doesn't contain signature information 3596 * or data and protection are interleaved in memory. 3597 * So need construct: 3598 * ------------------ 3599 * | data_klm | 3600 * ------------------ 3601 * | BSF | 3602 * ------------------ 3603 **/ 3604 struct mlx5_klm *data_klm = *seg; 3605 3606 data_klm->bcount = cpu_to_be32(data_len); 3607 data_klm->key = cpu_to_be32(data_key); 3608 data_klm->va = cpu_to_be64(data_va); 3609 wqe_size = ALIGN(sizeof(*data_klm), 64); 3610 } else { 3611 /** 3612 * Source domain contains signature information 3613 * So need construct a strided block format: 3614 * --------------------------- 3615 * | stride_block_ctrl | 3616 * --------------------------- 3617 * | data_klm | 3618 * --------------------------- 3619 * | prot_klm | 3620 * --------------------------- 3621 * | BSF | 3622 * --------------------------- 3623 **/ 3624 struct mlx5_stride_block_ctrl_seg *sblock_ctrl; 3625 struct mlx5_stride_block_entry *data_sentry; 3626 struct mlx5_stride_block_entry *prot_sentry; 3627 u32 prot_key = wr->prot->lkey; 3628 u64 prot_va = wr->prot->addr; 3629 u16 block_size = sig_attrs->mem.sig.dif.pi_interval; 3630 int prot_size; 3631 3632 sblock_ctrl = *seg; 3633 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl); 3634 prot_sentry = (void *)data_sentry + sizeof(*data_sentry); 3635 3636 prot_size = prot_field_size(sig_attrs->mem.sig_type); 3637 if (!prot_size) { 3638 pr_err("Bad block size given: %u\n", block_size); 3639 return -EINVAL; 3640 } 3641 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size + 3642 prot_size); 3643 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP); 3644 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size); 3645 sblock_ctrl->num_entries = cpu_to_be16(2); 3646 3647 data_sentry->bcount = cpu_to_be16(block_size); 3648 data_sentry->key = cpu_to_be32(data_key); 3649 data_sentry->va = cpu_to_be64(data_va); 3650 data_sentry->stride = cpu_to_be16(block_size); 3651 3652 prot_sentry->bcount = cpu_to_be16(prot_size); 3653 prot_sentry->key = cpu_to_be32(prot_key); 3654 prot_sentry->va = cpu_to_be64(prot_va); 3655 prot_sentry->stride = cpu_to_be16(prot_size); 3656 3657 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) + 3658 sizeof(*prot_sentry), 64); 3659 } 3660 3661 *seg += wqe_size; 3662 *size += wqe_size / 16; 3663 if (unlikely((*seg == qp->sq.qend))) 3664 *seg = mlx5_get_send_wqe(qp, 0); 3665 3666 bsf = *seg; 3667 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len); 3668 if (ret) 3669 return -EINVAL; 3670 3671 *seg += sizeof(*bsf); 3672 *size += sizeof(*bsf) / 16; 3673 if (unlikely((*seg == qp->sq.qend))) 3674 *seg = mlx5_get_send_wqe(qp, 0); 3675 3676 return 0; 3677 } 3678 3679 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg, 3680 struct ib_sig_handover_wr *wr, u32 size, 3681 u32 length, u32 pdn) 3682 { 3683 struct ib_mr *sig_mr = wr->sig_mr; 3684 u32 sig_key = sig_mr->rkey; 3685 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1; 3686 3687 memset(seg, 0, sizeof(*seg)); 3688 3689 seg->flags = get_umr_flags(wr->access_flags) | 3690 MLX5_MKC_ACCESS_MODE_KLMS; 3691 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00); 3692 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 | 3693 MLX5_MKEY_BSF_EN | pdn); 3694 seg->len = cpu_to_be64(length); 3695 seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size)); 3696 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE); 3697 } 3698 3699 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, 3700 u32 size) 3701 { 3702 memset(umr, 0, sizeof(*umr)); 3703 3704 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE; 3705 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size)); 3706 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE); 3707 umr->mkey_mask = sig_mkey_mask(); 3708 } 3709 3710 3711 static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp, 3712 void **seg, int *size) 3713 { 3714 struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr); 3715 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr); 3716 u32 pdn = get_pd(qp)->pdn; 3717 u32 xlt_size; 3718 int region_len, ret; 3719 3720 if (unlikely(wr->wr.num_sge != 1) || 3721 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) || 3722 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) || 3723 unlikely(!sig_mr->sig->sig_status_checked)) 3724 return -EINVAL; 3725 3726 /* length of the protected region, data + protection */ 3727 region_len = wr->wr.sg_list->length; 3728 if (wr->prot && 3729 (wr->prot->lkey != wr->wr.sg_list->lkey || 3730 wr->prot->addr != wr->wr.sg_list->addr || 3731 wr->prot->length != wr->wr.sg_list->length)) 3732 region_len += wr->prot->length; 3733 3734 /** 3735 * KLM octoword size - if protection was provided 3736 * then we use strided block format (3 octowords), 3737 * else we use single KLM (1 octoword) 3738 **/ 3739 xlt_size = wr->prot ? 0x30 : sizeof(struct mlx5_klm); 3740 3741 set_sig_umr_segment(*seg, xlt_size); 3742 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 3743 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 3744 if (unlikely((*seg == qp->sq.qend))) 3745 *seg = mlx5_get_send_wqe(qp, 0); 3746 3747 set_sig_mkey_segment(*seg, wr, xlt_size, region_len, pdn); 3748 *seg += sizeof(struct mlx5_mkey_seg); 3749 *size += sizeof(struct mlx5_mkey_seg) / 16; 3750 if (unlikely((*seg == qp->sq.qend))) 3751 *seg = mlx5_get_send_wqe(qp, 0); 3752 3753 ret = set_sig_data_segment(wr, qp, seg, size); 3754 if (ret) 3755 return ret; 3756 3757 sig_mr->sig->sig_status_checked = false; 3758 return 0; 3759 } 3760 3761 static int set_psv_wr(struct ib_sig_domain *domain, 3762 u32 psv_idx, void **seg, int *size) 3763 { 3764 struct mlx5_seg_set_psv *psv_seg = *seg; 3765 3766 memset(psv_seg, 0, sizeof(*psv_seg)); 3767 psv_seg->psv_num = cpu_to_be32(psv_idx); 3768 switch (domain->sig_type) { 3769 case IB_SIG_TYPE_NONE: 3770 break; 3771 case IB_SIG_TYPE_T10_DIF: 3772 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 | 3773 domain->sig.dif.app_tag); 3774 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag); 3775 break; 3776 default: 3777 pr_err("Bad signature type (%d) is given.\n", 3778 domain->sig_type); 3779 return -EINVAL; 3780 } 3781 3782 *seg += sizeof(*psv_seg); 3783 *size += sizeof(*psv_seg) / 16; 3784 3785 return 0; 3786 } 3787 3788 static int set_reg_wr(struct mlx5_ib_qp *qp, 3789 struct ib_reg_wr *wr, 3790 void **seg, int *size) 3791 { 3792 struct mlx5_ib_mr *mr = to_mmr(wr->mr); 3793 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd); 3794 3795 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) { 3796 mlx5_ib_warn(to_mdev(qp->ibqp.device), 3797 "Invalid IB_SEND_INLINE send flag\n"); 3798 return -EINVAL; 3799 } 3800 3801 set_reg_umr_seg(*seg, mr); 3802 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 3803 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 3804 if (unlikely((*seg == qp->sq.qend))) 3805 *seg = mlx5_get_send_wqe(qp, 0); 3806 3807 set_reg_mkey_seg(*seg, mr, wr->key, wr->access); 3808 *seg += sizeof(struct mlx5_mkey_seg); 3809 *size += sizeof(struct mlx5_mkey_seg) / 16; 3810 if (unlikely((*seg == qp->sq.qend))) 3811 *seg = mlx5_get_send_wqe(qp, 0); 3812 3813 set_reg_data_seg(*seg, mr, pd); 3814 *seg += sizeof(struct mlx5_wqe_data_seg); 3815 *size += (sizeof(struct mlx5_wqe_data_seg) / 16); 3816 3817 return 0; 3818 } 3819 3820 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size) 3821 { 3822 set_linv_umr_seg(*seg); 3823 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 3824 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 3825 if (unlikely((*seg == qp->sq.qend))) 3826 *seg = mlx5_get_send_wqe(qp, 0); 3827 set_linv_mkey_seg(*seg); 3828 *seg += sizeof(struct mlx5_mkey_seg); 3829 *size += sizeof(struct mlx5_mkey_seg) / 16; 3830 if (unlikely((*seg == qp->sq.qend))) 3831 *seg = mlx5_get_send_wqe(qp, 0); 3832 } 3833 3834 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16) 3835 { 3836 __be32 *p = NULL; 3837 int tidx = idx; 3838 int i, j; 3839 3840 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx)); 3841 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) { 3842 if ((i & 0xf) == 0) { 3843 void *buf = mlx5_get_send_wqe(qp, tidx); 3844 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1); 3845 p = buf; 3846 j = 0; 3847 } 3848 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]), 3849 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]), 3850 be32_to_cpu(p[j + 3])); 3851 } 3852 } 3853 3854 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg, 3855 struct mlx5_wqe_ctrl_seg **ctrl, 3856 struct ib_send_wr *wr, unsigned *idx, 3857 int *size, int nreq) 3858 { 3859 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq))) 3860 return -ENOMEM; 3861 3862 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1); 3863 *seg = mlx5_get_send_wqe(qp, *idx); 3864 *ctrl = *seg; 3865 *(uint32_t *)(*seg + 8) = 0; 3866 (*ctrl)->imm = send_ieth(wr); 3867 (*ctrl)->fm_ce_se = qp->sq_signal_bits | 3868 (wr->send_flags & IB_SEND_SIGNALED ? 3869 MLX5_WQE_CTRL_CQ_UPDATE : 0) | 3870 (wr->send_flags & IB_SEND_SOLICITED ? 3871 MLX5_WQE_CTRL_SOLICITED : 0); 3872 3873 *seg += sizeof(**ctrl); 3874 *size = sizeof(**ctrl) / 16; 3875 3876 return 0; 3877 } 3878 3879 static void finish_wqe(struct mlx5_ib_qp *qp, 3880 struct mlx5_wqe_ctrl_seg *ctrl, 3881 u8 size, unsigned idx, u64 wr_id, 3882 int nreq, u8 fence, u32 mlx5_opcode) 3883 { 3884 u8 opmod = 0; 3885 3886 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) | 3887 mlx5_opcode | ((u32)opmod << 24)); 3888 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8)); 3889 ctrl->fm_ce_se |= fence; 3890 if (unlikely(qp->wq_sig)) 3891 ctrl->signature = wq_sig(ctrl); 3892 3893 qp->sq.wrid[idx] = wr_id; 3894 qp->sq.w_list[idx].opcode = mlx5_opcode; 3895 qp->sq.wqe_head[idx] = qp->sq.head + nreq; 3896 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB); 3897 qp->sq.w_list[idx].next = qp->sq.cur_post; 3898 } 3899 3900 3901 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 3902 struct ib_send_wr **bad_wr) 3903 { 3904 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */ 3905 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3906 struct mlx5_core_dev *mdev = dev->mdev; 3907 struct mlx5_ib_qp *qp; 3908 struct mlx5_ib_mr *mr; 3909 struct mlx5_wqe_data_seg *dpseg; 3910 struct mlx5_wqe_xrc_seg *xrc; 3911 struct mlx5_bf *bf; 3912 int uninitialized_var(size); 3913 void *qend; 3914 unsigned long flags; 3915 unsigned idx; 3916 int err = 0; 3917 int num_sge; 3918 void *seg; 3919 int nreq; 3920 int i; 3921 u8 next_fence = 0; 3922 u8 fence; 3923 3924 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 3925 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr); 3926 3927 qp = to_mqp(ibqp); 3928 bf = &qp->bf; 3929 qend = qp->sq.qend; 3930 3931 spin_lock_irqsave(&qp->sq.lock, flags); 3932 3933 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 3934 err = -EIO; 3935 *bad_wr = wr; 3936 nreq = 0; 3937 goto out; 3938 } 3939 3940 for (nreq = 0; wr; nreq++, wr = wr->next) { 3941 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) { 3942 mlx5_ib_warn(dev, "\n"); 3943 err = -EINVAL; 3944 *bad_wr = wr; 3945 goto out; 3946 } 3947 3948 num_sge = wr->num_sge; 3949 if (unlikely(num_sge > qp->sq.max_gs)) { 3950 mlx5_ib_warn(dev, "\n"); 3951 err = -EINVAL; 3952 *bad_wr = wr; 3953 goto out; 3954 } 3955 3956 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq); 3957 if (err) { 3958 mlx5_ib_warn(dev, "\n"); 3959 err = -ENOMEM; 3960 *bad_wr = wr; 3961 goto out; 3962 } 3963 3964 if (wr->opcode == IB_WR_LOCAL_INV || 3965 wr->opcode == IB_WR_REG_MR) { 3966 fence = dev->umr_fence; 3967 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 3968 } else if (wr->send_flags & IB_SEND_FENCE) { 3969 if (qp->next_fence) 3970 fence = MLX5_FENCE_MODE_SMALL_AND_FENCE; 3971 else 3972 fence = MLX5_FENCE_MODE_FENCE; 3973 } else { 3974 fence = qp->next_fence; 3975 } 3976 3977 switch (ibqp->qp_type) { 3978 case IB_QPT_XRC_INI: 3979 xrc = seg; 3980 seg += sizeof(*xrc); 3981 size += sizeof(*xrc) / 16; 3982 /* fall through */ 3983 case IB_QPT_RC: 3984 switch (wr->opcode) { 3985 case IB_WR_RDMA_READ: 3986 case IB_WR_RDMA_WRITE: 3987 case IB_WR_RDMA_WRITE_WITH_IMM: 3988 set_raddr_seg(seg, rdma_wr(wr)->remote_addr, 3989 rdma_wr(wr)->rkey); 3990 seg += sizeof(struct mlx5_wqe_raddr_seg); 3991 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 3992 break; 3993 3994 case IB_WR_ATOMIC_CMP_AND_SWP: 3995 case IB_WR_ATOMIC_FETCH_AND_ADD: 3996 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP: 3997 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n"); 3998 err = -ENOSYS; 3999 *bad_wr = wr; 4000 goto out; 4001 4002 case IB_WR_LOCAL_INV: 4003 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV; 4004 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey); 4005 set_linv_wr(qp, &seg, &size); 4006 num_sge = 0; 4007 break; 4008 4009 case IB_WR_REG_MR: 4010 qp->sq.wr_data[idx] = IB_WR_REG_MR; 4011 ctrl->imm = cpu_to_be32(reg_wr(wr)->key); 4012 err = set_reg_wr(qp, reg_wr(wr), &seg, &size); 4013 if (err) { 4014 *bad_wr = wr; 4015 goto out; 4016 } 4017 num_sge = 0; 4018 break; 4019 4020 case IB_WR_REG_SIG_MR: 4021 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR; 4022 mr = to_mmr(sig_handover_wr(wr)->sig_mr); 4023 4024 ctrl->imm = cpu_to_be32(mr->ibmr.rkey); 4025 err = set_sig_umr_wr(wr, qp, &seg, &size); 4026 if (err) { 4027 mlx5_ib_warn(dev, "\n"); 4028 *bad_wr = wr; 4029 goto out; 4030 } 4031 4032 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, 4033 fence, MLX5_OPCODE_UMR); 4034 /* 4035 * SET_PSV WQEs are not signaled and solicited 4036 * on error 4037 */ 4038 wr->send_flags &= ~IB_SEND_SIGNALED; 4039 wr->send_flags |= IB_SEND_SOLICITED; 4040 err = begin_wqe(qp, &seg, &ctrl, wr, 4041 &idx, &size, nreq); 4042 if (err) { 4043 mlx5_ib_warn(dev, "\n"); 4044 err = -ENOMEM; 4045 *bad_wr = wr; 4046 goto out; 4047 } 4048 4049 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem, 4050 mr->sig->psv_memory.psv_idx, &seg, 4051 &size); 4052 if (err) { 4053 mlx5_ib_warn(dev, "\n"); 4054 *bad_wr = wr; 4055 goto out; 4056 } 4057 4058 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, 4059 fence, MLX5_OPCODE_SET_PSV); 4060 err = begin_wqe(qp, &seg, &ctrl, wr, 4061 &idx, &size, nreq); 4062 if (err) { 4063 mlx5_ib_warn(dev, "\n"); 4064 err = -ENOMEM; 4065 *bad_wr = wr; 4066 goto out; 4067 } 4068 4069 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire, 4070 mr->sig->psv_wire.psv_idx, &seg, 4071 &size); 4072 if (err) { 4073 mlx5_ib_warn(dev, "\n"); 4074 *bad_wr = wr; 4075 goto out; 4076 } 4077 4078 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, 4079 fence, MLX5_OPCODE_SET_PSV); 4080 qp->next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 4081 num_sge = 0; 4082 goto skip_psv; 4083 4084 default: 4085 break; 4086 } 4087 break; 4088 4089 case IB_QPT_UC: 4090 switch (wr->opcode) { 4091 case IB_WR_RDMA_WRITE: 4092 case IB_WR_RDMA_WRITE_WITH_IMM: 4093 set_raddr_seg(seg, rdma_wr(wr)->remote_addr, 4094 rdma_wr(wr)->rkey); 4095 seg += sizeof(struct mlx5_wqe_raddr_seg); 4096 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 4097 break; 4098 4099 default: 4100 break; 4101 } 4102 break; 4103 4104 case IB_QPT_SMI: 4105 if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) { 4106 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n"); 4107 err = -EPERM; 4108 *bad_wr = wr; 4109 goto out; 4110 } 4111 /* fall through */ 4112 case MLX5_IB_QPT_HW_GSI: 4113 set_datagram_seg(seg, wr); 4114 seg += sizeof(struct mlx5_wqe_datagram_seg); 4115 size += sizeof(struct mlx5_wqe_datagram_seg) / 16; 4116 if (unlikely((seg == qend))) 4117 seg = mlx5_get_send_wqe(qp, 0); 4118 break; 4119 case IB_QPT_UD: 4120 set_datagram_seg(seg, wr); 4121 seg += sizeof(struct mlx5_wqe_datagram_seg); 4122 size += sizeof(struct mlx5_wqe_datagram_seg) / 16; 4123 4124 if (unlikely((seg == qend))) 4125 seg = mlx5_get_send_wqe(qp, 0); 4126 4127 /* handle qp that supports ud offload */ 4128 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) { 4129 struct mlx5_wqe_eth_pad *pad; 4130 4131 pad = seg; 4132 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad)); 4133 seg += sizeof(struct mlx5_wqe_eth_pad); 4134 size += sizeof(struct mlx5_wqe_eth_pad) / 16; 4135 4136 seg = set_eth_seg(seg, wr, qend, qp, &size); 4137 4138 if (unlikely((seg == qend))) 4139 seg = mlx5_get_send_wqe(qp, 0); 4140 } 4141 break; 4142 case MLX5_IB_QPT_REG_UMR: 4143 if (wr->opcode != MLX5_IB_WR_UMR) { 4144 err = -EINVAL; 4145 mlx5_ib_warn(dev, "bad opcode\n"); 4146 goto out; 4147 } 4148 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR; 4149 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey); 4150 set_reg_umr_segment(seg, wr, !!(MLX5_CAP_GEN(mdev, atomic))); 4151 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 4152 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 4153 if (unlikely((seg == qend))) 4154 seg = mlx5_get_send_wqe(qp, 0); 4155 set_reg_mkey_segment(seg, wr); 4156 seg += sizeof(struct mlx5_mkey_seg); 4157 size += sizeof(struct mlx5_mkey_seg) / 16; 4158 if (unlikely((seg == qend))) 4159 seg = mlx5_get_send_wqe(qp, 0); 4160 break; 4161 4162 default: 4163 break; 4164 } 4165 4166 if (wr->send_flags & IB_SEND_INLINE && num_sge) { 4167 int uninitialized_var(sz); 4168 4169 err = set_data_inl_seg(qp, wr, seg, &sz); 4170 if (unlikely(err)) { 4171 mlx5_ib_warn(dev, "\n"); 4172 *bad_wr = wr; 4173 goto out; 4174 } 4175 size += sz; 4176 } else { 4177 dpseg = seg; 4178 for (i = 0; i < num_sge; i++) { 4179 if (unlikely(dpseg == qend)) { 4180 seg = mlx5_get_send_wqe(qp, 0); 4181 dpseg = seg; 4182 } 4183 if (likely(wr->sg_list[i].length)) { 4184 set_data_ptr_seg(dpseg, wr->sg_list + i); 4185 size += sizeof(struct mlx5_wqe_data_seg) / 16; 4186 dpseg++; 4187 } 4188 } 4189 } 4190 4191 qp->next_fence = next_fence; 4192 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, fence, 4193 mlx5_ib_opcode[wr->opcode]); 4194 skip_psv: 4195 if (0) 4196 dump_wqe(qp, idx, size); 4197 } 4198 4199 out: 4200 if (likely(nreq)) { 4201 qp->sq.head += nreq; 4202 4203 /* Make sure that descriptors are written before 4204 * updating doorbell record and ringing the doorbell 4205 */ 4206 wmb(); 4207 4208 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post); 4209 4210 /* Make sure doorbell record is visible to the HCA before 4211 * we hit doorbell */ 4212 wmb(); 4213 4214 /* currently we support only regular doorbells */ 4215 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset, NULL); 4216 /* Make sure doorbells don't leak out of SQ spinlock 4217 * and reach the HCA out of order. 4218 */ 4219 mmiowb(); 4220 bf->offset ^= bf->buf_size; 4221 } 4222 4223 spin_unlock_irqrestore(&qp->sq.lock, flags); 4224 4225 return err; 4226 } 4227 4228 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size) 4229 { 4230 sig->signature = calc_sig(sig, size); 4231 } 4232 4233 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, 4234 struct ib_recv_wr **bad_wr) 4235 { 4236 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4237 struct mlx5_wqe_data_seg *scat; 4238 struct mlx5_rwqe_sig *sig; 4239 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4240 struct mlx5_core_dev *mdev = dev->mdev; 4241 unsigned long flags; 4242 int err = 0; 4243 int nreq; 4244 int ind; 4245 int i; 4246 4247 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 4248 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr); 4249 4250 spin_lock_irqsave(&qp->rq.lock, flags); 4251 4252 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 4253 err = -EIO; 4254 *bad_wr = wr; 4255 nreq = 0; 4256 goto out; 4257 } 4258 4259 ind = qp->rq.head & (qp->rq.wqe_cnt - 1); 4260 4261 for (nreq = 0; wr; nreq++, wr = wr->next) { 4262 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) { 4263 err = -ENOMEM; 4264 *bad_wr = wr; 4265 goto out; 4266 } 4267 4268 if (unlikely(wr->num_sge > qp->rq.max_gs)) { 4269 err = -EINVAL; 4270 *bad_wr = wr; 4271 goto out; 4272 } 4273 4274 scat = get_recv_wqe(qp, ind); 4275 if (qp->wq_sig) 4276 scat++; 4277 4278 for (i = 0; i < wr->num_sge; i++) 4279 set_data_ptr_seg(scat + i, wr->sg_list + i); 4280 4281 if (i < qp->rq.max_gs) { 4282 scat[i].byte_count = 0; 4283 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY); 4284 scat[i].addr = 0; 4285 } 4286 4287 if (qp->wq_sig) { 4288 sig = (struct mlx5_rwqe_sig *)scat; 4289 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2); 4290 } 4291 4292 qp->rq.wrid[ind] = wr->wr_id; 4293 4294 ind = (ind + 1) & (qp->rq.wqe_cnt - 1); 4295 } 4296 4297 out: 4298 if (likely(nreq)) { 4299 qp->rq.head += nreq; 4300 4301 /* Make sure that descriptors are written before 4302 * doorbell record. 4303 */ 4304 wmb(); 4305 4306 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff); 4307 } 4308 4309 spin_unlock_irqrestore(&qp->rq.lock, flags); 4310 4311 return err; 4312 } 4313 4314 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state) 4315 { 4316 switch (mlx5_state) { 4317 case MLX5_QP_STATE_RST: return IB_QPS_RESET; 4318 case MLX5_QP_STATE_INIT: return IB_QPS_INIT; 4319 case MLX5_QP_STATE_RTR: return IB_QPS_RTR; 4320 case MLX5_QP_STATE_RTS: return IB_QPS_RTS; 4321 case MLX5_QP_STATE_SQ_DRAINING: 4322 case MLX5_QP_STATE_SQD: return IB_QPS_SQD; 4323 case MLX5_QP_STATE_SQER: return IB_QPS_SQE; 4324 case MLX5_QP_STATE_ERR: return IB_QPS_ERR; 4325 default: return -1; 4326 } 4327 } 4328 4329 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state) 4330 { 4331 switch (mlx5_mig_state) { 4332 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED; 4333 case MLX5_QP_PM_REARM: return IB_MIG_REARM; 4334 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED; 4335 default: return -1; 4336 } 4337 } 4338 4339 static int to_ib_qp_access_flags(int mlx5_flags) 4340 { 4341 int ib_flags = 0; 4342 4343 if (mlx5_flags & MLX5_QP_BIT_RRE) 4344 ib_flags |= IB_ACCESS_REMOTE_READ; 4345 if (mlx5_flags & MLX5_QP_BIT_RWE) 4346 ib_flags |= IB_ACCESS_REMOTE_WRITE; 4347 if (mlx5_flags & MLX5_QP_BIT_RAE) 4348 ib_flags |= IB_ACCESS_REMOTE_ATOMIC; 4349 4350 return ib_flags; 4351 } 4352 4353 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev, 4354 struct rdma_ah_attr *ah_attr, 4355 struct mlx5_qp_path *path) 4356 { 4357 struct mlx5_core_dev *dev = ibdev->mdev; 4358 4359 memset(ah_attr, 0, sizeof(*ah_attr)); 4360 4361 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port); 4362 rdma_ah_set_port_num(ah_attr, path->port); 4363 if (rdma_ah_get_port_num(ah_attr) == 0 || 4364 rdma_ah_get_port_num(ah_attr) > MLX5_CAP_GEN(dev, num_ports)) 4365 return; 4366 4367 rdma_ah_set_port_num(ah_attr, path->port); 4368 rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf); 4369 4370 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid)); 4371 rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f); 4372 rdma_ah_set_static_rate(ah_attr, 4373 path->static_rate ? path->static_rate - 5 : 0); 4374 if (path->grh_mlid & (1 << 7)) { 4375 u32 tc_fl = be32_to_cpu(path->tclass_flowlabel); 4376 4377 rdma_ah_set_grh(ah_attr, NULL, 4378 tc_fl & 0xfffff, 4379 path->mgid_index, 4380 path->hop_limit, 4381 (tc_fl >> 20) & 0xff); 4382 rdma_ah_set_dgid_raw(ah_attr, path->rgid); 4383 } 4384 } 4385 4386 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev, 4387 struct mlx5_ib_sq *sq, 4388 u8 *sq_state) 4389 { 4390 void *out; 4391 void *sqc; 4392 int inlen; 4393 int err; 4394 4395 inlen = MLX5_ST_SZ_BYTES(query_sq_out); 4396 out = kvzalloc(inlen, GFP_KERNEL); 4397 if (!out) 4398 return -ENOMEM; 4399 4400 err = mlx5_core_query_sq(dev->mdev, sq->base.mqp.qpn, out); 4401 if (err) 4402 goto out; 4403 4404 sqc = MLX5_ADDR_OF(query_sq_out, out, sq_context); 4405 *sq_state = MLX5_GET(sqc, sqc, state); 4406 sq->state = *sq_state; 4407 4408 out: 4409 kvfree(out); 4410 return err; 4411 } 4412 4413 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev, 4414 struct mlx5_ib_rq *rq, 4415 u8 *rq_state) 4416 { 4417 void *out; 4418 void *rqc; 4419 int inlen; 4420 int err; 4421 4422 inlen = MLX5_ST_SZ_BYTES(query_rq_out); 4423 out = kvzalloc(inlen, GFP_KERNEL); 4424 if (!out) 4425 return -ENOMEM; 4426 4427 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out); 4428 if (err) 4429 goto out; 4430 4431 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context); 4432 *rq_state = MLX5_GET(rqc, rqc, state); 4433 rq->state = *rq_state; 4434 4435 out: 4436 kvfree(out); 4437 return err; 4438 } 4439 4440 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state, 4441 struct mlx5_ib_qp *qp, u8 *qp_state) 4442 { 4443 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = { 4444 [MLX5_RQC_STATE_RST] = { 4445 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 4446 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4447 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD, 4448 [MLX5_SQ_STATE_NA] = IB_QPS_RESET, 4449 }, 4450 [MLX5_RQC_STATE_RDY] = { 4451 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 4452 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4453 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE, 4454 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE, 4455 }, 4456 [MLX5_RQC_STATE_ERR] = { 4457 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 4458 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4459 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR, 4460 [MLX5_SQ_STATE_NA] = IB_QPS_ERR, 4461 }, 4462 [MLX5_RQ_STATE_NA] = { 4463 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 4464 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4465 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE, 4466 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD, 4467 }, 4468 }; 4469 4470 *qp_state = sqrq_trans[rq_state][sq_state]; 4471 4472 if (*qp_state == MLX5_QP_STATE_BAD) { 4473 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x", 4474 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state, 4475 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state); 4476 return -EINVAL; 4477 } 4478 4479 if (*qp_state == MLX5_QP_STATE) 4480 *qp_state = qp->state; 4481 4482 return 0; 4483 } 4484 4485 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev, 4486 struct mlx5_ib_qp *qp, 4487 u8 *raw_packet_qp_state) 4488 { 4489 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 4490 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 4491 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 4492 int err; 4493 u8 sq_state = MLX5_SQ_STATE_NA; 4494 u8 rq_state = MLX5_RQ_STATE_NA; 4495 4496 if (qp->sq.wqe_cnt) { 4497 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state); 4498 if (err) 4499 return err; 4500 } 4501 4502 if (qp->rq.wqe_cnt) { 4503 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state); 4504 if (err) 4505 return err; 4506 } 4507 4508 return sqrq_state_to_qp_state(sq_state, rq_state, qp, 4509 raw_packet_qp_state); 4510 } 4511 4512 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 4513 struct ib_qp_attr *qp_attr) 4514 { 4515 int outlen = MLX5_ST_SZ_BYTES(query_qp_out); 4516 struct mlx5_qp_context *context; 4517 int mlx5_state; 4518 u32 *outb; 4519 int err = 0; 4520 4521 outb = kzalloc(outlen, GFP_KERNEL); 4522 if (!outb) 4523 return -ENOMEM; 4524 4525 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb, 4526 outlen); 4527 if (err) 4528 goto out; 4529 4530 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */ 4531 context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc); 4532 4533 mlx5_state = be32_to_cpu(context->flags) >> 28; 4534 4535 qp->state = to_ib_qp_state(mlx5_state); 4536 qp_attr->path_mtu = context->mtu_msgmax >> 5; 4537 qp_attr->path_mig_state = 4538 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3); 4539 qp_attr->qkey = be32_to_cpu(context->qkey); 4540 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff; 4541 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff; 4542 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff; 4543 qp_attr->qp_access_flags = 4544 to_ib_qp_access_flags(be32_to_cpu(context->params2)); 4545 4546 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) { 4547 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path); 4548 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path); 4549 qp_attr->alt_pkey_index = 4550 be16_to_cpu(context->alt_path.pkey_index); 4551 qp_attr->alt_port_num = 4552 rdma_ah_get_port_num(&qp_attr->alt_ah_attr); 4553 } 4554 4555 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index); 4556 qp_attr->port_num = context->pri_path.port; 4557 4558 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */ 4559 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING; 4560 4561 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7); 4562 4563 qp_attr->max_dest_rd_atomic = 4564 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7); 4565 qp_attr->min_rnr_timer = 4566 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f; 4567 qp_attr->timeout = context->pri_path.ackto_lt >> 3; 4568 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7; 4569 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7; 4570 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3; 4571 4572 out: 4573 kfree(outb); 4574 return err; 4575 } 4576 4577 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 4578 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 4579 { 4580 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4581 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4582 int err = 0; 4583 u8 raw_packet_qp_state; 4584 4585 if (ibqp->rwq_ind_tbl) 4586 return -ENOSYS; 4587 4588 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 4589 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask, 4590 qp_init_attr); 4591 4592 /* Not all of output fields are applicable, make sure to zero them */ 4593 memset(qp_init_attr, 0, sizeof(*qp_init_attr)); 4594 memset(qp_attr, 0, sizeof(*qp_attr)); 4595 4596 mutex_lock(&qp->mutex); 4597 4598 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 4599 qp->flags & MLX5_IB_QP_UNDERLAY) { 4600 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state); 4601 if (err) 4602 goto out; 4603 qp->state = raw_packet_qp_state; 4604 qp_attr->port_num = 1; 4605 } else { 4606 err = query_qp_attr(dev, qp, qp_attr); 4607 if (err) 4608 goto out; 4609 } 4610 4611 qp_attr->qp_state = qp->state; 4612 qp_attr->cur_qp_state = qp_attr->qp_state; 4613 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; 4614 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 4615 4616 if (!ibqp->uobject) { 4617 qp_attr->cap.max_send_wr = qp->sq.max_post; 4618 qp_attr->cap.max_send_sge = qp->sq.max_gs; 4619 qp_init_attr->qp_context = ibqp->qp_context; 4620 } else { 4621 qp_attr->cap.max_send_wr = 0; 4622 qp_attr->cap.max_send_sge = 0; 4623 } 4624 4625 qp_init_attr->qp_type = ibqp->qp_type; 4626 qp_init_attr->recv_cq = ibqp->recv_cq; 4627 qp_init_attr->send_cq = ibqp->send_cq; 4628 qp_init_attr->srq = ibqp->srq; 4629 qp_attr->cap.max_inline_data = qp->max_inline_data; 4630 4631 qp_init_attr->cap = qp_attr->cap; 4632 4633 qp_init_attr->create_flags = 0; 4634 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 4635 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK; 4636 4637 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 4638 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL; 4639 if (qp->flags & MLX5_IB_QP_MANAGED_SEND) 4640 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND; 4641 if (qp->flags & MLX5_IB_QP_MANAGED_RECV) 4642 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV; 4643 if (qp->flags & MLX5_IB_QP_SQPN_QP1) 4644 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1(); 4645 4646 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ? 4647 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; 4648 4649 out: 4650 mutex_unlock(&qp->mutex); 4651 return err; 4652 } 4653 4654 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, 4655 struct ib_ucontext *context, 4656 struct ib_udata *udata) 4657 { 4658 struct mlx5_ib_dev *dev = to_mdev(ibdev); 4659 struct mlx5_ib_xrcd *xrcd; 4660 int err; 4661 4662 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 4663 return ERR_PTR(-ENOSYS); 4664 4665 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL); 4666 if (!xrcd) 4667 return ERR_PTR(-ENOMEM); 4668 4669 err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn); 4670 if (err) { 4671 kfree(xrcd); 4672 return ERR_PTR(-ENOMEM); 4673 } 4674 4675 return &xrcd->ibxrcd; 4676 } 4677 4678 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd) 4679 { 4680 struct mlx5_ib_dev *dev = to_mdev(xrcd->device); 4681 u32 xrcdn = to_mxrcd(xrcd)->xrcdn; 4682 int err; 4683 4684 err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn); 4685 if (err) { 4686 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn); 4687 return err; 4688 } 4689 4690 kfree(xrcd); 4691 4692 return 0; 4693 } 4694 4695 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type) 4696 { 4697 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp); 4698 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device); 4699 struct ib_event event; 4700 4701 if (rwq->ibwq.event_handler) { 4702 event.device = rwq->ibwq.device; 4703 event.element.wq = &rwq->ibwq; 4704 switch (type) { 4705 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 4706 event.event = IB_EVENT_WQ_FATAL; 4707 break; 4708 default: 4709 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn); 4710 return; 4711 } 4712 4713 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context); 4714 } 4715 } 4716 4717 static int set_delay_drop(struct mlx5_ib_dev *dev) 4718 { 4719 int err = 0; 4720 4721 mutex_lock(&dev->delay_drop.lock); 4722 if (dev->delay_drop.activate) 4723 goto out; 4724 4725 err = mlx5_core_set_delay_drop(dev->mdev, dev->delay_drop.timeout); 4726 if (err) 4727 goto out; 4728 4729 dev->delay_drop.activate = true; 4730 out: 4731 mutex_unlock(&dev->delay_drop.lock); 4732 4733 if (!err) 4734 atomic_inc(&dev->delay_drop.rqs_cnt); 4735 return err; 4736 } 4737 4738 static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd, 4739 struct ib_wq_init_attr *init_attr) 4740 { 4741 struct mlx5_ib_dev *dev; 4742 int has_net_offloads; 4743 __be64 *rq_pas0; 4744 void *in; 4745 void *rqc; 4746 void *wq; 4747 int inlen; 4748 int err; 4749 4750 dev = to_mdev(pd->device); 4751 4752 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas; 4753 in = kvzalloc(inlen, GFP_KERNEL); 4754 if (!in) 4755 return -ENOMEM; 4756 4757 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 4758 MLX5_SET(rqc, rqc, mem_rq_type, 4759 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 4760 MLX5_SET(rqc, rqc, user_index, rwq->user_index); 4761 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn); 4762 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 4763 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 4764 wq = MLX5_ADDR_OF(rqc, rqc, wq); 4765 MLX5_SET(wq, wq, wq_type, 4766 rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ? 4767 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC); 4768 if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { 4769 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) { 4770 mlx5_ib_dbg(dev, "Scatter end padding is not supported\n"); 4771 err = -EOPNOTSUPP; 4772 goto out; 4773 } else { 4774 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 4775 } 4776 } 4777 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride); 4778 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) { 4779 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en); 4780 MLX5_SET(wq, wq, log_wqe_stride_size, 4781 rwq->single_stride_log_num_of_bytes - 4782 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES); 4783 MLX5_SET(wq, wq, log_wqe_num_of_strides, rwq->log_num_strides - 4784 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES); 4785 } 4786 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size); 4787 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn); 4788 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset); 4789 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size); 4790 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig); 4791 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma); 4792 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads); 4793 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) { 4794 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) { 4795 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n"); 4796 err = -EOPNOTSUPP; 4797 goto out; 4798 } 4799 } else { 4800 MLX5_SET(rqc, rqc, vsd, 1); 4801 } 4802 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) { 4803 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) { 4804 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n"); 4805 err = -EOPNOTSUPP; 4806 goto out; 4807 } 4808 MLX5_SET(rqc, rqc, scatter_fcs, 1); 4809 } 4810 if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { 4811 if (!(dev->ib_dev.attrs.raw_packet_caps & 4812 IB_RAW_PACKET_CAP_DELAY_DROP)) { 4813 mlx5_ib_dbg(dev, "Delay drop is not supported\n"); 4814 err = -EOPNOTSUPP; 4815 goto out; 4816 } 4817 MLX5_SET(rqc, rqc, delay_drop_en, 1); 4818 } 4819 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 4820 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0); 4821 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp); 4822 if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { 4823 err = set_delay_drop(dev); 4824 if (err) { 4825 mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n", 4826 err); 4827 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); 4828 } else { 4829 rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP; 4830 } 4831 } 4832 out: 4833 kvfree(in); 4834 return err; 4835 } 4836 4837 static int set_user_rq_size(struct mlx5_ib_dev *dev, 4838 struct ib_wq_init_attr *wq_init_attr, 4839 struct mlx5_ib_create_wq *ucmd, 4840 struct mlx5_ib_rwq *rwq) 4841 { 4842 /* Sanity check RQ size before proceeding */ 4843 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz))) 4844 return -EINVAL; 4845 4846 if (!ucmd->rq_wqe_count) 4847 return -EINVAL; 4848 4849 rwq->wqe_count = ucmd->rq_wqe_count; 4850 rwq->wqe_shift = ucmd->rq_wqe_shift; 4851 rwq->buf_size = (rwq->wqe_count << rwq->wqe_shift); 4852 rwq->log_rq_stride = rwq->wqe_shift; 4853 rwq->log_rq_size = ilog2(rwq->wqe_count); 4854 return 0; 4855 } 4856 4857 static int prepare_user_rq(struct ib_pd *pd, 4858 struct ib_wq_init_attr *init_attr, 4859 struct ib_udata *udata, 4860 struct mlx5_ib_rwq *rwq) 4861 { 4862 struct mlx5_ib_dev *dev = to_mdev(pd->device); 4863 struct mlx5_ib_create_wq ucmd = {}; 4864 int err; 4865 size_t required_cmd_sz; 4866 4867 required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes) 4868 + sizeof(ucmd.single_stride_log_num_of_bytes); 4869 if (udata->inlen < required_cmd_sz) { 4870 mlx5_ib_dbg(dev, "invalid inlen\n"); 4871 return -EINVAL; 4872 } 4873 4874 if (udata->inlen > sizeof(ucmd) && 4875 !ib_is_udata_cleared(udata, sizeof(ucmd), 4876 udata->inlen - sizeof(ucmd))) { 4877 mlx5_ib_dbg(dev, "inlen is not supported\n"); 4878 return -EOPNOTSUPP; 4879 } 4880 4881 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 4882 mlx5_ib_dbg(dev, "copy failed\n"); 4883 return -EFAULT; 4884 } 4885 4886 if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) { 4887 mlx5_ib_dbg(dev, "invalid comp mask\n"); 4888 return -EOPNOTSUPP; 4889 } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) { 4890 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) { 4891 mlx5_ib_dbg(dev, "Striding RQ is not supported\n"); 4892 return -EOPNOTSUPP; 4893 } 4894 if ((ucmd.single_stride_log_num_of_bytes < 4895 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) || 4896 (ucmd.single_stride_log_num_of_bytes > 4897 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) { 4898 mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n", 4899 ucmd.single_stride_log_num_of_bytes, 4900 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES, 4901 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES); 4902 return -EINVAL; 4903 } 4904 if ((ucmd.single_wqe_log_num_of_strides > 4905 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) || 4906 (ucmd.single_wqe_log_num_of_strides < 4907 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) { 4908 mlx5_ib_dbg(dev, "Invalid log num strides (%u. Range is %u - %u)\n", 4909 ucmd.single_wqe_log_num_of_strides, 4910 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES, 4911 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES); 4912 return -EINVAL; 4913 } 4914 rwq->single_stride_log_num_of_bytes = 4915 ucmd.single_stride_log_num_of_bytes; 4916 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides; 4917 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en; 4918 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ; 4919 } 4920 4921 err = set_user_rq_size(dev, init_attr, &ucmd, rwq); 4922 if (err) { 4923 mlx5_ib_dbg(dev, "err %d\n", err); 4924 return err; 4925 } 4926 4927 err = create_user_rq(dev, pd, rwq, &ucmd); 4928 if (err) { 4929 mlx5_ib_dbg(dev, "err %d\n", err); 4930 if (err) 4931 return err; 4932 } 4933 4934 rwq->user_index = ucmd.user_index; 4935 return 0; 4936 } 4937 4938 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 4939 struct ib_wq_init_attr *init_attr, 4940 struct ib_udata *udata) 4941 { 4942 struct mlx5_ib_dev *dev; 4943 struct mlx5_ib_rwq *rwq; 4944 struct mlx5_ib_create_wq_resp resp = {}; 4945 size_t min_resp_len; 4946 int err; 4947 4948 if (!udata) 4949 return ERR_PTR(-ENOSYS); 4950 4951 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 4952 if (udata->outlen && udata->outlen < min_resp_len) 4953 return ERR_PTR(-EINVAL); 4954 4955 dev = to_mdev(pd->device); 4956 switch (init_attr->wq_type) { 4957 case IB_WQT_RQ: 4958 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL); 4959 if (!rwq) 4960 return ERR_PTR(-ENOMEM); 4961 err = prepare_user_rq(pd, init_attr, udata, rwq); 4962 if (err) 4963 goto err; 4964 err = create_rq(rwq, pd, init_attr); 4965 if (err) 4966 goto err_user_rq; 4967 break; 4968 default: 4969 mlx5_ib_dbg(dev, "unsupported wq type %d\n", 4970 init_attr->wq_type); 4971 return ERR_PTR(-EINVAL); 4972 } 4973 4974 rwq->ibwq.wq_num = rwq->core_qp.qpn; 4975 rwq->ibwq.state = IB_WQS_RESET; 4976 if (udata->outlen) { 4977 resp.response_length = offsetof(typeof(resp), response_length) + 4978 sizeof(resp.response_length); 4979 err = ib_copy_to_udata(udata, &resp, resp.response_length); 4980 if (err) 4981 goto err_copy; 4982 } 4983 4984 rwq->core_qp.event = mlx5_ib_wq_event; 4985 rwq->ibwq.event_handler = init_attr->event_handler; 4986 return &rwq->ibwq; 4987 4988 err_copy: 4989 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); 4990 err_user_rq: 4991 destroy_user_rq(dev, pd, rwq); 4992 err: 4993 kfree(rwq); 4994 return ERR_PTR(err); 4995 } 4996 4997 int mlx5_ib_destroy_wq(struct ib_wq *wq) 4998 { 4999 struct mlx5_ib_dev *dev = to_mdev(wq->device); 5000 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 5001 5002 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); 5003 destroy_user_rq(dev, wq->pd, rwq); 5004 kfree(rwq); 5005 5006 return 0; 5007 } 5008 5009 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device, 5010 struct ib_rwq_ind_table_init_attr *init_attr, 5011 struct ib_udata *udata) 5012 { 5013 struct mlx5_ib_dev *dev = to_mdev(device); 5014 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl; 5015 int sz = 1 << init_attr->log_ind_tbl_size; 5016 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {}; 5017 size_t min_resp_len; 5018 int inlen; 5019 int err; 5020 int i; 5021 u32 *in; 5022 void *rqtc; 5023 5024 if (udata->inlen > 0 && 5025 !ib_is_udata_cleared(udata, 0, 5026 udata->inlen)) 5027 return ERR_PTR(-EOPNOTSUPP); 5028 5029 if (init_attr->log_ind_tbl_size > 5030 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) { 5031 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n", 5032 init_attr->log_ind_tbl_size, 5033 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)); 5034 return ERR_PTR(-EINVAL); 5035 } 5036 5037 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 5038 if (udata->outlen && udata->outlen < min_resp_len) 5039 return ERR_PTR(-EINVAL); 5040 5041 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL); 5042 if (!rwq_ind_tbl) 5043 return ERR_PTR(-ENOMEM); 5044 5045 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; 5046 in = kvzalloc(inlen, GFP_KERNEL); 5047 if (!in) { 5048 err = -ENOMEM; 5049 goto err; 5050 } 5051 5052 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 5053 5054 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 5055 MLX5_SET(rqtc, rqtc, rqt_max_size, sz); 5056 5057 for (i = 0; i < sz; i++) 5058 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num); 5059 5060 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn); 5061 kvfree(in); 5062 5063 if (err) 5064 goto err; 5065 5066 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn; 5067 if (udata->outlen) { 5068 resp.response_length = offsetof(typeof(resp), response_length) + 5069 sizeof(resp.response_length); 5070 err = ib_copy_to_udata(udata, &resp, resp.response_length); 5071 if (err) 5072 goto err_copy; 5073 } 5074 5075 return &rwq_ind_tbl->ib_rwq_ind_tbl; 5076 5077 err_copy: 5078 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn); 5079 err: 5080 kfree(rwq_ind_tbl); 5081 return ERR_PTR(err); 5082 } 5083 5084 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 5085 { 5086 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl); 5087 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device); 5088 5089 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn); 5090 5091 kfree(rwq_ind_tbl); 5092 return 0; 5093 } 5094 5095 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 5096 u32 wq_attr_mask, struct ib_udata *udata) 5097 { 5098 struct mlx5_ib_dev *dev = to_mdev(wq->device); 5099 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 5100 struct mlx5_ib_modify_wq ucmd = {}; 5101 size_t required_cmd_sz; 5102 int curr_wq_state; 5103 int wq_state; 5104 int inlen; 5105 int err; 5106 void *rqc; 5107 void *in; 5108 5109 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved); 5110 if (udata->inlen < required_cmd_sz) 5111 return -EINVAL; 5112 5113 if (udata->inlen > sizeof(ucmd) && 5114 !ib_is_udata_cleared(udata, sizeof(ucmd), 5115 udata->inlen - sizeof(ucmd))) 5116 return -EOPNOTSUPP; 5117 5118 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) 5119 return -EFAULT; 5120 5121 if (ucmd.comp_mask || ucmd.reserved) 5122 return -EOPNOTSUPP; 5123 5124 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 5125 in = kvzalloc(inlen, GFP_KERNEL); 5126 if (!in) 5127 return -ENOMEM; 5128 5129 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 5130 5131 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ? 5132 wq_attr->curr_wq_state : wq->state; 5133 wq_state = (wq_attr_mask & IB_WQ_STATE) ? 5134 wq_attr->wq_state : curr_wq_state; 5135 if (curr_wq_state == IB_WQS_ERR) 5136 curr_wq_state = MLX5_RQC_STATE_ERR; 5137 if (wq_state == IB_WQS_ERR) 5138 wq_state = MLX5_RQC_STATE_ERR; 5139 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state); 5140 MLX5_SET(rqc, rqc, state, wq_state); 5141 5142 if (wq_attr_mask & IB_WQ_FLAGS) { 5143 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) { 5144 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 5145 MLX5_CAP_ETH(dev->mdev, vlan_cap))) { 5146 mlx5_ib_dbg(dev, "VLAN offloads are not " 5147 "supported\n"); 5148 err = -EOPNOTSUPP; 5149 goto out; 5150 } 5151 MLX5_SET64(modify_rq_in, in, modify_bitmask, 5152 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD); 5153 MLX5_SET(rqc, rqc, vsd, 5154 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1); 5155 } 5156 5157 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { 5158 mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n"); 5159 err = -EOPNOTSUPP; 5160 goto out; 5161 } 5162 } 5163 5164 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) { 5165 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 5166 MLX5_SET64(modify_rq_in, in, modify_bitmask, 5167 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 5168 MLX5_SET(rqc, rqc, counter_set_id, 5169 dev->port->cnts.set_id); 5170 } else 5171 pr_info_once("%s: Receive WQ counters are not supported on current FW\n", 5172 dev->ib_dev.name); 5173 } 5174 5175 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen); 5176 if (!err) 5177 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state; 5178 5179 out: 5180 kvfree(in); 5181 return err; 5182 } 5183