1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/module.h> 34 #include <rdma/ib_umem.h> 35 #include <rdma/ib_cache.h> 36 #include <rdma/ib_user_verbs.h> 37 #include <linux/mlx5/fs.h> 38 #include "mlx5_ib.h" 39 40 /* not supported currently */ 41 static int wq_signature; 42 43 enum { 44 MLX5_IB_ACK_REQ_FREQ = 8, 45 }; 46 47 enum { 48 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83, 49 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, 50 MLX5_IB_LINK_TYPE_IB = 0, 51 MLX5_IB_LINK_TYPE_ETH = 1 52 }; 53 54 enum { 55 MLX5_IB_SQ_STRIDE = 6, 56 }; 57 58 static const u32 mlx5_ib_opcode[] = { 59 [IB_WR_SEND] = MLX5_OPCODE_SEND, 60 [IB_WR_LSO] = MLX5_OPCODE_LSO, 61 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM, 62 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE, 63 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM, 64 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ, 65 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS, 66 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA, 67 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL, 68 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR, 69 [IB_WR_REG_MR] = MLX5_OPCODE_UMR, 70 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS, 71 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA, 72 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR, 73 }; 74 75 struct mlx5_wqe_eth_pad { 76 u8 rsvd0[16]; 77 }; 78 79 enum raw_qp_set_mask_map { 80 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0, 81 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1, 82 }; 83 84 struct mlx5_modify_raw_qp_param { 85 u16 operation; 86 87 u32 set_mask; /* raw_qp_set_mask_map */ 88 u32 rate_limit; 89 u8 rq_q_ctr_id; 90 }; 91 92 static void get_cqs(enum ib_qp_type qp_type, 93 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 94 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq); 95 96 static int is_qp0(enum ib_qp_type qp_type) 97 { 98 return qp_type == IB_QPT_SMI; 99 } 100 101 static int is_sqp(enum ib_qp_type qp_type) 102 { 103 return is_qp0(qp_type) || is_qp1(qp_type); 104 } 105 106 static void *get_wqe(struct mlx5_ib_qp *qp, int offset) 107 { 108 return mlx5_buf_offset(&qp->buf, offset); 109 } 110 111 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n) 112 { 113 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift)); 114 } 115 116 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n) 117 { 118 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE)); 119 } 120 121 /** 122 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space. 123 * 124 * @qp: QP to copy from. 125 * @send: copy from the send queue when non-zero, use the receive queue 126 * otherwise. 127 * @wqe_index: index to start copying from. For send work queues, the 128 * wqe_index is in units of MLX5_SEND_WQE_BB. 129 * For receive work queue, it is the number of work queue 130 * element in the queue. 131 * @buffer: destination buffer. 132 * @length: maximum number of bytes to copy. 133 * 134 * Copies at least a single WQE, but may copy more data. 135 * 136 * Return: the number of bytes copied, or an error code. 137 */ 138 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index, 139 void *buffer, u32 length, 140 struct mlx5_ib_qp_base *base) 141 { 142 struct ib_device *ibdev = qp->ibqp.device; 143 struct mlx5_ib_dev *dev = to_mdev(ibdev); 144 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq; 145 size_t offset; 146 size_t wq_end; 147 struct ib_umem *umem = base->ubuffer.umem; 148 u32 first_copy_length; 149 int wqe_length; 150 int ret; 151 152 if (wq->wqe_cnt == 0) { 153 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n", 154 qp->ibqp.qp_type); 155 return -EINVAL; 156 } 157 158 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift); 159 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift); 160 161 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg)) 162 return -EINVAL; 163 164 if (offset > umem->length || 165 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length)) 166 return -EINVAL; 167 168 first_copy_length = min_t(u32, offset + length, wq_end) - offset; 169 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length); 170 if (ret) 171 return ret; 172 173 if (send) { 174 struct mlx5_wqe_ctrl_seg *ctrl = buffer; 175 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; 176 177 wqe_length = ds * MLX5_WQE_DS_UNITS; 178 } else { 179 wqe_length = 1 << wq->wqe_shift; 180 } 181 182 if (wqe_length <= first_copy_length) 183 return first_copy_length; 184 185 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset, 186 wqe_length - first_copy_length); 187 if (ret) 188 return ret; 189 190 return wqe_length; 191 } 192 193 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type) 194 { 195 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; 196 struct ib_event event; 197 198 if (type == MLX5_EVENT_TYPE_PATH_MIG) { 199 /* This event is only valid for trans_qps */ 200 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port; 201 } 202 203 if (ibqp->event_handler) { 204 event.device = ibqp->device; 205 event.element.qp = ibqp; 206 switch (type) { 207 case MLX5_EVENT_TYPE_PATH_MIG: 208 event.event = IB_EVENT_PATH_MIG; 209 break; 210 case MLX5_EVENT_TYPE_COMM_EST: 211 event.event = IB_EVENT_COMM_EST; 212 break; 213 case MLX5_EVENT_TYPE_SQ_DRAINED: 214 event.event = IB_EVENT_SQ_DRAINED; 215 break; 216 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 217 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 218 break; 219 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 220 event.event = IB_EVENT_QP_FATAL; 221 break; 222 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 223 event.event = IB_EVENT_PATH_MIG_ERR; 224 break; 225 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 226 event.event = IB_EVENT_QP_REQ_ERR; 227 break; 228 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 229 event.event = IB_EVENT_QP_ACCESS_ERR; 230 break; 231 default: 232 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn); 233 return; 234 } 235 236 ibqp->event_handler(&event, ibqp->qp_context); 237 } 238 } 239 240 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap, 241 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd) 242 { 243 int wqe_size; 244 int wq_size; 245 246 /* Sanity check RQ size before proceeding */ 247 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) 248 return -EINVAL; 249 250 if (!has_rq) { 251 qp->rq.max_gs = 0; 252 qp->rq.wqe_cnt = 0; 253 qp->rq.wqe_shift = 0; 254 cap->max_recv_wr = 0; 255 cap->max_recv_sge = 0; 256 } else { 257 if (ucmd) { 258 qp->rq.wqe_cnt = ucmd->rq_wqe_count; 259 qp->rq.wqe_shift = ucmd->rq_wqe_shift; 260 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 261 qp->rq.max_post = qp->rq.wqe_cnt; 262 } else { 263 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0; 264 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg); 265 wqe_size = roundup_pow_of_two(wqe_size); 266 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size; 267 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB); 268 qp->rq.wqe_cnt = wq_size / wqe_size; 269 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) { 270 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n", 271 wqe_size, 272 MLX5_CAP_GEN(dev->mdev, 273 max_wqe_sz_rq)); 274 return -EINVAL; 275 } 276 qp->rq.wqe_shift = ilog2(wqe_size); 277 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 278 qp->rq.max_post = qp->rq.wqe_cnt; 279 } 280 } 281 282 return 0; 283 } 284 285 static int sq_overhead(struct ib_qp_init_attr *attr) 286 { 287 int size = 0; 288 289 switch (attr->qp_type) { 290 case IB_QPT_XRC_INI: 291 size += sizeof(struct mlx5_wqe_xrc_seg); 292 /* fall through */ 293 case IB_QPT_RC: 294 size += sizeof(struct mlx5_wqe_ctrl_seg) + 295 max(sizeof(struct mlx5_wqe_atomic_seg) + 296 sizeof(struct mlx5_wqe_raddr_seg), 297 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 298 sizeof(struct mlx5_mkey_seg)); 299 break; 300 301 case IB_QPT_XRC_TGT: 302 return 0; 303 304 case IB_QPT_UC: 305 size += sizeof(struct mlx5_wqe_ctrl_seg) + 306 max(sizeof(struct mlx5_wqe_raddr_seg), 307 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 308 sizeof(struct mlx5_mkey_seg)); 309 break; 310 311 case IB_QPT_UD: 312 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) 313 size += sizeof(struct mlx5_wqe_eth_pad) + 314 sizeof(struct mlx5_wqe_eth_seg); 315 /* fall through */ 316 case IB_QPT_SMI: 317 case MLX5_IB_QPT_HW_GSI: 318 size += sizeof(struct mlx5_wqe_ctrl_seg) + 319 sizeof(struct mlx5_wqe_datagram_seg); 320 break; 321 322 case MLX5_IB_QPT_REG_UMR: 323 size += sizeof(struct mlx5_wqe_ctrl_seg) + 324 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 325 sizeof(struct mlx5_mkey_seg); 326 break; 327 328 default: 329 return -EINVAL; 330 } 331 332 return size; 333 } 334 335 static int calc_send_wqe(struct ib_qp_init_attr *attr) 336 { 337 int inl_size = 0; 338 int size; 339 340 size = sq_overhead(attr); 341 if (size < 0) 342 return size; 343 344 if (attr->cap.max_inline_data) { 345 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) + 346 attr->cap.max_inline_data; 347 } 348 349 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg); 350 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN && 351 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE) 352 return MLX5_SIG_WQE_SIZE; 353 else 354 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB); 355 } 356 357 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size) 358 { 359 int max_sge; 360 361 if (attr->qp_type == IB_QPT_RC) 362 max_sge = (min_t(int, wqe_size, 512) - 363 sizeof(struct mlx5_wqe_ctrl_seg) - 364 sizeof(struct mlx5_wqe_raddr_seg)) / 365 sizeof(struct mlx5_wqe_data_seg); 366 else if (attr->qp_type == IB_QPT_XRC_INI) 367 max_sge = (min_t(int, wqe_size, 512) - 368 sizeof(struct mlx5_wqe_ctrl_seg) - 369 sizeof(struct mlx5_wqe_xrc_seg) - 370 sizeof(struct mlx5_wqe_raddr_seg)) / 371 sizeof(struct mlx5_wqe_data_seg); 372 else 373 max_sge = (wqe_size - sq_overhead(attr)) / 374 sizeof(struct mlx5_wqe_data_seg); 375 376 return min_t(int, max_sge, wqe_size - sq_overhead(attr) / 377 sizeof(struct mlx5_wqe_data_seg)); 378 } 379 380 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, 381 struct mlx5_ib_qp *qp) 382 { 383 int wqe_size; 384 int wq_size; 385 386 if (!attr->cap.max_send_wr) 387 return 0; 388 389 wqe_size = calc_send_wqe(attr); 390 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size); 391 if (wqe_size < 0) 392 return wqe_size; 393 394 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 395 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n", 396 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 397 return -EINVAL; 398 } 399 400 qp->max_inline_data = wqe_size - sq_overhead(attr) - 401 sizeof(struct mlx5_wqe_inline_seg); 402 attr->cap.max_inline_data = qp->max_inline_data; 403 404 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN) 405 qp->signature_en = true; 406 407 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size); 408 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB; 409 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 410 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n", 411 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB, 412 qp->sq.wqe_cnt, 413 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 414 return -ENOMEM; 415 } 416 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 417 qp->sq.max_gs = get_send_sge(attr, wqe_size); 418 if (qp->sq.max_gs < attr->cap.max_send_sge) 419 return -ENOMEM; 420 421 attr->cap.max_send_sge = qp->sq.max_gs; 422 qp->sq.max_post = wq_size / wqe_size; 423 attr->cap.max_send_wr = qp->sq.max_post; 424 425 return wq_size; 426 } 427 428 static int set_user_buf_size(struct mlx5_ib_dev *dev, 429 struct mlx5_ib_qp *qp, 430 struct mlx5_ib_create_qp *ucmd, 431 struct mlx5_ib_qp_base *base, 432 struct ib_qp_init_attr *attr) 433 { 434 int desc_sz = 1 << qp->sq.wqe_shift; 435 436 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 437 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n", 438 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 439 return -EINVAL; 440 } 441 442 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) { 443 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n", 444 ucmd->sq_wqe_count, ucmd->sq_wqe_count); 445 return -EINVAL; 446 } 447 448 qp->sq.wqe_cnt = ucmd->sq_wqe_count; 449 450 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 451 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n", 452 qp->sq.wqe_cnt, 453 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 454 return -EINVAL; 455 } 456 457 if (attr->qp_type == IB_QPT_RAW_PACKET || 458 qp->flags & MLX5_IB_QP_UNDERLAY) { 459 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift; 460 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6; 461 } else { 462 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 463 (qp->sq.wqe_cnt << 6); 464 } 465 466 return 0; 467 } 468 469 static int qp_has_rq(struct ib_qp_init_attr *attr) 470 { 471 if (attr->qp_type == IB_QPT_XRC_INI || 472 attr->qp_type == IB_QPT_XRC_TGT || attr->srq || 473 attr->qp_type == MLX5_IB_QPT_REG_UMR || 474 !attr->cap.max_recv_wr) 475 return 0; 476 477 return 1; 478 } 479 480 static int first_med_bfreg(void) 481 { 482 return 1; 483 } 484 485 enum { 486 /* this is the first blue flame register in the array of bfregs assigned 487 * to a processes. Since we do not use it for blue flame but rather 488 * regular 64 bit doorbells, we do not need a lock for maintaiing 489 * "odd/even" order 490 */ 491 NUM_NON_BLUE_FLAME_BFREGS = 1, 492 }; 493 494 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi) 495 { 496 return get_num_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR; 497 } 498 499 static int num_med_bfreg(struct mlx5_ib_dev *dev, 500 struct mlx5_bfreg_info *bfregi) 501 { 502 int n; 503 504 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs - 505 NUM_NON_BLUE_FLAME_BFREGS; 506 507 return n >= 0 ? n : 0; 508 } 509 510 static int first_hi_bfreg(struct mlx5_ib_dev *dev, 511 struct mlx5_bfreg_info *bfregi) 512 { 513 int med; 514 515 med = num_med_bfreg(dev, bfregi); 516 return ++med; 517 } 518 519 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev, 520 struct mlx5_bfreg_info *bfregi) 521 { 522 int i; 523 524 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) { 525 if (!bfregi->count[i]) { 526 bfregi->count[i]++; 527 return i; 528 } 529 } 530 531 return -ENOMEM; 532 } 533 534 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev, 535 struct mlx5_bfreg_info *bfregi) 536 { 537 int minidx = first_med_bfreg(); 538 int i; 539 540 for (i = first_med_bfreg(); i < first_hi_bfreg(dev, bfregi); i++) { 541 if (bfregi->count[i] < bfregi->count[minidx]) 542 minidx = i; 543 if (!bfregi->count[minidx]) 544 break; 545 } 546 547 bfregi->count[minidx]++; 548 return minidx; 549 } 550 551 static int alloc_bfreg(struct mlx5_ib_dev *dev, 552 struct mlx5_bfreg_info *bfregi, 553 enum mlx5_ib_latency_class lat) 554 { 555 int bfregn = -EINVAL; 556 557 mutex_lock(&bfregi->lock); 558 switch (lat) { 559 case MLX5_IB_LATENCY_CLASS_LOW: 560 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1); 561 bfregn = 0; 562 bfregi->count[bfregn]++; 563 break; 564 565 case MLX5_IB_LATENCY_CLASS_MEDIUM: 566 if (bfregi->ver < 2) 567 bfregn = -ENOMEM; 568 else 569 bfregn = alloc_med_class_bfreg(dev, bfregi); 570 break; 571 572 case MLX5_IB_LATENCY_CLASS_HIGH: 573 if (bfregi->ver < 2) 574 bfregn = -ENOMEM; 575 else 576 bfregn = alloc_high_class_bfreg(dev, bfregi); 577 break; 578 } 579 mutex_unlock(&bfregi->lock); 580 581 return bfregn; 582 } 583 584 static void free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn) 585 { 586 mutex_lock(&bfregi->lock); 587 bfregi->count[bfregn]--; 588 mutex_unlock(&bfregi->lock); 589 } 590 591 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state) 592 { 593 switch (state) { 594 case IB_QPS_RESET: return MLX5_QP_STATE_RST; 595 case IB_QPS_INIT: return MLX5_QP_STATE_INIT; 596 case IB_QPS_RTR: return MLX5_QP_STATE_RTR; 597 case IB_QPS_RTS: return MLX5_QP_STATE_RTS; 598 case IB_QPS_SQD: return MLX5_QP_STATE_SQD; 599 case IB_QPS_SQE: return MLX5_QP_STATE_SQER; 600 case IB_QPS_ERR: return MLX5_QP_STATE_ERR; 601 default: return -1; 602 } 603 } 604 605 static int to_mlx5_st(enum ib_qp_type type) 606 { 607 switch (type) { 608 case IB_QPT_RC: return MLX5_QP_ST_RC; 609 case IB_QPT_UC: return MLX5_QP_ST_UC; 610 case IB_QPT_UD: return MLX5_QP_ST_UD; 611 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR; 612 case IB_QPT_XRC_INI: 613 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC; 614 case IB_QPT_SMI: return MLX5_QP_ST_QP0; 615 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1; 616 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6; 617 case IB_QPT_RAW_PACKET: 618 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE; 619 case IB_QPT_MAX: 620 default: return -EINVAL; 621 } 622 } 623 624 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, 625 struct mlx5_ib_cq *recv_cq); 626 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, 627 struct mlx5_ib_cq *recv_cq); 628 629 static int bfregn_to_uar_index(struct mlx5_ib_dev *dev, 630 struct mlx5_bfreg_info *bfregi, int bfregn) 631 { 632 int bfregs_per_sys_page; 633 int index_of_sys_page; 634 int offset; 635 636 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * 637 MLX5_NON_FP_BFREGS_PER_UAR; 638 index_of_sys_page = bfregn / bfregs_per_sys_page; 639 640 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR; 641 642 return bfregi->sys_pages[index_of_sys_page] + offset; 643 } 644 645 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev, 646 struct ib_pd *pd, 647 unsigned long addr, size_t size, 648 struct ib_umem **umem, 649 int *npages, int *page_shift, int *ncont, 650 u32 *offset) 651 { 652 int err; 653 654 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0); 655 if (IS_ERR(*umem)) { 656 mlx5_ib_dbg(dev, "umem_get failed\n"); 657 return PTR_ERR(*umem); 658 } 659 660 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL); 661 662 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset); 663 if (err) { 664 mlx5_ib_warn(dev, "bad offset\n"); 665 goto err_umem; 666 } 667 668 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n", 669 addr, size, *npages, *page_shift, *ncont, *offset); 670 671 return 0; 672 673 err_umem: 674 ib_umem_release(*umem); 675 *umem = NULL; 676 677 return err; 678 } 679 680 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 681 struct mlx5_ib_rwq *rwq) 682 { 683 struct mlx5_ib_ucontext *context; 684 685 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP) 686 atomic_dec(&dev->delay_drop.rqs_cnt); 687 688 context = to_mucontext(pd->uobject->context); 689 mlx5_ib_db_unmap_user(context, &rwq->db); 690 if (rwq->umem) 691 ib_umem_release(rwq->umem); 692 } 693 694 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 695 struct mlx5_ib_rwq *rwq, 696 struct mlx5_ib_create_wq *ucmd) 697 { 698 struct mlx5_ib_ucontext *context; 699 int page_shift = 0; 700 int npages; 701 u32 offset = 0; 702 int ncont = 0; 703 int err; 704 705 if (!ucmd->buf_addr) 706 return -EINVAL; 707 708 context = to_mucontext(pd->uobject->context); 709 rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr, 710 rwq->buf_size, 0, 0); 711 if (IS_ERR(rwq->umem)) { 712 mlx5_ib_dbg(dev, "umem_get failed\n"); 713 err = PTR_ERR(rwq->umem); 714 return err; 715 } 716 717 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift, 718 &ncont, NULL); 719 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift, 720 &rwq->rq_page_offset); 721 if (err) { 722 mlx5_ib_warn(dev, "bad offset\n"); 723 goto err_umem; 724 } 725 726 rwq->rq_num_pas = ncont; 727 rwq->page_shift = page_shift; 728 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT; 729 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE); 730 731 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n", 732 (unsigned long long)ucmd->buf_addr, rwq->buf_size, 733 npages, page_shift, ncont, offset); 734 735 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db); 736 if (err) { 737 mlx5_ib_dbg(dev, "map failed\n"); 738 goto err_umem; 739 } 740 741 rwq->create_type = MLX5_WQ_USER; 742 return 0; 743 744 err_umem: 745 ib_umem_release(rwq->umem); 746 return err; 747 } 748 749 static int adjust_bfregn(struct mlx5_ib_dev *dev, 750 struct mlx5_bfreg_info *bfregi, int bfregn) 751 { 752 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR + 753 bfregn % MLX5_NON_FP_BFREGS_PER_UAR; 754 } 755 756 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 757 struct mlx5_ib_qp *qp, struct ib_udata *udata, 758 struct ib_qp_init_attr *attr, 759 u32 **in, 760 struct mlx5_ib_create_qp_resp *resp, int *inlen, 761 struct mlx5_ib_qp_base *base) 762 { 763 struct mlx5_ib_ucontext *context; 764 struct mlx5_ib_create_qp ucmd; 765 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer; 766 int page_shift = 0; 767 int uar_index; 768 int npages; 769 u32 offset = 0; 770 int bfregn; 771 int ncont = 0; 772 __be64 *pas; 773 void *qpc; 774 int err; 775 776 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd)); 777 if (err) { 778 mlx5_ib_dbg(dev, "copy failed\n"); 779 return err; 780 } 781 782 context = to_mucontext(pd->uobject->context); 783 /* 784 * TBD: should come from the verbs when we have the API 785 */ 786 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 787 /* In CROSS_CHANNEL CQ and QP must use the same UAR */ 788 bfregn = MLX5_CROSS_CHANNEL_BFREG; 789 else { 790 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_HIGH); 791 if (bfregn < 0) { 792 mlx5_ib_dbg(dev, "failed to allocate low latency BFREG\n"); 793 mlx5_ib_dbg(dev, "reverting to medium latency\n"); 794 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_MEDIUM); 795 if (bfregn < 0) { 796 mlx5_ib_dbg(dev, "failed to allocate medium latency BFREG\n"); 797 mlx5_ib_dbg(dev, "reverting to high latency\n"); 798 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_LOW); 799 if (bfregn < 0) { 800 mlx5_ib_warn(dev, "bfreg allocation failed\n"); 801 return bfregn; 802 } 803 } 804 } 805 } 806 807 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn); 808 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index); 809 810 qp->rq.offset = 0; 811 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 812 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 813 814 err = set_user_buf_size(dev, qp, &ucmd, base, attr); 815 if (err) 816 goto err_bfreg; 817 818 if (ucmd.buf_addr && ubuffer->buf_size) { 819 ubuffer->buf_addr = ucmd.buf_addr; 820 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, 821 ubuffer->buf_size, 822 &ubuffer->umem, &npages, &page_shift, 823 &ncont, &offset); 824 if (err) 825 goto err_bfreg; 826 } else { 827 ubuffer->umem = NULL; 828 } 829 830 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 831 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont; 832 *in = kvzalloc(*inlen, GFP_KERNEL); 833 if (!*in) { 834 err = -ENOMEM; 835 goto err_umem; 836 } 837 838 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas); 839 if (ubuffer->umem) 840 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0); 841 842 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 843 844 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT); 845 MLX5_SET(qpc, qpc, page_offset, offset); 846 847 MLX5_SET(qpc, qpc, uar_page, uar_index); 848 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn); 849 qp->bfregn = bfregn; 850 851 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db); 852 if (err) { 853 mlx5_ib_dbg(dev, "map failed\n"); 854 goto err_free; 855 } 856 857 err = ib_copy_to_udata(udata, resp, sizeof(*resp)); 858 if (err) { 859 mlx5_ib_dbg(dev, "copy failed\n"); 860 goto err_unmap; 861 } 862 qp->create_type = MLX5_QP_USER; 863 864 return 0; 865 866 err_unmap: 867 mlx5_ib_db_unmap_user(context, &qp->db); 868 869 err_free: 870 kvfree(*in); 871 872 err_umem: 873 if (ubuffer->umem) 874 ib_umem_release(ubuffer->umem); 875 876 err_bfreg: 877 free_bfreg(dev, &context->bfregi, bfregn); 878 return err; 879 } 880 881 static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd, 882 struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base) 883 { 884 struct mlx5_ib_ucontext *context; 885 886 context = to_mucontext(pd->uobject->context); 887 mlx5_ib_db_unmap_user(context, &qp->db); 888 if (base->ubuffer.umem) 889 ib_umem_release(base->ubuffer.umem); 890 free_bfreg(dev, &context->bfregi, qp->bfregn); 891 } 892 893 static int create_kernel_qp(struct mlx5_ib_dev *dev, 894 struct ib_qp_init_attr *init_attr, 895 struct mlx5_ib_qp *qp, 896 u32 **in, int *inlen, 897 struct mlx5_ib_qp_base *base) 898 { 899 int uar_index; 900 void *qpc; 901 int err; 902 903 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN | 904 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK | 905 IB_QP_CREATE_IPOIB_UD_LSO | 906 IB_QP_CREATE_NETIF_QP | 907 mlx5_ib_create_qp_sqpn_qp1())) 908 return -EINVAL; 909 910 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR) 911 qp->bf.bfreg = &dev->fp_bfreg; 912 else 913 qp->bf.bfreg = &dev->bfreg; 914 915 /* We need to divide by two since each register is comprised of 916 * two buffers of identical size, namely odd and even 917 */ 918 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2; 919 uar_index = qp->bf.bfreg->index; 920 921 err = calc_sq_size(dev, init_attr, qp); 922 if (err < 0) { 923 mlx5_ib_dbg(dev, "err %d\n", err); 924 return err; 925 } 926 927 qp->rq.offset = 0; 928 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 929 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift); 930 931 err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf); 932 if (err) { 933 mlx5_ib_dbg(dev, "err %d\n", err); 934 return err; 935 } 936 937 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt); 938 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 939 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages; 940 *in = kvzalloc(*inlen, GFP_KERNEL); 941 if (!*in) { 942 err = -ENOMEM; 943 goto err_buf; 944 } 945 946 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 947 MLX5_SET(qpc, qpc, uar_page, uar_index); 948 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT); 949 950 /* Set "fast registration enabled" for all kernel QPs */ 951 MLX5_SET(qpc, qpc, fre, 1); 952 MLX5_SET(qpc, qpc, rlky, 1); 953 954 if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) { 955 MLX5_SET(qpc, qpc, deth_sqpn, 1); 956 qp->flags |= MLX5_IB_QP_SQPN_QP1; 957 } 958 959 mlx5_fill_page_array(&qp->buf, 960 (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas)); 961 962 err = mlx5_db_alloc(dev->mdev, &qp->db); 963 if (err) { 964 mlx5_ib_dbg(dev, "err %d\n", err); 965 goto err_free; 966 } 967 968 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt, 969 sizeof(*qp->sq.wrid), GFP_KERNEL); 970 qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt, 971 sizeof(*qp->sq.wr_data), GFP_KERNEL); 972 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt, 973 sizeof(*qp->rq.wrid), GFP_KERNEL); 974 qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt, 975 sizeof(*qp->sq.w_list), GFP_KERNEL); 976 qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt, 977 sizeof(*qp->sq.wqe_head), GFP_KERNEL); 978 979 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid || 980 !qp->sq.w_list || !qp->sq.wqe_head) { 981 err = -ENOMEM; 982 goto err_wrid; 983 } 984 qp->create_type = MLX5_QP_KERNEL; 985 986 return 0; 987 988 err_wrid: 989 kvfree(qp->sq.wqe_head); 990 kvfree(qp->sq.w_list); 991 kvfree(qp->sq.wrid); 992 kvfree(qp->sq.wr_data); 993 kvfree(qp->rq.wrid); 994 mlx5_db_free(dev->mdev, &qp->db); 995 996 err_free: 997 kvfree(*in); 998 999 err_buf: 1000 mlx5_buf_free(dev->mdev, &qp->buf); 1001 return err; 1002 } 1003 1004 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1005 { 1006 kvfree(qp->sq.wqe_head); 1007 kvfree(qp->sq.w_list); 1008 kvfree(qp->sq.wrid); 1009 kvfree(qp->sq.wr_data); 1010 kvfree(qp->rq.wrid); 1011 mlx5_db_free(dev->mdev, &qp->db); 1012 mlx5_buf_free(dev->mdev, &qp->buf); 1013 } 1014 1015 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr) 1016 { 1017 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) || 1018 (attr->qp_type == IB_QPT_XRC_INI)) 1019 return MLX5_SRQ_RQ; 1020 else if (!qp->has_rq) 1021 return MLX5_ZERO_LEN_RQ; 1022 else 1023 return MLX5_NON_ZERO_RQ; 1024 } 1025 1026 static int is_connected(enum ib_qp_type qp_type) 1027 { 1028 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC) 1029 return 1; 1030 1031 return 0; 1032 } 1033 1034 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1035 struct mlx5_ib_qp *qp, 1036 struct mlx5_ib_sq *sq, u32 tdn) 1037 { 1038 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 1039 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 1040 1041 MLX5_SET(tisc, tisc, transport_domain, tdn); 1042 if (qp->flags & MLX5_IB_QP_UNDERLAY) 1043 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn); 1044 1045 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn); 1046 } 1047 1048 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1049 struct mlx5_ib_sq *sq) 1050 { 1051 mlx5_core_destroy_tis(dev->mdev, sq->tisn); 1052 } 1053 1054 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1055 struct mlx5_ib_sq *sq, void *qpin, 1056 struct ib_pd *pd) 1057 { 1058 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer; 1059 __be64 *pas; 1060 void *in; 1061 void *sqc; 1062 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1063 void *wq; 1064 int inlen; 1065 int err; 1066 int page_shift = 0; 1067 int npages; 1068 int ncont = 0; 1069 u32 offset = 0; 1070 1071 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size, 1072 &sq->ubuffer.umem, &npages, &page_shift, 1073 &ncont, &offset); 1074 if (err) 1075 return err; 1076 1077 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont; 1078 in = kvzalloc(inlen, GFP_KERNEL); 1079 if (!in) { 1080 err = -ENOMEM; 1081 goto err_umem; 1082 } 1083 1084 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 1085 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 1086 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 1087 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1088 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd)); 1089 MLX5_SET(sqc, sqc, tis_lst_sz, 1); 1090 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn); 1091 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 1092 MLX5_CAP_ETH(dev->mdev, swp)) 1093 MLX5_SET(sqc, sqc, allow_swp, 1); 1094 1095 wq = MLX5_ADDR_OF(sqc, sqc, wq); 1096 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1097 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1098 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page)); 1099 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1100 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 1101 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size)); 1102 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT); 1103 MLX5_SET(wq, wq, page_offset, offset); 1104 1105 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1106 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0); 1107 1108 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp); 1109 1110 kvfree(in); 1111 1112 if (err) 1113 goto err_umem; 1114 1115 return 0; 1116 1117 err_umem: 1118 ib_umem_release(sq->ubuffer.umem); 1119 sq->ubuffer.umem = NULL; 1120 1121 return err; 1122 } 1123 1124 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1125 struct mlx5_ib_sq *sq) 1126 { 1127 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp); 1128 ib_umem_release(sq->ubuffer.umem); 1129 } 1130 1131 static int get_rq_pas_size(void *qpc) 1132 { 1133 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12; 1134 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride); 1135 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size); 1136 u32 page_offset = MLX5_GET(qpc, qpc, page_offset); 1137 u32 po_quanta = 1 << (log_page_size - 6); 1138 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride); 1139 u32 page_size = 1 << log_page_size; 1140 u32 rq_sz_po = rq_sz + (page_offset * po_quanta); 1141 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size; 1142 1143 return rq_num_pas * sizeof(u64); 1144 } 1145 1146 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1147 struct mlx5_ib_rq *rq, void *qpin) 1148 { 1149 struct mlx5_ib_qp *mqp = rq->base.container_mibqp; 1150 __be64 *pas; 1151 __be64 *qp_pas; 1152 void *in; 1153 void *rqc; 1154 void *wq; 1155 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1156 int inlen; 1157 int err; 1158 u32 rq_pas_size = get_rq_pas_size(qpc); 1159 1160 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size; 1161 in = kvzalloc(inlen, GFP_KERNEL); 1162 if (!in) 1163 return -ENOMEM; 1164 1165 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 1166 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING)) 1167 MLX5_SET(rqc, rqc, vsd, 1); 1168 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 1169 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 1170 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 1171 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1172 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv)); 1173 1174 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS) 1175 MLX5_SET(rqc, rqc, scatter_fcs, 1); 1176 1177 wq = MLX5_ADDR_OF(rqc, rqc, wq); 1178 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1179 MLX5_SET(wq, wq, end_padding_mode, 1180 MLX5_GET(qpc, qpc, end_padding_mode)); 1181 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset)); 1182 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1183 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1184 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4); 1185 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size)); 1186 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size)); 1187 1188 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1189 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas); 1190 memcpy(pas, qp_pas, rq_pas_size); 1191 1192 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp); 1193 1194 kvfree(in); 1195 1196 return err; 1197 } 1198 1199 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1200 struct mlx5_ib_rq *rq) 1201 { 1202 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp); 1203 } 1204 1205 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1206 struct mlx5_ib_rq *rq, u32 tdn) 1207 { 1208 u32 *in; 1209 void *tirc; 1210 int inlen; 1211 int err; 1212 1213 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1214 in = kvzalloc(inlen, GFP_KERNEL); 1215 if (!in) 1216 return -ENOMEM; 1217 1218 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1219 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT); 1220 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn); 1221 MLX5_SET(tirc, tirc, transport_domain, tdn); 1222 1223 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn); 1224 1225 kvfree(in); 1226 1227 return err; 1228 } 1229 1230 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1231 struct mlx5_ib_rq *rq) 1232 { 1233 mlx5_core_destroy_tir(dev->mdev, rq->tirn); 1234 } 1235 1236 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1237 u32 *in, 1238 struct ib_pd *pd) 1239 { 1240 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1241 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1242 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1243 struct ib_uobject *uobj = pd->uobject; 1244 struct ib_ucontext *ucontext = uobj->context; 1245 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext); 1246 int err; 1247 u32 tdn = mucontext->tdn; 1248 1249 if (qp->sq.wqe_cnt) { 1250 err = create_raw_packet_qp_tis(dev, qp, sq, tdn); 1251 if (err) 1252 return err; 1253 1254 err = create_raw_packet_qp_sq(dev, sq, in, pd); 1255 if (err) 1256 goto err_destroy_tis; 1257 1258 sq->base.container_mibqp = qp; 1259 sq->base.mqp.event = mlx5_ib_qp_event; 1260 } 1261 1262 if (qp->rq.wqe_cnt) { 1263 rq->base.container_mibqp = qp; 1264 1265 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING) 1266 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING; 1267 err = create_raw_packet_qp_rq(dev, rq, in); 1268 if (err) 1269 goto err_destroy_sq; 1270 1271 1272 err = create_raw_packet_qp_tir(dev, rq, tdn); 1273 if (err) 1274 goto err_destroy_rq; 1275 } 1276 1277 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn : 1278 rq->base.mqp.qpn; 1279 1280 return 0; 1281 1282 err_destroy_rq: 1283 destroy_raw_packet_qp_rq(dev, rq); 1284 err_destroy_sq: 1285 if (!qp->sq.wqe_cnt) 1286 return err; 1287 destroy_raw_packet_qp_sq(dev, sq); 1288 err_destroy_tis: 1289 destroy_raw_packet_qp_tis(dev, sq); 1290 1291 return err; 1292 } 1293 1294 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev, 1295 struct mlx5_ib_qp *qp) 1296 { 1297 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1298 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1299 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1300 1301 if (qp->rq.wqe_cnt) { 1302 destroy_raw_packet_qp_tir(dev, rq); 1303 destroy_raw_packet_qp_rq(dev, rq); 1304 } 1305 1306 if (qp->sq.wqe_cnt) { 1307 destroy_raw_packet_qp_sq(dev, sq); 1308 destroy_raw_packet_qp_tis(dev, sq); 1309 } 1310 } 1311 1312 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp, 1313 struct mlx5_ib_raw_packet_qp *raw_packet_qp) 1314 { 1315 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1316 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1317 1318 sq->sq = &qp->sq; 1319 rq->rq = &qp->rq; 1320 sq->doorbell = &qp->db; 1321 rq->doorbell = &qp->db; 1322 } 1323 1324 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1325 { 1326 mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn); 1327 } 1328 1329 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1330 struct ib_pd *pd, 1331 struct ib_qp_init_attr *init_attr, 1332 struct ib_udata *udata) 1333 { 1334 struct ib_uobject *uobj = pd->uobject; 1335 struct ib_ucontext *ucontext = uobj->context; 1336 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext); 1337 struct mlx5_ib_create_qp_resp resp = {}; 1338 int inlen; 1339 int err; 1340 u32 *in; 1341 void *tirc; 1342 void *hfso; 1343 u32 selected_fields = 0; 1344 size_t min_resp_len; 1345 u32 tdn = mucontext->tdn; 1346 struct mlx5_ib_create_qp_rss ucmd = {}; 1347 size_t required_cmd_sz; 1348 1349 if (init_attr->qp_type != IB_QPT_RAW_PACKET) 1350 return -EOPNOTSUPP; 1351 1352 if (init_attr->create_flags || init_attr->send_cq) 1353 return -EINVAL; 1354 1355 min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index); 1356 if (udata->outlen < min_resp_len) 1357 return -EINVAL; 1358 1359 required_cmd_sz = offsetof(typeof(ucmd), reserved1) + sizeof(ucmd.reserved1); 1360 if (udata->inlen < required_cmd_sz) { 1361 mlx5_ib_dbg(dev, "invalid inlen\n"); 1362 return -EINVAL; 1363 } 1364 1365 if (udata->inlen > sizeof(ucmd) && 1366 !ib_is_udata_cleared(udata, sizeof(ucmd), 1367 udata->inlen - sizeof(ucmd))) { 1368 mlx5_ib_dbg(dev, "inlen is not supported\n"); 1369 return -EOPNOTSUPP; 1370 } 1371 1372 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 1373 mlx5_ib_dbg(dev, "copy failed\n"); 1374 return -EFAULT; 1375 } 1376 1377 if (ucmd.comp_mask) { 1378 mlx5_ib_dbg(dev, "invalid comp mask\n"); 1379 return -EOPNOTSUPP; 1380 } 1381 1382 if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved)) || ucmd.reserved1) { 1383 mlx5_ib_dbg(dev, "invalid reserved\n"); 1384 return -EOPNOTSUPP; 1385 } 1386 1387 err = ib_copy_to_udata(udata, &resp, min_resp_len); 1388 if (err) { 1389 mlx5_ib_dbg(dev, "copy failed\n"); 1390 return -EINVAL; 1391 } 1392 1393 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1394 in = kvzalloc(inlen, GFP_KERNEL); 1395 if (!in) 1396 return -ENOMEM; 1397 1398 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1399 MLX5_SET(tirc, tirc, disp_type, 1400 MLX5_TIRC_DISP_TYPE_INDIRECT); 1401 MLX5_SET(tirc, tirc, indirect_table, 1402 init_attr->rwq_ind_tbl->ind_tbl_num); 1403 MLX5_SET(tirc, tirc, transport_domain, tdn); 1404 1405 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1406 switch (ucmd.rx_hash_function) { 1407 case MLX5_RX_HASH_FUNC_TOEPLITZ: 1408 { 1409 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key); 1410 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key); 1411 1412 if (len != ucmd.rx_key_len) { 1413 err = -EINVAL; 1414 goto err; 1415 } 1416 1417 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ); 1418 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1); 1419 memcpy(rss_key, ucmd.rx_hash_key, len); 1420 break; 1421 } 1422 default: 1423 err = -EOPNOTSUPP; 1424 goto err; 1425 } 1426 1427 if (!ucmd.rx_hash_fields_mask) { 1428 /* special case when this TIR serves as steering entry without hashing */ 1429 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size) 1430 goto create_tir; 1431 err = -EINVAL; 1432 goto err; 1433 } 1434 1435 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1436 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) && 1437 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1438 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) { 1439 err = -EINVAL; 1440 goto err; 1441 } 1442 1443 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */ 1444 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1445 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) 1446 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1447 MLX5_L3_PROT_TYPE_IPV4); 1448 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1449 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1450 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1451 MLX5_L3_PROT_TYPE_IPV6); 1452 1453 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1454 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) && 1455 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1456 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))) { 1457 err = -EINVAL; 1458 goto err; 1459 } 1460 1461 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */ 1462 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1463 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) 1464 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1465 MLX5_L4_PROT_TYPE_TCP); 1466 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1467 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1468 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1469 MLX5_L4_PROT_TYPE_UDP); 1470 1471 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1472 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6)) 1473 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP; 1474 1475 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) || 1476 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1477 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP; 1478 1479 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1480 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP)) 1481 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT; 1482 1483 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) || 1484 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1485 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT; 1486 1487 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields); 1488 1489 create_tir: 1490 err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn); 1491 1492 if (err) 1493 goto err; 1494 1495 kvfree(in); 1496 /* qpn is reserved for that QP */ 1497 qp->trans_qp.base.mqp.qpn = 0; 1498 qp->flags |= MLX5_IB_QP_RSS; 1499 return 0; 1500 1501 err: 1502 kvfree(in); 1503 return err; 1504 } 1505 1506 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd, 1507 struct ib_qp_init_attr *init_attr, 1508 struct ib_udata *udata, struct mlx5_ib_qp *qp) 1509 { 1510 struct mlx5_ib_resources *devr = &dev->devr; 1511 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 1512 struct mlx5_core_dev *mdev = dev->mdev; 1513 struct mlx5_ib_create_qp_resp resp; 1514 struct mlx5_ib_cq *send_cq; 1515 struct mlx5_ib_cq *recv_cq; 1516 unsigned long flags; 1517 u32 uidx = MLX5_IB_DEFAULT_UIDX; 1518 struct mlx5_ib_create_qp ucmd; 1519 struct mlx5_ib_qp_base *base; 1520 void *qpc; 1521 u32 *in; 1522 int err; 1523 1524 mutex_init(&qp->mutex); 1525 spin_lock_init(&qp->sq.lock); 1526 spin_lock_init(&qp->rq.lock); 1527 1528 if (init_attr->rwq_ind_tbl) { 1529 if (!udata) 1530 return -ENOSYS; 1531 1532 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata); 1533 return err; 1534 } 1535 1536 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) { 1537 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) { 1538 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n"); 1539 return -EINVAL; 1540 } else { 1541 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK; 1542 } 1543 } 1544 1545 if (init_attr->create_flags & 1546 (IB_QP_CREATE_CROSS_CHANNEL | 1547 IB_QP_CREATE_MANAGED_SEND | 1548 IB_QP_CREATE_MANAGED_RECV)) { 1549 if (!MLX5_CAP_GEN(mdev, cd)) { 1550 mlx5_ib_dbg(dev, "cross-channel isn't supported\n"); 1551 return -EINVAL; 1552 } 1553 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL) 1554 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL; 1555 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND) 1556 qp->flags |= MLX5_IB_QP_MANAGED_SEND; 1557 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV) 1558 qp->flags |= MLX5_IB_QP_MANAGED_RECV; 1559 } 1560 1561 if (init_attr->qp_type == IB_QPT_UD && 1562 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) 1563 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 1564 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n"); 1565 return -EOPNOTSUPP; 1566 } 1567 1568 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) { 1569 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 1570 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs"); 1571 return -EOPNOTSUPP; 1572 } 1573 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) || 1574 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) { 1575 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n"); 1576 return -EOPNOTSUPP; 1577 } 1578 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS; 1579 } 1580 1581 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 1582 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 1583 1584 if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) { 1585 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 1586 MLX5_CAP_ETH(dev->mdev, vlan_cap)) || 1587 (init_attr->qp_type != IB_QPT_RAW_PACKET)) 1588 return -EOPNOTSUPP; 1589 qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING; 1590 } 1591 1592 if (pd && pd->uobject) { 1593 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) { 1594 mlx5_ib_dbg(dev, "copy failed\n"); 1595 return -EFAULT; 1596 } 1597 1598 err = get_qp_user_index(to_mucontext(pd->uobject->context), 1599 &ucmd, udata->inlen, &uidx); 1600 if (err) 1601 return err; 1602 1603 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE); 1604 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE); 1605 1606 if (init_attr->create_flags & IB_QP_CREATE_SOURCE_QPN) { 1607 if (init_attr->qp_type != IB_QPT_UD || 1608 (MLX5_CAP_GEN(dev->mdev, port_type) != 1609 MLX5_CAP_PORT_TYPE_IB) || 1610 !mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) { 1611 mlx5_ib_dbg(dev, "Source QP option isn't supported\n"); 1612 return -EOPNOTSUPP; 1613 } 1614 1615 qp->flags |= MLX5_IB_QP_UNDERLAY; 1616 qp->underlay_qpn = init_attr->source_qpn; 1617 } 1618 } else { 1619 qp->wq_sig = !!wq_signature; 1620 } 1621 1622 base = (init_attr->qp_type == IB_QPT_RAW_PACKET || 1623 qp->flags & MLX5_IB_QP_UNDERLAY) ? 1624 &qp->raw_packet_qp.rq.base : 1625 &qp->trans_qp.base; 1626 1627 qp->has_rq = qp_has_rq(init_attr); 1628 err = set_rq_size(dev, &init_attr->cap, qp->has_rq, 1629 qp, (pd && pd->uobject) ? &ucmd : NULL); 1630 if (err) { 1631 mlx5_ib_dbg(dev, "err %d\n", err); 1632 return err; 1633 } 1634 1635 if (pd) { 1636 if (pd->uobject) { 1637 __u32 max_wqes = 1638 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 1639 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count); 1640 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift || 1641 ucmd.rq_wqe_count != qp->rq.wqe_cnt) { 1642 mlx5_ib_dbg(dev, "invalid rq params\n"); 1643 return -EINVAL; 1644 } 1645 if (ucmd.sq_wqe_count > max_wqes) { 1646 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n", 1647 ucmd.sq_wqe_count, max_wqes); 1648 return -EINVAL; 1649 } 1650 if (init_attr->create_flags & 1651 mlx5_ib_create_qp_sqpn_qp1()) { 1652 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n"); 1653 return -EINVAL; 1654 } 1655 err = create_user_qp(dev, pd, qp, udata, init_attr, &in, 1656 &resp, &inlen, base); 1657 if (err) 1658 mlx5_ib_dbg(dev, "err %d\n", err); 1659 } else { 1660 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen, 1661 base); 1662 if (err) 1663 mlx5_ib_dbg(dev, "err %d\n", err); 1664 } 1665 1666 if (err) 1667 return err; 1668 } else { 1669 in = kvzalloc(inlen, GFP_KERNEL); 1670 if (!in) 1671 return -ENOMEM; 1672 1673 qp->create_type = MLX5_QP_EMPTY; 1674 } 1675 1676 if (is_sqp(init_attr->qp_type)) 1677 qp->port = init_attr->port_num; 1678 1679 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 1680 1681 MLX5_SET(qpc, qpc, st, to_mlx5_st(init_attr->qp_type)); 1682 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 1683 1684 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR) 1685 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn); 1686 else 1687 MLX5_SET(qpc, qpc, latency_sensitive, 1); 1688 1689 1690 if (qp->wq_sig) 1691 MLX5_SET(qpc, qpc, wq_signature, 1); 1692 1693 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 1694 MLX5_SET(qpc, qpc, block_lb_mc, 1); 1695 1696 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 1697 MLX5_SET(qpc, qpc, cd_master, 1); 1698 if (qp->flags & MLX5_IB_QP_MANAGED_SEND) 1699 MLX5_SET(qpc, qpc, cd_slave_send, 1); 1700 if (qp->flags & MLX5_IB_QP_MANAGED_RECV) 1701 MLX5_SET(qpc, qpc, cd_slave_receive, 1); 1702 1703 if (qp->scat_cqe && is_connected(init_attr->qp_type)) { 1704 int rcqe_sz; 1705 int scqe_sz; 1706 1707 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq); 1708 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq); 1709 1710 if (rcqe_sz == 128) 1711 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE); 1712 else 1713 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE); 1714 1715 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) { 1716 if (scqe_sz == 128) 1717 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE); 1718 else 1719 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE); 1720 } 1721 } 1722 1723 if (qp->rq.wqe_cnt) { 1724 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); 1725 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); 1726 } 1727 1728 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr)); 1729 1730 if (qp->sq.wqe_cnt) 1731 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); 1732 else 1733 MLX5_SET(qpc, qpc, no_sq, 1); 1734 1735 /* Set default resources */ 1736 switch (init_attr->qp_type) { 1737 case IB_QPT_XRC_TGT: 1738 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 1739 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn); 1740 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 1741 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn); 1742 break; 1743 case IB_QPT_XRC_INI: 1744 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 1745 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn); 1746 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 1747 break; 1748 default: 1749 if (init_attr->srq) { 1750 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn); 1751 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn); 1752 } else { 1753 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn); 1754 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn); 1755 } 1756 } 1757 1758 if (init_attr->send_cq) 1759 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn); 1760 1761 if (init_attr->recv_cq) 1762 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn); 1763 1764 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 1765 1766 /* 0xffffff means we ask to work with cqe version 0 */ 1767 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 1768 MLX5_SET(qpc, qpc, user_index, uidx); 1769 1770 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */ 1771 if (init_attr->qp_type == IB_QPT_UD && 1772 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) { 1773 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1); 1774 qp->flags |= MLX5_IB_QP_LSO; 1775 } 1776 1777 if (init_attr->qp_type == IB_QPT_RAW_PACKET || 1778 qp->flags & MLX5_IB_QP_UNDERLAY) { 1779 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr; 1780 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp); 1781 err = create_raw_packet_qp(dev, qp, in, pd); 1782 } else { 1783 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen); 1784 } 1785 1786 if (err) { 1787 mlx5_ib_dbg(dev, "create qp failed\n"); 1788 goto err_create; 1789 } 1790 1791 kvfree(in); 1792 1793 base->container_mibqp = qp; 1794 base->mqp.event = mlx5_ib_qp_event; 1795 1796 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq, 1797 &send_cq, &recv_cq); 1798 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 1799 mlx5_ib_lock_cqs(send_cq, recv_cq); 1800 /* Maintain device to QPs access, needed for further handling via reset 1801 * flow 1802 */ 1803 list_add_tail(&qp->qps_list, &dev->qp_list); 1804 /* Maintain CQ to QPs access, needed for further handling via reset flow 1805 */ 1806 if (send_cq) 1807 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); 1808 if (recv_cq) 1809 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); 1810 mlx5_ib_unlock_cqs(send_cq, recv_cq); 1811 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 1812 1813 return 0; 1814 1815 err_create: 1816 if (qp->create_type == MLX5_QP_USER) 1817 destroy_qp_user(dev, pd, qp, base); 1818 else if (qp->create_type == MLX5_QP_KERNEL) 1819 destroy_qp_kernel(dev, qp); 1820 1821 kvfree(in); 1822 return err; 1823 } 1824 1825 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 1826 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 1827 { 1828 if (send_cq) { 1829 if (recv_cq) { 1830 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1831 spin_lock(&send_cq->lock); 1832 spin_lock_nested(&recv_cq->lock, 1833 SINGLE_DEPTH_NESTING); 1834 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 1835 spin_lock(&send_cq->lock); 1836 __acquire(&recv_cq->lock); 1837 } else { 1838 spin_lock(&recv_cq->lock); 1839 spin_lock_nested(&send_cq->lock, 1840 SINGLE_DEPTH_NESTING); 1841 } 1842 } else { 1843 spin_lock(&send_cq->lock); 1844 __acquire(&recv_cq->lock); 1845 } 1846 } else if (recv_cq) { 1847 spin_lock(&recv_cq->lock); 1848 __acquire(&send_cq->lock); 1849 } else { 1850 __acquire(&send_cq->lock); 1851 __acquire(&recv_cq->lock); 1852 } 1853 } 1854 1855 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 1856 __releases(&send_cq->lock) __releases(&recv_cq->lock) 1857 { 1858 if (send_cq) { 1859 if (recv_cq) { 1860 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1861 spin_unlock(&recv_cq->lock); 1862 spin_unlock(&send_cq->lock); 1863 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 1864 __release(&recv_cq->lock); 1865 spin_unlock(&send_cq->lock); 1866 } else { 1867 spin_unlock(&send_cq->lock); 1868 spin_unlock(&recv_cq->lock); 1869 } 1870 } else { 1871 __release(&recv_cq->lock); 1872 spin_unlock(&send_cq->lock); 1873 } 1874 } else if (recv_cq) { 1875 __release(&send_cq->lock); 1876 spin_unlock(&recv_cq->lock); 1877 } else { 1878 __release(&recv_cq->lock); 1879 __release(&send_cq->lock); 1880 } 1881 } 1882 1883 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp) 1884 { 1885 return to_mpd(qp->ibqp.pd); 1886 } 1887 1888 static void get_cqs(enum ib_qp_type qp_type, 1889 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 1890 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq) 1891 { 1892 switch (qp_type) { 1893 case IB_QPT_XRC_TGT: 1894 *send_cq = NULL; 1895 *recv_cq = NULL; 1896 break; 1897 case MLX5_IB_QPT_REG_UMR: 1898 case IB_QPT_XRC_INI: 1899 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 1900 *recv_cq = NULL; 1901 break; 1902 1903 case IB_QPT_SMI: 1904 case MLX5_IB_QPT_HW_GSI: 1905 case IB_QPT_RC: 1906 case IB_QPT_UC: 1907 case IB_QPT_UD: 1908 case IB_QPT_RAW_IPV6: 1909 case IB_QPT_RAW_ETHERTYPE: 1910 case IB_QPT_RAW_PACKET: 1911 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 1912 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL; 1913 break; 1914 1915 case IB_QPT_MAX: 1916 default: 1917 *send_cq = NULL; 1918 *recv_cq = NULL; 1919 break; 1920 } 1921 } 1922 1923 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1924 const struct mlx5_modify_raw_qp_param *raw_qp_param, 1925 u8 lag_tx_affinity); 1926 1927 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1928 { 1929 struct mlx5_ib_cq *send_cq, *recv_cq; 1930 struct mlx5_ib_qp_base *base; 1931 unsigned long flags; 1932 int err; 1933 1934 if (qp->ibqp.rwq_ind_tbl) { 1935 destroy_rss_raw_qp_tir(dev, qp); 1936 return; 1937 } 1938 1939 base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 1940 qp->flags & MLX5_IB_QP_UNDERLAY) ? 1941 &qp->raw_packet_qp.rq.base : 1942 &qp->trans_qp.base; 1943 1944 if (qp->state != IB_QPS_RESET) { 1945 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET && 1946 !(qp->flags & MLX5_IB_QP_UNDERLAY)) { 1947 err = mlx5_core_qp_modify(dev->mdev, 1948 MLX5_CMD_OP_2RST_QP, 0, 1949 NULL, &base->mqp); 1950 } else { 1951 struct mlx5_modify_raw_qp_param raw_qp_param = { 1952 .operation = MLX5_CMD_OP_2RST_QP 1953 }; 1954 1955 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0); 1956 } 1957 if (err) 1958 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n", 1959 base->mqp.qpn); 1960 } 1961 1962 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 1963 &send_cq, &recv_cq); 1964 1965 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 1966 mlx5_ib_lock_cqs(send_cq, recv_cq); 1967 /* del from lists under both locks above to protect reset flow paths */ 1968 list_del(&qp->qps_list); 1969 if (send_cq) 1970 list_del(&qp->cq_send_list); 1971 1972 if (recv_cq) 1973 list_del(&qp->cq_recv_list); 1974 1975 if (qp->create_type == MLX5_QP_KERNEL) { 1976 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 1977 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL); 1978 if (send_cq != recv_cq) 1979 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn, 1980 NULL); 1981 } 1982 mlx5_ib_unlock_cqs(send_cq, recv_cq); 1983 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 1984 1985 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 1986 qp->flags & MLX5_IB_QP_UNDERLAY) { 1987 destroy_raw_packet_qp(dev, qp); 1988 } else { 1989 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp); 1990 if (err) 1991 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n", 1992 base->mqp.qpn); 1993 } 1994 1995 if (qp->create_type == MLX5_QP_KERNEL) 1996 destroy_qp_kernel(dev, qp); 1997 else if (qp->create_type == MLX5_QP_USER) 1998 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base); 1999 } 2000 2001 static const char *ib_qp_type_str(enum ib_qp_type type) 2002 { 2003 switch (type) { 2004 case IB_QPT_SMI: 2005 return "IB_QPT_SMI"; 2006 case IB_QPT_GSI: 2007 return "IB_QPT_GSI"; 2008 case IB_QPT_RC: 2009 return "IB_QPT_RC"; 2010 case IB_QPT_UC: 2011 return "IB_QPT_UC"; 2012 case IB_QPT_UD: 2013 return "IB_QPT_UD"; 2014 case IB_QPT_RAW_IPV6: 2015 return "IB_QPT_RAW_IPV6"; 2016 case IB_QPT_RAW_ETHERTYPE: 2017 return "IB_QPT_RAW_ETHERTYPE"; 2018 case IB_QPT_XRC_INI: 2019 return "IB_QPT_XRC_INI"; 2020 case IB_QPT_XRC_TGT: 2021 return "IB_QPT_XRC_TGT"; 2022 case IB_QPT_RAW_PACKET: 2023 return "IB_QPT_RAW_PACKET"; 2024 case MLX5_IB_QPT_REG_UMR: 2025 return "MLX5_IB_QPT_REG_UMR"; 2026 case IB_QPT_MAX: 2027 default: 2028 return "Invalid QP type"; 2029 } 2030 } 2031 2032 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, 2033 struct ib_qp_init_attr *init_attr, 2034 struct ib_udata *udata) 2035 { 2036 struct mlx5_ib_dev *dev; 2037 struct mlx5_ib_qp *qp; 2038 u16 xrcdn = 0; 2039 int err; 2040 2041 if (pd) { 2042 dev = to_mdev(pd->device); 2043 2044 if (init_attr->qp_type == IB_QPT_RAW_PACKET) { 2045 if (!pd->uobject) { 2046 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n"); 2047 return ERR_PTR(-EINVAL); 2048 } else if (!to_mucontext(pd->uobject->context)->cqe_version) { 2049 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n"); 2050 return ERR_PTR(-EINVAL); 2051 } 2052 } 2053 } else { 2054 /* being cautious here */ 2055 if (init_attr->qp_type != IB_QPT_XRC_TGT && 2056 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) { 2057 pr_warn("%s: no PD for transport %s\n", __func__, 2058 ib_qp_type_str(init_attr->qp_type)); 2059 return ERR_PTR(-EINVAL); 2060 } 2061 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device); 2062 } 2063 2064 switch (init_attr->qp_type) { 2065 case IB_QPT_XRC_TGT: 2066 case IB_QPT_XRC_INI: 2067 if (!MLX5_CAP_GEN(dev->mdev, xrc)) { 2068 mlx5_ib_dbg(dev, "XRC not supported\n"); 2069 return ERR_PTR(-ENOSYS); 2070 } 2071 init_attr->recv_cq = NULL; 2072 if (init_attr->qp_type == IB_QPT_XRC_TGT) { 2073 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn; 2074 init_attr->send_cq = NULL; 2075 } 2076 2077 /* fall through */ 2078 case IB_QPT_RAW_PACKET: 2079 case IB_QPT_RC: 2080 case IB_QPT_UC: 2081 case IB_QPT_UD: 2082 case IB_QPT_SMI: 2083 case MLX5_IB_QPT_HW_GSI: 2084 case MLX5_IB_QPT_REG_UMR: 2085 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 2086 if (!qp) 2087 return ERR_PTR(-ENOMEM); 2088 2089 err = create_qp_common(dev, pd, init_attr, udata, qp); 2090 if (err) { 2091 mlx5_ib_dbg(dev, "create_qp_common failed\n"); 2092 kfree(qp); 2093 return ERR_PTR(err); 2094 } 2095 2096 if (is_qp0(init_attr->qp_type)) 2097 qp->ibqp.qp_num = 0; 2098 else if (is_qp1(init_attr->qp_type)) 2099 qp->ibqp.qp_num = 1; 2100 else 2101 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn; 2102 2103 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n", 2104 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn, 2105 init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1, 2106 init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1); 2107 2108 qp->trans_qp.xrcdn = xrcdn; 2109 2110 break; 2111 2112 case IB_QPT_GSI: 2113 return mlx5_ib_gsi_create_qp(pd, init_attr); 2114 2115 case IB_QPT_RAW_IPV6: 2116 case IB_QPT_RAW_ETHERTYPE: 2117 case IB_QPT_MAX: 2118 default: 2119 mlx5_ib_dbg(dev, "unsupported qp type %d\n", 2120 init_attr->qp_type); 2121 /* Don't support raw QPs */ 2122 return ERR_PTR(-EINVAL); 2123 } 2124 2125 return &qp->ibqp; 2126 } 2127 2128 int mlx5_ib_destroy_qp(struct ib_qp *qp) 2129 { 2130 struct mlx5_ib_dev *dev = to_mdev(qp->device); 2131 struct mlx5_ib_qp *mqp = to_mqp(qp); 2132 2133 if (unlikely(qp->qp_type == IB_QPT_GSI)) 2134 return mlx5_ib_gsi_destroy_qp(qp); 2135 2136 destroy_qp_common(dev, mqp); 2137 2138 kfree(mqp); 2139 2140 return 0; 2141 } 2142 2143 static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr, 2144 int attr_mask) 2145 { 2146 u32 hw_access_flags = 0; 2147 u8 dest_rd_atomic; 2148 u32 access_flags; 2149 2150 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 2151 dest_rd_atomic = attr->max_dest_rd_atomic; 2152 else 2153 dest_rd_atomic = qp->trans_qp.resp_depth; 2154 2155 if (attr_mask & IB_QP_ACCESS_FLAGS) 2156 access_flags = attr->qp_access_flags; 2157 else 2158 access_flags = qp->trans_qp.atomic_rd_en; 2159 2160 if (!dest_rd_atomic) 2161 access_flags &= IB_ACCESS_REMOTE_WRITE; 2162 2163 if (access_flags & IB_ACCESS_REMOTE_READ) 2164 hw_access_flags |= MLX5_QP_BIT_RRE; 2165 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) 2166 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX); 2167 if (access_flags & IB_ACCESS_REMOTE_WRITE) 2168 hw_access_flags |= MLX5_QP_BIT_RWE; 2169 2170 return cpu_to_be32(hw_access_flags); 2171 } 2172 2173 enum { 2174 MLX5_PATH_FLAG_FL = 1 << 0, 2175 MLX5_PATH_FLAG_FREE_AR = 1 << 1, 2176 MLX5_PATH_FLAG_COUNTER = 1 << 2, 2177 }; 2178 2179 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate) 2180 { 2181 if (rate == IB_RATE_PORT_CURRENT) { 2182 return 0; 2183 } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) { 2184 return -EINVAL; 2185 } else { 2186 while (rate != IB_RATE_2_5_GBPS && 2187 !(1 << (rate + MLX5_STAT_RATE_OFFSET) & 2188 MLX5_CAP_GEN(dev->mdev, stat_rate_support))) 2189 --rate; 2190 } 2191 2192 return rate + MLX5_STAT_RATE_OFFSET; 2193 } 2194 2195 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev, 2196 struct mlx5_ib_sq *sq, u8 sl) 2197 { 2198 void *in; 2199 void *tisc; 2200 int inlen; 2201 int err; 2202 2203 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 2204 in = kvzalloc(inlen, GFP_KERNEL); 2205 if (!in) 2206 return -ENOMEM; 2207 2208 MLX5_SET(modify_tis_in, in, bitmask.prio, 1); 2209 2210 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 2211 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1)); 2212 2213 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen); 2214 2215 kvfree(in); 2216 2217 return err; 2218 } 2219 2220 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev, 2221 struct mlx5_ib_sq *sq, u8 tx_affinity) 2222 { 2223 void *in; 2224 void *tisc; 2225 int inlen; 2226 int err; 2227 2228 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 2229 in = kvzalloc(inlen, GFP_KERNEL); 2230 if (!in) 2231 return -ENOMEM; 2232 2233 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1); 2234 2235 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 2236 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity); 2237 2238 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen); 2239 2240 kvfree(in); 2241 2242 return err; 2243 } 2244 2245 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2246 const struct rdma_ah_attr *ah, 2247 struct mlx5_qp_path *path, u8 port, int attr_mask, 2248 u32 path_flags, const struct ib_qp_attr *attr, 2249 bool alt) 2250 { 2251 const struct ib_global_route *grh = rdma_ah_read_grh(ah); 2252 int err; 2253 enum ib_gid_type gid_type; 2254 u8 ah_flags = rdma_ah_get_ah_flags(ah); 2255 u8 sl = rdma_ah_get_sl(ah); 2256 2257 if (attr_mask & IB_QP_PKEY_INDEX) 2258 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index : 2259 attr->pkey_index); 2260 2261 if (ah_flags & IB_AH_GRH) { 2262 if (grh->sgid_index >= 2263 dev->mdev->port_caps[port - 1].gid_table_len) { 2264 pr_err("sgid_index (%u) too large. max is %d\n", 2265 grh->sgid_index, 2266 dev->mdev->port_caps[port - 1].gid_table_len); 2267 return -EINVAL; 2268 } 2269 } 2270 2271 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) { 2272 if (!(ah_flags & IB_AH_GRH)) 2273 return -EINVAL; 2274 err = mlx5_get_roce_gid_type(dev, port, grh->sgid_index, 2275 &gid_type); 2276 if (err) 2277 return err; 2278 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac)); 2279 path->udp_sport = mlx5_get_roce_udp_sport(dev, port, 2280 grh->sgid_index); 2281 path->dci_cfi_prio_sl = (sl & 0x7) << 4; 2282 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) 2283 path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f; 2284 } else { 2285 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0; 2286 path->fl_free_ar |= 2287 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0; 2288 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah)); 2289 path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f; 2290 if (ah_flags & IB_AH_GRH) 2291 path->grh_mlid |= 1 << 7; 2292 path->dci_cfi_prio_sl = sl & 0xf; 2293 } 2294 2295 if (ah_flags & IB_AH_GRH) { 2296 path->mgid_index = grh->sgid_index; 2297 path->hop_limit = grh->hop_limit; 2298 path->tclass_flowlabel = 2299 cpu_to_be32((grh->traffic_class << 20) | 2300 (grh->flow_label)); 2301 memcpy(path->rgid, grh->dgid.raw, 16); 2302 } 2303 2304 err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah)); 2305 if (err < 0) 2306 return err; 2307 path->static_rate = err; 2308 path->port = port; 2309 2310 if (attr_mask & IB_QP_TIMEOUT) 2311 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3; 2312 2313 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt) 2314 return modify_raw_packet_eth_prio(dev->mdev, 2315 &qp->raw_packet_qp.sq, 2316 sl & 0xf); 2317 2318 return 0; 2319 } 2320 2321 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = { 2322 [MLX5_QP_STATE_INIT] = { 2323 [MLX5_QP_STATE_INIT] = { 2324 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 2325 MLX5_QP_OPTPAR_RAE | 2326 MLX5_QP_OPTPAR_RWE | 2327 MLX5_QP_OPTPAR_PKEY_INDEX | 2328 MLX5_QP_OPTPAR_PRI_PORT, 2329 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 2330 MLX5_QP_OPTPAR_PKEY_INDEX | 2331 MLX5_QP_OPTPAR_PRI_PORT, 2332 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 2333 MLX5_QP_OPTPAR_Q_KEY | 2334 MLX5_QP_OPTPAR_PRI_PORT, 2335 }, 2336 [MLX5_QP_STATE_RTR] = { 2337 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2338 MLX5_QP_OPTPAR_RRE | 2339 MLX5_QP_OPTPAR_RAE | 2340 MLX5_QP_OPTPAR_RWE | 2341 MLX5_QP_OPTPAR_PKEY_INDEX, 2342 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2343 MLX5_QP_OPTPAR_RWE | 2344 MLX5_QP_OPTPAR_PKEY_INDEX, 2345 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 2346 MLX5_QP_OPTPAR_Q_KEY, 2347 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX | 2348 MLX5_QP_OPTPAR_Q_KEY, 2349 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2350 MLX5_QP_OPTPAR_RRE | 2351 MLX5_QP_OPTPAR_RAE | 2352 MLX5_QP_OPTPAR_RWE | 2353 MLX5_QP_OPTPAR_PKEY_INDEX, 2354 }, 2355 }, 2356 [MLX5_QP_STATE_RTR] = { 2357 [MLX5_QP_STATE_RTS] = { 2358 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2359 MLX5_QP_OPTPAR_RRE | 2360 MLX5_QP_OPTPAR_RAE | 2361 MLX5_QP_OPTPAR_RWE | 2362 MLX5_QP_OPTPAR_PM_STATE | 2363 MLX5_QP_OPTPAR_RNR_TIMEOUT, 2364 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2365 MLX5_QP_OPTPAR_RWE | 2366 MLX5_QP_OPTPAR_PM_STATE, 2367 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 2368 }, 2369 }, 2370 [MLX5_QP_STATE_RTS] = { 2371 [MLX5_QP_STATE_RTS] = { 2372 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 2373 MLX5_QP_OPTPAR_RAE | 2374 MLX5_QP_OPTPAR_RWE | 2375 MLX5_QP_OPTPAR_RNR_TIMEOUT | 2376 MLX5_QP_OPTPAR_PM_STATE | 2377 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 2378 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 2379 MLX5_QP_OPTPAR_PM_STATE | 2380 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 2381 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY | 2382 MLX5_QP_OPTPAR_SRQN | 2383 MLX5_QP_OPTPAR_CQN_RCV, 2384 }, 2385 }, 2386 [MLX5_QP_STATE_SQER] = { 2387 [MLX5_QP_STATE_RTS] = { 2388 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 2389 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY, 2390 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE, 2391 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 2392 MLX5_QP_OPTPAR_RWE | 2393 MLX5_QP_OPTPAR_RAE | 2394 MLX5_QP_OPTPAR_RRE, 2395 }, 2396 }, 2397 }; 2398 2399 static int ib_nr_to_mlx5_nr(int ib_mask) 2400 { 2401 switch (ib_mask) { 2402 case IB_QP_STATE: 2403 return 0; 2404 case IB_QP_CUR_STATE: 2405 return 0; 2406 case IB_QP_EN_SQD_ASYNC_NOTIFY: 2407 return 0; 2408 case IB_QP_ACCESS_FLAGS: 2409 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE | 2410 MLX5_QP_OPTPAR_RAE; 2411 case IB_QP_PKEY_INDEX: 2412 return MLX5_QP_OPTPAR_PKEY_INDEX; 2413 case IB_QP_PORT: 2414 return MLX5_QP_OPTPAR_PRI_PORT; 2415 case IB_QP_QKEY: 2416 return MLX5_QP_OPTPAR_Q_KEY; 2417 case IB_QP_AV: 2418 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH | 2419 MLX5_QP_OPTPAR_PRI_PORT; 2420 case IB_QP_PATH_MTU: 2421 return 0; 2422 case IB_QP_TIMEOUT: 2423 return MLX5_QP_OPTPAR_ACK_TIMEOUT; 2424 case IB_QP_RETRY_CNT: 2425 return MLX5_QP_OPTPAR_RETRY_COUNT; 2426 case IB_QP_RNR_RETRY: 2427 return MLX5_QP_OPTPAR_RNR_RETRY; 2428 case IB_QP_RQ_PSN: 2429 return 0; 2430 case IB_QP_MAX_QP_RD_ATOMIC: 2431 return MLX5_QP_OPTPAR_SRA_MAX; 2432 case IB_QP_ALT_PATH: 2433 return MLX5_QP_OPTPAR_ALT_ADDR_PATH; 2434 case IB_QP_MIN_RNR_TIMER: 2435 return MLX5_QP_OPTPAR_RNR_TIMEOUT; 2436 case IB_QP_SQ_PSN: 2437 return 0; 2438 case IB_QP_MAX_DEST_RD_ATOMIC: 2439 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE | 2440 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE; 2441 case IB_QP_PATH_MIG_STATE: 2442 return MLX5_QP_OPTPAR_PM_STATE; 2443 case IB_QP_CAP: 2444 return 0; 2445 case IB_QP_DEST_QPN: 2446 return 0; 2447 } 2448 return 0; 2449 } 2450 2451 static int ib_mask_to_mlx5_opt(int ib_mask) 2452 { 2453 int result = 0; 2454 int i; 2455 2456 for (i = 0; i < 8 * sizeof(int); i++) { 2457 if ((1 << i) & ib_mask) 2458 result |= ib_nr_to_mlx5_nr(1 << i); 2459 } 2460 2461 return result; 2462 } 2463 2464 static int modify_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 2465 struct mlx5_ib_rq *rq, int new_state, 2466 const struct mlx5_modify_raw_qp_param *raw_qp_param) 2467 { 2468 void *in; 2469 void *rqc; 2470 int inlen; 2471 int err; 2472 2473 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 2474 in = kvzalloc(inlen, GFP_KERNEL); 2475 if (!in) 2476 return -ENOMEM; 2477 2478 MLX5_SET(modify_rq_in, in, rq_state, rq->state); 2479 2480 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 2481 MLX5_SET(rqc, rqc, state, new_state); 2482 2483 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) { 2484 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 2485 MLX5_SET64(modify_rq_in, in, modify_bitmask, 2486 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 2487 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id); 2488 } else 2489 pr_info_once("%s: RAW PACKET QP counters are not supported on current FW\n", 2490 dev->ib_dev.name); 2491 } 2492 2493 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen); 2494 if (err) 2495 goto out; 2496 2497 rq->state = new_state; 2498 2499 out: 2500 kvfree(in); 2501 return err; 2502 } 2503 2504 static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev, 2505 struct mlx5_ib_sq *sq, 2506 int new_state, 2507 const struct mlx5_modify_raw_qp_param *raw_qp_param) 2508 { 2509 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp; 2510 u32 old_rate = ibqp->rate_limit; 2511 u32 new_rate = old_rate; 2512 u16 rl_index = 0; 2513 void *in; 2514 void *sqc; 2515 int inlen; 2516 int err; 2517 2518 inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 2519 in = kvzalloc(inlen, GFP_KERNEL); 2520 if (!in) 2521 return -ENOMEM; 2522 2523 MLX5_SET(modify_sq_in, in, sq_state, sq->state); 2524 2525 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 2526 MLX5_SET(sqc, sqc, state, new_state); 2527 2528 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) { 2529 if (new_state != MLX5_SQC_STATE_RDY) 2530 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n", 2531 __func__); 2532 else 2533 new_rate = raw_qp_param->rate_limit; 2534 } 2535 2536 if (old_rate != new_rate) { 2537 if (new_rate) { 2538 err = mlx5_rl_add_rate(dev, new_rate, &rl_index); 2539 if (err) { 2540 pr_err("Failed configuring rate %u: %d\n", 2541 new_rate, err); 2542 goto out; 2543 } 2544 } 2545 2546 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1); 2547 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index); 2548 } 2549 2550 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen); 2551 if (err) { 2552 /* Remove new rate from table if failed */ 2553 if (new_rate && 2554 old_rate != new_rate) 2555 mlx5_rl_remove_rate(dev, new_rate); 2556 goto out; 2557 } 2558 2559 /* Only remove the old rate after new rate was set */ 2560 if ((old_rate && 2561 (old_rate != new_rate)) || 2562 (new_state != MLX5_SQC_STATE_RDY)) 2563 mlx5_rl_remove_rate(dev, old_rate); 2564 2565 ibqp->rate_limit = new_rate; 2566 sq->state = new_state; 2567 2568 out: 2569 kvfree(in); 2570 return err; 2571 } 2572 2573 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2574 const struct mlx5_modify_raw_qp_param *raw_qp_param, 2575 u8 tx_affinity) 2576 { 2577 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 2578 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 2579 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 2580 int modify_rq = !!qp->rq.wqe_cnt; 2581 int modify_sq = !!qp->sq.wqe_cnt; 2582 int rq_state; 2583 int sq_state; 2584 int err; 2585 2586 switch (raw_qp_param->operation) { 2587 case MLX5_CMD_OP_RST2INIT_QP: 2588 rq_state = MLX5_RQC_STATE_RDY; 2589 sq_state = MLX5_SQC_STATE_RDY; 2590 break; 2591 case MLX5_CMD_OP_2ERR_QP: 2592 rq_state = MLX5_RQC_STATE_ERR; 2593 sq_state = MLX5_SQC_STATE_ERR; 2594 break; 2595 case MLX5_CMD_OP_2RST_QP: 2596 rq_state = MLX5_RQC_STATE_RST; 2597 sq_state = MLX5_SQC_STATE_RST; 2598 break; 2599 case MLX5_CMD_OP_RTR2RTS_QP: 2600 case MLX5_CMD_OP_RTS2RTS_QP: 2601 if (raw_qp_param->set_mask == 2602 MLX5_RAW_QP_RATE_LIMIT) { 2603 modify_rq = 0; 2604 sq_state = sq->state; 2605 } else { 2606 return raw_qp_param->set_mask ? -EINVAL : 0; 2607 } 2608 break; 2609 case MLX5_CMD_OP_INIT2INIT_QP: 2610 case MLX5_CMD_OP_INIT2RTR_QP: 2611 if (raw_qp_param->set_mask) 2612 return -EINVAL; 2613 else 2614 return 0; 2615 default: 2616 WARN_ON(1); 2617 return -EINVAL; 2618 } 2619 2620 if (modify_rq) { 2621 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param); 2622 if (err) 2623 return err; 2624 } 2625 2626 if (modify_sq) { 2627 if (tx_affinity) { 2628 err = modify_raw_packet_tx_affinity(dev->mdev, sq, 2629 tx_affinity); 2630 if (err) 2631 return err; 2632 } 2633 2634 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, raw_qp_param); 2635 } 2636 2637 return 0; 2638 } 2639 2640 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp, 2641 const struct ib_qp_attr *attr, int attr_mask, 2642 enum ib_qp_state cur_state, enum ib_qp_state new_state) 2643 { 2644 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = { 2645 [MLX5_QP_STATE_RST] = { 2646 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2647 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2648 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP, 2649 }, 2650 [MLX5_QP_STATE_INIT] = { 2651 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2652 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2653 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP, 2654 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP, 2655 }, 2656 [MLX5_QP_STATE_RTR] = { 2657 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2658 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2659 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP, 2660 }, 2661 [MLX5_QP_STATE_RTS] = { 2662 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2663 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2664 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP, 2665 }, 2666 [MLX5_QP_STATE_SQD] = { 2667 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2668 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2669 }, 2670 [MLX5_QP_STATE_SQER] = { 2671 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2672 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2673 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP, 2674 }, 2675 [MLX5_QP_STATE_ERR] = { 2676 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2677 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2678 } 2679 }; 2680 2681 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2682 struct mlx5_ib_qp *qp = to_mqp(ibqp); 2683 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 2684 struct mlx5_ib_cq *send_cq, *recv_cq; 2685 struct mlx5_qp_context *context; 2686 struct mlx5_ib_pd *pd; 2687 struct mlx5_ib_port *mibport = NULL; 2688 enum mlx5_qp_state mlx5_cur, mlx5_new; 2689 enum mlx5_qp_optpar optpar; 2690 int mlx5_st; 2691 int err; 2692 u16 op; 2693 u8 tx_affinity = 0; 2694 2695 context = kzalloc(sizeof(*context), GFP_KERNEL); 2696 if (!context) 2697 return -ENOMEM; 2698 2699 err = to_mlx5_st(ibqp->qp_type); 2700 if (err < 0) { 2701 mlx5_ib_dbg(dev, "unsupported qp type %d\n", ibqp->qp_type); 2702 goto out; 2703 } 2704 2705 context->flags = cpu_to_be32(err << 16); 2706 2707 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) { 2708 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 2709 } else { 2710 switch (attr->path_mig_state) { 2711 case IB_MIG_MIGRATED: 2712 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 2713 break; 2714 case IB_MIG_REARM: 2715 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11); 2716 break; 2717 case IB_MIG_ARMED: 2718 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11); 2719 break; 2720 } 2721 } 2722 2723 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) { 2724 if ((ibqp->qp_type == IB_QPT_RC) || 2725 (ibqp->qp_type == IB_QPT_UD && 2726 !(qp->flags & MLX5_IB_QP_SQPN_QP1)) || 2727 (ibqp->qp_type == IB_QPT_UC) || 2728 (ibqp->qp_type == IB_QPT_RAW_PACKET) || 2729 (ibqp->qp_type == IB_QPT_XRC_INI) || 2730 (ibqp->qp_type == IB_QPT_XRC_TGT)) { 2731 if (mlx5_lag_is_active(dev->mdev)) { 2732 tx_affinity = (unsigned int)atomic_add_return(1, 2733 &dev->roce.next_port) % 2734 MLX5_MAX_PORTS + 1; 2735 context->flags |= cpu_to_be32(tx_affinity << 24); 2736 } 2737 } 2738 } 2739 2740 if (is_sqp(ibqp->qp_type)) { 2741 context->mtu_msgmax = (IB_MTU_256 << 5) | 8; 2742 } else if ((ibqp->qp_type == IB_QPT_UD && 2743 !(qp->flags & MLX5_IB_QP_UNDERLAY)) || 2744 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) { 2745 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12; 2746 } else if (attr_mask & IB_QP_PATH_MTU) { 2747 if (attr->path_mtu < IB_MTU_256 || 2748 attr->path_mtu > IB_MTU_4096) { 2749 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu); 2750 err = -EINVAL; 2751 goto out; 2752 } 2753 context->mtu_msgmax = (attr->path_mtu << 5) | 2754 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg); 2755 } 2756 2757 if (attr_mask & IB_QP_DEST_QPN) 2758 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num); 2759 2760 if (attr_mask & IB_QP_PKEY_INDEX) 2761 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index); 2762 2763 /* todo implement counter_index functionality */ 2764 2765 if (is_sqp(ibqp->qp_type)) 2766 context->pri_path.port = qp->port; 2767 2768 if (attr_mask & IB_QP_PORT) 2769 context->pri_path.port = attr->port_num; 2770 2771 if (attr_mask & IB_QP_AV) { 2772 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path, 2773 attr_mask & IB_QP_PORT ? attr->port_num : qp->port, 2774 attr_mask, 0, attr, false); 2775 if (err) 2776 goto out; 2777 } 2778 2779 if (attr_mask & IB_QP_TIMEOUT) 2780 context->pri_path.ackto_lt |= attr->timeout << 3; 2781 2782 if (attr_mask & IB_QP_ALT_PATH) { 2783 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr, 2784 &context->alt_path, 2785 attr->alt_port_num, 2786 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT, 2787 0, attr, true); 2788 if (err) 2789 goto out; 2790 } 2791 2792 pd = get_pd(qp); 2793 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 2794 &send_cq, &recv_cq); 2795 2796 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn); 2797 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0; 2798 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0; 2799 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28); 2800 2801 if (attr_mask & IB_QP_RNR_RETRY) 2802 context->params1 |= cpu_to_be32(attr->rnr_retry << 13); 2803 2804 if (attr_mask & IB_QP_RETRY_CNT) 2805 context->params1 |= cpu_to_be32(attr->retry_cnt << 16); 2806 2807 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 2808 if (attr->max_rd_atomic) 2809 context->params1 |= 2810 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21); 2811 } 2812 2813 if (attr_mask & IB_QP_SQ_PSN) 2814 context->next_send_psn = cpu_to_be32(attr->sq_psn); 2815 2816 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 2817 if (attr->max_dest_rd_atomic) 2818 context->params2 |= 2819 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21); 2820 } 2821 2822 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) 2823 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask); 2824 2825 if (attr_mask & IB_QP_MIN_RNR_TIMER) 2826 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24); 2827 2828 if (attr_mask & IB_QP_RQ_PSN) 2829 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn); 2830 2831 if (attr_mask & IB_QP_QKEY) 2832 context->qkey = cpu_to_be32(attr->qkey); 2833 2834 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 2835 context->db_rec_addr = cpu_to_be64(qp->db.dma); 2836 2837 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 2838 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num : 2839 qp->port) - 1; 2840 2841 /* Underlay port should be used - index 0 function per port */ 2842 if (qp->flags & MLX5_IB_QP_UNDERLAY) 2843 port_num = 0; 2844 2845 mibport = &dev->port[port_num]; 2846 context->qp_counter_set_usr_page |= 2847 cpu_to_be32((u32)(mibport->cnts.set_id) << 24); 2848 } 2849 2850 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 2851 context->sq_crq_size |= cpu_to_be16(1 << 4); 2852 2853 if (qp->flags & MLX5_IB_QP_SQPN_QP1) 2854 context->deth_sqpn = cpu_to_be32(1); 2855 2856 mlx5_cur = to_mlx5_state(cur_state); 2857 mlx5_new = to_mlx5_state(new_state); 2858 mlx5_st = to_mlx5_st(ibqp->qp_type); 2859 if (mlx5_st < 0) 2860 goto out; 2861 2862 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE || 2863 !optab[mlx5_cur][mlx5_new]) 2864 goto out; 2865 2866 op = optab[mlx5_cur][mlx5_new]; 2867 optpar = ib_mask_to_mlx5_opt(attr_mask); 2868 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st]; 2869 2870 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 2871 qp->flags & MLX5_IB_QP_UNDERLAY) { 2872 struct mlx5_modify_raw_qp_param raw_qp_param = {}; 2873 2874 raw_qp_param.operation = op; 2875 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 2876 raw_qp_param.rq_q_ctr_id = mibport->cnts.set_id; 2877 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID; 2878 } 2879 2880 if (attr_mask & IB_QP_RATE_LIMIT) { 2881 raw_qp_param.rate_limit = attr->rate_limit; 2882 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT; 2883 } 2884 2885 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity); 2886 } else { 2887 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context, 2888 &base->mqp); 2889 } 2890 2891 if (err) 2892 goto out; 2893 2894 qp->state = new_state; 2895 2896 if (attr_mask & IB_QP_ACCESS_FLAGS) 2897 qp->trans_qp.atomic_rd_en = attr->qp_access_flags; 2898 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 2899 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic; 2900 if (attr_mask & IB_QP_PORT) 2901 qp->port = attr->port_num; 2902 if (attr_mask & IB_QP_ALT_PATH) 2903 qp->trans_qp.alt_port = attr->alt_port_num; 2904 2905 /* 2906 * If we moved a kernel QP to RESET, clean up all old CQ 2907 * entries and reinitialize the QP. 2908 */ 2909 if (new_state == IB_QPS_RESET && !ibqp->uobject) { 2910 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 2911 ibqp->srq ? to_msrq(ibqp->srq) : NULL); 2912 if (send_cq != recv_cq) 2913 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL); 2914 2915 qp->rq.head = 0; 2916 qp->rq.tail = 0; 2917 qp->sq.head = 0; 2918 qp->sq.tail = 0; 2919 qp->sq.cur_post = 0; 2920 qp->sq.last_poll = 0; 2921 qp->db.db[MLX5_RCV_DBR] = 0; 2922 qp->db.db[MLX5_SND_DBR] = 0; 2923 } 2924 2925 out: 2926 kfree(context); 2927 return err; 2928 } 2929 2930 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 2931 int attr_mask, struct ib_udata *udata) 2932 { 2933 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2934 struct mlx5_ib_qp *qp = to_mqp(ibqp); 2935 enum ib_qp_type qp_type; 2936 enum ib_qp_state cur_state, new_state; 2937 int err = -EINVAL; 2938 int port; 2939 enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED; 2940 2941 if (ibqp->rwq_ind_tbl) 2942 return -ENOSYS; 2943 2944 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 2945 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask); 2946 2947 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ? 2948 IB_QPT_GSI : ibqp->qp_type; 2949 2950 mutex_lock(&qp->mutex); 2951 2952 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; 2953 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 2954 2955 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) { 2956 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 2957 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port); 2958 } 2959 2960 if (qp->flags & MLX5_IB_QP_UNDERLAY) { 2961 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) { 2962 mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n", 2963 attr_mask); 2964 goto out; 2965 } 2966 } else if (qp_type != MLX5_IB_QPT_REG_UMR && 2967 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) { 2968 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 2969 cur_state, new_state, ibqp->qp_type, attr_mask); 2970 goto out; 2971 } 2972 2973 if ((attr_mask & IB_QP_PORT) && 2974 (attr->port_num == 0 || 2975 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports))) { 2976 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 2977 attr->port_num, dev->num_ports); 2978 goto out; 2979 } 2980 2981 if (attr_mask & IB_QP_PKEY_INDEX) { 2982 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 2983 if (attr->pkey_index >= 2984 dev->mdev->port_caps[port - 1].pkey_table_len) { 2985 mlx5_ib_dbg(dev, "invalid pkey index %d\n", 2986 attr->pkey_index); 2987 goto out; 2988 } 2989 } 2990 2991 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 2992 attr->max_rd_atomic > 2993 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) { 2994 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n", 2995 attr->max_rd_atomic); 2996 goto out; 2997 } 2998 2999 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 3000 attr->max_dest_rd_atomic > 3001 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) { 3002 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n", 3003 attr->max_dest_rd_atomic); 3004 goto out; 3005 } 3006 3007 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 3008 err = 0; 3009 goto out; 3010 } 3011 3012 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state); 3013 3014 out: 3015 mutex_unlock(&qp->mutex); 3016 return err; 3017 } 3018 3019 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq) 3020 { 3021 struct mlx5_ib_cq *cq; 3022 unsigned cur; 3023 3024 cur = wq->head - wq->tail; 3025 if (likely(cur + nreq < wq->max_post)) 3026 return 0; 3027 3028 cq = to_mcq(ib_cq); 3029 spin_lock(&cq->lock); 3030 cur = wq->head - wq->tail; 3031 spin_unlock(&cq->lock); 3032 3033 return cur + nreq >= wq->max_post; 3034 } 3035 3036 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg, 3037 u64 remote_addr, u32 rkey) 3038 { 3039 rseg->raddr = cpu_to_be64(remote_addr); 3040 rseg->rkey = cpu_to_be32(rkey); 3041 rseg->reserved = 0; 3042 } 3043 3044 static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg, 3045 struct ib_send_wr *wr, void *qend, 3046 struct mlx5_ib_qp *qp, int *size) 3047 { 3048 void *seg = eseg; 3049 3050 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg)); 3051 3052 if (wr->send_flags & IB_SEND_IP_CSUM) 3053 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM | 3054 MLX5_ETH_WQE_L4_CSUM; 3055 3056 seg += sizeof(struct mlx5_wqe_eth_seg); 3057 *size += sizeof(struct mlx5_wqe_eth_seg) / 16; 3058 3059 if (wr->opcode == IB_WR_LSO) { 3060 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr); 3061 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr.start); 3062 u64 left, leftlen, copysz; 3063 void *pdata = ud_wr->header; 3064 3065 left = ud_wr->hlen; 3066 eseg->mss = cpu_to_be16(ud_wr->mss); 3067 eseg->inline_hdr.sz = cpu_to_be16(left); 3068 3069 /* 3070 * check if there is space till the end of queue, if yes, 3071 * copy all in one shot, otherwise copy till the end of queue, 3072 * rollback and than the copy the left 3073 */ 3074 leftlen = qend - (void *)eseg->inline_hdr.start; 3075 copysz = min_t(u64, leftlen, left); 3076 3077 memcpy(seg - size_of_inl_hdr_start, pdata, copysz); 3078 3079 if (likely(copysz > size_of_inl_hdr_start)) { 3080 seg += ALIGN(copysz - size_of_inl_hdr_start, 16); 3081 *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16; 3082 } 3083 3084 if (unlikely(copysz < left)) { /* the last wqe in the queue */ 3085 seg = mlx5_get_send_wqe(qp, 0); 3086 left -= copysz; 3087 pdata += copysz; 3088 memcpy(seg, pdata, left); 3089 seg += ALIGN(left, 16); 3090 *size += ALIGN(left, 16) / 16; 3091 } 3092 } 3093 3094 return seg; 3095 } 3096 3097 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg, 3098 struct ib_send_wr *wr) 3099 { 3100 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av)); 3101 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV); 3102 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey); 3103 } 3104 3105 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg) 3106 { 3107 dseg->byte_count = cpu_to_be32(sg->length); 3108 dseg->lkey = cpu_to_be32(sg->lkey); 3109 dseg->addr = cpu_to_be64(sg->addr); 3110 } 3111 3112 static u64 get_xlt_octo(u64 bytes) 3113 { 3114 return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) / 3115 MLX5_IB_UMR_OCTOWORD; 3116 } 3117 3118 static __be64 frwr_mkey_mask(void) 3119 { 3120 u64 result; 3121 3122 result = MLX5_MKEY_MASK_LEN | 3123 MLX5_MKEY_MASK_PAGE_SIZE | 3124 MLX5_MKEY_MASK_START_ADDR | 3125 MLX5_MKEY_MASK_EN_RINVAL | 3126 MLX5_MKEY_MASK_KEY | 3127 MLX5_MKEY_MASK_LR | 3128 MLX5_MKEY_MASK_LW | 3129 MLX5_MKEY_MASK_RR | 3130 MLX5_MKEY_MASK_RW | 3131 MLX5_MKEY_MASK_A | 3132 MLX5_MKEY_MASK_SMALL_FENCE | 3133 MLX5_MKEY_MASK_FREE; 3134 3135 return cpu_to_be64(result); 3136 } 3137 3138 static __be64 sig_mkey_mask(void) 3139 { 3140 u64 result; 3141 3142 result = MLX5_MKEY_MASK_LEN | 3143 MLX5_MKEY_MASK_PAGE_SIZE | 3144 MLX5_MKEY_MASK_START_ADDR | 3145 MLX5_MKEY_MASK_EN_SIGERR | 3146 MLX5_MKEY_MASK_EN_RINVAL | 3147 MLX5_MKEY_MASK_KEY | 3148 MLX5_MKEY_MASK_LR | 3149 MLX5_MKEY_MASK_LW | 3150 MLX5_MKEY_MASK_RR | 3151 MLX5_MKEY_MASK_RW | 3152 MLX5_MKEY_MASK_SMALL_FENCE | 3153 MLX5_MKEY_MASK_FREE | 3154 MLX5_MKEY_MASK_BSF_EN; 3155 3156 return cpu_to_be64(result); 3157 } 3158 3159 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr, 3160 struct mlx5_ib_mr *mr) 3161 { 3162 int size = mr->ndescs * mr->desc_size; 3163 3164 memset(umr, 0, sizeof(*umr)); 3165 3166 umr->flags = MLX5_UMR_CHECK_NOT_FREE; 3167 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size)); 3168 umr->mkey_mask = frwr_mkey_mask(); 3169 } 3170 3171 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr) 3172 { 3173 memset(umr, 0, sizeof(*umr)); 3174 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE); 3175 umr->flags = MLX5_UMR_INLINE; 3176 } 3177 3178 static __be64 get_umr_enable_mr_mask(void) 3179 { 3180 u64 result; 3181 3182 result = MLX5_MKEY_MASK_KEY | 3183 MLX5_MKEY_MASK_FREE; 3184 3185 return cpu_to_be64(result); 3186 } 3187 3188 static __be64 get_umr_disable_mr_mask(void) 3189 { 3190 u64 result; 3191 3192 result = MLX5_MKEY_MASK_FREE; 3193 3194 return cpu_to_be64(result); 3195 } 3196 3197 static __be64 get_umr_update_translation_mask(void) 3198 { 3199 u64 result; 3200 3201 result = MLX5_MKEY_MASK_LEN | 3202 MLX5_MKEY_MASK_PAGE_SIZE | 3203 MLX5_MKEY_MASK_START_ADDR; 3204 3205 return cpu_to_be64(result); 3206 } 3207 3208 static __be64 get_umr_update_access_mask(int atomic) 3209 { 3210 u64 result; 3211 3212 result = MLX5_MKEY_MASK_LR | 3213 MLX5_MKEY_MASK_LW | 3214 MLX5_MKEY_MASK_RR | 3215 MLX5_MKEY_MASK_RW; 3216 3217 if (atomic) 3218 result |= MLX5_MKEY_MASK_A; 3219 3220 return cpu_to_be64(result); 3221 } 3222 3223 static __be64 get_umr_update_pd_mask(void) 3224 { 3225 u64 result; 3226 3227 result = MLX5_MKEY_MASK_PD; 3228 3229 return cpu_to_be64(result); 3230 } 3231 3232 static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, 3233 struct ib_send_wr *wr, int atomic) 3234 { 3235 struct mlx5_umr_wr *umrwr = umr_wr(wr); 3236 3237 memset(umr, 0, sizeof(*umr)); 3238 3239 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE) 3240 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */ 3241 else 3242 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */ 3243 3244 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size)); 3245 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) { 3246 u64 offset = get_xlt_octo(umrwr->offset); 3247 3248 umr->xlt_offset = cpu_to_be16(offset & 0xffff); 3249 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16); 3250 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN; 3251 } 3252 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION) 3253 umr->mkey_mask |= get_umr_update_translation_mask(); 3254 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) { 3255 umr->mkey_mask |= get_umr_update_access_mask(atomic); 3256 umr->mkey_mask |= get_umr_update_pd_mask(); 3257 } 3258 if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR) 3259 umr->mkey_mask |= get_umr_enable_mr_mask(); 3260 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR) 3261 umr->mkey_mask |= get_umr_disable_mr_mask(); 3262 3263 if (!wr->num_sge) 3264 umr->flags |= MLX5_UMR_INLINE; 3265 } 3266 3267 static u8 get_umr_flags(int acc) 3268 { 3269 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | 3270 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | 3271 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | 3272 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | 3273 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN; 3274 } 3275 3276 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg, 3277 struct mlx5_ib_mr *mr, 3278 u32 key, int access) 3279 { 3280 int ndescs = ALIGN(mr->ndescs, 8) >> 1; 3281 3282 memset(seg, 0, sizeof(*seg)); 3283 3284 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT) 3285 seg->log2_page_size = ilog2(mr->ibmr.page_size); 3286 else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS) 3287 /* KLMs take twice the size of MTTs */ 3288 ndescs *= 2; 3289 3290 seg->flags = get_umr_flags(access) | mr->access_mode; 3291 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00); 3292 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL); 3293 seg->start_addr = cpu_to_be64(mr->ibmr.iova); 3294 seg->len = cpu_to_be64(mr->ibmr.length); 3295 seg->xlt_oct_size = cpu_to_be32(ndescs); 3296 } 3297 3298 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg) 3299 { 3300 memset(seg, 0, sizeof(*seg)); 3301 seg->status = MLX5_MKEY_STATUS_FREE; 3302 } 3303 3304 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr) 3305 { 3306 struct mlx5_umr_wr *umrwr = umr_wr(wr); 3307 3308 memset(seg, 0, sizeof(*seg)); 3309 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR) 3310 seg->status = MLX5_MKEY_STATUS_FREE; 3311 3312 seg->flags = convert_access(umrwr->access_flags); 3313 if (umrwr->pd) 3314 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn); 3315 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION && 3316 !umrwr->length) 3317 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64); 3318 3319 seg->start_addr = cpu_to_be64(umrwr->virt_addr); 3320 seg->len = cpu_to_be64(umrwr->length); 3321 seg->log2_page_size = umrwr->page_shift; 3322 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 | 3323 mlx5_mkey_variant(umrwr->mkey)); 3324 } 3325 3326 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg, 3327 struct mlx5_ib_mr *mr, 3328 struct mlx5_ib_pd *pd) 3329 { 3330 int bcount = mr->desc_size * mr->ndescs; 3331 3332 dseg->addr = cpu_to_be64(mr->desc_map); 3333 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64)); 3334 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey); 3335 } 3336 3337 static __be32 send_ieth(struct ib_send_wr *wr) 3338 { 3339 switch (wr->opcode) { 3340 case IB_WR_SEND_WITH_IMM: 3341 case IB_WR_RDMA_WRITE_WITH_IMM: 3342 return wr->ex.imm_data; 3343 3344 case IB_WR_SEND_WITH_INV: 3345 return cpu_to_be32(wr->ex.invalidate_rkey); 3346 3347 default: 3348 return 0; 3349 } 3350 } 3351 3352 static u8 calc_sig(void *wqe, int size) 3353 { 3354 u8 *p = wqe; 3355 u8 res = 0; 3356 int i; 3357 3358 for (i = 0; i < size; i++) 3359 res ^= p[i]; 3360 3361 return ~res; 3362 } 3363 3364 static u8 wq_sig(void *wqe) 3365 { 3366 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4); 3367 } 3368 3369 static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr, 3370 void *wqe, int *sz) 3371 { 3372 struct mlx5_wqe_inline_seg *seg; 3373 void *qend = qp->sq.qend; 3374 void *addr; 3375 int inl = 0; 3376 int copy; 3377 int len; 3378 int i; 3379 3380 seg = wqe; 3381 wqe += sizeof(*seg); 3382 for (i = 0; i < wr->num_sge; i++) { 3383 addr = (void *)(unsigned long)(wr->sg_list[i].addr); 3384 len = wr->sg_list[i].length; 3385 inl += len; 3386 3387 if (unlikely(inl > qp->max_inline_data)) 3388 return -ENOMEM; 3389 3390 if (unlikely(wqe + len > qend)) { 3391 copy = qend - wqe; 3392 memcpy(wqe, addr, copy); 3393 addr += copy; 3394 len -= copy; 3395 wqe = mlx5_get_send_wqe(qp, 0); 3396 } 3397 memcpy(wqe, addr, len); 3398 wqe += len; 3399 } 3400 3401 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG); 3402 3403 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16; 3404 3405 return 0; 3406 } 3407 3408 static u16 prot_field_size(enum ib_signature_type type) 3409 { 3410 switch (type) { 3411 case IB_SIG_TYPE_T10_DIF: 3412 return MLX5_DIF_SIZE; 3413 default: 3414 return 0; 3415 } 3416 } 3417 3418 static u8 bs_selector(int block_size) 3419 { 3420 switch (block_size) { 3421 case 512: return 0x1; 3422 case 520: return 0x2; 3423 case 4096: return 0x3; 3424 case 4160: return 0x4; 3425 case 1073741824: return 0x5; 3426 default: return 0; 3427 } 3428 } 3429 3430 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain, 3431 struct mlx5_bsf_inl *inl) 3432 { 3433 /* Valid inline section and allow BSF refresh */ 3434 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID | 3435 MLX5_BSF_REFRESH_DIF); 3436 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag); 3437 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag); 3438 /* repeating block */ 3439 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK; 3440 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ? 3441 MLX5_DIF_CRC : MLX5_DIF_IPCS; 3442 3443 if (domain->sig.dif.ref_remap) 3444 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG; 3445 3446 if (domain->sig.dif.app_escape) { 3447 if (domain->sig.dif.ref_escape) 3448 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE; 3449 else 3450 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE; 3451 } 3452 3453 inl->dif_app_bitmask_check = 3454 cpu_to_be16(domain->sig.dif.apptag_check_mask); 3455 } 3456 3457 static int mlx5_set_bsf(struct ib_mr *sig_mr, 3458 struct ib_sig_attrs *sig_attrs, 3459 struct mlx5_bsf *bsf, u32 data_size) 3460 { 3461 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig; 3462 struct mlx5_bsf_basic *basic = &bsf->basic; 3463 struct ib_sig_domain *mem = &sig_attrs->mem; 3464 struct ib_sig_domain *wire = &sig_attrs->wire; 3465 3466 memset(bsf, 0, sizeof(*bsf)); 3467 3468 /* Basic + Extended + Inline */ 3469 basic->bsf_size_sbs = 1 << 7; 3470 /* Input domain check byte mask */ 3471 basic->check_byte_mask = sig_attrs->check_mask; 3472 basic->raw_data_size = cpu_to_be32(data_size); 3473 3474 /* Memory domain */ 3475 switch (sig_attrs->mem.sig_type) { 3476 case IB_SIG_TYPE_NONE: 3477 break; 3478 case IB_SIG_TYPE_T10_DIF: 3479 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval); 3480 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx); 3481 mlx5_fill_inl_bsf(mem, &bsf->m_inl); 3482 break; 3483 default: 3484 return -EINVAL; 3485 } 3486 3487 /* Wire domain */ 3488 switch (sig_attrs->wire.sig_type) { 3489 case IB_SIG_TYPE_NONE: 3490 break; 3491 case IB_SIG_TYPE_T10_DIF: 3492 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval && 3493 mem->sig_type == wire->sig_type) { 3494 /* Same block structure */ 3495 basic->bsf_size_sbs |= 1 << 4; 3496 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type) 3497 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK; 3498 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag) 3499 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK; 3500 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag) 3501 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK; 3502 } else 3503 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval); 3504 3505 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx); 3506 mlx5_fill_inl_bsf(wire, &bsf->w_inl); 3507 break; 3508 default: 3509 return -EINVAL; 3510 } 3511 3512 return 0; 3513 } 3514 3515 static int set_sig_data_segment(struct ib_sig_handover_wr *wr, 3516 struct mlx5_ib_qp *qp, void **seg, int *size) 3517 { 3518 struct ib_sig_attrs *sig_attrs = wr->sig_attrs; 3519 struct ib_mr *sig_mr = wr->sig_mr; 3520 struct mlx5_bsf *bsf; 3521 u32 data_len = wr->wr.sg_list->length; 3522 u32 data_key = wr->wr.sg_list->lkey; 3523 u64 data_va = wr->wr.sg_list->addr; 3524 int ret; 3525 int wqe_size; 3526 3527 if (!wr->prot || 3528 (data_key == wr->prot->lkey && 3529 data_va == wr->prot->addr && 3530 data_len == wr->prot->length)) { 3531 /** 3532 * Source domain doesn't contain signature information 3533 * or data and protection are interleaved in memory. 3534 * So need construct: 3535 * ------------------ 3536 * | data_klm | 3537 * ------------------ 3538 * | BSF | 3539 * ------------------ 3540 **/ 3541 struct mlx5_klm *data_klm = *seg; 3542 3543 data_klm->bcount = cpu_to_be32(data_len); 3544 data_klm->key = cpu_to_be32(data_key); 3545 data_klm->va = cpu_to_be64(data_va); 3546 wqe_size = ALIGN(sizeof(*data_klm), 64); 3547 } else { 3548 /** 3549 * Source domain contains signature information 3550 * So need construct a strided block format: 3551 * --------------------------- 3552 * | stride_block_ctrl | 3553 * --------------------------- 3554 * | data_klm | 3555 * --------------------------- 3556 * | prot_klm | 3557 * --------------------------- 3558 * | BSF | 3559 * --------------------------- 3560 **/ 3561 struct mlx5_stride_block_ctrl_seg *sblock_ctrl; 3562 struct mlx5_stride_block_entry *data_sentry; 3563 struct mlx5_stride_block_entry *prot_sentry; 3564 u32 prot_key = wr->prot->lkey; 3565 u64 prot_va = wr->prot->addr; 3566 u16 block_size = sig_attrs->mem.sig.dif.pi_interval; 3567 int prot_size; 3568 3569 sblock_ctrl = *seg; 3570 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl); 3571 prot_sentry = (void *)data_sentry + sizeof(*data_sentry); 3572 3573 prot_size = prot_field_size(sig_attrs->mem.sig_type); 3574 if (!prot_size) { 3575 pr_err("Bad block size given: %u\n", block_size); 3576 return -EINVAL; 3577 } 3578 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size + 3579 prot_size); 3580 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP); 3581 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size); 3582 sblock_ctrl->num_entries = cpu_to_be16(2); 3583 3584 data_sentry->bcount = cpu_to_be16(block_size); 3585 data_sentry->key = cpu_to_be32(data_key); 3586 data_sentry->va = cpu_to_be64(data_va); 3587 data_sentry->stride = cpu_to_be16(block_size); 3588 3589 prot_sentry->bcount = cpu_to_be16(prot_size); 3590 prot_sentry->key = cpu_to_be32(prot_key); 3591 prot_sentry->va = cpu_to_be64(prot_va); 3592 prot_sentry->stride = cpu_to_be16(prot_size); 3593 3594 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) + 3595 sizeof(*prot_sentry), 64); 3596 } 3597 3598 *seg += wqe_size; 3599 *size += wqe_size / 16; 3600 if (unlikely((*seg == qp->sq.qend))) 3601 *seg = mlx5_get_send_wqe(qp, 0); 3602 3603 bsf = *seg; 3604 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len); 3605 if (ret) 3606 return -EINVAL; 3607 3608 *seg += sizeof(*bsf); 3609 *size += sizeof(*bsf) / 16; 3610 if (unlikely((*seg == qp->sq.qend))) 3611 *seg = mlx5_get_send_wqe(qp, 0); 3612 3613 return 0; 3614 } 3615 3616 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg, 3617 struct ib_sig_handover_wr *wr, u32 size, 3618 u32 length, u32 pdn) 3619 { 3620 struct ib_mr *sig_mr = wr->sig_mr; 3621 u32 sig_key = sig_mr->rkey; 3622 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1; 3623 3624 memset(seg, 0, sizeof(*seg)); 3625 3626 seg->flags = get_umr_flags(wr->access_flags) | 3627 MLX5_MKC_ACCESS_MODE_KLMS; 3628 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00); 3629 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 | 3630 MLX5_MKEY_BSF_EN | pdn); 3631 seg->len = cpu_to_be64(length); 3632 seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size)); 3633 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE); 3634 } 3635 3636 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, 3637 u32 size) 3638 { 3639 memset(umr, 0, sizeof(*umr)); 3640 3641 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE; 3642 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size)); 3643 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE); 3644 umr->mkey_mask = sig_mkey_mask(); 3645 } 3646 3647 3648 static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp, 3649 void **seg, int *size) 3650 { 3651 struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr); 3652 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr); 3653 u32 pdn = get_pd(qp)->pdn; 3654 u32 xlt_size; 3655 int region_len, ret; 3656 3657 if (unlikely(wr->wr.num_sge != 1) || 3658 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) || 3659 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) || 3660 unlikely(!sig_mr->sig->sig_status_checked)) 3661 return -EINVAL; 3662 3663 /* length of the protected region, data + protection */ 3664 region_len = wr->wr.sg_list->length; 3665 if (wr->prot && 3666 (wr->prot->lkey != wr->wr.sg_list->lkey || 3667 wr->prot->addr != wr->wr.sg_list->addr || 3668 wr->prot->length != wr->wr.sg_list->length)) 3669 region_len += wr->prot->length; 3670 3671 /** 3672 * KLM octoword size - if protection was provided 3673 * then we use strided block format (3 octowords), 3674 * else we use single KLM (1 octoword) 3675 **/ 3676 xlt_size = wr->prot ? 0x30 : sizeof(struct mlx5_klm); 3677 3678 set_sig_umr_segment(*seg, xlt_size); 3679 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 3680 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 3681 if (unlikely((*seg == qp->sq.qend))) 3682 *seg = mlx5_get_send_wqe(qp, 0); 3683 3684 set_sig_mkey_segment(*seg, wr, xlt_size, region_len, pdn); 3685 *seg += sizeof(struct mlx5_mkey_seg); 3686 *size += sizeof(struct mlx5_mkey_seg) / 16; 3687 if (unlikely((*seg == qp->sq.qend))) 3688 *seg = mlx5_get_send_wqe(qp, 0); 3689 3690 ret = set_sig_data_segment(wr, qp, seg, size); 3691 if (ret) 3692 return ret; 3693 3694 sig_mr->sig->sig_status_checked = false; 3695 return 0; 3696 } 3697 3698 static int set_psv_wr(struct ib_sig_domain *domain, 3699 u32 psv_idx, void **seg, int *size) 3700 { 3701 struct mlx5_seg_set_psv *psv_seg = *seg; 3702 3703 memset(psv_seg, 0, sizeof(*psv_seg)); 3704 psv_seg->psv_num = cpu_to_be32(psv_idx); 3705 switch (domain->sig_type) { 3706 case IB_SIG_TYPE_NONE: 3707 break; 3708 case IB_SIG_TYPE_T10_DIF: 3709 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 | 3710 domain->sig.dif.app_tag); 3711 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag); 3712 break; 3713 default: 3714 pr_err("Bad signature type (%d) is given.\n", 3715 domain->sig_type); 3716 return -EINVAL; 3717 } 3718 3719 *seg += sizeof(*psv_seg); 3720 *size += sizeof(*psv_seg) / 16; 3721 3722 return 0; 3723 } 3724 3725 static int set_reg_wr(struct mlx5_ib_qp *qp, 3726 struct ib_reg_wr *wr, 3727 void **seg, int *size) 3728 { 3729 struct mlx5_ib_mr *mr = to_mmr(wr->mr); 3730 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd); 3731 3732 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) { 3733 mlx5_ib_warn(to_mdev(qp->ibqp.device), 3734 "Invalid IB_SEND_INLINE send flag\n"); 3735 return -EINVAL; 3736 } 3737 3738 set_reg_umr_seg(*seg, mr); 3739 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 3740 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 3741 if (unlikely((*seg == qp->sq.qend))) 3742 *seg = mlx5_get_send_wqe(qp, 0); 3743 3744 set_reg_mkey_seg(*seg, mr, wr->key, wr->access); 3745 *seg += sizeof(struct mlx5_mkey_seg); 3746 *size += sizeof(struct mlx5_mkey_seg) / 16; 3747 if (unlikely((*seg == qp->sq.qend))) 3748 *seg = mlx5_get_send_wqe(qp, 0); 3749 3750 set_reg_data_seg(*seg, mr, pd); 3751 *seg += sizeof(struct mlx5_wqe_data_seg); 3752 *size += (sizeof(struct mlx5_wqe_data_seg) / 16); 3753 3754 return 0; 3755 } 3756 3757 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size) 3758 { 3759 set_linv_umr_seg(*seg); 3760 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 3761 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 3762 if (unlikely((*seg == qp->sq.qend))) 3763 *seg = mlx5_get_send_wqe(qp, 0); 3764 set_linv_mkey_seg(*seg); 3765 *seg += sizeof(struct mlx5_mkey_seg); 3766 *size += sizeof(struct mlx5_mkey_seg) / 16; 3767 if (unlikely((*seg == qp->sq.qend))) 3768 *seg = mlx5_get_send_wqe(qp, 0); 3769 } 3770 3771 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16) 3772 { 3773 __be32 *p = NULL; 3774 int tidx = idx; 3775 int i, j; 3776 3777 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx)); 3778 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) { 3779 if ((i & 0xf) == 0) { 3780 void *buf = mlx5_get_send_wqe(qp, tidx); 3781 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1); 3782 p = buf; 3783 j = 0; 3784 } 3785 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]), 3786 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]), 3787 be32_to_cpu(p[j + 3])); 3788 } 3789 } 3790 3791 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg, 3792 struct mlx5_wqe_ctrl_seg **ctrl, 3793 struct ib_send_wr *wr, unsigned *idx, 3794 int *size, int nreq) 3795 { 3796 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq))) 3797 return -ENOMEM; 3798 3799 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1); 3800 *seg = mlx5_get_send_wqe(qp, *idx); 3801 *ctrl = *seg; 3802 *(uint32_t *)(*seg + 8) = 0; 3803 (*ctrl)->imm = send_ieth(wr); 3804 (*ctrl)->fm_ce_se = qp->sq_signal_bits | 3805 (wr->send_flags & IB_SEND_SIGNALED ? 3806 MLX5_WQE_CTRL_CQ_UPDATE : 0) | 3807 (wr->send_flags & IB_SEND_SOLICITED ? 3808 MLX5_WQE_CTRL_SOLICITED : 0); 3809 3810 *seg += sizeof(**ctrl); 3811 *size = sizeof(**ctrl) / 16; 3812 3813 return 0; 3814 } 3815 3816 static void finish_wqe(struct mlx5_ib_qp *qp, 3817 struct mlx5_wqe_ctrl_seg *ctrl, 3818 u8 size, unsigned idx, u64 wr_id, 3819 int nreq, u8 fence, u32 mlx5_opcode) 3820 { 3821 u8 opmod = 0; 3822 3823 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) | 3824 mlx5_opcode | ((u32)opmod << 24)); 3825 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8)); 3826 ctrl->fm_ce_se |= fence; 3827 if (unlikely(qp->wq_sig)) 3828 ctrl->signature = wq_sig(ctrl); 3829 3830 qp->sq.wrid[idx] = wr_id; 3831 qp->sq.w_list[idx].opcode = mlx5_opcode; 3832 qp->sq.wqe_head[idx] = qp->sq.head + nreq; 3833 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB); 3834 qp->sq.w_list[idx].next = qp->sq.cur_post; 3835 } 3836 3837 3838 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 3839 struct ib_send_wr **bad_wr) 3840 { 3841 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */ 3842 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3843 struct mlx5_core_dev *mdev = dev->mdev; 3844 struct mlx5_ib_qp *qp; 3845 struct mlx5_ib_mr *mr; 3846 struct mlx5_wqe_data_seg *dpseg; 3847 struct mlx5_wqe_xrc_seg *xrc; 3848 struct mlx5_bf *bf; 3849 int uninitialized_var(size); 3850 void *qend; 3851 unsigned long flags; 3852 unsigned idx; 3853 int err = 0; 3854 int inl = 0; 3855 int num_sge; 3856 void *seg; 3857 int nreq; 3858 int i; 3859 u8 next_fence = 0; 3860 u8 fence; 3861 3862 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 3863 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr); 3864 3865 qp = to_mqp(ibqp); 3866 bf = &qp->bf; 3867 qend = qp->sq.qend; 3868 3869 spin_lock_irqsave(&qp->sq.lock, flags); 3870 3871 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 3872 err = -EIO; 3873 *bad_wr = wr; 3874 nreq = 0; 3875 goto out; 3876 } 3877 3878 for (nreq = 0; wr; nreq++, wr = wr->next) { 3879 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) { 3880 mlx5_ib_warn(dev, "\n"); 3881 err = -EINVAL; 3882 *bad_wr = wr; 3883 goto out; 3884 } 3885 3886 num_sge = wr->num_sge; 3887 if (unlikely(num_sge > qp->sq.max_gs)) { 3888 mlx5_ib_warn(dev, "\n"); 3889 err = -EINVAL; 3890 *bad_wr = wr; 3891 goto out; 3892 } 3893 3894 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq); 3895 if (err) { 3896 mlx5_ib_warn(dev, "\n"); 3897 err = -ENOMEM; 3898 *bad_wr = wr; 3899 goto out; 3900 } 3901 3902 if (wr->opcode == IB_WR_LOCAL_INV || 3903 wr->opcode == IB_WR_REG_MR) { 3904 fence = dev->umr_fence; 3905 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 3906 } else if (wr->send_flags & IB_SEND_FENCE) { 3907 if (qp->next_fence) 3908 fence = MLX5_FENCE_MODE_SMALL_AND_FENCE; 3909 else 3910 fence = MLX5_FENCE_MODE_FENCE; 3911 } else { 3912 fence = qp->next_fence; 3913 } 3914 3915 switch (ibqp->qp_type) { 3916 case IB_QPT_XRC_INI: 3917 xrc = seg; 3918 seg += sizeof(*xrc); 3919 size += sizeof(*xrc) / 16; 3920 /* fall through */ 3921 case IB_QPT_RC: 3922 switch (wr->opcode) { 3923 case IB_WR_RDMA_READ: 3924 case IB_WR_RDMA_WRITE: 3925 case IB_WR_RDMA_WRITE_WITH_IMM: 3926 set_raddr_seg(seg, rdma_wr(wr)->remote_addr, 3927 rdma_wr(wr)->rkey); 3928 seg += sizeof(struct mlx5_wqe_raddr_seg); 3929 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 3930 break; 3931 3932 case IB_WR_ATOMIC_CMP_AND_SWP: 3933 case IB_WR_ATOMIC_FETCH_AND_ADD: 3934 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP: 3935 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n"); 3936 err = -ENOSYS; 3937 *bad_wr = wr; 3938 goto out; 3939 3940 case IB_WR_LOCAL_INV: 3941 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV; 3942 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey); 3943 set_linv_wr(qp, &seg, &size); 3944 num_sge = 0; 3945 break; 3946 3947 case IB_WR_REG_MR: 3948 qp->sq.wr_data[idx] = IB_WR_REG_MR; 3949 ctrl->imm = cpu_to_be32(reg_wr(wr)->key); 3950 err = set_reg_wr(qp, reg_wr(wr), &seg, &size); 3951 if (err) { 3952 *bad_wr = wr; 3953 goto out; 3954 } 3955 num_sge = 0; 3956 break; 3957 3958 case IB_WR_REG_SIG_MR: 3959 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR; 3960 mr = to_mmr(sig_handover_wr(wr)->sig_mr); 3961 3962 ctrl->imm = cpu_to_be32(mr->ibmr.rkey); 3963 err = set_sig_umr_wr(wr, qp, &seg, &size); 3964 if (err) { 3965 mlx5_ib_warn(dev, "\n"); 3966 *bad_wr = wr; 3967 goto out; 3968 } 3969 3970 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, 3971 fence, MLX5_OPCODE_UMR); 3972 /* 3973 * SET_PSV WQEs are not signaled and solicited 3974 * on error 3975 */ 3976 wr->send_flags &= ~IB_SEND_SIGNALED; 3977 wr->send_flags |= IB_SEND_SOLICITED; 3978 err = begin_wqe(qp, &seg, &ctrl, wr, 3979 &idx, &size, nreq); 3980 if (err) { 3981 mlx5_ib_warn(dev, "\n"); 3982 err = -ENOMEM; 3983 *bad_wr = wr; 3984 goto out; 3985 } 3986 3987 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem, 3988 mr->sig->psv_memory.psv_idx, &seg, 3989 &size); 3990 if (err) { 3991 mlx5_ib_warn(dev, "\n"); 3992 *bad_wr = wr; 3993 goto out; 3994 } 3995 3996 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, 3997 fence, MLX5_OPCODE_SET_PSV); 3998 err = begin_wqe(qp, &seg, &ctrl, wr, 3999 &idx, &size, nreq); 4000 if (err) { 4001 mlx5_ib_warn(dev, "\n"); 4002 err = -ENOMEM; 4003 *bad_wr = wr; 4004 goto out; 4005 } 4006 4007 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire, 4008 mr->sig->psv_wire.psv_idx, &seg, 4009 &size); 4010 if (err) { 4011 mlx5_ib_warn(dev, "\n"); 4012 *bad_wr = wr; 4013 goto out; 4014 } 4015 4016 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, 4017 fence, MLX5_OPCODE_SET_PSV); 4018 qp->next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 4019 num_sge = 0; 4020 goto skip_psv; 4021 4022 default: 4023 break; 4024 } 4025 break; 4026 4027 case IB_QPT_UC: 4028 switch (wr->opcode) { 4029 case IB_WR_RDMA_WRITE: 4030 case IB_WR_RDMA_WRITE_WITH_IMM: 4031 set_raddr_seg(seg, rdma_wr(wr)->remote_addr, 4032 rdma_wr(wr)->rkey); 4033 seg += sizeof(struct mlx5_wqe_raddr_seg); 4034 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 4035 break; 4036 4037 default: 4038 break; 4039 } 4040 break; 4041 4042 case IB_QPT_SMI: 4043 if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) { 4044 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n"); 4045 err = -EPERM; 4046 *bad_wr = wr; 4047 goto out; 4048 } 4049 case MLX5_IB_QPT_HW_GSI: 4050 set_datagram_seg(seg, wr); 4051 seg += sizeof(struct mlx5_wqe_datagram_seg); 4052 size += sizeof(struct mlx5_wqe_datagram_seg) / 16; 4053 if (unlikely((seg == qend))) 4054 seg = mlx5_get_send_wqe(qp, 0); 4055 break; 4056 case IB_QPT_UD: 4057 set_datagram_seg(seg, wr); 4058 seg += sizeof(struct mlx5_wqe_datagram_seg); 4059 size += sizeof(struct mlx5_wqe_datagram_seg) / 16; 4060 4061 if (unlikely((seg == qend))) 4062 seg = mlx5_get_send_wqe(qp, 0); 4063 4064 /* handle qp that supports ud offload */ 4065 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) { 4066 struct mlx5_wqe_eth_pad *pad; 4067 4068 pad = seg; 4069 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad)); 4070 seg += sizeof(struct mlx5_wqe_eth_pad); 4071 size += sizeof(struct mlx5_wqe_eth_pad) / 16; 4072 4073 seg = set_eth_seg(seg, wr, qend, qp, &size); 4074 4075 if (unlikely((seg == qend))) 4076 seg = mlx5_get_send_wqe(qp, 0); 4077 } 4078 break; 4079 case MLX5_IB_QPT_REG_UMR: 4080 if (wr->opcode != MLX5_IB_WR_UMR) { 4081 err = -EINVAL; 4082 mlx5_ib_warn(dev, "bad opcode\n"); 4083 goto out; 4084 } 4085 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR; 4086 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey); 4087 set_reg_umr_segment(seg, wr, !!(MLX5_CAP_GEN(mdev, atomic))); 4088 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 4089 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 4090 if (unlikely((seg == qend))) 4091 seg = mlx5_get_send_wqe(qp, 0); 4092 set_reg_mkey_segment(seg, wr); 4093 seg += sizeof(struct mlx5_mkey_seg); 4094 size += sizeof(struct mlx5_mkey_seg) / 16; 4095 if (unlikely((seg == qend))) 4096 seg = mlx5_get_send_wqe(qp, 0); 4097 break; 4098 4099 default: 4100 break; 4101 } 4102 4103 if (wr->send_flags & IB_SEND_INLINE && num_sge) { 4104 int uninitialized_var(sz); 4105 4106 err = set_data_inl_seg(qp, wr, seg, &sz); 4107 if (unlikely(err)) { 4108 mlx5_ib_warn(dev, "\n"); 4109 *bad_wr = wr; 4110 goto out; 4111 } 4112 inl = 1; 4113 size += sz; 4114 } else { 4115 dpseg = seg; 4116 for (i = 0; i < num_sge; i++) { 4117 if (unlikely(dpseg == qend)) { 4118 seg = mlx5_get_send_wqe(qp, 0); 4119 dpseg = seg; 4120 } 4121 if (likely(wr->sg_list[i].length)) { 4122 set_data_ptr_seg(dpseg, wr->sg_list + i); 4123 size += sizeof(struct mlx5_wqe_data_seg) / 16; 4124 dpseg++; 4125 } 4126 } 4127 } 4128 4129 qp->next_fence = next_fence; 4130 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, fence, 4131 mlx5_ib_opcode[wr->opcode]); 4132 skip_psv: 4133 if (0) 4134 dump_wqe(qp, idx, size); 4135 } 4136 4137 out: 4138 if (likely(nreq)) { 4139 qp->sq.head += nreq; 4140 4141 /* Make sure that descriptors are written before 4142 * updating doorbell record and ringing the doorbell 4143 */ 4144 wmb(); 4145 4146 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post); 4147 4148 /* Make sure doorbell record is visible to the HCA before 4149 * we hit doorbell */ 4150 wmb(); 4151 4152 /* currently we support only regular doorbells */ 4153 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset, NULL); 4154 /* Make sure doorbells don't leak out of SQ spinlock 4155 * and reach the HCA out of order. 4156 */ 4157 mmiowb(); 4158 bf->offset ^= bf->buf_size; 4159 } 4160 4161 spin_unlock_irqrestore(&qp->sq.lock, flags); 4162 4163 return err; 4164 } 4165 4166 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size) 4167 { 4168 sig->signature = calc_sig(sig, size); 4169 } 4170 4171 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, 4172 struct ib_recv_wr **bad_wr) 4173 { 4174 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4175 struct mlx5_wqe_data_seg *scat; 4176 struct mlx5_rwqe_sig *sig; 4177 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4178 struct mlx5_core_dev *mdev = dev->mdev; 4179 unsigned long flags; 4180 int err = 0; 4181 int nreq; 4182 int ind; 4183 int i; 4184 4185 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 4186 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr); 4187 4188 spin_lock_irqsave(&qp->rq.lock, flags); 4189 4190 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 4191 err = -EIO; 4192 *bad_wr = wr; 4193 nreq = 0; 4194 goto out; 4195 } 4196 4197 ind = qp->rq.head & (qp->rq.wqe_cnt - 1); 4198 4199 for (nreq = 0; wr; nreq++, wr = wr->next) { 4200 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) { 4201 err = -ENOMEM; 4202 *bad_wr = wr; 4203 goto out; 4204 } 4205 4206 if (unlikely(wr->num_sge > qp->rq.max_gs)) { 4207 err = -EINVAL; 4208 *bad_wr = wr; 4209 goto out; 4210 } 4211 4212 scat = get_recv_wqe(qp, ind); 4213 if (qp->wq_sig) 4214 scat++; 4215 4216 for (i = 0; i < wr->num_sge; i++) 4217 set_data_ptr_seg(scat + i, wr->sg_list + i); 4218 4219 if (i < qp->rq.max_gs) { 4220 scat[i].byte_count = 0; 4221 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY); 4222 scat[i].addr = 0; 4223 } 4224 4225 if (qp->wq_sig) { 4226 sig = (struct mlx5_rwqe_sig *)scat; 4227 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2); 4228 } 4229 4230 qp->rq.wrid[ind] = wr->wr_id; 4231 4232 ind = (ind + 1) & (qp->rq.wqe_cnt - 1); 4233 } 4234 4235 out: 4236 if (likely(nreq)) { 4237 qp->rq.head += nreq; 4238 4239 /* Make sure that descriptors are written before 4240 * doorbell record. 4241 */ 4242 wmb(); 4243 4244 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff); 4245 } 4246 4247 spin_unlock_irqrestore(&qp->rq.lock, flags); 4248 4249 return err; 4250 } 4251 4252 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state) 4253 { 4254 switch (mlx5_state) { 4255 case MLX5_QP_STATE_RST: return IB_QPS_RESET; 4256 case MLX5_QP_STATE_INIT: return IB_QPS_INIT; 4257 case MLX5_QP_STATE_RTR: return IB_QPS_RTR; 4258 case MLX5_QP_STATE_RTS: return IB_QPS_RTS; 4259 case MLX5_QP_STATE_SQ_DRAINING: 4260 case MLX5_QP_STATE_SQD: return IB_QPS_SQD; 4261 case MLX5_QP_STATE_SQER: return IB_QPS_SQE; 4262 case MLX5_QP_STATE_ERR: return IB_QPS_ERR; 4263 default: return -1; 4264 } 4265 } 4266 4267 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state) 4268 { 4269 switch (mlx5_mig_state) { 4270 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED; 4271 case MLX5_QP_PM_REARM: return IB_MIG_REARM; 4272 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED; 4273 default: return -1; 4274 } 4275 } 4276 4277 static int to_ib_qp_access_flags(int mlx5_flags) 4278 { 4279 int ib_flags = 0; 4280 4281 if (mlx5_flags & MLX5_QP_BIT_RRE) 4282 ib_flags |= IB_ACCESS_REMOTE_READ; 4283 if (mlx5_flags & MLX5_QP_BIT_RWE) 4284 ib_flags |= IB_ACCESS_REMOTE_WRITE; 4285 if (mlx5_flags & MLX5_QP_BIT_RAE) 4286 ib_flags |= IB_ACCESS_REMOTE_ATOMIC; 4287 4288 return ib_flags; 4289 } 4290 4291 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev, 4292 struct rdma_ah_attr *ah_attr, 4293 struct mlx5_qp_path *path) 4294 { 4295 struct mlx5_core_dev *dev = ibdev->mdev; 4296 4297 memset(ah_attr, 0, sizeof(*ah_attr)); 4298 4299 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port); 4300 rdma_ah_set_port_num(ah_attr, path->port); 4301 if (rdma_ah_get_port_num(ah_attr) == 0 || 4302 rdma_ah_get_port_num(ah_attr) > MLX5_CAP_GEN(dev, num_ports)) 4303 return; 4304 4305 rdma_ah_set_port_num(ah_attr, path->port); 4306 rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf); 4307 4308 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid)); 4309 rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f); 4310 rdma_ah_set_static_rate(ah_attr, 4311 path->static_rate ? path->static_rate - 5 : 0); 4312 if (path->grh_mlid & (1 << 7)) { 4313 u32 tc_fl = be32_to_cpu(path->tclass_flowlabel); 4314 4315 rdma_ah_set_grh(ah_attr, NULL, 4316 tc_fl & 0xfffff, 4317 path->mgid_index, 4318 path->hop_limit, 4319 (tc_fl >> 20) & 0xff); 4320 rdma_ah_set_dgid_raw(ah_attr, path->rgid); 4321 } 4322 } 4323 4324 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev, 4325 struct mlx5_ib_sq *sq, 4326 u8 *sq_state) 4327 { 4328 void *out; 4329 void *sqc; 4330 int inlen; 4331 int err; 4332 4333 inlen = MLX5_ST_SZ_BYTES(query_sq_out); 4334 out = kvzalloc(inlen, GFP_KERNEL); 4335 if (!out) 4336 return -ENOMEM; 4337 4338 err = mlx5_core_query_sq(dev->mdev, sq->base.mqp.qpn, out); 4339 if (err) 4340 goto out; 4341 4342 sqc = MLX5_ADDR_OF(query_sq_out, out, sq_context); 4343 *sq_state = MLX5_GET(sqc, sqc, state); 4344 sq->state = *sq_state; 4345 4346 out: 4347 kvfree(out); 4348 return err; 4349 } 4350 4351 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev, 4352 struct mlx5_ib_rq *rq, 4353 u8 *rq_state) 4354 { 4355 void *out; 4356 void *rqc; 4357 int inlen; 4358 int err; 4359 4360 inlen = MLX5_ST_SZ_BYTES(query_rq_out); 4361 out = kvzalloc(inlen, GFP_KERNEL); 4362 if (!out) 4363 return -ENOMEM; 4364 4365 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out); 4366 if (err) 4367 goto out; 4368 4369 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context); 4370 *rq_state = MLX5_GET(rqc, rqc, state); 4371 rq->state = *rq_state; 4372 4373 out: 4374 kvfree(out); 4375 return err; 4376 } 4377 4378 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state, 4379 struct mlx5_ib_qp *qp, u8 *qp_state) 4380 { 4381 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = { 4382 [MLX5_RQC_STATE_RST] = { 4383 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 4384 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4385 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD, 4386 [MLX5_SQ_STATE_NA] = IB_QPS_RESET, 4387 }, 4388 [MLX5_RQC_STATE_RDY] = { 4389 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 4390 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4391 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE, 4392 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE, 4393 }, 4394 [MLX5_RQC_STATE_ERR] = { 4395 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 4396 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4397 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR, 4398 [MLX5_SQ_STATE_NA] = IB_QPS_ERR, 4399 }, 4400 [MLX5_RQ_STATE_NA] = { 4401 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 4402 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4403 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE, 4404 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD, 4405 }, 4406 }; 4407 4408 *qp_state = sqrq_trans[rq_state][sq_state]; 4409 4410 if (*qp_state == MLX5_QP_STATE_BAD) { 4411 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x", 4412 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state, 4413 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state); 4414 return -EINVAL; 4415 } 4416 4417 if (*qp_state == MLX5_QP_STATE) 4418 *qp_state = qp->state; 4419 4420 return 0; 4421 } 4422 4423 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev, 4424 struct mlx5_ib_qp *qp, 4425 u8 *raw_packet_qp_state) 4426 { 4427 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 4428 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 4429 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 4430 int err; 4431 u8 sq_state = MLX5_SQ_STATE_NA; 4432 u8 rq_state = MLX5_RQ_STATE_NA; 4433 4434 if (qp->sq.wqe_cnt) { 4435 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state); 4436 if (err) 4437 return err; 4438 } 4439 4440 if (qp->rq.wqe_cnt) { 4441 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state); 4442 if (err) 4443 return err; 4444 } 4445 4446 return sqrq_state_to_qp_state(sq_state, rq_state, qp, 4447 raw_packet_qp_state); 4448 } 4449 4450 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 4451 struct ib_qp_attr *qp_attr) 4452 { 4453 int outlen = MLX5_ST_SZ_BYTES(query_qp_out); 4454 struct mlx5_qp_context *context; 4455 int mlx5_state; 4456 u32 *outb; 4457 int err = 0; 4458 4459 outb = kzalloc(outlen, GFP_KERNEL); 4460 if (!outb) 4461 return -ENOMEM; 4462 4463 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb, 4464 outlen); 4465 if (err) 4466 goto out; 4467 4468 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */ 4469 context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc); 4470 4471 mlx5_state = be32_to_cpu(context->flags) >> 28; 4472 4473 qp->state = to_ib_qp_state(mlx5_state); 4474 qp_attr->path_mtu = context->mtu_msgmax >> 5; 4475 qp_attr->path_mig_state = 4476 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3); 4477 qp_attr->qkey = be32_to_cpu(context->qkey); 4478 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff; 4479 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff; 4480 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff; 4481 qp_attr->qp_access_flags = 4482 to_ib_qp_access_flags(be32_to_cpu(context->params2)); 4483 4484 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) { 4485 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path); 4486 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path); 4487 qp_attr->alt_pkey_index = 4488 be16_to_cpu(context->alt_path.pkey_index); 4489 qp_attr->alt_port_num = 4490 rdma_ah_get_port_num(&qp_attr->alt_ah_attr); 4491 } 4492 4493 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index); 4494 qp_attr->port_num = context->pri_path.port; 4495 4496 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */ 4497 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING; 4498 4499 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7); 4500 4501 qp_attr->max_dest_rd_atomic = 4502 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7); 4503 qp_attr->min_rnr_timer = 4504 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f; 4505 qp_attr->timeout = context->pri_path.ackto_lt >> 3; 4506 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7; 4507 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7; 4508 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3; 4509 4510 out: 4511 kfree(outb); 4512 return err; 4513 } 4514 4515 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 4516 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 4517 { 4518 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4519 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4520 int err = 0; 4521 u8 raw_packet_qp_state; 4522 4523 if (ibqp->rwq_ind_tbl) 4524 return -ENOSYS; 4525 4526 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 4527 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask, 4528 qp_init_attr); 4529 4530 /* Not all of output fields are applicable, make sure to zero them */ 4531 memset(qp_init_attr, 0, sizeof(*qp_init_attr)); 4532 memset(qp_attr, 0, sizeof(*qp_attr)); 4533 4534 mutex_lock(&qp->mutex); 4535 4536 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 4537 qp->flags & MLX5_IB_QP_UNDERLAY) { 4538 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state); 4539 if (err) 4540 goto out; 4541 qp->state = raw_packet_qp_state; 4542 qp_attr->port_num = 1; 4543 } else { 4544 err = query_qp_attr(dev, qp, qp_attr); 4545 if (err) 4546 goto out; 4547 } 4548 4549 qp_attr->qp_state = qp->state; 4550 qp_attr->cur_qp_state = qp_attr->qp_state; 4551 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; 4552 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 4553 4554 if (!ibqp->uobject) { 4555 qp_attr->cap.max_send_wr = qp->sq.max_post; 4556 qp_attr->cap.max_send_sge = qp->sq.max_gs; 4557 qp_init_attr->qp_context = ibqp->qp_context; 4558 } else { 4559 qp_attr->cap.max_send_wr = 0; 4560 qp_attr->cap.max_send_sge = 0; 4561 } 4562 4563 qp_init_attr->qp_type = ibqp->qp_type; 4564 qp_init_attr->recv_cq = ibqp->recv_cq; 4565 qp_init_attr->send_cq = ibqp->send_cq; 4566 qp_init_attr->srq = ibqp->srq; 4567 qp_attr->cap.max_inline_data = qp->max_inline_data; 4568 4569 qp_init_attr->cap = qp_attr->cap; 4570 4571 qp_init_attr->create_flags = 0; 4572 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 4573 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK; 4574 4575 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 4576 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL; 4577 if (qp->flags & MLX5_IB_QP_MANAGED_SEND) 4578 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND; 4579 if (qp->flags & MLX5_IB_QP_MANAGED_RECV) 4580 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV; 4581 if (qp->flags & MLX5_IB_QP_SQPN_QP1) 4582 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1(); 4583 4584 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ? 4585 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; 4586 4587 out: 4588 mutex_unlock(&qp->mutex); 4589 return err; 4590 } 4591 4592 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, 4593 struct ib_ucontext *context, 4594 struct ib_udata *udata) 4595 { 4596 struct mlx5_ib_dev *dev = to_mdev(ibdev); 4597 struct mlx5_ib_xrcd *xrcd; 4598 int err; 4599 4600 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 4601 return ERR_PTR(-ENOSYS); 4602 4603 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL); 4604 if (!xrcd) 4605 return ERR_PTR(-ENOMEM); 4606 4607 err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn); 4608 if (err) { 4609 kfree(xrcd); 4610 return ERR_PTR(-ENOMEM); 4611 } 4612 4613 return &xrcd->ibxrcd; 4614 } 4615 4616 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd) 4617 { 4618 struct mlx5_ib_dev *dev = to_mdev(xrcd->device); 4619 u32 xrcdn = to_mxrcd(xrcd)->xrcdn; 4620 int err; 4621 4622 err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn); 4623 if (err) { 4624 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn); 4625 return err; 4626 } 4627 4628 kfree(xrcd); 4629 4630 return 0; 4631 } 4632 4633 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type) 4634 { 4635 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp); 4636 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device); 4637 struct ib_event event; 4638 4639 if (rwq->ibwq.event_handler) { 4640 event.device = rwq->ibwq.device; 4641 event.element.wq = &rwq->ibwq; 4642 switch (type) { 4643 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 4644 event.event = IB_EVENT_WQ_FATAL; 4645 break; 4646 default: 4647 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn); 4648 return; 4649 } 4650 4651 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context); 4652 } 4653 } 4654 4655 static int set_delay_drop(struct mlx5_ib_dev *dev) 4656 { 4657 int err = 0; 4658 4659 mutex_lock(&dev->delay_drop.lock); 4660 if (dev->delay_drop.activate) 4661 goto out; 4662 4663 err = mlx5_core_set_delay_drop(dev->mdev, dev->delay_drop.timeout); 4664 if (err) 4665 goto out; 4666 4667 dev->delay_drop.activate = true; 4668 out: 4669 mutex_unlock(&dev->delay_drop.lock); 4670 4671 if (!err) 4672 atomic_inc(&dev->delay_drop.rqs_cnt); 4673 return err; 4674 } 4675 4676 static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd, 4677 struct ib_wq_init_attr *init_attr) 4678 { 4679 struct mlx5_ib_dev *dev; 4680 int has_net_offloads; 4681 __be64 *rq_pas0; 4682 void *in; 4683 void *rqc; 4684 void *wq; 4685 int inlen; 4686 int err; 4687 4688 dev = to_mdev(pd->device); 4689 4690 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas; 4691 in = kvzalloc(inlen, GFP_KERNEL); 4692 if (!in) 4693 return -ENOMEM; 4694 4695 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 4696 MLX5_SET(rqc, rqc, mem_rq_type, 4697 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 4698 MLX5_SET(rqc, rqc, user_index, rwq->user_index); 4699 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn); 4700 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 4701 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 4702 wq = MLX5_ADDR_OF(rqc, rqc, wq); 4703 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 4704 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 4705 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride); 4706 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size); 4707 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn); 4708 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset); 4709 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size); 4710 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig); 4711 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma); 4712 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads); 4713 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) { 4714 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) { 4715 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n"); 4716 err = -EOPNOTSUPP; 4717 goto out; 4718 } 4719 } else { 4720 MLX5_SET(rqc, rqc, vsd, 1); 4721 } 4722 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) { 4723 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) { 4724 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n"); 4725 err = -EOPNOTSUPP; 4726 goto out; 4727 } 4728 MLX5_SET(rqc, rqc, scatter_fcs, 1); 4729 } 4730 if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { 4731 if (!(dev->ib_dev.attrs.raw_packet_caps & 4732 IB_RAW_PACKET_CAP_DELAY_DROP)) { 4733 mlx5_ib_dbg(dev, "Delay drop is not supported\n"); 4734 err = -EOPNOTSUPP; 4735 goto out; 4736 } 4737 MLX5_SET(rqc, rqc, delay_drop_en, 1); 4738 } 4739 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 4740 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0); 4741 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp); 4742 if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { 4743 err = set_delay_drop(dev); 4744 if (err) { 4745 mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n", 4746 err); 4747 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); 4748 } else { 4749 rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP; 4750 } 4751 } 4752 out: 4753 kvfree(in); 4754 return err; 4755 } 4756 4757 static int set_user_rq_size(struct mlx5_ib_dev *dev, 4758 struct ib_wq_init_attr *wq_init_attr, 4759 struct mlx5_ib_create_wq *ucmd, 4760 struct mlx5_ib_rwq *rwq) 4761 { 4762 /* Sanity check RQ size before proceeding */ 4763 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz))) 4764 return -EINVAL; 4765 4766 if (!ucmd->rq_wqe_count) 4767 return -EINVAL; 4768 4769 rwq->wqe_count = ucmd->rq_wqe_count; 4770 rwq->wqe_shift = ucmd->rq_wqe_shift; 4771 rwq->buf_size = (rwq->wqe_count << rwq->wqe_shift); 4772 rwq->log_rq_stride = rwq->wqe_shift; 4773 rwq->log_rq_size = ilog2(rwq->wqe_count); 4774 return 0; 4775 } 4776 4777 static int prepare_user_rq(struct ib_pd *pd, 4778 struct ib_wq_init_attr *init_attr, 4779 struct ib_udata *udata, 4780 struct mlx5_ib_rwq *rwq) 4781 { 4782 struct mlx5_ib_dev *dev = to_mdev(pd->device); 4783 struct mlx5_ib_create_wq ucmd = {}; 4784 int err; 4785 size_t required_cmd_sz; 4786 4787 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved); 4788 if (udata->inlen < required_cmd_sz) { 4789 mlx5_ib_dbg(dev, "invalid inlen\n"); 4790 return -EINVAL; 4791 } 4792 4793 if (udata->inlen > sizeof(ucmd) && 4794 !ib_is_udata_cleared(udata, sizeof(ucmd), 4795 udata->inlen - sizeof(ucmd))) { 4796 mlx5_ib_dbg(dev, "inlen is not supported\n"); 4797 return -EOPNOTSUPP; 4798 } 4799 4800 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 4801 mlx5_ib_dbg(dev, "copy failed\n"); 4802 return -EFAULT; 4803 } 4804 4805 if (ucmd.comp_mask) { 4806 mlx5_ib_dbg(dev, "invalid comp mask\n"); 4807 return -EOPNOTSUPP; 4808 } 4809 4810 if (ucmd.reserved) { 4811 mlx5_ib_dbg(dev, "invalid reserved\n"); 4812 return -EOPNOTSUPP; 4813 } 4814 4815 err = set_user_rq_size(dev, init_attr, &ucmd, rwq); 4816 if (err) { 4817 mlx5_ib_dbg(dev, "err %d\n", err); 4818 return err; 4819 } 4820 4821 err = create_user_rq(dev, pd, rwq, &ucmd); 4822 if (err) { 4823 mlx5_ib_dbg(dev, "err %d\n", err); 4824 if (err) 4825 return err; 4826 } 4827 4828 rwq->user_index = ucmd.user_index; 4829 return 0; 4830 } 4831 4832 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 4833 struct ib_wq_init_attr *init_attr, 4834 struct ib_udata *udata) 4835 { 4836 struct mlx5_ib_dev *dev; 4837 struct mlx5_ib_rwq *rwq; 4838 struct mlx5_ib_create_wq_resp resp = {}; 4839 size_t min_resp_len; 4840 int err; 4841 4842 if (!udata) 4843 return ERR_PTR(-ENOSYS); 4844 4845 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 4846 if (udata->outlen && udata->outlen < min_resp_len) 4847 return ERR_PTR(-EINVAL); 4848 4849 dev = to_mdev(pd->device); 4850 switch (init_attr->wq_type) { 4851 case IB_WQT_RQ: 4852 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL); 4853 if (!rwq) 4854 return ERR_PTR(-ENOMEM); 4855 err = prepare_user_rq(pd, init_attr, udata, rwq); 4856 if (err) 4857 goto err; 4858 err = create_rq(rwq, pd, init_attr); 4859 if (err) 4860 goto err_user_rq; 4861 break; 4862 default: 4863 mlx5_ib_dbg(dev, "unsupported wq type %d\n", 4864 init_attr->wq_type); 4865 return ERR_PTR(-EINVAL); 4866 } 4867 4868 rwq->ibwq.wq_num = rwq->core_qp.qpn; 4869 rwq->ibwq.state = IB_WQS_RESET; 4870 if (udata->outlen) { 4871 resp.response_length = offsetof(typeof(resp), response_length) + 4872 sizeof(resp.response_length); 4873 err = ib_copy_to_udata(udata, &resp, resp.response_length); 4874 if (err) 4875 goto err_copy; 4876 } 4877 4878 rwq->core_qp.event = mlx5_ib_wq_event; 4879 rwq->ibwq.event_handler = init_attr->event_handler; 4880 return &rwq->ibwq; 4881 4882 err_copy: 4883 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); 4884 err_user_rq: 4885 destroy_user_rq(dev, pd, rwq); 4886 err: 4887 kfree(rwq); 4888 return ERR_PTR(err); 4889 } 4890 4891 int mlx5_ib_destroy_wq(struct ib_wq *wq) 4892 { 4893 struct mlx5_ib_dev *dev = to_mdev(wq->device); 4894 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 4895 4896 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); 4897 destroy_user_rq(dev, wq->pd, rwq); 4898 kfree(rwq); 4899 4900 return 0; 4901 } 4902 4903 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device, 4904 struct ib_rwq_ind_table_init_attr *init_attr, 4905 struct ib_udata *udata) 4906 { 4907 struct mlx5_ib_dev *dev = to_mdev(device); 4908 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl; 4909 int sz = 1 << init_attr->log_ind_tbl_size; 4910 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {}; 4911 size_t min_resp_len; 4912 int inlen; 4913 int err; 4914 int i; 4915 u32 *in; 4916 void *rqtc; 4917 4918 if (udata->inlen > 0 && 4919 !ib_is_udata_cleared(udata, 0, 4920 udata->inlen)) 4921 return ERR_PTR(-EOPNOTSUPP); 4922 4923 if (init_attr->log_ind_tbl_size > 4924 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) { 4925 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n", 4926 init_attr->log_ind_tbl_size, 4927 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)); 4928 return ERR_PTR(-EINVAL); 4929 } 4930 4931 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 4932 if (udata->outlen && udata->outlen < min_resp_len) 4933 return ERR_PTR(-EINVAL); 4934 4935 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL); 4936 if (!rwq_ind_tbl) 4937 return ERR_PTR(-ENOMEM); 4938 4939 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; 4940 in = kvzalloc(inlen, GFP_KERNEL); 4941 if (!in) { 4942 err = -ENOMEM; 4943 goto err; 4944 } 4945 4946 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 4947 4948 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 4949 MLX5_SET(rqtc, rqtc, rqt_max_size, sz); 4950 4951 for (i = 0; i < sz; i++) 4952 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num); 4953 4954 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn); 4955 kvfree(in); 4956 4957 if (err) 4958 goto err; 4959 4960 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn; 4961 if (udata->outlen) { 4962 resp.response_length = offsetof(typeof(resp), response_length) + 4963 sizeof(resp.response_length); 4964 err = ib_copy_to_udata(udata, &resp, resp.response_length); 4965 if (err) 4966 goto err_copy; 4967 } 4968 4969 return &rwq_ind_tbl->ib_rwq_ind_tbl; 4970 4971 err_copy: 4972 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn); 4973 err: 4974 kfree(rwq_ind_tbl); 4975 return ERR_PTR(err); 4976 } 4977 4978 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 4979 { 4980 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl); 4981 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device); 4982 4983 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn); 4984 4985 kfree(rwq_ind_tbl); 4986 return 0; 4987 } 4988 4989 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 4990 u32 wq_attr_mask, struct ib_udata *udata) 4991 { 4992 struct mlx5_ib_dev *dev = to_mdev(wq->device); 4993 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 4994 struct mlx5_ib_modify_wq ucmd = {}; 4995 size_t required_cmd_sz; 4996 int curr_wq_state; 4997 int wq_state; 4998 int inlen; 4999 int err; 5000 void *rqc; 5001 void *in; 5002 5003 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved); 5004 if (udata->inlen < required_cmd_sz) 5005 return -EINVAL; 5006 5007 if (udata->inlen > sizeof(ucmd) && 5008 !ib_is_udata_cleared(udata, sizeof(ucmd), 5009 udata->inlen - sizeof(ucmd))) 5010 return -EOPNOTSUPP; 5011 5012 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) 5013 return -EFAULT; 5014 5015 if (ucmd.comp_mask || ucmd.reserved) 5016 return -EOPNOTSUPP; 5017 5018 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 5019 in = kvzalloc(inlen, GFP_KERNEL); 5020 if (!in) 5021 return -ENOMEM; 5022 5023 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 5024 5025 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ? 5026 wq_attr->curr_wq_state : wq->state; 5027 wq_state = (wq_attr_mask & IB_WQ_STATE) ? 5028 wq_attr->wq_state : curr_wq_state; 5029 if (curr_wq_state == IB_WQS_ERR) 5030 curr_wq_state = MLX5_RQC_STATE_ERR; 5031 if (wq_state == IB_WQS_ERR) 5032 wq_state = MLX5_RQC_STATE_ERR; 5033 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state); 5034 MLX5_SET(rqc, rqc, state, wq_state); 5035 5036 if (wq_attr_mask & IB_WQ_FLAGS) { 5037 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) { 5038 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 5039 MLX5_CAP_ETH(dev->mdev, vlan_cap))) { 5040 mlx5_ib_dbg(dev, "VLAN offloads are not " 5041 "supported\n"); 5042 err = -EOPNOTSUPP; 5043 goto out; 5044 } 5045 MLX5_SET64(modify_rq_in, in, modify_bitmask, 5046 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD); 5047 MLX5_SET(rqc, rqc, vsd, 5048 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1); 5049 } 5050 } 5051 5052 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) { 5053 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 5054 MLX5_SET64(modify_rq_in, in, modify_bitmask, 5055 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 5056 MLX5_SET(rqc, rqc, counter_set_id, 5057 dev->port->cnts.set_id); 5058 } else 5059 pr_info_once("%s: Receive WQ counters are not supported on current FW\n", 5060 dev->ib_dev.name); 5061 } 5062 5063 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen); 5064 if (!err) 5065 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state; 5066 5067 out: 5068 kvfree(in); 5069 return err; 5070 } 5071