1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/module.h> 34 #include <rdma/ib_umem.h> 35 #include <rdma/ib_cache.h> 36 #include <rdma/ib_user_verbs.h> 37 #include <linux/mlx5/fs.h> 38 #include "mlx5_ib.h" 39 40 /* not supported currently */ 41 static int wq_signature; 42 43 enum { 44 MLX5_IB_ACK_REQ_FREQ = 8, 45 }; 46 47 enum { 48 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83, 49 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, 50 MLX5_IB_LINK_TYPE_IB = 0, 51 MLX5_IB_LINK_TYPE_ETH = 1 52 }; 53 54 enum { 55 MLX5_IB_SQ_STRIDE = 6, 56 }; 57 58 static const u32 mlx5_ib_opcode[] = { 59 [IB_WR_SEND] = MLX5_OPCODE_SEND, 60 [IB_WR_LSO] = MLX5_OPCODE_LSO, 61 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM, 62 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE, 63 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM, 64 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ, 65 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS, 66 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA, 67 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL, 68 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR, 69 [IB_WR_REG_MR] = MLX5_OPCODE_UMR, 70 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS, 71 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA, 72 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR, 73 }; 74 75 struct mlx5_wqe_eth_pad { 76 u8 rsvd0[16]; 77 }; 78 79 enum raw_qp_set_mask_map { 80 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0, 81 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1, 82 }; 83 84 struct mlx5_modify_raw_qp_param { 85 u16 operation; 86 87 u32 set_mask; /* raw_qp_set_mask_map */ 88 u32 rate_limit; 89 u8 rq_q_ctr_id; 90 }; 91 92 static void get_cqs(enum ib_qp_type qp_type, 93 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 94 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq); 95 96 static int is_qp0(enum ib_qp_type qp_type) 97 { 98 return qp_type == IB_QPT_SMI; 99 } 100 101 static int is_sqp(enum ib_qp_type qp_type) 102 { 103 return is_qp0(qp_type) || is_qp1(qp_type); 104 } 105 106 static void *get_wqe(struct mlx5_ib_qp *qp, int offset) 107 { 108 return mlx5_buf_offset(&qp->buf, offset); 109 } 110 111 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n) 112 { 113 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift)); 114 } 115 116 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n) 117 { 118 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE)); 119 } 120 121 /** 122 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space. 123 * 124 * @qp: QP to copy from. 125 * @send: copy from the send queue when non-zero, use the receive queue 126 * otherwise. 127 * @wqe_index: index to start copying from. For send work queues, the 128 * wqe_index is in units of MLX5_SEND_WQE_BB. 129 * For receive work queue, it is the number of work queue 130 * element in the queue. 131 * @buffer: destination buffer. 132 * @length: maximum number of bytes to copy. 133 * 134 * Copies at least a single WQE, but may copy more data. 135 * 136 * Return: the number of bytes copied, or an error code. 137 */ 138 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index, 139 void *buffer, u32 length, 140 struct mlx5_ib_qp_base *base) 141 { 142 struct ib_device *ibdev = qp->ibqp.device; 143 struct mlx5_ib_dev *dev = to_mdev(ibdev); 144 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq; 145 size_t offset; 146 size_t wq_end; 147 struct ib_umem *umem = base->ubuffer.umem; 148 u32 first_copy_length; 149 int wqe_length; 150 int ret; 151 152 if (wq->wqe_cnt == 0) { 153 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n", 154 qp->ibqp.qp_type); 155 return -EINVAL; 156 } 157 158 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift); 159 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift); 160 161 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg)) 162 return -EINVAL; 163 164 if (offset > umem->length || 165 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length)) 166 return -EINVAL; 167 168 first_copy_length = min_t(u32, offset + length, wq_end) - offset; 169 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length); 170 if (ret) 171 return ret; 172 173 if (send) { 174 struct mlx5_wqe_ctrl_seg *ctrl = buffer; 175 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; 176 177 wqe_length = ds * MLX5_WQE_DS_UNITS; 178 } else { 179 wqe_length = 1 << wq->wqe_shift; 180 } 181 182 if (wqe_length <= first_copy_length) 183 return first_copy_length; 184 185 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset, 186 wqe_length - first_copy_length); 187 if (ret) 188 return ret; 189 190 return wqe_length; 191 } 192 193 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type) 194 { 195 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; 196 struct ib_event event; 197 198 if (type == MLX5_EVENT_TYPE_PATH_MIG) { 199 /* This event is only valid for trans_qps */ 200 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port; 201 } 202 203 if (ibqp->event_handler) { 204 event.device = ibqp->device; 205 event.element.qp = ibqp; 206 switch (type) { 207 case MLX5_EVENT_TYPE_PATH_MIG: 208 event.event = IB_EVENT_PATH_MIG; 209 break; 210 case MLX5_EVENT_TYPE_COMM_EST: 211 event.event = IB_EVENT_COMM_EST; 212 break; 213 case MLX5_EVENT_TYPE_SQ_DRAINED: 214 event.event = IB_EVENT_SQ_DRAINED; 215 break; 216 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 217 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 218 break; 219 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 220 event.event = IB_EVENT_QP_FATAL; 221 break; 222 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 223 event.event = IB_EVENT_PATH_MIG_ERR; 224 break; 225 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 226 event.event = IB_EVENT_QP_REQ_ERR; 227 break; 228 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 229 event.event = IB_EVENT_QP_ACCESS_ERR; 230 break; 231 default: 232 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn); 233 return; 234 } 235 236 ibqp->event_handler(&event, ibqp->qp_context); 237 } 238 } 239 240 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap, 241 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd) 242 { 243 int wqe_size; 244 int wq_size; 245 246 /* Sanity check RQ size before proceeding */ 247 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) 248 return -EINVAL; 249 250 if (!has_rq) { 251 qp->rq.max_gs = 0; 252 qp->rq.wqe_cnt = 0; 253 qp->rq.wqe_shift = 0; 254 cap->max_recv_wr = 0; 255 cap->max_recv_sge = 0; 256 } else { 257 if (ucmd) { 258 qp->rq.wqe_cnt = ucmd->rq_wqe_count; 259 qp->rq.wqe_shift = ucmd->rq_wqe_shift; 260 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 261 qp->rq.max_post = qp->rq.wqe_cnt; 262 } else { 263 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0; 264 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg); 265 wqe_size = roundup_pow_of_two(wqe_size); 266 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size; 267 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB); 268 qp->rq.wqe_cnt = wq_size / wqe_size; 269 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) { 270 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n", 271 wqe_size, 272 MLX5_CAP_GEN(dev->mdev, 273 max_wqe_sz_rq)); 274 return -EINVAL; 275 } 276 qp->rq.wqe_shift = ilog2(wqe_size); 277 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 278 qp->rq.max_post = qp->rq.wqe_cnt; 279 } 280 } 281 282 return 0; 283 } 284 285 static int sq_overhead(struct ib_qp_init_attr *attr) 286 { 287 int size = 0; 288 289 switch (attr->qp_type) { 290 case IB_QPT_XRC_INI: 291 size += sizeof(struct mlx5_wqe_xrc_seg); 292 /* fall through */ 293 case IB_QPT_RC: 294 size += sizeof(struct mlx5_wqe_ctrl_seg) + 295 max(sizeof(struct mlx5_wqe_atomic_seg) + 296 sizeof(struct mlx5_wqe_raddr_seg), 297 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 298 sizeof(struct mlx5_mkey_seg)); 299 break; 300 301 case IB_QPT_XRC_TGT: 302 return 0; 303 304 case IB_QPT_UC: 305 size += sizeof(struct mlx5_wqe_ctrl_seg) + 306 max(sizeof(struct mlx5_wqe_raddr_seg), 307 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 308 sizeof(struct mlx5_mkey_seg)); 309 break; 310 311 case IB_QPT_UD: 312 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) 313 size += sizeof(struct mlx5_wqe_eth_pad) + 314 sizeof(struct mlx5_wqe_eth_seg); 315 /* fall through */ 316 case IB_QPT_SMI: 317 case MLX5_IB_QPT_HW_GSI: 318 size += sizeof(struct mlx5_wqe_ctrl_seg) + 319 sizeof(struct mlx5_wqe_datagram_seg); 320 break; 321 322 case MLX5_IB_QPT_REG_UMR: 323 size += sizeof(struct mlx5_wqe_ctrl_seg) + 324 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 325 sizeof(struct mlx5_mkey_seg); 326 break; 327 328 default: 329 return -EINVAL; 330 } 331 332 return size; 333 } 334 335 static int calc_send_wqe(struct ib_qp_init_attr *attr) 336 { 337 int inl_size = 0; 338 int size; 339 340 size = sq_overhead(attr); 341 if (size < 0) 342 return size; 343 344 if (attr->cap.max_inline_data) { 345 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) + 346 attr->cap.max_inline_data; 347 } 348 349 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg); 350 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN && 351 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE) 352 return MLX5_SIG_WQE_SIZE; 353 else 354 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB); 355 } 356 357 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size) 358 { 359 int max_sge; 360 361 if (attr->qp_type == IB_QPT_RC) 362 max_sge = (min_t(int, wqe_size, 512) - 363 sizeof(struct mlx5_wqe_ctrl_seg) - 364 sizeof(struct mlx5_wqe_raddr_seg)) / 365 sizeof(struct mlx5_wqe_data_seg); 366 else if (attr->qp_type == IB_QPT_XRC_INI) 367 max_sge = (min_t(int, wqe_size, 512) - 368 sizeof(struct mlx5_wqe_ctrl_seg) - 369 sizeof(struct mlx5_wqe_xrc_seg) - 370 sizeof(struct mlx5_wqe_raddr_seg)) / 371 sizeof(struct mlx5_wqe_data_seg); 372 else 373 max_sge = (wqe_size - sq_overhead(attr)) / 374 sizeof(struct mlx5_wqe_data_seg); 375 376 return min_t(int, max_sge, wqe_size - sq_overhead(attr) / 377 sizeof(struct mlx5_wqe_data_seg)); 378 } 379 380 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, 381 struct mlx5_ib_qp *qp) 382 { 383 int wqe_size; 384 int wq_size; 385 386 if (!attr->cap.max_send_wr) 387 return 0; 388 389 wqe_size = calc_send_wqe(attr); 390 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size); 391 if (wqe_size < 0) 392 return wqe_size; 393 394 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 395 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n", 396 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 397 return -EINVAL; 398 } 399 400 qp->max_inline_data = wqe_size - sq_overhead(attr) - 401 sizeof(struct mlx5_wqe_inline_seg); 402 attr->cap.max_inline_data = qp->max_inline_data; 403 404 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN) 405 qp->signature_en = true; 406 407 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size); 408 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB; 409 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 410 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n", 411 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB, 412 qp->sq.wqe_cnt, 413 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 414 return -ENOMEM; 415 } 416 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 417 qp->sq.max_gs = get_send_sge(attr, wqe_size); 418 if (qp->sq.max_gs < attr->cap.max_send_sge) 419 return -ENOMEM; 420 421 attr->cap.max_send_sge = qp->sq.max_gs; 422 qp->sq.max_post = wq_size / wqe_size; 423 attr->cap.max_send_wr = qp->sq.max_post; 424 425 return wq_size; 426 } 427 428 static int set_user_buf_size(struct mlx5_ib_dev *dev, 429 struct mlx5_ib_qp *qp, 430 struct mlx5_ib_create_qp *ucmd, 431 struct mlx5_ib_qp_base *base, 432 struct ib_qp_init_attr *attr) 433 { 434 int desc_sz = 1 << qp->sq.wqe_shift; 435 436 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 437 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n", 438 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 439 return -EINVAL; 440 } 441 442 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) { 443 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n", 444 ucmd->sq_wqe_count, ucmd->sq_wqe_count); 445 return -EINVAL; 446 } 447 448 qp->sq.wqe_cnt = ucmd->sq_wqe_count; 449 450 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 451 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n", 452 qp->sq.wqe_cnt, 453 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 454 return -EINVAL; 455 } 456 457 if (attr->qp_type == IB_QPT_RAW_PACKET || 458 qp->flags & MLX5_IB_QP_UNDERLAY) { 459 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift; 460 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6; 461 } else { 462 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 463 (qp->sq.wqe_cnt << 6); 464 } 465 466 return 0; 467 } 468 469 static int qp_has_rq(struct ib_qp_init_attr *attr) 470 { 471 if (attr->qp_type == IB_QPT_XRC_INI || 472 attr->qp_type == IB_QPT_XRC_TGT || attr->srq || 473 attr->qp_type == MLX5_IB_QPT_REG_UMR || 474 !attr->cap.max_recv_wr) 475 return 0; 476 477 return 1; 478 } 479 480 static int first_med_bfreg(void) 481 { 482 return 1; 483 } 484 485 enum { 486 /* this is the first blue flame register in the array of bfregs assigned 487 * to a processes. Since we do not use it for blue flame but rather 488 * regular 64 bit doorbells, we do not need a lock for maintaiing 489 * "odd/even" order 490 */ 491 NUM_NON_BLUE_FLAME_BFREGS = 1, 492 }; 493 494 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi) 495 { 496 return get_num_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR; 497 } 498 499 static int num_med_bfreg(struct mlx5_ib_dev *dev, 500 struct mlx5_bfreg_info *bfregi) 501 { 502 int n; 503 504 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs - 505 NUM_NON_BLUE_FLAME_BFREGS; 506 507 return n >= 0 ? n : 0; 508 } 509 510 static int first_hi_bfreg(struct mlx5_ib_dev *dev, 511 struct mlx5_bfreg_info *bfregi) 512 { 513 int med; 514 515 med = num_med_bfreg(dev, bfregi); 516 return ++med; 517 } 518 519 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev, 520 struct mlx5_bfreg_info *bfregi) 521 { 522 int i; 523 524 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) { 525 if (!bfregi->count[i]) { 526 bfregi->count[i]++; 527 return i; 528 } 529 } 530 531 return -ENOMEM; 532 } 533 534 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev, 535 struct mlx5_bfreg_info *bfregi) 536 { 537 int minidx = first_med_bfreg(); 538 int i; 539 540 for (i = first_med_bfreg(); i < first_hi_bfreg(dev, bfregi); i++) { 541 if (bfregi->count[i] < bfregi->count[minidx]) 542 minidx = i; 543 if (!bfregi->count[minidx]) 544 break; 545 } 546 547 bfregi->count[minidx]++; 548 return minidx; 549 } 550 551 static int alloc_bfreg(struct mlx5_ib_dev *dev, 552 struct mlx5_bfreg_info *bfregi, 553 enum mlx5_ib_latency_class lat) 554 { 555 int bfregn = -EINVAL; 556 557 mutex_lock(&bfregi->lock); 558 switch (lat) { 559 case MLX5_IB_LATENCY_CLASS_LOW: 560 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1); 561 bfregn = 0; 562 bfregi->count[bfregn]++; 563 break; 564 565 case MLX5_IB_LATENCY_CLASS_MEDIUM: 566 if (bfregi->ver < 2) 567 bfregn = -ENOMEM; 568 else 569 bfregn = alloc_med_class_bfreg(dev, bfregi); 570 break; 571 572 case MLX5_IB_LATENCY_CLASS_HIGH: 573 if (bfregi->ver < 2) 574 bfregn = -ENOMEM; 575 else 576 bfregn = alloc_high_class_bfreg(dev, bfregi); 577 break; 578 } 579 mutex_unlock(&bfregi->lock); 580 581 return bfregn; 582 } 583 584 static void free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn) 585 { 586 mutex_lock(&bfregi->lock); 587 bfregi->count[bfregn]--; 588 mutex_unlock(&bfregi->lock); 589 } 590 591 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state) 592 { 593 switch (state) { 594 case IB_QPS_RESET: return MLX5_QP_STATE_RST; 595 case IB_QPS_INIT: return MLX5_QP_STATE_INIT; 596 case IB_QPS_RTR: return MLX5_QP_STATE_RTR; 597 case IB_QPS_RTS: return MLX5_QP_STATE_RTS; 598 case IB_QPS_SQD: return MLX5_QP_STATE_SQD; 599 case IB_QPS_SQE: return MLX5_QP_STATE_SQER; 600 case IB_QPS_ERR: return MLX5_QP_STATE_ERR; 601 default: return -1; 602 } 603 } 604 605 static int to_mlx5_st(enum ib_qp_type type) 606 { 607 switch (type) { 608 case IB_QPT_RC: return MLX5_QP_ST_RC; 609 case IB_QPT_UC: return MLX5_QP_ST_UC; 610 case IB_QPT_UD: return MLX5_QP_ST_UD; 611 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR; 612 case IB_QPT_XRC_INI: 613 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC; 614 case IB_QPT_SMI: return MLX5_QP_ST_QP0; 615 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1; 616 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6; 617 case IB_QPT_RAW_PACKET: 618 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE; 619 case IB_QPT_MAX: 620 default: return -EINVAL; 621 } 622 } 623 624 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, 625 struct mlx5_ib_cq *recv_cq); 626 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, 627 struct mlx5_ib_cq *recv_cq); 628 629 static int bfregn_to_uar_index(struct mlx5_ib_dev *dev, 630 struct mlx5_bfreg_info *bfregi, int bfregn) 631 { 632 int bfregs_per_sys_page; 633 int index_of_sys_page; 634 int offset; 635 636 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * 637 MLX5_NON_FP_BFREGS_PER_UAR; 638 index_of_sys_page = bfregn / bfregs_per_sys_page; 639 640 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR; 641 642 return bfregi->sys_pages[index_of_sys_page] + offset; 643 } 644 645 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev, 646 struct ib_pd *pd, 647 unsigned long addr, size_t size, 648 struct ib_umem **umem, 649 int *npages, int *page_shift, int *ncont, 650 u32 *offset) 651 { 652 int err; 653 654 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0); 655 if (IS_ERR(*umem)) { 656 mlx5_ib_dbg(dev, "umem_get failed\n"); 657 return PTR_ERR(*umem); 658 } 659 660 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL); 661 662 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset); 663 if (err) { 664 mlx5_ib_warn(dev, "bad offset\n"); 665 goto err_umem; 666 } 667 668 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n", 669 addr, size, *npages, *page_shift, *ncont, *offset); 670 671 return 0; 672 673 err_umem: 674 ib_umem_release(*umem); 675 *umem = NULL; 676 677 return err; 678 } 679 680 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 681 struct mlx5_ib_rwq *rwq) 682 { 683 struct mlx5_ib_ucontext *context; 684 685 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP) 686 atomic_dec(&dev->delay_drop.rqs_cnt); 687 688 context = to_mucontext(pd->uobject->context); 689 mlx5_ib_db_unmap_user(context, &rwq->db); 690 if (rwq->umem) 691 ib_umem_release(rwq->umem); 692 } 693 694 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 695 struct mlx5_ib_rwq *rwq, 696 struct mlx5_ib_create_wq *ucmd) 697 { 698 struct mlx5_ib_ucontext *context; 699 int page_shift = 0; 700 int npages; 701 u32 offset = 0; 702 int ncont = 0; 703 int err; 704 705 if (!ucmd->buf_addr) 706 return -EINVAL; 707 708 context = to_mucontext(pd->uobject->context); 709 rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr, 710 rwq->buf_size, 0, 0); 711 if (IS_ERR(rwq->umem)) { 712 mlx5_ib_dbg(dev, "umem_get failed\n"); 713 err = PTR_ERR(rwq->umem); 714 return err; 715 } 716 717 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift, 718 &ncont, NULL); 719 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift, 720 &rwq->rq_page_offset); 721 if (err) { 722 mlx5_ib_warn(dev, "bad offset\n"); 723 goto err_umem; 724 } 725 726 rwq->rq_num_pas = ncont; 727 rwq->page_shift = page_shift; 728 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT; 729 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE); 730 731 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n", 732 (unsigned long long)ucmd->buf_addr, rwq->buf_size, 733 npages, page_shift, ncont, offset); 734 735 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db); 736 if (err) { 737 mlx5_ib_dbg(dev, "map failed\n"); 738 goto err_umem; 739 } 740 741 rwq->create_type = MLX5_WQ_USER; 742 return 0; 743 744 err_umem: 745 ib_umem_release(rwq->umem); 746 return err; 747 } 748 749 static int adjust_bfregn(struct mlx5_ib_dev *dev, 750 struct mlx5_bfreg_info *bfregi, int bfregn) 751 { 752 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR + 753 bfregn % MLX5_NON_FP_BFREGS_PER_UAR; 754 } 755 756 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 757 struct mlx5_ib_qp *qp, struct ib_udata *udata, 758 struct ib_qp_init_attr *attr, 759 u32 **in, 760 struct mlx5_ib_create_qp_resp *resp, int *inlen, 761 struct mlx5_ib_qp_base *base) 762 { 763 struct mlx5_ib_ucontext *context; 764 struct mlx5_ib_create_qp ucmd; 765 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer; 766 int page_shift = 0; 767 int uar_index; 768 int npages; 769 u32 offset = 0; 770 int bfregn; 771 int ncont = 0; 772 __be64 *pas; 773 void *qpc; 774 int err; 775 776 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd)); 777 if (err) { 778 mlx5_ib_dbg(dev, "copy failed\n"); 779 return err; 780 } 781 782 context = to_mucontext(pd->uobject->context); 783 /* 784 * TBD: should come from the verbs when we have the API 785 */ 786 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 787 /* In CROSS_CHANNEL CQ and QP must use the same UAR */ 788 bfregn = MLX5_CROSS_CHANNEL_BFREG; 789 else { 790 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_HIGH); 791 if (bfregn < 0) { 792 mlx5_ib_dbg(dev, "failed to allocate low latency BFREG\n"); 793 mlx5_ib_dbg(dev, "reverting to medium latency\n"); 794 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_MEDIUM); 795 if (bfregn < 0) { 796 mlx5_ib_dbg(dev, "failed to allocate medium latency BFREG\n"); 797 mlx5_ib_dbg(dev, "reverting to high latency\n"); 798 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_LOW); 799 if (bfregn < 0) { 800 mlx5_ib_warn(dev, "bfreg allocation failed\n"); 801 return bfregn; 802 } 803 } 804 } 805 } 806 807 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn); 808 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index); 809 810 qp->rq.offset = 0; 811 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 812 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 813 814 err = set_user_buf_size(dev, qp, &ucmd, base, attr); 815 if (err) 816 goto err_bfreg; 817 818 if (ucmd.buf_addr && ubuffer->buf_size) { 819 ubuffer->buf_addr = ucmd.buf_addr; 820 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, 821 ubuffer->buf_size, 822 &ubuffer->umem, &npages, &page_shift, 823 &ncont, &offset); 824 if (err) 825 goto err_bfreg; 826 } else { 827 ubuffer->umem = NULL; 828 } 829 830 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 831 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont; 832 *in = kvzalloc(*inlen, GFP_KERNEL); 833 if (!*in) { 834 err = -ENOMEM; 835 goto err_umem; 836 } 837 838 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas); 839 if (ubuffer->umem) 840 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0); 841 842 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 843 844 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT); 845 MLX5_SET(qpc, qpc, page_offset, offset); 846 847 MLX5_SET(qpc, qpc, uar_page, uar_index); 848 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn); 849 qp->bfregn = bfregn; 850 851 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db); 852 if (err) { 853 mlx5_ib_dbg(dev, "map failed\n"); 854 goto err_free; 855 } 856 857 err = ib_copy_to_udata(udata, resp, sizeof(*resp)); 858 if (err) { 859 mlx5_ib_dbg(dev, "copy failed\n"); 860 goto err_unmap; 861 } 862 qp->create_type = MLX5_QP_USER; 863 864 return 0; 865 866 err_unmap: 867 mlx5_ib_db_unmap_user(context, &qp->db); 868 869 err_free: 870 kvfree(*in); 871 872 err_umem: 873 if (ubuffer->umem) 874 ib_umem_release(ubuffer->umem); 875 876 err_bfreg: 877 free_bfreg(dev, &context->bfregi, bfregn); 878 return err; 879 } 880 881 static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd, 882 struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base) 883 { 884 struct mlx5_ib_ucontext *context; 885 886 context = to_mucontext(pd->uobject->context); 887 mlx5_ib_db_unmap_user(context, &qp->db); 888 if (base->ubuffer.umem) 889 ib_umem_release(base->ubuffer.umem); 890 free_bfreg(dev, &context->bfregi, qp->bfregn); 891 } 892 893 static int create_kernel_qp(struct mlx5_ib_dev *dev, 894 struct ib_qp_init_attr *init_attr, 895 struct mlx5_ib_qp *qp, 896 u32 **in, int *inlen, 897 struct mlx5_ib_qp_base *base) 898 { 899 int uar_index; 900 void *qpc; 901 int err; 902 903 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN | 904 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK | 905 IB_QP_CREATE_IPOIB_UD_LSO | 906 IB_QP_CREATE_NETIF_QP | 907 mlx5_ib_create_qp_sqpn_qp1())) 908 return -EINVAL; 909 910 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR) 911 qp->bf.bfreg = &dev->fp_bfreg; 912 else 913 qp->bf.bfreg = &dev->bfreg; 914 915 /* We need to divide by two since each register is comprised of 916 * two buffers of identical size, namely odd and even 917 */ 918 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2; 919 uar_index = qp->bf.bfreg->index; 920 921 err = calc_sq_size(dev, init_attr, qp); 922 if (err < 0) { 923 mlx5_ib_dbg(dev, "err %d\n", err); 924 return err; 925 } 926 927 qp->rq.offset = 0; 928 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 929 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift); 930 931 err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf); 932 if (err) { 933 mlx5_ib_dbg(dev, "err %d\n", err); 934 return err; 935 } 936 937 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt); 938 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 939 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages; 940 *in = kvzalloc(*inlen, GFP_KERNEL); 941 if (!*in) { 942 err = -ENOMEM; 943 goto err_buf; 944 } 945 946 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 947 MLX5_SET(qpc, qpc, uar_page, uar_index); 948 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT); 949 950 /* Set "fast registration enabled" for all kernel QPs */ 951 MLX5_SET(qpc, qpc, fre, 1); 952 MLX5_SET(qpc, qpc, rlky, 1); 953 954 if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) { 955 MLX5_SET(qpc, qpc, deth_sqpn, 1); 956 qp->flags |= MLX5_IB_QP_SQPN_QP1; 957 } 958 959 mlx5_fill_page_array(&qp->buf, 960 (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas)); 961 962 err = mlx5_db_alloc(dev->mdev, &qp->db); 963 if (err) { 964 mlx5_ib_dbg(dev, "err %d\n", err); 965 goto err_free; 966 } 967 968 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt, 969 sizeof(*qp->sq.wrid), GFP_KERNEL); 970 qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt, 971 sizeof(*qp->sq.wr_data), GFP_KERNEL); 972 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt, 973 sizeof(*qp->rq.wrid), GFP_KERNEL); 974 qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt, 975 sizeof(*qp->sq.w_list), GFP_KERNEL); 976 qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt, 977 sizeof(*qp->sq.wqe_head), GFP_KERNEL); 978 979 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid || 980 !qp->sq.w_list || !qp->sq.wqe_head) { 981 err = -ENOMEM; 982 goto err_wrid; 983 } 984 qp->create_type = MLX5_QP_KERNEL; 985 986 return 0; 987 988 err_wrid: 989 kvfree(qp->sq.wqe_head); 990 kvfree(qp->sq.w_list); 991 kvfree(qp->sq.wrid); 992 kvfree(qp->sq.wr_data); 993 kvfree(qp->rq.wrid); 994 mlx5_db_free(dev->mdev, &qp->db); 995 996 err_free: 997 kvfree(*in); 998 999 err_buf: 1000 mlx5_buf_free(dev->mdev, &qp->buf); 1001 return err; 1002 } 1003 1004 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1005 { 1006 kvfree(qp->sq.wqe_head); 1007 kvfree(qp->sq.w_list); 1008 kvfree(qp->sq.wrid); 1009 kvfree(qp->sq.wr_data); 1010 kvfree(qp->rq.wrid); 1011 mlx5_db_free(dev->mdev, &qp->db); 1012 mlx5_buf_free(dev->mdev, &qp->buf); 1013 } 1014 1015 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr) 1016 { 1017 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) || 1018 (attr->qp_type == IB_QPT_XRC_INI)) 1019 return MLX5_SRQ_RQ; 1020 else if (!qp->has_rq) 1021 return MLX5_ZERO_LEN_RQ; 1022 else 1023 return MLX5_NON_ZERO_RQ; 1024 } 1025 1026 static int is_connected(enum ib_qp_type qp_type) 1027 { 1028 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC) 1029 return 1; 1030 1031 return 0; 1032 } 1033 1034 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1035 struct mlx5_ib_qp *qp, 1036 struct mlx5_ib_sq *sq, u32 tdn) 1037 { 1038 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 1039 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 1040 1041 MLX5_SET(tisc, tisc, transport_domain, tdn); 1042 if (qp->flags & MLX5_IB_QP_UNDERLAY) 1043 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn); 1044 1045 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn); 1046 } 1047 1048 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1049 struct mlx5_ib_sq *sq) 1050 { 1051 mlx5_core_destroy_tis(dev->mdev, sq->tisn); 1052 } 1053 1054 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1055 struct mlx5_ib_sq *sq, void *qpin, 1056 struct ib_pd *pd) 1057 { 1058 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer; 1059 __be64 *pas; 1060 void *in; 1061 void *sqc; 1062 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1063 void *wq; 1064 int inlen; 1065 int err; 1066 int page_shift = 0; 1067 int npages; 1068 int ncont = 0; 1069 u32 offset = 0; 1070 1071 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size, 1072 &sq->ubuffer.umem, &npages, &page_shift, 1073 &ncont, &offset); 1074 if (err) 1075 return err; 1076 1077 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont; 1078 in = kvzalloc(inlen, GFP_KERNEL); 1079 if (!in) { 1080 err = -ENOMEM; 1081 goto err_umem; 1082 } 1083 1084 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 1085 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 1086 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe)) 1087 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1); 1088 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 1089 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1090 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd)); 1091 MLX5_SET(sqc, sqc, tis_lst_sz, 1); 1092 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn); 1093 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 1094 MLX5_CAP_ETH(dev->mdev, swp)) 1095 MLX5_SET(sqc, sqc, allow_swp, 1); 1096 1097 wq = MLX5_ADDR_OF(sqc, sqc, wq); 1098 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1099 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1100 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page)); 1101 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1102 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 1103 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size)); 1104 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT); 1105 MLX5_SET(wq, wq, page_offset, offset); 1106 1107 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1108 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0); 1109 1110 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp); 1111 1112 kvfree(in); 1113 1114 if (err) 1115 goto err_umem; 1116 1117 return 0; 1118 1119 err_umem: 1120 ib_umem_release(sq->ubuffer.umem); 1121 sq->ubuffer.umem = NULL; 1122 1123 return err; 1124 } 1125 1126 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1127 struct mlx5_ib_sq *sq) 1128 { 1129 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp); 1130 ib_umem_release(sq->ubuffer.umem); 1131 } 1132 1133 static int get_rq_pas_size(void *qpc) 1134 { 1135 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12; 1136 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride); 1137 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size); 1138 u32 page_offset = MLX5_GET(qpc, qpc, page_offset); 1139 u32 po_quanta = 1 << (log_page_size - 6); 1140 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride); 1141 u32 page_size = 1 << log_page_size; 1142 u32 rq_sz_po = rq_sz + (page_offset * po_quanta); 1143 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size; 1144 1145 return rq_num_pas * sizeof(u64); 1146 } 1147 1148 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1149 struct mlx5_ib_rq *rq, void *qpin) 1150 { 1151 struct mlx5_ib_qp *mqp = rq->base.container_mibqp; 1152 __be64 *pas; 1153 __be64 *qp_pas; 1154 void *in; 1155 void *rqc; 1156 void *wq; 1157 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1158 int inlen; 1159 int err; 1160 u32 rq_pas_size = get_rq_pas_size(qpc); 1161 1162 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size; 1163 in = kvzalloc(inlen, GFP_KERNEL); 1164 if (!in) 1165 return -ENOMEM; 1166 1167 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 1168 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING)) 1169 MLX5_SET(rqc, rqc, vsd, 1); 1170 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 1171 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 1172 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 1173 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1174 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv)); 1175 1176 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS) 1177 MLX5_SET(rqc, rqc, scatter_fcs, 1); 1178 1179 wq = MLX5_ADDR_OF(rqc, rqc, wq); 1180 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1181 MLX5_SET(wq, wq, end_padding_mode, 1182 MLX5_GET(qpc, qpc, end_padding_mode)); 1183 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset)); 1184 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1185 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1186 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4); 1187 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size)); 1188 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size)); 1189 1190 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1191 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas); 1192 memcpy(pas, qp_pas, rq_pas_size); 1193 1194 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp); 1195 1196 kvfree(in); 1197 1198 return err; 1199 } 1200 1201 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1202 struct mlx5_ib_rq *rq) 1203 { 1204 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp); 1205 } 1206 1207 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1208 struct mlx5_ib_rq *rq, u32 tdn) 1209 { 1210 u32 *in; 1211 void *tirc; 1212 int inlen; 1213 int err; 1214 1215 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1216 in = kvzalloc(inlen, GFP_KERNEL); 1217 if (!in) 1218 return -ENOMEM; 1219 1220 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1221 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT); 1222 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn); 1223 MLX5_SET(tirc, tirc, transport_domain, tdn); 1224 1225 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn); 1226 1227 kvfree(in); 1228 1229 return err; 1230 } 1231 1232 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1233 struct mlx5_ib_rq *rq) 1234 { 1235 mlx5_core_destroy_tir(dev->mdev, rq->tirn); 1236 } 1237 1238 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1239 u32 *in, 1240 struct ib_pd *pd) 1241 { 1242 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1243 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1244 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1245 struct ib_uobject *uobj = pd->uobject; 1246 struct ib_ucontext *ucontext = uobj->context; 1247 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext); 1248 int err; 1249 u32 tdn = mucontext->tdn; 1250 1251 if (qp->sq.wqe_cnt) { 1252 err = create_raw_packet_qp_tis(dev, qp, sq, tdn); 1253 if (err) 1254 return err; 1255 1256 err = create_raw_packet_qp_sq(dev, sq, in, pd); 1257 if (err) 1258 goto err_destroy_tis; 1259 1260 sq->base.container_mibqp = qp; 1261 sq->base.mqp.event = mlx5_ib_qp_event; 1262 } 1263 1264 if (qp->rq.wqe_cnt) { 1265 rq->base.container_mibqp = qp; 1266 1267 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING) 1268 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING; 1269 err = create_raw_packet_qp_rq(dev, rq, in); 1270 if (err) 1271 goto err_destroy_sq; 1272 1273 1274 err = create_raw_packet_qp_tir(dev, rq, tdn); 1275 if (err) 1276 goto err_destroy_rq; 1277 } 1278 1279 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn : 1280 rq->base.mqp.qpn; 1281 1282 return 0; 1283 1284 err_destroy_rq: 1285 destroy_raw_packet_qp_rq(dev, rq); 1286 err_destroy_sq: 1287 if (!qp->sq.wqe_cnt) 1288 return err; 1289 destroy_raw_packet_qp_sq(dev, sq); 1290 err_destroy_tis: 1291 destroy_raw_packet_qp_tis(dev, sq); 1292 1293 return err; 1294 } 1295 1296 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev, 1297 struct mlx5_ib_qp *qp) 1298 { 1299 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1300 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1301 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1302 1303 if (qp->rq.wqe_cnt) { 1304 destroy_raw_packet_qp_tir(dev, rq); 1305 destroy_raw_packet_qp_rq(dev, rq); 1306 } 1307 1308 if (qp->sq.wqe_cnt) { 1309 destroy_raw_packet_qp_sq(dev, sq); 1310 destroy_raw_packet_qp_tis(dev, sq); 1311 } 1312 } 1313 1314 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp, 1315 struct mlx5_ib_raw_packet_qp *raw_packet_qp) 1316 { 1317 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1318 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1319 1320 sq->sq = &qp->sq; 1321 rq->rq = &qp->rq; 1322 sq->doorbell = &qp->db; 1323 rq->doorbell = &qp->db; 1324 } 1325 1326 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1327 { 1328 mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn); 1329 } 1330 1331 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1332 struct ib_pd *pd, 1333 struct ib_qp_init_attr *init_attr, 1334 struct ib_udata *udata) 1335 { 1336 struct ib_uobject *uobj = pd->uobject; 1337 struct ib_ucontext *ucontext = uobj->context; 1338 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext); 1339 struct mlx5_ib_create_qp_resp resp = {}; 1340 int inlen; 1341 int err; 1342 u32 *in; 1343 void *tirc; 1344 void *hfso; 1345 u32 selected_fields = 0; 1346 size_t min_resp_len; 1347 u32 tdn = mucontext->tdn; 1348 struct mlx5_ib_create_qp_rss ucmd = {}; 1349 size_t required_cmd_sz; 1350 1351 if (init_attr->qp_type != IB_QPT_RAW_PACKET) 1352 return -EOPNOTSUPP; 1353 1354 if (init_attr->create_flags || init_attr->send_cq) 1355 return -EINVAL; 1356 1357 min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index); 1358 if (udata->outlen < min_resp_len) 1359 return -EINVAL; 1360 1361 required_cmd_sz = offsetof(typeof(ucmd), reserved1) + sizeof(ucmd.reserved1); 1362 if (udata->inlen < required_cmd_sz) { 1363 mlx5_ib_dbg(dev, "invalid inlen\n"); 1364 return -EINVAL; 1365 } 1366 1367 if (udata->inlen > sizeof(ucmd) && 1368 !ib_is_udata_cleared(udata, sizeof(ucmd), 1369 udata->inlen - sizeof(ucmd))) { 1370 mlx5_ib_dbg(dev, "inlen is not supported\n"); 1371 return -EOPNOTSUPP; 1372 } 1373 1374 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 1375 mlx5_ib_dbg(dev, "copy failed\n"); 1376 return -EFAULT; 1377 } 1378 1379 if (ucmd.comp_mask) { 1380 mlx5_ib_dbg(dev, "invalid comp mask\n"); 1381 return -EOPNOTSUPP; 1382 } 1383 1384 if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved)) || ucmd.reserved1) { 1385 mlx5_ib_dbg(dev, "invalid reserved\n"); 1386 return -EOPNOTSUPP; 1387 } 1388 1389 err = ib_copy_to_udata(udata, &resp, min_resp_len); 1390 if (err) { 1391 mlx5_ib_dbg(dev, "copy failed\n"); 1392 return -EINVAL; 1393 } 1394 1395 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1396 in = kvzalloc(inlen, GFP_KERNEL); 1397 if (!in) 1398 return -ENOMEM; 1399 1400 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1401 MLX5_SET(tirc, tirc, disp_type, 1402 MLX5_TIRC_DISP_TYPE_INDIRECT); 1403 MLX5_SET(tirc, tirc, indirect_table, 1404 init_attr->rwq_ind_tbl->ind_tbl_num); 1405 MLX5_SET(tirc, tirc, transport_domain, tdn); 1406 1407 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1408 switch (ucmd.rx_hash_function) { 1409 case MLX5_RX_HASH_FUNC_TOEPLITZ: 1410 { 1411 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key); 1412 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key); 1413 1414 if (len != ucmd.rx_key_len) { 1415 err = -EINVAL; 1416 goto err; 1417 } 1418 1419 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ); 1420 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1); 1421 memcpy(rss_key, ucmd.rx_hash_key, len); 1422 break; 1423 } 1424 default: 1425 err = -EOPNOTSUPP; 1426 goto err; 1427 } 1428 1429 if (!ucmd.rx_hash_fields_mask) { 1430 /* special case when this TIR serves as steering entry without hashing */ 1431 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size) 1432 goto create_tir; 1433 err = -EINVAL; 1434 goto err; 1435 } 1436 1437 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1438 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) && 1439 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1440 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) { 1441 err = -EINVAL; 1442 goto err; 1443 } 1444 1445 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */ 1446 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1447 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) 1448 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1449 MLX5_L3_PROT_TYPE_IPV4); 1450 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1451 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1452 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1453 MLX5_L3_PROT_TYPE_IPV6); 1454 1455 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1456 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) && 1457 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1458 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))) { 1459 err = -EINVAL; 1460 goto err; 1461 } 1462 1463 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */ 1464 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1465 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) 1466 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1467 MLX5_L4_PROT_TYPE_TCP); 1468 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1469 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1470 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1471 MLX5_L4_PROT_TYPE_UDP); 1472 1473 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1474 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6)) 1475 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP; 1476 1477 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) || 1478 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1479 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP; 1480 1481 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1482 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP)) 1483 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT; 1484 1485 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) || 1486 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1487 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT; 1488 1489 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields); 1490 1491 create_tir: 1492 err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn); 1493 1494 if (err) 1495 goto err; 1496 1497 kvfree(in); 1498 /* qpn is reserved for that QP */ 1499 qp->trans_qp.base.mqp.qpn = 0; 1500 qp->flags |= MLX5_IB_QP_RSS; 1501 return 0; 1502 1503 err: 1504 kvfree(in); 1505 return err; 1506 } 1507 1508 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd, 1509 struct ib_qp_init_attr *init_attr, 1510 struct ib_udata *udata, struct mlx5_ib_qp *qp) 1511 { 1512 struct mlx5_ib_resources *devr = &dev->devr; 1513 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 1514 struct mlx5_core_dev *mdev = dev->mdev; 1515 struct mlx5_ib_create_qp_resp resp; 1516 struct mlx5_ib_cq *send_cq; 1517 struct mlx5_ib_cq *recv_cq; 1518 unsigned long flags; 1519 u32 uidx = MLX5_IB_DEFAULT_UIDX; 1520 struct mlx5_ib_create_qp ucmd; 1521 struct mlx5_ib_qp_base *base; 1522 void *qpc; 1523 u32 *in; 1524 int err; 1525 1526 mutex_init(&qp->mutex); 1527 spin_lock_init(&qp->sq.lock); 1528 spin_lock_init(&qp->rq.lock); 1529 1530 if (init_attr->rwq_ind_tbl) { 1531 if (!udata) 1532 return -ENOSYS; 1533 1534 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata); 1535 return err; 1536 } 1537 1538 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) { 1539 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) { 1540 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n"); 1541 return -EINVAL; 1542 } else { 1543 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK; 1544 } 1545 } 1546 1547 if (init_attr->create_flags & 1548 (IB_QP_CREATE_CROSS_CHANNEL | 1549 IB_QP_CREATE_MANAGED_SEND | 1550 IB_QP_CREATE_MANAGED_RECV)) { 1551 if (!MLX5_CAP_GEN(mdev, cd)) { 1552 mlx5_ib_dbg(dev, "cross-channel isn't supported\n"); 1553 return -EINVAL; 1554 } 1555 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL) 1556 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL; 1557 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND) 1558 qp->flags |= MLX5_IB_QP_MANAGED_SEND; 1559 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV) 1560 qp->flags |= MLX5_IB_QP_MANAGED_RECV; 1561 } 1562 1563 if (init_attr->qp_type == IB_QPT_UD && 1564 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) 1565 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 1566 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n"); 1567 return -EOPNOTSUPP; 1568 } 1569 1570 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) { 1571 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 1572 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs"); 1573 return -EOPNOTSUPP; 1574 } 1575 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) || 1576 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) { 1577 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n"); 1578 return -EOPNOTSUPP; 1579 } 1580 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS; 1581 } 1582 1583 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 1584 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 1585 1586 if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) { 1587 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 1588 MLX5_CAP_ETH(dev->mdev, vlan_cap)) || 1589 (init_attr->qp_type != IB_QPT_RAW_PACKET)) 1590 return -EOPNOTSUPP; 1591 qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING; 1592 } 1593 1594 if (pd && pd->uobject) { 1595 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) { 1596 mlx5_ib_dbg(dev, "copy failed\n"); 1597 return -EFAULT; 1598 } 1599 1600 err = get_qp_user_index(to_mucontext(pd->uobject->context), 1601 &ucmd, udata->inlen, &uidx); 1602 if (err) 1603 return err; 1604 1605 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE); 1606 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE); 1607 1608 if (init_attr->create_flags & IB_QP_CREATE_SOURCE_QPN) { 1609 if (init_attr->qp_type != IB_QPT_UD || 1610 (MLX5_CAP_GEN(dev->mdev, port_type) != 1611 MLX5_CAP_PORT_TYPE_IB) || 1612 !mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) { 1613 mlx5_ib_dbg(dev, "Source QP option isn't supported\n"); 1614 return -EOPNOTSUPP; 1615 } 1616 1617 qp->flags |= MLX5_IB_QP_UNDERLAY; 1618 qp->underlay_qpn = init_attr->source_qpn; 1619 } 1620 } else { 1621 qp->wq_sig = !!wq_signature; 1622 } 1623 1624 base = (init_attr->qp_type == IB_QPT_RAW_PACKET || 1625 qp->flags & MLX5_IB_QP_UNDERLAY) ? 1626 &qp->raw_packet_qp.rq.base : 1627 &qp->trans_qp.base; 1628 1629 qp->has_rq = qp_has_rq(init_attr); 1630 err = set_rq_size(dev, &init_attr->cap, qp->has_rq, 1631 qp, (pd && pd->uobject) ? &ucmd : NULL); 1632 if (err) { 1633 mlx5_ib_dbg(dev, "err %d\n", err); 1634 return err; 1635 } 1636 1637 if (pd) { 1638 if (pd->uobject) { 1639 __u32 max_wqes = 1640 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 1641 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count); 1642 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift || 1643 ucmd.rq_wqe_count != qp->rq.wqe_cnt) { 1644 mlx5_ib_dbg(dev, "invalid rq params\n"); 1645 return -EINVAL; 1646 } 1647 if (ucmd.sq_wqe_count > max_wqes) { 1648 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n", 1649 ucmd.sq_wqe_count, max_wqes); 1650 return -EINVAL; 1651 } 1652 if (init_attr->create_flags & 1653 mlx5_ib_create_qp_sqpn_qp1()) { 1654 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n"); 1655 return -EINVAL; 1656 } 1657 err = create_user_qp(dev, pd, qp, udata, init_attr, &in, 1658 &resp, &inlen, base); 1659 if (err) 1660 mlx5_ib_dbg(dev, "err %d\n", err); 1661 } else { 1662 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen, 1663 base); 1664 if (err) 1665 mlx5_ib_dbg(dev, "err %d\n", err); 1666 } 1667 1668 if (err) 1669 return err; 1670 } else { 1671 in = kvzalloc(inlen, GFP_KERNEL); 1672 if (!in) 1673 return -ENOMEM; 1674 1675 qp->create_type = MLX5_QP_EMPTY; 1676 } 1677 1678 if (is_sqp(init_attr->qp_type)) 1679 qp->port = init_attr->port_num; 1680 1681 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 1682 1683 MLX5_SET(qpc, qpc, st, to_mlx5_st(init_attr->qp_type)); 1684 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 1685 1686 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR) 1687 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn); 1688 else 1689 MLX5_SET(qpc, qpc, latency_sensitive, 1); 1690 1691 1692 if (qp->wq_sig) 1693 MLX5_SET(qpc, qpc, wq_signature, 1); 1694 1695 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 1696 MLX5_SET(qpc, qpc, block_lb_mc, 1); 1697 1698 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 1699 MLX5_SET(qpc, qpc, cd_master, 1); 1700 if (qp->flags & MLX5_IB_QP_MANAGED_SEND) 1701 MLX5_SET(qpc, qpc, cd_slave_send, 1); 1702 if (qp->flags & MLX5_IB_QP_MANAGED_RECV) 1703 MLX5_SET(qpc, qpc, cd_slave_receive, 1); 1704 1705 if (qp->scat_cqe && is_connected(init_attr->qp_type)) { 1706 int rcqe_sz; 1707 int scqe_sz; 1708 1709 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq); 1710 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq); 1711 1712 if (rcqe_sz == 128) 1713 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE); 1714 else 1715 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE); 1716 1717 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) { 1718 if (scqe_sz == 128) 1719 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE); 1720 else 1721 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE); 1722 } 1723 } 1724 1725 if (qp->rq.wqe_cnt) { 1726 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); 1727 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); 1728 } 1729 1730 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr)); 1731 1732 if (qp->sq.wqe_cnt) 1733 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); 1734 else 1735 MLX5_SET(qpc, qpc, no_sq, 1); 1736 1737 /* Set default resources */ 1738 switch (init_attr->qp_type) { 1739 case IB_QPT_XRC_TGT: 1740 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 1741 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn); 1742 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 1743 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn); 1744 break; 1745 case IB_QPT_XRC_INI: 1746 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 1747 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn); 1748 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 1749 break; 1750 default: 1751 if (init_attr->srq) { 1752 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn); 1753 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn); 1754 } else { 1755 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn); 1756 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn); 1757 } 1758 } 1759 1760 if (init_attr->send_cq) 1761 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn); 1762 1763 if (init_attr->recv_cq) 1764 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn); 1765 1766 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 1767 1768 /* 0xffffff means we ask to work with cqe version 0 */ 1769 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 1770 MLX5_SET(qpc, qpc, user_index, uidx); 1771 1772 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */ 1773 if (init_attr->qp_type == IB_QPT_UD && 1774 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) { 1775 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1); 1776 qp->flags |= MLX5_IB_QP_LSO; 1777 } 1778 1779 if (init_attr->qp_type == IB_QPT_RAW_PACKET || 1780 qp->flags & MLX5_IB_QP_UNDERLAY) { 1781 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr; 1782 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp); 1783 err = create_raw_packet_qp(dev, qp, in, pd); 1784 } else { 1785 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen); 1786 } 1787 1788 if (err) { 1789 mlx5_ib_dbg(dev, "create qp failed\n"); 1790 goto err_create; 1791 } 1792 1793 kvfree(in); 1794 1795 base->container_mibqp = qp; 1796 base->mqp.event = mlx5_ib_qp_event; 1797 1798 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq, 1799 &send_cq, &recv_cq); 1800 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 1801 mlx5_ib_lock_cqs(send_cq, recv_cq); 1802 /* Maintain device to QPs access, needed for further handling via reset 1803 * flow 1804 */ 1805 list_add_tail(&qp->qps_list, &dev->qp_list); 1806 /* Maintain CQ to QPs access, needed for further handling via reset flow 1807 */ 1808 if (send_cq) 1809 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); 1810 if (recv_cq) 1811 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); 1812 mlx5_ib_unlock_cqs(send_cq, recv_cq); 1813 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 1814 1815 return 0; 1816 1817 err_create: 1818 if (qp->create_type == MLX5_QP_USER) 1819 destroy_qp_user(dev, pd, qp, base); 1820 else if (qp->create_type == MLX5_QP_KERNEL) 1821 destroy_qp_kernel(dev, qp); 1822 1823 kvfree(in); 1824 return err; 1825 } 1826 1827 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 1828 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 1829 { 1830 if (send_cq) { 1831 if (recv_cq) { 1832 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1833 spin_lock(&send_cq->lock); 1834 spin_lock_nested(&recv_cq->lock, 1835 SINGLE_DEPTH_NESTING); 1836 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 1837 spin_lock(&send_cq->lock); 1838 __acquire(&recv_cq->lock); 1839 } else { 1840 spin_lock(&recv_cq->lock); 1841 spin_lock_nested(&send_cq->lock, 1842 SINGLE_DEPTH_NESTING); 1843 } 1844 } else { 1845 spin_lock(&send_cq->lock); 1846 __acquire(&recv_cq->lock); 1847 } 1848 } else if (recv_cq) { 1849 spin_lock(&recv_cq->lock); 1850 __acquire(&send_cq->lock); 1851 } else { 1852 __acquire(&send_cq->lock); 1853 __acquire(&recv_cq->lock); 1854 } 1855 } 1856 1857 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 1858 __releases(&send_cq->lock) __releases(&recv_cq->lock) 1859 { 1860 if (send_cq) { 1861 if (recv_cq) { 1862 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1863 spin_unlock(&recv_cq->lock); 1864 spin_unlock(&send_cq->lock); 1865 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 1866 __release(&recv_cq->lock); 1867 spin_unlock(&send_cq->lock); 1868 } else { 1869 spin_unlock(&send_cq->lock); 1870 spin_unlock(&recv_cq->lock); 1871 } 1872 } else { 1873 __release(&recv_cq->lock); 1874 spin_unlock(&send_cq->lock); 1875 } 1876 } else if (recv_cq) { 1877 __release(&send_cq->lock); 1878 spin_unlock(&recv_cq->lock); 1879 } else { 1880 __release(&recv_cq->lock); 1881 __release(&send_cq->lock); 1882 } 1883 } 1884 1885 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp) 1886 { 1887 return to_mpd(qp->ibqp.pd); 1888 } 1889 1890 static void get_cqs(enum ib_qp_type qp_type, 1891 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 1892 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq) 1893 { 1894 switch (qp_type) { 1895 case IB_QPT_XRC_TGT: 1896 *send_cq = NULL; 1897 *recv_cq = NULL; 1898 break; 1899 case MLX5_IB_QPT_REG_UMR: 1900 case IB_QPT_XRC_INI: 1901 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 1902 *recv_cq = NULL; 1903 break; 1904 1905 case IB_QPT_SMI: 1906 case MLX5_IB_QPT_HW_GSI: 1907 case IB_QPT_RC: 1908 case IB_QPT_UC: 1909 case IB_QPT_UD: 1910 case IB_QPT_RAW_IPV6: 1911 case IB_QPT_RAW_ETHERTYPE: 1912 case IB_QPT_RAW_PACKET: 1913 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 1914 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL; 1915 break; 1916 1917 case IB_QPT_MAX: 1918 default: 1919 *send_cq = NULL; 1920 *recv_cq = NULL; 1921 break; 1922 } 1923 } 1924 1925 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1926 const struct mlx5_modify_raw_qp_param *raw_qp_param, 1927 u8 lag_tx_affinity); 1928 1929 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1930 { 1931 struct mlx5_ib_cq *send_cq, *recv_cq; 1932 struct mlx5_ib_qp_base *base; 1933 unsigned long flags; 1934 int err; 1935 1936 if (qp->ibqp.rwq_ind_tbl) { 1937 destroy_rss_raw_qp_tir(dev, qp); 1938 return; 1939 } 1940 1941 base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 1942 qp->flags & MLX5_IB_QP_UNDERLAY) ? 1943 &qp->raw_packet_qp.rq.base : 1944 &qp->trans_qp.base; 1945 1946 if (qp->state != IB_QPS_RESET) { 1947 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET && 1948 !(qp->flags & MLX5_IB_QP_UNDERLAY)) { 1949 err = mlx5_core_qp_modify(dev->mdev, 1950 MLX5_CMD_OP_2RST_QP, 0, 1951 NULL, &base->mqp); 1952 } else { 1953 struct mlx5_modify_raw_qp_param raw_qp_param = { 1954 .operation = MLX5_CMD_OP_2RST_QP 1955 }; 1956 1957 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0); 1958 } 1959 if (err) 1960 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n", 1961 base->mqp.qpn); 1962 } 1963 1964 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 1965 &send_cq, &recv_cq); 1966 1967 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 1968 mlx5_ib_lock_cqs(send_cq, recv_cq); 1969 /* del from lists under both locks above to protect reset flow paths */ 1970 list_del(&qp->qps_list); 1971 if (send_cq) 1972 list_del(&qp->cq_send_list); 1973 1974 if (recv_cq) 1975 list_del(&qp->cq_recv_list); 1976 1977 if (qp->create_type == MLX5_QP_KERNEL) { 1978 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 1979 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL); 1980 if (send_cq != recv_cq) 1981 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn, 1982 NULL); 1983 } 1984 mlx5_ib_unlock_cqs(send_cq, recv_cq); 1985 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 1986 1987 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 1988 qp->flags & MLX5_IB_QP_UNDERLAY) { 1989 destroy_raw_packet_qp(dev, qp); 1990 } else { 1991 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp); 1992 if (err) 1993 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n", 1994 base->mqp.qpn); 1995 } 1996 1997 if (qp->create_type == MLX5_QP_KERNEL) 1998 destroy_qp_kernel(dev, qp); 1999 else if (qp->create_type == MLX5_QP_USER) 2000 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base); 2001 } 2002 2003 static const char *ib_qp_type_str(enum ib_qp_type type) 2004 { 2005 switch (type) { 2006 case IB_QPT_SMI: 2007 return "IB_QPT_SMI"; 2008 case IB_QPT_GSI: 2009 return "IB_QPT_GSI"; 2010 case IB_QPT_RC: 2011 return "IB_QPT_RC"; 2012 case IB_QPT_UC: 2013 return "IB_QPT_UC"; 2014 case IB_QPT_UD: 2015 return "IB_QPT_UD"; 2016 case IB_QPT_RAW_IPV6: 2017 return "IB_QPT_RAW_IPV6"; 2018 case IB_QPT_RAW_ETHERTYPE: 2019 return "IB_QPT_RAW_ETHERTYPE"; 2020 case IB_QPT_XRC_INI: 2021 return "IB_QPT_XRC_INI"; 2022 case IB_QPT_XRC_TGT: 2023 return "IB_QPT_XRC_TGT"; 2024 case IB_QPT_RAW_PACKET: 2025 return "IB_QPT_RAW_PACKET"; 2026 case MLX5_IB_QPT_REG_UMR: 2027 return "MLX5_IB_QPT_REG_UMR"; 2028 case IB_QPT_MAX: 2029 default: 2030 return "Invalid QP type"; 2031 } 2032 } 2033 2034 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, 2035 struct ib_qp_init_attr *init_attr, 2036 struct ib_udata *udata) 2037 { 2038 struct mlx5_ib_dev *dev; 2039 struct mlx5_ib_qp *qp; 2040 u16 xrcdn = 0; 2041 int err; 2042 2043 if (pd) { 2044 dev = to_mdev(pd->device); 2045 2046 if (init_attr->qp_type == IB_QPT_RAW_PACKET) { 2047 if (!pd->uobject) { 2048 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n"); 2049 return ERR_PTR(-EINVAL); 2050 } else if (!to_mucontext(pd->uobject->context)->cqe_version) { 2051 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n"); 2052 return ERR_PTR(-EINVAL); 2053 } 2054 } 2055 } else { 2056 /* being cautious here */ 2057 if (init_attr->qp_type != IB_QPT_XRC_TGT && 2058 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) { 2059 pr_warn("%s: no PD for transport %s\n", __func__, 2060 ib_qp_type_str(init_attr->qp_type)); 2061 return ERR_PTR(-EINVAL); 2062 } 2063 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device); 2064 } 2065 2066 switch (init_attr->qp_type) { 2067 case IB_QPT_XRC_TGT: 2068 case IB_QPT_XRC_INI: 2069 if (!MLX5_CAP_GEN(dev->mdev, xrc)) { 2070 mlx5_ib_dbg(dev, "XRC not supported\n"); 2071 return ERR_PTR(-ENOSYS); 2072 } 2073 init_attr->recv_cq = NULL; 2074 if (init_attr->qp_type == IB_QPT_XRC_TGT) { 2075 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn; 2076 init_attr->send_cq = NULL; 2077 } 2078 2079 /* fall through */ 2080 case IB_QPT_RAW_PACKET: 2081 case IB_QPT_RC: 2082 case IB_QPT_UC: 2083 case IB_QPT_UD: 2084 case IB_QPT_SMI: 2085 case MLX5_IB_QPT_HW_GSI: 2086 case MLX5_IB_QPT_REG_UMR: 2087 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 2088 if (!qp) 2089 return ERR_PTR(-ENOMEM); 2090 2091 err = create_qp_common(dev, pd, init_attr, udata, qp); 2092 if (err) { 2093 mlx5_ib_dbg(dev, "create_qp_common failed\n"); 2094 kfree(qp); 2095 return ERR_PTR(err); 2096 } 2097 2098 if (is_qp0(init_attr->qp_type)) 2099 qp->ibqp.qp_num = 0; 2100 else if (is_qp1(init_attr->qp_type)) 2101 qp->ibqp.qp_num = 1; 2102 else 2103 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn; 2104 2105 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n", 2106 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn, 2107 init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1, 2108 init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1); 2109 2110 qp->trans_qp.xrcdn = xrcdn; 2111 2112 break; 2113 2114 case IB_QPT_GSI: 2115 return mlx5_ib_gsi_create_qp(pd, init_attr); 2116 2117 case IB_QPT_RAW_IPV6: 2118 case IB_QPT_RAW_ETHERTYPE: 2119 case IB_QPT_MAX: 2120 default: 2121 mlx5_ib_dbg(dev, "unsupported qp type %d\n", 2122 init_attr->qp_type); 2123 /* Don't support raw QPs */ 2124 return ERR_PTR(-EINVAL); 2125 } 2126 2127 return &qp->ibqp; 2128 } 2129 2130 int mlx5_ib_destroy_qp(struct ib_qp *qp) 2131 { 2132 struct mlx5_ib_dev *dev = to_mdev(qp->device); 2133 struct mlx5_ib_qp *mqp = to_mqp(qp); 2134 2135 if (unlikely(qp->qp_type == IB_QPT_GSI)) 2136 return mlx5_ib_gsi_destroy_qp(qp); 2137 2138 destroy_qp_common(dev, mqp); 2139 2140 kfree(mqp); 2141 2142 return 0; 2143 } 2144 2145 static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr, 2146 int attr_mask) 2147 { 2148 u32 hw_access_flags = 0; 2149 u8 dest_rd_atomic; 2150 u32 access_flags; 2151 2152 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 2153 dest_rd_atomic = attr->max_dest_rd_atomic; 2154 else 2155 dest_rd_atomic = qp->trans_qp.resp_depth; 2156 2157 if (attr_mask & IB_QP_ACCESS_FLAGS) 2158 access_flags = attr->qp_access_flags; 2159 else 2160 access_flags = qp->trans_qp.atomic_rd_en; 2161 2162 if (!dest_rd_atomic) 2163 access_flags &= IB_ACCESS_REMOTE_WRITE; 2164 2165 if (access_flags & IB_ACCESS_REMOTE_READ) 2166 hw_access_flags |= MLX5_QP_BIT_RRE; 2167 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) 2168 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX); 2169 if (access_flags & IB_ACCESS_REMOTE_WRITE) 2170 hw_access_flags |= MLX5_QP_BIT_RWE; 2171 2172 return cpu_to_be32(hw_access_flags); 2173 } 2174 2175 enum { 2176 MLX5_PATH_FLAG_FL = 1 << 0, 2177 MLX5_PATH_FLAG_FREE_AR = 1 << 1, 2178 MLX5_PATH_FLAG_COUNTER = 1 << 2, 2179 }; 2180 2181 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate) 2182 { 2183 if (rate == IB_RATE_PORT_CURRENT) { 2184 return 0; 2185 } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) { 2186 return -EINVAL; 2187 } else { 2188 while (rate != IB_RATE_2_5_GBPS && 2189 !(1 << (rate + MLX5_STAT_RATE_OFFSET) & 2190 MLX5_CAP_GEN(dev->mdev, stat_rate_support))) 2191 --rate; 2192 } 2193 2194 return rate + MLX5_STAT_RATE_OFFSET; 2195 } 2196 2197 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev, 2198 struct mlx5_ib_sq *sq, u8 sl) 2199 { 2200 void *in; 2201 void *tisc; 2202 int inlen; 2203 int err; 2204 2205 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 2206 in = kvzalloc(inlen, GFP_KERNEL); 2207 if (!in) 2208 return -ENOMEM; 2209 2210 MLX5_SET(modify_tis_in, in, bitmask.prio, 1); 2211 2212 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 2213 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1)); 2214 2215 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen); 2216 2217 kvfree(in); 2218 2219 return err; 2220 } 2221 2222 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev, 2223 struct mlx5_ib_sq *sq, u8 tx_affinity) 2224 { 2225 void *in; 2226 void *tisc; 2227 int inlen; 2228 int err; 2229 2230 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 2231 in = kvzalloc(inlen, GFP_KERNEL); 2232 if (!in) 2233 return -ENOMEM; 2234 2235 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1); 2236 2237 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 2238 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity); 2239 2240 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen); 2241 2242 kvfree(in); 2243 2244 return err; 2245 } 2246 2247 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2248 const struct rdma_ah_attr *ah, 2249 struct mlx5_qp_path *path, u8 port, int attr_mask, 2250 u32 path_flags, const struct ib_qp_attr *attr, 2251 bool alt) 2252 { 2253 const struct ib_global_route *grh = rdma_ah_read_grh(ah); 2254 int err; 2255 enum ib_gid_type gid_type; 2256 u8 ah_flags = rdma_ah_get_ah_flags(ah); 2257 u8 sl = rdma_ah_get_sl(ah); 2258 2259 if (attr_mask & IB_QP_PKEY_INDEX) 2260 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index : 2261 attr->pkey_index); 2262 2263 if (ah_flags & IB_AH_GRH) { 2264 if (grh->sgid_index >= 2265 dev->mdev->port_caps[port - 1].gid_table_len) { 2266 pr_err("sgid_index (%u) too large. max is %d\n", 2267 grh->sgid_index, 2268 dev->mdev->port_caps[port - 1].gid_table_len); 2269 return -EINVAL; 2270 } 2271 } 2272 2273 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) { 2274 if (!(ah_flags & IB_AH_GRH)) 2275 return -EINVAL; 2276 err = mlx5_get_roce_gid_type(dev, port, grh->sgid_index, 2277 &gid_type); 2278 if (err) 2279 return err; 2280 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac)); 2281 path->udp_sport = mlx5_get_roce_udp_sport(dev, port, 2282 grh->sgid_index); 2283 path->dci_cfi_prio_sl = (sl & 0x7) << 4; 2284 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) 2285 path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f; 2286 } else { 2287 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0; 2288 path->fl_free_ar |= 2289 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0; 2290 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah)); 2291 path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f; 2292 if (ah_flags & IB_AH_GRH) 2293 path->grh_mlid |= 1 << 7; 2294 path->dci_cfi_prio_sl = sl & 0xf; 2295 } 2296 2297 if (ah_flags & IB_AH_GRH) { 2298 path->mgid_index = grh->sgid_index; 2299 path->hop_limit = grh->hop_limit; 2300 path->tclass_flowlabel = 2301 cpu_to_be32((grh->traffic_class << 20) | 2302 (grh->flow_label)); 2303 memcpy(path->rgid, grh->dgid.raw, 16); 2304 } 2305 2306 err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah)); 2307 if (err < 0) 2308 return err; 2309 path->static_rate = err; 2310 path->port = port; 2311 2312 if (attr_mask & IB_QP_TIMEOUT) 2313 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3; 2314 2315 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt) 2316 return modify_raw_packet_eth_prio(dev->mdev, 2317 &qp->raw_packet_qp.sq, 2318 sl & 0xf); 2319 2320 return 0; 2321 } 2322 2323 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = { 2324 [MLX5_QP_STATE_INIT] = { 2325 [MLX5_QP_STATE_INIT] = { 2326 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 2327 MLX5_QP_OPTPAR_RAE | 2328 MLX5_QP_OPTPAR_RWE | 2329 MLX5_QP_OPTPAR_PKEY_INDEX | 2330 MLX5_QP_OPTPAR_PRI_PORT, 2331 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 2332 MLX5_QP_OPTPAR_PKEY_INDEX | 2333 MLX5_QP_OPTPAR_PRI_PORT, 2334 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 2335 MLX5_QP_OPTPAR_Q_KEY | 2336 MLX5_QP_OPTPAR_PRI_PORT, 2337 }, 2338 [MLX5_QP_STATE_RTR] = { 2339 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2340 MLX5_QP_OPTPAR_RRE | 2341 MLX5_QP_OPTPAR_RAE | 2342 MLX5_QP_OPTPAR_RWE | 2343 MLX5_QP_OPTPAR_PKEY_INDEX, 2344 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2345 MLX5_QP_OPTPAR_RWE | 2346 MLX5_QP_OPTPAR_PKEY_INDEX, 2347 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 2348 MLX5_QP_OPTPAR_Q_KEY, 2349 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX | 2350 MLX5_QP_OPTPAR_Q_KEY, 2351 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2352 MLX5_QP_OPTPAR_RRE | 2353 MLX5_QP_OPTPAR_RAE | 2354 MLX5_QP_OPTPAR_RWE | 2355 MLX5_QP_OPTPAR_PKEY_INDEX, 2356 }, 2357 }, 2358 [MLX5_QP_STATE_RTR] = { 2359 [MLX5_QP_STATE_RTS] = { 2360 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2361 MLX5_QP_OPTPAR_RRE | 2362 MLX5_QP_OPTPAR_RAE | 2363 MLX5_QP_OPTPAR_RWE | 2364 MLX5_QP_OPTPAR_PM_STATE | 2365 MLX5_QP_OPTPAR_RNR_TIMEOUT, 2366 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2367 MLX5_QP_OPTPAR_RWE | 2368 MLX5_QP_OPTPAR_PM_STATE, 2369 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 2370 }, 2371 }, 2372 [MLX5_QP_STATE_RTS] = { 2373 [MLX5_QP_STATE_RTS] = { 2374 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 2375 MLX5_QP_OPTPAR_RAE | 2376 MLX5_QP_OPTPAR_RWE | 2377 MLX5_QP_OPTPAR_RNR_TIMEOUT | 2378 MLX5_QP_OPTPAR_PM_STATE | 2379 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 2380 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 2381 MLX5_QP_OPTPAR_PM_STATE | 2382 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 2383 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY | 2384 MLX5_QP_OPTPAR_SRQN | 2385 MLX5_QP_OPTPAR_CQN_RCV, 2386 }, 2387 }, 2388 [MLX5_QP_STATE_SQER] = { 2389 [MLX5_QP_STATE_RTS] = { 2390 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 2391 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY, 2392 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE, 2393 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 2394 MLX5_QP_OPTPAR_RWE | 2395 MLX5_QP_OPTPAR_RAE | 2396 MLX5_QP_OPTPAR_RRE, 2397 }, 2398 }, 2399 }; 2400 2401 static int ib_nr_to_mlx5_nr(int ib_mask) 2402 { 2403 switch (ib_mask) { 2404 case IB_QP_STATE: 2405 return 0; 2406 case IB_QP_CUR_STATE: 2407 return 0; 2408 case IB_QP_EN_SQD_ASYNC_NOTIFY: 2409 return 0; 2410 case IB_QP_ACCESS_FLAGS: 2411 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE | 2412 MLX5_QP_OPTPAR_RAE; 2413 case IB_QP_PKEY_INDEX: 2414 return MLX5_QP_OPTPAR_PKEY_INDEX; 2415 case IB_QP_PORT: 2416 return MLX5_QP_OPTPAR_PRI_PORT; 2417 case IB_QP_QKEY: 2418 return MLX5_QP_OPTPAR_Q_KEY; 2419 case IB_QP_AV: 2420 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH | 2421 MLX5_QP_OPTPAR_PRI_PORT; 2422 case IB_QP_PATH_MTU: 2423 return 0; 2424 case IB_QP_TIMEOUT: 2425 return MLX5_QP_OPTPAR_ACK_TIMEOUT; 2426 case IB_QP_RETRY_CNT: 2427 return MLX5_QP_OPTPAR_RETRY_COUNT; 2428 case IB_QP_RNR_RETRY: 2429 return MLX5_QP_OPTPAR_RNR_RETRY; 2430 case IB_QP_RQ_PSN: 2431 return 0; 2432 case IB_QP_MAX_QP_RD_ATOMIC: 2433 return MLX5_QP_OPTPAR_SRA_MAX; 2434 case IB_QP_ALT_PATH: 2435 return MLX5_QP_OPTPAR_ALT_ADDR_PATH; 2436 case IB_QP_MIN_RNR_TIMER: 2437 return MLX5_QP_OPTPAR_RNR_TIMEOUT; 2438 case IB_QP_SQ_PSN: 2439 return 0; 2440 case IB_QP_MAX_DEST_RD_ATOMIC: 2441 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE | 2442 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE; 2443 case IB_QP_PATH_MIG_STATE: 2444 return MLX5_QP_OPTPAR_PM_STATE; 2445 case IB_QP_CAP: 2446 return 0; 2447 case IB_QP_DEST_QPN: 2448 return 0; 2449 } 2450 return 0; 2451 } 2452 2453 static int ib_mask_to_mlx5_opt(int ib_mask) 2454 { 2455 int result = 0; 2456 int i; 2457 2458 for (i = 0; i < 8 * sizeof(int); i++) { 2459 if ((1 << i) & ib_mask) 2460 result |= ib_nr_to_mlx5_nr(1 << i); 2461 } 2462 2463 return result; 2464 } 2465 2466 static int modify_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 2467 struct mlx5_ib_rq *rq, int new_state, 2468 const struct mlx5_modify_raw_qp_param *raw_qp_param) 2469 { 2470 void *in; 2471 void *rqc; 2472 int inlen; 2473 int err; 2474 2475 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 2476 in = kvzalloc(inlen, GFP_KERNEL); 2477 if (!in) 2478 return -ENOMEM; 2479 2480 MLX5_SET(modify_rq_in, in, rq_state, rq->state); 2481 2482 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 2483 MLX5_SET(rqc, rqc, state, new_state); 2484 2485 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) { 2486 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 2487 MLX5_SET64(modify_rq_in, in, modify_bitmask, 2488 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 2489 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id); 2490 } else 2491 pr_info_once("%s: RAW PACKET QP counters are not supported on current FW\n", 2492 dev->ib_dev.name); 2493 } 2494 2495 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen); 2496 if (err) 2497 goto out; 2498 2499 rq->state = new_state; 2500 2501 out: 2502 kvfree(in); 2503 return err; 2504 } 2505 2506 static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev, 2507 struct mlx5_ib_sq *sq, 2508 int new_state, 2509 const struct mlx5_modify_raw_qp_param *raw_qp_param) 2510 { 2511 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp; 2512 u32 old_rate = ibqp->rate_limit; 2513 u32 new_rate = old_rate; 2514 u16 rl_index = 0; 2515 void *in; 2516 void *sqc; 2517 int inlen; 2518 int err; 2519 2520 inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 2521 in = kvzalloc(inlen, GFP_KERNEL); 2522 if (!in) 2523 return -ENOMEM; 2524 2525 MLX5_SET(modify_sq_in, in, sq_state, sq->state); 2526 2527 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 2528 MLX5_SET(sqc, sqc, state, new_state); 2529 2530 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) { 2531 if (new_state != MLX5_SQC_STATE_RDY) 2532 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n", 2533 __func__); 2534 else 2535 new_rate = raw_qp_param->rate_limit; 2536 } 2537 2538 if (old_rate != new_rate) { 2539 if (new_rate) { 2540 err = mlx5_rl_add_rate(dev, new_rate, &rl_index); 2541 if (err) { 2542 pr_err("Failed configuring rate %u: %d\n", 2543 new_rate, err); 2544 goto out; 2545 } 2546 } 2547 2548 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1); 2549 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index); 2550 } 2551 2552 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen); 2553 if (err) { 2554 /* Remove new rate from table if failed */ 2555 if (new_rate && 2556 old_rate != new_rate) 2557 mlx5_rl_remove_rate(dev, new_rate); 2558 goto out; 2559 } 2560 2561 /* Only remove the old rate after new rate was set */ 2562 if ((old_rate && 2563 (old_rate != new_rate)) || 2564 (new_state != MLX5_SQC_STATE_RDY)) 2565 mlx5_rl_remove_rate(dev, old_rate); 2566 2567 ibqp->rate_limit = new_rate; 2568 sq->state = new_state; 2569 2570 out: 2571 kvfree(in); 2572 return err; 2573 } 2574 2575 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2576 const struct mlx5_modify_raw_qp_param *raw_qp_param, 2577 u8 tx_affinity) 2578 { 2579 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 2580 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 2581 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 2582 int modify_rq = !!qp->rq.wqe_cnt; 2583 int modify_sq = !!qp->sq.wqe_cnt; 2584 int rq_state; 2585 int sq_state; 2586 int err; 2587 2588 switch (raw_qp_param->operation) { 2589 case MLX5_CMD_OP_RST2INIT_QP: 2590 rq_state = MLX5_RQC_STATE_RDY; 2591 sq_state = MLX5_SQC_STATE_RDY; 2592 break; 2593 case MLX5_CMD_OP_2ERR_QP: 2594 rq_state = MLX5_RQC_STATE_ERR; 2595 sq_state = MLX5_SQC_STATE_ERR; 2596 break; 2597 case MLX5_CMD_OP_2RST_QP: 2598 rq_state = MLX5_RQC_STATE_RST; 2599 sq_state = MLX5_SQC_STATE_RST; 2600 break; 2601 case MLX5_CMD_OP_RTR2RTS_QP: 2602 case MLX5_CMD_OP_RTS2RTS_QP: 2603 if (raw_qp_param->set_mask == 2604 MLX5_RAW_QP_RATE_LIMIT) { 2605 modify_rq = 0; 2606 sq_state = sq->state; 2607 } else { 2608 return raw_qp_param->set_mask ? -EINVAL : 0; 2609 } 2610 break; 2611 case MLX5_CMD_OP_INIT2INIT_QP: 2612 case MLX5_CMD_OP_INIT2RTR_QP: 2613 if (raw_qp_param->set_mask) 2614 return -EINVAL; 2615 else 2616 return 0; 2617 default: 2618 WARN_ON(1); 2619 return -EINVAL; 2620 } 2621 2622 if (modify_rq) { 2623 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param); 2624 if (err) 2625 return err; 2626 } 2627 2628 if (modify_sq) { 2629 if (tx_affinity) { 2630 err = modify_raw_packet_tx_affinity(dev->mdev, sq, 2631 tx_affinity); 2632 if (err) 2633 return err; 2634 } 2635 2636 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, raw_qp_param); 2637 } 2638 2639 return 0; 2640 } 2641 2642 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp, 2643 const struct ib_qp_attr *attr, int attr_mask, 2644 enum ib_qp_state cur_state, enum ib_qp_state new_state) 2645 { 2646 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = { 2647 [MLX5_QP_STATE_RST] = { 2648 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2649 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2650 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP, 2651 }, 2652 [MLX5_QP_STATE_INIT] = { 2653 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2654 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2655 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP, 2656 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP, 2657 }, 2658 [MLX5_QP_STATE_RTR] = { 2659 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2660 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2661 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP, 2662 }, 2663 [MLX5_QP_STATE_RTS] = { 2664 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2665 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2666 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP, 2667 }, 2668 [MLX5_QP_STATE_SQD] = { 2669 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2670 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2671 }, 2672 [MLX5_QP_STATE_SQER] = { 2673 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2674 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2675 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP, 2676 }, 2677 [MLX5_QP_STATE_ERR] = { 2678 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2679 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2680 } 2681 }; 2682 2683 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2684 struct mlx5_ib_qp *qp = to_mqp(ibqp); 2685 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 2686 struct mlx5_ib_cq *send_cq, *recv_cq; 2687 struct mlx5_qp_context *context; 2688 struct mlx5_ib_pd *pd; 2689 struct mlx5_ib_port *mibport = NULL; 2690 enum mlx5_qp_state mlx5_cur, mlx5_new; 2691 enum mlx5_qp_optpar optpar; 2692 int mlx5_st; 2693 int err; 2694 u16 op; 2695 u8 tx_affinity = 0; 2696 2697 context = kzalloc(sizeof(*context), GFP_KERNEL); 2698 if (!context) 2699 return -ENOMEM; 2700 2701 err = to_mlx5_st(ibqp->qp_type); 2702 if (err < 0) { 2703 mlx5_ib_dbg(dev, "unsupported qp type %d\n", ibqp->qp_type); 2704 goto out; 2705 } 2706 2707 context->flags = cpu_to_be32(err << 16); 2708 2709 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) { 2710 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 2711 } else { 2712 switch (attr->path_mig_state) { 2713 case IB_MIG_MIGRATED: 2714 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 2715 break; 2716 case IB_MIG_REARM: 2717 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11); 2718 break; 2719 case IB_MIG_ARMED: 2720 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11); 2721 break; 2722 } 2723 } 2724 2725 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) { 2726 if ((ibqp->qp_type == IB_QPT_RC) || 2727 (ibqp->qp_type == IB_QPT_UD && 2728 !(qp->flags & MLX5_IB_QP_SQPN_QP1)) || 2729 (ibqp->qp_type == IB_QPT_UC) || 2730 (ibqp->qp_type == IB_QPT_RAW_PACKET) || 2731 (ibqp->qp_type == IB_QPT_XRC_INI) || 2732 (ibqp->qp_type == IB_QPT_XRC_TGT)) { 2733 if (mlx5_lag_is_active(dev->mdev)) { 2734 tx_affinity = (unsigned int)atomic_add_return(1, 2735 &dev->roce.next_port) % 2736 MLX5_MAX_PORTS + 1; 2737 context->flags |= cpu_to_be32(tx_affinity << 24); 2738 } 2739 } 2740 } 2741 2742 if (is_sqp(ibqp->qp_type)) { 2743 context->mtu_msgmax = (IB_MTU_256 << 5) | 8; 2744 } else if ((ibqp->qp_type == IB_QPT_UD && 2745 !(qp->flags & MLX5_IB_QP_UNDERLAY)) || 2746 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) { 2747 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12; 2748 } else if (attr_mask & IB_QP_PATH_MTU) { 2749 if (attr->path_mtu < IB_MTU_256 || 2750 attr->path_mtu > IB_MTU_4096) { 2751 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu); 2752 err = -EINVAL; 2753 goto out; 2754 } 2755 context->mtu_msgmax = (attr->path_mtu << 5) | 2756 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg); 2757 } 2758 2759 if (attr_mask & IB_QP_DEST_QPN) 2760 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num); 2761 2762 if (attr_mask & IB_QP_PKEY_INDEX) 2763 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index); 2764 2765 /* todo implement counter_index functionality */ 2766 2767 if (is_sqp(ibqp->qp_type)) 2768 context->pri_path.port = qp->port; 2769 2770 if (attr_mask & IB_QP_PORT) 2771 context->pri_path.port = attr->port_num; 2772 2773 if (attr_mask & IB_QP_AV) { 2774 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path, 2775 attr_mask & IB_QP_PORT ? attr->port_num : qp->port, 2776 attr_mask, 0, attr, false); 2777 if (err) 2778 goto out; 2779 } 2780 2781 if (attr_mask & IB_QP_TIMEOUT) 2782 context->pri_path.ackto_lt |= attr->timeout << 3; 2783 2784 if (attr_mask & IB_QP_ALT_PATH) { 2785 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr, 2786 &context->alt_path, 2787 attr->alt_port_num, 2788 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT, 2789 0, attr, true); 2790 if (err) 2791 goto out; 2792 } 2793 2794 pd = get_pd(qp); 2795 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 2796 &send_cq, &recv_cq); 2797 2798 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn); 2799 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0; 2800 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0; 2801 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28); 2802 2803 if (attr_mask & IB_QP_RNR_RETRY) 2804 context->params1 |= cpu_to_be32(attr->rnr_retry << 13); 2805 2806 if (attr_mask & IB_QP_RETRY_CNT) 2807 context->params1 |= cpu_to_be32(attr->retry_cnt << 16); 2808 2809 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 2810 if (attr->max_rd_atomic) 2811 context->params1 |= 2812 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21); 2813 } 2814 2815 if (attr_mask & IB_QP_SQ_PSN) 2816 context->next_send_psn = cpu_to_be32(attr->sq_psn); 2817 2818 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 2819 if (attr->max_dest_rd_atomic) 2820 context->params2 |= 2821 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21); 2822 } 2823 2824 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) 2825 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask); 2826 2827 if (attr_mask & IB_QP_MIN_RNR_TIMER) 2828 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24); 2829 2830 if (attr_mask & IB_QP_RQ_PSN) 2831 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn); 2832 2833 if (attr_mask & IB_QP_QKEY) 2834 context->qkey = cpu_to_be32(attr->qkey); 2835 2836 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 2837 context->db_rec_addr = cpu_to_be64(qp->db.dma); 2838 2839 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 2840 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num : 2841 qp->port) - 1; 2842 2843 /* Underlay port should be used - index 0 function per port */ 2844 if (qp->flags & MLX5_IB_QP_UNDERLAY) 2845 port_num = 0; 2846 2847 mibport = &dev->port[port_num]; 2848 context->qp_counter_set_usr_page |= 2849 cpu_to_be32((u32)(mibport->cnts.set_id) << 24); 2850 } 2851 2852 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 2853 context->sq_crq_size |= cpu_to_be16(1 << 4); 2854 2855 if (qp->flags & MLX5_IB_QP_SQPN_QP1) 2856 context->deth_sqpn = cpu_to_be32(1); 2857 2858 mlx5_cur = to_mlx5_state(cur_state); 2859 mlx5_new = to_mlx5_state(new_state); 2860 mlx5_st = to_mlx5_st(ibqp->qp_type); 2861 if (mlx5_st < 0) 2862 goto out; 2863 2864 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE || 2865 !optab[mlx5_cur][mlx5_new]) 2866 goto out; 2867 2868 op = optab[mlx5_cur][mlx5_new]; 2869 optpar = ib_mask_to_mlx5_opt(attr_mask); 2870 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st]; 2871 2872 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 2873 qp->flags & MLX5_IB_QP_UNDERLAY) { 2874 struct mlx5_modify_raw_qp_param raw_qp_param = {}; 2875 2876 raw_qp_param.operation = op; 2877 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 2878 raw_qp_param.rq_q_ctr_id = mibport->cnts.set_id; 2879 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID; 2880 } 2881 2882 if (attr_mask & IB_QP_RATE_LIMIT) { 2883 raw_qp_param.rate_limit = attr->rate_limit; 2884 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT; 2885 } 2886 2887 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity); 2888 } else { 2889 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context, 2890 &base->mqp); 2891 } 2892 2893 if (err) 2894 goto out; 2895 2896 qp->state = new_state; 2897 2898 if (attr_mask & IB_QP_ACCESS_FLAGS) 2899 qp->trans_qp.atomic_rd_en = attr->qp_access_flags; 2900 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 2901 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic; 2902 if (attr_mask & IB_QP_PORT) 2903 qp->port = attr->port_num; 2904 if (attr_mask & IB_QP_ALT_PATH) 2905 qp->trans_qp.alt_port = attr->alt_port_num; 2906 2907 /* 2908 * If we moved a kernel QP to RESET, clean up all old CQ 2909 * entries and reinitialize the QP. 2910 */ 2911 if (new_state == IB_QPS_RESET && !ibqp->uobject) { 2912 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 2913 ibqp->srq ? to_msrq(ibqp->srq) : NULL); 2914 if (send_cq != recv_cq) 2915 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL); 2916 2917 qp->rq.head = 0; 2918 qp->rq.tail = 0; 2919 qp->sq.head = 0; 2920 qp->sq.tail = 0; 2921 qp->sq.cur_post = 0; 2922 qp->sq.last_poll = 0; 2923 qp->db.db[MLX5_RCV_DBR] = 0; 2924 qp->db.db[MLX5_SND_DBR] = 0; 2925 } 2926 2927 out: 2928 kfree(context); 2929 return err; 2930 } 2931 2932 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 2933 int attr_mask, struct ib_udata *udata) 2934 { 2935 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2936 struct mlx5_ib_qp *qp = to_mqp(ibqp); 2937 enum ib_qp_type qp_type; 2938 enum ib_qp_state cur_state, new_state; 2939 int err = -EINVAL; 2940 int port; 2941 enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED; 2942 2943 if (ibqp->rwq_ind_tbl) 2944 return -ENOSYS; 2945 2946 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 2947 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask); 2948 2949 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ? 2950 IB_QPT_GSI : ibqp->qp_type; 2951 2952 mutex_lock(&qp->mutex); 2953 2954 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; 2955 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 2956 2957 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) { 2958 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 2959 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port); 2960 } 2961 2962 if (qp->flags & MLX5_IB_QP_UNDERLAY) { 2963 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) { 2964 mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n", 2965 attr_mask); 2966 goto out; 2967 } 2968 } else if (qp_type != MLX5_IB_QPT_REG_UMR && 2969 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) { 2970 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 2971 cur_state, new_state, ibqp->qp_type, attr_mask); 2972 goto out; 2973 } 2974 2975 if ((attr_mask & IB_QP_PORT) && 2976 (attr->port_num == 0 || 2977 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports))) { 2978 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 2979 attr->port_num, dev->num_ports); 2980 goto out; 2981 } 2982 2983 if (attr_mask & IB_QP_PKEY_INDEX) { 2984 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 2985 if (attr->pkey_index >= 2986 dev->mdev->port_caps[port - 1].pkey_table_len) { 2987 mlx5_ib_dbg(dev, "invalid pkey index %d\n", 2988 attr->pkey_index); 2989 goto out; 2990 } 2991 } 2992 2993 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 2994 attr->max_rd_atomic > 2995 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) { 2996 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n", 2997 attr->max_rd_atomic); 2998 goto out; 2999 } 3000 3001 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 3002 attr->max_dest_rd_atomic > 3003 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) { 3004 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n", 3005 attr->max_dest_rd_atomic); 3006 goto out; 3007 } 3008 3009 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 3010 err = 0; 3011 goto out; 3012 } 3013 3014 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state); 3015 3016 out: 3017 mutex_unlock(&qp->mutex); 3018 return err; 3019 } 3020 3021 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq) 3022 { 3023 struct mlx5_ib_cq *cq; 3024 unsigned cur; 3025 3026 cur = wq->head - wq->tail; 3027 if (likely(cur + nreq < wq->max_post)) 3028 return 0; 3029 3030 cq = to_mcq(ib_cq); 3031 spin_lock(&cq->lock); 3032 cur = wq->head - wq->tail; 3033 spin_unlock(&cq->lock); 3034 3035 return cur + nreq >= wq->max_post; 3036 } 3037 3038 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg, 3039 u64 remote_addr, u32 rkey) 3040 { 3041 rseg->raddr = cpu_to_be64(remote_addr); 3042 rseg->rkey = cpu_to_be32(rkey); 3043 rseg->reserved = 0; 3044 } 3045 3046 static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg, 3047 struct ib_send_wr *wr, void *qend, 3048 struct mlx5_ib_qp *qp, int *size) 3049 { 3050 void *seg = eseg; 3051 3052 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg)); 3053 3054 if (wr->send_flags & IB_SEND_IP_CSUM) 3055 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM | 3056 MLX5_ETH_WQE_L4_CSUM; 3057 3058 seg += sizeof(struct mlx5_wqe_eth_seg); 3059 *size += sizeof(struct mlx5_wqe_eth_seg) / 16; 3060 3061 if (wr->opcode == IB_WR_LSO) { 3062 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr); 3063 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr.start); 3064 u64 left, leftlen, copysz; 3065 void *pdata = ud_wr->header; 3066 3067 left = ud_wr->hlen; 3068 eseg->mss = cpu_to_be16(ud_wr->mss); 3069 eseg->inline_hdr.sz = cpu_to_be16(left); 3070 3071 /* 3072 * check if there is space till the end of queue, if yes, 3073 * copy all in one shot, otherwise copy till the end of queue, 3074 * rollback and than the copy the left 3075 */ 3076 leftlen = qend - (void *)eseg->inline_hdr.start; 3077 copysz = min_t(u64, leftlen, left); 3078 3079 memcpy(seg - size_of_inl_hdr_start, pdata, copysz); 3080 3081 if (likely(copysz > size_of_inl_hdr_start)) { 3082 seg += ALIGN(copysz - size_of_inl_hdr_start, 16); 3083 *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16; 3084 } 3085 3086 if (unlikely(copysz < left)) { /* the last wqe in the queue */ 3087 seg = mlx5_get_send_wqe(qp, 0); 3088 left -= copysz; 3089 pdata += copysz; 3090 memcpy(seg, pdata, left); 3091 seg += ALIGN(left, 16); 3092 *size += ALIGN(left, 16) / 16; 3093 } 3094 } 3095 3096 return seg; 3097 } 3098 3099 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg, 3100 struct ib_send_wr *wr) 3101 { 3102 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av)); 3103 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV); 3104 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey); 3105 } 3106 3107 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg) 3108 { 3109 dseg->byte_count = cpu_to_be32(sg->length); 3110 dseg->lkey = cpu_to_be32(sg->lkey); 3111 dseg->addr = cpu_to_be64(sg->addr); 3112 } 3113 3114 static u64 get_xlt_octo(u64 bytes) 3115 { 3116 return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) / 3117 MLX5_IB_UMR_OCTOWORD; 3118 } 3119 3120 static __be64 frwr_mkey_mask(void) 3121 { 3122 u64 result; 3123 3124 result = MLX5_MKEY_MASK_LEN | 3125 MLX5_MKEY_MASK_PAGE_SIZE | 3126 MLX5_MKEY_MASK_START_ADDR | 3127 MLX5_MKEY_MASK_EN_RINVAL | 3128 MLX5_MKEY_MASK_KEY | 3129 MLX5_MKEY_MASK_LR | 3130 MLX5_MKEY_MASK_LW | 3131 MLX5_MKEY_MASK_RR | 3132 MLX5_MKEY_MASK_RW | 3133 MLX5_MKEY_MASK_A | 3134 MLX5_MKEY_MASK_SMALL_FENCE | 3135 MLX5_MKEY_MASK_FREE; 3136 3137 return cpu_to_be64(result); 3138 } 3139 3140 static __be64 sig_mkey_mask(void) 3141 { 3142 u64 result; 3143 3144 result = MLX5_MKEY_MASK_LEN | 3145 MLX5_MKEY_MASK_PAGE_SIZE | 3146 MLX5_MKEY_MASK_START_ADDR | 3147 MLX5_MKEY_MASK_EN_SIGERR | 3148 MLX5_MKEY_MASK_EN_RINVAL | 3149 MLX5_MKEY_MASK_KEY | 3150 MLX5_MKEY_MASK_LR | 3151 MLX5_MKEY_MASK_LW | 3152 MLX5_MKEY_MASK_RR | 3153 MLX5_MKEY_MASK_RW | 3154 MLX5_MKEY_MASK_SMALL_FENCE | 3155 MLX5_MKEY_MASK_FREE | 3156 MLX5_MKEY_MASK_BSF_EN; 3157 3158 return cpu_to_be64(result); 3159 } 3160 3161 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr, 3162 struct mlx5_ib_mr *mr) 3163 { 3164 int size = mr->ndescs * mr->desc_size; 3165 3166 memset(umr, 0, sizeof(*umr)); 3167 3168 umr->flags = MLX5_UMR_CHECK_NOT_FREE; 3169 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size)); 3170 umr->mkey_mask = frwr_mkey_mask(); 3171 } 3172 3173 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr) 3174 { 3175 memset(umr, 0, sizeof(*umr)); 3176 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE); 3177 umr->flags = MLX5_UMR_INLINE; 3178 } 3179 3180 static __be64 get_umr_enable_mr_mask(void) 3181 { 3182 u64 result; 3183 3184 result = MLX5_MKEY_MASK_KEY | 3185 MLX5_MKEY_MASK_FREE; 3186 3187 return cpu_to_be64(result); 3188 } 3189 3190 static __be64 get_umr_disable_mr_mask(void) 3191 { 3192 u64 result; 3193 3194 result = MLX5_MKEY_MASK_FREE; 3195 3196 return cpu_to_be64(result); 3197 } 3198 3199 static __be64 get_umr_update_translation_mask(void) 3200 { 3201 u64 result; 3202 3203 result = MLX5_MKEY_MASK_LEN | 3204 MLX5_MKEY_MASK_PAGE_SIZE | 3205 MLX5_MKEY_MASK_START_ADDR; 3206 3207 return cpu_to_be64(result); 3208 } 3209 3210 static __be64 get_umr_update_access_mask(int atomic) 3211 { 3212 u64 result; 3213 3214 result = MLX5_MKEY_MASK_LR | 3215 MLX5_MKEY_MASK_LW | 3216 MLX5_MKEY_MASK_RR | 3217 MLX5_MKEY_MASK_RW; 3218 3219 if (atomic) 3220 result |= MLX5_MKEY_MASK_A; 3221 3222 return cpu_to_be64(result); 3223 } 3224 3225 static __be64 get_umr_update_pd_mask(void) 3226 { 3227 u64 result; 3228 3229 result = MLX5_MKEY_MASK_PD; 3230 3231 return cpu_to_be64(result); 3232 } 3233 3234 static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, 3235 struct ib_send_wr *wr, int atomic) 3236 { 3237 struct mlx5_umr_wr *umrwr = umr_wr(wr); 3238 3239 memset(umr, 0, sizeof(*umr)); 3240 3241 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE) 3242 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */ 3243 else 3244 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */ 3245 3246 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size)); 3247 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) { 3248 u64 offset = get_xlt_octo(umrwr->offset); 3249 3250 umr->xlt_offset = cpu_to_be16(offset & 0xffff); 3251 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16); 3252 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN; 3253 } 3254 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION) 3255 umr->mkey_mask |= get_umr_update_translation_mask(); 3256 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) { 3257 umr->mkey_mask |= get_umr_update_access_mask(atomic); 3258 umr->mkey_mask |= get_umr_update_pd_mask(); 3259 } 3260 if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR) 3261 umr->mkey_mask |= get_umr_enable_mr_mask(); 3262 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR) 3263 umr->mkey_mask |= get_umr_disable_mr_mask(); 3264 3265 if (!wr->num_sge) 3266 umr->flags |= MLX5_UMR_INLINE; 3267 } 3268 3269 static u8 get_umr_flags(int acc) 3270 { 3271 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | 3272 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | 3273 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | 3274 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | 3275 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN; 3276 } 3277 3278 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg, 3279 struct mlx5_ib_mr *mr, 3280 u32 key, int access) 3281 { 3282 int ndescs = ALIGN(mr->ndescs, 8) >> 1; 3283 3284 memset(seg, 0, sizeof(*seg)); 3285 3286 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT) 3287 seg->log2_page_size = ilog2(mr->ibmr.page_size); 3288 else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS) 3289 /* KLMs take twice the size of MTTs */ 3290 ndescs *= 2; 3291 3292 seg->flags = get_umr_flags(access) | mr->access_mode; 3293 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00); 3294 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL); 3295 seg->start_addr = cpu_to_be64(mr->ibmr.iova); 3296 seg->len = cpu_to_be64(mr->ibmr.length); 3297 seg->xlt_oct_size = cpu_to_be32(ndescs); 3298 } 3299 3300 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg) 3301 { 3302 memset(seg, 0, sizeof(*seg)); 3303 seg->status = MLX5_MKEY_STATUS_FREE; 3304 } 3305 3306 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr) 3307 { 3308 struct mlx5_umr_wr *umrwr = umr_wr(wr); 3309 3310 memset(seg, 0, sizeof(*seg)); 3311 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR) 3312 seg->status = MLX5_MKEY_STATUS_FREE; 3313 3314 seg->flags = convert_access(umrwr->access_flags); 3315 if (umrwr->pd) 3316 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn); 3317 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION && 3318 !umrwr->length) 3319 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64); 3320 3321 seg->start_addr = cpu_to_be64(umrwr->virt_addr); 3322 seg->len = cpu_to_be64(umrwr->length); 3323 seg->log2_page_size = umrwr->page_shift; 3324 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 | 3325 mlx5_mkey_variant(umrwr->mkey)); 3326 } 3327 3328 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg, 3329 struct mlx5_ib_mr *mr, 3330 struct mlx5_ib_pd *pd) 3331 { 3332 int bcount = mr->desc_size * mr->ndescs; 3333 3334 dseg->addr = cpu_to_be64(mr->desc_map); 3335 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64)); 3336 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey); 3337 } 3338 3339 static __be32 send_ieth(struct ib_send_wr *wr) 3340 { 3341 switch (wr->opcode) { 3342 case IB_WR_SEND_WITH_IMM: 3343 case IB_WR_RDMA_WRITE_WITH_IMM: 3344 return wr->ex.imm_data; 3345 3346 case IB_WR_SEND_WITH_INV: 3347 return cpu_to_be32(wr->ex.invalidate_rkey); 3348 3349 default: 3350 return 0; 3351 } 3352 } 3353 3354 static u8 calc_sig(void *wqe, int size) 3355 { 3356 u8 *p = wqe; 3357 u8 res = 0; 3358 int i; 3359 3360 for (i = 0; i < size; i++) 3361 res ^= p[i]; 3362 3363 return ~res; 3364 } 3365 3366 static u8 wq_sig(void *wqe) 3367 { 3368 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4); 3369 } 3370 3371 static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr, 3372 void *wqe, int *sz) 3373 { 3374 struct mlx5_wqe_inline_seg *seg; 3375 void *qend = qp->sq.qend; 3376 void *addr; 3377 int inl = 0; 3378 int copy; 3379 int len; 3380 int i; 3381 3382 seg = wqe; 3383 wqe += sizeof(*seg); 3384 for (i = 0; i < wr->num_sge; i++) { 3385 addr = (void *)(unsigned long)(wr->sg_list[i].addr); 3386 len = wr->sg_list[i].length; 3387 inl += len; 3388 3389 if (unlikely(inl > qp->max_inline_data)) 3390 return -ENOMEM; 3391 3392 if (unlikely(wqe + len > qend)) { 3393 copy = qend - wqe; 3394 memcpy(wqe, addr, copy); 3395 addr += copy; 3396 len -= copy; 3397 wqe = mlx5_get_send_wqe(qp, 0); 3398 } 3399 memcpy(wqe, addr, len); 3400 wqe += len; 3401 } 3402 3403 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG); 3404 3405 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16; 3406 3407 return 0; 3408 } 3409 3410 static u16 prot_field_size(enum ib_signature_type type) 3411 { 3412 switch (type) { 3413 case IB_SIG_TYPE_T10_DIF: 3414 return MLX5_DIF_SIZE; 3415 default: 3416 return 0; 3417 } 3418 } 3419 3420 static u8 bs_selector(int block_size) 3421 { 3422 switch (block_size) { 3423 case 512: return 0x1; 3424 case 520: return 0x2; 3425 case 4096: return 0x3; 3426 case 4160: return 0x4; 3427 case 1073741824: return 0x5; 3428 default: return 0; 3429 } 3430 } 3431 3432 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain, 3433 struct mlx5_bsf_inl *inl) 3434 { 3435 /* Valid inline section and allow BSF refresh */ 3436 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID | 3437 MLX5_BSF_REFRESH_DIF); 3438 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag); 3439 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag); 3440 /* repeating block */ 3441 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK; 3442 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ? 3443 MLX5_DIF_CRC : MLX5_DIF_IPCS; 3444 3445 if (domain->sig.dif.ref_remap) 3446 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG; 3447 3448 if (domain->sig.dif.app_escape) { 3449 if (domain->sig.dif.ref_escape) 3450 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE; 3451 else 3452 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE; 3453 } 3454 3455 inl->dif_app_bitmask_check = 3456 cpu_to_be16(domain->sig.dif.apptag_check_mask); 3457 } 3458 3459 static int mlx5_set_bsf(struct ib_mr *sig_mr, 3460 struct ib_sig_attrs *sig_attrs, 3461 struct mlx5_bsf *bsf, u32 data_size) 3462 { 3463 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig; 3464 struct mlx5_bsf_basic *basic = &bsf->basic; 3465 struct ib_sig_domain *mem = &sig_attrs->mem; 3466 struct ib_sig_domain *wire = &sig_attrs->wire; 3467 3468 memset(bsf, 0, sizeof(*bsf)); 3469 3470 /* Basic + Extended + Inline */ 3471 basic->bsf_size_sbs = 1 << 7; 3472 /* Input domain check byte mask */ 3473 basic->check_byte_mask = sig_attrs->check_mask; 3474 basic->raw_data_size = cpu_to_be32(data_size); 3475 3476 /* Memory domain */ 3477 switch (sig_attrs->mem.sig_type) { 3478 case IB_SIG_TYPE_NONE: 3479 break; 3480 case IB_SIG_TYPE_T10_DIF: 3481 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval); 3482 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx); 3483 mlx5_fill_inl_bsf(mem, &bsf->m_inl); 3484 break; 3485 default: 3486 return -EINVAL; 3487 } 3488 3489 /* Wire domain */ 3490 switch (sig_attrs->wire.sig_type) { 3491 case IB_SIG_TYPE_NONE: 3492 break; 3493 case IB_SIG_TYPE_T10_DIF: 3494 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval && 3495 mem->sig_type == wire->sig_type) { 3496 /* Same block structure */ 3497 basic->bsf_size_sbs |= 1 << 4; 3498 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type) 3499 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK; 3500 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag) 3501 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK; 3502 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag) 3503 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK; 3504 } else 3505 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval); 3506 3507 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx); 3508 mlx5_fill_inl_bsf(wire, &bsf->w_inl); 3509 break; 3510 default: 3511 return -EINVAL; 3512 } 3513 3514 return 0; 3515 } 3516 3517 static int set_sig_data_segment(struct ib_sig_handover_wr *wr, 3518 struct mlx5_ib_qp *qp, void **seg, int *size) 3519 { 3520 struct ib_sig_attrs *sig_attrs = wr->sig_attrs; 3521 struct ib_mr *sig_mr = wr->sig_mr; 3522 struct mlx5_bsf *bsf; 3523 u32 data_len = wr->wr.sg_list->length; 3524 u32 data_key = wr->wr.sg_list->lkey; 3525 u64 data_va = wr->wr.sg_list->addr; 3526 int ret; 3527 int wqe_size; 3528 3529 if (!wr->prot || 3530 (data_key == wr->prot->lkey && 3531 data_va == wr->prot->addr && 3532 data_len == wr->prot->length)) { 3533 /** 3534 * Source domain doesn't contain signature information 3535 * or data and protection are interleaved in memory. 3536 * So need construct: 3537 * ------------------ 3538 * | data_klm | 3539 * ------------------ 3540 * | BSF | 3541 * ------------------ 3542 **/ 3543 struct mlx5_klm *data_klm = *seg; 3544 3545 data_klm->bcount = cpu_to_be32(data_len); 3546 data_klm->key = cpu_to_be32(data_key); 3547 data_klm->va = cpu_to_be64(data_va); 3548 wqe_size = ALIGN(sizeof(*data_klm), 64); 3549 } else { 3550 /** 3551 * Source domain contains signature information 3552 * So need construct a strided block format: 3553 * --------------------------- 3554 * | stride_block_ctrl | 3555 * --------------------------- 3556 * | data_klm | 3557 * --------------------------- 3558 * | prot_klm | 3559 * --------------------------- 3560 * | BSF | 3561 * --------------------------- 3562 **/ 3563 struct mlx5_stride_block_ctrl_seg *sblock_ctrl; 3564 struct mlx5_stride_block_entry *data_sentry; 3565 struct mlx5_stride_block_entry *prot_sentry; 3566 u32 prot_key = wr->prot->lkey; 3567 u64 prot_va = wr->prot->addr; 3568 u16 block_size = sig_attrs->mem.sig.dif.pi_interval; 3569 int prot_size; 3570 3571 sblock_ctrl = *seg; 3572 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl); 3573 prot_sentry = (void *)data_sentry + sizeof(*data_sentry); 3574 3575 prot_size = prot_field_size(sig_attrs->mem.sig_type); 3576 if (!prot_size) { 3577 pr_err("Bad block size given: %u\n", block_size); 3578 return -EINVAL; 3579 } 3580 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size + 3581 prot_size); 3582 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP); 3583 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size); 3584 sblock_ctrl->num_entries = cpu_to_be16(2); 3585 3586 data_sentry->bcount = cpu_to_be16(block_size); 3587 data_sentry->key = cpu_to_be32(data_key); 3588 data_sentry->va = cpu_to_be64(data_va); 3589 data_sentry->stride = cpu_to_be16(block_size); 3590 3591 prot_sentry->bcount = cpu_to_be16(prot_size); 3592 prot_sentry->key = cpu_to_be32(prot_key); 3593 prot_sentry->va = cpu_to_be64(prot_va); 3594 prot_sentry->stride = cpu_to_be16(prot_size); 3595 3596 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) + 3597 sizeof(*prot_sentry), 64); 3598 } 3599 3600 *seg += wqe_size; 3601 *size += wqe_size / 16; 3602 if (unlikely((*seg == qp->sq.qend))) 3603 *seg = mlx5_get_send_wqe(qp, 0); 3604 3605 bsf = *seg; 3606 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len); 3607 if (ret) 3608 return -EINVAL; 3609 3610 *seg += sizeof(*bsf); 3611 *size += sizeof(*bsf) / 16; 3612 if (unlikely((*seg == qp->sq.qend))) 3613 *seg = mlx5_get_send_wqe(qp, 0); 3614 3615 return 0; 3616 } 3617 3618 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg, 3619 struct ib_sig_handover_wr *wr, u32 size, 3620 u32 length, u32 pdn) 3621 { 3622 struct ib_mr *sig_mr = wr->sig_mr; 3623 u32 sig_key = sig_mr->rkey; 3624 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1; 3625 3626 memset(seg, 0, sizeof(*seg)); 3627 3628 seg->flags = get_umr_flags(wr->access_flags) | 3629 MLX5_MKC_ACCESS_MODE_KLMS; 3630 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00); 3631 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 | 3632 MLX5_MKEY_BSF_EN | pdn); 3633 seg->len = cpu_to_be64(length); 3634 seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size)); 3635 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE); 3636 } 3637 3638 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, 3639 u32 size) 3640 { 3641 memset(umr, 0, sizeof(*umr)); 3642 3643 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE; 3644 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size)); 3645 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE); 3646 umr->mkey_mask = sig_mkey_mask(); 3647 } 3648 3649 3650 static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp, 3651 void **seg, int *size) 3652 { 3653 struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr); 3654 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr); 3655 u32 pdn = get_pd(qp)->pdn; 3656 u32 xlt_size; 3657 int region_len, ret; 3658 3659 if (unlikely(wr->wr.num_sge != 1) || 3660 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) || 3661 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) || 3662 unlikely(!sig_mr->sig->sig_status_checked)) 3663 return -EINVAL; 3664 3665 /* length of the protected region, data + protection */ 3666 region_len = wr->wr.sg_list->length; 3667 if (wr->prot && 3668 (wr->prot->lkey != wr->wr.sg_list->lkey || 3669 wr->prot->addr != wr->wr.sg_list->addr || 3670 wr->prot->length != wr->wr.sg_list->length)) 3671 region_len += wr->prot->length; 3672 3673 /** 3674 * KLM octoword size - if protection was provided 3675 * then we use strided block format (3 octowords), 3676 * else we use single KLM (1 octoword) 3677 **/ 3678 xlt_size = wr->prot ? 0x30 : sizeof(struct mlx5_klm); 3679 3680 set_sig_umr_segment(*seg, xlt_size); 3681 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 3682 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 3683 if (unlikely((*seg == qp->sq.qend))) 3684 *seg = mlx5_get_send_wqe(qp, 0); 3685 3686 set_sig_mkey_segment(*seg, wr, xlt_size, region_len, pdn); 3687 *seg += sizeof(struct mlx5_mkey_seg); 3688 *size += sizeof(struct mlx5_mkey_seg) / 16; 3689 if (unlikely((*seg == qp->sq.qend))) 3690 *seg = mlx5_get_send_wqe(qp, 0); 3691 3692 ret = set_sig_data_segment(wr, qp, seg, size); 3693 if (ret) 3694 return ret; 3695 3696 sig_mr->sig->sig_status_checked = false; 3697 return 0; 3698 } 3699 3700 static int set_psv_wr(struct ib_sig_domain *domain, 3701 u32 psv_idx, void **seg, int *size) 3702 { 3703 struct mlx5_seg_set_psv *psv_seg = *seg; 3704 3705 memset(psv_seg, 0, sizeof(*psv_seg)); 3706 psv_seg->psv_num = cpu_to_be32(psv_idx); 3707 switch (domain->sig_type) { 3708 case IB_SIG_TYPE_NONE: 3709 break; 3710 case IB_SIG_TYPE_T10_DIF: 3711 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 | 3712 domain->sig.dif.app_tag); 3713 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag); 3714 break; 3715 default: 3716 pr_err("Bad signature type (%d) is given.\n", 3717 domain->sig_type); 3718 return -EINVAL; 3719 } 3720 3721 *seg += sizeof(*psv_seg); 3722 *size += sizeof(*psv_seg) / 16; 3723 3724 return 0; 3725 } 3726 3727 static int set_reg_wr(struct mlx5_ib_qp *qp, 3728 struct ib_reg_wr *wr, 3729 void **seg, int *size) 3730 { 3731 struct mlx5_ib_mr *mr = to_mmr(wr->mr); 3732 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd); 3733 3734 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) { 3735 mlx5_ib_warn(to_mdev(qp->ibqp.device), 3736 "Invalid IB_SEND_INLINE send flag\n"); 3737 return -EINVAL; 3738 } 3739 3740 set_reg_umr_seg(*seg, mr); 3741 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 3742 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 3743 if (unlikely((*seg == qp->sq.qend))) 3744 *seg = mlx5_get_send_wqe(qp, 0); 3745 3746 set_reg_mkey_seg(*seg, mr, wr->key, wr->access); 3747 *seg += sizeof(struct mlx5_mkey_seg); 3748 *size += sizeof(struct mlx5_mkey_seg) / 16; 3749 if (unlikely((*seg == qp->sq.qend))) 3750 *seg = mlx5_get_send_wqe(qp, 0); 3751 3752 set_reg_data_seg(*seg, mr, pd); 3753 *seg += sizeof(struct mlx5_wqe_data_seg); 3754 *size += (sizeof(struct mlx5_wqe_data_seg) / 16); 3755 3756 return 0; 3757 } 3758 3759 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size) 3760 { 3761 set_linv_umr_seg(*seg); 3762 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 3763 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 3764 if (unlikely((*seg == qp->sq.qend))) 3765 *seg = mlx5_get_send_wqe(qp, 0); 3766 set_linv_mkey_seg(*seg); 3767 *seg += sizeof(struct mlx5_mkey_seg); 3768 *size += sizeof(struct mlx5_mkey_seg) / 16; 3769 if (unlikely((*seg == qp->sq.qend))) 3770 *seg = mlx5_get_send_wqe(qp, 0); 3771 } 3772 3773 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16) 3774 { 3775 __be32 *p = NULL; 3776 int tidx = idx; 3777 int i, j; 3778 3779 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx)); 3780 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) { 3781 if ((i & 0xf) == 0) { 3782 void *buf = mlx5_get_send_wqe(qp, tidx); 3783 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1); 3784 p = buf; 3785 j = 0; 3786 } 3787 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]), 3788 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]), 3789 be32_to_cpu(p[j + 3])); 3790 } 3791 } 3792 3793 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg, 3794 struct mlx5_wqe_ctrl_seg **ctrl, 3795 struct ib_send_wr *wr, unsigned *idx, 3796 int *size, int nreq) 3797 { 3798 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq))) 3799 return -ENOMEM; 3800 3801 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1); 3802 *seg = mlx5_get_send_wqe(qp, *idx); 3803 *ctrl = *seg; 3804 *(uint32_t *)(*seg + 8) = 0; 3805 (*ctrl)->imm = send_ieth(wr); 3806 (*ctrl)->fm_ce_se = qp->sq_signal_bits | 3807 (wr->send_flags & IB_SEND_SIGNALED ? 3808 MLX5_WQE_CTRL_CQ_UPDATE : 0) | 3809 (wr->send_flags & IB_SEND_SOLICITED ? 3810 MLX5_WQE_CTRL_SOLICITED : 0); 3811 3812 *seg += sizeof(**ctrl); 3813 *size = sizeof(**ctrl) / 16; 3814 3815 return 0; 3816 } 3817 3818 static void finish_wqe(struct mlx5_ib_qp *qp, 3819 struct mlx5_wqe_ctrl_seg *ctrl, 3820 u8 size, unsigned idx, u64 wr_id, 3821 int nreq, u8 fence, u32 mlx5_opcode) 3822 { 3823 u8 opmod = 0; 3824 3825 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) | 3826 mlx5_opcode | ((u32)opmod << 24)); 3827 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8)); 3828 ctrl->fm_ce_se |= fence; 3829 if (unlikely(qp->wq_sig)) 3830 ctrl->signature = wq_sig(ctrl); 3831 3832 qp->sq.wrid[idx] = wr_id; 3833 qp->sq.w_list[idx].opcode = mlx5_opcode; 3834 qp->sq.wqe_head[idx] = qp->sq.head + nreq; 3835 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB); 3836 qp->sq.w_list[idx].next = qp->sq.cur_post; 3837 } 3838 3839 3840 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 3841 struct ib_send_wr **bad_wr) 3842 { 3843 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */ 3844 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3845 struct mlx5_core_dev *mdev = dev->mdev; 3846 struct mlx5_ib_qp *qp; 3847 struct mlx5_ib_mr *mr; 3848 struct mlx5_wqe_data_seg *dpseg; 3849 struct mlx5_wqe_xrc_seg *xrc; 3850 struct mlx5_bf *bf; 3851 int uninitialized_var(size); 3852 void *qend; 3853 unsigned long flags; 3854 unsigned idx; 3855 int err = 0; 3856 int inl = 0; 3857 int num_sge; 3858 void *seg; 3859 int nreq; 3860 int i; 3861 u8 next_fence = 0; 3862 u8 fence; 3863 3864 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 3865 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr); 3866 3867 qp = to_mqp(ibqp); 3868 bf = &qp->bf; 3869 qend = qp->sq.qend; 3870 3871 spin_lock_irqsave(&qp->sq.lock, flags); 3872 3873 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 3874 err = -EIO; 3875 *bad_wr = wr; 3876 nreq = 0; 3877 goto out; 3878 } 3879 3880 for (nreq = 0; wr; nreq++, wr = wr->next) { 3881 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) { 3882 mlx5_ib_warn(dev, "\n"); 3883 err = -EINVAL; 3884 *bad_wr = wr; 3885 goto out; 3886 } 3887 3888 num_sge = wr->num_sge; 3889 if (unlikely(num_sge > qp->sq.max_gs)) { 3890 mlx5_ib_warn(dev, "\n"); 3891 err = -EINVAL; 3892 *bad_wr = wr; 3893 goto out; 3894 } 3895 3896 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq); 3897 if (err) { 3898 mlx5_ib_warn(dev, "\n"); 3899 err = -ENOMEM; 3900 *bad_wr = wr; 3901 goto out; 3902 } 3903 3904 if (wr->opcode == IB_WR_LOCAL_INV || 3905 wr->opcode == IB_WR_REG_MR) { 3906 fence = dev->umr_fence; 3907 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 3908 } else if (wr->send_flags & IB_SEND_FENCE) { 3909 if (qp->next_fence) 3910 fence = MLX5_FENCE_MODE_SMALL_AND_FENCE; 3911 else 3912 fence = MLX5_FENCE_MODE_FENCE; 3913 } else { 3914 fence = qp->next_fence; 3915 } 3916 3917 switch (ibqp->qp_type) { 3918 case IB_QPT_XRC_INI: 3919 xrc = seg; 3920 seg += sizeof(*xrc); 3921 size += sizeof(*xrc) / 16; 3922 /* fall through */ 3923 case IB_QPT_RC: 3924 switch (wr->opcode) { 3925 case IB_WR_RDMA_READ: 3926 case IB_WR_RDMA_WRITE: 3927 case IB_WR_RDMA_WRITE_WITH_IMM: 3928 set_raddr_seg(seg, rdma_wr(wr)->remote_addr, 3929 rdma_wr(wr)->rkey); 3930 seg += sizeof(struct mlx5_wqe_raddr_seg); 3931 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 3932 break; 3933 3934 case IB_WR_ATOMIC_CMP_AND_SWP: 3935 case IB_WR_ATOMIC_FETCH_AND_ADD: 3936 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP: 3937 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n"); 3938 err = -ENOSYS; 3939 *bad_wr = wr; 3940 goto out; 3941 3942 case IB_WR_LOCAL_INV: 3943 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV; 3944 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey); 3945 set_linv_wr(qp, &seg, &size); 3946 num_sge = 0; 3947 break; 3948 3949 case IB_WR_REG_MR: 3950 qp->sq.wr_data[idx] = IB_WR_REG_MR; 3951 ctrl->imm = cpu_to_be32(reg_wr(wr)->key); 3952 err = set_reg_wr(qp, reg_wr(wr), &seg, &size); 3953 if (err) { 3954 *bad_wr = wr; 3955 goto out; 3956 } 3957 num_sge = 0; 3958 break; 3959 3960 case IB_WR_REG_SIG_MR: 3961 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR; 3962 mr = to_mmr(sig_handover_wr(wr)->sig_mr); 3963 3964 ctrl->imm = cpu_to_be32(mr->ibmr.rkey); 3965 err = set_sig_umr_wr(wr, qp, &seg, &size); 3966 if (err) { 3967 mlx5_ib_warn(dev, "\n"); 3968 *bad_wr = wr; 3969 goto out; 3970 } 3971 3972 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, 3973 fence, MLX5_OPCODE_UMR); 3974 /* 3975 * SET_PSV WQEs are not signaled and solicited 3976 * on error 3977 */ 3978 wr->send_flags &= ~IB_SEND_SIGNALED; 3979 wr->send_flags |= IB_SEND_SOLICITED; 3980 err = begin_wqe(qp, &seg, &ctrl, wr, 3981 &idx, &size, nreq); 3982 if (err) { 3983 mlx5_ib_warn(dev, "\n"); 3984 err = -ENOMEM; 3985 *bad_wr = wr; 3986 goto out; 3987 } 3988 3989 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem, 3990 mr->sig->psv_memory.psv_idx, &seg, 3991 &size); 3992 if (err) { 3993 mlx5_ib_warn(dev, "\n"); 3994 *bad_wr = wr; 3995 goto out; 3996 } 3997 3998 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, 3999 fence, MLX5_OPCODE_SET_PSV); 4000 err = begin_wqe(qp, &seg, &ctrl, wr, 4001 &idx, &size, nreq); 4002 if (err) { 4003 mlx5_ib_warn(dev, "\n"); 4004 err = -ENOMEM; 4005 *bad_wr = wr; 4006 goto out; 4007 } 4008 4009 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire, 4010 mr->sig->psv_wire.psv_idx, &seg, 4011 &size); 4012 if (err) { 4013 mlx5_ib_warn(dev, "\n"); 4014 *bad_wr = wr; 4015 goto out; 4016 } 4017 4018 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, 4019 fence, MLX5_OPCODE_SET_PSV); 4020 qp->next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 4021 num_sge = 0; 4022 goto skip_psv; 4023 4024 default: 4025 break; 4026 } 4027 break; 4028 4029 case IB_QPT_UC: 4030 switch (wr->opcode) { 4031 case IB_WR_RDMA_WRITE: 4032 case IB_WR_RDMA_WRITE_WITH_IMM: 4033 set_raddr_seg(seg, rdma_wr(wr)->remote_addr, 4034 rdma_wr(wr)->rkey); 4035 seg += sizeof(struct mlx5_wqe_raddr_seg); 4036 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 4037 break; 4038 4039 default: 4040 break; 4041 } 4042 break; 4043 4044 case IB_QPT_SMI: 4045 if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) { 4046 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n"); 4047 err = -EPERM; 4048 *bad_wr = wr; 4049 goto out; 4050 } 4051 case MLX5_IB_QPT_HW_GSI: 4052 set_datagram_seg(seg, wr); 4053 seg += sizeof(struct mlx5_wqe_datagram_seg); 4054 size += sizeof(struct mlx5_wqe_datagram_seg) / 16; 4055 if (unlikely((seg == qend))) 4056 seg = mlx5_get_send_wqe(qp, 0); 4057 break; 4058 case IB_QPT_UD: 4059 set_datagram_seg(seg, wr); 4060 seg += sizeof(struct mlx5_wqe_datagram_seg); 4061 size += sizeof(struct mlx5_wqe_datagram_seg) / 16; 4062 4063 if (unlikely((seg == qend))) 4064 seg = mlx5_get_send_wqe(qp, 0); 4065 4066 /* handle qp that supports ud offload */ 4067 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) { 4068 struct mlx5_wqe_eth_pad *pad; 4069 4070 pad = seg; 4071 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad)); 4072 seg += sizeof(struct mlx5_wqe_eth_pad); 4073 size += sizeof(struct mlx5_wqe_eth_pad) / 16; 4074 4075 seg = set_eth_seg(seg, wr, qend, qp, &size); 4076 4077 if (unlikely((seg == qend))) 4078 seg = mlx5_get_send_wqe(qp, 0); 4079 } 4080 break; 4081 case MLX5_IB_QPT_REG_UMR: 4082 if (wr->opcode != MLX5_IB_WR_UMR) { 4083 err = -EINVAL; 4084 mlx5_ib_warn(dev, "bad opcode\n"); 4085 goto out; 4086 } 4087 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR; 4088 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey); 4089 set_reg_umr_segment(seg, wr, !!(MLX5_CAP_GEN(mdev, atomic))); 4090 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 4091 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 4092 if (unlikely((seg == qend))) 4093 seg = mlx5_get_send_wqe(qp, 0); 4094 set_reg_mkey_segment(seg, wr); 4095 seg += sizeof(struct mlx5_mkey_seg); 4096 size += sizeof(struct mlx5_mkey_seg) / 16; 4097 if (unlikely((seg == qend))) 4098 seg = mlx5_get_send_wqe(qp, 0); 4099 break; 4100 4101 default: 4102 break; 4103 } 4104 4105 if (wr->send_flags & IB_SEND_INLINE && num_sge) { 4106 int uninitialized_var(sz); 4107 4108 err = set_data_inl_seg(qp, wr, seg, &sz); 4109 if (unlikely(err)) { 4110 mlx5_ib_warn(dev, "\n"); 4111 *bad_wr = wr; 4112 goto out; 4113 } 4114 inl = 1; 4115 size += sz; 4116 } else { 4117 dpseg = seg; 4118 for (i = 0; i < num_sge; i++) { 4119 if (unlikely(dpseg == qend)) { 4120 seg = mlx5_get_send_wqe(qp, 0); 4121 dpseg = seg; 4122 } 4123 if (likely(wr->sg_list[i].length)) { 4124 set_data_ptr_seg(dpseg, wr->sg_list + i); 4125 size += sizeof(struct mlx5_wqe_data_seg) / 16; 4126 dpseg++; 4127 } 4128 } 4129 } 4130 4131 qp->next_fence = next_fence; 4132 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, fence, 4133 mlx5_ib_opcode[wr->opcode]); 4134 skip_psv: 4135 if (0) 4136 dump_wqe(qp, idx, size); 4137 } 4138 4139 out: 4140 if (likely(nreq)) { 4141 qp->sq.head += nreq; 4142 4143 /* Make sure that descriptors are written before 4144 * updating doorbell record and ringing the doorbell 4145 */ 4146 wmb(); 4147 4148 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post); 4149 4150 /* Make sure doorbell record is visible to the HCA before 4151 * we hit doorbell */ 4152 wmb(); 4153 4154 /* currently we support only regular doorbells */ 4155 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset, NULL); 4156 /* Make sure doorbells don't leak out of SQ spinlock 4157 * and reach the HCA out of order. 4158 */ 4159 mmiowb(); 4160 bf->offset ^= bf->buf_size; 4161 } 4162 4163 spin_unlock_irqrestore(&qp->sq.lock, flags); 4164 4165 return err; 4166 } 4167 4168 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size) 4169 { 4170 sig->signature = calc_sig(sig, size); 4171 } 4172 4173 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, 4174 struct ib_recv_wr **bad_wr) 4175 { 4176 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4177 struct mlx5_wqe_data_seg *scat; 4178 struct mlx5_rwqe_sig *sig; 4179 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4180 struct mlx5_core_dev *mdev = dev->mdev; 4181 unsigned long flags; 4182 int err = 0; 4183 int nreq; 4184 int ind; 4185 int i; 4186 4187 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 4188 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr); 4189 4190 spin_lock_irqsave(&qp->rq.lock, flags); 4191 4192 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 4193 err = -EIO; 4194 *bad_wr = wr; 4195 nreq = 0; 4196 goto out; 4197 } 4198 4199 ind = qp->rq.head & (qp->rq.wqe_cnt - 1); 4200 4201 for (nreq = 0; wr; nreq++, wr = wr->next) { 4202 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) { 4203 err = -ENOMEM; 4204 *bad_wr = wr; 4205 goto out; 4206 } 4207 4208 if (unlikely(wr->num_sge > qp->rq.max_gs)) { 4209 err = -EINVAL; 4210 *bad_wr = wr; 4211 goto out; 4212 } 4213 4214 scat = get_recv_wqe(qp, ind); 4215 if (qp->wq_sig) 4216 scat++; 4217 4218 for (i = 0; i < wr->num_sge; i++) 4219 set_data_ptr_seg(scat + i, wr->sg_list + i); 4220 4221 if (i < qp->rq.max_gs) { 4222 scat[i].byte_count = 0; 4223 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY); 4224 scat[i].addr = 0; 4225 } 4226 4227 if (qp->wq_sig) { 4228 sig = (struct mlx5_rwqe_sig *)scat; 4229 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2); 4230 } 4231 4232 qp->rq.wrid[ind] = wr->wr_id; 4233 4234 ind = (ind + 1) & (qp->rq.wqe_cnt - 1); 4235 } 4236 4237 out: 4238 if (likely(nreq)) { 4239 qp->rq.head += nreq; 4240 4241 /* Make sure that descriptors are written before 4242 * doorbell record. 4243 */ 4244 wmb(); 4245 4246 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff); 4247 } 4248 4249 spin_unlock_irqrestore(&qp->rq.lock, flags); 4250 4251 return err; 4252 } 4253 4254 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state) 4255 { 4256 switch (mlx5_state) { 4257 case MLX5_QP_STATE_RST: return IB_QPS_RESET; 4258 case MLX5_QP_STATE_INIT: return IB_QPS_INIT; 4259 case MLX5_QP_STATE_RTR: return IB_QPS_RTR; 4260 case MLX5_QP_STATE_RTS: return IB_QPS_RTS; 4261 case MLX5_QP_STATE_SQ_DRAINING: 4262 case MLX5_QP_STATE_SQD: return IB_QPS_SQD; 4263 case MLX5_QP_STATE_SQER: return IB_QPS_SQE; 4264 case MLX5_QP_STATE_ERR: return IB_QPS_ERR; 4265 default: return -1; 4266 } 4267 } 4268 4269 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state) 4270 { 4271 switch (mlx5_mig_state) { 4272 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED; 4273 case MLX5_QP_PM_REARM: return IB_MIG_REARM; 4274 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED; 4275 default: return -1; 4276 } 4277 } 4278 4279 static int to_ib_qp_access_flags(int mlx5_flags) 4280 { 4281 int ib_flags = 0; 4282 4283 if (mlx5_flags & MLX5_QP_BIT_RRE) 4284 ib_flags |= IB_ACCESS_REMOTE_READ; 4285 if (mlx5_flags & MLX5_QP_BIT_RWE) 4286 ib_flags |= IB_ACCESS_REMOTE_WRITE; 4287 if (mlx5_flags & MLX5_QP_BIT_RAE) 4288 ib_flags |= IB_ACCESS_REMOTE_ATOMIC; 4289 4290 return ib_flags; 4291 } 4292 4293 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev, 4294 struct rdma_ah_attr *ah_attr, 4295 struct mlx5_qp_path *path) 4296 { 4297 struct mlx5_core_dev *dev = ibdev->mdev; 4298 4299 memset(ah_attr, 0, sizeof(*ah_attr)); 4300 4301 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port); 4302 rdma_ah_set_port_num(ah_attr, path->port); 4303 if (rdma_ah_get_port_num(ah_attr) == 0 || 4304 rdma_ah_get_port_num(ah_attr) > MLX5_CAP_GEN(dev, num_ports)) 4305 return; 4306 4307 rdma_ah_set_port_num(ah_attr, path->port); 4308 rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf); 4309 4310 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid)); 4311 rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f); 4312 rdma_ah_set_static_rate(ah_attr, 4313 path->static_rate ? path->static_rate - 5 : 0); 4314 if (path->grh_mlid & (1 << 7)) { 4315 u32 tc_fl = be32_to_cpu(path->tclass_flowlabel); 4316 4317 rdma_ah_set_grh(ah_attr, NULL, 4318 tc_fl & 0xfffff, 4319 path->mgid_index, 4320 path->hop_limit, 4321 (tc_fl >> 20) & 0xff); 4322 rdma_ah_set_dgid_raw(ah_attr, path->rgid); 4323 } 4324 } 4325 4326 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev, 4327 struct mlx5_ib_sq *sq, 4328 u8 *sq_state) 4329 { 4330 void *out; 4331 void *sqc; 4332 int inlen; 4333 int err; 4334 4335 inlen = MLX5_ST_SZ_BYTES(query_sq_out); 4336 out = kvzalloc(inlen, GFP_KERNEL); 4337 if (!out) 4338 return -ENOMEM; 4339 4340 err = mlx5_core_query_sq(dev->mdev, sq->base.mqp.qpn, out); 4341 if (err) 4342 goto out; 4343 4344 sqc = MLX5_ADDR_OF(query_sq_out, out, sq_context); 4345 *sq_state = MLX5_GET(sqc, sqc, state); 4346 sq->state = *sq_state; 4347 4348 out: 4349 kvfree(out); 4350 return err; 4351 } 4352 4353 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev, 4354 struct mlx5_ib_rq *rq, 4355 u8 *rq_state) 4356 { 4357 void *out; 4358 void *rqc; 4359 int inlen; 4360 int err; 4361 4362 inlen = MLX5_ST_SZ_BYTES(query_rq_out); 4363 out = kvzalloc(inlen, GFP_KERNEL); 4364 if (!out) 4365 return -ENOMEM; 4366 4367 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out); 4368 if (err) 4369 goto out; 4370 4371 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context); 4372 *rq_state = MLX5_GET(rqc, rqc, state); 4373 rq->state = *rq_state; 4374 4375 out: 4376 kvfree(out); 4377 return err; 4378 } 4379 4380 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state, 4381 struct mlx5_ib_qp *qp, u8 *qp_state) 4382 { 4383 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = { 4384 [MLX5_RQC_STATE_RST] = { 4385 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 4386 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4387 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD, 4388 [MLX5_SQ_STATE_NA] = IB_QPS_RESET, 4389 }, 4390 [MLX5_RQC_STATE_RDY] = { 4391 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 4392 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4393 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE, 4394 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE, 4395 }, 4396 [MLX5_RQC_STATE_ERR] = { 4397 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 4398 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4399 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR, 4400 [MLX5_SQ_STATE_NA] = IB_QPS_ERR, 4401 }, 4402 [MLX5_RQ_STATE_NA] = { 4403 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 4404 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4405 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE, 4406 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD, 4407 }, 4408 }; 4409 4410 *qp_state = sqrq_trans[rq_state][sq_state]; 4411 4412 if (*qp_state == MLX5_QP_STATE_BAD) { 4413 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x", 4414 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state, 4415 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state); 4416 return -EINVAL; 4417 } 4418 4419 if (*qp_state == MLX5_QP_STATE) 4420 *qp_state = qp->state; 4421 4422 return 0; 4423 } 4424 4425 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev, 4426 struct mlx5_ib_qp *qp, 4427 u8 *raw_packet_qp_state) 4428 { 4429 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 4430 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 4431 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 4432 int err; 4433 u8 sq_state = MLX5_SQ_STATE_NA; 4434 u8 rq_state = MLX5_RQ_STATE_NA; 4435 4436 if (qp->sq.wqe_cnt) { 4437 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state); 4438 if (err) 4439 return err; 4440 } 4441 4442 if (qp->rq.wqe_cnt) { 4443 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state); 4444 if (err) 4445 return err; 4446 } 4447 4448 return sqrq_state_to_qp_state(sq_state, rq_state, qp, 4449 raw_packet_qp_state); 4450 } 4451 4452 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 4453 struct ib_qp_attr *qp_attr) 4454 { 4455 int outlen = MLX5_ST_SZ_BYTES(query_qp_out); 4456 struct mlx5_qp_context *context; 4457 int mlx5_state; 4458 u32 *outb; 4459 int err = 0; 4460 4461 outb = kzalloc(outlen, GFP_KERNEL); 4462 if (!outb) 4463 return -ENOMEM; 4464 4465 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb, 4466 outlen); 4467 if (err) 4468 goto out; 4469 4470 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */ 4471 context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc); 4472 4473 mlx5_state = be32_to_cpu(context->flags) >> 28; 4474 4475 qp->state = to_ib_qp_state(mlx5_state); 4476 qp_attr->path_mtu = context->mtu_msgmax >> 5; 4477 qp_attr->path_mig_state = 4478 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3); 4479 qp_attr->qkey = be32_to_cpu(context->qkey); 4480 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff; 4481 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff; 4482 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff; 4483 qp_attr->qp_access_flags = 4484 to_ib_qp_access_flags(be32_to_cpu(context->params2)); 4485 4486 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) { 4487 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path); 4488 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path); 4489 qp_attr->alt_pkey_index = 4490 be16_to_cpu(context->alt_path.pkey_index); 4491 qp_attr->alt_port_num = 4492 rdma_ah_get_port_num(&qp_attr->alt_ah_attr); 4493 } 4494 4495 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index); 4496 qp_attr->port_num = context->pri_path.port; 4497 4498 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */ 4499 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING; 4500 4501 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7); 4502 4503 qp_attr->max_dest_rd_atomic = 4504 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7); 4505 qp_attr->min_rnr_timer = 4506 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f; 4507 qp_attr->timeout = context->pri_path.ackto_lt >> 3; 4508 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7; 4509 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7; 4510 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3; 4511 4512 out: 4513 kfree(outb); 4514 return err; 4515 } 4516 4517 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 4518 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 4519 { 4520 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4521 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4522 int err = 0; 4523 u8 raw_packet_qp_state; 4524 4525 if (ibqp->rwq_ind_tbl) 4526 return -ENOSYS; 4527 4528 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 4529 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask, 4530 qp_init_attr); 4531 4532 /* Not all of output fields are applicable, make sure to zero them */ 4533 memset(qp_init_attr, 0, sizeof(*qp_init_attr)); 4534 memset(qp_attr, 0, sizeof(*qp_attr)); 4535 4536 mutex_lock(&qp->mutex); 4537 4538 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 4539 qp->flags & MLX5_IB_QP_UNDERLAY) { 4540 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state); 4541 if (err) 4542 goto out; 4543 qp->state = raw_packet_qp_state; 4544 qp_attr->port_num = 1; 4545 } else { 4546 err = query_qp_attr(dev, qp, qp_attr); 4547 if (err) 4548 goto out; 4549 } 4550 4551 qp_attr->qp_state = qp->state; 4552 qp_attr->cur_qp_state = qp_attr->qp_state; 4553 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; 4554 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 4555 4556 if (!ibqp->uobject) { 4557 qp_attr->cap.max_send_wr = qp->sq.max_post; 4558 qp_attr->cap.max_send_sge = qp->sq.max_gs; 4559 qp_init_attr->qp_context = ibqp->qp_context; 4560 } else { 4561 qp_attr->cap.max_send_wr = 0; 4562 qp_attr->cap.max_send_sge = 0; 4563 } 4564 4565 qp_init_attr->qp_type = ibqp->qp_type; 4566 qp_init_attr->recv_cq = ibqp->recv_cq; 4567 qp_init_attr->send_cq = ibqp->send_cq; 4568 qp_init_attr->srq = ibqp->srq; 4569 qp_attr->cap.max_inline_data = qp->max_inline_data; 4570 4571 qp_init_attr->cap = qp_attr->cap; 4572 4573 qp_init_attr->create_flags = 0; 4574 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 4575 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK; 4576 4577 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 4578 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL; 4579 if (qp->flags & MLX5_IB_QP_MANAGED_SEND) 4580 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND; 4581 if (qp->flags & MLX5_IB_QP_MANAGED_RECV) 4582 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV; 4583 if (qp->flags & MLX5_IB_QP_SQPN_QP1) 4584 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1(); 4585 4586 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ? 4587 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; 4588 4589 out: 4590 mutex_unlock(&qp->mutex); 4591 return err; 4592 } 4593 4594 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, 4595 struct ib_ucontext *context, 4596 struct ib_udata *udata) 4597 { 4598 struct mlx5_ib_dev *dev = to_mdev(ibdev); 4599 struct mlx5_ib_xrcd *xrcd; 4600 int err; 4601 4602 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 4603 return ERR_PTR(-ENOSYS); 4604 4605 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL); 4606 if (!xrcd) 4607 return ERR_PTR(-ENOMEM); 4608 4609 err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn); 4610 if (err) { 4611 kfree(xrcd); 4612 return ERR_PTR(-ENOMEM); 4613 } 4614 4615 return &xrcd->ibxrcd; 4616 } 4617 4618 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd) 4619 { 4620 struct mlx5_ib_dev *dev = to_mdev(xrcd->device); 4621 u32 xrcdn = to_mxrcd(xrcd)->xrcdn; 4622 int err; 4623 4624 err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn); 4625 if (err) { 4626 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn); 4627 return err; 4628 } 4629 4630 kfree(xrcd); 4631 4632 return 0; 4633 } 4634 4635 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type) 4636 { 4637 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp); 4638 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device); 4639 struct ib_event event; 4640 4641 if (rwq->ibwq.event_handler) { 4642 event.device = rwq->ibwq.device; 4643 event.element.wq = &rwq->ibwq; 4644 switch (type) { 4645 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 4646 event.event = IB_EVENT_WQ_FATAL; 4647 break; 4648 default: 4649 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn); 4650 return; 4651 } 4652 4653 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context); 4654 } 4655 } 4656 4657 static int set_delay_drop(struct mlx5_ib_dev *dev) 4658 { 4659 int err = 0; 4660 4661 mutex_lock(&dev->delay_drop.lock); 4662 if (dev->delay_drop.activate) 4663 goto out; 4664 4665 err = mlx5_core_set_delay_drop(dev->mdev, dev->delay_drop.timeout); 4666 if (err) 4667 goto out; 4668 4669 dev->delay_drop.activate = true; 4670 out: 4671 mutex_unlock(&dev->delay_drop.lock); 4672 4673 if (!err) 4674 atomic_inc(&dev->delay_drop.rqs_cnt); 4675 return err; 4676 } 4677 4678 static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd, 4679 struct ib_wq_init_attr *init_attr) 4680 { 4681 struct mlx5_ib_dev *dev; 4682 int has_net_offloads; 4683 __be64 *rq_pas0; 4684 void *in; 4685 void *rqc; 4686 void *wq; 4687 int inlen; 4688 int err; 4689 4690 dev = to_mdev(pd->device); 4691 4692 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas; 4693 in = kvzalloc(inlen, GFP_KERNEL); 4694 if (!in) 4695 return -ENOMEM; 4696 4697 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 4698 MLX5_SET(rqc, rqc, mem_rq_type, 4699 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 4700 MLX5_SET(rqc, rqc, user_index, rwq->user_index); 4701 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn); 4702 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 4703 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 4704 wq = MLX5_ADDR_OF(rqc, rqc, wq); 4705 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 4706 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 4707 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride); 4708 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size); 4709 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn); 4710 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset); 4711 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size); 4712 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig); 4713 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma); 4714 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads); 4715 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) { 4716 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) { 4717 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n"); 4718 err = -EOPNOTSUPP; 4719 goto out; 4720 } 4721 } else { 4722 MLX5_SET(rqc, rqc, vsd, 1); 4723 } 4724 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) { 4725 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) { 4726 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n"); 4727 err = -EOPNOTSUPP; 4728 goto out; 4729 } 4730 MLX5_SET(rqc, rqc, scatter_fcs, 1); 4731 } 4732 if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { 4733 if (!(dev->ib_dev.attrs.raw_packet_caps & 4734 IB_RAW_PACKET_CAP_DELAY_DROP)) { 4735 mlx5_ib_dbg(dev, "Delay drop is not supported\n"); 4736 err = -EOPNOTSUPP; 4737 goto out; 4738 } 4739 MLX5_SET(rqc, rqc, delay_drop_en, 1); 4740 } 4741 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 4742 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0); 4743 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp); 4744 if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { 4745 err = set_delay_drop(dev); 4746 if (err) { 4747 mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n", 4748 err); 4749 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); 4750 } else { 4751 rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP; 4752 } 4753 } 4754 out: 4755 kvfree(in); 4756 return err; 4757 } 4758 4759 static int set_user_rq_size(struct mlx5_ib_dev *dev, 4760 struct ib_wq_init_attr *wq_init_attr, 4761 struct mlx5_ib_create_wq *ucmd, 4762 struct mlx5_ib_rwq *rwq) 4763 { 4764 /* Sanity check RQ size before proceeding */ 4765 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz))) 4766 return -EINVAL; 4767 4768 if (!ucmd->rq_wqe_count) 4769 return -EINVAL; 4770 4771 rwq->wqe_count = ucmd->rq_wqe_count; 4772 rwq->wqe_shift = ucmd->rq_wqe_shift; 4773 rwq->buf_size = (rwq->wqe_count << rwq->wqe_shift); 4774 rwq->log_rq_stride = rwq->wqe_shift; 4775 rwq->log_rq_size = ilog2(rwq->wqe_count); 4776 return 0; 4777 } 4778 4779 static int prepare_user_rq(struct ib_pd *pd, 4780 struct ib_wq_init_attr *init_attr, 4781 struct ib_udata *udata, 4782 struct mlx5_ib_rwq *rwq) 4783 { 4784 struct mlx5_ib_dev *dev = to_mdev(pd->device); 4785 struct mlx5_ib_create_wq ucmd = {}; 4786 int err; 4787 size_t required_cmd_sz; 4788 4789 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved); 4790 if (udata->inlen < required_cmd_sz) { 4791 mlx5_ib_dbg(dev, "invalid inlen\n"); 4792 return -EINVAL; 4793 } 4794 4795 if (udata->inlen > sizeof(ucmd) && 4796 !ib_is_udata_cleared(udata, sizeof(ucmd), 4797 udata->inlen - sizeof(ucmd))) { 4798 mlx5_ib_dbg(dev, "inlen is not supported\n"); 4799 return -EOPNOTSUPP; 4800 } 4801 4802 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 4803 mlx5_ib_dbg(dev, "copy failed\n"); 4804 return -EFAULT; 4805 } 4806 4807 if (ucmd.comp_mask) { 4808 mlx5_ib_dbg(dev, "invalid comp mask\n"); 4809 return -EOPNOTSUPP; 4810 } 4811 4812 if (ucmd.reserved) { 4813 mlx5_ib_dbg(dev, "invalid reserved\n"); 4814 return -EOPNOTSUPP; 4815 } 4816 4817 err = set_user_rq_size(dev, init_attr, &ucmd, rwq); 4818 if (err) { 4819 mlx5_ib_dbg(dev, "err %d\n", err); 4820 return err; 4821 } 4822 4823 err = create_user_rq(dev, pd, rwq, &ucmd); 4824 if (err) { 4825 mlx5_ib_dbg(dev, "err %d\n", err); 4826 if (err) 4827 return err; 4828 } 4829 4830 rwq->user_index = ucmd.user_index; 4831 return 0; 4832 } 4833 4834 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 4835 struct ib_wq_init_attr *init_attr, 4836 struct ib_udata *udata) 4837 { 4838 struct mlx5_ib_dev *dev; 4839 struct mlx5_ib_rwq *rwq; 4840 struct mlx5_ib_create_wq_resp resp = {}; 4841 size_t min_resp_len; 4842 int err; 4843 4844 if (!udata) 4845 return ERR_PTR(-ENOSYS); 4846 4847 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 4848 if (udata->outlen && udata->outlen < min_resp_len) 4849 return ERR_PTR(-EINVAL); 4850 4851 dev = to_mdev(pd->device); 4852 switch (init_attr->wq_type) { 4853 case IB_WQT_RQ: 4854 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL); 4855 if (!rwq) 4856 return ERR_PTR(-ENOMEM); 4857 err = prepare_user_rq(pd, init_attr, udata, rwq); 4858 if (err) 4859 goto err; 4860 err = create_rq(rwq, pd, init_attr); 4861 if (err) 4862 goto err_user_rq; 4863 break; 4864 default: 4865 mlx5_ib_dbg(dev, "unsupported wq type %d\n", 4866 init_attr->wq_type); 4867 return ERR_PTR(-EINVAL); 4868 } 4869 4870 rwq->ibwq.wq_num = rwq->core_qp.qpn; 4871 rwq->ibwq.state = IB_WQS_RESET; 4872 if (udata->outlen) { 4873 resp.response_length = offsetof(typeof(resp), response_length) + 4874 sizeof(resp.response_length); 4875 err = ib_copy_to_udata(udata, &resp, resp.response_length); 4876 if (err) 4877 goto err_copy; 4878 } 4879 4880 rwq->core_qp.event = mlx5_ib_wq_event; 4881 rwq->ibwq.event_handler = init_attr->event_handler; 4882 return &rwq->ibwq; 4883 4884 err_copy: 4885 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); 4886 err_user_rq: 4887 destroy_user_rq(dev, pd, rwq); 4888 err: 4889 kfree(rwq); 4890 return ERR_PTR(err); 4891 } 4892 4893 int mlx5_ib_destroy_wq(struct ib_wq *wq) 4894 { 4895 struct mlx5_ib_dev *dev = to_mdev(wq->device); 4896 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 4897 4898 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); 4899 destroy_user_rq(dev, wq->pd, rwq); 4900 kfree(rwq); 4901 4902 return 0; 4903 } 4904 4905 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device, 4906 struct ib_rwq_ind_table_init_attr *init_attr, 4907 struct ib_udata *udata) 4908 { 4909 struct mlx5_ib_dev *dev = to_mdev(device); 4910 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl; 4911 int sz = 1 << init_attr->log_ind_tbl_size; 4912 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {}; 4913 size_t min_resp_len; 4914 int inlen; 4915 int err; 4916 int i; 4917 u32 *in; 4918 void *rqtc; 4919 4920 if (udata->inlen > 0 && 4921 !ib_is_udata_cleared(udata, 0, 4922 udata->inlen)) 4923 return ERR_PTR(-EOPNOTSUPP); 4924 4925 if (init_attr->log_ind_tbl_size > 4926 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) { 4927 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n", 4928 init_attr->log_ind_tbl_size, 4929 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)); 4930 return ERR_PTR(-EINVAL); 4931 } 4932 4933 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 4934 if (udata->outlen && udata->outlen < min_resp_len) 4935 return ERR_PTR(-EINVAL); 4936 4937 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL); 4938 if (!rwq_ind_tbl) 4939 return ERR_PTR(-ENOMEM); 4940 4941 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; 4942 in = kvzalloc(inlen, GFP_KERNEL); 4943 if (!in) { 4944 err = -ENOMEM; 4945 goto err; 4946 } 4947 4948 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 4949 4950 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 4951 MLX5_SET(rqtc, rqtc, rqt_max_size, sz); 4952 4953 for (i = 0; i < sz; i++) 4954 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num); 4955 4956 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn); 4957 kvfree(in); 4958 4959 if (err) 4960 goto err; 4961 4962 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn; 4963 if (udata->outlen) { 4964 resp.response_length = offsetof(typeof(resp), response_length) + 4965 sizeof(resp.response_length); 4966 err = ib_copy_to_udata(udata, &resp, resp.response_length); 4967 if (err) 4968 goto err_copy; 4969 } 4970 4971 return &rwq_ind_tbl->ib_rwq_ind_tbl; 4972 4973 err_copy: 4974 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn); 4975 err: 4976 kfree(rwq_ind_tbl); 4977 return ERR_PTR(err); 4978 } 4979 4980 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 4981 { 4982 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl); 4983 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device); 4984 4985 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn); 4986 4987 kfree(rwq_ind_tbl); 4988 return 0; 4989 } 4990 4991 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 4992 u32 wq_attr_mask, struct ib_udata *udata) 4993 { 4994 struct mlx5_ib_dev *dev = to_mdev(wq->device); 4995 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 4996 struct mlx5_ib_modify_wq ucmd = {}; 4997 size_t required_cmd_sz; 4998 int curr_wq_state; 4999 int wq_state; 5000 int inlen; 5001 int err; 5002 void *rqc; 5003 void *in; 5004 5005 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved); 5006 if (udata->inlen < required_cmd_sz) 5007 return -EINVAL; 5008 5009 if (udata->inlen > sizeof(ucmd) && 5010 !ib_is_udata_cleared(udata, sizeof(ucmd), 5011 udata->inlen - sizeof(ucmd))) 5012 return -EOPNOTSUPP; 5013 5014 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) 5015 return -EFAULT; 5016 5017 if (ucmd.comp_mask || ucmd.reserved) 5018 return -EOPNOTSUPP; 5019 5020 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 5021 in = kvzalloc(inlen, GFP_KERNEL); 5022 if (!in) 5023 return -ENOMEM; 5024 5025 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 5026 5027 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ? 5028 wq_attr->curr_wq_state : wq->state; 5029 wq_state = (wq_attr_mask & IB_WQ_STATE) ? 5030 wq_attr->wq_state : curr_wq_state; 5031 if (curr_wq_state == IB_WQS_ERR) 5032 curr_wq_state = MLX5_RQC_STATE_ERR; 5033 if (wq_state == IB_WQS_ERR) 5034 wq_state = MLX5_RQC_STATE_ERR; 5035 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state); 5036 MLX5_SET(rqc, rqc, state, wq_state); 5037 5038 if (wq_attr_mask & IB_WQ_FLAGS) { 5039 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) { 5040 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 5041 MLX5_CAP_ETH(dev->mdev, vlan_cap))) { 5042 mlx5_ib_dbg(dev, "VLAN offloads are not " 5043 "supported\n"); 5044 err = -EOPNOTSUPP; 5045 goto out; 5046 } 5047 MLX5_SET64(modify_rq_in, in, modify_bitmask, 5048 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD); 5049 MLX5_SET(rqc, rqc, vsd, 5050 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1); 5051 } 5052 } 5053 5054 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) { 5055 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 5056 MLX5_SET64(modify_rq_in, in, modify_bitmask, 5057 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 5058 MLX5_SET(rqc, rqc, counter_set_id, 5059 dev->port->cnts.set_id); 5060 } else 5061 pr_info_once("%s: Receive WQ counters are not supported on current FW\n", 5062 dev->ib_dev.name); 5063 } 5064 5065 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen); 5066 if (!err) 5067 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state; 5068 5069 out: 5070 kvfree(in); 5071 return err; 5072 } 5073