1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/module.h> 34 #include <rdma/ib_umem.h> 35 #include <rdma/ib_cache.h> 36 #include <rdma/ib_user_verbs.h> 37 #include <rdma/rdma_counter.h> 38 #include <linux/mlx5/fs.h> 39 #include "mlx5_ib.h" 40 #include "ib_rep.h" 41 #include "counters.h" 42 #include "cmd.h" 43 #include "qp.h" 44 #include "wr.h" 45 46 enum { 47 MLX5_IB_ACK_REQ_FREQ = 8, 48 }; 49 50 enum { 51 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83, 52 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, 53 MLX5_IB_LINK_TYPE_IB = 0, 54 MLX5_IB_LINK_TYPE_ETH = 1 55 }; 56 57 enum raw_qp_set_mask_map { 58 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0, 59 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1, 60 }; 61 62 struct mlx5_modify_raw_qp_param { 63 u16 operation; 64 65 u32 set_mask; /* raw_qp_set_mask_map */ 66 67 struct mlx5_rate_limit rl; 68 69 u8 rq_q_ctr_id; 70 u16 port; 71 }; 72 73 static void get_cqs(enum ib_qp_type qp_type, 74 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 75 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq); 76 77 static int is_qp0(enum ib_qp_type qp_type) 78 { 79 return qp_type == IB_QPT_SMI; 80 } 81 82 static int is_sqp(enum ib_qp_type qp_type) 83 { 84 return is_qp0(qp_type) || is_qp1(qp_type); 85 } 86 87 /** 88 * mlx5_ib_read_user_wqe_common() - Copy a WQE (or part of) from user WQ 89 * to kernel buffer 90 * 91 * @umem: User space memory where the WQ is 92 * @buffer: buffer to copy to 93 * @buflen: buffer length 94 * @wqe_index: index of WQE to copy from 95 * @wq_offset: offset to start of WQ 96 * @wq_wqe_cnt: number of WQEs in WQ 97 * @wq_wqe_shift: log2 of WQE size 98 * @bcnt: number of bytes to copy 99 * @bytes_copied: number of bytes to copy (return value) 100 * 101 * Copies from start of WQE bcnt or less bytes. 102 * Does not gurantee to copy the entire WQE. 103 * 104 * Return: zero on success, or an error code. 105 */ 106 static int mlx5_ib_read_user_wqe_common(struct ib_umem *umem, void *buffer, 107 size_t buflen, int wqe_index, 108 int wq_offset, int wq_wqe_cnt, 109 int wq_wqe_shift, int bcnt, 110 size_t *bytes_copied) 111 { 112 size_t offset = wq_offset + ((wqe_index % wq_wqe_cnt) << wq_wqe_shift); 113 size_t wq_end = wq_offset + (wq_wqe_cnt << wq_wqe_shift); 114 size_t copy_length; 115 int ret; 116 117 /* don't copy more than requested, more than buffer length or 118 * beyond WQ end 119 */ 120 copy_length = min_t(u32, buflen, wq_end - offset); 121 copy_length = min_t(u32, copy_length, bcnt); 122 123 ret = ib_umem_copy_from(buffer, umem, offset, copy_length); 124 if (ret) 125 return ret; 126 127 if (!ret && bytes_copied) 128 *bytes_copied = copy_length; 129 130 return 0; 131 } 132 133 static int mlx5_ib_read_kernel_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, 134 void *buffer, size_t buflen, size_t *bc) 135 { 136 struct mlx5_wqe_ctrl_seg *ctrl; 137 size_t bytes_copied = 0; 138 size_t wqe_length; 139 void *p; 140 int ds; 141 142 wqe_index = wqe_index & qp->sq.fbc.sz_m1; 143 144 /* read the control segment first */ 145 p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, wqe_index); 146 ctrl = p; 147 ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; 148 wqe_length = ds * MLX5_WQE_DS_UNITS; 149 150 /* read rest of WQE if it spreads over more than one stride */ 151 while (bytes_copied < wqe_length) { 152 size_t copy_length = 153 min_t(size_t, buflen - bytes_copied, MLX5_SEND_WQE_BB); 154 155 if (!copy_length) 156 break; 157 158 memcpy(buffer + bytes_copied, p, copy_length); 159 bytes_copied += copy_length; 160 161 wqe_index = (wqe_index + 1) & qp->sq.fbc.sz_m1; 162 p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, wqe_index); 163 } 164 *bc = bytes_copied; 165 return 0; 166 } 167 168 static int mlx5_ib_read_user_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, 169 void *buffer, size_t buflen, size_t *bc) 170 { 171 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 172 struct ib_umem *umem = base->ubuffer.umem; 173 struct mlx5_ib_wq *wq = &qp->sq; 174 struct mlx5_wqe_ctrl_seg *ctrl; 175 size_t bytes_copied; 176 size_t bytes_copied2; 177 size_t wqe_length; 178 int ret; 179 int ds; 180 181 /* at first read as much as possible */ 182 ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index, 183 wq->offset, wq->wqe_cnt, 184 wq->wqe_shift, buflen, 185 &bytes_copied); 186 if (ret) 187 return ret; 188 189 /* we need at least control segment size to proceed */ 190 if (bytes_copied < sizeof(*ctrl)) 191 return -EINVAL; 192 193 ctrl = buffer; 194 ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; 195 wqe_length = ds * MLX5_WQE_DS_UNITS; 196 197 /* if we copied enough then we are done */ 198 if (bytes_copied >= wqe_length) { 199 *bc = bytes_copied; 200 return 0; 201 } 202 203 /* otherwise this a wrapped around wqe 204 * so read the remaining bytes starting 205 * from wqe_index 0 206 */ 207 ret = mlx5_ib_read_user_wqe_common(umem, buffer + bytes_copied, 208 buflen - bytes_copied, 0, wq->offset, 209 wq->wqe_cnt, wq->wqe_shift, 210 wqe_length - bytes_copied, 211 &bytes_copied2); 212 213 if (ret) 214 return ret; 215 *bc = bytes_copied + bytes_copied2; 216 return 0; 217 } 218 219 int mlx5_ib_read_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 220 size_t buflen, size_t *bc) 221 { 222 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 223 struct ib_umem *umem = base->ubuffer.umem; 224 225 if (buflen < sizeof(struct mlx5_wqe_ctrl_seg)) 226 return -EINVAL; 227 228 if (!umem) 229 return mlx5_ib_read_kernel_wqe_sq(qp, wqe_index, buffer, 230 buflen, bc); 231 232 return mlx5_ib_read_user_wqe_sq(qp, wqe_index, buffer, buflen, bc); 233 } 234 235 static int mlx5_ib_read_user_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, 236 void *buffer, size_t buflen, size_t *bc) 237 { 238 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 239 struct ib_umem *umem = base->ubuffer.umem; 240 struct mlx5_ib_wq *wq = &qp->rq; 241 size_t bytes_copied; 242 int ret; 243 244 ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index, 245 wq->offset, wq->wqe_cnt, 246 wq->wqe_shift, buflen, 247 &bytes_copied); 248 249 if (ret) 250 return ret; 251 *bc = bytes_copied; 252 return 0; 253 } 254 255 int mlx5_ib_read_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 256 size_t buflen, size_t *bc) 257 { 258 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 259 struct ib_umem *umem = base->ubuffer.umem; 260 struct mlx5_ib_wq *wq = &qp->rq; 261 size_t wqe_size = 1 << wq->wqe_shift; 262 263 if (buflen < wqe_size) 264 return -EINVAL; 265 266 if (!umem) 267 return -EOPNOTSUPP; 268 269 return mlx5_ib_read_user_wqe_rq(qp, wqe_index, buffer, buflen, bc); 270 } 271 272 static int mlx5_ib_read_user_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, 273 void *buffer, size_t buflen, size_t *bc) 274 { 275 struct ib_umem *umem = srq->umem; 276 size_t bytes_copied; 277 int ret; 278 279 ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index, 0, 280 srq->msrq.max, srq->msrq.wqe_shift, 281 buflen, &bytes_copied); 282 283 if (ret) 284 return ret; 285 *bc = bytes_copied; 286 return 0; 287 } 288 289 int mlx5_ib_read_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, void *buffer, 290 size_t buflen, size_t *bc) 291 { 292 struct ib_umem *umem = srq->umem; 293 size_t wqe_size = 1 << srq->msrq.wqe_shift; 294 295 if (buflen < wqe_size) 296 return -EINVAL; 297 298 if (!umem) 299 return -EOPNOTSUPP; 300 301 return mlx5_ib_read_user_wqe_srq(srq, wqe_index, buffer, buflen, bc); 302 } 303 304 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type) 305 { 306 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; 307 struct ib_event event; 308 309 if (type == MLX5_EVENT_TYPE_PATH_MIG) { 310 /* This event is only valid for trans_qps */ 311 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port; 312 } 313 314 if (ibqp->event_handler) { 315 event.device = ibqp->device; 316 event.element.qp = ibqp; 317 switch (type) { 318 case MLX5_EVENT_TYPE_PATH_MIG: 319 event.event = IB_EVENT_PATH_MIG; 320 break; 321 case MLX5_EVENT_TYPE_COMM_EST: 322 event.event = IB_EVENT_COMM_EST; 323 break; 324 case MLX5_EVENT_TYPE_SQ_DRAINED: 325 event.event = IB_EVENT_SQ_DRAINED; 326 break; 327 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 328 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 329 break; 330 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 331 event.event = IB_EVENT_QP_FATAL; 332 break; 333 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 334 event.event = IB_EVENT_PATH_MIG_ERR; 335 break; 336 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 337 event.event = IB_EVENT_QP_REQ_ERR; 338 break; 339 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 340 event.event = IB_EVENT_QP_ACCESS_ERR; 341 break; 342 default: 343 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn); 344 return; 345 } 346 347 ibqp->event_handler(&event, ibqp->qp_context); 348 } 349 } 350 351 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap, 352 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd) 353 { 354 int wqe_size; 355 int wq_size; 356 357 /* Sanity check RQ size before proceeding */ 358 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) 359 return -EINVAL; 360 361 if (!has_rq) { 362 qp->rq.max_gs = 0; 363 qp->rq.wqe_cnt = 0; 364 qp->rq.wqe_shift = 0; 365 cap->max_recv_wr = 0; 366 cap->max_recv_sge = 0; 367 } else { 368 int wq_sig = !!(qp->flags_en & MLX5_QP_FLAG_SIGNATURE); 369 370 if (ucmd) { 371 qp->rq.wqe_cnt = ucmd->rq_wqe_count; 372 if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift)) 373 return -EINVAL; 374 qp->rq.wqe_shift = ucmd->rq_wqe_shift; 375 if ((1 << qp->rq.wqe_shift) / 376 sizeof(struct mlx5_wqe_data_seg) < 377 wq_sig) 378 return -EINVAL; 379 qp->rq.max_gs = 380 (1 << qp->rq.wqe_shift) / 381 sizeof(struct mlx5_wqe_data_seg) - 382 wq_sig; 383 qp->rq.max_post = qp->rq.wqe_cnt; 384 } else { 385 wqe_size = 386 wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 387 0; 388 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg); 389 wqe_size = roundup_pow_of_two(wqe_size); 390 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size; 391 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB); 392 qp->rq.wqe_cnt = wq_size / wqe_size; 393 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) { 394 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n", 395 wqe_size, 396 MLX5_CAP_GEN(dev->mdev, 397 max_wqe_sz_rq)); 398 return -EINVAL; 399 } 400 qp->rq.wqe_shift = ilog2(wqe_size); 401 qp->rq.max_gs = 402 (1 << qp->rq.wqe_shift) / 403 sizeof(struct mlx5_wqe_data_seg) - 404 wq_sig; 405 qp->rq.max_post = qp->rq.wqe_cnt; 406 } 407 } 408 409 return 0; 410 } 411 412 static int sq_overhead(struct ib_qp_init_attr *attr) 413 { 414 int size = 0; 415 416 switch (attr->qp_type) { 417 case IB_QPT_XRC_INI: 418 size += sizeof(struct mlx5_wqe_xrc_seg); 419 fallthrough; 420 case IB_QPT_RC: 421 size += sizeof(struct mlx5_wqe_ctrl_seg) + 422 max(sizeof(struct mlx5_wqe_atomic_seg) + 423 sizeof(struct mlx5_wqe_raddr_seg), 424 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 425 sizeof(struct mlx5_mkey_seg) + 426 MLX5_IB_SQ_UMR_INLINE_THRESHOLD / 427 MLX5_IB_UMR_OCTOWORD); 428 break; 429 430 case IB_QPT_XRC_TGT: 431 return 0; 432 433 case IB_QPT_UC: 434 size += sizeof(struct mlx5_wqe_ctrl_seg) + 435 max(sizeof(struct mlx5_wqe_raddr_seg), 436 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 437 sizeof(struct mlx5_mkey_seg)); 438 break; 439 440 case IB_QPT_UD: 441 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) 442 size += sizeof(struct mlx5_wqe_eth_pad) + 443 sizeof(struct mlx5_wqe_eth_seg); 444 fallthrough; 445 case IB_QPT_SMI: 446 case MLX5_IB_QPT_HW_GSI: 447 size += sizeof(struct mlx5_wqe_ctrl_seg) + 448 sizeof(struct mlx5_wqe_datagram_seg); 449 break; 450 451 case MLX5_IB_QPT_REG_UMR: 452 size += sizeof(struct mlx5_wqe_ctrl_seg) + 453 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 454 sizeof(struct mlx5_mkey_seg); 455 break; 456 457 default: 458 return -EINVAL; 459 } 460 461 return size; 462 } 463 464 static int calc_send_wqe(struct ib_qp_init_attr *attr) 465 { 466 int inl_size = 0; 467 int size; 468 469 size = sq_overhead(attr); 470 if (size < 0) 471 return size; 472 473 if (attr->cap.max_inline_data) { 474 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) + 475 attr->cap.max_inline_data; 476 } 477 478 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg); 479 if (attr->create_flags & IB_QP_CREATE_INTEGRITY_EN && 480 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE) 481 return MLX5_SIG_WQE_SIZE; 482 else 483 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB); 484 } 485 486 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size) 487 { 488 int max_sge; 489 490 if (attr->qp_type == IB_QPT_RC) 491 max_sge = (min_t(int, wqe_size, 512) - 492 sizeof(struct mlx5_wqe_ctrl_seg) - 493 sizeof(struct mlx5_wqe_raddr_seg)) / 494 sizeof(struct mlx5_wqe_data_seg); 495 else if (attr->qp_type == IB_QPT_XRC_INI) 496 max_sge = (min_t(int, wqe_size, 512) - 497 sizeof(struct mlx5_wqe_ctrl_seg) - 498 sizeof(struct mlx5_wqe_xrc_seg) - 499 sizeof(struct mlx5_wqe_raddr_seg)) / 500 sizeof(struct mlx5_wqe_data_seg); 501 else 502 max_sge = (wqe_size - sq_overhead(attr)) / 503 sizeof(struct mlx5_wqe_data_seg); 504 505 return min_t(int, max_sge, wqe_size - sq_overhead(attr) / 506 sizeof(struct mlx5_wqe_data_seg)); 507 } 508 509 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, 510 struct mlx5_ib_qp *qp) 511 { 512 int wqe_size; 513 int wq_size; 514 515 if (!attr->cap.max_send_wr) 516 return 0; 517 518 wqe_size = calc_send_wqe(attr); 519 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size); 520 if (wqe_size < 0) 521 return wqe_size; 522 523 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 524 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n", 525 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 526 return -EINVAL; 527 } 528 529 qp->max_inline_data = wqe_size - sq_overhead(attr) - 530 sizeof(struct mlx5_wqe_inline_seg); 531 attr->cap.max_inline_data = qp->max_inline_data; 532 533 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size); 534 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB; 535 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 536 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n", 537 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB, 538 qp->sq.wqe_cnt, 539 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 540 return -ENOMEM; 541 } 542 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 543 qp->sq.max_gs = get_send_sge(attr, wqe_size); 544 if (qp->sq.max_gs < attr->cap.max_send_sge) 545 return -ENOMEM; 546 547 attr->cap.max_send_sge = qp->sq.max_gs; 548 qp->sq.max_post = wq_size / wqe_size; 549 attr->cap.max_send_wr = qp->sq.max_post; 550 551 return wq_size; 552 } 553 554 static int set_user_buf_size(struct mlx5_ib_dev *dev, 555 struct mlx5_ib_qp *qp, 556 struct mlx5_ib_create_qp *ucmd, 557 struct mlx5_ib_qp_base *base, 558 struct ib_qp_init_attr *attr) 559 { 560 int desc_sz = 1 << qp->sq.wqe_shift; 561 562 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 563 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n", 564 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 565 return -EINVAL; 566 } 567 568 if (ucmd->sq_wqe_count && !is_power_of_2(ucmd->sq_wqe_count)) { 569 mlx5_ib_warn(dev, "sq_wqe_count %d is not a power of two\n", 570 ucmd->sq_wqe_count); 571 return -EINVAL; 572 } 573 574 qp->sq.wqe_cnt = ucmd->sq_wqe_count; 575 576 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 577 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n", 578 qp->sq.wqe_cnt, 579 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 580 return -EINVAL; 581 } 582 583 if (attr->qp_type == IB_QPT_RAW_PACKET || 584 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 585 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift; 586 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6; 587 } else { 588 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 589 (qp->sq.wqe_cnt << 6); 590 } 591 592 return 0; 593 } 594 595 static int qp_has_rq(struct ib_qp_init_attr *attr) 596 { 597 if (attr->qp_type == IB_QPT_XRC_INI || 598 attr->qp_type == IB_QPT_XRC_TGT || attr->srq || 599 attr->qp_type == MLX5_IB_QPT_REG_UMR || 600 !attr->cap.max_recv_wr) 601 return 0; 602 603 return 1; 604 } 605 606 enum { 607 /* this is the first blue flame register in the array of bfregs assigned 608 * to a processes. Since we do not use it for blue flame but rather 609 * regular 64 bit doorbells, we do not need a lock for maintaiing 610 * "odd/even" order 611 */ 612 NUM_NON_BLUE_FLAME_BFREGS = 1, 613 }; 614 615 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi) 616 { 617 return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR; 618 } 619 620 static int num_med_bfreg(struct mlx5_ib_dev *dev, 621 struct mlx5_bfreg_info *bfregi) 622 { 623 int n; 624 625 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs - 626 NUM_NON_BLUE_FLAME_BFREGS; 627 628 return n >= 0 ? n : 0; 629 } 630 631 static int first_med_bfreg(struct mlx5_ib_dev *dev, 632 struct mlx5_bfreg_info *bfregi) 633 { 634 return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM; 635 } 636 637 static int first_hi_bfreg(struct mlx5_ib_dev *dev, 638 struct mlx5_bfreg_info *bfregi) 639 { 640 int med; 641 642 med = num_med_bfreg(dev, bfregi); 643 return ++med; 644 } 645 646 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev, 647 struct mlx5_bfreg_info *bfregi) 648 { 649 int i; 650 651 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) { 652 if (!bfregi->count[i]) { 653 bfregi->count[i]++; 654 return i; 655 } 656 } 657 658 return -ENOMEM; 659 } 660 661 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev, 662 struct mlx5_bfreg_info *bfregi) 663 { 664 int minidx = first_med_bfreg(dev, bfregi); 665 int i; 666 667 if (minidx < 0) 668 return minidx; 669 670 for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) { 671 if (bfregi->count[i] < bfregi->count[minidx]) 672 minidx = i; 673 if (!bfregi->count[minidx]) 674 break; 675 } 676 677 bfregi->count[minidx]++; 678 return minidx; 679 } 680 681 static int alloc_bfreg(struct mlx5_ib_dev *dev, 682 struct mlx5_bfreg_info *bfregi) 683 { 684 int bfregn = -ENOMEM; 685 686 if (bfregi->lib_uar_dyn) 687 return -EINVAL; 688 689 mutex_lock(&bfregi->lock); 690 if (bfregi->ver >= 2) { 691 bfregn = alloc_high_class_bfreg(dev, bfregi); 692 if (bfregn < 0) 693 bfregn = alloc_med_class_bfreg(dev, bfregi); 694 } 695 696 if (bfregn < 0) { 697 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1); 698 bfregn = 0; 699 bfregi->count[bfregn]++; 700 } 701 mutex_unlock(&bfregi->lock); 702 703 return bfregn; 704 } 705 706 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn) 707 { 708 mutex_lock(&bfregi->lock); 709 bfregi->count[bfregn]--; 710 mutex_unlock(&bfregi->lock); 711 } 712 713 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state) 714 { 715 switch (state) { 716 case IB_QPS_RESET: return MLX5_QP_STATE_RST; 717 case IB_QPS_INIT: return MLX5_QP_STATE_INIT; 718 case IB_QPS_RTR: return MLX5_QP_STATE_RTR; 719 case IB_QPS_RTS: return MLX5_QP_STATE_RTS; 720 case IB_QPS_SQD: return MLX5_QP_STATE_SQD; 721 case IB_QPS_SQE: return MLX5_QP_STATE_SQER; 722 case IB_QPS_ERR: return MLX5_QP_STATE_ERR; 723 default: return -1; 724 } 725 } 726 727 static int to_mlx5_st(enum ib_qp_type type) 728 { 729 switch (type) { 730 case IB_QPT_RC: return MLX5_QP_ST_RC; 731 case IB_QPT_UC: return MLX5_QP_ST_UC; 732 case IB_QPT_UD: return MLX5_QP_ST_UD; 733 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR; 734 case IB_QPT_XRC_INI: 735 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC; 736 case IB_QPT_SMI: return MLX5_QP_ST_QP0; 737 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1; 738 case MLX5_IB_QPT_DCI: return MLX5_QP_ST_DCI; 739 case IB_QPT_RAW_PACKET: return MLX5_QP_ST_RAW_ETHERTYPE; 740 default: return -EINVAL; 741 } 742 } 743 744 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, 745 struct mlx5_ib_cq *recv_cq); 746 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, 747 struct mlx5_ib_cq *recv_cq); 748 749 int bfregn_to_uar_index(struct mlx5_ib_dev *dev, 750 struct mlx5_bfreg_info *bfregi, u32 bfregn, 751 bool dyn_bfreg) 752 { 753 unsigned int bfregs_per_sys_page; 754 u32 index_of_sys_page; 755 u32 offset; 756 757 if (bfregi->lib_uar_dyn) 758 return -EINVAL; 759 760 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * 761 MLX5_NON_FP_BFREGS_PER_UAR; 762 index_of_sys_page = bfregn / bfregs_per_sys_page; 763 764 if (dyn_bfreg) { 765 index_of_sys_page += bfregi->num_static_sys_pages; 766 767 if (index_of_sys_page >= bfregi->num_sys_pages) 768 return -EINVAL; 769 770 if (bfregn > bfregi->num_dyn_bfregs || 771 bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) { 772 mlx5_ib_dbg(dev, "Invalid dynamic uar index\n"); 773 return -EINVAL; 774 } 775 } 776 777 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR; 778 return bfregi->sys_pages[index_of_sys_page] + offset; 779 } 780 781 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 782 struct mlx5_ib_rwq *rwq, struct ib_udata *udata) 783 { 784 struct mlx5_ib_ucontext *context = 785 rdma_udata_to_drv_context( 786 udata, 787 struct mlx5_ib_ucontext, 788 ibucontext); 789 790 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP) 791 atomic_dec(&dev->delay_drop.rqs_cnt); 792 793 mlx5_ib_db_unmap_user(context, &rwq->db); 794 ib_umem_release(rwq->umem); 795 } 796 797 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 798 struct ib_udata *udata, struct mlx5_ib_rwq *rwq, 799 struct mlx5_ib_create_wq *ucmd) 800 { 801 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 802 udata, struct mlx5_ib_ucontext, ibucontext); 803 unsigned long page_size = 0; 804 u32 offset = 0; 805 int err; 806 807 if (!ucmd->buf_addr) 808 return -EINVAL; 809 810 rwq->umem = ib_umem_get(&dev->ib_dev, ucmd->buf_addr, rwq->buf_size, 0); 811 if (IS_ERR(rwq->umem)) { 812 mlx5_ib_dbg(dev, "umem_get failed\n"); 813 err = PTR_ERR(rwq->umem); 814 return err; 815 } 816 817 page_size = mlx5_umem_find_best_quantized_pgoff( 818 rwq->umem, wq, log_wq_pg_sz, MLX5_ADAPTER_PAGE_SHIFT, 819 page_offset, 64, &rwq->rq_page_offset); 820 if (!page_size) { 821 mlx5_ib_warn(dev, "bad offset\n"); 822 err = -EINVAL; 823 goto err_umem; 824 } 825 826 rwq->rq_num_pas = ib_umem_num_dma_blocks(rwq->umem, page_size); 827 rwq->page_shift = order_base_2(page_size); 828 rwq->log_page_size = rwq->page_shift - MLX5_ADAPTER_PAGE_SHIFT; 829 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE); 830 831 mlx5_ib_dbg( 832 dev, 833 "addr 0x%llx, size %zd, npages %zu, page_size %ld, ncont %d, offset %d\n", 834 (unsigned long long)ucmd->buf_addr, rwq->buf_size, 835 ib_umem_num_pages(rwq->umem), page_size, rwq->rq_num_pas, 836 offset); 837 838 err = mlx5_ib_db_map_user(ucontext, udata, ucmd->db_addr, &rwq->db); 839 if (err) { 840 mlx5_ib_dbg(dev, "map failed\n"); 841 goto err_umem; 842 } 843 844 return 0; 845 846 err_umem: 847 ib_umem_release(rwq->umem); 848 return err; 849 } 850 851 static int adjust_bfregn(struct mlx5_ib_dev *dev, 852 struct mlx5_bfreg_info *bfregi, int bfregn) 853 { 854 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR + 855 bfregn % MLX5_NON_FP_BFREGS_PER_UAR; 856 } 857 858 static int _create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 859 struct mlx5_ib_qp *qp, struct ib_udata *udata, 860 struct ib_qp_init_attr *attr, u32 **in, 861 struct mlx5_ib_create_qp_resp *resp, int *inlen, 862 struct mlx5_ib_qp_base *base, 863 struct mlx5_ib_create_qp *ucmd) 864 { 865 struct mlx5_ib_ucontext *context; 866 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer; 867 unsigned int page_offset_quantized = 0; 868 unsigned long page_size = 0; 869 int uar_index = 0; 870 int bfregn; 871 int ncont = 0; 872 __be64 *pas; 873 void *qpc; 874 int err; 875 u16 uid; 876 u32 uar_flags; 877 878 context = rdma_udata_to_drv_context(udata, struct mlx5_ib_ucontext, 879 ibucontext); 880 uar_flags = qp->flags_en & 881 (MLX5_QP_FLAG_UAR_PAGE_INDEX | MLX5_QP_FLAG_BFREG_INDEX); 882 switch (uar_flags) { 883 case MLX5_QP_FLAG_UAR_PAGE_INDEX: 884 uar_index = ucmd->bfreg_index; 885 bfregn = MLX5_IB_INVALID_BFREG; 886 break; 887 case MLX5_QP_FLAG_BFREG_INDEX: 888 uar_index = bfregn_to_uar_index(dev, &context->bfregi, 889 ucmd->bfreg_index, true); 890 if (uar_index < 0) 891 return uar_index; 892 bfregn = MLX5_IB_INVALID_BFREG; 893 break; 894 case 0: 895 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL) 896 return -EINVAL; 897 bfregn = alloc_bfreg(dev, &context->bfregi); 898 if (bfregn < 0) 899 return bfregn; 900 break; 901 default: 902 return -EINVAL; 903 } 904 905 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index); 906 if (bfregn != MLX5_IB_INVALID_BFREG) 907 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn, 908 false); 909 910 qp->rq.offset = 0; 911 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 912 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 913 914 err = set_user_buf_size(dev, qp, ucmd, base, attr); 915 if (err) 916 goto err_bfreg; 917 918 if (ucmd->buf_addr && ubuffer->buf_size) { 919 ubuffer->buf_addr = ucmd->buf_addr; 920 ubuffer->umem = ib_umem_get(&dev->ib_dev, ubuffer->buf_addr, 921 ubuffer->buf_size, 0); 922 if (IS_ERR(ubuffer->umem)) { 923 err = PTR_ERR(ubuffer->umem); 924 goto err_bfreg; 925 } 926 page_size = mlx5_umem_find_best_quantized_pgoff( 927 ubuffer->umem, qpc, log_page_size, 928 MLX5_ADAPTER_PAGE_SHIFT, page_offset, 64, 929 &page_offset_quantized); 930 if (!page_size) { 931 err = -EINVAL; 932 goto err_umem; 933 } 934 ncont = ib_umem_num_dma_blocks(ubuffer->umem, page_size); 935 } else { 936 ubuffer->umem = NULL; 937 } 938 939 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 940 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont; 941 *in = kvzalloc(*inlen, GFP_KERNEL); 942 if (!*in) { 943 err = -ENOMEM; 944 goto err_umem; 945 } 946 947 uid = (attr->qp_type != IB_QPT_XRC_INI) ? to_mpd(pd)->uid : 0; 948 MLX5_SET(create_qp_in, *in, uid, uid); 949 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 950 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas); 951 if (ubuffer->umem) { 952 mlx5_ib_populate_pas(ubuffer->umem, page_size, pas, 0); 953 MLX5_SET(qpc, qpc, log_page_size, 954 order_base_2(page_size) - MLX5_ADAPTER_PAGE_SHIFT); 955 MLX5_SET(qpc, qpc, page_offset, page_offset_quantized); 956 } 957 MLX5_SET(qpc, qpc, uar_page, uar_index); 958 if (bfregn != MLX5_IB_INVALID_BFREG) 959 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn); 960 else 961 resp->bfreg_index = MLX5_IB_INVALID_BFREG; 962 qp->bfregn = bfregn; 963 964 err = mlx5_ib_db_map_user(context, udata, ucmd->db_addr, &qp->db); 965 if (err) { 966 mlx5_ib_dbg(dev, "map failed\n"); 967 goto err_free; 968 } 969 970 return 0; 971 972 err_free: 973 kvfree(*in); 974 975 err_umem: 976 ib_umem_release(ubuffer->umem); 977 978 err_bfreg: 979 if (bfregn != MLX5_IB_INVALID_BFREG) 980 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn); 981 return err; 982 } 983 984 static void destroy_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 985 struct mlx5_ib_qp_base *base, struct ib_udata *udata) 986 { 987 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 988 udata, struct mlx5_ib_ucontext, ibucontext); 989 990 if (udata) { 991 /* User QP */ 992 mlx5_ib_db_unmap_user(context, &qp->db); 993 ib_umem_release(base->ubuffer.umem); 994 995 /* 996 * Free only the BFREGs which are handled by the kernel. 997 * BFREGs of UARs allocated dynamically are handled by user. 998 */ 999 if (qp->bfregn != MLX5_IB_INVALID_BFREG) 1000 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn); 1001 return; 1002 } 1003 1004 /* Kernel QP */ 1005 kvfree(qp->sq.wqe_head); 1006 kvfree(qp->sq.w_list); 1007 kvfree(qp->sq.wrid); 1008 kvfree(qp->sq.wr_data); 1009 kvfree(qp->rq.wrid); 1010 if (qp->db.db) 1011 mlx5_db_free(dev->mdev, &qp->db); 1012 if (qp->buf.frags) 1013 mlx5_frag_buf_free(dev->mdev, &qp->buf); 1014 } 1015 1016 static int _create_kernel_qp(struct mlx5_ib_dev *dev, 1017 struct ib_qp_init_attr *init_attr, 1018 struct mlx5_ib_qp *qp, u32 **in, int *inlen, 1019 struct mlx5_ib_qp_base *base) 1020 { 1021 int uar_index; 1022 void *qpc; 1023 int err; 1024 1025 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR) 1026 qp->bf.bfreg = &dev->fp_bfreg; 1027 else if (qp->flags & MLX5_IB_QP_CREATE_WC_TEST) 1028 qp->bf.bfreg = &dev->wc_bfreg; 1029 else 1030 qp->bf.bfreg = &dev->bfreg; 1031 1032 /* We need to divide by two since each register is comprised of 1033 * two buffers of identical size, namely odd and even 1034 */ 1035 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2; 1036 uar_index = qp->bf.bfreg->index; 1037 1038 err = calc_sq_size(dev, init_attr, qp); 1039 if (err < 0) { 1040 mlx5_ib_dbg(dev, "err %d\n", err); 1041 return err; 1042 } 1043 1044 qp->rq.offset = 0; 1045 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 1046 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift); 1047 1048 err = mlx5_frag_buf_alloc_node(dev->mdev, base->ubuffer.buf_size, 1049 &qp->buf, dev->mdev->priv.numa_node); 1050 if (err) { 1051 mlx5_ib_dbg(dev, "err %d\n", err); 1052 return err; 1053 } 1054 1055 if (qp->rq.wqe_cnt) 1056 mlx5_init_fbc(qp->buf.frags, qp->rq.wqe_shift, 1057 ilog2(qp->rq.wqe_cnt), &qp->rq.fbc); 1058 1059 if (qp->sq.wqe_cnt) { 1060 int sq_strides_offset = (qp->sq.offset & (PAGE_SIZE - 1)) / 1061 MLX5_SEND_WQE_BB; 1062 mlx5_init_fbc_offset(qp->buf.frags + 1063 (qp->sq.offset / PAGE_SIZE), 1064 ilog2(MLX5_SEND_WQE_BB), 1065 ilog2(qp->sq.wqe_cnt), 1066 sq_strides_offset, &qp->sq.fbc); 1067 1068 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0); 1069 } 1070 1071 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 1072 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages; 1073 *in = kvzalloc(*inlen, GFP_KERNEL); 1074 if (!*in) { 1075 err = -ENOMEM; 1076 goto err_buf; 1077 } 1078 1079 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 1080 MLX5_SET(qpc, qpc, uar_page, uar_index); 1081 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT); 1082 1083 /* Set "fast registration enabled" for all kernel QPs */ 1084 MLX5_SET(qpc, qpc, fre, 1); 1085 MLX5_SET(qpc, qpc, rlky, 1); 1086 1087 if (qp->flags & MLX5_IB_QP_CREATE_SQPN_QP1) 1088 MLX5_SET(qpc, qpc, deth_sqpn, 1); 1089 1090 mlx5_fill_page_frag_array(&qp->buf, 1091 (__be64 *)MLX5_ADDR_OF(create_qp_in, 1092 *in, pas)); 1093 1094 err = mlx5_db_alloc(dev->mdev, &qp->db); 1095 if (err) { 1096 mlx5_ib_dbg(dev, "err %d\n", err); 1097 goto err_free; 1098 } 1099 1100 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt, 1101 sizeof(*qp->sq.wrid), GFP_KERNEL); 1102 qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt, 1103 sizeof(*qp->sq.wr_data), GFP_KERNEL); 1104 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt, 1105 sizeof(*qp->rq.wrid), GFP_KERNEL); 1106 qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt, 1107 sizeof(*qp->sq.w_list), GFP_KERNEL); 1108 qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt, 1109 sizeof(*qp->sq.wqe_head), GFP_KERNEL); 1110 1111 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid || 1112 !qp->sq.w_list || !qp->sq.wqe_head) { 1113 err = -ENOMEM; 1114 goto err_wrid; 1115 } 1116 1117 return 0; 1118 1119 err_wrid: 1120 kvfree(qp->sq.wqe_head); 1121 kvfree(qp->sq.w_list); 1122 kvfree(qp->sq.wrid); 1123 kvfree(qp->sq.wr_data); 1124 kvfree(qp->rq.wrid); 1125 mlx5_db_free(dev->mdev, &qp->db); 1126 1127 err_free: 1128 kvfree(*in); 1129 1130 err_buf: 1131 mlx5_frag_buf_free(dev->mdev, &qp->buf); 1132 return err; 1133 } 1134 1135 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr) 1136 { 1137 if (attr->srq || (qp->type == IB_QPT_XRC_TGT) || 1138 (qp->type == MLX5_IB_QPT_DCI) || (qp->type == IB_QPT_XRC_INI)) 1139 return MLX5_SRQ_RQ; 1140 else if (!qp->has_rq) 1141 return MLX5_ZERO_LEN_RQ; 1142 1143 return MLX5_NON_ZERO_RQ; 1144 } 1145 1146 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1147 struct mlx5_ib_qp *qp, 1148 struct mlx5_ib_sq *sq, u32 tdn, 1149 struct ib_pd *pd) 1150 { 1151 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {}; 1152 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 1153 1154 MLX5_SET(create_tis_in, in, uid, to_mpd(pd)->uid); 1155 MLX5_SET(tisc, tisc, transport_domain, tdn); 1156 if (qp->flags & IB_QP_CREATE_SOURCE_QPN) 1157 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn); 1158 1159 return mlx5_core_create_tis(dev->mdev, in, &sq->tisn); 1160 } 1161 1162 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1163 struct mlx5_ib_sq *sq, struct ib_pd *pd) 1164 { 1165 mlx5_cmd_destroy_tis(dev->mdev, sq->tisn, to_mpd(pd)->uid); 1166 } 1167 1168 static void destroy_flow_rule_vport_sq(struct mlx5_ib_sq *sq) 1169 { 1170 if (sq->flow_rule) 1171 mlx5_del_flow_rules(sq->flow_rule); 1172 sq->flow_rule = NULL; 1173 } 1174 1175 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1176 struct ib_udata *udata, 1177 struct mlx5_ib_sq *sq, void *qpin, 1178 struct ib_pd *pd) 1179 { 1180 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer; 1181 __be64 *pas; 1182 void *in; 1183 void *sqc; 1184 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1185 void *wq; 1186 int inlen; 1187 int err; 1188 unsigned int page_offset_quantized; 1189 unsigned long page_size; 1190 1191 sq->ubuffer.umem = ib_umem_get(&dev->ib_dev, ubuffer->buf_addr, 1192 ubuffer->buf_size, 0); 1193 if (IS_ERR(sq->ubuffer.umem)) 1194 return PTR_ERR(sq->ubuffer.umem); 1195 page_size = mlx5_umem_find_best_quantized_pgoff( 1196 ubuffer->umem, wq, log_wq_pg_sz, MLX5_ADAPTER_PAGE_SHIFT, 1197 page_offset, 64, &page_offset_quantized); 1198 if (!page_size) { 1199 err = -EINVAL; 1200 goto err_umem; 1201 } 1202 1203 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + 1204 sizeof(u64) * 1205 ib_umem_num_dma_blocks(sq->ubuffer.umem, page_size); 1206 in = kvzalloc(inlen, GFP_KERNEL); 1207 if (!in) { 1208 err = -ENOMEM; 1209 goto err_umem; 1210 } 1211 1212 MLX5_SET(create_sq_in, in, uid, to_mpd(pd)->uid); 1213 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 1214 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 1215 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe)) 1216 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1); 1217 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 1218 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1219 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd)); 1220 MLX5_SET(sqc, sqc, tis_lst_sz, 1); 1221 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn); 1222 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 1223 MLX5_CAP_ETH(dev->mdev, swp)) 1224 MLX5_SET(sqc, sqc, allow_swp, 1); 1225 1226 wq = MLX5_ADDR_OF(sqc, sqc, wq); 1227 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1228 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1229 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page)); 1230 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1231 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 1232 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size)); 1233 MLX5_SET(wq, wq, log_wq_pg_sz, 1234 order_base_2(page_size) - MLX5_ADAPTER_PAGE_SHIFT); 1235 MLX5_SET(wq, wq, page_offset, page_offset_quantized); 1236 1237 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1238 mlx5_ib_populate_pas(sq->ubuffer.umem, page_size, pas, 0); 1239 1240 err = mlx5_core_create_sq_tracked(dev, in, inlen, &sq->base.mqp); 1241 1242 kvfree(in); 1243 1244 if (err) 1245 goto err_umem; 1246 1247 return 0; 1248 1249 err_umem: 1250 ib_umem_release(sq->ubuffer.umem); 1251 sq->ubuffer.umem = NULL; 1252 1253 return err; 1254 } 1255 1256 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1257 struct mlx5_ib_sq *sq) 1258 { 1259 destroy_flow_rule_vport_sq(sq); 1260 mlx5_core_destroy_sq_tracked(dev, &sq->base.mqp); 1261 ib_umem_release(sq->ubuffer.umem); 1262 } 1263 1264 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1265 struct mlx5_ib_rq *rq, void *qpin, 1266 struct ib_pd *pd) 1267 { 1268 struct mlx5_ib_qp *mqp = rq->base.container_mibqp; 1269 __be64 *pas; 1270 void *in; 1271 void *rqc; 1272 void *wq; 1273 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1274 struct ib_umem *umem = rq->base.ubuffer.umem; 1275 unsigned int page_offset_quantized; 1276 unsigned long page_size = 0; 1277 size_t inlen; 1278 int err; 1279 1280 page_size = mlx5_umem_find_best_quantized_pgoff(umem, wq, log_wq_pg_sz, 1281 MLX5_ADAPTER_PAGE_SHIFT, 1282 page_offset, 64, 1283 &page_offset_quantized); 1284 if (!page_size) 1285 return -EINVAL; 1286 1287 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + 1288 sizeof(u64) * ib_umem_num_dma_blocks(umem, page_size); 1289 in = kvzalloc(inlen, GFP_KERNEL); 1290 if (!in) 1291 return -ENOMEM; 1292 1293 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid); 1294 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 1295 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING)) 1296 MLX5_SET(rqc, rqc, vsd, 1); 1297 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 1298 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 1299 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 1300 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1301 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv)); 1302 1303 if (mqp->flags & IB_QP_CREATE_SCATTER_FCS) 1304 MLX5_SET(rqc, rqc, scatter_fcs, 1); 1305 1306 wq = MLX5_ADDR_OF(rqc, rqc, wq); 1307 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1308 if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING) 1309 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 1310 MLX5_SET(wq, wq, page_offset, page_offset_quantized); 1311 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1312 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1313 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4); 1314 MLX5_SET(wq, wq, log_wq_pg_sz, 1315 order_base_2(page_size) - MLX5_ADAPTER_PAGE_SHIFT); 1316 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size)); 1317 1318 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1319 mlx5_ib_populate_pas(umem, page_size, pas, 0); 1320 1321 err = mlx5_core_create_rq_tracked(dev, in, inlen, &rq->base.mqp); 1322 1323 kvfree(in); 1324 1325 return err; 1326 } 1327 1328 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1329 struct mlx5_ib_rq *rq) 1330 { 1331 mlx5_core_destroy_rq_tracked(dev, &rq->base.mqp); 1332 } 1333 1334 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1335 struct mlx5_ib_rq *rq, 1336 u32 qp_flags_en, 1337 struct ib_pd *pd) 1338 { 1339 if (qp_flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 1340 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) 1341 mlx5_ib_disable_lb(dev, false, true); 1342 mlx5_cmd_destroy_tir(dev->mdev, rq->tirn, to_mpd(pd)->uid); 1343 } 1344 1345 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1346 struct mlx5_ib_rq *rq, u32 tdn, 1347 u32 *qp_flags_en, struct ib_pd *pd, 1348 u32 *out) 1349 { 1350 u8 lb_flag = 0; 1351 u32 *in; 1352 void *tirc; 1353 int inlen; 1354 int err; 1355 1356 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1357 in = kvzalloc(inlen, GFP_KERNEL); 1358 if (!in) 1359 return -ENOMEM; 1360 1361 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid); 1362 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1363 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT); 1364 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn); 1365 MLX5_SET(tirc, tirc, transport_domain, tdn); 1366 if (*qp_flags_en & MLX5_QP_FLAG_TUNNEL_OFFLOADS) 1367 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 1368 1369 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) 1370 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1371 1372 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) 1373 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST; 1374 1375 if (dev->is_rep) { 1376 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1377 *qp_flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC; 1378 } 1379 1380 MLX5_SET(tirc, tirc, self_lb_block, lb_flag); 1381 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1382 err = mlx5_cmd_exec_inout(dev->mdev, create_tir, in, out); 1383 rq->tirn = MLX5_GET(create_tir_out, out, tirn); 1384 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) { 1385 err = mlx5_ib_enable_lb(dev, false, true); 1386 1387 if (err) 1388 destroy_raw_packet_qp_tir(dev, rq, 0, pd); 1389 } 1390 kvfree(in); 1391 1392 return err; 1393 } 1394 1395 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1396 u32 *in, size_t inlen, 1397 struct ib_pd *pd, 1398 struct ib_udata *udata, 1399 struct mlx5_ib_create_qp_resp *resp) 1400 { 1401 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1402 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1403 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1404 struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context( 1405 udata, struct mlx5_ib_ucontext, ibucontext); 1406 int err; 1407 u32 tdn = mucontext->tdn; 1408 u16 uid = to_mpd(pd)->uid; 1409 u32 out[MLX5_ST_SZ_DW(create_tir_out)] = {}; 1410 1411 if (!qp->sq.wqe_cnt && !qp->rq.wqe_cnt) 1412 return -EINVAL; 1413 if (qp->sq.wqe_cnt) { 1414 err = create_raw_packet_qp_tis(dev, qp, sq, tdn, pd); 1415 if (err) 1416 return err; 1417 1418 err = create_raw_packet_qp_sq(dev, udata, sq, in, pd); 1419 if (err) 1420 goto err_destroy_tis; 1421 1422 if (uid) { 1423 resp->tisn = sq->tisn; 1424 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TISN; 1425 resp->sqn = sq->base.mqp.qpn; 1426 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_SQN; 1427 } 1428 1429 sq->base.container_mibqp = qp; 1430 sq->base.mqp.event = mlx5_ib_qp_event; 1431 } 1432 1433 if (qp->rq.wqe_cnt) { 1434 rq->base.container_mibqp = qp; 1435 1436 if (qp->flags & IB_QP_CREATE_CVLAN_STRIPPING) 1437 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING; 1438 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) 1439 rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING; 1440 err = create_raw_packet_qp_rq(dev, rq, in, pd); 1441 if (err) 1442 goto err_destroy_sq; 1443 1444 err = create_raw_packet_qp_tir(dev, rq, tdn, &qp->flags_en, pd, 1445 out); 1446 if (err) 1447 goto err_destroy_rq; 1448 1449 if (uid) { 1450 resp->rqn = rq->base.mqp.qpn; 1451 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_RQN; 1452 resp->tirn = rq->tirn; 1453 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN; 1454 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) || 1455 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner_v2)) { 1456 resp->tir_icm_addr = MLX5_GET( 1457 create_tir_out, out, icm_address_31_0); 1458 resp->tir_icm_addr |= 1459 (u64)MLX5_GET(create_tir_out, out, 1460 icm_address_39_32) 1461 << 32; 1462 resp->tir_icm_addr |= 1463 (u64)MLX5_GET(create_tir_out, out, 1464 icm_address_63_40) 1465 << 40; 1466 resp->comp_mask |= 1467 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR; 1468 } 1469 } 1470 } 1471 1472 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn : 1473 rq->base.mqp.qpn; 1474 return 0; 1475 1476 err_destroy_rq: 1477 destroy_raw_packet_qp_rq(dev, rq); 1478 err_destroy_sq: 1479 if (!qp->sq.wqe_cnt) 1480 return err; 1481 destroy_raw_packet_qp_sq(dev, sq); 1482 err_destroy_tis: 1483 destroy_raw_packet_qp_tis(dev, sq, pd); 1484 1485 return err; 1486 } 1487 1488 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev, 1489 struct mlx5_ib_qp *qp) 1490 { 1491 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1492 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1493 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1494 1495 if (qp->rq.wqe_cnt) { 1496 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, qp->ibqp.pd); 1497 destroy_raw_packet_qp_rq(dev, rq); 1498 } 1499 1500 if (qp->sq.wqe_cnt) { 1501 destroy_raw_packet_qp_sq(dev, sq); 1502 destroy_raw_packet_qp_tis(dev, sq, qp->ibqp.pd); 1503 } 1504 } 1505 1506 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp, 1507 struct mlx5_ib_raw_packet_qp *raw_packet_qp) 1508 { 1509 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1510 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1511 1512 sq->sq = &qp->sq; 1513 rq->rq = &qp->rq; 1514 sq->doorbell = &qp->db; 1515 rq->doorbell = &qp->db; 1516 } 1517 1518 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1519 { 1520 if (qp->flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 1521 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) 1522 mlx5_ib_disable_lb(dev, false, true); 1523 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, 1524 to_mpd(qp->ibqp.pd)->uid); 1525 } 1526 1527 struct mlx5_create_qp_params { 1528 struct ib_udata *udata; 1529 size_t inlen; 1530 size_t outlen; 1531 size_t ucmd_size; 1532 void *ucmd; 1533 u8 is_rss_raw : 1; 1534 struct ib_qp_init_attr *attr; 1535 u32 uidx; 1536 struct mlx5_ib_create_qp_resp resp; 1537 }; 1538 1539 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct ib_pd *pd, 1540 struct mlx5_ib_qp *qp, 1541 struct mlx5_create_qp_params *params) 1542 { 1543 struct ib_qp_init_attr *init_attr = params->attr; 1544 struct mlx5_ib_create_qp_rss *ucmd = params->ucmd; 1545 struct ib_udata *udata = params->udata; 1546 struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context( 1547 udata, struct mlx5_ib_ucontext, ibucontext); 1548 int inlen; 1549 int outlen; 1550 int err; 1551 u32 *in; 1552 u32 *out; 1553 void *tirc; 1554 void *hfso; 1555 u32 selected_fields = 0; 1556 u32 outer_l4; 1557 u32 tdn = mucontext->tdn; 1558 u8 lb_flag = 0; 1559 1560 if (ucmd->comp_mask) { 1561 mlx5_ib_dbg(dev, "invalid comp mask\n"); 1562 return -EOPNOTSUPP; 1563 } 1564 1565 if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_INNER && 1566 !(ucmd->flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) { 1567 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n"); 1568 return -EOPNOTSUPP; 1569 } 1570 1571 if (dev->is_rep) 1572 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC; 1573 1574 if (qp->flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) 1575 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1576 1577 if (qp->flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) 1578 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST; 1579 1580 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1581 outlen = MLX5_ST_SZ_BYTES(create_tir_out); 1582 in = kvzalloc(inlen + outlen, GFP_KERNEL); 1583 if (!in) 1584 return -ENOMEM; 1585 1586 out = in + MLX5_ST_SZ_DW(create_tir_in); 1587 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid); 1588 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1589 MLX5_SET(tirc, tirc, disp_type, 1590 MLX5_TIRC_DISP_TYPE_INDIRECT); 1591 MLX5_SET(tirc, tirc, indirect_table, 1592 init_attr->rwq_ind_tbl->ind_tbl_num); 1593 MLX5_SET(tirc, tirc, transport_domain, tdn); 1594 1595 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1596 1597 if (ucmd->flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) 1598 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 1599 1600 MLX5_SET(tirc, tirc, self_lb_block, lb_flag); 1601 1602 if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_INNER) 1603 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner); 1604 else 1605 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1606 1607 switch (ucmd->rx_hash_function) { 1608 case MLX5_RX_HASH_FUNC_TOEPLITZ: 1609 { 1610 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key); 1611 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key); 1612 1613 if (len != ucmd->rx_key_len) { 1614 err = -EINVAL; 1615 goto err; 1616 } 1617 1618 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ); 1619 memcpy(rss_key, ucmd->rx_hash_key, len); 1620 break; 1621 } 1622 default: 1623 err = -EOPNOTSUPP; 1624 goto err; 1625 } 1626 1627 if (!ucmd->rx_hash_fields_mask) { 1628 /* special case when this TIR serves as steering entry without hashing */ 1629 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size) 1630 goto create_tir; 1631 err = -EINVAL; 1632 goto err; 1633 } 1634 1635 if (((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1636 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) && 1637 ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1638 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) { 1639 err = -EINVAL; 1640 goto err; 1641 } 1642 1643 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */ 1644 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1645 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) 1646 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1647 MLX5_L3_PROT_TYPE_IPV4); 1648 else if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1649 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1650 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1651 MLX5_L3_PROT_TYPE_IPV6); 1652 1653 outer_l4 = ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1654 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) 1655 << 0 | 1656 ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1657 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1658 << 1 | 1659 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2; 1660 1661 /* Check that only one l4 protocol is set */ 1662 if (outer_l4 & (outer_l4 - 1)) { 1663 err = -EINVAL; 1664 goto err; 1665 } 1666 1667 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */ 1668 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1669 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) 1670 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1671 MLX5_L4_PROT_TYPE_TCP); 1672 else if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1673 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1674 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1675 MLX5_L4_PROT_TYPE_UDP); 1676 1677 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1678 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6)) 1679 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP; 1680 1681 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) || 1682 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1683 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP; 1684 1685 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1686 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP)) 1687 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT; 1688 1689 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) || 1690 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1691 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT; 1692 1693 if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) 1694 selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI; 1695 1696 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields); 1697 1698 create_tir: 1699 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1700 err = mlx5_cmd_exec_inout(dev->mdev, create_tir, in, out); 1701 1702 qp->rss_qp.tirn = MLX5_GET(create_tir_out, out, tirn); 1703 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) { 1704 err = mlx5_ib_enable_lb(dev, false, true); 1705 1706 if (err) 1707 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, 1708 to_mpd(pd)->uid); 1709 } 1710 1711 if (err) 1712 goto err; 1713 1714 if (mucontext->devx_uid) { 1715 params->resp.comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN; 1716 params->resp.tirn = qp->rss_qp.tirn; 1717 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) || 1718 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner_v2)) { 1719 params->resp.tir_icm_addr = 1720 MLX5_GET(create_tir_out, out, icm_address_31_0); 1721 params->resp.tir_icm_addr |= 1722 (u64)MLX5_GET(create_tir_out, out, 1723 icm_address_39_32) 1724 << 32; 1725 params->resp.tir_icm_addr |= 1726 (u64)MLX5_GET(create_tir_out, out, 1727 icm_address_63_40) 1728 << 40; 1729 params->resp.comp_mask |= 1730 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR; 1731 } 1732 } 1733 1734 kvfree(in); 1735 /* qpn is reserved for that QP */ 1736 qp->trans_qp.base.mqp.qpn = 0; 1737 qp->is_rss = true; 1738 return 0; 1739 1740 err: 1741 kvfree(in); 1742 return err; 1743 } 1744 1745 static void configure_requester_scat_cqe(struct mlx5_ib_dev *dev, 1746 struct mlx5_ib_qp *qp, 1747 struct ib_qp_init_attr *init_attr, 1748 void *qpc) 1749 { 1750 int scqe_sz; 1751 bool allow_scat_cqe = false; 1752 1753 allow_scat_cqe = qp->flags_en & MLX5_QP_FLAG_ALLOW_SCATTER_CQE; 1754 1755 if (!allow_scat_cqe && init_attr->sq_sig_type != IB_SIGNAL_ALL_WR) 1756 return; 1757 1758 scqe_sz = mlx5_ib_get_cqe_size(init_attr->send_cq); 1759 if (scqe_sz == 128) { 1760 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE); 1761 return; 1762 } 1763 1764 if (init_attr->qp_type != MLX5_IB_QPT_DCI || 1765 MLX5_CAP_GEN(dev->mdev, dc_req_scat_data_cqe)) 1766 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE); 1767 } 1768 1769 static int atomic_size_to_mode(int size_mask) 1770 { 1771 /* driver does not support atomic_size > 256B 1772 * and does not know how to translate bigger sizes 1773 */ 1774 int supported_size_mask = size_mask & 0x1ff; 1775 int log_max_size; 1776 1777 if (!supported_size_mask) 1778 return -EOPNOTSUPP; 1779 1780 log_max_size = __fls(supported_size_mask); 1781 1782 if (log_max_size > 3) 1783 return log_max_size; 1784 1785 return MLX5_ATOMIC_MODE_8B; 1786 } 1787 1788 static int get_atomic_mode(struct mlx5_ib_dev *dev, 1789 enum ib_qp_type qp_type) 1790 { 1791 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 1792 u8 atomic = MLX5_CAP_GEN(dev->mdev, atomic); 1793 int atomic_mode = -EOPNOTSUPP; 1794 int atomic_size_mask; 1795 1796 if (!atomic) 1797 return -EOPNOTSUPP; 1798 1799 if (qp_type == MLX5_IB_QPT_DCT) 1800 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc); 1801 else 1802 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 1803 1804 if ((atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP) || 1805 (atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD)) 1806 atomic_mode = atomic_size_to_mode(atomic_size_mask); 1807 1808 if (atomic_mode <= 0 && 1809 (atomic_operations & MLX5_ATOMIC_OPS_CMP_SWAP && 1810 atomic_operations & MLX5_ATOMIC_OPS_FETCH_ADD)) 1811 atomic_mode = MLX5_ATOMIC_MODE_IB_COMP; 1812 1813 return atomic_mode; 1814 } 1815 1816 static int create_xrc_tgt_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1817 struct mlx5_create_qp_params *params) 1818 { 1819 struct mlx5_ib_create_qp *ucmd = params->ucmd; 1820 struct ib_qp_init_attr *attr = params->attr; 1821 u32 uidx = params->uidx; 1822 struct mlx5_ib_resources *devr = &dev->devr; 1823 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {}; 1824 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 1825 struct mlx5_core_dev *mdev = dev->mdev; 1826 struct mlx5_ib_qp_base *base; 1827 unsigned long flags; 1828 void *qpc; 1829 u32 *in; 1830 int err; 1831 1832 if (attr->sq_sig_type == IB_SIGNAL_ALL_WR) 1833 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 1834 1835 in = kvzalloc(inlen, GFP_KERNEL); 1836 if (!in) 1837 return -ENOMEM; 1838 1839 if (MLX5_CAP_GEN(mdev, ece_support) && ucmd) 1840 MLX5_SET(create_qp_in, in, ece, ucmd->ece_options); 1841 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 1842 1843 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_XRC); 1844 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 1845 MLX5_SET(qpc, qpc, pd, to_mpd(devr->p0)->pdn); 1846 1847 if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) 1848 MLX5_SET(qpc, qpc, block_lb_mc, 1); 1849 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL) 1850 MLX5_SET(qpc, qpc, cd_master, 1); 1851 if (qp->flags & IB_QP_CREATE_MANAGED_SEND) 1852 MLX5_SET(qpc, qpc, cd_slave_send, 1); 1853 if (qp->flags & IB_QP_CREATE_MANAGED_RECV) 1854 MLX5_SET(qpc, qpc, cd_slave_receive, 1); 1855 1856 MLX5_SET(qpc, qpc, rq_type, MLX5_SRQ_RQ); 1857 MLX5_SET(qpc, qpc, no_sq, 1); 1858 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 1859 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn); 1860 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 1861 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(attr->xrcd)->xrcdn); 1862 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 1863 1864 /* 0xffffff means we ask to work with cqe version 0 */ 1865 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 1866 MLX5_SET(qpc, qpc, user_index, uidx); 1867 1868 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) { 1869 MLX5_SET(qpc, qpc, end_padding_mode, 1870 MLX5_WQ_END_PAD_MODE_ALIGN); 1871 /* Special case to clean flag */ 1872 qp->flags &= ~IB_QP_CREATE_PCI_WRITE_END_PADDING; 1873 } 1874 1875 base = &qp->trans_qp.base; 1876 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out); 1877 kvfree(in); 1878 if (err) 1879 return err; 1880 1881 base->container_mibqp = qp; 1882 base->mqp.event = mlx5_ib_qp_event; 1883 if (MLX5_CAP_GEN(mdev, ece_support)) 1884 params->resp.ece_options = MLX5_GET(create_qp_out, out, ece); 1885 1886 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 1887 list_add_tail(&qp->qps_list, &dev->qp_list); 1888 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 1889 1890 qp->trans_qp.xrcdn = to_mxrcd(attr->xrcd)->xrcdn; 1891 return 0; 1892 } 1893 1894 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 1895 struct mlx5_ib_qp *qp, 1896 struct mlx5_create_qp_params *params) 1897 { 1898 struct ib_qp_init_attr *init_attr = params->attr; 1899 struct mlx5_ib_create_qp *ucmd = params->ucmd; 1900 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {}; 1901 struct ib_udata *udata = params->udata; 1902 u32 uidx = params->uidx; 1903 struct mlx5_ib_resources *devr = &dev->devr; 1904 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 1905 struct mlx5_core_dev *mdev = dev->mdev; 1906 struct mlx5_ib_cq *send_cq; 1907 struct mlx5_ib_cq *recv_cq; 1908 unsigned long flags; 1909 struct mlx5_ib_qp_base *base; 1910 int mlx5_st; 1911 void *qpc; 1912 u32 *in; 1913 int err; 1914 1915 spin_lock_init(&qp->sq.lock); 1916 spin_lock_init(&qp->rq.lock); 1917 1918 mlx5_st = to_mlx5_st(qp->type); 1919 if (mlx5_st < 0) 1920 return -EINVAL; 1921 1922 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 1923 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 1924 1925 if (qp->flags & IB_QP_CREATE_SOURCE_QPN) 1926 qp->underlay_qpn = init_attr->source_qpn; 1927 1928 base = (init_attr->qp_type == IB_QPT_RAW_PACKET || 1929 qp->flags & IB_QP_CREATE_SOURCE_QPN) ? 1930 &qp->raw_packet_qp.rq.base : 1931 &qp->trans_qp.base; 1932 1933 qp->has_rq = qp_has_rq(init_attr); 1934 err = set_rq_size(dev, &init_attr->cap, qp->has_rq, qp, ucmd); 1935 if (err) { 1936 mlx5_ib_dbg(dev, "err %d\n", err); 1937 return err; 1938 } 1939 1940 if (ucmd->rq_wqe_shift != qp->rq.wqe_shift || 1941 ucmd->rq_wqe_count != qp->rq.wqe_cnt) 1942 return -EINVAL; 1943 1944 if (ucmd->sq_wqe_count > (1 << MLX5_CAP_GEN(mdev, log_max_qp_sz))) 1945 return -EINVAL; 1946 1947 err = _create_user_qp(dev, pd, qp, udata, init_attr, &in, ¶ms->resp, 1948 &inlen, base, ucmd); 1949 if (err) 1950 return err; 1951 1952 if (is_sqp(init_attr->qp_type)) 1953 qp->port = init_attr->port_num; 1954 1955 if (MLX5_CAP_GEN(mdev, ece_support)) 1956 MLX5_SET(create_qp_in, in, ece, ucmd->ece_options); 1957 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 1958 1959 MLX5_SET(qpc, qpc, st, mlx5_st); 1960 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 1961 MLX5_SET(qpc, qpc, pd, to_mpd(pd)->pdn); 1962 1963 if (qp->flags_en & MLX5_QP_FLAG_SIGNATURE) 1964 MLX5_SET(qpc, qpc, wq_signature, 1); 1965 1966 if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) 1967 MLX5_SET(qpc, qpc, block_lb_mc, 1); 1968 1969 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL) 1970 MLX5_SET(qpc, qpc, cd_master, 1); 1971 if (qp->flags & IB_QP_CREATE_MANAGED_SEND) 1972 MLX5_SET(qpc, qpc, cd_slave_send, 1); 1973 if (qp->flags & IB_QP_CREATE_MANAGED_RECV) 1974 MLX5_SET(qpc, qpc, cd_slave_receive, 1); 1975 if (qp->flags_en & MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE) 1976 MLX5_SET(qpc, qpc, req_e2e_credit_mode, 1); 1977 if ((qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) && 1978 (init_attr->qp_type == IB_QPT_RC || 1979 init_attr->qp_type == IB_QPT_UC)) { 1980 int rcqe_sz = mlx5_ib_get_cqe_size(init_attr->recv_cq); 1981 1982 MLX5_SET(qpc, qpc, cs_res, 1983 rcqe_sz == 128 ? MLX5_RES_SCAT_DATA64_CQE : 1984 MLX5_RES_SCAT_DATA32_CQE); 1985 } 1986 if ((qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) && 1987 (qp->type == MLX5_IB_QPT_DCI || qp->type == IB_QPT_RC)) 1988 configure_requester_scat_cqe(dev, qp, init_attr, qpc); 1989 1990 if (qp->rq.wqe_cnt) { 1991 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); 1992 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); 1993 } 1994 1995 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr)); 1996 1997 if (qp->sq.wqe_cnt) { 1998 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); 1999 } else { 2000 MLX5_SET(qpc, qpc, no_sq, 1); 2001 if (init_attr->srq && 2002 init_attr->srq->srq_type == IB_SRQT_TM) 2003 MLX5_SET(qpc, qpc, offload_type, 2004 MLX5_QPC_OFFLOAD_TYPE_RNDV); 2005 } 2006 2007 /* Set default resources */ 2008 switch (init_attr->qp_type) { 2009 case IB_QPT_XRC_INI: 2010 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 2011 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn1); 2012 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 2013 break; 2014 default: 2015 if (init_attr->srq) { 2016 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn0); 2017 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn); 2018 } else { 2019 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn1); 2020 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn); 2021 } 2022 } 2023 2024 if (init_attr->send_cq) 2025 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn); 2026 2027 if (init_attr->recv_cq) 2028 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn); 2029 2030 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 2031 2032 /* 0xffffff means we ask to work with cqe version 0 */ 2033 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 2034 MLX5_SET(qpc, qpc, user_index, uidx); 2035 2036 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING && 2037 init_attr->qp_type != IB_QPT_RAW_PACKET) { 2038 MLX5_SET(qpc, qpc, end_padding_mode, 2039 MLX5_WQ_END_PAD_MODE_ALIGN); 2040 /* Special case to clean flag */ 2041 qp->flags &= ~IB_QP_CREATE_PCI_WRITE_END_PADDING; 2042 } 2043 2044 if (init_attr->qp_type == IB_QPT_RAW_PACKET || 2045 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 2046 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd->sq_buf_addr; 2047 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp); 2048 err = create_raw_packet_qp(dev, qp, in, inlen, pd, udata, 2049 ¶ms->resp); 2050 } else 2051 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out); 2052 2053 kvfree(in); 2054 if (err) 2055 goto err_create; 2056 2057 base->container_mibqp = qp; 2058 base->mqp.event = mlx5_ib_qp_event; 2059 if (MLX5_CAP_GEN(mdev, ece_support)) 2060 params->resp.ece_options = MLX5_GET(create_qp_out, out, ece); 2061 2062 get_cqs(qp->type, init_attr->send_cq, init_attr->recv_cq, 2063 &send_cq, &recv_cq); 2064 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2065 mlx5_ib_lock_cqs(send_cq, recv_cq); 2066 /* Maintain device to QPs access, needed for further handling via reset 2067 * flow 2068 */ 2069 list_add_tail(&qp->qps_list, &dev->qp_list); 2070 /* Maintain CQ to QPs access, needed for further handling via reset flow 2071 */ 2072 if (send_cq) 2073 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); 2074 if (recv_cq) 2075 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); 2076 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2077 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2078 2079 return 0; 2080 2081 err_create: 2082 destroy_qp(dev, qp, base, udata); 2083 return err; 2084 } 2085 2086 static int create_kernel_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2087 struct mlx5_ib_qp *qp, 2088 struct mlx5_create_qp_params *params) 2089 { 2090 struct ib_qp_init_attr *attr = params->attr; 2091 u32 uidx = params->uidx; 2092 struct mlx5_ib_resources *devr = &dev->devr; 2093 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {}; 2094 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 2095 struct mlx5_core_dev *mdev = dev->mdev; 2096 struct mlx5_ib_cq *send_cq; 2097 struct mlx5_ib_cq *recv_cq; 2098 unsigned long flags; 2099 struct mlx5_ib_qp_base *base; 2100 int mlx5_st; 2101 void *qpc; 2102 u32 *in; 2103 int err; 2104 2105 spin_lock_init(&qp->sq.lock); 2106 spin_lock_init(&qp->rq.lock); 2107 2108 mlx5_st = to_mlx5_st(qp->type); 2109 if (mlx5_st < 0) 2110 return -EINVAL; 2111 2112 if (attr->sq_sig_type == IB_SIGNAL_ALL_WR) 2113 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 2114 2115 base = &qp->trans_qp.base; 2116 2117 qp->has_rq = qp_has_rq(attr); 2118 err = set_rq_size(dev, &attr->cap, qp->has_rq, qp, NULL); 2119 if (err) { 2120 mlx5_ib_dbg(dev, "err %d\n", err); 2121 return err; 2122 } 2123 2124 err = _create_kernel_qp(dev, attr, qp, &in, &inlen, base); 2125 if (err) 2126 return err; 2127 2128 if (is_sqp(attr->qp_type)) 2129 qp->port = attr->port_num; 2130 2131 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2132 2133 MLX5_SET(qpc, qpc, st, mlx5_st); 2134 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2135 2136 if (attr->qp_type != MLX5_IB_QPT_REG_UMR) 2137 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn); 2138 else 2139 MLX5_SET(qpc, qpc, latency_sensitive, 1); 2140 2141 2142 if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) 2143 MLX5_SET(qpc, qpc, block_lb_mc, 1); 2144 2145 if (qp->rq.wqe_cnt) { 2146 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); 2147 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); 2148 } 2149 2150 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, attr)); 2151 2152 if (qp->sq.wqe_cnt) 2153 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); 2154 else 2155 MLX5_SET(qpc, qpc, no_sq, 1); 2156 2157 if (attr->srq) { 2158 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn0); 2159 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, 2160 to_msrq(attr->srq)->msrq.srqn); 2161 } else { 2162 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn1); 2163 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, 2164 to_msrq(devr->s1)->msrq.srqn); 2165 } 2166 2167 if (attr->send_cq) 2168 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(attr->send_cq)->mcq.cqn); 2169 2170 if (attr->recv_cq) 2171 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(attr->recv_cq)->mcq.cqn); 2172 2173 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 2174 2175 /* 0xffffff means we ask to work with cqe version 0 */ 2176 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 2177 MLX5_SET(qpc, qpc, user_index, uidx); 2178 2179 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */ 2180 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) 2181 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1); 2182 2183 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out); 2184 kvfree(in); 2185 if (err) 2186 goto err_create; 2187 2188 base->container_mibqp = qp; 2189 base->mqp.event = mlx5_ib_qp_event; 2190 2191 get_cqs(qp->type, attr->send_cq, attr->recv_cq, 2192 &send_cq, &recv_cq); 2193 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2194 mlx5_ib_lock_cqs(send_cq, recv_cq); 2195 /* Maintain device to QPs access, needed for further handling via reset 2196 * flow 2197 */ 2198 list_add_tail(&qp->qps_list, &dev->qp_list); 2199 /* Maintain CQ to QPs access, needed for further handling via reset flow 2200 */ 2201 if (send_cq) 2202 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); 2203 if (recv_cq) 2204 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); 2205 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2206 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2207 2208 return 0; 2209 2210 err_create: 2211 destroy_qp(dev, qp, base, NULL); 2212 return err; 2213 } 2214 2215 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 2216 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 2217 { 2218 if (send_cq) { 2219 if (recv_cq) { 2220 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 2221 spin_lock(&send_cq->lock); 2222 spin_lock_nested(&recv_cq->lock, 2223 SINGLE_DEPTH_NESTING); 2224 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 2225 spin_lock(&send_cq->lock); 2226 __acquire(&recv_cq->lock); 2227 } else { 2228 spin_lock(&recv_cq->lock); 2229 spin_lock_nested(&send_cq->lock, 2230 SINGLE_DEPTH_NESTING); 2231 } 2232 } else { 2233 spin_lock(&send_cq->lock); 2234 __acquire(&recv_cq->lock); 2235 } 2236 } else if (recv_cq) { 2237 spin_lock(&recv_cq->lock); 2238 __acquire(&send_cq->lock); 2239 } else { 2240 __acquire(&send_cq->lock); 2241 __acquire(&recv_cq->lock); 2242 } 2243 } 2244 2245 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 2246 __releases(&send_cq->lock) __releases(&recv_cq->lock) 2247 { 2248 if (send_cq) { 2249 if (recv_cq) { 2250 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 2251 spin_unlock(&recv_cq->lock); 2252 spin_unlock(&send_cq->lock); 2253 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 2254 __release(&recv_cq->lock); 2255 spin_unlock(&send_cq->lock); 2256 } else { 2257 spin_unlock(&send_cq->lock); 2258 spin_unlock(&recv_cq->lock); 2259 } 2260 } else { 2261 __release(&recv_cq->lock); 2262 spin_unlock(&send_cq->lock); 2263 } 2264 } else if (recv_cq) { 2265 __release(&send_cq->lock); 2266 spin_unlock(&recv_cq->lock); 2267 } else { 2268 __release(&recv_cq->lock); 2269 __release(&send_cq->lock); 2270 } 2271 } 2272 2273 static void get_cqs(enum ib_qp_type qp_type, 2274 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 2275 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq) 2276 { 2277 switch (qp_type) { 2278 case IB_QPT_XRC_TGT: 2279 *send_cq = NULL; 2280 *recv_cq = NULL; 2281 break; 2282 case MLX5_IB_QPT_REG_UMR: 2283 case IB_QPT_XRC_INI: 2284 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 2285 *recv_cq = NULL; 2286 break; 2287 2288 case IB_QPT_SMI: 2289 case MLX5_IB_QPT_HW_GSI: 2290 case IB_QPT_RC: 2291 case IB_QPT_UC: 2292 case IB_QPT_UD: 2293 case IB_QPT_RAW_PACKET: 2294 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 2295 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL; 2296 break; 2297 default: 2298 *send_cq = NULL; 2299 *recv_cq = NULL; 2300 break; 2301 } 2302 } 2303 2304 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2305 const struct mlx5_modify_raw_qp_param *raw_qp_param, 2306 u8 lag_tx_affinity); 2307 2308 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2309 struct ib_udata *udata) 2310 { 2311 struct mlx5_ib_cq *send_cq, *recv_cq; 2312 struct mlx5_ib_qp_base *base; 2313 unsigned long flags; 2314 int err; 2315 2316 if (qp->is_rss) { 2317 destroy_rss_raw_qp_tir(dev, qp); 2318 return; 2319 } 2320 2321 base = (qp->type == IB_QPT_RAW_PACKET || 2322 qp->flags & IB_QP_CREATE_SOURCE_QPN) ? 2323 &qp->raw_packet_qp.rq.base : 2324 &qp->trans_qp.base; 2325 2326 if (qp->state != IB_QPS_RESET) { 2327 if (qp->type != IB_QPT_RAW_PACKET && 2328 !(qp->flags & IB_QP_CREATE_SOURCE_QPN)) { 2329 err = mlx5_core_qp_modify(dev, MLX5_CMD_OP_2RST_QP, 0, 2330 NULL, &base->mqp, NULL); 2331 } else { 2332 struct mlx5_modify_raw_qp_param raw_qp_param = { 2333 .operation = MLX5_CMD_OP_2RST_QP 2334 }; 2335 2336 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0); 2337 } 2338 if (err) 2339 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n", 2340 base->mqp.qpn); 2341 } 2342 2343 get_cqs(qp->type, qp->ibqp.send_cq, qp->ibqp.recv_cq, &send_cq, 2344 &recv_cq); 2345 2346 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2347 mlx5_ib_lock_cqs(send_cq, recv_cq); 2348 /* del from lists under both locks above to protect reset flow paths */ 2349 list_del(&qp->qps_list); 2350 if (send_cq) 2351 list_del(&qp->cq_send_list); 2352 2353 if (recv_cq) 2354 list_del(&qp->cq_recv_list); 2355 2356 if (!udata) { 2357 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 2358 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL); 2359 if (send_cq != recv_cq) 2360 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn, 2361 NULL); 2362 } 2363 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2364 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2365 2366 if (qp->type == IB_QPT_RAW_PACKET || 2367 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 2368 destroy_raw_packet_qp(dev, qp); 2369 } else { 2370 err = mlx5_core_destroy_qp(dev, &base->mqp); 2371 if (err) 2372 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n", 2373 base->mqp.qpn); 2374 } 2375 2376 destroy_qp(dev, qp, base, udata); 2377 } 2378 2379 static int create_dct(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2380 struct mlx5_ib_qp *qp, 2381 struct mlx5_create_qp_params *params) 2382 { 2383 struct ib_qp_init_attr *attr = params->attr; 2384 struct mlx5_ib_create_qp *ucmd = params->ucmd; 2385 u32 uidx = params->uidx; 2386 void *dctc; 2387 2388 if (mlx5_lag_is_active(dev->mdev) && !MLX5_CAP_GEN(dev->mdev, lag_dct)) 2389 return -EOPNOTSUPP; 2390 2391 qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL); 2392 if (!qp->dct.in) 2393 return -ENOMEM; 2394 2395 MLX5_SET(create_dct_in, qp->dct.in, uid, to_mpd(pd)->uid); 2396 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); 2397 MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn); 2398 MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn); 2399 MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn); 2400 MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key); 2401 MLX5_SET(dctc, dctc, user_index, uidx); 2402 if (MLX5_CAP_GEN(dev->mdev, ece_support)) 2403 MLX5_SET(dctc, dctc, ece, ucmd->ece_options); 2404 2405 if (qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) { 2406 int rcqe_sz = mlx5_ib_get_cqe_size(attr->recv_cq); 2407 2408 if (rcqe_sz == 128) 2409 MLX5_SET(dctc, dctc, cs_res, MLX5_RES_SCAT_DATA64_CQE); 2410 } 2411 2412 qp->state = IB_QPS_RESET; 2413 rdma_restrack_no_track(&qp->ibqp.res); 2414 return 0; 2415 } 2416 2417 static int check_qp_type(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, 2418 enum ib_qp_type *type) 2419 { 2420 if (attr->qp_type == IB_QPT_DRIVER && !MLX5_CAP_GEN(dev->mdev, dct)) 2421 goto out; 2422 2423 switch (attr->qp_type) { 2424 case IB_QPT_XRC_TGT: 2425 case IB_QPT_XRC_INI: 2426 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 2427 goto out; 2428 fallthrough; 2429 case IB_QPT_RC: 2430 case IB_QPT_UC: 2431 case IB_QPT_SMI: 2432 case MLX5_IB_QPT_HW_GSI: 2433 case IB_QPT_DRIVER: 2434 case IB_QPT_GSI: 2435 case IB_QPT_RAW_PACKET: 2436 case IB_QPT_UD: 2437 case MLX5_IB_QPT_REG_UMR: 2438 break; 2439 default: 2440 goto out; 2441 } 2442 2443 *type = attr->qp_type; 2444 return 0; 2445 2446 out: 2447 mlx5_ib_dbg(dev, "Unsupported QP type %d\n", attr->qp_type); 2448 return -EOPNOTSUPP; 2449 } 2450 2451 static int check_valid_flow(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2452 struct ib_qp_init_attr *attr, 2453 struct ib_udata *udata) 2454 { 2455 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 2456 udata, struct mlx5_ib_ucontext, ibucontext); 2457 2458 if (!udata) { 2459 /* Kernel create_qp callers */ 2460 if (attr->rwq_ind_tbl) 2461 return -EOPNOTSUPP; 2462 2463 switch (attr->qp_type) { 2464 case IB_QPT_RAW_PACKET: 2465 case IB_QPT_DRIVER: 2466 return -EOPNOTSUPP; 2467 default: 2468 return 0; 2469 } 2470 } 2471 2472 /* Userspace create_qp callers */ 2473 if (attr->qp_type == IB_QPT_RAW_PACKET && !ucontext->cqe_version) { 2474 mlx5_ib_dbg(dev, 2475 "Raw Packet QP is only supported for CQE version > 0\n"); 2476 return -EINVAL; 2477 } 2478 2479 if (attr->qp_type != IB_QPT_RAW_PACKET && attr->rwq_ind_tbl) { 2480 mlx5_ib_dbg(dev, 2481 "Wrong QP type %d for the RWQ indirect table\n", 2482 attr->qp_type); 2483 return -EINVAL; 2484 } 2485 2486 /* 2487 * We don't need to see this warning, it means that kernel code 2488 * missing ib_pd. Placed here to catch developer's mistakes. 2489 */ 2490 WARN_ONCE(!pd && attr->qp_type != IB_QPT_XRC_TGT, 2491 "There is a missing PD pointer assignment\n"); 2492 return 0; 2493 } 2494 2495 static void process_vendor_flag(struct mlx5_ib_dev *dev, int *flags, int flag, 2496 bool cond, struct mlx5_ib_qp *qp) 2497 { 2498 if (!(*flags & flag)) 2499 return; 2500 2501 if (cond) { 2502 qp->flags_en |= flag; 2503 *flags &= ~flag; 2504 return; 2505 } 2506 2507 switch (flag) { 2508 case MLX5_QP_FLAG_SCATTER_CQE: 2509 case MLX5_QP_FLAG_ALLOW_SCATTER_CQE: 2510 /* 2511 * We don't return error if these flags were provided, 2512 * and mlx5 doesn't have right capability. 2513 */ 2514 *flags &= ~(MLX5_QP_FLAG_SCATTER_CQE | 2515 MLX5_QP_FLAG_ALLOW_SCATTER_CQE); 2516 return; 2517 default: 2518 break; 2519 } 2520 mlx5_ib_dbg(dev, "Vendor create QP flag 0x%X is not supported\n", flag); 2521 } 2522 2523 static int process_vendor_flags(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2524 void *ucmd, struct ib_qp_init_attr *attr) 2525 { 2526 struct mlx5_core_dev *mdev = dev->mdev; 2527 bool cond; 2528 int flags; 2529 2530 if (attr->rwq_ind_tbl) 2531 flags = ((struct mlx5_ib_create_qp_rss *)ucmd)->flags; 2532 else 2533 flags = ((struct mlx5_ib_create_qp *)ucmd)->flags; 2534 2535 switch (flags & (MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI)) { 2536 case MLX5_QP_FLAG_TYPE_DCI: 2537 qp->type = MLX5_IB_QPT_DCI; 2538 break; 2539 case MLX5_QP_FLAG_TYPE_DCT: 2540 qp->type = MLX5_IB_QPT_DCT; 2541 break; 2542 default: 2543 if (qp->type != IB_QPT_DRIVER) 2544 break; 2545 /* 2546 * It is IB_QPT_DRIVER and or no subtype or 2547 * wrong subtype were provided. 2548 */ 2549 return -EINVAL; 2550 } 2551 2552 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TYPE_DCI, true, qp); 2553 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TYPE_DCT, true, qp); 2554 2555 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_SIGNATURE, true, qp); 2556 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_SCATTER_CQE, 2557 MLX5_CAP_GEN(mdev, sctr_data_cqe), qp); 2558 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_ALLOW_SCATTER_CQE, 2559 MLX5_CAP_GEN(mdev, sctr_data_cqe), qp); 2560 2561 if (qp->type == IB_QPT_RAW_PACKET) { 2562 cond = MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan) || 2563 MLX5_CAP_ETH(mdev, tunnel_stateless_gre) || 2564 MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx); 2565 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TUNNEL_OFFLOADS, 2566 cond, qp); 2567 process_vendor_flag(dev, &flags, 2568 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC, true, 2569 qp); 2570 process_vendor_flag(dev, &flags, 2571 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC, true, 2572 qp); 2573 } 2574 2575 if (qp->type == IB_QPT_RC) 2576 process_vendor_flag(dev, &flags, 2577 MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE, 2578 MLX5_CAP_GEN(mdev, qp_packet_based), qp); 2579 2580 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_BFREG_INDEX, true, qp); 2581 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_UAR_PAGE_INDEX, true, qp); 2582 2583 cond = qp->flags_en & ~(MLX5_QP_FLAG_TUNNEL_OFFLOADS | 2584 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 2585 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC); 2586 if (attr->rwq_ind_tbl && cond) { 2587 mlx5_ib_dbg(dev, "RSS RAW QP has unsupported flags 0x%X\n", 2588 cond); 2589 return -EINVAL; 2590 } 2591 2592 if (flags) 2593 mlx5_ib_dbg(dev, "udata has unsupported flags 0x%X\n", flags); 2594 2595 return (flags) ? -EINVAL : 0; 2596 } 2597 2598 static void process_create_flag(struct mlx5_ib_dev *dev, int *flags, int flag, 2599 bool cond, struct mlx5_ib_qp *qp) 2600 { 2601 if (!(*flags & flag)) 2602 return; 2603 2604 if (cond) { 2605 qp->flags |= flag; 2606 *flags &= ~flag; 2607 return; 2608 } 2609 2610 if (flag == MLX5_IB_QP_CREATE_WC_TEST) { 2611 /* 2612 * Special case, if condition didn't meet, it won't be error, 2613 * just different in-kernel flow. 2614 */ 2615 *flags &= ~MLX5_IB_QP_CREATE_WC_TEST; 2616 return; 2617 } 2618 mlx5_ib_dbg(dev, "Verbs create QP flag 0x%X is not supported\n", flag); 2619 } 2620 2621 static int process_create_flags(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2622 struct ib_qp_init_attr *attr) 2623 { 2624 enum ib_qp_type qp_type = qp->type; 2625 struct mlx5_core_dev *mdev = dev->mdev; 2626 int create_flags = attr->create_flags; 2627 bool cond; 2628 2629 if (qp_type == MLX5_IB_QPT_DCT) 2630 return (create_flags) ? -EINVAL : 0; 2631 2632 if (qp_type == IB_QPT_RAW_PACKET && attr->rwq_ind_tbl) 2633 return (create_flags) ? -EINVAL : 0; 2634 2635 process_create_flag(dev, &create_flags, IB_QP_CREATE_NETIF_QP, 2636 mlx5_get_flow_namespace(dev->mdev, 2637 MLX5_FLOW_NAMESPACE_BYPASS), 2638 qp); 2639 process_create_flag(dev, &create_flags, 2640 IB_QP_CREATE_INTEGRITY_EN, 2641 MLX5_CAP_GEN(mdev, sho), qp); 2642 process_create_flag(dev, &create_flags, 2643 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK, 2644 MLX5_CAP_GEN(mdev, block_lb_mc), qp); 2645 process_create_flag(dev, &create_flags, IB_QP_CREATE_CROSS_CHANNEL, 2646 MLX5_CAP_GEN(mdev, cd), qp); 2647 process_create_flag(dev, &create_flags, IB_QP_CREATE_MANAGED_SEND, 2648 MLX5_CAP_GEN(mdev, cd), qp); 2649 process_create_flag(dev, &create_flags, IB_QP_CREATE_MANAGED_RECV, 2650 MLX5_CAP_GEN(mdev, cd), qp); 2651 2652 if (qp_type == IB_QPT_UD) { 2653 process_create_flag(dev, &create_flags, 2654 IB_QP_CREATE_IPOIB_UD_LSO, 2655 MLX5_CAP_GEN(mdev, ipoib_basic_offloads), 2656 qp); 2657 cond = MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_IB; 2658 process_create_flag(dev, &create_flags, IB_QP_CREATE_SOURCE_QPN, 2659 cond, qp); 2660 } 2661 2662 if (qp_type == IB_QPT_RAW_PACKET) { 2663 cond = MLX5_CAP_GEN(mdev, eth_net_offloads) && 2664 MLX5_CAP_ETH(mdev, scatter_fcs); 2665 process_create_flag(dev, &create_flags, 2666 IB_QP_CREATE_SCATTER_FCS, cond, qp); 2667 2668 cond = MLX5_CAP_GEN(mdev, eth_net_offloads) && 2669 MLX5_CAP_ETH(mdev, vlan_cap); 2670 process_create_flag(dev, &create_flags, 2671 IB_QP_CREATE_CVLAN_STRIPPING, cond, qp); 2672 } 2673 2674 process_create_flag(dev, &create_flags, 2675 IB_QP_CREATE_PCI_WRITE_END_PADDING, 2676 MLX5_CAP_GEN(mdev, end_pad), qp); 2677 2678 process_create_flag(dev, &create_flags, MLX5_IB_QP_CREATE_WC_TEST, 2679 qp_type != MLX5_IB_QPT_REG_UMR, qp); 2680 process_create_flag(dev, &create_flags, MLX5_IB_QP_CREATE_SQPN_QP1, 2681 true, qp); 2682 2683 if (create_flags) { 2684 mlx5_ib_dbg(dev, "Create QP has unsupported flags 0x%X\n", 2685 create_flags); 2686 return -EOPNOTSUPP; 2687 } 2688 return 0; 2689 } 2690 2691 static int process_udata_size(struct mlx5_ib_dev *dev, 2692 struct mlx5_create_qp_params *params) 2693 { 2694 size_t ucmd = sizeof(struct mlx5_ib_create_qp); 2695 struct ib_udata *udata = params->udata; 2696 size_t outlen = udata->outlen; 2697 size_t inlen = udata->inlen; 2698 2699 params->outlen = min(outlen, sizeof(struct mlx5_ib_create_qp_resp)); 2700 params->ucmd_size = ucmd; 2701 if (!params->is_rss_raw) { 2702 /* User has old rdma-core, which doesn't support ECE */ 2703 size_t min_inlen = 2704 offsetof(struct mlx5_ib_create_qp, ece_options); 2705 2706 /* 2707 * We will check in check_ucmd_data() that user 2708 * cleared everything after inlen. 2709 */ 2710 params->inlen = (inlen < min_inlen) ? 0 : min(inlen, ucmd); 2711 goto out; 2712 } 2713 2714 /* RSS RAW QP */ 2715 if (inlen < offsetofend(struct mlx5_ib_create_qp_rss, flags)) 2716 return -EINVAL; 2717 2718 if (outlen < offsetofend(struct mlx5_ib_create_qp_resp, bfreg_index)) 2719 return -EINVAL; 2720 2721 ucmd = sizeof(struct mlx5_ib_create_qp_rss); 2722 params->ucmd_size = ucmd; 2723 if (inlen > ucmd && !ib_is_udata_cleared(udata, ucmd, inlen - ucmd)) 2724 return -EINVAL; 2725 2726 params->inlen = min(ucmd, inlen); 2727 out: 2728 if (!params->inlen) 2729 mlx5_ib_dbg(dev, "udata is too small\n"); 2730 2731 return (params->inlen) ? 0 : -EINVAL; 2732 } 2733 2734 static int create_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2735 struct mlx5_ib_qp *qp, 2736 struct mlx5_create_qp_params *params) 2737 { 2738 int err; 2739 2740 if (params->is_rss_raw) { 2741 err = create_rss_raw_qp_tir(dev, pd, qp, params); 2742 goto out; 2743 } 2744 2745 switch (qp->type) { 2746 case MLX5_IB_QPT_DCT: 2747 err = create_dct(dev, pd, qp, params); 2748 break; 2749 case IB_QPT_XRC_TGT: 2750 err = create_xrc_tgt_qp(dev, qp, params); 2751 break; 2752 case IB_QPT_GSI: 2753 err = mlx5_ib_create_gsi(pd, qp, params->attr); 2754 break; 2755 default: 2756 if (params->udata) 2757 err = create_user_qp(dev, pd, qp, params); 2758 else 2759 err = create_kernel_qp(dev, pd, qp, params); 2760 } 2761 2762 out: 2763 if (err) { 2764 mlx5_ib_err(dev, "Create QP type %d failed\n", qp->type); 2765 return err; 2766 } 2767 2768 if (is_qp0(qp->type)) 2769 qp->ibqp.qp_num = 0; 2770 else if (is_qp1(qp->type)) 2771 qp->ibqp.qp_num = 1; 2772 else 2773 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn; 2774 2775 mlx5_ib_dbg(dev, 2776 "QP type %d, ib qpn 0x%X, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x, ece 0x%x\n", 2777 qp->type, qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn, 2778 params->attr->recv_cq ? to_mcq(params->attr->recv_cq)->mcq.cqn : 2779 -1, 2780 params->attr->send_cq ? to_mcq(params->attr->send_cq)->mcq.cqn : 2781 -1, 2782 params->resp.ece_options); 2783 2784 return 0; 2785 } 2786 2787 static int check_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2788 struct ib_qp_init_attr *attr) 2789 { 2790 int ret = 0; 2791 2792 switch (qp->type) { 2793 case MLX5_IB_QPT_DCT: 2794 ret = (!attr->srq || !attr->recv_cq) ? -EINVAL : 0; 2795 break; 2796 case MLX5_IB_QPT_DCI: 2797 ret = (attr->cap.max_recv_wr || attr->cap.max_recv_sge) ? 2798 -EINVAL : 2799 0; 2800 break; 2801 case IB_QPT_RAW_PACKET: 2802 ret = (attr->rwq_ind_tbl && attr->send_cq) ? -EINVAL : 0; 2803 break; 2804 default: 2805 break; 2806 } 2807 2808 if (ret) 2809 mlx5_ib_dbg(dev, "QP type %d has wrong attributes\n", qp->type); 2810 2811 return ret; 2812 } 2813 2814 static int get_qp_uidx(struct mlx5_ib_qp *qp, 2815 struct mlx5_create_qp_params *params) 2816 { 2817 struct mlx5_ib_create_qp *ucmd = params->ucmd; 2818 struct ib_udata *udata = params->udata; 2819 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 2820 udata, struct mlx5_ib_ucontext, ibucontext); 2821 2822 if (params->is_rss_raw) 2823 return 0; 2824 2825 return get_qp_user_index(ucontext, ucmd, sizeof(*ucmd), ¶ms->uidx); 2826 } 2827 2828 static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp) 2829 { 2830 struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device); 2831 2832 if (mqp->state == IB_QPS_RTR) { 2833 int err; 2834 2835 err = mlx5_core_destroy_dct(dev, &mqp->dct.mdct); 2836 if (err) { 2837 mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err); 2838 return err; 2839 } 2840 } 2841 2842 kfree(mqp->dct.in); 2843 kfree(mqp); 2844 return 0; 2845 } 2846 2847 static int check_ucmd_data(struct mlx5_ib_dev *dev, 2848 struct mlx5_create_qp_params *params) 2849 { 2850 struct ib_udata *udata = params->udata; 2851 size_t size, last; 2852 int ret; 2853 2854 if (params->is_rss_raw) 2855 /* 2856 * These QPs don't have "reserved" field in their 2857 * create_qp input struct, so their data is always valid. 2858 */ 2859 last = sizeof(struct mlx5_ib_create_qp_rss); 2860 else 2861 last = offsetof(struct mlx5_ib_create_qp, reserved); 2862 2863 if (udata->inlen <= last) 2864 return 0; 2865 2866 /* 2867 * User provides different create_qp structures based on the 2868 * flow and we need to know if he cleared memory after our 2869 * struct create_qp ends. 2870 */ 2871 size = udata->inlen - last; 2872 ret = ib_is_udata_cleared(params->udata, last, size); 2873 if (!ret) 2874 mlx5_ib_dbg( 2875 dev, 2876 "udata is not cleared, inlen = %zu, ucmd = %zu, last = %zu, size = %zu\n", 2877 udata->inlen, params->ucmd_size, last, size); 2878 return ret ? 0 : -EINVAL; 2879 } 2880 2881 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attr, 2882 struct ib_udata *udata) 2883 { 2884 struct mlx5_create_qp_params params = {}; 2885 struct mlx5_ib_dev *dev; 2886 struct mlx5_ib_qp *qp; 2887 enum ib_qp_type type; 2888 int err; 2889 2890 dev = pd ? to_mdev(pd->device) : 2891 to_mdev(to_mxrcd(attr->xrcd)->ibxrcd.device); 2892 2893 err = check_qp_type(dev, attr, &type); 2894 if (err) 2895 return ERR_PTR(err); 2896 2897 err = check_valid_flow(dev, pd, attr, udata); 2898 if (err) 2899 return ERR_PTR(err); 2900 2901 params.udata = udata; 2902 params.uidx = MLX5_IB_DEFAULT_UIDX; 2903 params.attr = attr; 2904 params.is_rss_raw = !!attr->rwq_ind_tbl; 2905 2906 if (udata) { 2907 err = process_udata_size(dev, ¶ms); 2908 if (err) 2909 return ERR_PTR(err); 2910 2911 err = check_ucmd_data(dev, ¶ms); 2912 if (err) 2913 return ERR_PTR(err); 2914 2915 params.ucmd = kzalloc(params.ucmd_size, GFP_KERNEL); 2916 if (!params.ucmd) 2917 return ERR_PTR(-ENOMEM); 2918 2919 err = ib_copy_from_udata(params.ucmd, udata, params.inlen); 2920 if (err) 2921 goto free_ucmd; 2922 } 2923 2924 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 2925 if (!qp) { 2926 err = -ENOMEM; 2927 goto free_ucmd; 2928 } 2929 2930 mutex_init(&qp->mutex); 2931 qp->type = type; 2932 if (udata) { 2933 err = process_vendor_flags(dev, qp, params.ucmd, attr); 2934 if (err) 2935 goto free_qp; 2936 2937 err = get_qp_uidx(qp, ¶ms); 2938 if (err) 2939 goto free_qp; 2940 } 2941 err = process_create_flags(dev, qp, attr); 2942 if (err) 2943 goto free_qp; 2944 2945 err = check_qp_attr(dev, qp, attr); 2946 if (err) 2947 goto free_qp; 2948 2949 err = create_qp(dev, pd, qp, ¶ms); 2950 if (err) 2951 goto free_qp; 2952 2953 kfree(params.ucmd); 2954 params.ucmd = NULL; 2955 2956 if (udata) 2957 /* 2958 * It is safe to copy response for all user create QP flows, 2959 * including MLX5_IB_QPT_DCT, which doesn't need it. 2960 * In that case, resp will be filled with zeros. 2961 */ 2962 err = ib_copy_to_udata(udata, ¶ms.resp, params.outlen); 2963 if (err) 2964 goto destroy_qp; 2965 2966 return &qp->ibqp; 2967 2968 destroy_qp: 2969 switch (qp->type) { 2970 case MLX5_IB_QPT_DCT: 2971 mlx5_ib_destroy_dct(qp); 2972 break; 2973 case IB_QPT_GSI: 2974 mlx5_ib_destroy_gsi(qp); 2975 break; 2976 default: 2977 /* 2978 * These lines below are temp solution till QP allocation 2979 * will be moved to be under IB/core responsiblity. 2980 */ 2981 qp->ibqp.send_cq = attr->send_cq; 2982 qp->ibqp.recv_cq = attr->recv_cq; 2983 qp->ibqp.pd = pd; 2984 destroy_qp_common(dev, qp, udata); 2985 } 2986 2987 qp = NULL; 2988 free_qp: 2989 kfree(qp); 2990 free_ucmd: 2991 kfree(params.ucmd); 2992 return ERR_PTR(err); 2993 } 2994 2995 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata) 2996 { 2997 struct mlx5_ib_dev *dev = to_mdev(qp->device); 2998 struct mlx5_ib_qp *mqp = to_mqp(qp); 2999 3000 if (unlikely(qp->qp_type == IB_QPT_GSI)) 3001 return mlx5_ib_destroy_gsi(mqp); 3002 3003 if (mqp->type == MLX5_IB_QPT_DCT) 3004 return mlx5_ib_destroy_dct(mqp); 3005 3006 destroy_qp_common(dev, mqp, udata); 3007 3008 kfree(mqp); 3009 3010 return 0; 3011 } 3012 3013 static int set_qpc_atomic_flags(struct mlx5_ib_qp *qp, 3014 const struct ib_qp_attr *attr, int attr_mask, 3015 void *qpc) 3016 { 3017 struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device); 3018 u8 dest_rd_atomic; 3019 u32 access_flags; 3020 3021 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 3022 dest_rd_atomic = attr->max_dest_rd_atomic; 3023 else 3024 dest_rd_atomic = qp->trans_qp.resp_depth; 3025 3026 if (attr_mask & IB_QP_ACCESS_FLAGS) 3027 access_flags = attr->qp_access_flags; 3028 else 3029 access_flags = qp->trans_qp.atomic_rd_en; 3030 3031 if (!dest_rd_atomic) 3032 access_flags &= IB_ACCESS_REMOTE_WRITE; 3033 3034 MLX5_SET(qpc, qpc, rre, !!(access_flags & IB_ACCESS_REMOTE_READ)); 3035 3036 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) { 3037 int atomic_mode; 3038 3039 atomic_mode = get_atomic_mode(dev, qp->ibqp.qp_type); 3040 if (atomic_mode < 0) 3041 return -EOPNOTSUPP; 3042 3043 MLX5_SET(qpc, qpc, rae, 1); 3044 MLX5_SET(qpc, qpc, atomic_mode, atomic_mode); 3045 } 3046 3047 MLX5_SET(qpc, qpc, rwe, !!(access_flags & IB_ACCESS_REMOTE_WRITE)); 3048 return 0; 3049 } 3050 3051 enum { 3052 MLX5_PATH_FLAG_FL = 1 << 0, 3053 MLX5_PATH_FLAG_FREE_AR = 1 << 1, 3054 MLX5_PATH_FLAG_COUNTER = 1 << 2, 3055 }; 3056 3057 static int ib_to_mlx5_rate_map(u8 rate) 3058 { 3059 switch (rate) { 3060 case IB_RATE_PORT_CURRENT: 3061 return 0; 3062 case IB_RATE_56_GBPS: 3063 return 1; 3064 case IB_RATE_25_GBPS: 3065 return 2; 3066 case IB_RATE_100_GBPS: 3067 return 3; 3068 case IB_RATE_200_GBPS: 3069 return 4; 3070 case IB_RATE_50_GBPS: 3071 return 5; 3072 default: 3073 return rate + MLX5_STAT_RATE_OFFSET; 3074 } 3075 3076 return 0; 3077 } 3078 3079 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate) 3080 { 3081 u32 stat_rate_support; 3082 3083 if (rate == IB_RATE_PORT_CURRENT) 3084 return 0; 3085 3086 if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_600_GBPS) 3087 return -EINVAL; 3088 3089 stat_rate_support = MLX5_CAP_GEN(dev->mdev, stat_rate_support); 3090 while (rate != IB_RATE_PORT_CURRENT && 3091 !(1 << ib_to_mlx5_rate_map(rate) & stat_rate_support)) 3092 --rate; 3093 3094 return ib_to_mlx5_rate_map(rate); 3095 } 3096 3097 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev, 3098 struct mlx5_ib_sq *sq, u8 sl, 3099 struct ib_pd *pd) 3100 { 3101 void *in; 3102 void *tisc; 3103 int inlen; 3104 int err; 3105 3106 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 3107 in = kvzalloc(inlen, GFP_KERNEL); 3108 if (!in) 3109 return -ENOMEM; 3110 3111 MLX5_SET(modify_tis_in, in, bitmask.prio, 1); 3112 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid); 3113 3114 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 3115 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1)); 3116 3117 err = mlx5_core_modify_tis(dev, sq->tisn, in); 3118 3119 kvfree(in); 3120 3121 return err; 3122 } 3123 3124 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev, 3125 struct mlx5_ib_sq *sq, u8 tx_affinity, 3126 struct ib_pd *pd) 3127 { 3128 void *in; 3129 void *tisc; 3130 int inlen; 3131 int err; 3132 3133 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 3134 in = kvzalloc(inlen, GFP_KERNEL); 3135 if (!in) 3136 return -ENOMEM; 3137 3138 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1); 3139 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid); 3140 3141 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 3142 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity); 3143 3144 err = mlx5_core_modify_tis(dev, sq->tisn, in); 3145 3146 kvfree(in); 3147 3148 return err; 3149 } 3150 3151 static void mlx5_set_path_udp_sport(void *path, const struct rdma_ah_attr *ah, 3152 u32 lqpn, u32 rqpn) 3153 3154 { 3155 u32 fl = ah->grh.flow_label; 3156 3157 if (!fl) 3158 fl = rdma_calc_flow_label(lqpn, rqpn); 3159 3160 MLX5_SET(ads, path, udp_sport, rdma_flow_label_to_udp_sport(fl)); 3161 } 3162 3163 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 3164 const struct rdma_ah_attr *ah, void *path, u8 port, 3165 int attr_mask, u32 path_flags, 3166 const struct ib_qp_attr *attr, bool alt) 3167 { 3168 const struct ib_global_route *grh = rdma_ah_read_grh(ah); 3169 int err; 3170 enum ib_gid_type gid_type; 3171 u8 ah_flags = rdma_ah_get_ah_flags(ah); 3172 u8 sl = rdma_ah_get_sl(ah); 3173 3174 if (attr_mask & IB_QP_PKEY_INDEX) 3175 MLX5_SET(ads, path, pkey_index, 3176 alt ? attr->alt_pkey_index : attr->pkey_index); 3177 3178 if (ah_flags & IB_AH_GRH) { 3179 if (grh->sgid_index >= 3180 dev->port_caps[port - 1].gid_table_len) { 3181 pr_err("sgid_index (%u) too large. max is %d\n", 3182 grh->sgid_index, 3183 dev->port_caps[port - 1].gid_table_len); 3184 return -EINVAL; 3185 } 3186 } 3187 3188 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) { 3189 if (!(ah_flags & IB_AH_GRH)) 3190 return -EINVAL; 3191 3192 ether_addr_copy(MLX5_ADDR_OF(ads, path, rmac_47_32), 3193 ah->roce.dmac); 3194 if ((qp->ibqp.qp_type == IB_QPT_RC || 3195 qp->ibqp.qp_type == IB_QPT_UC || 3196 qp->ibqp.qp_type == IB_QPT_XRC_INI || 3197 qp->ibqp.qp_type == IB_QPT_XRC_TGT) && 3198 (grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) && 3199 (attr_mask & IB_QP_DEST_QPN)) 3200 mlx5_set_path_udp_sport(path, ah, 3201 qp->ibqp.qp_num, 3202 attr->dest_qp_num); 3203 MLX5_SET(ads, path, eth_prio, sl & 0x7); 3204 gid_type = ah->grh.sgid_attr->gid_type; 3205 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) 3206 MLX5_SET(ads, path, dscp, grh->traffic_class >> 2); 3207 } else { 3208 MLX5_SET(ads, path, fl, !!(path_flags & MLX5_PATH_FLAG_FL)); 3209 MLX5_SET(ads, path, free_ar, 3210 !!(path_flags & MLX5_PATH_FLAG_FREE_AR)); 3211 MLX5_SET(ads, path, rlid, rdma_ah_get_dlid(ah)); 3212 MLX5_SET(ads, path, mlid, rdma_ah_get_path_bits(ah)); 3213 MLX5_SET(ads, path, grh, !!(ah_flags & IB_AH_GRH)); 3214 MLX5_SET(ads, path, sl, sl); 3215 } 3216 3217 if (ah_flags & IB_AH_GRH) { 3218 MLX5_SET(ads, path, src_addr_index, grh->sgid_index); 3219 MLX5_SET(ads, path, hop_limit, grh->hop_limit); 3220 MLX5_SET(ads, path, tclass, grh->traffic_class); 3221 MLX5_SET(ads, path, flow_label, grh->flow_label); 3222 memcpy(MLX5_ADDR_OF(ads, path, rgid_rip), grh->dgid.raw, 3223 sizeof(grh->dgid.raw)); 3224 } 3225 3226 err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah)); 3227 if (err < 0) 3228 return err; 3229 MLX5_SET(ads, path, stat_rate, err); 3230 MLX5_SET(ads, path, vhca_port_num, port); 3231 3232 if (attr_mask & IB_QP_TIMEOUT) 3233 MLX5_SET(ads, path, ack_timeout, 3234 alt ? attr->alt_timeout : attr->timeout); 3235 3236 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt) 3237 return modify_raw_packet_eth_prio(dev->mdev, 3238 &qp->raw_packet_qp.sq, 3239 sl & 0xf, qp->ibqp.pd); 3240 3241 return 0; 3242 } 3243 3244 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = { 3245 [MLX5_QP_STATE_INIT] = { 3246 [MLX5_QP_STATE_INIT] = { 3247 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 3248 MLX5_QP_OPTPAR_RAE | 3249 MLX5_QP_OPTPAR_RWE | 3250 MLX5_QP_OPTPAR_PKEY_INDEX | 3251 MLX5_QP_OPTPAR_PRI_PORT | 3252 MLX5_QP_OPTPAR_LAG_TX_AFF, 3253 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 3254 MLX5_QP_OPTPAR_PKEY_INDEX | 3255 MLX5_QP_OPTPAR_PRI_PORT | 3256 MLX5_QP_OPTPAR_LAG_TX_AFF, 3257 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 3258 MLX5_QP_OPTPAR_Q_KEY | 3259 MLX5_QP_OPTPAR_PRI_PORT, 3260 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE | 3261 MLX5_QP_OPTPAR_RAE | 3262 MLX5_QP_OPTPAR_RWE | 3263 MLX5_QP_OPTPAR_PKEY_INDEX | 3264 MLX5_QP_OPTPAR_PRI_PORT | 3265 MLX5_QP_OPTPAR_LAG_TX_AFF, 3266 }, 3267 [MLX5_QP_STATE_RTR] = { 3268 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3269 MLX5_QP_OPTPAR_RRE | 3270 MLX5_QP_OPTPAR_RAE | 3271 MLX5_QP_OPTPAR_RWE | 3272 MLX5_QP_OPTPAR_PKEY_INDEX | 3273 MLX5_QP_OPTPAR_LAG_TX_AFF, 3274 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3275 MLX5_QP_OPTPAR_RWE | 3276 MLX5_QP_OPTPAR_PKEY_INDEX | 3277 MLX5_QP_OPTPAR_LAG_TX_AFF, 3278 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 3279 MLX5_QP_OPTPAR_Q_KEY, 3280 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX | 3281 MLX5_QP_OPTPAR_Q_KEY, 3282 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3283 MLX5_QP_OPTPAR_RRE | 3284 MLX5_QP_OPTPAR_RAE | 3285 MLX5_QP_OPTPAR_RWE | 3286 MLX5_QP_OPTPAR_PKEY_INDEX | 3287 MLX5_QP_OPTPAR_LAG_TX_AFF, 3288 }, 3289 }, 3290 [MLX5_QP_STATE_RTR] = { 3291 [MLX5_QP_STATE_RTS] = { 3292 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3293 MLX5_QP_OPTPAR_RRE | 3294 MLX5_QP_OPTPAR_RAE | 3295 MLX5_QP_OPTPAR_RWE | 3296 MLX5_QP_OPTPAR_PM_STATE | 3297 MLX5_QP_OPTPAR_RNR_TIMEOUT, 3298 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3299 MLX5_QP_OPTPAR_RWE | 3300 MLX5_QP_OPTPAR_PM_STATE, 3301 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 3302 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3303 MLX5_QP_OPTPAR_RRE | 3304 MLX5_QP_OPTPAR_RAE | 3305 MLX5_QP_OPTPAR_RWE | 3306 MLX5_QP_OPTPAR_PM_STATE | 3307 MLX5_QP_OPTPAR_RNR_TIMEOUT, 3308 }, 3309 }, 3310 [MLX5_QP_STATE_RTS] = { 3311 [MLX5_QP_STATE_RTS] = { 3312 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 3313 MLX5_QP_OPTPAR_RAE | 3314 MLX5_QP_OPTPAR_RWE | 3315 MLX5_QP_OPTPAR_RNR_TIMEOUT | 3316 MLX5_QP_OPTPAR_PM_STATE | 3317 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 3318 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 3319 MLX5_QP_OPTPAR_PM_STATE | 3320 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 3321 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY | 3322 MLX5_QP_OPTPAR_SRQN | 3323 MLX5_QP_OPTPAR_CQN_RCV, 3324 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE | 3325 MLX5_QP_OPTPAR_RAE | 3326 MLX5_QP_OPTPAR_RWE | 3327 MLX5_QP_OPTPAR_RNR_TIMEOUT | 3328 MLX5_QP_OPTPAR_PM_STATE | 3329 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 3330 }, 3331 }, 3332 [MLX5_QP_STATE_SQER] = { 3333 [MLX5_QP_STATE_RTS] = { 3334 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 3335 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY, 3336 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE, 3337 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 3338 MLX5_QP_OPTPAR_RWE | 3339 MLX5_QP_OPTPAR_RAE | 3340 MLX5_QP_OPTPAR_RRE, 3341 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 3342 MLX5_QP_OPTPAR_RWE | 3343 MLX5_QP_OPTPAR_RAE | 3344 MLX5_QP_OPTPAR_RRE, 3345 }, 3346 }, 3347 }; 3348 3349 static int ib_nr_to_mlx5_nr(int ib_mask) 3350 { 3351 switch (ib_mask) { 3352 case IB_QP_STATE: 3353 return 0; 3354 case IB_QP_CUR_STATE: 3355 return 0; 3356 case IB_QP_EN_SQD_ASYNC_NOTIFY: 3357 return 0; 3358 case IB_QP_ACCESS_FLAGS: 3359 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE | 3360 MLX5_QP_OPTPAR_RAE; 3361 case IB_QP_PKEY_INDEX: 3362 return MLX5_QP_OPTPAR_PKEY_INDEX; 3363 case IB_QP_PORT: 3364 return MLX5_QP_OPTPAR_PRI_PORT; 3365 case IB_QP_QKEY: 3366 return MLX5_QP_OPTPAR_Q_KEY; 3367 case IB_QP_AV: 3368 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH | 3369 MLX5_QP_OPTPAR_PRI_PORT; 3370 case IB_QP_PATH_MTU: 3371 return 0; 3372 case IB_QP_TIMEOUT: 3373 return MLX5_QP_OPTPAR_ACK_TIMEOUT; 3374 case IB_QP_RETRY_CNT: 3375 return MLX5_QP_OPTPAR_RETRY_COUNT; 3376 case IB_QP_RNR_RETRY: 3377 return MLX5_QP_OPTPAR_RNR_RETRY; 3378 case IB_QP_RQ_PSN: 3379 return 0; 3380 case IB_QP_MAX_QP_RD_ATOMIC: 3381 return MLX5_QP_OPTPAR_SRA_MAX; 3382 case IB_QP_ALT_PATH: 3383 return MLX5_QP_OPTPAR_ALT_ADDR_PATH; 3384 case IB_QP_MIN_RNR_TIMER: 3385 return MLX5_QP_OPTPAR_RNR_TIMEOUT; 3386 case IB_QP_SQ_PSN: 3387 return 0; 3388 case IB_QP_MAX_DEST_RD_ATOMIC: 3389 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE | 3390 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE; 3391 case IB_QP_PATH_MIG_STATE: 3392 return MLX5_QP_OPTPAR_PM_STATE; 3393 case IB_QP_CAP: 3394 return 0; 3395 case IB_QP_DEST_QPN: 3396 return 0; 3397 } 3398 return 0; 3399 } 3400 3401 static int ib_mask_to_mlx5_opt(int ib_mask) 3402 { 3403 int result = 0; 3404 int i; 3405 3406 for (i = 0; i < 8 * sizeof(int); i++) { 3407 if ((1 << i) & ib_mask) 3408 result |= ib_nr_to_mlx5_nr(1 << i); 3409 } 3410 3411 return result; 3412 } 3413 3414 static int modify_raw_packet_qp_rq( 3415 struct mlx5_ib_dev *dev, struct mlx5_ib_rq *rq, int new_state, 3416 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd) 3417 { 3418 void *in; 3419 void *rqc; 3420 int inlen; 3421 int err; 3422 3423 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 3424 in = kvzalloc(inlen, GFP_KERNEL); 3425 if (!in) 3426 return -ENOMEM; 3427 3428 MLX5_SET(modify_rq_in, in, rq_state, rq->state); 3429 MLX5_SET(modify_rq_in, in, uid, to_mpd(pd)->uid); 3430 3431 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 3432 MLX5_SET(rqc, rqc, state, new_state); 3433 3434 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) { 3435 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 3436 MLX5_SET64(modify_rq_in, in, modify_bitmask, 3437 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 3438 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id); 3439 } else 3440 dev_info_once( 3441 &dev->ib_dev.dev, 3442 "RAW PACKET QP counters are not supported on current FW\n"); 3443 } 3444 3445 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in); 3446 if (err) 3447 goto out; 3448 3449 rq->state = new_state; 3450 3451 out: 3452 kvfree(in); 3453 return err; 3454 } 3455 3456 static int modify_raw_packet_qp_sq( 3457 struct mlx5_core_dev *dev, struct mlx5_ib_sq *sq, int new_state, 3458 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd) 3459 { 3460 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp; 3461 struct mlx5_rate_limit old_rl = ibqp->rl; 3462 struct mlx5_rate_limit new_rl = old_rl; 3463 bool new_rate_added = false; 3464 u16 rl_index = 0; 3465 void *in; 3466 void *sqc; 3467 int inlen; 3468 int err; 3469 3470 inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 3471 in = kvzalloc(inlen, GFP_KERNEL); 3472 if (!in) 3473 return -ENOMEM; 3474 3475 MLX5_SET(modify_sq_in, in, uid, to_mpd(pd)->uid); 3476 MLX5_SET(modify_sq_in, in, sq_state, sq->state); 3477 3478 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 3479 MLX5_SET(sqc, sqc, state, new_state); 3480 3481 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) { 3482 if (new_state != MLX5_SQC_STATE_RDY) 3483 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n", 3484 __func__); 3485 else 3486 new_rl = raw_qp_param->rl; 3487 } 3488 3489 if (!mlx5_rl_are_equal(&old_rl, &new_rl)) { 3490 if (new_rl.rate) { 3491 err = mlx5_rl_add_rate(dev, &rl_index, &new_rl); 3492 if (err) { 3493 pr_err("Failed configuring rate limit(err %d): \ 3494 rate %u, max_burst_sz %u, typical_pkt_sz %u\n", 3495 err, new_rl.rate, new_rl.max_burst_sz, 3496 new_rl.typical_pkt_sz); 3497 3498 goto out; 3499 } 3500 new_rate_added = true; 3501 } 3502 3503 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1); 3504 /* index 0 means no limit */ 3505 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index); 3506 } 3507 3508 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in); 3509 if (err) { 3510 /* Remove new rate from table if failed */ 3511 if (new_rate_added) 3512 mlx5_rl_remove_rate(dev, &new_rl); 3513 goto out; 3514 } 3515 3516 /* Only remove the old rate after new rate was set */ 3517 if ((old_rl.rate && !mlx5_rl_are_equal(&old_rl, &new_rl)) || 3518 (new_state != MLX5_SQC_STATE_RDY)) { 3519 mlx5_rl_remove_rate(dev, &old_rl); 3520 if (new_state != MLX5_SQC_STATE_RDY) 3521 memset(&new_rl, 0, sizeof(new_rl)); 3522 } 3523 3524 ibqp->rl = new_rl; 3525 sq->state = new_state; 3526 3527 out: 3528 kvfree(in); 3529 return err; 3530 } 3531 3532 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 3533 const struct mlx5_modify_raw_qp_param *raw_qp_param, 3534 u8 tx_affinity) 3535 { 3536 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 3537 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 3538 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 3539 int modify_rq = !!qp->rq.wqe_cnt; 3540 int modify_sq = !!qp->sq.wqe_cnt; 3541 int rq_state; 3542 int sq_state; 3543 int err; 3544 3545 switch (raw_qp_param->operation) { 3546 case MLX5_CMD_OP_RST2INIT_QP: 3547 rq_state = MLX5_RQC_STATE_RDY; 3548 sq_state = MLX5_SQC_STATE_RST; 3549 break; 3550 case MLX5_CMD_OP_2ERR_QP: 3551 rq_state = MLX5_RQC_STATE_ERR; 3552 sq_state = MLX5_SQC_STATE_ERR; 3553 break; 3554 case MLX5_CMD_OP_2RST_QP: 3555 rq_state = MLX5_RQC_STATE_RST; 3556 sq_state = MLX5_SQC_STATE_RST; 3557 break; 3558 case MLX5_CMD_OP_RTR2RTS_QP: 3559 case MLX5_CMD_OP_RTS2RTS_QP: 3560 if (raw_qp_param->set_mask & ~MLX5_RAW_QP_RATE_LIMIT) 3561 return -EINVAL; 3562 3563 modify_rq = 0; 3564 sq_state = MLX5_SQC_STATE_RDY; 3565 break; 3566 case MLX5_CMD_OP_INIT2INIT_QP: 3567 case MLX5_CMD_OP_INIT2RTR_QP: 3568 if (raw_qp_param->set_mask) 3569 return -EINVAL; 3570 else 3571 return 0; 3572 default: 3573 WARN_ON(1); 3574 return -EINVAL; 3575 } 3576 3577 if (modify_rq) { 3578 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param, 3579 qp->ibqp.pd); 3580 if (err) 3581 return err; 3582 } 3583 3584 if (modify_sq) { 3585 struct mlx5_flow_handle *flow_rule; 3586 3587 if (tx_affinity) { 3588 err = modify_raw_packet_tx_affinity(dev->mdev, sq, 3589 tx_affinity, 3590 qp->ibqp.pd); 3591 if (err) 3592 return err; 3593 } 3594 3595 flow_rule = create_flow_rule_vport_sq(dev, sq, 3596 raw_qp_param->port); 3597 if (IS_ERR(flow_rule)) 3598 return PTR_ERR(flow_rule); 3599 3600 err = modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, 3601 raw_qp_param, qp->ibqp.pd); 3602 if (err) { 3603 if (flow_rule) 3604 mlx5_del_flow_rules(flow_rule); 3605 return err; 3606 } 3607 3608 if (flow_rule) { 3609 destroy_flow_rule_vport_sq(sq); 3610 sq->flow_rule = flow_rule; 3611 } 3612 3613 return err; 3614 } 3615 3616 return 0; 3617 } 3618 3619 static unsigned int get_tx_affinity_rr(struct mlx5_ib_dev *dev, 3620 struct ib_udata *udata) 3621 { 3622 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 3623 udata, struct mlx5_ib_ucontext, ibucontext); 3624 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3625 atomic_t *tx_port_affinity; 3626 3627 if (ucontext) 3628 tx_port_affinity = &ucontext->tx_port_affinity; 3629 else 3630 tx_port_affinity = &dev->port[port_num].roce.tx_port_affinity; 3631 3632 return (unsigned int)atomic_add_return(1, tx_port_affinity) % 3633 MLX5_MAX_PORTS + 1; 3634 } 3635 3636 static bool qp_supports_affinity(struct mlx5_ib_qp *qp) 3637 { 3638 if ((qp->type == IB_QPT_RC) || (qp->type == IB_QPT_UD) || 3639 (qp->type == IB_QPT_UC) || (qp->type == IB_QPT_RAW_PACKET) || 3640 (qp->type == IB_QPT_XRC_INI) || (qp->type == IB_QPT_XRC_TGT) || 3641 (qp->type == MLX5_IB_QPT_DCI)) 3642 return true; 3643 return false; 3644 } 3645 3646 static unsigned int get_tx_affinity(struct ib_qp *qp, 3647 const struct ib_qp_attr *attr, 3648 int attr_mask, u8 init, 3649 struct ib_udata *udata) 3650 { 3651 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 3652 udata, struct mlx5_ib_ucontext, ibucontext); 3653 struct mlx5_ib_dev *dev = to_mdev(qp->device); 3654 struct mlx5_ib_qp *mqp = to_mqp(qp); 3655 struct mlx5_ib_qp_base *qp_base; 3656 unsigned int tx_affinity; 3657 3658 if (!(mlx5_ib_lag_should_assign_affinity(dev) && 3659 qp_supports_affinity(mqp))) 3660 return 0; 3661 3662 if (mqp->flags & MLX5_IB_QP_CREATE_SQPN_QP1) 3663 tx_affinity = mqp->gsi_lag_port; 3664 else if (init) 3665 tx_affinity = get_tx_affinity_rr(dev, udata); 3666 else if ((attr_mask & IB_QP_AV) && attr->xmit_slave) 3667 tx_affinity = 3668 mlx5_lag_get_slave_port(dev->mdev, attr->xmit_slave); 3669 else 3670 return 0; 3671 3672 qp_base = &mqp->trans_qp.base; 3673 if (ucontext) 3674 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x ucontext %p\n", 3675 tx_affinity, qp_base->mqp.qpn, ucontext); 3676 else 3677 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x\n", 3678 tx_affinity, qp_base->mqp.qpn); 3679 return tx_affinity; 3680 } 3681 3682 static int __mlx5_ib_qp_set_counter(struct ib_qp *qp, 3683 struct rdma_counter *counter) 3684 { 3685 struct mlx5_ib_dev *dev = to_mdev(qp->device); 3686 u32 in[MLX5_ST_SZ_DW(rts2rts_qp_in)] = {}; 3687 struct mlx5_ib_qp *mqp = to_mqp(qp); 3688 struct mlx5_ib_qp_base *base; 3689 u32 set_id; 3690 u32 *qpc; 3691 3692 if (counter) 3693 set_id = counter->id; 3694 else 3695 set_id = mlx5_ib_get_counters_id(dev, mqp->port - 1); 3696 3697 base = &mqp->trans_qp.base; 3698 MLX5_SET(rts2rts_qp_in, in, opcode, MLX5_CMD_OP_RTS2RTS_QP); 3699 MLX5_SET(rts2rts_qp_in, in, qpn, base->mqp.qpn); 3700 MLX5_SET(rts2rts_qp_in, in, uid, base->mqp.uid); 3701 MLX5_SET(rts2rts_qp_in, in, opt_param_mask, 3702 MLX5_QP_OPTPAR_COUNTER_SET_ID); 3703 3704 qpc = MLX5_ADDR_OF(rts2rts_qp_in, in, qpc); 3705 MLX5_SET(qpc, qpc, counter_set_id, set_id); 3706 return mlx5_cmd_exec_in(dev->mdev, rts2rts_qp, in); 3707 } 3708 3709 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp, 3710 const struct ib_qp_attr *attr, int attr_mask, 3711 enum ib_qp_state cur_state, 3712 enum ib_qp_state new_state, 3713 const struct mlx5_ib_modify_qp *ucmd, 3714 struct mlx5_ib_modify_qp_resp *resp, 3715 struct ib_udata *udata) 3716 { 3717 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = { 3718 [MLX5_QP_STATE_RST] = { 3719 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3720 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3721 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP, 3722 }, 3723 [MLX5_QP_STATE_INIT] = { 3724 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3725 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3726 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP, 3727 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP, 3728 }, 3729 [MLX5_QP_STATE_RTR] = { 3730 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3731 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3732 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP, 3733 }, 3734 [MLX5_QP_STATE_RTS] = { 3735 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3736 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3737 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP, 3738 }, 3739 [MLX5_QP_STATE_SQD] = { 3740 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3741 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3742 }, 3743 [MLX5_QP_STATE_SQER] = { 3744 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3745 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3746 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP, 3747 }, 3748 [MLX5_QP_STATE_ERR] = { 3749 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 3750 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 3751 } 3752 }; 3753 3754 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3755 struct mlx5_ib_qp *qp = to_mqp(ibqp); 3756 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 3757 struct mlx5_ib_cq *send_cq, *recv_cq; 3758 struct mlx5_ib_pd *pd; 3759 enum mlx5_qp_state mlx5_cur, mlx5_new; 3760 void *qpc, *pri_path, *alt_path; 3761 enum mlx5_qp_optpar optpar = 0; 3762 u32 set_id = 0; 3763 int mlx5_st; 3764 int err; 3765 u16 op; 3766 u8 tx_affinity = 0; 3767 3768 mlx5_st = to_mlx5_st(qp->type); 3769 if (mlx5_st < 0) 3770 return -EINVAL; 3771 3772 qpc = kzalloc(MLX5_ST_SZ_BYTES(qpc), GFP_KERNEL); 3773 if (!qpc) 3774 return -ENOMEM; 3775 3776 pd = to_mpd(qp->ibqp.pd); 3777 MLX5_SET(qpc, qpc, st, mlx5_st); 3778 3779 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) { 3780 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 3781 } else { 3782 switch (attr->path_mig_state) { 3783 case IB_MIG_MIGRATED: 3784 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 3785 break; 3786 case IB_MIG_REARM: 3787 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_REARM); 3788 break; 3789 case IB_MIG_ARMED: 3790 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_ARMED); 3791 break; 3792 } 3793 } 3794 3795 tx_affinity = get_tx_affinity(ibqp, attr, attr_mask, 3796 cur_state == IB_QPS_RESET && 3797 new_state == IB_QPS_INIT, udata); 3798 3799 MLX5_SET(qpc, qpc, lag_tx_port_affinity, tx_affinity); 3800 if (tx_affinity && new_state == IB_QPS_RTR && 3801 MLX5_CAP_GEN(dev->mdev, init2_lag_tx_port_affinity)) 3802 optpar |= MLX5_QP_OPTPAR_LAG_TX_AFF; 3803 3804 if (is_sqp(ibqp->qp_type)) { 3805 MLX5_SET(qpc, qpc, mtu, IB_MTU_256); 3806 MLX5_SET(qpc, qpc, log_msg_max, 8); 3807 } else if ((ibqp->qp_type == IB_QPT_UD && 3808 !(qp->flags & IB_QP_CREATE_SOURCE_QPN)) || 3809 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) { 3810 MLX5_SET(qpc, qpc, mtu, IB_MTU_4096); 3811 MLX5_SET(qpc, qpc, log_msg_max, 12); 3812 } else if (attr_mask & IB_QP_PATH_MTU) { 3813 if (attr->path_mtu < IB_MTU_256 || 3814 attr->path_mtu > IB_MTU_4096) { 3815 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu); 3816 err = -EINVAL; 3817 goto out; 3818 } 3819 MLX5_SET(qpc, qpc, mtu, attr->path_mtu); 3820 MLX5_SET(qpc, qpc, log_msg_max, 3821 MLX5_CAP_GEN(dev->mdev, log_max_msg)); 3822 } 3823 3824 if (attr_mask & IB_QP_DEST_QPN) 3825 MLX5_SET(qpc, qpc, remote_qpn, attr->dest_qp_num); 3826 3827 pri_path = MLX5_ADDR_OF(qpc, qpc, primary_address_path); 3828 alt_path = MLX5_ADDR_OF(qpc, qpc, secondary_address_path); 3829 3830 if (attr_mask & IB_QP_PKEY_INDEX) 3831 MLX5_SET(ads, pri_path, pkey_index, attr->pkey_index); 3832 3833 /* todo implement counter_index functionality */ 3834 3835 if (is_sqp(ibqp->qp_type)) 3836 MLX5_SET(ads, pri_path, vhca_port_num, qp->port); 3837 3838 if (attr_mask & IB_QP_PORT) 3839 MLX5_SET(ads, pri_path, vhca_port_num, attr->port_num); 3840 3841 if (attr_mask & IB_QP_AV) { 3842 err = mlx5_set_path(dev, qp, &attr->ah_attr, pri_path, 3843 attr_mask & IB_QP_PORT ? attr->port_num : 3844 qp->port, 3845 attr_mask, 0, attr, false); 3846 if (err) 3847 goto out; 3848 } 3849 3850 if (attr_mask & IB_QP_TIMEOUT) 3851 MLX5_SET(ads, pri_path, ack_timeout, attr->timeout); 3852 3853 if (attr_mask & IB_QP_ALT_PATH) { 3854 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr, alt_path, 3855 attr->alt_port_num, 3856 attr_mask | IB_QP_PKEY_INDEX | 3857 IB_QP_TIMEOUT, 3858 0, attr, true); 3859 if (err) 3860 goto out; 3861 } 3862 3863 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 3864 &send_cq, &recv_cq); 3865 3866 MLX5_SET(qpc, qpc, pd, pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn); 3867 if (send_cq) 3868 MLX5_SET(qpc, qpc, cqn_snd, send_cq->mcq.cqn); 3869 if (recv_cq) 3870 MLX5_SET(qpc, qpc, cqn_rcv, recv_cq->mcq.cqn); 3871 3872 MLX5_SET(qpc, qpc, log_ack_req_freq, MLX5_IB_ACK_REQ_FREQ); 3873 3874 if (attr_mask & IB_QP_RNR_RETRY) 3875 MLX5_SET(qpc, qpc, rnr_retry, attr->rnr_retry); 3876 3877 if (attr_mask & IB_QP_RETRY_CNT) 3878 MLX5_SET(qpc, qpc, retry_count, attr->retry_cnt); 3879 3880 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && attr->max_rd_atomic) 3881 MLX5_SET(qpc, qpc, log_sra_max, ilog2(attr->max_rd_atomic)); 3882 3883 if (attr_mask & IB_QP_SQ_PSN) 3884 MLX5_SET(qpc, qpc, next_send_psn, attr->sq_psn); 3885 3886 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && attr->max_dest_rd_atomic) 3887 MLX5_SET(qpc, qpc, log_rra_max, 3888 ilog2(attr->max_dest_rd_atomic)); 3889 3890 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) { 3891 err = set_qpc_atomic_flags(qp, attr, attr_mask, qpc); 3892 if (err) 3893 goto out; 3894 } 3895 3896 if (attr_mask & IB_QP_MIN_RNR_TIMER) 3897 MLX5_SET(qpc, qpc, min_rnr_nak, attr->min_rnr_timer); 3898 3899 if (attr_mask & IB_QP_RQ_PSN) 3900 MLX5_SET(qpc, qpc, next_rcv_psn, attr->rq_psn); 3901 3902 if (attr_mask & IB_QP_QKEY) 3903 MLX5_SET(qpc, qpc, q_key, attr->qkey); 3904 3905 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 3906 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 3907 3908 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3909 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num : 3910 qp->port) - 1; 3911 3912 /* Underlay port should be used - index 0 function per port */ 3913 if (qp->flags & IB_QP_CREATE_SOURCE_QPN) 3914 port_num = 0; 3915 3916 if (ibqp->counter) 3917 set_id = ibqp->counter->id; 3918 else 3919 set_id = mlx5_ib_get_counters_id(dev, port_num); 3920 MLX5_SET(qpc, qpc, counter_set_id, set_id); 3921 } 3922 3923 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 3924 MLX5_SET(qpc, qpc, rlky, 1); 3925 3926 if (qp->flags & MLX5_IB_QP_CREATE_SQPN_QP1) 3927 MLX5_SET(qpc, qpc, deth_sqpn, 1); 3928 3929 mlx5_cur = to_mlx5_state(cur_state); 3930 mlx5_new = to_mlx5_state(new_state); 3931 3932 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE || 3933 !optab[mlx5_cur][mlx5_new]) { 3934 err = -EINVAL; 3935 goto out; 3936 } 3937 3938 op = optab[mlx5_cur][mlx5_new]; 3939 optpar |= ib_mask_to_mlx5_opt(attr_mask); 3940 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st]; 3941 3942 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 3943 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 3944 struct mlx5_modify_raw_qp_param raw_qp_param = {}; 3945 3946 raw_qp_param.operation = op; 3947 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3948 raw_qp_param.rq_q_ctr_id = set_id; 3949 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID; 3950 } 3951 3952 if (attr_mask & IB_QP_PORT) 3953 raw_qp_param.port = attr->port_num; 3954 3955 if (attr_mask & IB_QP_RATE_LIMIT) { 3956 raw_qp_param.rl.rate = attr->rate_limit; 3957 3958 if (ucmd->burst_info.max_burst_sz) { 3959 if (attr->rate_limit && 3960 MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) { 3961 raw_qp_param.rl.max_burst_sz = 3962 ucmd->burst_info.max_burst_sz; 3963 } else { 3964 err = -EINVAL; 3965 goto out; 3966 } 3967 } 3968 3969 if (ucmd->burst_info.typical_pkt_sz) { 3970 if (attr->rate_limit && 3971 MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) { 3972 raw_qp_param.rl.typical_pkt_sz = 3973 ucmd->burst_info.typical_pkt_sz; 3974 } else { 3975 err = -EINVAL; 3976 goto out; 3977 } 3978 } 3979 3980 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT; 3981 } 3982 3983 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity); 3984 } else { 3985 if (udata) { 3986 /* For the kernel flows, the resp will stay zero */ 3987 resp->ece_options = 3988 MLX5_CAP_GEN(dev->mdev, ece_support) ? 3989 ucmd->ece_options : 0; 3990 resp->response_length = sizeof(*resp); 3991 } 3992 err = mlx5_core_qp_modify(dev, op, optpar, qpc, &base->mqp, 3993 &resp->ece_options); 3994 } 3995 3996 if (err) 3997 goto out; 3998 3999 qp->state = new_state; 4000 4001 if (attr_mask & IB_QP_ACCESS_FLAGS) 4002 qp->trans_qp.atomic_rd_en = attr->qp_access_flags; 4003 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 4004 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic; 4005 if (attr_mask & IB_QP_PORT) 4006 qp->port = attr->port_num; 4007 if (attr_mask & IB_QP_ALT_PATH) 4008 qp->trans_qp.alt_port = attr->alt_port_num; 4009 4010 /* 4011 * If we moved a kernel QP to RESET, clean up all old CQ 4012 * entries and reinitialize the QP. 4013 */ 4014 if (new_state == IB_QPS_RESET && 4015 !ibqp->uobject && ibqp->qp_type != IB_QPT_XRC_TGT) { 4016 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 4017 ibqp->srq ? to_msrq(ibqp->srq) : NULL); 4018 if (send_cq != recv_cq) 4019 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL); 4020 4021 qp->rq.head = 0; 4022 qp->rq.tail = 0; 4023 qp->sq.head = 0; 4024 qp->sq.tail = 0; 4025 qp->sq.cur_post = 0; 4026 if (qp->sq.wqe_cnt) 4027 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0); 4028 qp->sq.last_poll = 0; 4029 qp->db.db[MLX5_RCV_DBR] = 0; 4030 qp->db.db[MLX5_SND_DBR] = 0; 4031 } 4032 4033 if ((new_state == IB_QPS_RTS) && qp->counter_pending) { 4034 err = __mlx5_ib_qp_set_counter(ibqp, ibqp->counter); 4035 if (!err) 4036 qp->counter_pending = 0; 4037 } 4038 4039 out: 4040 kfree(qpc); 4041 return err; 4042 } 4043 4044 static inline bool is_valid_mask(int mask, int req, int opt) 4045 { 4046 if ((mask & req) != req) 4047 return false; 4048 4049 if (mask & ~(req | opt)) 4050 return false; 4051 4052 return true; 4053 } 4054 4055 /* check valid transition for driver QP types 4056 * for now the only QP type that this function supports is DCI 4057 */ 4058 static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state, 4059 enum ib_qp_attr_mask attr_mask) 4060 { 4061 int req = IB_QP_STATE; 4062 int opt = 0; 4063 4064 if (new_state == IB_QPS_RESET) { 4065 return is_valid_mask(attr_mask, req, opt); 4066 } else if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4067 req |= IB_QP_PKEY_INDEX | IB_QP_PORT; 4068 return is_valid_mask(attr_mask, req, opt); 4069 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { 4070 opt = IB_QP_PKEY_INDEX | IB_QP_PORT; 4071 return is_valid_mask(attr_mask, req, opt); 4072 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 4073 req |= IB_QP_PATH_MTU; 4074 opt = IB_QP_PKEY_INDEX | IB_QP_AV; 4075 return is_valid_mask(attr_mask, req, opt); 4076 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { 4077 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY | 4078 IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN; 4079 opt = IB_QP_MIN_RNR_TIMER; 4080 return is_valid_mask(attr_mask, req, opt); 4081 } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) { 4082 opt = IB_QP_MIN_RNR_TIMER; 4083 return is_valid_mask(attr_mask, req, opt); 4084 } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) { 4085 return is_valid_mask(attr_mask, req, opt); 4086 } 4087 return false; 4088 } 4089 4090 /* mlx5_ib_modify_dct: modify a DCT QP 4091 * valid transitions are: 4092 * RESET to INIT: must set access_flags, pkey_index and port 4093 * INIT to RTR : must set min_rnr_timer, tclass, flow_label, 4094 * mtu, gid_index and hop_limit 4095 * Other transitions and attributes are illegal 4096 */ 4097 static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr, 4098 int attr_mask, struct mlx5_ib_modify_qp *ucmd, 4099 struct ib_udata *udata) 4100 { 4101 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4102 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4103 enum ib_qp_state cur_state, new_state; 4104 int required = IB_QP_STATE; 4105 void *dctc; 4106 int err; 4107 4108 if (!(attr_mask & IB_QP_STATE)) 4109 return -EINVAL; 4110 4111 cur_state = qp->state; 4112 new_state = attr->qp_state; 4113 4114 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); 4115 if (MLX5_CAP_GEN(dev->mdev, ece_support) && ucmd->ece_options) 4116 /* 4117 * DCT doesn't initialize QP till modify command is executed, 4118 * so we need to overwrite previously set ECE field if user 4119 * provided any value except zero, which means not set/not 4120 * valid. 4121 */ 4122 MLX5_SET(dctc, dctc, ece, ucmd->ece_options); 4123 4124 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4125 u16 set_id; 4126 4127 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT; 4128 if (!is_valid_mask(attr_mask, required, 0)) 4129 return -EINVAL; 4130 4131 if (attr->port_num == 0 || 4132 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) { 4133 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 4134 attr->port_num, dev->num_ports); 4135 return -EINVAL; 4136 } 4137 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ) 4138 MLX5_SET(dctc, dctc, rre, 1); 4139 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE) 4140 MLX5_SET(dctc, dctc, rwe, 1); 4141 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) { 4142 int atomic_mode; 4143 4144 atomic_mode = get_atomic_mode(dev, MLX5_IB_QPT_DCT); 4145 if (atomic_mode < 0) 4146 return -EOPNOTSUPP; 4147 4148 MLX5_SET(dctc, dctc, atomic_mode, atomic_mode); 4149 MLX5_SET(dctc, dctc, rae, 1); 4150 } 4151 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index); 4152 if (mlx5_lag_is_active(dev->mdev)) 4153 MLX5_SET(dctc, dctc, port, 4154 get_tx_affinity_rr(dev, udata)); 4155 else 4156 MLX5_SET(dctc, dctc, port, attr->port_num); 4157 4158 set_id = mlx5_ib_get_counters_id(dev, attr->port_num - 1); 4159 MLX5_SET(dctc, dctc, counter_set_id, set_id); 4160 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 4161 struct mlx5_ib_modify_qp_resp resp = {}; 4162 u32 out[MLX5_ST_SZ_DW(create_dct_out)] = {}; 4163 u32 min_resp_len = offsetofend(typeof(resp), dctn); 4164 4165 if (udata->outlen < min_resp_len) 4166 return -EINVAL; 4167 /* 4168 * If we don't have enough space for the ECE options, 4169 * simply indicate it with resp.response_length. 4170 */ 4171 resp.response_length = (udata->outlen < sizeof(resp)) ? 4172 min_resp_len : 4173 sizeof(resp); 4174 4175 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU; 4176 if (!is_valid_mask(attr_mask, required, 0)) 4177 return -EINVAL; 4178 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer); 4179 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class); 4180 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label); 4181 MLX5_SET(dctc, dctc, mtu, attr->path_mtu); 4182 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index); 4183 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit); 4184 4185 err = mlx5_core_create_dct(dev, &qp->dct.mdct, qp->dct.in, 4186 MLX5_ST_SZ_BYTES(create_dct_in), out, 4187 sizeof(out)); 4188 if (err) 4189 return err; 4190 resp.dctn = qp->dct.mdct.mqp.qpn; 4191 if (MLX5_CAP_GEN(dev->mdev, ece_support)) 4192 resp.ece_options = MLX5_GET(create_dct_out, out, ece); 4193 err = ib_copy_to_udata(udata, &resp, resp.response_length); 4194 if (err) { 4195 mlx5_core_destroy_dct(dev, &qp->dct.mdct); 4196 return err; 4197 } 4198 } else { 4199 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state); 4200 return -EINVAL; 4201 } 4202 4203 qp->state = new_state; 4204 return 0; 4205 } 4206 4207 static bool mlx5_ib_modify_qp_allowed(struct mlx5_ib_dev *dev, 4208 struct mlx5_ib_qp *qp, 4209 enum ib_qp_type qp_type) 4210 { 4211 if (dev->profile != &raw_eth_profile) 4212 return true; 4213 4214 if (qp_type == IB_QPT_RAW_PACKET || qp_type == MLX5_IB_QPT_REG_UMR) 4215 return true; 4216 4217 /* Internal QP used for wc testing, with NOPs in wq */ 4218 if (qp->flags & MLX5_IB_QP_CREATE_WC_TEST) 4219 return true; 4220 4221 return false; 4222 } 4223 4224 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 4225 int attr_mask, struct ib_udata *udata) 4226 { 4227 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4228 struct mlx5_ib_modify_qp_resp resp = {}; 4229 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4230 struct mlx5_ib_modify_qp ucmd = {}; 4231 enum ib_qp_type qp_type; 4232 enum ib_qp_state cur_state, new_state; 4233 int err = -EINVAL; 4234 4235 if (!mlx5_ib_modify_qp_allowed(dev, qp, ibqp->qp_type)) 4236 return -EOPNOTSUPP; 4237 4238 if (attr_mask & ~(IB_QP_ATTR_STANDARD_BITS | IB_QP_RATE_LIMIT)) 4239 return -EOPNOTSUPP; 4240 4241 if (ibqp->rwq_ind_tbl) 4242 return -ENOSYS; 4243 4244 if (udata && udata->inlen) { 4245 if (udata->inlen < offsetofend(typeof(ucmd), ece_options)) 4246 return -EINVAL; 4247 4248 if (udata->inlen > sizeof(ucmd) && 4249 !ib_is_udata_cleared(udata, sizeof(ucmd), 4250 udata->inlen - sizeof(ucmd))) 4251 return -EOPNOTSUPP; 4252 4253 if (ib_copy_from_udata(&ucmd, udata, 4254 min(udata->inlen, sizeof(ucmd)))) 4255 return -EFAULT; 4256 4257 if (ucmd.comp_mask || 4258 memchr_inv(&ucmd.burst_info.reserved, 0, 4259 sizeof(ucmd.burst_info.reserved))) 4260 return -EOPNOTSUPP; 4261 4262 } 4263 4264 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 4265 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask); 4266 4267 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ? IB_QPT_GSI : 4268 qp->type; 4269 4270 if (qp_type == MLX5_IB_QPT_DCT) 4271 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, &ucmd, udata); 4272 4273 mutex_lock(&qp->mutex); 4274 4275 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; 4276 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 4277 4278 if (qp->flags & IB_QP_CREATE_SOURCE_QPN) { 4279 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) { 4280 mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n", 4281 attr_mask); 4282 goto out; 4283 } 4284 } else if (qp_type != MLX5_IB_QPT_REG_UMR && 4285 qp_type != MLX5_IB_QPT_DCI && 4286 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, 4287 attr_mask)) { 4288 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 4289 cur_state, new_state, ibqp->qp_type, attr_mask); 4290 goto out; 4291 } else if (qp_type == MLX5_IB_QPT_DCI && 4292 !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) { 4293 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 4294 cur_state, new_state, qp_type, attr_mask); 4295 goto out; 4296 } 4297 4298 if ((attr_mask & IB_QP_PORT) && 4299 (attr->port_num == 0 || 4300 attr->port_num > dev->num_ports)) { 4301 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 4302 attr->port_num, dev->num_ports); 4303 goto out; 4304 } 4305 4306 if ((attr_mask & IB_QP_PKEY_INDEX) && 4307 attr->pkey_index >= dev->pkey_table_len) { 4308 mlx5_ib_dbg(dev, "invalid pkey index %d\n", attr->pkey_index); 4309 goto out; 4310 } 4311 4312 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 4313 attr->max_rd_atomic > 4314 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) { 4315 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n", 4316 attr->max_rd_atomic); 4317 goto out; 4318 } 4319 4320 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 4321 attr->max_dest_rd_atomic > 4322 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) { 4323 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n", 4324 attr->max_dest_rd_atomic); 4325 goto out; 4326 } 4327 4328 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 4329 err = 0; 4330 goto out; 4331 } 4332 4333 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, 4334 new_state, &ucmd, &resp, udata); 4335 4336 /* resp.response_length is set in ECE supported flows only */ 4337 if (!err && resp.response_length && 4338 udata->outlen >= resp.response_length) 4339 /* Return -EFAULT to the user and expect him to destroy QP. */ 4340 err = ib_copy_to_udata(udata, &resp, resp.response_length); 4341 4342 out: 4343 mutex_unlock(&qp->mutex); 4344 return err; 4345 } 4346 4347 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state) 4348 { 4349 switch (mlx5_state) { 4350 case MLX5_QP_STATE_RST: return IB_QPS_RESET; 4351 case MLX5_QP_STATE_INIT: return IB_QPS_INIT; 4352 case MLX5_QP_STATE_RTR: return IB_QPS_RTR; 4353 case MLX5_QP_STATE_RTS: return IB_QPS_RTS; 4354 case MLX5_QP_STATE_SQ_DRAINING: 4355 case MLX5_QP_STATE_SQD: return IB_QPS_SQD; 4356 case MLX5_QP_STATE_SQER: return IB_QPS_SQE; 4357 case MLX5_QP_STATE_ERR: return IB_QPS_ERR; 4358 default: return -1; 4359 } 4360 } 4361 4362 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state) 4363 { 4364 switch (mlx5_mig_state) { 4365 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED; 4366 case MLX5_QP_PM_REARM: return IB_MIG_REARM; 4367 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED; 4368 default: return -1; 4369 } 4370 } 4371 4372 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev, 4373 struct rdma_ah_attr *ah_attr, void *path) 4374 { 4375 int port = MLX5_GET(ads, path, vhca_port_num); 4376 int static_rate; 4377 4378 memset(ah_attr, 0, sizeof(*ah_attr)); 4379 4380 if (!port || port > ibdev->num_ports) 4381 return; 4382 4383 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, port); 4384 4385 rdma_ah_set_port_num(ah_attr, port); 4386 rdma_ah_set_sl(ah_attr, MLX5_GET(ads, path, sl)); 4387 4388 rdma_ah_set_dlid(ah_attr, MLX5_GET(ads, path, rlid)); 4389 rdma_ah_set_path_bits(ah_attr, MLX5_GET(ads, path, mlid)); 4390 4391 static_rate = MLX5_GET(ads, path, stat_rate); 4392 rdma_ah_set_static_rate(ah_attr, static_rate ? static_rate - 5 : 0); 4393 if (MLX5_GET(ads, path, grh) || 4394 ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE) { 4395 rdma_ah_set_grh(ah_attr, NULL, MLX5_GET(ads, path, flow_label), 4396 MLX5_GET(ads, path, src_addr_index), 4397 MLX5_GET(ads, path, hop_limit), 4398 MLX5_GET(ads, path, tclass)); 4399 rdma_ah_set_dgid_raw(ah_attr, MLX5_ADDR_OF(ads, path, rgid_rip)); 4400 } 4401 } 4402 4403 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev, 4404 struct mlx5_ib_sq *sq, 4405 u8 *sq_state) 4406 { 4407 int err; 4408 4409 err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state); 4410 if (err) 4411 goto out; 4412 sq->state = *sq_state; 4413 4414 out: 4415 return err; 4416 } 4417 4418 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev, 4419 struct mlx5_ib_rq *rq, 4420 u8 *rq_state) 4421 { 4422 void *out; 4423 void *rqc; 4424 int inlen; 4425 int err; 4426 4427 inlen = MLX5_ST_SZ_BYTES(query_rq_out); 4428 out = kvzalloc(inlen, GFP_KERNEL); 4429 if (!out) 4430 return -ENOMEM; 4431 4432 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out); 4433 if (err) 4434 goto out; 4435 4436 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context); 4437 *rq_state = MLX5_GET(rqc, rqc, state); 4438 rq->state = *rq_state; 4439 4440 out: 4441 kvfree(out); 4442 return err; 4443 } 4444 4445 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state, 4446 struct mlx5_ib_qp *qp, u8 *qp_state) 4447 { 4448 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = { 4449 [MLX5_RQC_STATE_RST] = { 4450 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 4451 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4452 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD, 4453 [MLX5_SQ_STATE_NA] = IB_QPS_RESET, 4454 }, 4455 [MLX5_RQC_STATE_RDY] = { 4456 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE, 4457 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4458 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE, 4459 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE, 4460 }, 4461 [MLX5_RQC_STATE_ERR] = { 4462 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 4463 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4464 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR, 4465 [MLX5_SQ_STATE_NA] = IB_QPS_ERR, 4466 }, 4467 [MLX5_RQ_STATE_NA] = { 4468 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE, 4469 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4470 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE, 4471 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD, 4472 }, 4473 }; 4474 4475 *qp_state = sqrq_trans[rq_state][sq_state]; 4476 4477 if (*qp_state == MLX5_QP_STATE_BAD) { 4478 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x", 4479 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state, 4480 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state); 4481 return -EINVAL; 4482 } 4483 4484 if (*qp_state == MLX5_QP_STATE) 4485 *qp_state = qp->state; 4486 4487 return 0; 4488 } 4489 4490 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev, 4491 struct mlx5_ib_qp *qp, 4492 u8 *raw_packet_qp_state) 4493 { 4494 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 4495 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 4496 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 4497 int err; 4498 u8 sq_state = MLX5_SQ_STATE_NA; 4499 u8 rq_state = MLX5_RQ_STATE_NA; 4500 4501 if (qp->sq.wqe_cnt) { 4502 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state); 4503 if (err) 4504 return err; 4505 } 4506 4507 if (qp->rq.wqe_cnt) { 4508 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state); 4509 if (err) 4510 return err; 4511 } 4512 4513 return sqrq_state_to_qp_state(sq_state, rq_state, qp, 4514 raw_packet_qp_state); 4515 } 4516 4517 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 4518 struct ib_qp_attr *qp_attr) 4519 { 4520 int outlen = MLX5_ST_SZ_BYTES(query_qp_out); 4521 void *qpc, *pri_path, *alt_path; 4522 u32 *outb; 4523 int err; 4524 4525 outb = kzalloc(outlen, GFP_KERNEL); 4526 if (!outb) 4527 return -ENOMEM; 4528 4529 err = mlx5_core_qp_query(dev, &qp->trans_qp.base.mqp, outb, outlen); 4530 if (err) 4531 goto out; 4532 4533 qpc = MLX5_ADDR_OF(query_qp_out, outb, qpc); 4534 4535 qp->state = to_ib_qp_state(MLX5_GET(qpc, qpc, state)); 4536 if (MLX5_GET(qpc, qpc, state) == MLX5_QP_STATE_SQ_DRAINING) 4537 qp_attr->sq_draining = 1; 4538 4539 qp_attr->path_mtu = MLX5_GET(qpc, qpc, mtu); 4540 qp_attr->path_mig_state = to_ib_mig_state(MLX5_GET(qpc, qpc, pm_state)); 4541 qp_attr->qkey = MLX5_GET(qpc, qpc, q_key); 4542 qp_attr->rq_psn = MLX5_GET(qpc, qpc, next_rcv_psn); 4543 qp_attr->sq_psn = MLX5_GET(qpc, qpc, next_send_psn); 4544 qp_attr->dest_qp_num = MLX5_GET(qpc, qpc, remote_qpn); 4545 4546 if (MLX5_GET(qpc, qpc, rre)) 4547 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_READ; 4548 if (MLX5_GET(qpc, qpc, rwe)) 4549 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_WRITE; 4550 if (MLX5_GET(qpc, qpc, rae)) 4551 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_ATOMIC; 4552 4553 qp_attr->max_rd_atomic = 1 << MLX5_GET(qpc, qpc, log_sra_max); 4554 qp_attr->max_dest_rd_atomic = 1 << MLX5_GET(qpc, qpc, log_rra_max); 4555 qp_attr->min_rnr_timer = MLX5_GET(qpc, qpc, min_rnr_nak); 4556 qp_attr->retry_cnt = MLX5_GET(qpc, qpc, retry_count); 4557 qp_attr->rnr_retry = MLX5_GET(qpc, qpc, rnr_retry); 4558 4559 pri_path = MLX5_ADDR_OF(qpc, qpc, primary_address_path); 4560 alt_path = MLX5_ADDR_OF(qpc, qpc, secondary_address_path); 4561 4562 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC || 4563 qp->ibqp.qp_type == IB_QPT_XRC_INI || 4564 qp->ibqp.qp_type == IB_QPT_XRC_TGT) { 4565 to_rdma_ah_attr(dev, &qp_attr->ah_attr, pri_path); 4566 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, alt_path); 4567 qp_attr->alt_pkey_index = MLX5_GET(ads, alt_path, pkey_index); 4568 qp_attr->alt_port_num = MLX5_GET(ads, alt_path, vhca_port_num); 4569 } 4570 4571 qp_attr->pkey_index = MLX5_GET(ads, pri_path, pkey_index); 4572 qp_attr->port_num = MLX5_GET(ads, pri_path, vhca_port_num); 4573 qp_attr->timeout = MLX5_GET(ads, pri_path, ack_timeout); 4574 qp_attr->alt_timeout = MLX5_GET(ads, alt_path, ack_timeout); 4575 4576 out: 4577 kfree(outb); 4578 return err; 4579 } 4580 4581 static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp, 4582 struct ib_qp_attr *qp_attr, int qp_attr_mask, 4583 struct ib_qp_init_attr *qp_init_attr) 4584 { 4585 struct mlx5_core_dct *dct = &mqp->dct.mdct; 4586 u32 *out; 4587 u32 access_flags = 0; 4588 int outlen = MLX5_ST_SZ_BYTES(query_dct_out); 4589 void *dctc; 4590 int err; 4591 int supported_mask = IB_QP_STATE | 4592 IB_QP_ACCESS_FLAGS | 4593 IB_QP_PORT | 4594 IB_QP_MIN_RNR_TIMER | 4595 IB_QP_AV | 4596 IB_QP_PATH_MTU | 4597 IB_QP_PKEY_INDEX; 4598 4599 if (qp_attr_mask & ~supported_mask) 4600 return -EINVAL; 4601 if (mqp->state != IB_QPS_RTR) 4602 return -EINVAL; 4603 4604 out = kzalloc(outlen, GFP_KERNEL); 4605 if (!out) 4606 return -ENOMEM; 4607 4608 err = mlx5_core_dct_query(dev, dct, out, outlen); 4609 if (err) 4610 goto out; 4611 4612 dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry); 4613 4614 if (qp_attr_mask & IB_QP_STATE) 4615 qp_attr->qp_state = IB_QPS_RTR; 4616 4617 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) { 4618 if (MLX5_GET(dctc, dctc, rre)) 4619 access_flags |= IB_ACCESS_REMOTE_READ; 4620 if (MLX5_GET(dctc, dctc, rwe)) 4621 access_flags |= IB_ACCESS_REMOTE_WRITE; 4622 if (MLX5_GET(dctc, dctc, rae)) 4623 access_flags |= IB_ACCESS_REMOTE_ATOMIC; 4624 qp_attr->qp_access_flags = access_flags; 4625 } 4626 4627 if (qp_attr_mask & IB_QP_PORT) 4628 qp_attr->port_num = MLX5_GET(dctc, dctc, port); 4629 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) 4630 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak); 4631 if (qp_attr_mask & IB_QP_AV) { 4632 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass); 4633 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label); 4634 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index); 4635 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit); 4636 } 4637 if (qp_attr_mask & IB_QP_PATH_MTU) 4638 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu); 4639 if (qp_attr_mask & IB_QP_PKEY_INDEX) 4640 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index); 4641 out: 4642 kfree(out); 4643 return err; 4644 } 4645 4646 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 4647 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 4648 { 4649 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4650 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4651 int err = 0; 4652 u8 raw_packet_qp_state; 4653 4654 if (ibqp->rwq_ind_tbl) 4655 return -ENOSYS; 4656 4657 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 4658 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask, 4659 qp_init_attr); 4660 4661 /* Not all of output fields are applicable, make sure to zero them */ 4662 memset(qp_init_attr, 0, sizeof(*qp_init_attr)); 4663 memset(qp_attr, 0, sizeof(*qp_attr)); 4664 4665 if (unlikely(qp->type == MLX5_IB_QPT_DCT)) 4666 return mlx5_ib_dct_query_qp(dev, qp, qp_attr, 4667 qp_attr_mask, qp_init_attr); 4668 4669 mutex_lock(&qp->mutex); 4670 4671 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || 4672 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 4673 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state); 4674 if (err) 4675 goto out; 4676 qp->state = raw_packet_qp_state; 4677 qp_attr->port_num = 1; 4678 } else { 4679 err = query_qp_attr(dev, qp, qp_attr); 4680 if (err) 4681 goto out; 4682 } 4683 4684 qp_attr->qp_state = qp->state; 4685 qp_attr->cur_qp_state = qp_attr->qp_state; 4686 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; 4687 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 4688 4689 if (!ibqp->uobject) { 4690 qp_attr->cap.max_send_wr = qp->sq.max_post; 4691 qp_attr->cap.max_send_sge = qp->sq.max_gs; 4692 qp_init_attr->qp_context = ibqp->qp_context; 4693 } else { 4694 qp_attr->cap.max_send_wr = 0; 4695 qp_attr->cap.max_send_sge = 0; 4696 } 4697 4698 qp_init_attr->qp_type = ibqp->qp_type; 4699 qp_init_attr->recv_cq = ibqp->recv_cq; 4700 qp_init_attr->send_cq = ibqp->send_cq; 4701 qp_init_attr->srq = ibqp->srq; 4702 qp_attr->cap.max_inline_data = qp->max_inline_data; 4703 4704 qp_init_attr->cap = qp_attr->cap; 4705 4706 qp_init_attr->create_flags = qp->flags; 4707 4708 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ? 4709 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; 4710 4711 out: 4712 mutex_unlock(&qp->mutex); 4713 return err; 4714 } 4715 4716 int mlx5_ib_alloc_xrcd(struct ib_xrcd *ibxrcd, struct ib_udata *udata) 4717 { 4718 struct mlx5_ib_dev *dev = to_mdev(ibxrcd->device); 4719 struct mlx5_ib_xrcd *xrcd = to_mxrcd(ibxrcd); 4720 4721 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 4722 return -EOPNOTSUPP; 4723 4724 return mlx5_cmd_xrcd_alloc(dev->mdev, &xrcd->xrcdn, 0); 4725 } 4726 4727 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata) 4728 { 4729 struct mlx5_ib_dev *dev = to_mdev(xrcd->device); 4730 u32 xrcdn = to_mxrcd(xrcd)->xrcdn; 4731 4732 return mlx5_cmd_xrcd_dealloc(dev->mdev, xrcdn, 0); 4733 } 4734 4735 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type) 4736 { 4737 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp); 4738 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device); 4739 struct ib_event event; 4740 4741 if (rwq->ibwq.event_handler) { 4742 event.device = rwq->ibwq.device; 4743 event.element.wq = &rwq->ibwq; 4744 switch (type) { 4745 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 4746 event.event = IB_EVENT_WQ_FATAL; 4747 break; 4748 default: 4749 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn); 4750 return; 4751 } 4752 4753 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context); 4754 } 4755 } 4756 4757 static int set_delay_drop(struct mlx5_ib_dev *dev) 4758 { 4759 int err = 0; 4760 4761 mutex_lock(&dev->delay_drop.lock); 4762 if (dev->delay_drop.activate) 4763 goto out; 4764 4765 err = mlx5_core_set_delay_drop(dev, dev->delay_drop.timeout); 4766 if (err) 4767 goto out; 4768 4769 dev->delay_drop.activate = true; 4770 out: 4771 mutex_unlock(&dev->delay_drop.lock); 4772 4773 if (!err) 4774 atomic_inc(&dev->delay_drop.rqs_cnt); 4775 return err; 4776 } 4777 4778 static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd, 4779 struct ib_wq_init_attr *init_attr) 4780 { 4781 struct mlx5_ib_dev *dev; 4782 int has_net_offloads; 4783 __be64 *rq_pas0; 4784 void *in; 4785 void *rqc; 4786 void *wq; 4787 int inlen; 4788 int err; 4789 4790 dev = to_mdev(pd->device); 4791 4792 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas; 4793 in = kvzalloc(inlen, GFP_KERNEL); 4794 if (!in) 4795 return -ENOMEM; 4796 4797 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid); 4798 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 4799 MLX5_SET(rqc, rqc, mem_rq_type, 4800 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 4801 MLX5_SET(rqc, rqc, user_index, rwq->user_index); 4802 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn); 4803 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 4804 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 4805 wq = MLX5_ADDR_OF(rqc, rqc, wq); 4806 MLX5_SET(wq, wq, wq_type, 4807 rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ? 4808 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC); 4809 if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { 4810 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) { 4811 mlx5_ib_dbg(dev, "Scatter end padding is not supported\n"); 4812 err = -EOPNOTSUPP; 4813 goto out; 4814 } else { 4815 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 4816 } 4817 } 4818 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride); 4819 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) { 4820 /* 4821 * In Firmware number of strides in each WQE is: 4822 * "512 * 2^single_wqe_log_num_of_strides" 4823 * Values 3 to 8 are accepted as 10 to 15, 9 to 18 are 4824 * accepted as 0 to 9 4825 */ 4826 static const u8 fw_map[] = { 10, 11, 12, 13, 14, 15, 0, 1, 4827 2, 3, 4, 5, 6, 7, 8, 9 }; 4828 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en); 4829 MLX5_SET(wq, wq, log_wqe_stride_size, 4830 rwq->single_stride_log_num_of_bytes - 4831 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES); 4832 MLX5_SET(wq, wq, log_wqe_num_of_strides, 4833 fw_map[rwq->log_num_strides - 4834 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES]); 4835 } 4836 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size); 4837 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn); 4838 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset); 4839 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size); 4840 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig); 4841 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma); 4842 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads); 4843 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) { 4844 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) { 4845 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n"); 4846 err = -EOPNOTSUPP; 4847 goto out; 4848 } 4849 } else { 4850 MLX5_SET(rqc, rqc, vsd, 1); 4851 } 4852 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) { 4853 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) { 4854 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n"); 4855 err = -EOPNOTSUPP; 4856 goto out; 4857 } 4858 MLX5_SET(rqc, rqc, scatter_fcs, 1); 4859 } 4860 if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { 4861 if (!(dev->ib_dev.attrs.raw_packet_caps & 4862 IB_RAW_PACKET_CAP_DELAY_DROP)) { 4863 mlx5_ib_dbg(dev, "Delay drop is not supported\n"); 4864 err = -EOPNOTSUPP; 4865 goto out; 4866 } 4867 MLX5_SET(rqc, rqc, delay_drop_en, 1); 4868 } 4869 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 4870 mlx5_ib_populate_pas(rwq->umem, 1UL << rwq->page_shift, rq_pas0, 0); 4871 err = mlx5_core_create_rq_tracked(dev, in, inlen, &rwq->core_qp); 4872 if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { 4873 err = set_delay_drop(dev); 4874 if (err) { 4875 mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n", 4876 err); 4877 mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp); 4878 } else { 4879 rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP; 4880 } 4881 } 4882 out: 4883 kvfree(in); 4884 return err; 4885 } 4886 4887 static int set_user_rq_size(struct mlx5_ib_dev *dev, 4888 struct ib_wq_init_attr *wq_init_attr, 4889 struct mlx5_ib_create_wq *ucmd, 4890 struct mlx5_ib_rwq *rwq) 4891 { 4892 /* Sanity check RQ size before proceeding */ 4893 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz))) 4894 return -EINVAL; 4895 4896 if (!ucmd->rq_wqe_count) 4897 return -EINVAL; 4898 4899 rwq->wqe_count = ucmd->rq_wqe_count; 4900 rwq->wqe_shift = ucmd->rq_wqe_shift; 4901 if (check_shl_overflow(rwq->wqe_count, rwq->wqe_shift, &rwq->buf_size)) 4902 return -EINVAL; 4903 4904 rwq->log_rq_stride = rwq->wqe_shift; 4905 rwq->log_rq_size = ilog2(rwq->wqe_count); 4906 return 0; 4907 } 4908 4909 static bool log_of_strides_valid(struct mlx5_ib_dev *dev, u32 log_num_strides) 4910 { 4911 if ((log_num_strides > MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) || 4912 (log_num_strides < MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) 4913 return false; 4914 4915 if (!MLX5_CAP_GEN(dev->mdev, ext_stride_num_range) && 4916 (log_num_strides < MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) 4917 return false; 4918 4919 return true; 4920 } 4921 4922 static int prepare_user_rq(struct ib_pd *pd, 4923 struct ib_wq_init_attr *init_attr, 4924 struct ib_udata *udata, 4925 struct mlx5_ib_rwq *rwq) 4926 { 4927 struct mlx5_ib_dev *dev = to_mdev(pd->device); 4928 struct mlx5_ib_create_wq ucmd = {}; 4929 int err; 4930 size_t required_cmd_sz; 4931 4932 required_cmd_sz = offsetofend(struct mlx5_ib_create_wq, 4933 single_stride_log_num_of_bytes); 4934 if (udata->inlen < required_cmd_sz) { 4935 mlx5_ib_dbg(dev, "invalid inlen\n"); 4936 return -EINVAL; 4937 } 4938 4939 if (udata->inlen > sizeof(ucmd) && 4940 !ib_is_udata_cleared(udata, sizeof(ucmd), 4941 udata->inlen - sizeof(ucmd))) { 4942 mlx5_ib_dbg(dev, "inlen is not supported\n"); 4943 return -EOPNOTSUPP; 4944 } 4945 4946 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 4947 mlx5_ib_dbg(dev, "copy failed\n"); 4948 return -EFAULT; 4949 } 4950 4951 if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) { 4952 mlx5_ib_dbg(dev, "invalid comp mask\n"); 4953 return -EOPNOTSUPP; 4954 } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) { 4955 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) { 4956 mlx5_ib_dbg(dev, "Striding RQ is not supported\n"); 4957 return -EOPNOTSUPP; 4958 } 4959 if ((ucmd.single_stride_log_num_of_bytes < 4960 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) || 4961 (ucmd.single_stride_log_num_of_bytes > 4962 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) { 4963 mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n", 4964 ucmd.single_stride_log_num_of_bytes, 4965 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES, 4966 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES); 4967 return -EINVAL; 4968 } 4969 if (!log_of_strides_valid(dev, 4970 ucmd.single_wqe_log_num_of_strides)) { 4971 mlx5_ib_dbg( 4972 dev, 4973 "Invalid log num strides (%u. Range is %u - %u)\n", 4974 ucmd.single_wqe_log_num_of_strides, 4975 MLX5_CAP_GEN(dev->mdev, ext_stride_num_range) ? 4976 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES : 4977 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES, 4978 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES); 4979 return -EINVAL; 4980 } 4981 rwq->single_stride_log_num_of_bytes = 4982 ucmd.single_stride_log_num_of_bytes; 4983 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides; 4984 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en; 4985 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ; 4986 } 4987 4988 err = set_user_rq_size(dev, init_attr, &ucmd, rwq); 4989 if (err) { 4990 mlx5_ib_dbg(dev, "err %d\n", err); 4991 return err; 4992 } 4993 4994 err = create_user_rq(dev, pd, udata, rwq, &ucmd); 4995 if (err) { 4996 mlx5_ib_dbg(dev, "err %d\n", err); 4997 return err; 4998 } 4999 5000 rwq->user_index = ucmd.user_index; 5001 return 0; 5002 } 5003 5004 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 5005 struct ib_wq_init_attr *init_attr, 5006 struct ib_udata *udata) 5007 { 5008 struct mlx5_ib_dev *dev; 5009 struct mlx5_ib_rwq *rwq; 5010 struct mlx5_ib_create_wq_resp resp = {}; 5011 size_t min_resp_len; 5012 int err; 5013 5014 if (!udata) 5015 return ERR_PTR(-ENOSYS); 5016 5017 min_resp_len = offsetofend(struct mlx5_ib_create_wq_resp, reserved); 5018 if (udata->outlen && udata->outlen < min_resp_len) 5019 return ERR_PTR(-EINVAL); 5020 5021 if (!capable(CAP_SYS_RAWIO) && 5022 init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) 5023 return ERR_PTR(-EPERM); 5024 5025 dev = to_mdev(pd->device); 5026 switch (init_attr->wq_type) { 5027 case IB_WQT_RQ: 5028 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL); 5029 if (!rwq) 5030 return ERR_PTR(-ENOMEM); 5031 err = prepare_user_rq(pd, init_attr, udata, rwq); 5032 if (err) 5033 goto err; 5034 err = create_rq(rwq, pd, init_attr); 5035 if (err) 5036 goto err_user_rq; 5037 break; 5038 default: 5039 mlx5_ib_dbg(dev, "unsupported wq type %d\n", 5040 init_attr->wq_type); 5041 return ERR_PTR(-EINVAL); 5042 } 5043 5044 rwq->ibwq.wq_num = rwq->core_qp.qpn; 5045 rwq->ibwq.state = IB_WQS_RESET; 5046 if (udata->outlen) { 5047 resp.response_length = offsetofend( 5048 struct mlx5_ib_create_wq_resp, response_length); 5049 err = ib_copy_to_udata(udata, &resp, resp.response_length); 5050 if (err) 5051 goto err_copy; 5052 } 5053 5054 rwq->core_qp.event = mlx5_ib_wq_event; 5055 rwq->ibwq.event_handler = init_attr->event_handler; 5056 return &rwq->ibwq; 5057 5058 err_copy: 5059 mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp); 5060 err_user_rq: 5061 destroy_user_rq(dev, pd, rwq, udata); 5062 err: 5063 kfree(rwq); 5064 return ERR_PTR(err); 5065 } 5066 5067 int mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata) 5068 { 5069 struct mlx5_ib_dev *dev = to_mdev(wq->device); 5070 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 5071 int ret; 5072 5073 ret = mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp); 5074 if (ret) 5075 return ret; 5076 destroy_user_rq(dev, wq->pd, rwq, udata); 5077 kfree(rwq); 5078 return 0; 5079 } 5080 5081 int mlx5_ib_create_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_table, 5082 struct ib_rwq_ind_table_init_attr *init_attr, 5083 struct ib_udata *udata) 5084 { 5085 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = 5086 to_mrwq_ind_table(ib_rwq_ind_table); 5087 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_table->device); 5088 int sz = 1 << init_attr->log_ind_tbl_size; 5089 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {}; 5090 size_t min_resp_len; 5091 int inlen; 5092 int err; 5093 int i; 5094 u32 *in; 5095 void *rqtc; 5096 5097 if (udata->inlen > 0 && 5098 !ib_is_udata_cleared(udata, 0, 5099 udata->inlen)) 5100 return -EOPNOTSUPP; 5101 5102 if (init_attr->log_ind_tbl_size > 5103 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) { 5104 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n", 5105 init_attr->log_ind_tbl_size, 5106 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)); 5107 return -EINVAL; 5108 } 5109 5110 min_resp_len = 5111 offsetofend(struct mlx5_ib_create_rwq_ind_tbl_resp, reserved); 5112 if (udata->outlen && udata->outlen < min_resp_len) 5113 return -EINVAL; 5114 5115 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; 5116 in = kvzalloc(inlen, GFP_KERNEL); 5117 if (!in) 5118 return -ENOMEM; 5119 5120 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 5121 5122 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 5123 MLX5_SET(rqtc, rqtc, rqt_max_size, sz); 5124 5125 for (i = 0; i < sz; i++) 5126 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num); 5127 5128 rwq_ind_tbl->uid = to_mpd(init_attr->ind_tbl[0]->pd)->uid; 5129 MLX5_SET(create_rqt_in, in, uid, rwq_ind_tbl->uid); 5130 5131 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn); 5132 kvfree(in); 5133 if (err) 5134 return err; 5135 5136 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn; 5137 if (udata->outlen) { 5138 resp.response_length = 5139 offsetofend(struct mlx5_ib_create_rwq_ind_tbl_resp, 5140 response_length); 5141 err = ib_copy_to_udata(udata, &resp, resp.response_length); 5142 if (err) 5143 goto err_copy; 5144 } 5145 5146 return 0; 5147 5148 err_copy: 5149 mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid); 5150 return err; 5151 } 5152 5153 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 5154 { 5155 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl); 5156 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device); 5157 5158 return mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid); 5159 } 5160 5161 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 5162 u32 wq_attr_mask, struct ib_udata *udata) 5163 { 5164 struct mlx5_ib_dev *dev = to_mdev(wq->device); 5165 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 5166 struct mlx5_ib_modify_wq ucmd = {}; 5167 size_t required_cmd_sz; 5168 int curr_wq_state; 5169 int wq_state; 5170 int inlen; 5171 int err; 5172 void *rqc; 5173 void *in; 5174 5175 required_cmd_sz = offsetofend(struct mlx5_ib_modify_wq, reserved); 5176 if (udata->inlen < required_cmd_sz) 5177 return -EINVAL; 5178 5179 if (udata->inlen > sizeof(ucmd) && 5180 !ib_is_udata_cleared(udata, sizeof(ucmd), 5181 udata->inlen - sizeof(ucmd))) 5182 return -EOPNOTSUPP; 5183 5184 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) 5185 return -EFAULT; 5186 5187 if (ucmd.comp_mask || ucmd.reserved) 5188 return -EOPNOTSUPP; 5189 5190 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 5191 in = kvzalloc(inlen, GFP_KERNEL); 5192 if (!in) 5193 return -ENOMEM; 5194 5195 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 5196 5197 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ? 5198 wq_attr->curr_wq_state : wq->state; 5199 wq_state = (wq_attr_mask & IB_WQ_STATE) ? 5200 wq_attr->wq_state : curr_wq_state; 5201 if (curr_wq_state == IB_WQS_ERR) 5202 curr_wq_state = MLX5_RQC_STATE_ERR; 5203 if (wq_state == IB_WQS_ERR) 5204 wq_state = MLX5_RQC_STATE_ERR; 5205 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state); 5206 MLX5_SET(modify_rq_in, in, uid, to_mpd(wq->pd)->uid); 5207 MLX5_SET(rqc, rqc, state, wq_state); 5208 5209 if (wq_attr_mask & IB_WQ_FLAGS) { 5210 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) { 5211 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 5212 MLX5_CAP_ETH(dev->mdev, vlan_cap))) { 5213 mlx5_ib_dbg(dev, "VLAN offloads are not " 5214 "supported\n"); 5215 err = -EOPNOTSUPP; 5216 goto out; 5217 } 5218 MLX5_SET64(modify_rq_in, in, modify_bitmask, 5219 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD); 5220 MLX5_SET(rqc, rqc, vsd, 5221 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1); 5222 } 5223 5224 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { 5225 mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n"); 5226 err = -EOPNOTSUPP; 5227 goto out; 5228 } 5229 } 5230 5231 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) { 5232 u16 set_id; 5233 5234 set_id = mlx5_ib_get_counters_id(dev, 0); 5235 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 5236 MLX5_SET64(modify_rq_in, in, modify_bitmask, 5237 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 5238 MLX5_SET(rqc, rqc, counter_set_id, set_id); 5239 } else 5240 dev_info_once( 5241 &dev->ib_dev.dev, 5242 "Receive WQ counters are not supported on current FW\n"); 5243 } 5244 5245 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in); 5246 if (!err) 5247 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state; 5248 5249 out: 5250 kvfree(in); 5251 return err; 5252 } 5253 5254 struct mlx5_ib_drain_cqe { 5255 struct ib_cqe cqe; 5256 struct completion done; 5257 }; 5258 5259 static void mlx5_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc) 5260 { 5261 struct mlx5_ib_drain_cqe *cqe = container_of(wc->wr_cqe, 5262 struct mlx5_ib_drain_cqe, 5263 cqe); 5264 5265 complete(&cqe->done); 5266 } 5267 5268 /* This function returns only once the drained WR was completed */ 5269 static void handle_drain_completion(struct ib_cq *cq, 5270 struct mlx5_ib_drain_cqe *sdrain, 5271 struct mlx5_ib_dev *dev) 5272 { 5273 struct mlx5_core_dev *mdev = dev->mdev; 5274 5275 if (cq->poll_ctx == IB_POLL_DIRECT) { 5276 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0) 5277 ib_process_cq_direct(cq, -1); 5278 return; 5279 } 5280 5281 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 5282 struct mlx5_ib_cq *mcq = to_mcq(cq); 5283 bool triggered = false; 5284 unsigned long flags; 5285 5286 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 5287 /* Make sure that the CQ handler won't run if wasn't run yet */ 5288 if (!mcq->mcq.reset_notify_added) 5289 mcq->mcq.reset_notify_added = 1; 5290 else 5291 triggered = true; 5292 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 5293 5294 if (triggered) { 5295 /* Wait for any scheduled/running task to be ended */ 5296 switch (cq->poll_ctx) { 5297 case IB_POLL_SOFTIRQ: 5298 irq_poll_disable(&cq->iop); 5299 irq_poll_enable(&cq->iop); 5300 break; 5301 case IB_POLL_WORKQUEUE: 5302 cancel_work_sync(&cq->work); 5303 break; 5304 default: 5305 WARN_ON_ONCE(1); 5306 } 5307 } 5308 5309 /* Run the CQ handler - this makes sure that the drain WR will 5310 * be processed if wasn't processed yet. 5311 */ 5312 mcq->mcq.comp(&mcq->mcq, NULL); 5313 } 5314 5315 wait_for_completion(&sdrain->done); 5316 } 5317 5318 void mlx5_ib_drain_sq(struct ib_qp *qp) 5319 { 5320 struct ib_cq *cq = qp->send_cq; 5321 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; 5322 struct mlx5_ib_drain_cqe sdrain; 5323 const struct ib_send_wr *bad_swr; 5324 struct ib_rdma_wr swr = { 5325 .wr = { 5326 .next = NULL, 5327 { .wr_cqe = &sdrain.cqe, }, 5328 .opcode = IB_WR_RDMA_WRITE, 5329 }, 5330 }; 5331 int ret; 5332 struct mlx5_ib_dev *dev = to_mdev(qp->device); 5333 struct mlx5_core_dev *mdev = dev->mdev; 5334 5335 ret = ib_modify_qp(qp, &attr, IB_QP_STATE); 5336 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { 5337 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); 5338 return; 5339 } 5340 5341 sdrain.cqe.done = mlx5_ib_drain_qp_done; 5342 init_completion(&sdrain.done); 5343 5344 ret = mlx5_ib_post_send_drain(qp, &swr.wr, &bad_swr); 5345 if (ret) { 5346 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); 5347 return; 5348 } 5349 5350 handle_drain_completion(cq, &sdrain, dev); 5351 } 5352 5353 void mlx5_ib_drain_rq(struct ib_qp *qp) 5354 { 5355 struct ib_cq *cq = qp->recv_cq; 5356 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; 5357 struct mlx5_ib_drain_cqe rdrain; 5358 struct ib_recv_wr rwr = {}; 5359 const struct ib_recv_wr *bad_rwr; 5360 int ret; 5361 struct mlx5_ib_dev *dev = to_mdev(qp->device); 5362 struct mlx5_core_dev *mdev = dev->mdev; 5363 5364 ret = ib_modify_qp(qp, &attr, IB_QP_STATE); 5365 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { 5366 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); 5367 return; 5368 } 5369 5370 rwr.wr_cqe = &rdrain.cqe; 5371 rdrain.cqe.done = mlx5_ib_drain_qp_done; 5372 init_completion(&rdrain.done); 5373 5374 ret = mlx5_ib_post_recv_drain(qp, &rwr, &bad_rwr); 5375 if (ret) { 5376 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); 5377 return; 5378 } 5379 5380 handle_drain_completion(cq, &rdrain, dev); 5381 } 5382 5383 /* 5384 * Bind a qp to a counter. If @counter is NULL then bind the qp to 5385 * the default counter 5386 */ 5387 int mlx5_ib_qp_set_counter(struct ib_qp *qp, struct rdma_counter *counter) 5388 { 5389 struct mlx5_ib_dev *dev = to_mdev(qp->device); 5390 struct mlx5_ib_qp *mqp = to_mqp(qp); 5391 int err = 0; 5392 5393 mutex_lock(&mqp->mutex); 5394 if (mqp->state == IB_QPS_RESET) { 5395 qp->counter = counter; 5396 goto out; 5397 } 5398 5399 if (!MLX5_CAP_GEN(dev->mdev, rts2rts_qp_counters_set_id)) { 5400 err = -EOPNOTSUPP; 5401 goto out; 5402 } 5403 5404 if (mqp->state == IB_QPS_RTS) { 5405 err = __mlx5_ib_qp_set_counter(qp, counter); 5406 if (!err) 5407 qp->counter = counter; 5408 5409 goto out; 5410 } 5411 5412 mqp->counter_pending = 1; 5413 qp->counter = counter; 5414 5415 out: 5416 mutex_unlock(&mqp->mutex); 5417 return err; 5418 } 5419