1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/debugfs.h> 34 #include <linux/highmem.h> 35 #include <linux/module.h> 36 #include <linux/init.h> 37 #include <linux/errno.h> 38 #include <linux/pci.h> 39 #include <linux/dma-mapping.h> 40 #include <linux/slab.h> 41 #include <linux/bitmap.h> 42 #if defined(CONFIG_X86) 43 #include <asm/pat.h> 44 #endif 45 #include <linux/sched.h> 46 #include <linux/sched/mm.h> 47 #include <linux/sched/task.h> 48 #include <linux/delay.h> 49 #include <rdma/ib_user_verbs.h> 50 #include <rdma/ib_addr.h> 51 #include <rdma/ib_cache.h> 52 #include <linux/mlx5/port.h> 53 #include <linux/mlx5/vport.h> 54 #include <linux/mlx5/fs.h> 55 #include <linux/list.h> 56 #include <rdma/ib_smi.h> 57 #include <rdma/ib_umem.h> 58 #include <linux/in.h> 59 #include <linux/etherdevice.h> 60 #include "mlx5_ib.h" 61 #include "ib_rep.h" 62 #include "cmd.h" 63 #include <linux/mlx5/fs_helpers.h> 64 #include <linux/mlx5/accel.h> 65 #include <rdma/uverbs_std_types.h> 66 #include <rdma/mlx5_user_ioctl_verbs.h> 67 #include <rdma/mlx5_user_ioctl_cmds.h> 68 69 #define UVERBS_MODULE_NAME mlx5_ib 70 #include <rdma/uverbs_named_ioctl.h> 71 72 #define DRIVER_NAME "mlx5_ib" 73 #define DRIVER_VERSION "5.0-0" 74 75 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 76 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver"); 77 MODULE_LICENSE("Dual BSD/GPL"); 78 79 static char mlx5_version[] = 80 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v" 81 DRIVER_VERSION "\n"; 82 83 struct mlx5_ib_event_work { 84 struct work_struct work; 85 struct mlx5_core_dev *dev; 86 void *context; 87 enum mlx5_dev_event event; 88 unsigned long param; 89 }; 90 91 enum { 92 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 93 }; 94 95 static struct workqueue_struct *mlx5_ib_event_wq; 96 static LIST_HEAD(mlx5_ib_unaffiliated_port_list); 97 static LIST_HEAD(mlx5_ib_dev_list); 98 /* 99 * This mutex should be held when accessing either of the above lists 100 */ 101 static DEFINE_MUTEX(mlx5_ib_multiport_mutex); 102 103 /* We can't use an array for xlt_emergency_page because dma_map_single 104 * doesn't work on kernel modules memory 105 */ 106 static unsigned long xlt_emergency_page; 107 static struct mutex xlt_emergency_page_mutex; 108 109 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi) 110 { 111 struct mlx5_ib_dev *dev; 112 113 mutex_lock(&mlx5_ib_multiport_mutex); 114 dev = mpi->ibdev; 115 mutex_unlock(&mlx5_ib_multiport_mutex); 116 return dev; 117 } 118 119 static enum rdma_link_layer 120 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 121 { 122 switch (port_type_cap) { 123 case MLX5_CAP_PORT_TYPE_IB: 124 return IB_LINK_LAYER_INFINIBAND; 125 case MLX5_CAP_PORT_TYPE_ETH: 126 return IB_LINK_LAYER_ETHERNET; 127 default: 128 return IB_LINK_LAYER_UNSPECIFIED; 129 } 130 } 131 132 static enum rdma_link_layer 133 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num) 134 { 135 struct mlx5_ib_dev *dev = to_mdev(device); 136 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 137 138 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 139 } 140 141 static int get_port_state(struct ib_device *ibdev, 142 u8 port_num, 143 enum ib_port_state *state) 144 { 145 struct ib_port_attr attr; 146 int ret; 147 148 memset(&attr, 0, sizeof(attr)); 149 ret = ibdev->query_port(ibdev, port_num, &attr); 150 if (!ret) 151 *state = attr.state; 152 return ret; 153 } 154 155 static int mlx5_netdev_event(struct notifier_block *this, 156 unsigned long event, void *ptr) 157 { 158 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb); 159 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 160 u8 port_num = roce->native_port_num; 161 struct mlx5_core_dev *mdev; 162 struct mlx5_ib_dev *ibdev; 163 164 ibdev = roce->dev; 165 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 166 if (!mdev) 167 return NOTIFY_DONE; 168 169 switch (event) { 170 case NETDEV_REGISTER: 171 case NETDEV_UNREGISTER: 172 write_lock(&roce->netdev_lock); 173 if (ibdev->rep) { 174 struct mlx5_eswitch *esw = ibdev->mdev->priv.eswitch; 175 struct net_device *rep_ndev; 176 177 rep_ndev = mlx5_ib_get_rep_netdev(esw, 178 ibdev->rep->vport); 179 if (rep_ndev == ndev) 180 roce->netdev = (event == NETDEV_UNREGISTER) ? 181 NULL : ndev; 182 } else if (ndev->dev.parent == &mdev->pdev->dev) { 183 roce->netdev = (event == NETDEV_UNREGISTER) ? 184 NULL : ndev; 185 } 186 write_unlock(&roce->netdev_lock); 187 break; 188 189 case NETDEV_CHANGE: 190 case NETDEV_UP: 191 case NETDEV_DOWN: { 192 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev); 193 struct net_device *upper = NULL; 194 195 if (lag_ndev) { 196 upper = netdev_master_upper_dev_get(lag_ndev); 197 dev_put(lag_ndev); 198 } 199 200 if ((upper == ndev || (!upper && ndev == roce->netdev)) 201 && ibdev->ib_active) { 202 struct ib_event ibev = { }; 203 enum ib_port_state port_state; 204 205 if (get_port_state(&ibdev->ib_dev, port_num, 206 &port_state)) 207 goto done; 208 209 if (roce->last_port_state == port_state) 210 goto done; 211 212 roce->last_port_state = port_state; 213 ibev.device = &ibdev->ib_dev; 214 if (port_state == IB_PORT_DOWN) 215 ibev.event = IB_EVENT_PORT_ERR; 216 else if (port_state == IB_PORT_ACTIVE) 217 ibev.event = IB_EVENT_PORT_ACTIVE; 218 else 219 goto done; 220 221 ibev.element.port_num = port_num; 222 ib_dispatch_event(&ibev); 223 } 224 break; 225 } 226 227 default: 228 break; 229 } 230 done: 231 mlx5_ib_put_native_port_mdev(ibdev, port_num); 232 return NOTIFY_DONE; 233 } 234 235 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device, 236 u8 port_num) 237 { 238 struct mlx5_ib_dev *ibdev = to_mdev(device); 239 struct net_device *ndev; 240 struct mlx5_core_dev *mdev; 241 242 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 243 if (!mdev) 244 return NULL; 245 246 ndev = mlx5_lag_get_roce_netdev(mdev); 247 if (ndev) 248 goto out; 249 250 /* Ensure ndev does not disappear before we invoke dev_hold() 251 */ 252 read_lock(&ibdev->roce[port_num - 1].netdev_lock); 253 ndev = ibdev->roce[port_num - 1].netdev; 254 if (ndev) 255 dev_hold(ndev); 256 read_unlock(&ibdev->roce[port_num - 1].netdev_lock); 257 258 out: 259 mlx5_ib_put_native_port_mdev(ibdev, port_num); 260 return ndev; 261 } 262 263 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev, 264 u8 ib_port_num, 265 u8 *native_port_num) 266 { 267 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 268 ib_port_num); 269 struct mlx5_core_dev *mdev = NULL; 270 struct mlx5_ib_multiport_info *mpi; 271 struct mlx5_ib_port *port; 272 273 if (!mlx5_core_mp_enabled(ibdev->mdev) || 274 ll != IB_LINK_LAYER_ETHERNET) { 275 if (native_port_num) 276 *native_port_num = ib_port_num; 277 return ibdev->mdev; 278 } 279 280 if (native_port_num) 281 *native_port_num = 1; 282 283 port = &ibdev->port[ib_port_num - 1]; 284 if (!port) 285 return NULL; 286 287 spin_lock(&port->mp.mpi_lock); 288 mpi = ibdev->port[ib_port_num - 1].mp.mpi; 289 if (mpi && !mpi->unaffiliate) { 290 mdev = mpi->mdev; 291 /* If it's the master no need to refcount, it'll exist 292 * as long as the ib_dev exists. 293 */ 294 if (!mpi->is_master) 295 mpi->mdev_refcnt++; 296 } 297 spin_unlock(&port->mp.mpi_lock); 298 299 return mdev; 300 } 301 302 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num) 303 { 304 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 305 port_num); 306 struct mlx5_ib_multiport_info *mpi; 307 struct mlx5_ib_port *port; 308 309 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 310 return; 311 312 port = &ibdev->port[port_num - 1]; 313 314 spin_lock(&port->mp.mpi_lock); 315 mpi = ibdev->port[port_num - 1].mp.mpi; 316 if (mpi->is_master) 317 goto out; 318 319 mpi->mdev_refcnt--; 320 if (mpi->unaffiliate) 321 complete(&mpi->unref_comp); 322 out: 323 spin_unlock(&port->mp.mpi_lock); 324 } 325 326 static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed, 327 u8 *active_width) 328 { 329 switch (eth_proto_oper) { 330 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII): 331 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX): 332 case MLX5E_PROT_MASK(MLX5E_100BASE_TX): 333 case MLX5E_PROT_MASK(MLX5E_1000BASE_T): 334 *active_width = IB_WIDTH_1X; 335 *active_speed = IB_SPEED_SDR; 336 break; 337 case MLX5E_PROT_MASK(MLX5E_10GBASE_T): 338 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4): 339 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4): 340 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR): 341 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR): 342 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR): 343 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER): 344 *active_width = IB_WIDTH_1X; 345 *active_speed = IB_SPEED_QDR; 346 break; 347 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR): 348 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR): 349 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR): 350 *active_width = IB_WIDTH_1X; 351 *active_speed = IB_SPEED_EDR; 352 break; 353 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4): 354 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4): 355 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4): 356 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4): 357 *active_width = IB_WIDTH_4X; 358 *active_speed = IB_SPEED_QDR; 359 break; 360 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2): 361 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2): 362 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2): 363 *active_width = IB_WIDTH_1X; 364 *active_speed = IB_SPEED_HDR; 365 break; 366 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4): 367 *active_width = IB_WIDTH_4X; 368 *active_speed = IB_SPEED_FDR; 369 break; 370 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4): 371 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4): 372 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4): 373 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4): 374 *active_width = IB_WIDTH_4X; 375 *active_speed = IB_SPEED_EDR; 376 break; 377 default: 378 return -EINVAL; 379 } 380 381 return 0; 382 } 383 384 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num, 385 struct ib_port_attr *props) 386 { 387 struct mlx5_ib_dev *dev = to_mdev(device); 388 struct mlx5_core_dev *mdev; 389 struct net_device *ndev, *upper; 390 enum ib_mtu ndev_ib_mtu; 391 bool put_mdev = true; 392 u16 qkey_viol_cntr; 393 u32 eth_prot_oper; 394 u8 mdev_port_num; 395 int err; 396 397 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 398 if (!mdev) { 399 /* This means the port isn't affiliated yet. Get the 400 * info for the master port instead. 401 */ 402 put_mdev = false; 403 mdev = dev->mdev; 404 mdev_port_num = 1; 405 port_num = 1; 406 } 407 408 /* Possible bad flows are checked before filling out props so in case 409 * of an error it will still be zeroed out. 410 */ 411 err = mlx5_query_port_eth_proto_oper(mdev, ð_prot_oper, 412 mdev_port_num); 413 if (err) 414 goto out; 415 416 props->active_width = IB_WIDTH_4X; 417 props->active_speed = IB_SPEED_QDR; 418 419 translate_eth_proto_oper(eth_prot_oper, &props->active_speed, 420 &props->active_width); 421 422 props->port_cap_flags |= IB_PORT_CM_SUP; 423 props->ip_gids = true; 424 425 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 426 roce_address_table_size); 427 props->max_mtu = IB_MTU_4096; 428 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 429 props->pkey_tbl_len = 1; 430 props->state = IB_PORT_DOWN; 431 props->phys_state = 3; 432 433 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr); 434 props->qkey_viol_cntr = qkey_viol_cntr; 435 436 /* If this is a stub query for an unaffiliated port stop here */ 437 if (!put_mdev) 438 goto out; 439 440 ndev = mlx5_ib_get_netdev(device, port_num); 441 if (!ndev) 442 goto out; 443 444 if (mlx5_lag_is_active(dev->mdev)) { 445 rcu_read_lock(); 446 upper = netdev_master_upper_dev_get_rcu(ndev); 447 if (upper) { 448 dev_put(ndev); 449 ndev = upper; 450 dev_hold(ndev); 451 } 452 rcu_read_unlock(); 453 } 454 455 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 456 props->state = IB_PORT_ACTIVE; 457 props->phys_state = 5; 458 } 459 460 ndev_ib_mtu = iboe_get_mtu(ndev->mtu); 461 462 dev_put(ndev); 463 464 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 465 out: 466 if (put_mdev) 467 mlx5_ib_put_native_port_mdev(dev, port_num); 468 return err; 469 } 470 471 static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num, 472 unsigned int index, const union ib_gid *gid, 473 const struct ib_gid_attr *attr) 474 { 475 enum ib_gid_type gid_type = IB_GID_TYPE_IB; 476 u8 roce_version = 0; 477 u8 roce_l3_type = 0; 478 bool vlan = false; 479 u8 mac[ETH_ALEN]; 480 u16 vlan_id = 0; 481 482 if (gid) { 483 gid_type = attr->gid_type; 484 ether_addr_copy(mac, attr->ndev->dev_addr); 485 486 if (is_vlan_dev(attr->ndev)) { 487 vlan = true; 488 vlan_id = vlan_dev_vlan_id(attr->ndev); 489 } 490 } 491 492 switch (gid_type) { 493 case IB_GID_TYPE_IB: 494 roce_version = MLX5_ROCE_VERSION_1; 495 break; 496 case IB_GID_TYPE_ROCE_UDP_ENCAP: 497 roce_version = MLX5_ROCE_VERSION_2; 498 if (ipv6_addr_v4mapped((void *)gid)) 499 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4; 500 else 501 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6; 502 break; 503 504 default: 505 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type); 506 } 507 508 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version, 509 roce_l3_type, gid->raw, mac, vlan, 510 vlan_id, port_num); 511 } 512 513 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr, 514 __always_unused void **context) 515 { 516 return set_roce_addr(to_mdev(attr->device), attr->port_num, 517 attr->index, &attr->gid, attr); 518 } 519 520 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr, 521 __always_unused void **context) 522 { 523 return set_roce_addr(to_mdev(attr->device), attr->port_num, 524 attr->index, NULL, NULL); 525 } 526 527 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, 528 const struct ib_gid_attr *attr) 529 { 530 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 531 return 0; 532 533 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 534 } 535 536 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 537 { 538 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 539 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 540 return 0; 541 } 542 543 enum { 544 MLX5_VPORT_ACCESS_METHOD_MAD, 545 MLX5_VPORT_ACCESS_METHOD_HCA, 546 MLX5_VPORT_ACCESS_METHOD_NIC, 547 }; 548 549 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 550 { 551 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 552 return MLX5_VPORT_ACCESS_METHOD_MAD; 553 554 if (mlx5_ib_port_link_layer(ibdev, 1) == 555 IB_LINK_LAYER_ETHERNET) 556 return MLX5_VPORT_ACCESS_METHOD_NIC; 557 558 return MLX5_VPORT_ACCESS_METHOD_HCA; 559 } 560 561 static void get_atomic_caps(struct mlx5_ib_dev *dev, 562 u8 atomic_size_qp, 563 struct ib_device_attr *props) 564 { 565 u8 tmp; 566 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 567 u8 atomic_req_8B_endianness_mode = 568 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode); 569 570 /* Check if HW supports 8 bytes standard atomic operations and capable 571 * of host endianness respond 572 */ 573 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 574 if (((atomic_operations & tmp) == tmp) && 575 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 576 (atomic_req_8B_endianness_mode)) { 577 props->atomic_cap = IB_ATOMIC_HCA; 578 } else { 579 props->atomic_cap = IB_ATOMIC_NONE; 580 } 581 } 582 583 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev, 584 struct ib_device_attr *props) 585 { 586 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 587 588 get_atomic_caps(dev, atomic_size_qp, props); 589 } 590 591 static void get_atomic_caps_dc(struct mlx5_ib_dev *dev, 592 struct ib_device_attr *props) 593 { 594 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc); 595 596 get_atomic_caps(dev, atomic_size_qp, props); 597 } 598 599 bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev) 600 { 601 struct ib_device_attr props = {}; 602 603 get_atomic_caps_dc(dev, &props); 604 return (props.atomic_cap == IB_ATOMIC_HCA) ? true : false; 605 } 606 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 607 __be64 *sys_image_guid) 608 { 609 struct mlx5_ib_dev *dev = to_mdev(ibdev); 610 struct mlx5_core_dev *mdev = dev->mdev; 611 u64 tmp; 612 int err; 613 614 switch (mlx5_get_vport_access_method(ibdev)) { 615 case MLX5_VPORT_ACCESS_METHOD_MAD: 616 return mlx5_query_mad_ifc_system_image_guid(ibdev, 617 sys_image_guid); 618 619 case MLX5_VPORT_ACCESS_METHOD_HCA: 620 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 621 break; 622 623 case MLX5_VPORT_ACCESS_METHOD_NIC: 624 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 625 break; 626 627 default: 628 return -EINVAL; 629 } 630 631 if (!err) 632 *sys_image_guid = cpu_to_be64(tmp); 633 634 return err; 635 636 } 637 638 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 639 u16 *max_pkeys) 640 { 641 struct mlx5_ib_dev *dev = to_mdev(ibdev); 642 struct mlx5_core_dev *mdev = dev->mdev; 643 644 switch (mlx5_get_vport_access_method(ibdev)) { 645 case MLX5_VPORT_ACCESS_METHOD_MAD: 646 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 647 648 case MLX5_VPORT_ACCESS_METHOD_HCA: 649 case MLX5_VPORT_ACCESS_METHOD_NIC: 650 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 651 pkey_table_size)); 652 return 0; 653 654 default: 655 return -EINVAL; 656 } 657 } 658 659 static int mlx5_query_vendor_id(struct ib_device *ibdev, 660 u32 *vendor_id) 661 { 662 struct mlx5_ib_dev *dev = to_mdev(ibdev); 663 664 switch (mlx5_get_vport_access_method(ibdev)) { 665 case MLX5_VPORT_ACCESS_METHOD_MAD: 666 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 667 668 case MLX5_VPORT_ACCESS_METHOD_HCA: 669 case MLX5_VPORT_ACCESS_METHOD_NIC: 670 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 671 672 default: 673 return -EINVAL; 674 } 675 } 676 677 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 678 __be64 *node_guid) 679 { 680 u64 tmp; 681 int err; 682 683 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 684 case MLX5_VPORT_ACCESS_METHOD_MAD: 685 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 686 687 case MLX5_VPORT_ACCESS_METHOD_HCA: 688 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 689 break; 690 691 case MLX5_VPORT_ACCESS_METHOD_NIC: 692 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 693 break; 694 695 default: 696 return -EINVAL; 697 } 698 699 if (!err) 700 *node_guid = cpu_to_be64(tmp); 701 702 return err; 703 } 704 705 struct mlx5_reg_node_desc { 706 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 707 }; 708 709 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 710 { 711 struct mlx5_reg_node_desc in; 712 713 if (mlx5_use_mad_ifc(dev)) 714 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 715 716 memset(&in, 0, sizeof(in)); 717 718 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 719 sizeof(struct mlx5_reg_node_desc), 720 MLX5_REG_NODE_DESC, 0, 0); 721 } 722 723 static int mlx5_ib_query_device(struct ib_device *ibdev, 724 struct ib_device_attr *props, 725 struct ib_udata *uhw) 726 { 727 struct mlx5_ib_dev *dev = to_mdev(ibdev); 728 struct mlx5_core_dev *mdev = dev->mdev; 729 int err = -ENOMEM; 730 int max_sq_desc; 731 int max_rq_sg; 732 int max_sq_sg; 733 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 734 bool raw_support = !mlx5_core_mp_enabled(mdev); 735 struct mlx5_ib_query_device_resp resp = {}; 736 size_t resp_len; 737 u64 max_tso; 738 739 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 740 if (uhw->outlen && uhw->outlen < resp_len) 741 return -EINVAL; 742 else 743 resp.response_length = resp_len; 744 745 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) 746 return -EINVAL; 747 748 memset(props, 0, sizeof(*props)); 749 err = mlx5_query_system_image_guid(ibdev, 750 &props->sys_image_guid); 751 if (err) 752 return err; 753 754 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys); 755 if (err) 756 return err; 757 758 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 759 if (err) 760 return err; 761 762 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 763 (fw_rev_min(dev->mdev) << 16) | 764 fw_rev_sub(dev->mdev); 765 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 766 IB_DEVICE_PORT_ACTIVE_EVENT | 767 IB_DEVICE_SYS_IMAGE_GUID | 768 IB_DEVICE_RC_RNR_NAK_GEN; 769 770 if (MLX5_CAP_GEN(mdev, pkv)) 771 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 772 if (MLX5_CAP_GEN(mdev, qkv)) 773 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 774 if (MLX5_CAP_GEN(mdev, apm)) 775 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 776 if (MLX5_CAP_GEN(mdev, xrc)) 777 props->device_cap_flags |= IB_DEVICE_XRC; 778 if (MLX5_CAP_GEN(mdev, imaicl)) { 779 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 780 IB_DEVICE_MEM_WINDOW_TYPE_2B; 781 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 782 /* We support 'Gappy' memory registration too */ 783 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG; 784 } 785 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 786 if (MLX5_CAP_GEN(mdev, sho)) { 787 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER; 788 /* At this stage no support for signature handover */ 789 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 790 IB_PROT_T10DIF_TYPE_2 | 791 IB_PROT_T10DIF_TYPE_3; 792 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 793 IB_GUARD_T10DIF_CSUM; 794 } 795 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 796 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 797 798 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) { 799 if (MLX5_CAP_ETH(mdev, csum_cap)) { 800 /* Legacy bit to support old userspace libraries */ 801 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 802 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM; 803 } 804 805 if (MLX5_CAP_ETH(dev->mdev, vlan_cap)) 806 props->raw_packet_caps |= 807 IB_RAW_PACKET_CAP_CVLAN_STRIPPING; 808 809 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) { 810 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 811 if (max_tso) { 812 resp.tso_caps.max_tso = 1 << max_tso; 813 resp.tso_caps.supported_qpts |= 814 1 << IB_QPT_RAW_PACKET; 815 resp.response_length += sizeof(resp.tso_caps); 816 } 817 } 818 819 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) { 820 resp.rss_caps.rx_hash_function = 821 MLX5_RX_HASH_FUNC_TOEPLITZ; 822 resp.rss_caps.rx_hash_fields_mask = 823 MLX5_RX_HASH_SRC_IPV4 | 824 MLX5_RX_HASH_DST_IPV4 | 825 MLX5_RX_HASH_SRC_IPV6 | 826 MLX5_RX_HASH_DST_IPV6 | 827 MLX5_RX_HASH_SRC_PORT_TCP | 828 MLX5_RX_HASH_DST_PORT_TCP | 829 MLX5_RX_HASH_SRC_PORT_UDP | 830 MLX5_RX_HASH_DST_PORT_UDP | 831 MLX5_RX_HASH_INNER; 832 if (mlx5_accel_ipsec_device_caps(dev->mdev) & 833 MLX5_ACCEL_IPSEC_CAP_DEVICE) 834 resp.rss_caps.rx_hash_fields_mask |= 835 MLX5_RX_HASH_IPSEC_SPI; 836 resp.response_length += sizeof(resp.rss_caps); 837 } 838 } else { 839 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) 840 resp.response_length += sizeof(resp.tso_caps); 841 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) 842 resp.response_length += sizeof(resp.rss_caps); 843 } 844 845 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 846 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 847 props->device_cap_flags |= IB_DEVICE_UD_TSO; 848 } 849 850 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) && 851 MLX5_CAP_GEN(dev->mdev, general_notification_event) && 852 raw_support) 853 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP; 854 855 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 856 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap)) 857 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 858 859 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 860 MLX5_CAP_ETH(dev->mdev, scatter_fcs) && 861 raw_support) { 862 /* Legacy bit to support old userspace libraries */ 863 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 864 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; 865 } 866 867 if (MLX5_CAP_DEV_MEM(mdev, memic)) { 868 props->max_dm_size = 869 MLX5_CAP_DEV_MEM(mdev, max_memic_size); 870 } 871 872 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 873 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 874 875 if (MLX5_CAP_GEN(mdev, end_pad)) 876 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING; 877 878 props->vendor_part_id = mdev->pdev->device; 879 props->hw_ver = mdev->pdev->revision; 880 881 props->max_mr_size = ~0ull; 882 props->page_size_cap = ~(min_page_size - 1); 883 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 884 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 885 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 886 sizeof(struct mlx5_wqe_data_seg); 887 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512); 888 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) - 889 sizeof(struct mlx5_wqe_raddr_seg)) / 890 sizeof(struct mlx5_wqe_data_seg); 891 props->max_send_sge = max_sq_sg; 892 props->max_recv_sge = max_rq_sg; 893 props->max_sge_rd = MLX5_MAX_SGE_RD; 894 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 895 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 896 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 897 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 898 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 899 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 900 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 901 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 902 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 903 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 904 props->max_srq_sge = max_rq_sg - 1; 905 props->max_fast_reg_page_list_len = 906 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 907 get_atomic_caps_qp(dev, props); 908 props->masked_atomic_cap = IB_ATOMIC_NONE; 909 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 910 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 911 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 912 props->max_mcast_grp; 913 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */ 914 props->max_ah = INT_MAX; 915 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 916 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 917 918 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 919 if (MLX5_CAP_GEN(mdev, pg)) 920 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING; 921 props->odp_caps = dev->odp_caps; 922 #endif 923 924 if (MLX5_CAP_GEN(mdev, cd)) 925 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL; 926 927 if (!mlx5_core_is_pf(mdev)) 928 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION; 929 930 if (mlx5_ib_port_link_layer(ibdev, 1) == 931 IB_LINK_LAYER_ETHERNET && raw_support) { 932 props->rss_caps.max_rwq_indirection_tables = 933 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 934 props->rss_caps.max_rwq_indirection_table_size = 935 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 936 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 937 props->max_wq_type_rq = 938 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 939 } 940 941 if (MLX5_CAP_GEN(mdev, tag_matching)) { 942 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE; 943 props->tm_caps.max_num_tags = 944 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1; 945 props->tm_caps.flags = IB_TM_CAP_RC; 946 props->tm_caps.max_ops = 947 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 948 props->tm_caps.max_sge = MLX5_TM_MAX_SGE; 949 } 950 951 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) { 952 props->cq_caps.max_cq_moderation_count = 953 MLX5_MAX_CQ_COUNT; 954 props->cq_caps.max_cq_moderation_period = 955 MLX5_MAX_CQ_PERIOD; 956 } 957 958 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) { 959 resp.response_length += sizeof(resp.cqe_comp_caps); 960 961 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) { 962 resp.cqe_comp_caps.max_num = 963 MLX5_CAP_GEN(dev->mdev, 964 cqe_compression_max_num); 965 966 resp.cqe_comp_caps.supported_format = 967 MLX5_IB_CQE_RES_FORMAT_HASH | 968 MLX5_IB_CQE_RES_FORMAT_CSUM; 969 970 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index)) 971 resp.cqe_comp_caps.supported_format |= 972 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX; 973 } 974 } 975 976 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen) && 977 raw_support) { 978 if (MLX5_CAP_QOS(mdev, packet_pacing) && 979 MLX5_CAP_GEN(mdev, qos)) { 980 resp.packet_pacing_caps.qp_rate_limit_max = 981 MLX5_CAP_QOS(mdev, packet_pacing_max_rate); 982 resp.packet_pacing_caps.qp_rate_limit_min = 983 MLX5_CAP_QOS(mdev, packet_pacing_min_rate); 984 resp.packet_pacing_caps.supported_qpts |= 985 1 << IB_QPT_RAW_PACKET; 986 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) && 987 MLX5_CAP_QOS(mdev, packet_pacing_typical_size)) 988 resp.packet_pacing_caps.cap_flags |= 989 MLX5_IB_PP_SUPPORT_BURST; 990 } 991 resp.response_length += sizeof(resp.packet_pacing_caps); 992 } 993 994 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes, 995 uhw->outlen)) { 996 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe)) 997 resp.mlx5_ib_support_multi_pkt_send_wqes = 998 MLX5_IB_ALLOW_MPW; 999 1000 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe)) 1001 resp.mlx5_ib_support_multi_pkt_send_wqes |= 1002 MLX5_IB_SUPPORT_EMPW; 1003 1004 resp.response_length += 1005 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes); 1006 } 1007 1008 if (field_avail(typeof(resp), flags, uhw->outlen)) { 1009 resp.response_length += sizeof(resp.flags); 1010 1011 if (MLX5_CAP_GEN(mdev, cqe_compression_128)) 1012 resp.flags |= 1013 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP; 1014 1015 if (MLX5_CAP_GEN(mdev, cqe_128_always)) 1016 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD; 1017 } 1018 1019 if (field_avail(typeof(resp), sw_parsing_caps, 1020 uhw->outlen)) { 1021 resp.response_length += sizeof(resp.sw_parsing_caps); 1022 if (MLX5_CAP_ETH(mdev, swp)) { 1023 resp.sw_parsing_caps.sw_parsing_offloads |= 1024 MLX5_IB_SW_PARSING; 1025 1026 if (MLX5_CAP_ETH(mdev, swp_csum)) 1027 resp.sw_parsing_caps.sw_parsing_offloads |= 1028 MLX5_IB_SW_PARSING_CSUM; 1029 1030 if (MLX5_CAP_ETH(mdev, swp_lso)) 1031 resp.sw_parsing_caps.sw_parsing_offloads |= 1032 MLX5_IB_SW_PARSING_LSO; 1033 1034 if (resp.sw_parsing_caps.sw_parsing_offloads) 1035 resp.sw_parsing_caps.supported_qpts = 1036 BIT(IB_QPT_RAW_PACKET); 1037 } 1038 } 1039 1040 if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen) && 1041 raw_support) { 1042 resp.response_length += sizeof(resp.striding_rq_caps); 1043 if (MLX5_CAP_GEN(mdev, striding_rq)) { 1044 resp.striding_rq_caps.min_single_stride_log_num_of_bytes = 1045 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES; 1046 resp.striding_rq_caps.max_single_stride_log_num_of_bytes = 1047 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES; 1048 resp.striding_rq_caps.min_single_wqe_log_num_of_strides = 1049 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1050 resp.striding_rq_caps.max_single_wqe_log_num_of_strides = 1051 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES; 1052 resp.striding_rq_caps.supported_qpts = 1053 BIT(IB_QPT_RAW_PACKET); 1054 } 1055 } 1056 1057 if (field_avail(typeof(resp), tunnel_offloads_caps, 1058 uhw->outlen)) { 1059 resp.response_length += sizeof(resp.tunnel_offloads_caps); 1060 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan)) 1061 resp.tunnel_offloads_caps |= 1062 MLX5_IB_TUNNELED_OFFLOADS_VXLAN; 1063 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx)) 1064 resp.tunnel_offloads_caps |= 1065 MLX5_IB_TUNNELED_OFFLOADS_GENEVE; 1066 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) 1067 resp.tunnel_offloads_caps |= 1068 MLX5_IB_TUNNELED_OFFLOADS_GRE; 1069 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) & 1070 MLX5_FLEX_PROTO_CW_MPLS_GRE) 1071 resp.tunnel_offloads_caps |= 1072 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE; 1073 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) & 1074 MLX5_FLEX_PROTO_CW_MPLS_UDP) 1075 resp.tunnel_offloads_caps |= 1076 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP; 1077 } 1078 1079 if (uhw->outlen) { 1080 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 1081 1082 if (err) 1083 return err; 1084 } 1085 1086 return 0; 1087 } 1088 1089 enum mlx5_ib_width { 1090 MLX5_IB_WIDTH_1X = 1 << 0, 1091 MLX5_IB_WIDTH_2X = 1 << 1, 1092 MLX5_IB_WIDTH_4X = 1 << 2, 1093 MLX5_IB_WIDTH_8X = 1 << 3, 1094 MLX5_IB_WIDTH_12X = 1 << 4 1095 }; 1096 1097 static int translate_active_width(struct ib_device *ibdev, u8 active_width, 1098 u8 *ib_width) 1099 { 1100 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1101 int err = 0; 1102 1103 if (active_width & MLX5_IB_WIDTH_1X) { 1104 *ib_width = IB_WIDTH_1X; 1105 } else if (active_width & MLX5_IB_WIDTH_2X) { 1106 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n", 1107 (int)active_width); 1108 err = -EINVAL; 1109 } else if (active_width & MLX5_IB_WIDTH_4X) { 1110 *ib_width = IB_WIDTH_4X; 1111 } else if (active_width & MLX5_IB_WIDTH_8X) { 1112 *ib_width = IB_WIDTH_8X; 1113 } else if (active_width & MLX5_IB_WIDTH_12X) { 1114 *ib_width = IB_WIDTH_12X; 1115 } else { 1116 mlx5_ib_dbg(dev, "Invalid active_width %d\n", 1117 (int)active_width); 1118 err = -EINVAL; 1119 } 1120 1121 return err; 1122 } 1123 1124 static int mlx5_mtu_to_ib_mtu(int mtu) 1125 { 1126 switch (mtu) { 1127 case 256: return 1; 1128 case 512: return 2; 1129 case 1024: return 3; 1130 case 2048: return 4; 1131 case 4096: return 5; 1132 default: 1133 pr_warn("invalid mtu\n"); 1134 return -1; 1135 } 1136 } 1137 1138 enum ib_max_vl_num { 1139 __IB_MAX_VL_0 = 1, 1140 __IB_MAX_VL_0_1 = 2, 1141 __IB_MAX_VL_0_3 = 3, 1142 __IB_MAX_VL_0_7 = 4, 1143 __IB_MAX_VL_0_14 = 5, 1144 }; 1145 1146 enum mlx5_vl_hw_cap { 1147 MLX5_VL_HW_0 = 1, 1148 MLX5_VL_HW_0_1 = 2, 1149 MLX5_VL_HW_0_2 = 3, 1150 MLX5_VL_HW_0_3 = 4, 1151 MLX5_VL_HW_0_4 = 5, 1152 MLX5_VL_HW_0_5 = 6, 1153 MLX5_VL_HW_0_6 = 7, 1154 MLX5_VL_HW_0_7 = 8, 1155 MLX5_VL_HW_0_14 = 15 1156 }; 1157 1158 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 1159 u8 *max_vl_num) 1160 { 1161 switch (vl_hw_cap) { 1162 case MLX5_VL_HW_0: 1163 *max_vl_num = __IB_MAX_VL_0; 1164 break; 1165 case MLX5_VL_HW_0_1: 1166 *max_vl_num = __IB_MAX_VL_0_1; 1167 break; 1168 case MLX5_VL_HW_0_3: 1169 *max_vl_num = __IB_MAX_VL_0_3; 1170 break; 1171 case MLX5_VL_HW_0_7: 1172 *max_vl_num = __IB_MAX_VL_0_7; 1173 break; 1174 case MLX5_VL_HW_0_14: 1175 *max_vl_num = __IB_MAX_VL_0_14; 1176 break; 1177 1178 default: 1179 return -EINVAL; 1180 } 1181 1182 return 0; 1183 } 1184 1185 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port, 1186 struct ib_port_attr *props) 1187 { 1188 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1189 struct mlx5_core_dev *mdev = dev->mdev; 1190 struct mlx5_hca_vport_context *rep; 1191 u16 max_mtu; 1192 u16 oper_mtu; 1193 int err; 1194 u8 ib_link_width_oper; 1195 u8 vl_hw_cap; 1196 1197 rep = kzalloc(sizeof(*rep), GFP_KERNEL); 1198 if (!rep) { 1199 err = -ENOMEM; 1200 goto out; 1201 } 1202 1203 /* props being zeroed by the caller, avoid zeroing it here */ 1204 1205 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); 1206 if (err) 1207 goto out; 1208 1209 props->lid = rep->lid; 1210 props->lmc = rep->lmc; 1211 props->sm_lid = rep->sm_lid; 1212 props->sm_sl = rep->sm_sl; 1213 props->state = rep->vport_state; 1214 props->phys_state = rep->port_physical_state; 1215 props->port_cap_flags = rep->cap_mask1; 1216 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 1217 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 1218 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 1219 props->bad_pkey_cntr = rep->pkey_violation_counter; 1220 props->qkey_viol_cntr = rep->qkey_violation_counter; 1221 props->subnet_timeout = rep->subnet_timeout; 1222 props->init_type_reply = rep->init_type_reply; 1223 1224 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port); 1225 if (err) 1226 goto out; 1227 1228 err = translate_active_width(ibdev, ib_link_width_oper, 1229 &props->active_width); 1230 if (err) 1231 goto out; 1232 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port); 1233 if (err) 1234 goto out; 1235 1236 mlx5_query_port_max_mtu(mdev, &max_mtu, port); 1237 1238 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); 1239 1240 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); 1241 1242 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); 1243 1244 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); 1245 if (err) 1246 goto out; 1247 1248 err = translate_max_vl_num(ibdev, vl_hw_cap, 1249 &props->max_vl_num); 1250 out: 1251 kfree(rep); 1252 return err; 1253 } 1254 1255 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 1256 struct ib_port_attr *props) 1257 { 1258 unsigned int count; 1259 int ret; 1260 1261 switch (mlx5_get_vport_access_method(ibdev)) { 1262 case MLX5_VPORT_ACCESS_METHOD_MAD: 1263 ret = mlx5_query_mad_ifc_port(ibdev, port, props); 1264 break; 1265 1266 case MLX5_VPORT_ACCESS_METHOD_HCA: 1267 ret = mlx5_query_hca_port(ibdev, port, props); 1268 break; 1269 1270 case MLX5_VPORT_ACCESS_METHOD_NIC: 1271 ret = mlx5_query_port_roce(ibdev, port, props); 1272 break; 1273 1274 default: 1275 ret = -EINVAL; 1276 } 1277 1278 if (!ret && props) { 1279 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1280 struct mlx5_core_dev *mdev; 1281 bool put_mdev = true; 1282 1283 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL); 1284 if (!mdev) { 1285 /* If the port isn't affiliated yet query the master. 1286 * The master and slave will have the same values. 1287 */ 1288 mdev = dev->mdev; 1289 port = 1; 1290 put_mdev = false; 1291 } 1292 count = mlx5_core_reserved_gids_count(mdev); 1293 if (put_mdev) 1294 mlx5_ib_put_native_port_mdev(dev, port); 1295 props->gid_tbl_len -= count; 1296 } 1297 return ret; 1298 } 1299 1300 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port, 1301 struct ib_port_attr *props) 1302 { 1303 int ret; 1304 1305 /* Only link layer == ethernet is valid for representors */ 1306 ret = mlx5_query_port_roce(ibdev, port, props); 1307 if (ret || !props) 1308 return ret; 1309 1310 /* We don't support GIDS */ 1311 props->gid_tbl_len = 0; 1312 1313 return ret; 1314 } 1315 1316 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 1317 union ib_gid *gid) 1318 { 1319 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1320 struct mlx5_core_dev *mdev = dev->mdev; 1321 1322 switch (mlx5_get_vport_access_method(ibdev)) { 1323 case MLX5_VPORT_ACCESS_METHOD_MAD: 1324 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 1325 1326 case MLX5_VPORT_ACCESS_METHOD_HCA: 1327 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); 1328 1329 default: 1330 return -EINVAL; 1331 } 1332 1333 } 1334 1335 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port, 1336 u16 index, u16 *pkey) 1337 { 1338 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1339 struct mlx5_core_dev *mdev; 1340 bool put_mdev = true; 1341 u8 mdev_port_num; 1342 int err; 1343 1344 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num); 1345 if (!mdev) { 1346 /* The port isn't affiliated yet, get the PKey from the master 1347 * port. For RoCE the PKey tables will be the same. 1348 */ 1349 put_mdev = false; 1350 mdev = dev->mdev; 1351 mdev_port_num = 1; 1352 } 1353 1354 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0, 1355 index, pkey); 1356 if (put_mdev) 1357 mlx5_ib_put_native_port_mdev(dev, port); 1358 1359 return err; 1360 } 1361 1362 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 1363 u16 *pkey) 1364 { 1365 switch (mlx5_get_vport_access_method(ibdev)) { 1366 case MLX5_VPORT_ACCESS_METHOD_MAD: 1367 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 1368 1369 case MLX5_VPORT_ACCESS_METHOD_HCA: 1370 case MLX5_VPORT_ACCESS_METHOD_NIC: 1371 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey); 1372 default: 1373 return -EINVAL; 1374 } 1375 } 1376 1377 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 1378 struct ib_device_modify *props) 1379 { 1380 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1381 struct mlx5_reg_node_desc in; 1382 struct mlx5_reg_node_desc out; 1383 int err; 1384 1385 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 1386 return -EOPNOTSUPP; 1387 1388 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 1389 return 0; 1390 1391 /* 1392 * If possible, pass node desc to FW, so it can generate 1393 * a 144 trap. If cmd fails, just ignore. 1394 */ 1395 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1396 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 1397 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 1398 if (err) 1399 return err; 1400 1401 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1402 1403 return err; 1404 } 1405 1406 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask, 1407 u32 value) 1408 { 1409 struct mlx5_hca_vport_context ctx = {}; 1410 struct mlx5_core_dev *mdev; 1411 u8 mdev_port_num; 1412 int err; 1413 1414 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 1415 if (!mdev) 1416 return -ENODEV; 1417 1418 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx); 1419 if (err) 1420 goto out; 1421 1422 if (~ctx.cap_mask1_perm & mask) { 1423 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n", 1424 mask, ctx.cap_mask1_perm); 1425 err = -EINVAL; 1426 goto out; 1427 } 1428 1429 ctx.cap_mask1 = value; 1430 ctx.cap_mask1_perm = mask; 1431 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num, 1432 0, &ctx); 1433 1434 out: 1435 mlx5_ib_put_native_port_mdev(dev, port_num); 1436 1437 return err; 1438 } 1439 1440 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, 1441 struct ib_port_modify *props) 1442 { 1443 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1444 struct ib_port_attr attr; 1445 u32 tmp; 1446 int err; 1447 u32 change_mask; 1448 u32 value; 1449 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) == 1450 IB_LINK_LAYER_INFINIBAND); 1451 1452 /* CM layer calls ib_modify_port() regardless of the link layer. For 1453 * Ethernet ports, qkey violation and Port capabilities are meaningless. 1454 */ 1455 if (!is_ib) 1456 return 0; 1457 1458 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) { 1459 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask; 1460 value = ~props->clr_port_cap_mask | props->set_port_cap_mask; 1461 return set_port_caps_atomic(dev, port, change_mask, value); 1462 } 1463 1464 mutex_lock(&dev->cap_mask_mutex); 1465 1466 err = ib_query_port(ibdev, port, &attr); 1467 if (err) 1468 goto out; 1469 1470 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 1471 ~props->clr_port_cap_mask; 1472 1473 err = mlx5_set_port_caps(dev->mdev, port, tmp); 1474 1475 out: 1476 mutex_unlock(&dev->cap_mask_mutex); 1477 return err; 1478 } 1479 1480 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps) 1481 { 1482 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n", 1483 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n"); 1484 } 1485 1486 static u16 calc_dynamic_bfregs(int uars_per_sys_page) 1487 { 1488 /* Large page with non 4k uar support might limit the dynamic size */ 1489 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096) 1490 return MLX5_MIN_DYN_BFREGS; 1491 1492 return MLX5_MAX_DYN_BFREGS; 1493 } 1494 1495 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k, 1496 struct mlx5_ib_alloc_ucontext_req_v2 *req, 1497 struct mlx5_bfreg_info *bfregi) 1498 { 1499 int uars_per_sys_page; 1500 int bfregs_per_sys_page; 1501 int ref_bfregs = req->total_num_bfregs; 1502 1503 if (req->total_num_bfregs == 0) 1504 return -EINVAL; 1505 1506 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE); 1507 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE); 1508 1509 if (req->total_num_bfregs > MLX5_MAX_BFREGS) 1510 return -ENOMEM; 1511 1512 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k); 1513 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR; 1514 /* This holds the required static allocation asked by the user */ 1515 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page); 1516 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1) 1517 return -EINVAL; 1518 1519 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page; 1520 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page); 1521 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs; 1522 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page; 1523 1524 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n", 1525 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no", 1526 lib_uar_4k ? "yes" : "no", ref_bfregs, 1527 req->total_num_bfregs, bfregi->total_num_bfregs, 1528 bfregi->num_sys_pages); 1529 1530 return 0; 1531 } 1532 1533 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1534 { 1535 struct mlx5_bfreg_info *bfregi; 1536 int err; 1537 int i; 1538 1539 bfregi = &context->bfregi; 1540 for (i = 0; i < bfregi->num_static_sys_pages; i++) { 1541 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]); 1542 if (err) 1543 goto error; 1544 1545 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]); 1546 } 1547 1548 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++) 1549 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX; 1550 1551 return 0; 1552 1553 error: 1554 for (--i; i >= 0; i--) 1555 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i])) 1556 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1557 1558 return err; 1559 } 1560 1561 static void deallocate_uars(struct mlx5_ib_dev *dev, 1562 struct mlx5_ib_ucontext *context) 1563 { 1564 struct mlx5_bfreg_info *bfregi; 1565 int i; 1566 1567 bfregi = &context->bfregi; 1568 for (i = 0; i < bfregi->num_sys_pages; i++) 1569 if (i < bfregi->num_static_sys_pages || 1570 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) 1571 mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]); 1572 } 1573 1574 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn) 1575 { 1576 int err; 1577 1578 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1579 return 0; 1580 1581 err = mlx5_core_alloc_transport_domain(dev->mdev, tdn); 1582 if (err) 1583 return err; 1584 1585 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1586 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1587 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1588 return err; 1589 1590 mutex_lock(&dev->lb_mutex); 1591 dev->user_td++; 1592 1593 if (dev->user_td == 2) 1594 err = mlx5_nic_vport_update_local_lb(dev->mdev, true); 1595 1596 mutex_unlock(&dev->lb_mutex); 1597 return err; 1598 } 1599 1600 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn) 1601 { 1602 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1603 return; 1604 1605 mlx5_core_dealloc_transport_domain(dev->mdev, tdn); 1606 1607 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1608 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1609 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1610 return; 1611 1612 mutex_lock(&dev->lb_mutex); 1613 dev->user_td--; 1614 1615 if (dev->user_td < 2) 1616 mlx5_nic_vport_update_local_lb(dev->mdev, false); 1617 1618 mutex_unlock(&dev->lb_mutex); 1619 } 1620 1621 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev, 1622 struct ib_udata *udata) 1623 { 1624 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1625 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 1626 struct mlx5_ib_alloc_ucontext_resp resp = {}; 1627 struct mlx5_core_dev *mdev = dev->mdev; 1628 struct mlx5_ib_ucontext *context; 1629 struct mlx5_bfreg_info *bfregi; 1630 int ver; 1631 int err; 1632 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 1633 max_cqe_version); 1634 u32 dump_fill_mkey; 1635 bool lib_uar_4k; 1636 1637 if (!dev->ib_active) 1638 return ERR_PTR(-EAGAIN); 1639 1640 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 1641 ver = 0; 1642 else if (udata->inlen >= min_req_v2) 1643 ver = 2; 1644 else 1645 return ERR_PTR(-EINVAL); 1646 1647 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req))); 1648 if (err) 1649 return ERR_PTR(err); 1650 1651 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX) 1652 return ERR_PTR(-EOPNOTSUPP); 1653 1654 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 1655 return ERR_PTR(-EOPNOTSUPP); 1656 1657 req.total_num_bfregs = ALIGN(req.total_num_bfregs, 1658 MLX5_NON_FP_BFREGS_PER_UAR); 1659 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1) 1660 return ERR_PTR(-EINVAL); 1661 1662 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 1663 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf)) 1664 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size); 1665 resp.cache_line_size = cache_line_size(); 1666 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 1667 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 1668 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1669 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1670 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 1671 resp.cqe_version = min_t(__u8, 1672 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 1673 req.max_cqe_version); 1674 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1675 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT; 1676 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1677 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1; 1678 resp.response_length = min(offsetof(typeof(resp), response_length) + 1679 sizeof(resp.response_length), udata->outlen); 1680 1681 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE) { 1682 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_EGRESS)) 1683 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM; 1684 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA) 1685 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA; 1686 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi)) 1687 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING; 1688 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN) 1689 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN; 1690 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */ 1691 } 1692 1693 context = kzalloc(sizeof(*context), GFP_KERNEL); 1694 if (!context) 1695 return ERR_PTR(-ENOMEM); 1696 1697 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR; 1698 bfregi = &context->bfregi; 1699 1700 /* updates req->total_num_bfregs */ 1701 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi); 1702 if (err) 1703 goto out_ctx; 1704 1705 mutex_init(&bfregi->lock); 1706 bfregi->lib_uar_4k = lib_uar_4k; 1707 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count), 1708 GFP_KERNEL); 1709 if (!bfregi->count) { 1710 err = -ENOMEM; 1711 goto out_ctx; 1712 } 1713 1714 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages, 1715 sizeof(*bfregi->sys_pages), 1716 GFP_KERNEL); 1717 if (!bfregi->sys_pages) { 1718 err = -ENOMEM; 1719 goto out_count; 1720 } 1721 1722 err = allocate_uars(dev, context); 1723 if (err) 1724 goto out_sys_pages; 1725 1726 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1727 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range; 1728 #endif 1729 1730 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn); 1731 if (err) 1732 goto out_uars; 1733 1734 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) { 1735 /* Block DEVX on Infiniband as of SELinux */ 1736 if (mlx5_ib_port_link_layer(ibdev, 1) != IB_LINK_LAYER_ETHERNET) { 1737 err = -EPERM; 1738 goto out_td; 1739 } 1740 1741 err = mlx5_ib_devx_create(dev, context); 1742 if (err) 1743 goto out_td; 1744 } 1745 1746 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) { 1747 err = mlx5_cmd_dump_fill_mkey(dev->mdev, &dump_fill_mkey); 1748 if (err) 1749 goto out_mdev; 1750 } 1751 1752 INIT_LIST_HEAD(&context->db_page_list); 1753 mutex_init(&context->db_page_mutex); 1754 1755 resp.tot_bfregs = req.total_num_bfregs; 1756 resp.num_ports = dev->num_ports; 1757 1758 if (field_avail(typeof(resp), cqe_version, udata->outlen)) 1759 resp.response_length += sizeof(resp.cqe_version); 1760 1761 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) { 1762 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 1763 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 1764 resp.response_length += sizeof(resp.cmds_supp_uhw); 1765 } 1766 1767 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) { 1768 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) { 1769 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline); 1770 resp.eth_min_inline++; 1771 } 1772 resp.response_length += sizeof(resp.eth_min_inline); 1773 } 1774 1775 if (field_avail(typeof(resp), clock_info_versions, udata->outlen)) { 1776 if (mdev->clock_info) 1777 resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1); 1778 resp.response_length += sizeof(resp.clock_info_versions); 1779 } 1780 1781 /* 1782 * We don't want to expose information from the PCI bar that is located 1783 * after 4096 bytes, so if the arch only supports larger pages, let's 1784 * pretend we don't support reading the HCA's core clock. This is also 1785 * forced by mmap function. 1786 */ 1787 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) { 1788 if (PAGE_SIZE <= 4096) { 1789 resp.comp_mask |= 1790 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 1791 resp.hca_core_clock_offset = 1792 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE; 1793 } 1794 resp.response_length += sizeof(resp.hca_core_clock_offset); 1795 } 1796 1797 if (field_avail(typeof(resp), log_uar_size, udata->outlen)) 1798 resp.response_length += sizeof(resp.log_uar_size); 1799 1800 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen)) 1801 resp.response_length += sizeof(resp.num_uars_per_page); 1802 1803 if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) { 1804 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs; 1805 resp.response_length += sizeof(resp.num_dyn_bfregs); 1806 } 1807 1808 if (field_avail(typeof(resp), dump_fill_mkey, udata->outlen)) { 1809 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) { 1810 resp.dump_fill_mkey = dump_fill_mkey; 1811 resp.comp_mask |= 1812 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY; 1813 } 1814 resp.response_length += sizeof(resp.dump_fill_mkey); 1815 } 1816 1817 err = ib_copy_to_udata(udata, &resp, resp.response_length); 1818 if (err) 1819 goto out_mdev; 1820 1821 bfregi->ver = ver; 1822 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs; 1823 context->cqe_version = resp.cqe_version; 1824 context->lib_caps = req.lib_caps; 1825 print_lib_caps(dev, context->lib_caps); 1826 1827 if (mlx5_lag_is_active(dev->mdev)) { 1828 u8 port = mlx5_core_native_port_num(dev->mdev); 1829 1830 atomic_set(&context->tx_port_affinity, 1831 atomic_add_return( 1832 1, &dev->roce[port].tx_port_affinity)); 1833 } 1834 1835 return &context->ibucontext; 1836 1837 out_mdev: 1838 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) 1839 mlx5_ib_devx_destroy(dev, context); 1840 out_td: 1841 mlx5_ib_dealloc_transport_domain(dev, context->tdn); 1842 1843 out_uars: 1844 deallocate_uars(dev, context); 1845 1846 out_sys_pages: 1847 kfree(bfregi->sys_pages); 1848 1849 out_count: 1850 kfree(bfregi->count); 1851 1852 out_ctx: 1853 kfree(context); 1854 1855 return ERR_PTR(err); 1856 } 1857 1858 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1859 { 1860 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1861 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1862 struct mlx5_bfreg_info *bfregi; 1863 1864 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1865 /* All umem's must be destroyed before destroying the ucontext. */ 1866 mutex_lock(&ibcontext->per_mm_list_lock); 1867 WARN_ON(!list_empty(&ibcontext->per_mm_list)); 1868 mutex_unlock(&ibcontext->per_mm_list_lock); 1869 #endif 1870 1871 if (context->devx_uid) 1872 mlx5_ib_devx_destroy(dev, context); 1873 1874 bfregi = &context->bfregi; 1875 mlx5_ib_dealloc_transport_domain(dev, context->tdn); 1876 1877 deallocate_uars(dev, context); 1878 kfree(bfregi->sys_pages); 1879 kfree(bfregi->count); 1880 kfree(context); 1881 1882 return 0; 1883 } 1884 1885 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, 1886 int uar_idx) 1887 { 1888 int fw_uars_per_page; 1889 1890 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1; 1891 1892 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + uar_idx / fw_uars_per_page; 1893 } 1894 1895 static int get_command(unsigned long offset) 1896 { 1897 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 1898 } 1899 1900 static int get_arg(unsigned long offset) 1901 { 1902 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 1903 } 1904 1905 static int get_index(unsigned long offset) 1906 { 1907 return get_arg(offset); 1908 } 1909 1910 /* Index resides in an extra byte to enable larger values than 255 */ 1911 static int get_extended_index(unsigned long offset) 1912 { 1913 return get_arg(offset) | ((offset >> 16) & 0xff) << 8; 1914 } 1915 1916 1917 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 1918 { 1919 } 1920 1921 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 1922 { 1923 switch (cmd) { 1924 case MLX5_IB_MMAP_WC_PAGE: 1925 return "WC"; 1926 case MLX5_IB_MMAP_REGULAR_PAGE: 1927 return "best effort WC"; 1928 case MLX5_IB_MMAP_NC_PAGE: 1929 return "NC"; 1930 case MLX5_IB_MMAP_DEVICE_MEM: 1931 return "Device Memory"; 1932 default: 1933 return NULL; 1934 } 1935 } 1936 1937 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev, 1938 struct vm_area_struct *vma, 1939 struct mlx5_ib_ucontext *context) 1940 { 1941 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1942 return -EINVAL; 1943 1944 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1) 1945 return -EOPNOTSUPP; 1946 1947 if (vma->vm_flags & VM_WRITE) 1948 return -EPERM; 1949 1950 if (!dev->mdev->clock_info_page) 1951 return -EOPNOTSUPP; 1952 1953 return rdma_user_mmap_page(&context->ibucontext, vma, 1954 dev->mdev->clock_info_page, PAGE_SIZE); 1955 } 1956 1957 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 1958 struct vm_area_struct *vma, 1959 struct mlx5_ib_ucontext *context) 1960 { 1961 struct mlx5_bfreg_info *bfregi = &context->bfregi; 1962 int err; 1963 unsigned long idx; 1964 phys_addr_t pfn; 1965 pgprot_t prot; 1966 u32 bfreg_dyn_idx = 0; 1967 u32 uar_index; 1968 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC); 1969 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages : 1970 bfregi->num_static_sys_pages; 1971 1972 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1973 return -EINVAL; 1974 1975 if (dyn_uar) 1976 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages; 1977 else 1978 idx = get_index(vma->vm_pgoff); 1979 1980 if (idx >= max_valid_idx) { 1981 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n", 1982 idx, max_valid_idx); 1983 return -EINVAL; 1984 } 1985 1986 switch (cmd) { 1987 case MLX5_IB_MMAP_WC_PAGE: 1988 case MLX5_IB_MMAP_ALLOC_WC: 1989 /* Some architectures don't support WC memory */ 1990 #if defined(CONFIG_X86) 1991 if (!pat_enabled()) 1992 return -EPERM; 1993 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU))) 1994 return -EPERM; 1995 #endif 1996 /* fall through */ 1997 case MLX5_IB_MMAP_REGULAR_PAGE: 1998 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 1999 prot = pgprot_writecombine(vma->vm_page_prot); 2000 break; 2001 case MLX5_IB_MMAP_NC_PAGE: 2002 prot = pgprot_noncached(vma->vm_page_prot); 2003 break; 2004 default: 2005 return -EINVAL; 2006 } 2007 2008 if (dyn_uar) { 2009 int uars_per_page; 2010 2011 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k); 2012 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR); 2013 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) { 2014 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n", 2015 bfreg_dyn_idx, bfregi->total_num_bfregs); 2016 return -EINVAL; 2017 } 2018 2019 mutex_lock(&bfregi->lock); 2020 /* Fail if uar already allocated, first bfreg index of each 2021 * page holds its count. 2022 */ 2023 if (bfregi->count[bfreg_dyn_idx]) { 2024 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx); 2025 mutex_unlock(&bfregi->lock); 2026 return -EINVAL; 2027 } 2028 2029 bfregi->count[bfreg_dyn_idx]++; 2030 mutex_unlock(&bfregi->lock); 2031 2032 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index); 2033 if (err) { 2034 mlx5_ib_warn(dev, "UAR alloc failed\n"); 2035 goto free_bfreg; 2036 } 2037 } else { 2038 uar_index = bfregi->sys_pages[idx]; 2039 } 2040 2041 pfn = uar_index2pfn(dev, uar_index); 2042 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 2043 2044 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE, 2045 prot); 2046 if (err) { 2047 mlx5_ib_err(dev, 2048 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n", 2049 err, mmap_cmd2str(cmd)); 2050 goto err; 2051 } 2052 2053 if (dyn_uar) 2054 bfregi->sys_pages[idx] = uar_index; 2055 return 0; 2056 2057 err: 2058 if (!dyn_uar) 2059 return err; 2060 2061 mlx5_cmd_free_uar(dev->mdev, idx); 2062 2063 free_bfreg: 2064 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx); 2065 2066 return err; 2067 } 2068 2069 static int dm_mmap(struct ib_ucontext *context, struct vm_area_struct *vma) 2070 { 2071 struct mlx5_ib_ucontext *mctx = to_mucontext(context); 2072 struct mlx5_ib_dev *dev = to_mdev(context->device); 2073 u16 page_idx = get_extended_index(vma->vm_pgoff); 2074 size_t map_size = vma->vm_end - vma->vm_start; 2075 u32 npages = map_size >> PAGE_SHIFT; 2076 phys_addr_t pfn; 2077 2078 if (find_next_zero_bit(mctx->dm_pages, page_idx + npages, page_idx) != 2079 page_idx + npages) 2080 return -EINVAL; 2081 2082 pfn = ((pci_resource_start(dev->mdev->pdev, 0) + 2083 MLX5_CAP64_DEV_MEM(dev->mdev, memic_bar_start_addr)) >> 2084 PAGE_SHIFT) + 2085 page_idx; 2086 return rdma_user_mmap_io(context, vma, pfn, map_size, 2087 pgprot_writecombine(vma->vm_page_prot)); 2088 } 2089 2090 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 2091 { 2092 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2093 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2094 unsigned long command; 2095 phys_addr_t pfn; 2096 2097 command = get_command(vma->vm_pgoff); 2098 switch (command) { 2099 case MLX5_IB_MMAP_WC_PAGE: 2100 case MLX5_IB_MMAP_NC_PAGE: 2101 case MLX5_IB_MMAP_REGULAR_PAGE: 2102 case MLX5_IB_MMAP_ALLOC_WC: 2103 return uar_mmap(dev, command, vma, context); 2104 2105 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 2106 return -ENOSYS; 2107 2108 case MLX5_IB_MMAP_CORE_CLOCK: 2109 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2110 return -EINVAL; 2111 2112 if (vma->vm_flags & VM_WRITE) 2113 return -EPERM; 2114 2115 /* Don't expose to user-space information it shouldn't have */ 2116 if (PAGE_SIZE > 4096) 2117 return -EOPNOTSUPP; 2118 2119 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 2120 pfn = (dev->mdev->iseg_base + 2121 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 2122 PAGE_SHIFT; 2123 if (io_remap_pfn_range(vma, vma->vm_start, pfn, 2124 PAGE_SIZE, vma->vm_page_prot)) 2125 return -EAGAIN; 2126 break; 2127 case MLX5_IB_MMAP_CLOCK_INFO: 2128 return mlx5_ib_mmap_clock_info_page(dev, vma, context); 2129 2130 case MLX5_IB_MMAP_DEVICE_MEM: 2131 return dm_mmap(ibcontext, vma); 2132 2133 default: 2134 return -EINVAL; 2135 } 2136 2137 return 0; 2138 } 2139 2140 struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev, 2141 struct ib_ucontext *context, 2142 struct ib_dm_alloc_attr *attr, 2143 struct uverbs_attr_bundle *attrs) 2144 { 2145 u64 act_size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE); 2146 struct mlx5_memic *memic = &to_mdev(ibdev)->memic; 2147 phys_addr_t memic_addr; 2148 struct mlx5_ib_dm *dm; 2149 u64 start_offset; 2150 u32 page_idx; 2151 int err; 2152 2153 dm = kzalloc(sizeof(*dm), GFP_KERNEL); 2154 if (!dm) 2155 return ERR_PTR(-ENOMEM); 2156 2157 mlx5_ib_dbg(to_mdev(ibdev), "alloc_memic req: user_length=0x%llx act_length=0x%llx log_alignment=%d\n", 2158 attr->length, act_size, attr->alignment); 2159 2160 err = mlx5_cmd_alloc_memic(memic, &memic_addr, 2161 act_size, attr->alignment); 2162 if (err) 2163 goto err_free; 2164 2165 start_offset = memic_addr & ~PAGE_MASK; 2166 page_idx = (memic_addr - pci_resource_start(memic->dev->pdev, 0) - 2167 MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >> 2168 PAGE_SHIFT; 2169 2170 err = uverbs_copy_to(attrs, 2171 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET, 2172 &start_offset, sizeof(start_offset)); 2173 if (err) 2174 goto err_dealloc; 2175 2176 err = uverbs_copy_to(attrs, 2177 MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX, 2178 &page_idx, sizeof(page_idx)); 2179 if (err) 2180 goto err_dealloc; 2181 2182 bitmap_set(to_mucontext(context)->dm_pages, page_idx, 2183 DIV_ROUND_UP(act_size, PAGE_SIZE)); 2184 2185 dm->dev_addr = memic_addr; 2186 2187 return &dm->ibdm; 2188 2189 err_dealloc: 2190 mlx5_cmd_dealloc_memic(memic, memic_addr, 2191 act_size); 2192 err_free: 2193 kfree(dm); 2194 return ERR_PTR(err); 2195 } 2196 2197 int mlx5_ib_dealloc_dm(struct ib_dm *ibdm) 2198 { 2199 struct mlx5_memic *memic = &to_mdev(ibdm->device)->memic; 2200 struct mlx5_ib_dm *dm = to_mdm(ibdm); 2201 u64 act_size = roundup(dm->ibdm.length, MLX5_MEMIC_BASE_SIZE); 2202 u32 page_idx; 2203 int ret; 2204 2205 ret = mlx5_cmd_dealloc_memic(memic, dm->dev_addr, act_size); 2206 if (ret) 2207 return ret; 2208 2209 page_idx = (dm->dev_addr - pci_resource_start(memic->dev->pdev, 0) - 2210 MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >> 2211 PAGE_SHIFT; 2212 bitmap_clear(to_mucontext(ibdm->uobject->context)->dm_pages, 2213 page_idx, 2214 DIV_ROUND_UP(act_size, PAGE_SIZE)); 2215 2216 kfree(dm); 2217 2218 return 0; 2219 } 2220 2221 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev, 2222 struct ib_ucontext *context, 2223 struct ib_udata *udata) 2224 { 2225 struct mlx5_ib_alloc_pd_resp resp; 2226 struct mlx5_ib_pd *pd; 2227 int err; 2228 2229 pd = kmalloc(sizeof(*pd), GFP_KERNEL); 2230 if (!pd) 2231 return ERR_PTR(-ENOMEM); 2232 2233 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn); 2234 if (err) { 2235 kfree(pd); 2236 return ERR_PTR(err); 2237 } 2238 2239 if (context) { 2240 resp.pdn = pd->pdn; 2241 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 2242 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn); 2243 kfree(pd); 2244 return ERR_PTR(-EFAULT); 2245 } 2246 } 2247 2248 return &pd->ibpd; 2249 } 2250 2251 static int mlx5_ib_dealloc_pd(struct ib_pd *pd) 2252 { 2253 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 2254 struct mlx5_ib_pd *mpd = to_mpd(pd); 2255 2256 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn); 2257 kfree(mpd); 2258 2259 return 0; 2260 } 2261 2262 enum { 2263 MATCH_CRITERIA_ENABLE_OUTER_BIT, 2264 MATCH_CRITERIA_ENABLE_MISC_BIT, 2265 MATCH_CRITERIA_ENABLE_INNER_BIT, 2266 MATCH_CRITERIA_ENABLE_MISC2_BIT 2267 }; 2268 2269 #define HEADER_IS_ZERO(match_criteria, headers) \ 2270 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \ 2271 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \ 2272 2273 static u8 get_match_criteria_enable(u32 *match_criteria) 2274 { 2275 u8 match_criteria_enable; 2276 2277 match_criteria_enable = 2278 (!HEADER_IS_ZERO(match_criteria, outer_headers)) << 2279 MATCH_CRITERIA_ENABLE_OUTER_BIT; 2280 match_criteria_enable |= 2281 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) << 2282 MATCH_CRITERIA_ENABLE_MISC_BIT; 2283 match_criteria_enable |= 2284 (!HEADER_IS_ZERO(match_criteria, inner_headers)) << 2285 MATCH_CRITERIA_ENABLE_INNER_BIT; 2286 match_criteria_enable |= 2287 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) << 2288 MATCH_CRITERIA_ENABLE_MISC2_BIT; 2289 2290 return match_criteria_enable; 2291 } 2292 2293 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val) 2294 { 2295 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask); 2296 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val); 2297 } 2298 2299 static void set_flow_label(void *misc_c, void *misc_v, u32 mask, u32 val, 2300 bool inner) 2301 { 2302 if (inner) { 2303 MLX5_SET(fte_match_set_misc, 2304 misc_c, inner_ipv6_flow_label, mask); 2305 MLX5_SET(fte_match_set_misc, 2306 misc_v, inner_ipv6_flow_label, val); 2307 } else { 2308 MLX5_SET(fte_match_set_misc, 2309 misc_c, outer_ipv6_flow_label, mask); 2310 MLX5_SET(fte_match_set_misc, 2311 misc_v, outer_ipv6_flow_label, val); 2312 } 2313 } 2314 2315 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val) 2316 { 2317 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask); 2318 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val); 2319 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2); 2320 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2); 2321 } 2322 2323 static int check_mpls_supp_fields(u32 field_support, const __be32 *set_mask) 2324 { 2325 if (MLX5_GET(fte_match_mpls, set_mask, mpls_label) && 2326 !(field_support & MLX5_FIELD_SUPPORT_MPLS_LABEL)) 2327 return -EOPNOTSUPP; 2328 2329 if (MLX5_GET(fte_match_mpls, set_mask, mpls_exp) && 2330 !(field_support & MLX5_FIELD_SUPPORT_MPLS_EXP)) 2331 return -EOPNOTSUPP; 2332 2333 if (MLX5_GET(fte_match_mpls, set_mask, mpls_s_bos) && 2334 !(field_support & MLX5_FIELD_SUPPORT_MPLS_S_BOS)) 2335 return -EOPNOTSUPP; 2336 2337 if (MLX5_GET(fte_match_mpls, set_mask, mpls_ttl) && 2338 !(field_support & MLX5_FIELD_SUPPORT_MPLS_TTL)) 2339 return -EOPNOTSUPP; 2340 2341 return 0; 2342 } 2343 2344 #define LAST_ETH_FIELD vlan_tag 2345 #define LAST_IB_FIELD sl 2346 #define LAST_IPV4_FIELD tos 2347 #define LAST_IPV6_FIELD traffic_class 2348 #define LAST_TCP_UDP_FIELD src_port 2349 #define LAST_TUNNEL_FIELD tunnel_id 2350 #define LAST_FLOW_TAG_FIELD tag_id 2351 #define LAST_DROP_FIELD size 2352 #define LAST_COUNTERS_FIELD counters 2353 2354 /* Field is the last supported field */ 2355 #define FIELDS_NOT_SUPPORTED(filter, field)\ 2356 memchr_inv((void *)&filter.field +\ 2357 sizeof(filter.field), 0,\ 2358 sizeof(filter) -\ 2359 offsetof(typeof(filter), field) -\ 2360 sizeof(filter.field)) 2361 2362 int parse_flow_flow_action(struct mlx5_ib_flow_action *maction, 2363 bool is_egress, 2364 struct mlx5_flow_act *action) 2365 { 2366 2367 switch (maction->ib_action.type) { 2368 case IB_FLOW_ACTION_ESP: 2369 if (action->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT | 2370 MLX5_FLOW_CONTEXT_ACTION_DECRYPT)) 2371 return -EINVAL; 2372 /* Currently only AES_GCM keymat is supported by the driver */ 2373 action->esp_id = (uintptr_t)maction->esp_aes_gcm.ctx; 2374 action->action |= is_egress ? 2375 MLX5_FLOW_CONTEXT_ACTION_ENCRYPT : 2376 MLX5_FLOW_CONTEXT_ACTION_DECRYPT; 2377 return 0; 2378 case IB_FLOW_ACTION_UNSPECIFIED: 2379 if (maction->flow_action_raw.sub_type == 2380 MLX5_IB_FLOW_ACTION_MODIFY_HEADER) { 2381 if (action->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) 2382 return -EINVAL; 2383 action->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR; 2384 action->modify_id = maction->flow_action_raw.action_id; 2385 return 0; 2386 } 2387 if (maction->flow_action_raw.sub_type == 2388 MLX5_IB_FLOW_ACTION_DECAP) { 2389 if (action->action & MLX5_FLOW_CONTEXT_ACTION_DECAP) 2390 return -EINVAL; 2391 action->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP; 2392 return 0; 2393 } 2394 if (maction->flow_action_raw.sub_type == 2395 MLX5_IB_FLOW_ACTION_PACKET_REFORMAT) { 2396 if (action->action & 2397 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT) 2398 return -EINVAL; 2399 action->action |= 2400 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT; 2401 action->reformat_id = 2402 maction->flow_action_raw.action_id; 2403 return 0; 2404 } 2405 /* fall through */ 2406 default: 2407 return -EOPNOTSUPP; 2408 } 2409 } 2410 2411 static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c, 2412 u32 *match_v, const union ib_flow_spec *ib_spec, 2413 const struct ib_flow_attr *flow_attr, 2414 struct mlx5_flow_act *action, u32 prev_type) 2415 { 2416 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c, 2417 misc_parameters); 2418 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v, 2419 misc_parameters); 2420 void *misc_params2_c = MLX5_ADDR_OF(fte_match_param, match_c, 2421 misc_parameters_2); 2422 void *misc_params2_v = MLX5_ADDR_OF(fte_match_param, match_v, 2423 misc_parameters_2); 2424 void *headers_c; 2425 void *headers_v; 2426 int match_ipv; 2427 int ret; 2428 2429 if (ib_spec->type & IB_FLOW_SPEC_INNER) { 2430 headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 2431 inner_headers); 2432 headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 2433 inner_headers); 2434 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2435 ft_field_support.inner_ip_version); 2436 } else { 2437 headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 2438 outer_headers); 2439 headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 2440 outer_headers); 2441 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2442 ft_field_support.outer_ip_version); 2443 } 2444 2445 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) { 2446 case IB_FLOW_SPEC_ETH: 2447 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD)) 2448 return -EOPNOTSUPP; 2449 2450 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2451 dmac_47_16), 2452 ib_spec->eth.mask.dst_mac); 2453 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2454 dmac_47_16), 2455 ib_spec->eth.val.dst_mac); 2456 2457 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2458 smac_47_16), 2459 ib_spec->eth.mask.src_mac); 2460 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2461 smac_47_16), 2462 ib_spec->eth.val.src_mac); 2463 2464 if (ib_spec->eth.mask.vlan_tag) { 2465 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2466 cvlan_tag, 1); 2467 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2468 cvlan_tag, 1); 2469 2470 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2471 first_vid, ntohs(ib_spec->eth.mask.vlan_tag)); 2472 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2473 first_vid, ntohs(ib_spec->eth.val.vlan_tag)); 2474 2475 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2476 first_cfi, 2477 ntohs(ib_spec->eth.mask.vlan_tag) >> 12); 2478 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2479 first_cfi, 2480 ntohs(ib_spec->eth.val.vlan_tag) >> 12); 2481 2482 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2483 first_prio, 2484 ntohs(ib_spec->eth.mask.vlan_tag) >> 13); 2485 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2486 first_prio, 2487 ntohs(ib_spec->eth.val.vlan_tag) >> 13); 2488 } 2489 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2490 ethertype, ntohs(ib_spec->eth.mask.ether_type)); 2491 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2492 ethertype, ntohs(ib_spec->eth.val.ether_type)); 2493 break; 2494 case IB_FLOW_SPEC_IPV4: 2495 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD)) 2496 return -EOPNOTSUPP; 2497 2498 if (match_ipv) { 2499 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2500 ip_version, 0xf); 2501 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2502 ip_version, MLX5_FS_IPV4_VERSION); 2503 } else { 2504 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2505 ethertype, 0xffff); 2506 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2507 ethertype, ETH_P_IP); 2508 } 2509 2510 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2511 src_ipv4_src_ipv6.ipv4_layout.ipv4), 2512 &ib_spec->ipv4.mask.src_ip, 2513 sizeof(ib_spec->ipv4.mask.src_ip)); 2514 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2515 src_ipv4_src_ipv6.ipv4_layout.ipv4), 2516 &ib_spec->ipv4.val.src_ip, 2517 sizeof(ib_spec->ipv4.val.src_ip)); 2518 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2519 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 2520 &ib_spec->ipv4.mask.dst_ip, 2521 sizeof(ib_spec->ipv4.mask.dst_ip)); 2522 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2523 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 2524 &ib_spec->ipv4.val.dst_ip, 2525 sizeof(ib_spec->ipv4.val.dst_ip)); 2526 2527 set_tos(headers_c, headers_v, 2528 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos); 2529 2530 set_proto(headers_c, headers_v, 2531 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto); 2532 break; 2533 case IB_FLOW_SPEC_IPV6: 2534 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD)) 2535 return -EOPNOTSUPP; 2536 2537 if (match_ipv) { 2538 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2539 ip_version, 0xf); 2540 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2541 ip_version, MLX5_FS_IPV6_VERSION); 2542 } else { 2543 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2544 ethertype, 0xffff); 2545 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2546 ethertype, ETH_P_IPV6); 2547 } 2548 2549 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2550 src_ipv4_src_ipv6.ipv6_layout.ipv6), 2551 &ib_spec->ipv6.mask.src_ip, 2552 sizeof(ib_spec->ipv6.mask.src_ip)); 2553 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2554 src_ipv4_src_ipv6.ipv6_layout.ipv6), 2555 &ib_spec->ipv6.val.src_ip, 2556 sizeof(ib_spec->ipv6.val.src_ip)); 2557 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2558 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 2559 &ib_spec->ipv6.mask.dst_ip, 2560 sizeof(ib_spec->ipv6.mask.dst_ip)); 2561 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2562 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 2563 &ib_spec->ipv6.val.dst_ip, 2564 sizeof(ib_spec->ipv6.val.dst_ip)); 2565 2566 set_tos(headers_c, headers_v, 2567 ib_spec->ipv6.mask.traffic_class, 2568 ib_spec->ipv6.val.traffic_class); 2569 2570 set_proto(headers_c, headers_v, 2571 ib_spec->ipv6.mask.next_hdr, 2572 ib_spec->ipv6.val.next_hdr); 2573 2574 set_flow_label(misc_params_c, misc_params_v, 2575 ntohl(ib_spec->ipv6.mask.flow_label), 2576 ntohl(ib_spec->ipv6.val.flow_label), 2577 ib_spec->type & IB_FLOW_SPEC_INNER); 2578 break; 2579 case IB_FLOW_SPEC_ESP: 2580 if (ib_spec->esp.mask.seq) 2581 return -EOPNOTSUPP; 2582 2583 MLX5_SET(fte_match_set_misc, misc_params_c, outer_esp_spi, 2584 ntohl(ib_spec->esp.mask.spi)); 2585 MLX5_SET(fte_match_set_misc, misc_params_v, outer_esp_spi, 2586 ntohl(ib_spec->esp.val.spi)); 2587 break; 2588 case IB_FLOW_SPEC_TCP: 2589 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 2590 LAST_TCP_UDP_FIELD)) 2591 return -EOPNOTSUPP; 2592 2593 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol, 2594 0xff); 2595 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, 2596 IPPROTO_TCP); 2597 2598 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport, 2599 ntohs(ib_spec->tcp_udp.mask.src_port)); 2600 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport, 2601 ntohs(ib_spec->tcp_udp.val.src_port)); 2602 2603 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport, 2604 ntohs(ib_spec->tcp_udp.mask.dst_port)); 2605 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport, 2606 ntohs(ib_spec->tcp_udp.val.dst_port)); 2607 break; 2608 case IB_FLOW_SPEC_UDP: 2609 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 2610 LAST_TCP_UDP_FIELD)) 2611 return -EOPNOTSUPP; 2612 2613 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol, 2614 0xff); 2615 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, 2616 IPPROTO_UDP); 2617 2618 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport, 2619 ntohs(ib_spec->tcp_udp.mask.src_port)); 2620 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport, 2621 ntohs(ib_spec->tcp_udp.val.src_port)); 2622 2623 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport, 2624 ntohs(ib_spec->tcp_udp.mask.dst_port)); 2625 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, 2626 ntohs(ib_spec->tcp_udp.val.dst_port)); 2627 break; 2628 case IB_FLOW_SPEC_GRE: 2629 if (ib_spec->gre.mask.c_ks_res0_ver) 2630 return -EOPNOTSUPP; 2631 2632 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol, 2633 0xff); 2634 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, 2635 IPPROTO_GRE); 2636 2637 MLX5_SET(fte_match_set_misc, misc_params_c, gre_protocol, 2638 ntohs(ib_spec->gre.mask.protocol)); 2639 MLX5_SET(fte_match_set_misc, misc_params_v, gre_protocol, 2640 ntohs(ib_spec->gre.val.protocol)); 2641 2642 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_c, 2643 gre_key_h), 2644 &ib_spec->gre.mask.key, 2645 sizeof(ib_spec->gre.mask.key)); 2646 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_v, 2647 gre_key_h), 2648 &ib_spec->gre.val.key, 2649 sizeof(ib_spec->gre.val.key)); 2650 break; 2651 case IB_FLOW_SPEC_MPLS: 2652 switch (prev_type) { 2653 case IB_FLOW_SPEC_UDP: 2654 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2655 ft_field_support.outer_first_mpls_over_udp), 2656 &ib_spec->mpls.mask.tag)) 2657 return -EOPNOTSUPP; 2658 2659 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v, 2660 outer_first_mpls_over_udp), 2661 &ib_spec->mpls.val.tag, 2662 sizeof(ib_spec->mpls.val.tag)); 2663 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c, 2664 outer_first_mpls_over_udp), 2665 &ib_spec->mpls.mask.tag, 2666 sizeof(ib_spec->mpls.mask.tag)); 2667 break; 2668 case IB_FLOW_SPEC_GRE: 2669 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2670 ft_field_support.outer_first_mpls_over_gre), 2671 &ib_spec->mpls.mask.tag)) 2672 return -EOPNOTSUPP; 2673 2674 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v, 2675 outer_first_mpls_over_gre), 2676 &ib_spec->mpls.val.tag, 2677 sizeof(ib_spec->mpls.val.tag)); 2678 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c, 2679 outer_first_mpls_over_gre), 2680 &ib_spec->mpls.mask.tag, 2681 sizeof(ib_spec->mpls.mask.tag)); 2682 break; 2683 default: 2684 if (ib_spec->type & IB_FLOW_SPEC_INNER) { 2685 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2686 ft_field_support.inner_first_mpls), 2687 &ib_spec->mpls.mask.tag)) 2688 return -EOPNOTSUPP; 2689 2690 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v, 2691 inner_first_mpls), 2692 &ib_spec->mpls.val.tag, 2693 sizeof(ib_spec->mpls.val.tag)); 2694 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c, 2695 inner_first_mpls), 2696 &ib_spec->mpls.mask.tag, 2697 sizeof(ib_spec->mpls.mask.tag)); 2698 } else { 2699 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2700 ft_field_support.outer_first_mpls), 2701 &ib_spec->mpls.mask.tag)) 2702 return -EOPNOTSUPP; 2703 2704 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v, 2705 outer_first_mpls), 2706 &ib_spec->mpls.val.tag, 2707 sizeof(ib_spec->mpls.val.tag)); 2708 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c, 2709 outer_first_mpls), 2710 &ib_spec->mpls.mask.tag, 2711 sizeof(ib_spec->mpls.mask.tag)); 2712 } 2713 } 2714 break; 2715 case IB_FLOW_SPEC_VXLAN_TUNNEL: 2716 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask, 2717 LAST_TUNNEL_FIELD)) 2718 return -EOPNOTSUPP; 2719 2720 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni, 2721 ntohl(ib_spec->tunnel.mask.tunnel_id)); 2722 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni, 2723 ntohl(ib_spec->tunnel.val.tunnel_id)); 2724 break; 2725 case IB_FLOW_SPEC_ACTION_TAG: 2726 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag, 2727 LAST_FLOW_TAG_FIELD)) 2728 return -EOPNOTSUPP; 2729 if (ib_spec->flow_tag.tag_id >= BIT(24)) 2730 return -EINVAL; 2731 2732 action->flow_tag = ib_spec->flow_tag.tag_id; 2733 action->has_flow_tag = true; 2734 break; 2735 case IB_FLOW_SPEC_ACTION_DROP: 2736 if (FIELDS_NOT_SUPPORTED(ib_spec->drop, 2737 LAST_DROP_FIELD)) 2738 return -EOPNOTSUPP; 2739 action->action |= MLX5_FLOW_CONTEXT_ACTION_DROP; 2740 break; 2741 case IB_FLOW_SPEC_ACTION_HANDLE: 2742 ret = parse_flow_flow_action(to_mflow_act(ib_spec->action.act), 2743 flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS, action); 2744 if (ret) 2745 return ret; 2746 break; 2747 case IB_FLOW_SPEC_ACTION_COUNT: 2748 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_count, 2749 LAST_COUNTERS_FIELD)) 2750 return -EOPNOTSUPP; 2751 2752 /* for now support only one counters spec per flow */ 2753 if (action->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) 2754 return -EINVAL; 2755 2756 action->counters = ib_spec->flow_count.counters; 2757 action->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT; 2758 break; 2759 default: 2760 return -EINVAL; 2761 } 2762 2763 return 0; 2764 } 2765 2766 /* If a flow could catch both multicast and unicast packets, 2767 * it won't fall into the multicast flow steering table and this rule 2768 * could steal other multicast packets. 2769 */ 2770 static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr) 2771 { 2772 union ib_flow_spec *flow_spec; 2773 2774 if (ib_attr->type != IB_FLOW_ATTR_NORMAL || 2775 ib_attr->num_of_specs < 1) 2776 return false; 2777 2778 flow_spec = (union ib_flow_spec *)(ib_attr + 1); 2779 if (flow_spec->type == IB_FLOW_SPEC_IPV4) { 2780 struct ib_flow_spec_ipv4 *ipv4_spec; 2781 2782 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec; 2783 if (ipv4_is_multicast(ipv4_spec->val.dst_ip)) 2784 return true; 2785 2786 return false; 2787 } 2788 2789 if (flow_spec->type == IB_FLOW_SPEC_ETH) { 2790 struct ib_flow_spec_eth *eth_spec; 2791 2792 eth_spec = (struct ib_flow_spec_eth *)flow_spec; 2793 return is_multicast_ether_addr(eth_spec->mask.dst_mac) && 2794 is_multicast_ether_addr(eth_spec->val.dst_mac); 2795 } 2796 2797 return false; 2798 } 2799 2800 enum valid_spec { 2801 VALID_SPEC_INVALID, 2802 VALID_SPEC_VALID, 2803 VALID_SPEC_NA, 2804 }; 2805 2806 static enum valid_spec 2807 is_valid_esp_aes_gcm(struct mlx5_core_dev *mdev, 2808 const struct mlx5_flow_spec *spec, 2809 const struct mlx5_flow_act *flow_act, 2810 bool egress) 2811 { 2812 const u32 *match_c = spec->match_criteria; 2813 bool is_crypto = 2814 (flow_act->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT | 2815 MLX5_FLOW_CONTEXT_ACTION_DECRYPT)); 2816 bool is_ipsec = mlx5_fs_is_ipsec_flow(match_c); 2817 bool is_drop = flow_act->action & MLX5_FLOW_CONTEXT_ACTION_DROP; 2818 2819 /* 2820 * Currently only crypto is supported in egress, when regular egress 2821 * rules would be supported, always return VALID_SPEC_NA. 2822 */ 2823 if (!is_crypto) 2824 return VALID_SPEC_NA; 2825 2826 return is_crypto && is_ipsec && 2827 (!egress || (!is_drop && !flow_act->has_flow_tag)) ? 2828 VALID_SPEC_VALID : VALID_SPEC_INVALID; 2829 } 2830 2831 static bool is_valid_spec(struct mlx5_core_dev *mdev, 2832 const struct mlx5_flow_spec *spec, 2833 const struct mlx5_flow_act *flow_act, 2834 bool egress) 2835 { 2836 /* We curretly only support ipsec egress flow */ 2837 return is_valid_esp_aes_gcm(mdev, spec, flow_act, egress) != VALID_SPEC_INVALID; 2838 } 2839 2840 static bool is_valid_ethertype(struct mlx5_core_dev *mdev, 2841 const struct ib_flow_attr *flow_attr, 2842 bool check_inner) 2843 { 2844 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1); 2845 int match_ipv = check_inner ? 2846 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2847 ft_field_support.inner_ip_version) : 2848 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2849 ft_field_support.outer_ip_version); 2850 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0; 2851 bool ipv4_spec_valid, ipv6_spec_valid; 2852 unsigned int ip_spec_type = 0; 2853 bool has_ethertype = false; 2854 unsigned int spec_index; 2855 bool mask_valid = true; 2856 u16 eth_type = 0; 2857 bool type_valid; 2858 2859 /* Validate that ethertype is correct */ 2860 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 2861 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) && 2862 ib_spec->eth.mask.ether_type) { 2863 mask_valid = (ib_spec->eth.mask.ether_type == 2864 htons(0xffff)); 2865 has_ethertype = true; 2866 eth_type = ntohs(ib_spec->eth.val.ether_type); 2867 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) || 2868 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) { 2869 ip_spec_type = ib_spec->type; 2870 } 2871 ib_spec = (void *)ib_spec + ib_spec->size; 2872 } 2873 2874 type_valid = (!has_ethertype) || (!ip_spec_type); 2875 if (!type_valid && mask_valid) { 2876 ipv4_spec_valid = (eth_type == ETH_P_IP) && 2877 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit)); 2878 ipv6_spec_valid = (eth_type == ETH_P_IPV6) && 2879 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit)); 2880 2881 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) || 2882 (((eth_type == ETH_P_MPLS_UC) || 2883 (eth_type == ETH_P_MPLS_MC)) && match_ipv); 2884 } 2885 2886 return type_valid; 2887 } 2888 2889 static bool is_valid_attr(struct mlx5_core_dev *mdev, 2890 const struct ib_flow_attr *flow_attr) 2891 { 2892 return is_valid_ethertype(mdev, flow_attr, false) && 2893 is_valid_ethertype(mdev, flow_attr, true); 2894 } 2895 2896 static void put_flow_table(struct mlx5_ib_dev *dev, 2897 struct mlx5_ib_flow_prio *prio, bool ft_added) 2898 { 2899 prio->refcount -= !!ft_added; 2900 if (!prio->refcount) { 2901 mlx5_destroy_flow_table(prio->flow_table); 2902 prio->flow_table = NULL; 2903 } 2904 } 2905 2906 static void counters_clear_description(struct ib_counters *counters) 2907 { 2908 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters); 2909 2910 mutex_lock(&mcounters->mcntrs_mutex); 2911 kfree(mcounters->counters_data); 2912 mcounters->counters_data = NULL; 2913 mcounters->cntrs_max_index = 0; 2914 mutex_unlock(&mcounters->mcntrs_mutex); 2915 } 2916 2917 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id) 2918 { 2919 struct mlx5_ib_flow_handler *handler = container_of(flow_id, 2920 struct mlx5_ib_flow_handler, 2921 ibflow); 2922 struct mlx5_ib_flow_handler *iter, *tmp; 2923 struct mlx5_ib_dev *dev = handler->dev; 2924 2925 mutex_lock(&dev->flow_db->lock); 2926 2927 list_for_each_entry_safe(iter, tmp, &handler->list, list) { 2928 mlx5_del_flow_rules(iter->rule); 2929 put_flow_table(dev, iter->prio, true); 2930 list_del(&iter->list); 2931 kfree(iter); 2932 } 2933 2934 mlx5_del_flow_rules(handler->rule); 2935 put_flow_table(dev, handler->prio, true); 2936 if (handler->ibcounters && 2937 atomic_read(&handler->ibcounters->usecnt) == 1) 2938 counters_clear_description(handler->ibcounters); 2939 2940 mutex_unlock(&dev->flow_db->lock); 2941 if (handler->flow_matcher) 2942 atomic_dec(&handler->flow_matcher->usecnt); 2943 kfree(handler); 2944 2945 return 0; 2946 } 2947 2948 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap) 2949 { 2950 priority *= 2; 2951 if (!dont_trap) 2952 priority++; 2953 return priority; 2954 } 2955 2956 enum flow_table_type { 2957 MLX5_IB_FT_RX, 2958 MLX5_IB_FT_TX 2959 }; 2960 2961 #define MLX5_FS_MAX_TYPES 6 2962 #define MLX5_FS_MAX_ENTRIES BIT(16) 2963 2964 static struct mlx5_ib_flow_prio *_get_prio(struct mlx5_flow_namespace *ns, 2965 struct mlx5_ib_flow_prio *prio, 2966 int priority, 2967 int num_entries, int num_groups, 2968 u32 flags) 2969 { 2970 struct mlx5_flow_table *ft; 2971 2972 ft = mlx5_create_auto_grouped_flow_table(ns, priority, 2973 num_entries, 2974 num_groups, 2975 0, flags); 2976 if (IS_ERR(ft)) 2977 return ERR_CAST(ft); 2978 2979 prio->flow_table = ft; 2980 prio->refcount = 0; 2981 return prio; 2982 } 2983 2984 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev, 2985 struct ib_flow_attr *flow_attr, 2986 enum flow_table_type ft_type) 2987 { 2988 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP; 2989 struct mlx5_flow_namespace *ns = NULL; 2990 struct mlx5_ib_flow_prio *prio; 2991 struct mlx5_flow_table *ft; 2992 int max_table_size; 2993 int num_entries; 2994 int num_groups; 2995 u32 flags = 0; 2996 int priority; 2997 2998 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 2999 log_max_ft_size)); 3000 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 3001 enum mlx5_flow_namespace_type fn_type; 3002 3003 if (flow_is_multicast_only(flow_attr) && 3004 !dont_trap) 3005 priority = MLX5_IB_FLOW_MCAST_PRIO; 3006 else 3007 priority = ib_prio_to_core_prio(flow_attr->priority, 3008 dont_trap); 3009 if (ft_type == MLX5_IB_FT_RX) { 3010 fn_type = MLX5_FLOW_NAMESPACE_BYPASS; 3011 prio = &dev->flow_db->prios[priority]; 3012 if (!dev->rep && 3013 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap)) 3014 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP; 3015 if (!dev->rep && 3016 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 3017 reformat_l3_tunnel_to_l2)) 3018 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT; 3019 } else { 3020 max_table_size = 3021 BIT(MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, 3022 log_max_ft_size)); 3023 fn_type = MLX5_FLOW_NAMESPACE_EGRESS; 3024 prio = &dev->flow_db->egress_prios[priority]; 3025 if (!dev->rep && 3026 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat)) 3027 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT; 3028 } 3029 ns = mlx5_get_flow_namespace(dev->mdev, fn_type); 3030 num_entries = MLX5_FS_MAX_ENTRIES; 3031 num_groups = MLX5_FS_MAX_TYPES; 3032 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 3033 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 3034 ns = mlx5_get_flow_namespace(dev->mdev, 3035 MLX5_FLOW_NAMESPACE_LEFTOVERS); 3036 build_leftovers_ft_param(&priority, 3037 &num_entries, 3038 &num_groups); 3039 prio = &dev->flow_db->prios[MLX5_IB_FLOW_LEFTOVERS_PRIO]; 3040 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 3041 if (!MLX5_CAP_FLOWTABLE(dev->mdev, 3042 allow_sniffer_and_nic_rx_shared_tir)) 3043 return ERR_PTR(-ENOTSUPP); 3044 3045 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ? 3046 MLX5_FLOW_NAMESPACE_SNIFFER_RX : 3047 MLX5_FLOW_NAMESPACE_SNIFFER_TX); 3048 3049 prio = &dev->flow_db->sniffer[ft_type]; 3050 priority = 0; 3051 num_entries = 1; 3052 num_groups = 1; 3053 } 3054 3055 if (!ns) 3056 return ERR_PTR(-ENOTSUPP); 3057 3058 if (num_entries > max_table_size) 3059 return ERR_PTR(-ENOMEM); 3060 3061 ft = prio->flow_table; 3062 if (!ft) 3063 return _get_prio(ns, prio, priority, num_entries, num_groups, 3064 flags); 3065 3066 return prio; 3067 } 3068 3069 static void set_underlay_qp(struct mlx5_ib_dev *dev, 3070 struct mlx5_flow_spec *spec, 3071 u32 underlay_qpn) 3072 { 3073 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, 3074 spec->match_criteria, 3075 misc_parameters); 3076 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, 3077 misc_parameters); 3078 3079 if (underlay_qpn && 3080 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 3081 ft_field_support.bth_dst_qp)) { 3082 MLX5_SET(fte_match_set_misc, 3083 misc_params_v, bth_dst_qp, underlay_qpn); 3084 MLX5_SET(fte_match_set_misc, 3085 misc_params_c, bth_dst_qp, 0xffffff); 3086 } 3087 } 3088 3089 static int read_flow_counters(struct ib_device *ibdev, 3090 struct mlx5_read_counters_attr *read_attr) 3091 { 3092 struct mlx5_fc *fc = read_attr->hw_cntrs_hndl; 3093 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3094 3095 return mlx5_fc_query(dev->mdev, fc, 3096 &read_attr->out[IB_COUNTER_PACKETS], 3097 &read_attr->out[IB_COUNTER_BYTES]); 3098 } 3099 3100 /* flow counters currently expose two counters packets and bytes */ 3101 #define FLOW_COUNTERS_NUM 2 3102 static int counters_set_description(struct ib_counters *counters, 3103 enum mlx5_ib_counters_type counters_type, 3104 struct mlx5_ib_flow_counters_desc *desc_data, 3105 u32 ncounters) 3106 { 3107 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters); 3108 u32 cntrs_max_index = 0; 3109 int i; 3110 3111 if (counters_type != MLX5_IB_COUNTERS_FLOW) 3112 return -EINVAL; 3113 3114 /* init the fields for the object */ 3115 mcounters->type = counters_type; 3116 mcounters->read_counters = read_flow_counters; 3117 mcounters->counters_num = FLOW_COUNTERS_NUM; 3118 mcounters->ncounters = ncounters; 3119 /* each counter entry have both description and index pair */ 3120 for (i = 0; i < ncounters; i++) { 3121 if (desc_data[i].description > IB_COUNTER_BYTES) 3122 return -EINVAL; 3123 3124 if (cntrs_max_index <= desc_data[i].index) 3125 cntrs_max_index = desc_data[i].index + 1; 3126 } 3127 3128 mutex_lock(&mcounters->mcntrs_mutex); 3129 mcounters->counters_data = desc_data; 3130 mcounters->cntrs_max_index = cntrs_max_index; 3131 mutex_unlock(&mcounters->mcntrs_mutex); 3132 3133 return 0; 3134 } 3135 3136 #define MAX_COUNTERS_NUM (USHRT_MAX / (sizeof(u32) * 2)) 3137 static int flow_counters_set_data(struct ib_counters *ibcounters, 3138 struct mlx5_ib_create_flow *ucmd) 3139 { 3140 struct mlx5_ib_mcounters *mcounters = to_mcounters(ibcounters); 3141 struct mlx5_ib_flow_counters_data *cntrs_data = NULL; 3142 struct mlx5_ib_flow_counters_desc *desc_data = NULL; 3143 bool hw_hndl = false; 3144 int ret = 0; 3145 3146 if (ucmd && ucmd->ncounters_data != 0) { 3147 cntrs_data = ucmd->data; 3148 if (cntrs_data->ncounters > MAX_COUNTERS_NUM) 3149 return -EINVAL; 3150 3151 desc_data = kcalloc(cntrs_data->ncounters, 3152 sizeof(*desc_data), 3153 GFP_KERNEL); 3154 if (!desc_data) 3155 return -ENOMEM; 3156 3157 if (copy_from_user(desc_data, 3158 u64_to_user_ptr(cntrs_data->counters_data), 3159 sizeof(*desc_data) * cntrs_data->ncounters)) { 3160 ret = -EFAULT; 3161 goto free; 3162 } 3163 } 3164 3165 if (!mcounters->hw_cntrs_hndl) { 3166 mcounters->hw_cntrs_hndl = mlx5_fc_create( 3167 to_mdev(ibcounters->device)->mdev, false); 3168 if (IS_ERR(mcounters->hw_cntrs_hndl)) { 3169 ret = PTR_ERR(mcounters->hw_cntrs_hndl); 3170 goto free; 3171 } 3172 hw_hndl = true; 3173 } 3174 3175 if (desc_data) { 3176 /* counters already bound to at least one flow */ 3177 if (mcounters->cntrs_max_index) { 3178 ret = -EINVAL; 3179 goto free_hndl; 3180 } 3181 3182 ret = counters_set_description(ibcounters, 3183 MLX5_IB_COUNTERS_FLOW, 3184 desc_data, 3185 cntrs_data->ncounters); 3186 if (ret) 3187 goto free_hndl; 3188 3189 } else if (!mcounters->cntrs_max_index) { 3190 /* counters not bound yet, must have udata passed */ 3191 ret = -EINVAL; 3192 goto free_hndl; 3193 } 3194 3195 return 0; 3196 3197 free_hndl: 3198 if (hw_hndl) { 3199 mlx5_fc_destroy(to_mdev(ibcounters->device)->mdev, 3200 mcounters->hw_cntrs_hndl); 3201 mcounters->hw_cntrs_hndl = NULL; 3202 } 3203 free: 3204 kfree(desc_data); 3205 return ret; 3206 } 3207 3208 static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev, 3209 struct mlx5_ib_flow_prio *ft_prio, 3210 const struct ib_flow_attr *flow_attr, 3211 struct mlx5_flow_destination *dst, 3212 u32 underlay_qpn, 3213 struct mlx5_ib_create_flow *ucmd) 3214 { 3215 struct mlx5_flow_table *ft = ft_prio->flow_table; 3216 struct mlx5_ib_flow_handler *handler; 3217 struct mlx5_flow_act flow_act = {.flow_tag = MLX5_FS_DEFAULT_FLOW_TAG}; 3218 struct mlx5_flow_spec *spec; 3219 struct mlx5_flow_destination dest_arr[2] = {}; 3220 struct mlx5_flow_destination *rule_dst = dest_arr; 3221 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr); 3222 unsigned int spec_index; 3223 u32 prev_type = 0; 3224 int err = 0; 3225 int dest_num = 0; 3226 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS; 3227 3228 if (!is_valid_attr(dev->mdev, flow_attr)) 3229 return ERR_PTR(-EINVAL); 3230 3231 if (dev->rep && is_egress) 3232 return ERR_PTR(-EINVAL); 3233 3234 spec = kvzalloc(sizeof(*spec), GFP_KERNEL); 3235 handler = kzalloc(sizeof(*handler), GFP_KERNEL); 3236 if (!handler || !spec) { 3237 err = -ENOMEM; 3238 goto free; 3239 } 3240 3241 INIT_LIST_HEAD(&handler->list); 3242 if (dst) { 3243 memcpy(&dest_arr[0], dst, sizeof(*dst)); 3244 dest_num++; 3245 } 3246 3247 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 3248 err = parse_flow_attr(dev->mdev, spec->match_criteria, 3249 spec->match_value, 3250 ib_flow, flow_attr, &flow_act, 3251 prev_type); 3252 if (err < 0) 3253 goto free; 3254 3255 prev_type = ((union ib_flow_spec *)ib_flow)->type; 3256 ib_flow += ((union ib_flow_spec *)ib_flow)->size; 3257 } 3258 3259 if (!flow_is_multicast_only(flow_attr)) 3260 set_underlay_qp(dev, spec, underlay_qpn); 3261 3262 if (dev->rep) { 3263 void *misc; 3264 3265 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, 3266 misc_parameters); 3267 MLX5_SET(fte_match_set_misc, misc, source_port, 3268 dev->rep->vport); 3269 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, 3270 misc_parameters); 3271 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port); 3272 } 3273 3274 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria); 3275 3276 if (is_egress && 3277 !is_valid_spec(dev->mdev, spec, &flow_act, is_egress)) { 3278 err = -EINVAL; 3279 goto free; 3280 } 3281 3282 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) { 3283 err = flow_counters_set_data(flow_act.counters, ucmd); 3284 if (err) 3285 goto free; 3286 3287 handler->ibcounters = flow_act.counters; 3288 dest_arr[dest_num].type = 3289 MLX5_FLOW_DESTINATION_TYPE_COUNTER; 3290 dest_arr[dest_num].counter = 3291 to_mcounters(flow_act.counters)->hw_cntrs_hndl; 3292 dest_num++; 3293 } 3294 3295 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP) { 3296 if (!(flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT)) { 3297 rule_dst = NULL; 3298 dest_num = 0; 3299 } 3300 } else { 3301 if (is_egress) 3302 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW; 3303 else 3304 flow_act.action |= 3305 dest_num ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST : 3306 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO; 3307 } 3308 3309 if (flow_act.has_flow_tag && 3310 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 3311 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) { 3312 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n", 3313 flow_act.flow_tag, flow_attr->type); 3314 err = -EINVAL; 3315 goto free; 3316 } 3317 handler->rule = mlx5_add_flow_rules(ft, spec, 3318 &flow_act, 3319 rule_dst, dest_num); 3320 3321 if (IS_ERR(handler->rule)) { 3322 err = PTR_ERR(handler->rule); 3323 goto free; 3324 } 3325 3326 ft_prio->refcount++; 3327 handler->prio = ft_prio; 3328 handler->dev = dev; 3329 3330 ft_prio->flow_table = ft; 3331 free: 3332 if (err && handler) { 3333 if (handler->ibcounters && 3334 atomic_read(&handler->ibcounters->usecnt) == 1) 3335 counters_clear_description(handler->ibcounters); 3336 kfree(handler); 3337 } 3338 kvfree(spec); 3339 return err ? ERR_PTR(err) : handler; 3340 } 3341 3342 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev, 3343 struct mlx5_ib_flow_prio *ft_prio, 3344 const struct ib_flow_attr *flow_attr, 3345 struct mlx5_flow_destination *dst) 3346 { 3347 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0, NULL); 3348 } 3349 3350 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev, 3351 struct mlx5_ib_flow_prio *ft_prio, 3352 struct ib_flow_attr *flow_attr, 3353 struct mlx5_flow_destination *dst) 3354 { 3355 struct mlx5_ib_flow_handler *handler_dst = NULL; 3356 struct mlx5_ib_flow_handler *handler = NULL; 3357 3358 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL); 3359 if (!IS_ERR(handler)) { 3360 handler_dst = create_flow_rule(dev, ft_prio, 3361 flow_attr, dst); 3362 if (IS_ERR(handler_dst)) { 3363 mlx5_del_flow_rules(handler->rule); 3364 ft_prio->refcount--; 3365 kfree(handler); 3366 handler = handler_dst; 3367 } else { 3368 list_add(&handler_dst->list, &handler->list); 3369 } 3370 } 3371 3372 return handler; 3373 } 3374 enum { 3375 LEFTOVERS_MC, 3376 LEFTOVERS_UC, 3377 }; 3378 3379 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev, 3380 struct mlx5_ib_flow_prio *ft_prio, 3381 struct ib_flow_attr *flow_attr, 3382 struct mlx5_flow_destination *dst) 3383 { 3384 struct mlx5_ib_flow_handler *handler_ucast = NULL; 3385 struct mlx5_ib_flow_handler *handler = NULL; 3386 3387 static struct { 3388 struct ib_flow_attr flow_attr; 3389 struct ib_flow_spec_eth eth_flow; 3390 } leftovers_specs[] = { 3391 [LEFTOVERS_MC] = { 3392 .flow_attr = { 3393 .num_of_specs = 1, 3394 .size = sizeof(leftovers_specs[0]) 3395 }, 3396 .eth_flow = { 3397 .type = IB_FLOW_SPEC_ETH, 3398 .size = sizeof(struct ib_flow_spec_eth), 3399 .mask = {.dst_mac = {0x1} }, 3400 .val = {.dst_mac = {0x1} } 3401 } 3402 }, 3403 [LEFTOVERS_UC] = { 3404 .flow_attr = { 3405 .num_of_specs = 1, 3406 .size = sizeof(leftovers_specs[0]) 3407 }, 3408 .eth_flow = { 3409 .type = IB_FLOW_SPEC_ETH, 3410 .size = sizeof(struct ib_flow_spec_eth), 3411 .mask = {.dst_mac = {0x1} }, 3412 .val = {.dst_mac = {} } 3413 } 3414 } 3415 }; 3416 3417 handler = create_flow_rule(dev, ft_prio, 3418 &leftovers_specs[LEFTOVERS_MC].flow_attr, 3419 dst); 3420 if (!IS_ERR(handler) && 3421 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) { 3422 handler_ucast = create_flow_rule(dev, ft_prio, 3423 &leftovers_specs[LEFTOVERS_UC].flow_attr, 3424 dst); 3425 if (IS_ERR(handler_ucast)) { 3426 mlx5_del_flow_rules(handler->rule); 3427 ft_prio->refcount--; 3428 kfree(handler); 3429 handler = handler_ucast; 3430 } else { 3431 list_add(&handler_ucast->list, &handler->list); 3432 } 3433 } 3434 3435 return handler; 3436 } 3437 3438 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev, 3439 struct mlx5_ib_flow_prio *ft_rx, 3440 struct mlx5_ib_flow_prio *ft_tx, 3441 struct mlx5_flow_destination *dst) 3442 { 3443 struct mlx5_ib_flow_handler *handler_rx; 3444 struct mlx5_ib_flow_handler *handler_tx; 3445 int err; 3446 static const struct ib_flow_attr flow_attr = { 3447 .num_of_specs = 0, 3448 .size = sizeof(flow_attr) 3449 }; 3450 3451 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst); 3452 if (IS_ERR(handler_rx)) { 3453 err = PTR_ERR(handler_rx); 3454 goto err; 3455 } 3456 3457 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst); 3458 if (IS_ERR(handler_tx)) { 3459 err = PTR_ERR(handler_tx); 3460 goto err_tx; 3461 } 3462 3463 list_add(&handler_tx->list, &handler_rx->list); 3464 3465 return handler_rx; 3466 3467 err_tx: 3468 mlx5_del_flow_rules(handler_rx->rule); 3469 ft_rx->refcount--; 3470 kfree(handler_rx); 3471 err: 3472 return ERR_PTR(err); 3473 } 3474 3475 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp, 3476 struct ib_flow_attr *flow_attr, 3477 int domain, 3478 struct ib_udata *udata) 3479 { 3480 struct mlx5_ib_dev *dev = to_mdev(qp->device); 3481 struct mlx5_ib_qp *mqp = to_mqp(qp); 3482 struct mlx5_ib_flow_handler *handler = NULL; 3483 struct mlx5_flow_destination *dst = NULL; 3484 struct mlx5_ib_flow_prio *ft_prio_tx = NULL; 3485 struct mlx5_ib_flow_prio *ft_prio; 3486 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS; 3487 struct mlx5_ib_create_flow *ucmd = NULL, ucmd_hdr; 3488 size_t min_ucmd_sz, required_ucmd_sz; 3489 int err; 3490 int underlay_qpn; 3491 3492 if (udata && udata->inlen) { 3493 min_ucmd_sz = offsetof(typeof(ucmd_hdr), reserved) + 3494 sizeof(ucmd_hdr.reserved); 3495 if (udata->inlen < min_ucmd_sz) 3496 return ERR_PTR(-EOPNOTSUPP); 3497 3498 err = ib_copy_from_udata(&ucmd_hdr, udata, min_ucmd_sz); 3499 if (err) 3500 return ERR_PTR(err); 3501 3502 /* currently supports only one counters data */ 3503 if (ucmd_hdr.ncounters_data > 1) 3504 return ERR_PTR(-EINVAL); 3505 3506 required_ucmd_sz = min_ucmd_sz + 3507 sizeof(struct mlx5_ib_flow_counters_data) * 3508 ucmd_hdr.ncounters_data; 3509 if (udata->inlen > required_ucmd_sz && 3510 !ib_is_udata_cleared(udata, required_ucmd_sz, 3511 udata->inlen - required_ucmd_sz)) 3512 return ERR_PTR(-EOPNOTSUPP); 3513 3514 ucmd = kzalloc(required_ucmd_sz, GFP_KERNEL); 3515 if (!ucmd) 3516 return ERR_PTR(-ENOMEM); 3517 3518 err = ib_copy_from_udata(ucmd, udata, required_ucmd_sz); 3519 if (err) 3520 goto free_ucmd; 3521 } 3522 3523 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) { 3524 err = -ENOMEM; 3525 goto free_ucmd; 3526 } 3527 3528 if (domain != IB_FLOW_DOMAIN_USER || 3529 flow_attr->port > dev->num_ports || 3530 (flow_attr->flags & ~(IB_FLOW_ATTR_FLAGS_DONT_TRAP | 3531 IB_FLOW_ATTR_FLAGS_EGRESS))) { 3532 err = -EINVAL; 3533 goto free_ucmd; 3534 } 3535 3536 if (is_egress && 3537 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 3538 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) { 3539 err = -EINVAL; 3540 goto free_ucmd; 3541 } 3542 3543 dst = kzalloc(sizeof(*dst), GFP_KERNEL); 3544 if (!dst) { 3545 err = -ENOMEM; 3546 goto free_ucmd; 3547 } 3548 3549 mutex_lock(&dev->flow_db->lock); 3550 3551 ft_prio = get_flow_table(dev, flow_attr, 3552 is_egress ? MLX5_IB_FT_TX : MLX5_IB_FT_RX); 3553 if (IS_ERR(ft_prio)) { 3554 err = PTR_ERR(ft_prio); 3555 goto unlock; 3556 } 3557 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 3558 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX); 3559 if (IS_ERR(ft_prio_tx)) { 3560 err = PTR_ERR(ft_prio_tx); 3561 ft_prio_tx = NULL; 3562 goto destroy_ft; 3563 } 3564 } 3565 3566 if (is_egress) { 3567 dst->type = MLX5_FLOW_DESTINATION_TYPE_PORT; 3568 } else { 3569 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR; 3570 if (mqp->flags & MLX5_IB_QP_RSS) 3571 dst->tir_num = mqp->rss_qp.tirn; 3572 else 3573 dst->tir_num = mqp->raw_packet_qp.rq.tirn; 3574 } 3575 3576 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 3577 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) { 3578 handler = create_dont_trap_rule(dev, ft_prio, 3579 flow_attr, dst); 3580 } else { 3581 underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ? 3582 mqp->underlay_qpn : 0; 3583 handler = _create_flow_rule(dev, ft_prio, flow_attr, 3584 dst, underlay_qpn, ucmd); 3585 } 3586 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 3587 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 3588 handler = create_leftovers_rule(dev, ft_prio, flow_attr, 3589 dst); 3590 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 3591 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst); 3592 } else { 3593 err = -EINVAL; 3594 goto destroy_ft; 3595 } 3596 3597 if (IS_ERR(handler)) { 3598 err = PTR_ERR(handler); 3599 handler = NULL; 3600 goto destroy_ft; 3601 } 3602 3603 mutex_unlock(&dev->flow_db->lock); 3604 kfree(dst); 3605 kfree(ucmd); 3606 3607 return &handler->ibflow; 3608 3609 destroy_ft: 3610 put_flow_table(dev, ft_prio, false); 3611 if (ft_prio_tx) 3612 put_flow_table(dev, ft_prio_tx, false); 3613 unlock: 3614 mutex_unlock(&dev->flow_db->lock); 3615 kfree(dst); 3616 free_ucmd: 3617 kfree(ucmd); 3618 return ERR_PTR(err); 3619 } 3620 3621 static struct mlx5_ib_flow_prio * 3622 _get_flow_table(struct mlx5_ib_dev *dev, 3623 struct mlx5_ib_flow_matcher *fs_matcher, 3624 bool mcast) 3625 { 3626 struct mlx5_flow_namespace *ns = NULL; 3627 struct mlx5_ib_flow_prio *prio; 3628 int max_table_size; 3629 u32 flags = 0; 3630 int priority; 3631 3632 if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS) { 3633 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 3634 log_max_ft_size)); 3635 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap)) 3636 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP; 3637 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 3638 reformat_l3_tunnel_to_l2)) 3639 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT; 3640 } else { /* Can only be MLX5_FLOW_NAMESPACE_EGRESS */ 3641 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, 3642 log_max_ft_size)); 3643 if (MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat)) 3644 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT; 3645 } 3646 3647 if (max_table_size < MLX5_FS_MAX_ENTRIES) 3648 return ERR_PTR(-ENOMEM); 3649 3650 if (mcast) 3651 priority = MLX5_IB_FLOW_MCAST_PRIO; 3652 else 3653 priority = ib_prio_to_core_prio(fs_matcher->priority, false); 3654 3655 ns = mlx5_get_flow_namespace(dev->mdev, fs_matcher->ns_type); 3656 if (!ns) 3657 return ERR_PTR(-ENOTSUPP); 3658 3659 if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS) 3660 prio = &dev->flow_db->prios[priority]; 3661 else 3662 prio = &dev->flow_db->egress_prios[priority]; 3663 3664 if (prio->flow_table) 3665 return prio; 3666 3667 return _get_prio(ns, prio, priority, MLX5_FS_MAX_ENTRIES, 3668 MLX5_FS_MAX_TYPES, flags); 3669 } 3670 3671 static struct mlx5_ib_flow_handler * 3672 _create_raw_flow_rule(struct mlx5_ib_dev *dev, 3673 struct mlx5_ib_flow_prio *ft_prio, 3674 struct mlx5_flow_destination *dst, 3675 struct mlx5_ib_flow_matcher *fs_matcher, 3676 struct mlx5_flow_act *flow_act, 3677 void *cmd_in, int inlen) 3678 { 3679 struct mlx5_ib_flow_handler *handler; 3680 struct mlx5_flow_spec *spec; 3681 struct mlx5_flow_table *ft = ft_prio->flow_table; 3682 int err = 0; 3683 3684 spec = kvzalloc(sizeof(*spec), GFP_KERNEL); 3685 handler = kzalloc(sizeof(*handler), GFP_KERNEL); 3686 if (!handler || !spec) { 3687 err = -ENOMEM; 3688 goto free; 3689 } 3690 3691 INIT_LIST_HEAD(&handler->list); 3692 3693 memcpy(spec->match_value, cmd_in, inlen); 3694 memcpy(spec->match_criteria, fs_matcher->matcher_mask.match_params, 3695 fs_matcher->mask_len); 3696 spec->match_criteria_enable = fs_matcher->match_criteria_enable; 3697 3698 handler->rule = mlx5_add_flow_rules(ft, spec, 3699 flow_act, dst, 1); 3700 3701 if (IS_ERR(handler->rule)) { 3702 err = PTR_ERR(handler->rule); 3703 goto free; 3704 } 3705 3706 ft_prio->refcount++; 3707 handler->prio = ft_prio; 3708 handler->dev = dev; 3709 ft_prio->flow_table = ft; 3710 3711 free: 3712 if (err) 3713 kfree(handler); 3714 kvfree(spec); 3715 return err ? ERR_PTR(err) : handler; 3716 } 3717 3718 static bool raw_fs_is_multicast(struct mlx5_ib_flow_matcher *fs_matcher, 3719 void *match_v) 3720 { 3721 void *match_c; 3722 void *match_v_set_lyr_2_4, *match_c_set_lyr_2_4; 3723 void *dmac, *dmac_mask; 3724 void *ipv4, *ipv4_mask; 3725 3726 if (!(fs_matcher->match_criteria_enable & 3727 (1 << MATCH_CRITERIA_ENABLE_OUTER_BIT))) 3728 return false; 3729 3730 match_c = fs_matcher->matcher_mask.match_params; 3731 match_v_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_v, 3732 outer_headers); 3733 match_c_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_c, 3734 outer_headers); 3735 3736 dmac = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4, 3737 dmac_47_16); 3738 dmac_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4, 3739 dmac_47_16); 3740 3741 if (is_multicast_ether_addr(dmac) && 3742 is_multicast_ether_addr(dmac_mask)) 3743 return true; 3744 3745 ipv4 = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4, 3746 dst_ipv4_dst_ipv6.ipv4_layout.ipv4); 3747 3748 ipv4_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4, 3749 dst_ipv4_dst_ipv6.ipv4_layout.ipv4); 3750 3751 if (ipv4_is_multicast(*(__be32 *)(ipv4)) && 3752 ipv4_is_multicast(*(__be32 *)(ipv4_mask))) 3753 return true; 3754 3755 return false; 3756 } 3757 3758 struct mlx5_ib_flow_handler * 3759 mlx5_ib_raw_fs_rule_add(struct mlx5_ib_dev *dev, 3760 struct mlx5_ib_flow_matcher *fs_matcher, 3761 struct mlx5_flow_act *flow_act, 3762 void *cmd_in, int inlen, int dest_id, 3763 int dest_type) 3764 { 3765 struct mlx5_flow_destination *dst; 3766 struct mlx5_ib_flow_prio *ft_prio; 3767 struct mlx5_ib_flow_handler *handler; 3768 bool mcast; 3769 int err; 3770 3771 if (fs_matcher->flow_type != MLX5_IB_FLOW_TYPE_NORMAL) 3772 return ERR_PTR(-EOPNOTSUPP); 3773 3774 if (fs_matcher->priority > MLX5_IB_FLOW_LAST_PRIO) 3775 return ERR_PTR(-ENOMEM); 3776 3777 dst = kzalloc(sizeof(*dst), GFP_KERNEL); 3778 if (!dst) 3779 return ERR_PTR(-ENOMEM); 3780 3781 mcast = raw_fs_is_multicast(fs_matcher, cmd_in); 3782 mutex_lock(&dev->flow_db->lock); 3783 3784 ft_prio = _get_flow_table(dev, fs_matcher, mcast); 3785 if (IS_ERR(ft_prio)) { 3786 err = PTR_ERR(ft_prio); 3787 goto unlock; 3788 } 3789 3790 if (dest_type == MLX5_FLOW_DESTINATION_TYPE_TIR) { 3791 dst->type = dest_type; 3792 dst->tir_num = dest_id; 3793 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; 3794 } else if (dest_type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE) { 3795 dst->type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM; 3796 dst->ft_num = dest_id; 3797 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; 3798 } else { 3799 dst->type = MLX5_FLOW_DESTINATION_TYPE_PORT; 3800 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW; 3801 } 3802 3803 handler = _create_raw_flow_rule(dev, ft_prio, dst, fs_matcher, flow_act, 3804 cmd_in, inlen); 3805 3806 if (IS_ERR(handler)) { 3807 err = PTR_ERR(handler); 3808 goto destroy_ft; 3809 } 3810 3811 mutex_unlock(&dev->flow_db->lock); 3812 atomic_inc(&fs_matcher->usecnt); 3813 handler->flow_matcher = fs_matcher; 3814 3815 kfree(dst); 3816 3817 return handler; 3818 3819 destroy_ft: 3820 put_flow_table(dev, ft_prio, false); 3821 unlock: 3822 mutex_unlock(&dev->flow_db->lock); 3823 kfree(dst); 3824 3825 return ERR_PTR(err); 3826 } 3827 3828 static u32 mlx5_ib_flow_action_flags_to_accel_xfrm_flags(u32 mlx5_flags) 3829 { 3830 u32 flags = 0; 3831 3832 if (mlx5_flags & MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA) 3833 flags |= MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA; 3834 3835 return flags; 3836 } 3837 3838 #define MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA 3839 static struct ib_flow_action * 3840 mlx5_ib_create_flow_action_esp(struct ib_device *device, 3841 const struct ib_flow_action_attrs_esp *attr, 3842 struct uverbs_attr_bundle *attrs) 3843 { 3844 struct mlx5_ib_dev *mdev = to_mdev(device); 3845 struct ib_uverbs_flow_action_esp_keymat_aes_gcm *aes_gcm; 3846 struct mlx5_accel_esp_xfrm_attrs accel_attrs = {}; 3847 struct mlx5_ib_flow_action *action; 3848 u64 action_flags; 3849 u64 flags; 3850 int err = 0; 3851 3852 err = uverbs_get_flags64( 3853 &action_flags, attrs, MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS, 3854 ((MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED << 1) - 1)); 3855 if (err) 3856 return ERR_PTR(err); 3857 3858 flags = mlx5_ib_flow_action_flags_to_accel_xfrm_flags(action_flags); 3859 3860 /* We current only support a subset of the standard features. Only a 3861 * keymat of type AES_GCM, with icv_len == 16, iv_algo == SEQ and esn 3862 * (with overlap). Full offload mode isn't supported. 3863 */ 3864 if (!attr->keymat || attr->replay || attr->encap || 3865 attr->spi || attr->seq || attr->tfc_pad || 3866 attr->hard_limit_pkts || 3867 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED | 3868 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT))) 3869 return ERR_PTR(-EOPNOTSUPP); 3870 3871 if (attr->keymat->protocol != 3872 IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM) 3873 return ERR_PTR(-EOPNOTSUPP); 3874 3875 aes_gcm = &attr->keymat->keymat.aes_gcm; 3876 3877 if (aes_gcm->icv_len != 16 || 3878 aes_gcm->iv_algo != IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ) 3879 return ERR_PTR(-EOPNOTSUPP); 3880 3881 action = kmalloc(sizeof(*action), GFP_KERNEL); 3882 if (!action) 3883 return ERR_PTR(-ENOMEM); 3884 3885 action->esp_aes_gcm.ib_flags = attr->flags; 3886 memcpy(&accel_attrs.keymat.aes_gcm.aes_key, &aes_gcm->aes_key, 3887 sizeof(accel_attrs.keymat.aes_gcm.aes_key)); 3888 accel_attrs.keymat.aes_gcm.key_len = aes_gcm->key_len * 8; 3889 memcpy(&accel_attrs.keymat.aes_gcm.salt, &aes_gcm->salt, 3890 sizeof(accel_attrs.keymat.aes_gcm.salt)); 3891 memcpy(&accel_attrs.keymat.aes_gcm.seq_iv, &aes_gcm->iv, 3892 sizeof(accel_attrs.keymat.aes_gcm.seq_iv)); 3893 accel_attrs.keymat.aes_gcm.icv_len = aes_gcm->icv_len * 8; 3894 accel_attrs.keymat.aes_gcm.iv_algo = MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ; 3895 accel_attrs.keymat_type = MLX5_ACCEL_ESP_KEYMAT_AES_GCM; 3896 3897 accel_attrs.esn = attr->esn; 3898 if (attr->flags & IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) 3899 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED; 3900 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW) 3901 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP; 3902 3903 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT) 3904 accel_attrs.action |= MLX5_ACCEL_ESP_ACTION_ENCRYPT; 3905 3906 action->esp_aes_gcm.ctx = 3907 mlx5_accel_esp_create_xfrm(mdev->mdev, &accel_attrs, flags); 3908 if (IS_ERR(action->esp_aes_gcm.ctx)) { 3909 err = PTR_ERR(action->esp_aes_gcm.ctx); 3910 goto err_parse; 3911 } 3912 3913 action->esp_aes_gcm.ib_flags = attr->flags; 3914 3915 return &action->ib_action; 3916 3917 err_parse: 3918 kfree(action); 3919 return ERR_PTR(err); 3920 } 3921 3922 static int 3923 mlx5_ib_modify_flow_action_esp(struct ib_flow_action *action, 3924 const struct ib_flow_action_attrs_esp *attr, 3925 struct uverbs_attr_bundle *attrs) 3926 { 3927 struct mlx5_ib_flow_action *maction = to_mflow_act(action); 3928 struct mlx5_accel_esp_xfrm_attrs accel_attrs; 3929 int err = 0; 3930 3931 if (attr->keymat || attr->replay || attr->encap || 3932 attr->spi || attr->seq || attr->tfc_pad || 3933 attr->hard_limit_pkts || 3934 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED | 3935 IB_FLOW_ACTION_ESP_FLAGS_MOD_ESP_ATTRS | 3936 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW))) 3937 return -EOPNOTSUPP; 3938 3939 /* Only the ESN value or the MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP can 3940 * be modified. 3941 */ 3942 if (!(maction->esp_aes_gcm.ib_flags & 3943 IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) && 3944 attr->flags & (IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED | 3945 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)) 3946 return -EINVAL; 3947 3948 memcpy(&accel_attrs, &maction->esp_aes_gcm.ctx->attrs, 3949 sizeof(accel_attrs)); 3950 3951 accel_attrs.esn = attr->esn; 3952 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW) 3953 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP; 3954 else 3955 accel_attrs.flags &= ~MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP; 3956 3957 err = mlx5_accel_esp_modify_xfrm(maction->esp_aes_gcm.ctx, 3958 &accel_attrs); 3959 if (err) 3960 return err; 3961 3962 maction->esp_aes_gcm.ib_flags &= 3963 ~IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW; 3964 maction->esp_aes_gcm.ib_flags |= 3965 attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW; 3966 3967 return 0; 3968 } 3969 3970 static int mlx5_ib_destroy_flow_action(struct ib_flow_action *action) 3971 { 3972 struct mlx5_ib_flow_action *maction = to_mflow_act(action); 3973 3974 switch (action->type) { 3975 case IB_FLOW_ACTION_ESP: 3976 /* 3977 * We only support aes_gcm by now, so we implicitly know this is 3978 * the underline crypto. 3979 */ 3980 mlx5_accel_esp_destroy_xfrm(maction->esp_aes_gcm.ctx); 3981 break; 3982 case IB_FLOW_ACTION_UNSPECIFIED: 3983 mlx5_ib_destroy_flow_action_raw(maction); 3984 break; 3985 default: 3986 WARN_ON(true); 3987 break; 3988 } 3989 3990 kfree(maction); 3991 return 0; 3992 } 3993 3994 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 3995 { 3996 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3997 struct mlx5_ib_qp *mqp = to_mqp(ibqp); 3998 int err; 3999 4000 if (mqp->flags & MLX5_IB_QP_UNDERLAY) { 4001 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n"); 4002 return -EOPNOTSUPP; 4003 } 4004 4005 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num); 4006 if (err) 4007 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 4008 ibqp->qp_num, gid->raw); 4009 4010 return err; 4011 } 4012 4013 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 4014 { 4015 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4016 int err; 4017 4018 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num); 4019 if (err) 4020 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 4021 ibqp->qp_num, gid->raw); 4022 4023 return err; 4024 } 4025 4026 static int init_node_data(struct mlx5_ib_dev *dev) 4027 { 4028 int err; 4029 4030 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 4031 if (err) 4032 return err; 4033 4034 dev->mdev->rev_id = dev->mdev->pdev->revision; 4035 4036 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 4037 } 4038 4039 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr, 4040 char *buf) 4041 { 4042 struct mlx5_ib_dev *dev = 4043 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 4044 4045 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages); 4046 } 4047 4048 static ssize_t show_reg_pages(struct device *device, 4049 struct device_attribute *attr, char *buf) 4050 { 4051 struct mlx5_ib_dev *dev = 4052 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 4053 4054 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 4055 } 4056 4057 static ssize_t show_hca(struct device *device, struct device_attribute *attr, 4058 char *buf) 4059 { 4060 struct mlx5_ib_dev *dev = 4061 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 4062 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device); 4063 } 4064 4065 static ssize_t show_rev(struct device *device, struct device_attribute *attr, 4066 char *buf) 4067 { 4068 struct mlx5_ib_dev *dev = 4069 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 4070 return sprintf(buf, "%x\n", dev->mdev->rev_id); 4071 } 4072 4073 static ssize_t show_board(struct device *device, struct device_attribute *attr, 4074 char *buf) 4075 { 4076 struct mlx5_ib_dev *dev = 4077 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 4078 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 4079 dev->mdev->board_id); 4080 } 4081 4082 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL); 4083 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL); 4084 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL); 4085 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL); 4086 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL); 4087 4088 static struct device_attribute *mlx5_class_attributes[] = { 4089 &dev_attr_hw_rev, 4090 &dev_attr_hca_type, 4091 &dev_attr_board_id, 4092 &dev_attr_fw_pages, 4093 &dev_attr_reg_pages, 4094 }; 4095 4096 static void pkey_change_handler(struct work_struct *work) 4097 { 4098 struct mlx5_ib_port_resources *ports = 4099 container_of(work, struct mlx5_ib_port_resources, 4100 pkey_change_work); 4101 4102 mutex_lock(&ports->devr->mutex); 4103 mlx5_ib_gsi_pkey_change(ports->gsi); 4104 mutex_unlock(&ports->devr->mutex); 4105 } 4106 4107 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 4108 { 4109 struct mlx5_ib_qp *mqp; 4110 struct mlx5_ib_cq *send_mcq, *recv_mcq; 4111 struct mlx5_core_cq *mcq; 4112 struct list_head cq_armed_list; 4113 unsigned long flags_qp; 4114 unsigned long flags_cq; 4115 unsigned long flags; 4116 4117 INIT_LIST_HEAD(&cq_armed_list); 4118 4119 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 4120 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 4121 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 4122 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 4123 if (mqp->sq.tail != mqp->sq.head) { 4124 send_mcq = to_mcq(mqp->ibqp.send_cq); 4125 spin_lock_irqsave(&send_mcq->lock, flags_cq); 4126 if (send_mcq->mcq.comp && 4127 mqp->ibqp.send_cq->comp_handler) { 4128 if (!send_mcq->mcq.reset_notify_added) { 4129 send_mcq->mcq.reset_notify_added = 1; 4130 list_add_tail(&send_mcq->mcq.reset_notify, 4131 &cq_armed_list); 4132 } 4133 } 4134 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 4135 } 4136 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 4137 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 4138 /* no handling is needed for SRQ */ 4139 if (!mqp->ibqp.srq) { 4140 if (mqp->rq.tail != mqp->rq.head) { 4141 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 4142 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 4143 if (recv_mcq->mcq.comp && 4144 mqp->ibqp.recv_cq->comp_handler) { 4145 if (!recv_mcq->mcq.reset_notify_added) { 4146 recv_mcq->mcq.reset_notify_added = 1; 4147 list_add_tail(&recv_mcq->mcq.reset_notify, 4148 &cq_armed_list); 4149 } 4150 } 4151 spin_unlock_irqrestore(&recv_mcq->lock, 4152 flags_cq); 4153 } 4154 } 4155 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 4156 } 4157 /*At that point all inflight post send were put to be executed as of we 4158 * lock/unlock above locks Now need to arm all involved CQs. 4159 */ 4160 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 4161 mcq->comp(mcq); 4162 } 4163 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 4164 } 4165 4166 static void delay_drop_handler(struct work_struct *work) 4167 { 4168 int err; 4169 struct mlx5_ib_delay_drop *delay_drop = 4170 container_of(work, struct mlx5_ib_delay_drop, 4171 delay_drop_work); 4172 4173 atomic_inc(&delay_drop->events_cnt); 4174 4175 mutex_lock(&delay_drop->lock); 4176 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev, 4177 delay_drop->timeout); 4178 if (err) { 4179 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n", 4180 delay_drop->timeout); 4181 delay_drop->activate = false; 4182 } 4183 mutex_unlock(&delay_drop->lock); 4184 } 4185 4186 static void mlx5_ib_handle_event(struct work_struct *_work) 4187 { 4188 struct mlx5_ib_event_work *work = 4189 container_of(_work, struct mlx5_ib_event_work, work); 4190 struct mlx5_ib_dev *ibdev; 4191 struct ib_event ibev; 4192 bool fatal = false; 4193 u8 port = (u8)work->param; 4194 4195 if (mlx5_core_is_mp_slave(work->dev)) { 4196 ibdev = mlx5_ib_get_ibdev_from_mpi(work->context); 4197 if (!ibdev) 4198 goto out; 4199 } else { 4200 ibdev = work->context; 4201 } 4202 4203 switch (work->event) { 4204 case MLX5_DEV_EVENT_SYS_ERROR: 4205 ibev.event = IB_EVENT_DEVICE_FATAL; 4206 mlx5_ib_handle_internal_error(ibdev); 4207 fatal = true; 4208 break; 4209 4210 case MLX5_DEV_EVENT_PORT_UP: 4211 case MLX5_DEV_EVENT_PORT_DOWN: 4212 case MLX5_DEV_EVENT_PORT_INITIALIZED: 4213 /* In RoCE, port up/down events are handled in 4214 * mlx5_netdev_event(). 4215 */ 4216 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 4217 IB_LINK_LAYER_ETHERNET) 4218 goto out; 4219 4220 ibev.event = (work->event == MLX5_DEV_EVENT_PORT_UP) ? 4221 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 4222 break; 4223 4224 case MLX5_DEV_EVENT_LID_CHANGE: 4225 ibev.event = IB_EVENT_LID_CHANGE; 4226 break; 4227 4228 case MLX5_DEV_EVENT_PKEY_CHANGE: 4229 ibev.event = IB_EVENT_PKEY_CHANGE; 4230 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 4231 break; 4232 4233 case MLX5_DEV_EVENT_GUID_CHANGE: 4234 ibev.event = IB_EVENT_GID_CHANGE; 4235 break; 4236 4237 case MLX5_DEV_EVENT_CLIENT_REREG: 4238 ibev.event = IB_EVENT_CLIENT_REREGISTER; 4239 break; 4240 case MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT: 4241 schedule_work(&ibdev->delay_drop.delay_drop_work); 4242 goto out; 4243 default: 4244 goto out; 4245 } 4246 4247 ibev.device = &ibdev->ib_dev; 4248 ibev.element.port_num = port; 4249 4250 if (!rdma_is_port_valid(&ibdev->ib_dev, port)) { 4251 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port); 4252 goto out; 4253 } 4254 4255 if (ibdev->ib_active) 4256 ib_dispatch_event(&ibev); 4257 4258 if (fatal) 4259 ibdev->ib_active = false; 4260 out: 4261 kfree(work); 4262 } 4263 4264 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context, 4265 enum mlx5_dev_event event, unsigned long param) 4266 { 4267 struct mlx5_ib_event_work *work; 4268 4269 work = kmalloc(sizeof(*work), GFP_ATOMIC); 4270 if (!work) 4271 return; 4272 4273 INIT_WORK(&work->work, mlx5_ib_handle_event); 4274 work->dev = dev; 4275 work->param = param; 4276 work->context = context; 4277 work->event = event; 4278 4279 queue_work(mlx5_ib_event_wq, &work->work); 4280 } 4281 4282 static int set_has_smi_cap(struct mlx5_ib_dev *dev) 4283 { 4284 struct mlx5_hca_vport_context vport_ctx; 4285 int err; 4286 int port; 4287 4288 for (port = 1; port <= dev->num_ports; port++) { 4289 dev->mdev->port_caps[port - 1].has_smi = false; 4290 if (MLX5_CAP_GEN(dev->mdev, port_type) == 4291 MLX5_CAP_PORT_TYPE_IB) { 4292 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) { 4293 err = mlx5_query_hca_vport_context(dev->mdev, 0, 4294 port, 0, 4295 &vport_ctx); 4296 if (err) { 4297 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n", 4298 port, err); 4299 return err; 4300 } 4301 dev->mdev->port_caps[port - 1].has_smi = 4302 vport_ctx.has_smi; 4303 } else { 4304 dev->mdev->port_caps[port - 1].has_smi = true; 4305 } 4306 } 4307 } 4308 return 0; 4309 } 4310 4311 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 4312 { 4313 int port; 4314 4315 for (port = 1; port <= dev->num_ports; port++) 4316 mlx5_query_ext_port_caps(dev, port); 4317 } 4318 4319 static int get_port_caps(struct mlx5_ib_dev *dev, u8 port) 4320 { 4321 struct ib_device_attr *dprops = NULL; 4322 struct ib_port_attr *pprops = NULL; 4323 int err = -ENOMEM; 4324 struct ib_udata uhw = {.inlen = 0, .outlen = 0}; 4325 4326 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL); 4327 if (!pprops) 4328 goto out; 4329 4330 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL); 4331 if (!dprops) 4332 goto out; 4333 4334 err = set_has_smi_cap(dev); 4335 if (err) 4336 goto out; 4337 4338 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw); 4339 if (err) { 4340 mlx5_ib_warn(dev, "query_device failed %d\n", err); 4341 goto out; 4342 } 4343 4344 memset(pprops, 0, sizeof(*pprops)); 4345 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops); 4346 if (err) { 4347 mlx5_ib_warn(dev, "query_port %d failed %d\n", 4348 port, err); 4349 goto out; 4350 } 4351 4352 dev->mdev->port_caps[port - 1].pkey_table_len = 4353 dprops->max_pkeys; 4354 dev->mdev->port_caps[port - 1].gid_table_len = 4355 pprops->gid_tbl_len; 4356 mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n", 4357 port, dprops->max_pkeys, pprops->gid_tbl_len); 4358 4359 out: 4360 kfree(pprops); 4361 kfree(dprops); 4362 4363 return err; 4364 } 4365 4366 static void destroy_umrc_res(struct mlx5_ib_dev *dev) 4367 { 4368 int err; 4369 4370 err = mlx5_mr_cache_cleanup(dev); 4371 if (err) 4372 mlx5_ib_warn(dev, "mr cache cleanup failed\n"); 4373 4374 if (dev->umrc.qp) 4375 mlx5_ib_destroy_qp(dev->umrc.qp); 4376 if (dev->umrc.cq) 4377 ib_free_cq(dev->umrc.cq); 4378 if (dev->umrc.pd) 4379 ib_dealloc_pd(dev->umrc.pd); 4380 } 4381 4382 enum { 4383 MAX_UMR_WR = 128, 4384 }; 4385 4386 static int create_umr_res(struct mlx5_ib_dev *dev) 4387 { 4388 struct ib_qp_init_attr *init_attr = NULL; 4389 struct ib_qp_attr *attr = NULL; 4390 struct ib_pd *pd; 4391 struct ib_cq *cq; 4392 struct ib_qp *qp; 4393 int ret; 4394 4395 attr = kzalloc(sizeof(*attr), GFP_KERNEL); 4396 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL); 4397 if (!attr || !init_attr) { 4398 ret = -ENOMEM; 4399 goto error_0; 4400 } 4401 4402 pd = ib_alloc_pd(&dev->ib_dev, 0); 4403 if (IS_ERR(pd)) { 4404 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n"); 4405 ret = PTR_ERR(pd); 4406 goto error_0; 4407 } 4408 4409 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ); 4410 if (IS_ERR(cq)) { 4411 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n"); 4412 ret = PTR_ERR(cq); 4413 goto error_2; 4414 } 4415 4416 init_attr->send_cq = cq; 4417 init_attr->recv_cq = cq; 4418 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR; 4419 init_attr->cap.max_send_wr = MAX_UMR_WR; 4420 init_attr->cap.max_send_sge = 1; 4421 init_attr->qp_type = MLX5_IB_QPT_REG_UMR; 4422 init_attr->port_num = 1; 4423 qp = mlx5_ib_create_qp(pd, init_attr, NULL); 4424 if (IS_ERR(qp)) { 4425 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n"); 4426 ret = PTR_ERR(qp); 4427 goto error_3; 4428 } 4429 qp->device = &dev->ib_dev; 4430 qp->real_qp = qp; 4431 qp->uobject = NULL; 4432 qp->qp_type = MLX5_IB_QPT_REG_UMR; 4433 qp->send_cq = init_attr->send_cq; 4434 qp->recv_cq = init_attr->recv_cq; 4435 4436 attr->qp_state = IB_QPS_INIT; 4437 attr->port_num = 1; 4438 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX | 4439 IB_QP_PORT, NULL); 4440 if (ret) { 4441 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n"); 4442 goto error_4; 4443 } 4444 4445 memset(attr, 0, sizeof(*attr)); 4446 attr->qp_state = IB_QPS_RTR; 4447 attr->path_mtu = IB_MTU_256; 4448 4449 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 4450 if (ret) { 4451 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n"); 4452 goto error_4; 4453 } 4454 4455 memset(attr, 0, sizeof(*attr)); 4456 attr->qp_state = IB_QPS_RTS; 4457 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 4458 if (ret) { 4459 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n"); 4460 goto error_4; 4461 } 4462 4463 dev->umrc.qp = qp; 4464 dev->umrc.cq = cq; 4465 dev->umrc.pd = pd; 4466 4467 sema_init(&dev->umrc.sem, MAX_UMR_WR); 4468 ret = mlx5_mr_cache_init(dev); 4469 if (ret) { 4470 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 4471 goto error_4; 4472 } 4473 4474 kfree(attr); 4475 kfree(init_attr); 4476 4477 return 0; 4478 4479 error_4: 4480 mlx5_ib_destroy_qp(qp); 4481 dev->umrc.qp = NULL; 4482 4483 error_3: 4484 ib_free_cq(cq); 4485 dev->umrc.cq = NULL; 4486 4487 error_2: 4488 ib_dealloc_pd(pd); 4489 dev->umrc.pd = NULL; 4490 4491 error_0: 4492 kfree(attr); 4493 kfree(init_attr); 4494 return ret; 4495 } 4496 4497 static u8 mlx5_get_umr_fence(u8 umr_fence_cap) 4498 { 4499 switch (umr_fence_cap) { 4500 case MLX5_CAP_UMR_FENCE_NONE: 4501 return MLX5_FENCE_MODE_NONE; 4502 case MLX5_CAP_UMR_FENCE_SMALL: 4503 return MLX5_FENCE_MODE_INITIATOR_SMALL; 4504 default: 4505 return MLX5_FENCE_MODE_STRONG_ORDERING; 4506 } 4507 } 4508 4509 static int create_dev_resources(struct mlx5_ib_resources *devr) 4510 { 4511 struct ib_srq_init_attr attr; 4512 struct mlx5_ib_dev *dev; 4513 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 4514 int port; 4515 int ret = 0; 4516 4517 dev = container_of(devr, struct mlx5_ib_dev, devr); 4518 4519 mutex_init(&devr->mutex); 4520 4521 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL); 4522 if (IS_ERR(devr->p0)) { 4523 ret = PTR_ERR(devr->p0); 4524 goto error0; 4525 } 4526 devr->p0->device = &dev->ib_dev; 4527 devr->p0->uobject = NULL; 4528 atomic_set(&devr->p0->usecnt, 0); 4529 4530 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL); 4531 if (IS_ERR(devr->c0)) { 4532 ret = PTR_ERR(devr->c0); 4533 goto error1; 4534 } 4535 devr->c0->device = &dev->ib_dev; 4536 devr->c0->uobject = NULL; 4537 devr->c0->comp_handler = NULL; 4538 devr->c0->event_handler = NULL; 4539 devr->c0->cq_context = NULL; 4540 atomic_set(&devr->c0->usecnt, 0); 4541 4542 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 4543 if (IS_ERR(devr->x0)) { 4544 ret = PTR_ERR(devr->x0); 4545 goto error2; 4546 } 4547 devr->x0->device = &dev->ib_dev; 4548 devr->x0->inode = NULL; 4549 atomic_set(&devr->x0->usecnt, 0); 4550 mutex_init(&devr->x0->tgt_qp_mutex); 4551 INIT_LIST_HEAD(&devr->x0->tgt_qp_list); 4552 4553 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 4554 if (IS_ERR(devr->x1)) { 4555 ret = PTR_ERR(devr->x1); 4556 goto error3; 4557 } 4558 devr->x1->device = &dev->ib_dev; 4559 devr->x1->inode = NULL; 4560 atomic_set(&devr->x1->usecnt, 0); 4561 mutex_init(&devr->x1->tgt_qp_mutex); 4562 INIT_LIST_HEAD(&devr->x1->tgt_qp_list); 4563 4564 memset(&attr, 0, sizeof(attr)); 4565 attr.attr.max_sge = 1; 4566 attr.attr.max_wr = 1; 4567 attr.srq_type = IB_SRQT_XRC; 4568 attr.ext.cq = devr->c0; 4569 attr.ext.xrc.xrcd = devr->x0; 4570 4571 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 4572 if (IS_ERR(devr->s0)) { 4573 ret = PTR_ERR(devr->s0); 4574 goto error4; 4575 } 4576 devr->s0->device = &dev->ib_dev; 4577 devr->s0->pd = devr->p0; 4578 devr->s0->uobject = NULL; 4579 devr->s0->event_handler = NULL; 4580 devr->s0->srq_context = NULL; 4581 devr->s0->srq_type = IB_SRQT_XRC; 4582 devr->s0->ext.xrc.xrcd = devr->x0; 4583 devr->s0->ext.cq = devr->c0; 4584 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt); 4585 atomic_inc(&devr->s0->ext.cq->usecnt); 4586 atomic_inc(&devr->p0->usecnt); 4587 atomic_set(&devr->s0->usecnt, 0); 4588 4589 memset(&attr, 0, sizeof(attr)); 4590 attr.attr.max_sge = 1; 4591 attr.attr.max_wr = 1; 4592 attr.srq_type = IB_SRQT_BASIC; 4593 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 4594 if (IS_ERR(devr->s1)) { 4595 ret = PTR_ERR(devr->s1); 4596 goto error5; 4597 } 4598 devr->s1->device = &dev->ib_dev; 4599 devr->s1->pd = devr->p0; 4600 devr->s1->uobject = NULL; 4601 devr->s1->event_handler = NULL; 4602 devr->s1->srq_context = NULL; 4603 devr->s1->srq_type = IB_SRQT_BASIC; 4604 devr->s1->ext.cq = devr->c0; 4605 atomic_inc(&devr->p0->usecnt); 4606 atomic_set(&devr->s1->usecnt, 0); 4607 4608 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) { 4609 INIT_WORK(&devr->ports[port].pkey_change_work, 4610 pkey_change_handler); 4611 devr->ports[port].devr = devr; 4612 } 4613 4614 return 0; 4615 4616 error5: 4617 mlx5_ib_destroy_srq(devr->s0); 4618 error4: 4619 mlx5_ib_dealloc_xrcd(devr->x1); 4620 error3: 4621 mlx5_ib_dealloc_xrcd(devr->x0); 4622 error2: 4623 mlx5_ib_destroy_cq(devr->c0); 4624 error1: 4625 mlx5_ib_dealloc_pd(devr->p0); 4626 error0: 4627 return ret; 4628 } 4629 4630 static void destroy_dev_resources(struct mlx5_ib_resources *devr) 4631 { 4632 struct mlx5_ib_dev *dev = 4633 container_of(devr, struct mlx5_ib_dev, devr); 4634 int port; 4635 4636 mlx5_ib_destroy_srq(devr->s1); 4637 mlx5_ib_destroy_srq(devr->s0); 4638 mlx5_ib_dealloc_xrcd(devr->x0); 4639 mlx5_ib_dealloc_xrcd(devr->x1); 4640 mlx5_ib_destroy_cq(devr->c0); 4641 mlx5_ib_dealloc_pd(devr->p0); 4642 4643 /* Make sure no change P_Key work items are still executing */ 4644 for (port = 0; port < dev->num_ports; ++port) 4645 cancel_work_sync(&devr->ports[port].pkey_change_work); 4646 } 4647 4648 static u32 get_core_cap_flags(struct ib_device *ibdev, 4649 struct mlx5_hca_vport_context *rep) 4650 { 4651 struct mlx5_ib_dev *dev = to_mdev(ibdev); 4652 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 4653 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 4654 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 4655 bool raw_support = !mlx5_core_mp_enabled(dev->mdev); 4656 u32 ret = 0; 4657 4658 if (rep->grh_required) 4659 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED; 4660 4661 if (ll == IB_LINK_LAYER_INFINIBAND) 4662 return ret | RDMA_CORE_PORT_IBA_IB; 4663 4664 if (raw_support) 4665 ret |= RDMA_CORE_PORT_RAW_PACKET; 4666 4667 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 4668 return ret; 4669 4670 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 4671 return ret; 4672 4673 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 4674 ret |= RDMA_CORE_PORT_IBA_ROCE; 4675 4676 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 4677 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 4678 4679 return ret; 4680 } 4681 4682 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num, 4683 struct ib_port_immutable *immutable) 4684 { 4685 struct ib_port_attr attr; 4686 struct mlx5_ib_dev *dev = to_mdev(ibdev); 4687 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num); 4688 struct mlx5_hca_vport_context rep = {0}; 4689 int err; 4690 4691 err = ib_query_port(ibdev, port_num, &attr); 4692 if (err) 4693 return err; 4694 4695 if (ll == IB_LINK_LAYER_INFINIBAND) { 4696 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0, 4697 &rep); 4698 if (err) 4699 return err; 4700 } 4701 4702 immutable->pkey_tbl_len = attr.pkey_tbl_len; 4703 immutable->gid_tbl_len = attr.gid_tbl_len; 4704 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep); 4705 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce)) 4706 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 4707 4708 return 0; 4709 } 4710 4711 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num, 4712 struct ib_port_immutable *immutable) 4713 { 4714 struct ib_port_attr attr; 4715 int err; 4716 4717 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 4718 4719 err = ib_query_port(ibdev, port_num, &attr); 4720 if (err) 4721 return err; 4722 4723 immutable->pkey_tbl_len = attr.pkey_tbl_len; 4724 immutable->gid_tbl_len = attr.gid_tbl_len; 4725 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 4726 4727 return 0; 4728 } 4729 4730 static void get_dev_fw_str(struct ib_device *ibdev, char *str) 4731 { 4732 struct mlx5_ib_dev *dev = 4733 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 4734 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d", 4735 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev), 4736 fw_rev_sub(dev->mdev)); 4737 } 4738 4739 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev) 4740 { 4741 struct mlx5_core_dev *mdev = dev->mdev; 4742 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev, 4743 MLX5_FLOW_NAMESPACE_LAG); 4744 struct mlx5_flow_table *ft; 4745 int err; 4746 4747 if (!ns || !mlx5_lag_is_active(mdev)) 4748 return 0; 4749 4750 err = mlx5_cmd_create_vport_lag(mdev); 4751 if (err) 4752 return err; 4753 4754 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0); 4755 if (IS_ERR(ft)) { 4756 err = PTR_ERR(ft); 4757 goto err_destroy_vport_lag; 4758 } 4759 4760 dev->flow_db->lag_demux_ft = ft; 4761 return 0; 4762 4763 err_destroy_vport_lag: 4764 mlx5_cmd_destroy_vport_lag(mdev); 4765 return err; 4766 } 4767 4768 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev) 4769 { 4770 struct mlx5_core_dev *mdev = dev->mdev; 4771 4772 if (dev->flow_db->lag_demux_ft) { 4773 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft); 4774 dev->flow_db->lag_demux_ft = NULL; 4775 4776 mlx5_cmd_destroy_vport_lag(mdev); 4777 } 4778 } 4779 4780 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num) 4781 { 4782 int err; 4783 4784 dev->roce[port_num].nb.notifier_call = mlx5_netdev_event; 4785 err = register_netdevice_notifier(&dev->roce[port_num].nb); 4786 if (err) { 4787 dev->roce[port_num].nb.notifier_call = NULL; 4788 return err; 4789 } 4790 4791 return 0; 4792 } 4793 4794 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num) 4795 { 4796 if (dev->roce[port_num].nb.notifier_call) { 4797 unregister_netdevice_notifier(&dev->roce[port_num].nb); 4798 dev->roce[port_num].nb.notifier_call = NULL; 4799 } 4800 } 4801 4802 static int mlx5_enable_eth(struct mlx5_ib_dev *dev) 4803 { 4804 int err; 4805 4806 if (MLX5_CAP_GEN(dev->mdev, roce)) { 4807 err = mlx5_nic_vport_enable_roce(dev->mdev); 4808 if (err) 4809 return err; 4810 } 4811 4812 err = mlx5_eth_lag_init(dev); 4813 if (err) 4814 goto err_disable_roce; 4815 4816 return 0; 4817 4818 err_disable_roce: 4819 if (MLX5_CAP_GEN(dev->mdev, roce)) 4820 mlx5_nic_vport_disable_roce(dev->mdev); 4821 4822 return err; 4823 } 4824 4825 static void mlx5_disable_eth(struct mlx5_ib_dev *dev) 4826 { 4827 mlx5_eth_lag_cleanup(dev); 4828 if (MLX5_CAP_GEN(dev->mdev, roce)) 4829 mlx5_nic_vport_disable_roce(dev->mdev); 4830 } 4831 4832 struct mlx5_ib_counter { 4833 const char *name; 4834 size_t offset; 4835 }; 4836 4837 #define INIT_Q_COUNTER(_name) \ 4838 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)} 4839 4840 static const struct mlx5_ib_counter basic_q_cnts[] = { 4841 INIT_Q_COUNTER(rx_write_requests), 4842 INIT_Q_COUNTER(rx_read_requests), 4843 INIT_Q_COUNTER(rx_atomic_requests), 4844 INIT_Q_COUNTER(out_of_buffer), 4845 }; 4846 4847 static const struct mlx5_ib_counter out_of_seq_q_cnts[] = { 4848 INIT_Q_COUNTER(out_of_sequence), 4849 }; 4850 4851 static const struct mlx5_ib_counter retrans_q_cnts[] = { 4852 INIT_Q_COUNTER(duplicate_request), 4853 INIT_Q_COUNTER(rnr_nak_retry_err), 4854 INIT_Q_COUNTER(packet_seq_err), 4855 INIT_Q_COUNTER(implied_nak_seq_err), 4856 INIT_Q_COUNTER(local_ack_timeout_err), 4857 }; 4858 4859 #define INIT_CONG_COUNTER(_name) \ 4860 { .name = #_name, .offset = \ 4861 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)} 4862 4863 static const struct mlx5_ib_counter cong_cnts[] = { 4864 INIT_CONG_COUNTER(rp_cnp_ignored), 4865 INIT_CONG_COUNTER(rp_cnp_handled), 4866 INIT_CONG_COUNTER(np_ecn_marked_roce_packets), 4867 INIT_CONG_COUNTER(np_cnp_sent), 4868 }; 4869 4870 static const struct mlx5_ib_counter extended_err_cnts[] = { 4871 INIT_Q_COUNTER(resp_local_length_error), 4872 INIT_Q_COUNTER(resp_cqe_error), 4873 INIT_Q_COUNTER(req_cqe_error), 4874 INIT_Q_COUNTER(req_remote_invalid_request), 4875 INIT_Q_COUNTER(req_remote_access_errors), 4876 INIT_Q_COUNTER(resp_remote_access_errors), 4877 INIT_Q_COUNTER(resp_cqe_flush_error), 4878 INIT_Q_COUNTER(req_cqe_flush_error), 4879 }; 4880 4881 #define INIT_EXT_PPCNT_COUNTER(_name) \ 4882 { .name = #_name, .offset = \ 4883 MLX5_BYTE_OFF(ppcnt_reg, \ 4884 counter_set.eth_extended_cntrs_grp_data_layout._name##_high)} 4885 4886 static const struct mlx5_ib_counter ext_ppcnt_cnts[] = { 4887 INIT_EXT_PPCNT_COUNTER(rx_icrc_encapsulated), 4888 }; 4889 4890 static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev) 4891 { 4892 int i; 4893 4894 for (i = 0; i < dev->num_ports; i++) { 4895 if (dev->port[i].cnts.set_id_valid) 4896 mlx5_core_dealloc_q_counter(dev->mdev, 4897 dev->port[i].cnts.set_id); 4898 kfree(dev->port[i].cnts.names); 4899 kfree(dev->port[i].cnts.offsets); 4900 } 4901 } 4902 4903 static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev, 4904 struct mlx5_ib_counters *cnts) 4905 { 4906 u32 num_counters; 4907 4908 num_counters = ARRAY_SIZE(basic_q_cnts); 4909 4910 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) 4911 num_counters += ARRAY_SIZE(out_of_seq_q_cnts); 4912 4913 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) 4914 num_counters += ARRAY_SIZE(retrans_q_cnts); 4915 4916 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) 4917 num_counters += ARRAY_SIZE(extended_err_cnts); 4918 4919 cnts->num_q_counters = num_counters; 4920 4921 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 4922 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts); 4923 num_counters += ARRAY_SIZE(cong_cnts); 4924 } 4925 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) { 4926 cnts->num_ext_ppcnt_counters = ARRAY_SIZE(ext_ppcnt_cnts); 4927 num_counters += ARRAY_SIZE(ext_ppcnt_cnts); 4928 } 4929 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL); 4930 if (!cnts->names) 4931 return -ENOMEM; 4932 4933 cnts->offsets = kcalloc(num_counters, 4934 sizeof(cnts->offsets), GFP_KERNEL); 4935 if (!cnts->offsets) 4936 goto err_names; 4937 4938 return 0; 4939 4940 err_names: 4941 kfree(cnts->names); 4942 cnts->names = NULL; 4943 return -ENOMEM; 4944 } 4945 4946 static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev, 4947 const char **names, 4948 size_t *offsets) 4949 { 4950 int i; 4951 int j = 0; 4952 4953 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) { 4954 names[j] = basic_q_cnts[i].name; 4955 offsets[j] = basic_q_cnts[i].offset; 4956 } 4957 4958 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) { 4959 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) { 4960 names[j] = out_of_seq_q_cnts[i].name; 4961 offsets[j] = out_of_seq_q_cnts[i].offset; 4962 } 4963 } 4964 4965 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) { 4966 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) { 4967 names[j] = retrans_q_cnts[i].name; 4968 offsets[j] = retrans_q_cnts[i].offset; 4969 } 4970 } 4971 4972 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) { 4973 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) { 4974 names[j] = extended_err_cnts[i].name; 4975 offsets[j] = extended_err_cnts[i].offset; 4976 } 4977 } 4978 4979 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 4980 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) { 4981 names[j] = cong_cnts[i].name; 4982 offsets[j] = cong_cnts[i].offset; 4983 } 4984 } 4985 4986 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) { 4987 for (i = 0; i < ARRAY_SIZE(ext_ppcnt_cnts); i++, j++) { 4988 names[j] = ext_ppcnt_cnts[i].name; 4989 offsets[j] = ext_ppcnt_cnts[i].offset; 4990 } 4991 } 4992 } 4993 4994 static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev) 4995 { 4996 int err = 0; 4997 int i; 4998 4999 for (i = 0; i < dev->num_ports; i++) { 5000 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts); 5001 if (err) 5002 goto err_alloc; 5003 5004 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names, 5005 dev->port[i].cnts.offsets); 5006 5007 err = mlx5_core_alloc_q_counter(dev->mdev, 5008 &dev->port[i].cnts.set_id); 5009 if (err) { 5010 mlx5_ib_warn(dev, 5011 "couldn't allocate queue counter for port %d, err %d\n", 5012 i + 1, err); 5013 goto err_alloc; 5014 } 5015 dev->port[i].cnts.set_id_valid = true; 5016 } 5017 5018 return 0; 5019 5020 err_alloc: 5021 mlx5_ib_dealloc_counters(dev); 5022 return err; 5023 } 5024 5025 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev, 5026 u8 port_num) 5027 { 5028 struct mlx5_ib_dev *dev = to_mdev(ibdev); 5029 struct mlx5_ib_port *port = &dev->port[port_num - 1]; 5030 5031 /* We support only per port stats */ 5032 if (port_num == 0) 5033 return NULL; 5034 5035 return rdma_alloc_hw_stats_struct(port->cnts.names, 5036 port->cnts.num_q_counters + 5037 port->cnts.num_cong_counters + 5038 port->cnts.num_ext_ppcnt_counters, 5039 RDMA_HW_STATS_DEFAULT_LIFESPAN); 5040 } 5041 5042 static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev, 5043 struct mlx5_ib_port *port, 5044 struct rdma_hw_stats *stats) 5045 { 5046 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out); 5047 void *out; 5048 __be32 val; 5049 int ret, i; 5050 5051 out = kvzalloc(outlen, GFP_KERNEL); 5052 if (!out) 5053 return -ENOMEM; 5054 5055 ret = mlx5_core_query_q_counter(mdev, 5056 port->cnts.set_id, 0, 5057 out, outlen); 5058 if (ret) 5059 goto free; 5060 5061 for (i = 0; i < port->cnts.num_q_counters; i++) { 5062 val = *(__be32 *)(out + port->cnts.offsets[i]); 5063 stats->value[i] = (u64)be32_to_cpu(val); 5064 } 5065 5066 free: 5067 kvfree(out); 5068 return ret; 5069 } 5070 5071 static int mlx5_ib_query_ext_ppcnt_counters(struct mlx5_ib_dev *dev, 5072 struct mlx5_ib_port *port, 5073 struct rdma_hw_stats *stats) 5074 { 5075 int offset = port->cnts.num_q_counters + port->cnts.num_cong_counters; 5076 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg); 5077 int ret, i; 5078 void *out; 5079 5080 out = kvzalloc(sz, GFP_KERNEL); 5081 if (!out) 5082 return -ENOMEM; 5083 5084 ret = mlx5_cmd_query_ext_ppcnt_counters(dev->mdev, out); 5085 if (ret) 5086 goto free; 5087 5088 for (i = 0; i < port->cnts.num_ext_ppcnt_counters; i++) { 5089 stats->value[i + offset] = 5090 be64_to_cpup((__be64 *)(out + 5091 port->cnts.offsets[i + offset])); 5092 } 5093 5094 free: 5095 kvfree(out); 5096 return ret; 5097 } 5098 5099 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev, 5100 struct rdma_hw_stats *stats, 5101 u8 port_num, int index) 5102 { 5103 struct mlx5_ib_dev *dev = to_mdev(ibdev); 5104 struct mlx5_ib_port *port = &dev->port[port_num - 1]; 5105 struct mlx5_core_dev *mdev; 5106 int ret, num_counters; 5107 u8 mdev_port_num; 5108 5109 if (!stats) 5110 return -EINVAL; 5111 5112 num_counters = port->cnts.num_q_counters + 5113 port->cnts.num_cong_counters + 5114 port->cnts.num_ext_ppcnt_counters; 5115 5116 /* q_counters are per IB device, query the master mdev */ 5117 ret = mlx5_ib_query_q_counters(dev->mdev, port, stats); 5118 if (ret) 5119 return ret; 5120 5121 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) { 5122 ret = mlx5_ib_query_ext_ppcnt_counters(dev, port, stats); 5123 if (ret) 5124 return ret; 5125 } 5126 5127 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 5128 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, 5129 &mdev_port_num); 5130 if (!mdev) { 5131 /* If port is not affiliated yet, its in down state 5132 * which doesn't have any counters yet, so it would be 5133 * zero. So no need to read from the HCA. 5134 */ 5135 goto done; 5136 } 5137 ret = mlx5_lag_query_cong_counters(dev->mdev, 5138 stats->value + 5139 port->cnts.num_q_counters, 5140 port->cnts.num_cong_counters, 5141 port->cnts.offsets + 5142 port->cnts.num_q_counters); 5143 5144 mlx5_ib_put_native_port_mdev(dev, port_num); 5145 if (ret) 5146 return ret; 5147 } 5148 5149 done: 5150 return num_counters; 5151 } 5152 5153 static struct net_device* 5154 mlx5_ib_alloc_rdma_netdev(struct ib_device *hca, 5155 u8 port_num, 5156 enum rdma_netdev_t type, 5157 const char *name, 5158 unsigned char name_assign_type, 5159 void (*setup)(struct net_device *)) 5160 { 5161 struct net_device *netdev; 5162 5163 if (type != RDMA_NETDEV_IPOIB) 5164 return ERR_PTR(-EOPNOTSUPP); 5165 5166 netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca, 5167 name, setup); 5168 return netdev; 5169 } 5170 5171 static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev) 5172 { 5173 if (!dev->delay_drop.dbg) 5174 return; 5175 debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs); 5176 kfree(dev->delay_drop.dbg); 5177 dev->delay_drop.dbg = NULL; 5178 } 5179 5180 static void cancel_delay_drop(struct mlx5_ib_dev *dev) 5181 { 5182 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 5183 return; 5184 5185 cancel_work_sync(&dev->delay_drop.delay_drop_work); 5186 delay_drop_debugfs_cleanup(dev); 5187 } 5188 5189 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf, 5190 size_t count, loff_t *pos) 5191 { 5192 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 5193 char lbuf[20]; 5194 int len; 5195 5196 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout); 5197 return simple_read_from_buffer(buf, count, pos, lbuf, len); 5198 } 5199 5200 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf, 5201 size_t count, loff_t *pos) 5202 { 5203 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 5204 u32 timeout; 5205 u32 var; 5206 5207 if (kstrtouint_from_user(buf, count, 0, &var)) 5208 return -EFAULT; 5209 5210 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 5211 1000); 5212 if (timeout != var) 5213 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n", 5214 timeout); 5215 5216 delay_drop->timeout = timeout; 5217 5218 return count; 5219 } 5220 5221 static const struct file_operations fops_delay_drop_timeout = { 5222 .owner = THIS_MODULE, 5223 .open = simple_open, 5224 .write = delay_drop_timeout_write, 5225 .read = delay_drop_timeout_read, 5226 }; 5227 5228 static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev) 5229 { 5230 struct mlx5_ib_dbg_delay_drop *dbg; 5231 5232 if (!mlx5_debugfs_root) 5233 return 0; 5234 5235 dbg = kzalloc(sizeof(*dbg), GFP_KERNEL); 5236 if (!dbg) 5237 return -ENOMEM; 5238 5239 dev->delay_drop.dbg = dbg; 5240 5241 dbg->dir_debugfs = 5242 debugfs_create_dir("delay_drop", 5243 dev->mdev->priv.dbg_root); 5244 if (!dbg->dir_debugfs) 5245 goto out_debugfs; 5246 5247 dbg->events_cnt_debugfs = 5248 debugfs_create_atomic_t("num_timeout_events", 0400, 5249 dbg->dir_debugfs, 5250 &dev->delay_drop.events_cnt); 5251 if (!dbg->events_cnt_debugfs) 5252 goto out_debugfs; 5253 5254 dbg->rqs_cnt_debugfs = 5255 debugfs_create_atomic_t("num_rqs", 0400, 5256 dbg->dir_debugfs, 5257 &dev->delay_drop.rqs_cnt); 5258 if (!dbg->rqs_cnt_debugfs) 5259 goto out_debugfs; 5260 5261 dbg->timeout_debugfs = 5262 debugfs_create_file("timeout", 0600, 5263 dbg->dir_debugfs, 5264 &dev->delay_drop, 5265 &fops_delay_drop_timeout); 5266 if (!dbg->timeout_debugfs) 5267 goto out_debugfs; 5268 5269 return 0; 5270 5271 out_debugfs: 5272 delay_drop_debugfs_cleanup(dev); 5273 return -ENOMEM; 5274 } 5275 5276 static void init_delay_drop(struct mlx5_ib_dev *dev) 5277 { 5278 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 5279 return; 5280 5281 mutex_init(&dev->delay_drop.lock); 5282 dev->delay_drop.dev = dev; 5283 dev->delay_drop.activate = false; 5284 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000; 5285 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler); 5286 atomic_set(&dev->delay_drop.rqs_cnt, 0); 5287 atomic_set(&dev->delay_drop.events_cnt, 0); 5288 5289 if (delay_drop_debugfs_init(dev)) 5290 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n"); 5291 } 5292 5293 static const struct cpumask * 5294 mlx5_ib_get_vector_affinity(struct ib_device *ibdev, int comp_vector) 5295 { 5296 struct mlx5_ib_dev *dev = to_mdev(ibdev); 5297 5298 return mlx5_get_vector_affinity_hint(dev->mdev, comp_vector); 5299 } 5300 5301 /* The mlx5_ib_multiport_mutex should be held when calling this function */ 5302 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev, 5303 struct mlx5_ib_multiport_info *mpi) 5304 { 5305 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 5306 struct mlx5_ib_port *port = &ibdev->port[port_num]; 5307 int comps; 5308 int err; 5309 int i; 5310 5311 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num); 5312 5313 spin_lock(&port->mp.mpi_lock); 5314 if (!mpi->ibdev) { 5315 spin_unlock(&port->mp.mpi_lock); 5316 return; 5317 } 5318 mpi->ibdev = NULL; 5319 5320 spin_unlock(&port->mp.mpi_lock); 5321 mlx5_remove_netdev_notifier(ibdev, port_num); 5322 spin_lock(&port->mp.mpi_lock); 5323 5324 comps = mpi->mdev_refcnt; 5325 if (comps) { 5326 mpi->unaffiliate = true; 5327 init_completion(&mpi->unref_comp); 5328 spin_unlock(&port->mp.mpi_lock); 5329 5330 for (i = 0; i < comps; i++) 5331 wait_for_completion(&mpi->unref_comp); 5332 5333 spin_lock(&port->mp.mpi_lock); 5334 mpi->unaffiliate = false; 5335 } 5336 5337 port->mp.mpi = NULL; 5338 5339 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 5340 5341 spin_unlock(&port->mp.mpi_lock); 5342 5343 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev); 5344 5345 mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1); 5346 /* Log an error, still needed to cleanup the pointers and add 5347 * it back to the list. 5348 */ 5349 if (err) 5350 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n", 5351 port_num + 1); 5352 5353 ibdev->roce[port_num].last_port_state = IB_PORT_DOWN; 5354 } 5355 5356 /* The mlx5_ib_multiport_mutex should be held when calling this function */ 5357 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev, 5358 struct mlx5_ib_multiport_info *mpi) 5359 { 5360 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 5361 int err; 5362 5363 spin_lock(&ibdev->port[port_num].mp.mpi_lock); 5364 if (ibdev->port[port_num].mp.mpi) { 5365 mlx5_ib_dbg(ibdev, "port %d already affiliated.\n", 5366 port_num + 1); 5367 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 5368 return false; 5369 } 5370 5371 ibdev->port[port_num].mp.mpi = mpi; 5372 mpi->ibdev = ibdev; 5373 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 5374 5375 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev); 5376 if (err) 5377 goto unbind; 5378 5379 err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev)); 5380 if (err) 5381 goto unbind; 5382 5383 err = mlx5_add_netdev_notifier(ibdev, port_num); 5384 if (err) { 5385 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n", 5386 port_num + 1); 5387 goto unbind; 5388 } 5389 5390 err = mlx5_ib_init_cong_debugfs(ibdev, port_num); 5391 if (err) 5392 goto unbind; 5393 5394 return true; 5395 5396 unbind: 5397 mlx5_ib_unbind_slave_port(ibdev, mpi); 5398 return false; 5399 } 5400 5401 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev) 5402 { 5403 int port_num = mlx5_core_native_port_num(dev->mdev) - 1; 5404 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 5405 port_num + 1); 5406 struct mlx5_ib_multiport_info *mpi; 5407 int err; 5408 int i; 5409 5410 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 5411 return 0; 5412 5413 err = mlx5_query_nic_vport_system_image_guid(dev->mdev, 5414 &dev->sys_image_guid); 5415 if (err) 5416 return err; 5417 5418 err = mlx5_nic_vport_enable_roce(dev->mdev); 5419 if (err) 5420 return err; 5421 5422 mutex_lock(&mlx5_ib_multiport_mutex); 5423 for (i = 0; i < dev->num_ports; i++) { 5424 bool bound = false; 5425 5426 /* build a stub multiport info struct for the native port. */ 5427 if (i == port_num) { 5428 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 5429 if (!mpi) { 5430 mutex_unlock(&mlx5_ib_multiport_mutex); 5431 mlx5_nic_vport_disable_roce(dev->mdev); 5432 return -ENOMEM; 5433 } 5434 5435 mpi->is_master = true; 5436 mpi->mdev = dev->mdev; 5437 mpi->sys_image_guid = dev->sys_image_guid; 5438 dev->port[i].mp.mpi = mpi; 5439 mpi->ibdev = dev; 5440 mpi = NULL; 5441 continue; 5442 } 5443 5444 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list, 5445 list) { 5446 if (dev->sys_image_guid == mpi->sys_image_guid && 5447 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) { 5448 bound = mlx5_ib_bind_slave_port(dev, mpi); 5449 } 5450 5451 if (bound) { 5452 dev_dbg(&mpi->mdev->pdev->dev, "removing port from unaffiliated list.\n"); 5453 mlx5_ib_dbg(dev, "port %d bound\n", i + 1); 5454 list_del(&mpi->list); 5455 break; 5456 } 5457 } 5458 if (!bound) { 5459 get_port_caps(dev, i + 1); 5460 mlx5_ib_dbg(dev, "no free port found for port %d\n", 5461 i + 1); 5462 } 5463 } 5464 5465 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list); 5466 mutex_unlock(&mlx5_ib_multiport_mutex); 5467 return err; 5468 } 5469 5470 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev) 5471 { 5472 int port_num = mlx5_core_native_port_num(dev->mdev) - 1; 5473 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 5474 port_num + 1); 5475 int i; 5476 5477 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 5478 return; 5479 5480 mutex_lock(&mlx5_ib_multiport_mutex); 5481 for (i = 0; i < dev->num_ports; i++) { 5482 if (dev->port[i].mp.mpi) { 5483 /* Destroy the native port stub */ 5484 if (i == port_num) { 5485 kfree(dev->port[i].mp.mpi); 5486 dev->port[i].mp.mpi = NULL; 5487 } else { 5488 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1); 5489 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi); 5490 } 5491 } 5492 } 5493 5494 mlx5_ib_dbg(dev, "removing from devlist\n"); 5495 list_del(&dev->ib_dev_list); 5496 mutex_unlock(&mlx5_ib_multiport_mutex); 5497 5498 mlx5_nic_vport_disable_roce(dev->mdev); 5499 } 5500 5501 ADD_UVERBS_ATTRIBUTES_SIMPLE( 5502 mlx5_ib_dm, 5503 UVERBS_OBJECT_DM, 5504 UVERBS_METHOD_DM_ALLOC, 5505 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET, 5506 UVERBS_ATTR_TYPE(u64), 5507 UA_MANDATORY), 5508 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX, 5509 UVERBS_ATTR_TYPE(u16), 5510 UA_MANDATORY)); 5511 5512 ADD_UVERBS_ATTRIBUTES_SIMPLE( 5513 mlx5_ib_flow_action, 5514 UVERBS_OBJECT_FLOW_ACTION, 5515 UVERBS_METHOD_FLOW_ACTION_ESP_CREATE, 5516 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS, 5517 enum mlx5_ib_uapi_flow_action_flags)); 5518 5519 static int populate_specs_root(struct mlx5_ib_dev *dev) 5520 { 5521 const struct uverbs_object_tree_def **trees = dev->driver_trees; 5522 size_t num_trees = 0; 5523 5524 if (mlx5_accel_ipsec_device_caps(dev->mdev) & 5525 MLX5_ACCEL_IPSEC_CAP_DEVICE) 5526 trees[num_trees++] = &mlx5_ib_flow_action; 5527 5528 if (MLX5_CAP_DEV_MEM(dev->mdev, memic)) 5529 trees[num_trees++] = &mlx5_ib_dm; 5530 5531 if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 5532 MLX5_GENERAL_OBJ_TYPES_CAP_UCTX) 5533 trees[num_trees++] = mlx5_ib_get_devx_tree(); 5534 5535 num_trees += mlx5_ib_get_flow_trees(trees + num_trees); 5536 5537 WARN_ON(num_trees >= ARRAY_SIZE(dev->driver_trees)); 5538 trees[num_trees] = NULL; 5539 dev->ib_dev.driver_specs = trees; 5540 5541 return 0; 5542 } 5543 5544 static int mlx5_ib_read_counters(struct ib_counters *counters, 5545 struct ib_counters_read_attr *read_attr, 5546 struct uverbs_attr_bundle *attrs) 5547 { 5548 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters); 5549 struct mlx5_read_counters_attr mread_attr = {}; 5550 struct mlx5_ib_flow_counters_desc *desc; 5551 int ret, i; 5552 5553 mutex_lock(&mcounters->mcntrs_mutex); 5554 if (mcounters->cntrs_max_index > read_attr->ncounters) { 5555 ret = -EINVAL; 5556 goto err_bound; 5557 } 5558 5559 mread_attr.out = kcalloc(mcounters->counters_num, sizeof(u64), 5560 GFP_KERNEL); 5561 if (!mread_attr.out) { 5562 ret = -ENOMEM; 5563 goto err_bound; 5564 } 5565 5566 mread_attr.hw_cntrs_hndl = mcounters->hw_cntrs_hndl; 5567 mread_attr.flags = read_attr->flags; 5568 ret = mcounters->read_counters(counters->device, &mread_attr); 5569 if (ret) 5570 goto err_read; 5571 5572 /* do the pass over the counters data array to assign according to the 5573 * descriptions and indexing pairs 5574 */ 5575 desc = mcounters->counters_data; 5576 for (i = 0; i < mcounters->ncounters; i++) 5577 read_attr->counters_buff[desc[i].index] += mread_attr.out[desc[i].description]; 5578 5579 err_read: 5580 kfree(mread_attr.out); 5581 err_bound: 5582 mutex_unlock(&mcounters->mcntrs_mutex); 5583 return ret; 5584 } 5585 5586 static int mlx5_ib_destroy_counters(struct ib_counters *counters) 5587 { 5588 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters); 5589 5590 counters_clear_description(counters); 5591 if (mcounters->hw_cntrs_hndl) 5592 mlx5_fc_destroy(to_mdev(counters->device)->mdev, 5593 mcounters->hw_cntrs_hndl); 5594 5595 kfree(mcounters); 5596 5597 return 0; 5598 } 5599 5600 static struct ib_counters *mlx5_ib_create_counters(struct ib_device *device, 5601 struct uverbs_attr_bundle *attrs) 5602 { 5603 struct mlx5_ib_mcounters *mcounters; 5604 5605 mcounters = kzalloc(sizeof(*mcounters), GFP_KERNEL); 5606 if (!mcounters) 5607 return ERR_PTR(-ENOMEM); 5608 5609 mutex_init(&mcounters->mcntrs_mutex); 5610 5611 return &mcounters->ibcntrs; 5612 } 5613 5614 void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev) 5615 { 5616 mlx5_ib_cleanup_multiport_master(dev); 5617 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 5618 cleanup_srcu_struct(&dev->mr_srcu); 5619 #endif 5620 kfree(dev->port); 5621 } 5622 5623 int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev) 5624 { 5625 struct mlx5_core_dev *mdev = dev->mdev; 5626 const char *name; 5627 int err; 5628 int i; 5629 5630 dev->port = kcalloc(dev->num_ports, sizeof(*dev->port), 5631 GFP_KERNEL); 5632 if (!dev->port) 5633 return -ENOMEM; 5634 5635 for (i = 0; i < dev->num_ports; i++) { 5636 spin_lock_init(&dev->port[i].mp.mpi_lock); 5637 rwlock_init(&dev->roce[i].netdev_lock); 5638 } 5639 5640 err = mlx5_ib_init_multiport_master(dev); 5641 if (err) 5642 goto err_free_port; 5643 5644 if (!mlx5_core_mp_enabled(mdev)) { 5645 for (i = 1; i <= dev->num_ports; i++) { 5646 err = get_port_caps(dev, i); 5647 if (err) 5648 break; 5649 } 5650 } else { 5651 err = get_port_caps(dev, mlx5_core_native_port_num(mdev)); 5652 } 5653 if (err) 5654 goto err_mp; 5655 5656 if (mlx5_use_mad_ifc(dev)) 5657 get_ext_port_caps(dev); 5658 5659 if (!mlx5_lag_is_active(mdev)) 5660 name = "mlx5_%d"; 5661 else 5662 name = "mlx5_bond_%d"; 5663 5664 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX); 5665 dev->ib_dev.owner = THIS_MODULE; 5666 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 5667 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 5668 dev->ib_dev.phys_port_cnt = dev->num_ports; 5669 dev->ib_dev.num_comp_vectors = 5670 dev->mdev->priv.eq_table.num_comp_vectors; 5671 dev->ib_dev.dev.parent = &mdev->pdev->dev; 5672 5673 mutex_init(&dev->cap_mask_mutex); 5674 INIT_LIST_HEAD(&dev->qp_list); 5675 spin_lock_init(&dev->reset_flow_resource_lock); 5676 5677 spin_lock_init(&dev->memic.memic_lock); 5678 dev->memic.dev = mdev; 5679 5680 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 5681 err = init_srcu_struct(&dev->mr_srcu); 5682 if (err) 5683 goto err_free_port; 5684 #endif 5685 5686 return 0; 5687 err_mp: 5688 mlx5_ib_cleanup_multiport_master(dev); 5689 5690 err_free_port: 5691 kfree(dev->port); 5692 5693 return -ENOMEM; 5694 } 5695 5696 static int mlx5_ib_stage_flow_db_init(struct mlx5_ib_dev *dev) 5697 { 5698 dev->flow_db = kzalloc(sizeof(*dev->flow_db), GFP_KERNEL); 5699 5700 if (!dev->flow_db) 5701 return -ENOMEM; 5702 5703 mutex_init(&dev->flow_db->lock); 5704 5705 return 0; 5706 } 5707 5708 int mlx5_ib_stage_rep_flow_db_init(struct mlx5_ib_dev *dev) 5709 { 5710 struct mlx5_ib_dev *nic_dev; 5711 5712 nic_dev = mlx5_ib_get_uplink_ibdev(dev->mdev->priv.eswitch); 5713 5714 if (!nic_dev) 5715 return -EINVAL; 5716 5717 dev->flow_db = nic_dev->flow_db; 5718 5719 return 0; 5720 } 5721 5722 static void mlx5_ib_stage_flow_db_cleanup(struct mlx5_ib_dev *dev) 5723 { 5724 kfree(dev->flow_db); 5725 } 5726 5727 int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev) 5728 { 5729 struct mlx5_core_dev *mdev = dev->mdev; 5730 int err; 5731 5732 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION; 5733 dev->ib_dev.uverbs_cmd_mask = 5734 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | 5735 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | 5736 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | 5737 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | 5738 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | 5739 (1ull << IB_USER_VERBS_CMD_CREATE_AH) | 5740 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) | 5741 (1ull << IB_USER_VERBS_CMD_REG_MR) | 5742 (1ull << IB_USER_VERBS_CMD_REREG_MR) | 5743 (1ull << IB_USER_VERBS_CMD_DEREG_MR) | 5744 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 5745 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | 5746 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) | 5747 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | 5748 (1ull << IB_USER_VERBS_CMD_CREATE_QP) | 5749 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | 5750 (1ull << IB_USER_VERBS_CMD_QUERY_QP) | 5751 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | 5752 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) | 5753 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) | 5754 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | 5755 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | 5756 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | 5757 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | 5758 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) | 5759 (1ull << IB_USER_VERBS_CMD_OPEN_QP); 5760 dev->ib_dev.uverbs_ex_cmd_mask = 5761 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) | 5762 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) | 5763 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) | 5764 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP) | 5765 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ); 5766 5767 dev->ib_dev.query_device = mlx5_ib_query_device; 5768 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer; 5769 dev->ib_dev.query_gid = mlx5_ib_query_gid; 5770 dev->ib_dev.add_gid = mlx5_ib_add_gid; 5771 dev->ib_dev.del_gid = mlx5_ib_del_gid; 5772 dev->ib_dev.query_pkey = mlx5_ib_query_pkey; 5773 dev->ib_dev.modify_device = mlx5_ib_modify_device; 5774 dev->ib_dev.modify_port = mlx5_ib_modify_port; 5775 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext; 5776 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext; 5777 dev->ib_dev.mmap = mlx5_ib_mmap; 5778 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd; 5779 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd; 5780 dev->ib_dev.create_ah = mlx5_ib_create_ah; 5781 dev->ib_dev.query_ah = mlx5_ib_query_ah; 5782 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah; 5783 dev->ib_dev.create_srq = mlx5_ib_create_srq; 5784 dev->ib_dev.modify_srq = mlx5_ib_modify_srq; 5785 dev->ib_dev.query_srq = mlx5_ib_query_srq; 5786 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq; 5787 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv; 5788 dev->ib_dev.create_qp = mlx5_ib_create_qp; 5789 dev->ib_dev.modify_qp = mlx5_ib_modify_qp; 5790 dev->ib_dev.query_qp = mlx5_ib_query_qp; 5791 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp; 5792 dev->ib_dev.drain_sq = mlx5_ib_drain_sq; 5793 dev->ib_dev.drain_rq = mlx5_ib_drain_rq; 5794 dev->ib_dev.post_send = mlx5_ib_post_send; 5795 dev->ib_dev.post_recv = mlx5_ib_post_recv; 5796 dev->ib_dev.create_cq = mlx5_ib_create_cq; 5797 dev->ib_dev.modify_cq = mlx5_ib_modify_cq; 5798 dev->ib_dev.resize_cq = mlx5_ib_resize_cq; 5799 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq; 5800 dev->ib_dev.poll_cq = mlx5_ib_poll_cq; 5801 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq; 5802 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr; 5803 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr; 5804 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr; 5805 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr; 5806 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach; 5807 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach; 5808 dev->ib_dev.process_mad = mlx5_ib_process_mad; 5809 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr; 5810 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg; 5811 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status; 5812 dev->ib_dev.get_dev_fw_str = get_dev_fw_str; 5813 dev->ib_dev.get_vector_affinity = mlx5_ib_get_vector_affinity; 5814 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads)) 5815 dev->ib_dev.alloc_rdma_netdev = mlx5_ib_alloc_rdma_netdev; 5816 5817 if (mlx5_core_is_pf(mdev)) { 5818 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config; 5819 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state; 5820 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats; 5821 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid; 5822 } 5823 5824 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext; 5825 5826 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence)); 5827 5828 if (MLX5_CAP_GEN(mdev, imaicl)) { 5829 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw; 5830 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw; 5831 dev->ib_dev.uverbs_cmd_mask |= 5832 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) | 5833 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW); 5834 } 5835 5836 if (MLX5_CAP_GEN(mdev, xrc)) { 5837 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd; 5838 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd; 5839 dev->ib_dev.uverbs_cmd_mask |= 5840 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) | 5841 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD); 5842 } 5843 5844 if (MLX5_CAP_DEV_MEM(mdev, memic)) { 5845 dev->ib_dev.alloc_dm = mlx5_ib_alloc_dm; 5846 dev->ib_dev.dealloc_dm = mlx5_ib_dealloc_dm; 5847 dev->ib_dev.reg_dm_mr = mlx5_ib_reg_dm_mr; 5848 } 5849 5850 dev->ib_dev.create_flow = mlx5_ib_create_flow; 5851 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow; 5852 dev->ib_dev.uverbs_ex_cmd_mask |= 5853 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) | 5854 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW); 5855 dev->ib_dev.create_flow_action_esp = mlx5_ib_create_flow_action_esp; 5856 dev->ib_dev.destroy_flow_action = mlx5_ib_destroy_flow_action; 5857 dev->ib_dev.modify_flow_action_esp = mlx5_ib_modify_flow_action_esp; 5858 dev->ib_dev.driver_id = RDMA_DRIVER_MLX5; 5859 dev->ib_dev.create_counters = mlx5_ib_create_counters; 5860 dev->ib_dev.destroy_counters = mlx5_ib_destroy_counters; 5861 dev->ib_dev.read_counters = mlx5_ib_read_counters; 5862 5863 err = init_node_data(dev); 5864 if (err) 5865 return err; 5866 5867 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && 5868 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) || 5869 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 5870 mutex_init(&dev->lb_mutex); 5871 5872 return 0; 5873 } 5874 5875 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev) 5876 { 5877 dev->ib_dev.get_port_immutable = mlx5_port_immutable; 5878 dev->ib_dev.query_port = mlx5_ib_query_port; 5879 5880 return 0; 5881 } 5882 5883 int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev) 5884 { 5885 dev->ib_dev.get_port_immutable = mlx5_port_rep_immutable; 5886 dev->ib_dev.query_port = mlx5_ib_rep_query_port; 5887 5888 return 0; 5889 } 5890 5891 static int mlx5_ib_stage_common_roce_init(struct mlx5_ib_dev *dev) 5892 { 5893 u8 port_num; 5894 int i; 5895 5896 for (i = 0; i < dev->num_ports; i++) { 5897 dev->roce[i].dev = dev; 5898 dev->roce[i].native_port_num = i + 1; 5899 dev->roce[i].last_port_state = IB_PORT_DOWN; 5900 } 5901 5902 dev->ib_dev.get_netdev = mlx5_ib_get_netdev; 5903 dev->ib_dev.create_wq = mlx5_ib_create_wq; 5904 dev->ib_dev.modify_wq = mlx5_ib_modify_wq; 5905 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq; 5906 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table; 5907 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table; 5908 5909 dev->ib_dev.uverbs_ex_cmd_mask |= 5910 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) | 5911 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) | 5912 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) | 5913 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) | 5914 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL); 5915 5916 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 5917 5918 return mlx5_add_netdev_notifier(dev, port_num); 5919 } 5920 5921 static void mlx5_ib_stage_common_roce_cleanup(struct mlx5_ib_dev *dev) 5922 { 5923 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 5924 5925 mlx5_remove_netdev_notifier(dev, port_num); 5926 } 5927 5928 int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev) 5929 { 5930 struct mlx5_core_dev *mdev = dev->mdev; 5931 enum rdma_link_layer ll; 5932 int port_type_cap; 5933 int err = 0; 5934 5935 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 5936 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 5937 5938 if (ll == IB_LINK_LAYER_ETHERNET) 5939 err = mlx5_ib_stage_common_roce_init(dev); 5940 5941 return err; 5942 } 5943 5944 void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev) 5945 { 5946 mlx5_ib_stage_common_roce_cleanup(dev); 5947 } 5948 5949 static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev) 5950 { 5951 struct mlx5_core_dev *mdev = dev->mdev; 5952 enum rdma_link_layer ll; 5953 int port_type_cap; 5954 int err; 5955 5956 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 5957 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 5958 5959 if (ll == IB_LINK_LAYER_ETHERNET) { 5960 err = mlx5_ib_stage_common_roce_init(dev); 5961 if (err) 5962 return err; 5963 5964 err = mlx5_enable_eth(dev); 5965 if (err) 5966 goto cleanup; 5967 } 5968 5969 return 0; 5970 cleanup: 5971 mlx5_ib_stage_common_roce_cleanup(dev); 5972 5973 return err; 5974 } 5975 5976 static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev) 5977 { 5978 struct mlx5_core_dev *mdev = dev->mdev; 5979 enum rdma_link_layer ll; 5980 int port_type_cap; 5981 5982 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 5983 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 5984 5985 if (ll == IB_LINK_LAYER_ETHERNET) { 5986 mlx5_disable_eth(dev); 5987 mlx5_ib_stage_common_roce_cleanup(dev); 5988 } 5989 } 5990 5991 int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev) 5992 { 5993 return create_dev_resources(&dev->devr); 5994 } 5995 5996 void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev) 5997 { 5998 destroy_dev_resources(&dev->devr); 5999 } 6000 6001 static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev) 6002 { 6003 mlx5_ib_internal_fill_odp_caps(dev); 6004 6005 return mlx5_ib_odp_init_one(dev); 6006 } 6007 6008 int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev) 6009 { 6010 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) { 6011 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats; 6012 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats; 6013 6014 return mlx5_ib_alloc_counters(dev); 6015 } 6016 6017 return 0; 6018 } 6019 6020 void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev) 6021 { 6022 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) 6023 mlx5_ib_dealloc_counters(dev); 6024 } 6025 6026 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev) 6027 { 6028 return mlx5_ib_init_cong_debugfs(dev, 6029 mlx5_core_native_port_num(dev->mdev) - 1); 6030 } 6031 6032 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev) 6033 { 6034 mlx5_ib_cleanup_cong_debugfs(dev, 6035 mlx5_core_native_port_num(dev->mdev) - 1); 6036 } 6037 6038 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev) 6039 { 6040 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev); 6041 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar); 6042 } 6043 6044 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev) 6045 { 6046 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar); 6047 } 6048 6049 int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev) 6050 { 6051 int err; 6052 6053 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false); 6054 if (err) 6055 return err; 6056 6057 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true); 6058 if (err) 6059 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 6060 6061 return err; 6062 } 6063 6064 void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev) 6065 { 6066 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 6067 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 6068 } 6069 6070 static int mlx5_ib_stage_populate_specs(struct mlx5_ib_dev *dev) 6071 { 6072 return populate_specs_root(dev); 6073 } 6074 6075 int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev) 6076 { 6077 return ib_register_device(&dev->ib_dev, NULL); 6078 } 6079 6080 void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev) 6081 { 6082 destroy_umrc_res(dev); 6083 } 6084 6085 void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev) 6086 { 6087 ib_unregister_device(&dev->ib_dev); 6088 } 6089 6090 int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev) 6091 { 6092 return create_umr_res(dev); 6093 } 6094 6095 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev) 6096 { 6097 init_delay_drop(dev); 6098 6099 return 0; 6100 } 6101 6102 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev) 6103 { 6104 cancel_delay_drop(dev); 6105 } 6106 6107 int mlx5_ib_stage_class_attr_init(struct mlx5_ib_dev *dev) 6108 { 6109 int err; 6110 int i; 6111 6112 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) { 6113 err = device_create_file(&dev->ib_dev.dev, 6114 mlx5_class_attributes[i]); 6115 if (err) 6116 return err; 6117 } 6118 6119 return 0; 6120 } 6121 6122 static int mlx5_ib_stage_rep_reg_init(struct mlx5_ib_dev *dev) 6123 { 6124 mlx5_ib_register_vport_reps(dev); 6125 6126 return 0; 6127 } 6128 6129 static void mlx5_ib_stage_rep_reg_cleanup(struct mlx5_ib_dev *dev) 6130 { 6131 mlx5_ib_unregister_vport_reps(dev); 6132 } 6133 6134 void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 6135 const struct mlx5_ib_profile *profile, 6136 int stage) 6137 { 6138 /* Number of stages to cleanup */ 6139 while (stage) { 6140 stage--; 6141 if (profile->stage[stage].cleanup) 6142 profile->stage[stage].cleanup(dev); 6143 } 6144 6145 ib_dealloc_device((struct ib_device *)dev); 6146 } 6147 6148 void *__mlx5_ib_add(struct mlx5_ib_dev *dev, 6149 const struct mlx5_ib_profile *profile) 6150 { 6151 int err; 6152 int i; 6153 6154 printk_once(KERN_INFO "%s", mlx5_version); 6155 6156 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) { 6157 if (profile->stage[i].init) { 6158 err = profile->stage[i].init(dev); 6159 if (err) 6160 goto err_out; 6161 } 6162 } 6163 6164 dev->profile = profile; 6165 dev->ib_active = true; 6166 6167 return dev; 6168 6169 err_out: 6170 __mlx5_ib_remove(dev, profile, i); 6171 6172 return NULL; 6173 } 6174 6175 static const struct mlx5_ib_profile pf_profile = { 6176 STAGE_CREATE(MLX5_IB_STAGE_INIT, 6177 mlx5_ib_stage_init_init, 6178 mlx5_ib_stage_init_cleanup), 6179 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB, 6180 mlx5_ib_stage_flow_db_init, 6181 mlx5_ib_stage_flow_db_cleanup), 6182 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 6183 mlx5_ib_stage_caps_init, 6184 NULL), 6185 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 6186 mlx5_ib_stage_non_default_cb, 6187 NULL), 6188 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 6189 mlx5_ib_stage_roce_init, 6190 mlx5_ib_stage_roce_cleanup), 6191 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 6192 mlx5_ib_stage_dev_res_init, 6193 mlx5_ib_stage_dev_res_cleanup), 6194 STAGE_CREATE(MLX5_IB_STAGE_ODP, 6195 mlx5_ib_stage_odp_init, 6196 NULL), 6197 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 6198 mlx5_ib_stage_counters_init, 6199 mlx5_ib_stage_counters_cleanup), 6200 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 6201 mlx5_ib_stage_cong_debugfs_init, 6202 mlx5_ib_stage_cong_debugfs_cleanup), 6203 STAGE_CREATE(MLX5_IB_STAGE_UAR, 6204 mlx5_ib_stage_uar_init, 6205 mlx5_ib_stage_uar_cleanup), 6206 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 6207 mlx5_ib_stage_bfrag_init, 6208 mlx5_ib_stage_bfrag_cleanup), 6209 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 6210 NULL, 6211 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 6212 STAGE_CREATE(MLX5_IB_STAGE_SPECS, 6213 mlx5_ib_stage_populate_specs, 6214 NULL), 6215 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 6216 mlx5_ib_stage_ib_reg_init, 6217 mlx5_ib_stage_ib_reg_cleanup), 6218 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 6219 mlx5_ib_stage_post_ib_reg_umr_init, 6220 NULL), 6221 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP, 6222 mlx5_ib_stage_delay_drop_init, 6223 mlx5_ib_stage_delay_drop_cleanup), 6224 STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR, 6225 mlx5_ib_stage_class_attr_init, 6226 NULL), 6227 }; 6228 6229 static const struct mlx5_ib_profile nic_rep_profile = { 6230 STAGE_CREATE(MLX5_IB_STAGE_INIT, 6231 mlx5_ib_stage_init_init, 6232 mlx5_ib_stage_init_cleanup), 6233 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB, 6234 mlx5_ib_stage_flow_db_init, 6235 mlx5_ib_stage_flow_db_cleanup), 6236 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 6237 mlx5_ib_stage_caps_init, 6238 NULL), 6239 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 6240 mlx5_ib_stage_rep_non_default_cb, 6241 NULL), 6242 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 6243 mlx5_ib_stage_rep_roce_init, 6244 mlx5_ib_stage_rep_roce_cleanup), 6245 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 6246 mlx5_ib_stage_dev_res_init, 6247 mlx5_ib_stage_dev_res_cleanup), 6248 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 6249 mlx5_ib_stage_counters_init, 6250 mlx5_ib_stage_counters_cleanup), 6251 STAGE_CREATE(MLX5_IB_STAGE_UAR, 6252 mlx5_ib_stage_uar_init, 6253 mlx5_ib_stage_uar_cleanup), 6254 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 6255 mlx5_ib_stage_bfrag_init, 6256 mlx5_ib_stage_bfrag_cleanup), 6257 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 6258 NULL, 6259 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 6260 STAGE_CREATE(MLX5_IB_STAGE_SPECS, 6261 mlx5_ib_stage_populate_specs, 6262 NULL), 6263 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 6264 mlx5_ib_stage_ib_reg_init, 6265 mlx5_ib_stage_ib_reg_cleanup), 6266 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 6267 mlx5_ib_stage_post_ib_reg_umr_init, 6268 NULL), 6269 STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR, 6270 mlx5_ib_stage_class_attr_init, 6271 NULL), 6272 STAGE_CREATE(MLX5_IB_STAGE_REP_REG, 6273 mlx5_ib_stage_rep_reg_init, 6274 mlx5_ib_stage_rep_reg_cleanup), 6275 }; 6276 6277 static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev) 6278 { 6279 struct mlx5_ib_multiport_info *mpi; 6280 struct mlx5_ib_dev *dev; 6281 bool bound = false; 6282 int err; 6283 6284 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 6285 if (!mpi) 6286 return NULL; 6287 6288 mpi->mdev = mdev; 6289 6290 err = mlx5_query_nic_vport_system_image_guid(mdev, 6291 &mpi->sys_image_guid); 6292 if (err) { 6293 kfree(mpi); 6294 return NULL; 6295 } 6296 6297 mutex_lock(&mlx5_ib_multiport_mutex); 6298 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) { 6299 if (dev->sys_image_guid == mpi->sys_image_guid) 6300 bound = mlx5_ib_bind_slave_port(dev, mpi); 6301 6302 if (bound) { 6303 rdma_roce_rescan_device(&dev->ib_dev); 6304 break; 6305 } 6306 } 6307 6308 if (!bound) { 6309 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 6310 dev_dbg(&mdev->pdev->dev, "no suitable IB device found to bind to, added to unaffiliated list.\n"); 6311 } 6312 mutex_unlock(&mlx5_ib_multiport_mutex); 6313 6314 return mpi; 6315 } 6316 6317 static void *mlx5_ib_add(struct mlx5_core_dev *mdev) 6318 { 6319 enum rdma_link_layer ll; 6320 struct mlx5_ib_dev *dev; 6321 int port_type_cap; 6322 6323 printk_once(KERN_INFO "%s", mlx5_version); 6324 6325 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 6326 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 6327 6328 if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET) 6329 return mlx5_ib_add_slave_port(mdev); 6330 6331 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev)); 6332 if (!dev) 6333 return NULL; 6334 6335 dev->mdev = mdev; 6336 dev->num_ports = max(MLX5_CAP_GEN(mdev, num_ports), 6337 MLX5_CAP_GEN(mdev, num_vhca_ports)); 6338 6339 if (MLX5_ESWITCH_MANAGER(mdev) && 6340 mlx5_ib_eswitch_mode(mdev->priv.eswitch) == SRIOV_OFFLOADS) { 6341 dev->rep = mlx5_ib_vport_rep(mdev->priv.eswitch, 0); 6342 6343 return __mlx5_ib_add(dev, &nic_rep_profile); 6344 } 6345 6346 return __mlx5_ib_add(dev, &pf_profile); 6347 } 6348 6349 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context) 6350 { 6351 struct mlx5_ib_multiport_info *mpi; 6352 struct mlx5_ib_dev *dev; 6353 6354 if (mlx5_core_is_mp_slave(mdev)) { 6355 mpi = context; 6356 mutex_lock(&mlx5_ib_multiport_mutex); 6357 if (mpi->ibdev) 6358 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi); 6359 list_del(&mpi->list); 6360 mutex_unlock(&mlx5_ib_multiport_mutex); 6361 return; 6362 } 6363 6364 dev = context; 6365 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX); 6366 } 6367 6368 static struct mlx5_interface mlx5_ib_interface = { 6369 .add = mlx5_ib_add, 6370 .remove = mlx5_ib_remove, 6371 .event = mlx5_ib_event, 6372 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 6373 .pfault = mlx5_ib_pfault, 6374 #endif 6375 .protocol = MLX5_INTERFACE_PROTOCOL_IB, 6376 }; 6377 6378 unsigned long mlx5_ib_get_xlt_emergency_page(void) 6379 { 6380 mutex_lock(&xlt_emergency_page_mutex); 6381 return xlt_emergency_page; 6382 } 6383 6384 void mlx5_ib_put_xlt_emergency_page(void) 6385 { 6386 mutex_unlock(&xlt_emergency_page_mutex); 6387 } 6388 6389 static int __init mlx5_ib_init(void) 6390 { 6391 int err; 6392 6393 xlt_emergency_page = __get_free_page(GFP_KERNEL); 6394 if (!xlt_emergency_page) 6395 return -ENOMEM; 6396 6397 mutex_init(&xlt_emergency_page_mutex); 6398 6399 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0); 6400 if (!mlx5_ib_event_wq) { 6401 free_page(xlt_emergency_page); 6402 return -ENOMEM; 6403 } 6404 6405 mlx5_ib_odp_init(); 6406 6407 err = mlx5_register_interface(&mlx5_ib_interface); 6408 6409 return err; 6410 } 6411 6412 static void __exit mlx5_ib_cleanup(void) 6413 { 6414 mlx5_unregister_interface(&mlx5_ib_interface); 6415 destroy_workqueue(mlx5_ib_event_wq); 6416 mutex_destroy(&xlt_emergency_page_mutex); 6417 free_page(xlt_emergency_page); 6418 } 6419 6420 module_init(mlx5_ib_init); 6421 module_exit(mlx5_ib_cleanup); 6422