1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/highmem.h> 34 #include <linux/module.h> 35 #include <linux/init.h> 36 #include <linux/errno.h> 37 #include <linux/pci.h> 38 #include <linux/dma-mapping.h> 39 #include <linux/slab.h> 40 #include <linux/io-mapping.h> 41 #include <linux/sched.h> 42 #include <rdma/ib_user_verbs.h> 43 #include <rdma/ib_addr.h> 44 #include <rdma/ib_cache.h> 45 #include <linux/mlx5/vport.h> 46 #include <rdma/ib_smi.h> 47 #include <rdma/ib_umem.h> 48 #include <linux/in.h> 49 #include <linux/etherdevice.h> 50 #include <linux/mlx5/fs.h> 51 #include "user.h" 52 #include "mlx5_ib.h" 53 54 #define DRIVER_NAME "mlx5_ib" 55 #define DRIVER_VERSION "2.2-1" 56 #define DRIVER_RELDATE "Feb 2014" 57 58 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 59 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver"); 60 MODULE_LICENSE("Dual BSD/GPL"); 61 MODULE_VERSION(DRIVER_VERSION); 62 63 static int deprecated_prof_sel = 2; 64 module_param_named(prof_sel, deprecated_prof_sel, int, 0444); 65 MODULE_PARM_DESC(prof_sel, "profile selector. Deprecated here. Moved to module mlx5_core"); 66 67 static char mlx5_version[] = 68 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v" 69 DRIVER_VERSION " (" DRIVER_RELDATE ")\n"; 70 71 enum { 72 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 73 }; 74 75 static enum rdma_link_layer 76 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 77 { 78 switch (port_type_cap) { 79 case MLX5_CAP_PORT_TYPE_IB: 80 return IB_LINK_LAYER_INFINIBAND; 81 case MLX5_CAP_PORT_TYPE_ETH: 82 return IB_LINK_LAYER_ETHERNET; 83 default: 84 return IB_LINK_LAYER_UNSPECIFIED; 85 } 86 } 87 88 static enum rdma_link_layer 89 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num) 90 { 91 struct mlx5_ib_dev *dev = to_mdev(device); 92 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 93 94 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 95 } 96 97 static int mlx5_netdev_event(struct notifier_block *this, 98 unsigned long event, void *ptr) 99 { 100 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 101 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev, 102 roce.nb); 103 104 if ((event != NETDEV_UNREGISTER) && (event != NETDEV_REGISTER)) 105 return NOTIFY_DONE; 106 107 write_lock(&ibdev->roce.netdev_lock); 108 if (ndev->dev.parent == &ibdev->mdev->pdev->dev) 109 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ? NULL : ndev; 110 write_unlock(&ibdev->roce.netdev_lock); 111 112 return NOTIFY_DONE; 113 } 114 115 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device, 116 u8 port_num) 117 { 118 struct mlx5_ib_dev *ibdev = to_mdev(device); 119 struct net_device *ndev; 120 121 /* Ensure ndev does not disappear before we invoke dev_hold() 122 */ 123 read_lock(&ibdev->roce.netdev_lock); 124 ndev = ibdev->roce.netdev; 125 if (ndev) 126 dev_hold(ndev); 127 read_unlock(&ibdev->roce.netdev_lock); 128 129 return ndev; 130 } 131 132 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num, 133 struct ib_port_attr *props) 134 { 135 struct mlx5_ib_dev *dev = to_mdev(device); 136 struct net_device *ndev; 137 enum ib_mtu ndev_ib_mtu; 138 u16 qkey_viol_cntr; 139 140 memset(props, 0, sizeof(*props)); 141 142 props->port_cap_flags |= IB_PORT_CM_SUP; 143 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS; 144 145 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 146 roce_address_table_size); 147 props->max_mtu = IB_MTU_4096; 148 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 149 props->pkey_tbl_len = 1; 150 props->state = IB_PORT_DOWN; 151 props->phys_state = 3; 152 153 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr); 154 props->qkey_viol_cntr = qkey_viol_cntr; 155 156 ndev = mlx5_ib_get_netdev(device, port_num); 157 if (!ndev) 158 return 0; 159 160 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 161 props->state = IB_PORT_ACTIVE; 162 props->phys_state = 5; 163 } 164 165 ndev_ib_mtu = iboe_get_mtu(ndev->mtu); 166 167 dev_put(ndev); 168 169 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 170 171 props->active_width = IB_WIDTH_4X; /* TODO */ 172 props->active_speed = IB_SPEED_QDR; /* TODO */ 173 174 return 0; 175 } 176 177 static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid, 178 const struct ib_gid_attr *attr, 179 void *mlx5_addr) 180 { 181 #define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v) 182 char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr, 183 source_l3_address); 184 void *mlx5_addr_mac = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr, 185 source_mac_47_32); 186 187 if (!gid) 188 return; 189 190 ether_addr_copy(mlx5_addr_mac, attr->ndev->dev_addr); 191 192 if (is_vlan_dev(attr->ndev)) { 193 MLX5_SET_RA(mlx5_addr, vlan_valid, 1); 194 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_dev_vlan_id(attr->ndev)); 195 } 196 197 switch (attr->gid_type) { 198 case IB_GID_TYPE_IB: 199 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1); 200 break; 201 case IB_GID_TYPE_ROCE_UDP_ENCAP: 202 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2); 203 break; 204 205 default: 206 WARN_ON(true); 207 } 208 209 if (attr->gid_type != IB_GID_TYPE_IB) { 210 if (ipv6_addr_v4mapped((void *)gid)) 211 MLX5_SET_RA(mlx5_addr, roce_l3_type, 212 MLX5_ROCE_L3_TYPE_IPV4); 213 else 214 MLX5_SET_RA(mlx5_addr, roce_l3_type, 215 MLX5_ROCE_L3_TYPE_IPV6); 216 } 217 218 if ((attr->gid_type == IB_GID_TYPE_IB) || 219 !ipv6_addr_v4mapped((void *)gid)) 220 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid)); 221 else 222 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4); 223 } 224 225 static int set_roce_addr(struct ib_device *device, u8 port_num, 226 unsigned int index, 227 const union ib_gid *gid, 228 const struct ib_gid_attr *attr) 229 { 230 struct mlx5_ib_dev *dev = to_mdev(device); 231 u32 in[MLX5_ST_SZ_DW(set_roce_address_in)]; 232 u32 out[MLX5_ST_SZ_DW(set_roce_address_out)]; 233 void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address); 234 enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num); 235 236 if (ll != IB_LINK_LAYER_ETHERNET) 237 return -EINVAL; 238 239 memset(in, 0, sizeof(in)); 240 241 ib_gid_to_mlx5_roce_addr(gid, attr, in_addr); 242 243 MLX5_SET(set_roce_address_in, in, roce_address_index, index); 244 MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS); 245 246 memset(out, 0, sizeof(out)); 247 return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out)); 248 } 249 250 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num, 251 unsigned int index, const union ib_gid *gid, 252 const struct ib_gid_attr *attr, 253 __always_unused void **context) 254 { 255 return set_roce_addr(device, port_num, index, gid, attr); 256 } 257 258 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num, 259 unsigned int index, __always_unused void **context) 260 { 261 return set_roce_addr(device, port_num, index, NULL, NULL); 262 } 263 264 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num, 265 int index) 266 { 267 struct ib_gid_attr attr; 268 union ib_gid gid; 269 270 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr)) 271 return 0; 272 273 if (!attr.ndev) 274 return 0; 275 276 dev_put(attr.ndev); 277 278 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 279 return 0; 280 281 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 282 } 283 284 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 285 { 286 return !dev->mdev->issi; 287 } 288 289 enum { 290 MLX5_VPORT_ACCESS_METHOD_MAD, 291 MLX5_VPORT_ACCESS_METHOD_HCA, 292 MLX5_VPORT_ACCESS_METHOD_NIC, 293 }; 294 295 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 296 { 297 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 298 return MLX5_VPORT_ACCESS_METHOD_MAD; 299 300 if (mlx5_ib_port_link_layer(ibdev, 1) == 301 IB_LINK_LAYER_ETHERNET) 302 return MLX5_VPORT_ACCESS_METHOD_NIC; 303 304 return MLX5_VPORT_ACCESS_METHOD_HCA; 305 } 306 307 static void get_atomic_caps(struct mlx5_ib_dev *dev, 308 struct ib_device_attr *props) 309 { 310 u8 tmp; 311 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 312 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 313 u8 atomic_req_8B_endianness_mode = 314 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode); 315 316 /* Check if HW supports 8 bytes standard atomic operations and capable 317 * of host endianness respond 318 */ 319 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 320 if (((atomic_operations & tmp) == tmp) && 321 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 322 (atomic_req_8B_endianness_mode)) { 323 props->atomic_cap = IB_ATOMIC_HCA; 324 } else { 325 props->atomic_cap = IB_ATOMIC_NONE; 326 } 327 } 328 329 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 330 __be64 *sys_image_guid) 331 { 332 struct mlx5_ib_dev *dev = to_mdev(ibdev); 333 struct mlx5_core_dev *mdev = dev->mdev; 334 u64 tmp; 335 int err; 336 337 switch (mlx5_get_vport_access_method(ibdev)) { 338 case MLX5_VPORT_ACCESS_METHOD_MAD: 339 return mlx5_query_mad_ifc_system_image_guid(ibdev, 340 sys_image_guid); 341 342 case MLX5_VPORT_ACCESS_METHOD_HCA: 343 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 344 break; 345 346 case MLX5_VPORT_ACCESS_METHOD_NIC: 347 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 348 break; 349 350 default: 351 return -EINVAL; 352 } 353 354 if (!err) 355 *sys_image_guid = cpu_to_be64(tmp); 356 357 return err; 358 359 } 360 361 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 362 u16 *max_pkeys) 363 { 364 struct mlx5_ib_dev *dev = to_mdev(ibdev); 365 struct mlx5_core_dev *mdev = dev->mdev; 366 367 switch (mlx5_get_vport_access_method(ibdev)) { 368 case MLX5_VPORT_ACCESS_METHOD_MAD: 369 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 370 371 case MLX5_VPORT_ACCESS_METHOD_HCA: 372 case MLX5_VPORT_ACCESS_METHOD_NIC: 373 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 374 pkey_table_size)); 375 return 0; 376 377 default: 378 return -EINVAL; 379 } 380 } 381 382 static int mlx5_query_vendor_id(struct ib_device *ibdev, 383 u32 *vendor_id) 384 { 385 struct mlx5_ib_dev *dev = to_mdev(ibdev); 386 387 switch (mlx5_get_vport_access_method(ibdev)) { 388 case MLX5_VPORT_ACCESS_METHOD_MAD: 389 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 390 391 case MLX5_VPORT_ACCESS_METHOD_HCA: 392 case MLX5_VPORT_ACCESS_METHOD_NIC: 393 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 394 395 default: 396 return -EINVAL; 397 } 398 } 399 400 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 401 __be64 *node_guid) 402 { 403 u64 tmp; 404 int err; 405 406 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 407 case MLX5_VPORT_ACCESS_METHOD_MAD: 408 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 409 410 case MLX5_VPORT_ACCESS_METHOD_HCA: 411 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 412 break; 413 414 case MLX5_VPORT_ACCESS_METHOD_NIC: 415 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 416 break; 417 418 default: 419 return -EINVAL; 420 } 421 422 if (!err) 423 *node_guid = cpu_to_be64(tmp); 424 425 return err; 426 } 427 428 struct mlx5_reg_node_desc { 429 u8 desc[64]; 430 }; 431 432 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 433 { 434 struct mlx5_reg_node_desc in; 435 436 if (mlx5_use_mad_ifc(dev)) 437 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 438 439 memset(&in, 0, sizeof(in)); 440 441 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 442 sizeof(struct mlx5_reg_node_desc), 443 MLX5_REG_NODE_DESC, 0, 0); 444 } 445 446 static int mlx5_ib_query_device(struct ib_device *ibdev, 447 struct ib_device_attr *props, 448 struct ib_udata *uhw) 449 { 450 struct mlx5_ib_dev *dev = to_mdev(ibdev); 451 struct mlx5_core_dev *mdev = dev->mdev; 452 int err = -ENOMEM; 453 int max_rq_sg; 454 int max_sq_sg; 455 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 456 457 if (uhw->inlen || uhw->outlen) 458 return -EINVAL; 459 460 memset(props, 0, sizeof(*props)); 461 err = mlx5_query_system_image_guid(ibdev, 462 &props->sys_image_guid); 463 if (err) 464 return err; 465 466 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys); 467 if (err) 468 return err; 469 470 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 471 if (err) 472 return err; 473 474 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 475 (fw_rev_min(dev->mdev) << 16) | 476 fw_rev_sub(dev->mdev); 477 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 478 IB_DEVICE_PORT_ACTIVE_EVENT | 479 IB_DEVICE_SYS_IMAGE_GUID | 480 IB_DEVICE_RC_RNR_NAK_GEN; 481 482 if (MLX5_CAP_GEN(mdev, pkv)) 483 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 484 if (MLX5_CAP_GEN(mdev, qkv)) 485 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 486 if (MLX5_CAP_GEN(mdev, apm)) 487 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 488 if (MLX5_CAP_GEN(mdev, xrc)) 489 props->device_cap_flags |= IB_DEVICE_XRC; 490 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 491 if (MLX5_CAP_GEN(mdev, sho)) { 492 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER; 493 /* At this stage no support for signature handover */ 494 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 495 IB_PROT_T10DIF_TYPE_2 | 496 IB_PROT_T10DIF_TYPE_3; 497 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 498 IB_GUARD_T10DIF_CSUM; 499 } 500 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 501 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 502 503 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 504 (MLX5_CAP_ETH(dev->mdev, csum_cap))) 505 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 506 507 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 508 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 509 props->device_cap_flags |= IB_DEVICE_UD_TSO; 510 } 511 512 props->vendor_part_id = mdev->pdev->device; 513 props->hw_ver = mdev->pdev->revision; 514 515 props->max_mr_size = ~0ull; 516 props->page_size_cap = ~(min_page_size - 1); 517 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 518 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 519 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 520 sizeof(struct mlx5_wqe_data_seg); 521 max_sq_sg = (MLX5_CAP_GEN(mdev, max_wqe_sz_sq) - 522 sizeof(struct mlx5_wqe_ctrl_seg)) / 523 sizeof(struct mlx5_wqe_data_seg); 524 props->max_sge = min(max_rq_sg, max_sq_sg); 525 props->max_sge_rd = props->max_sge; 526 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 527 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 528 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 529 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 530 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 531 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 532 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 533 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 534 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 535 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 536 props->max_srq_sge = max_rq_sg - 1; 537 props->max_fast_reg_page_list_len = (unsigned int)-1; 538 get_atomic_caps(dev, props); 539 props->masked_atomic_cap = IB_ATOMIC_NONE; 540 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 541 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 542 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 543 props->max_mcast_grp; 544 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */ 545 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 546 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 547 548 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 549 if (MLX5_CAP_GEN(mdev, pg)) 550 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING; 551 props->odp_caps = dev->odp_caps; 552 #endif 553 554 if (MLX5_CAP_GEN(mdev, cd)) 555 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL; 556 557 return 0; 558 } 559 560 enum mlx5_ib_width { 561 MLX5_IB_WIDTH_1X = 1 << 0, 562 MLX5_IB_WIDTH_2X = 1 << 1, 563 MLX5_IB_WIDTH_4X = 1 << 2, 564 MLX5_IB_WIDTH_8X = 1 << 3, 565 MLX5_IB_WIDTH_12X = 1 << 4 566 }; 567 568 static int translate_active_width(struct ib_device *ibdev, u8 active_width, 569 u8 *ib_width) 570 { 571 struct mlx5_ib_dev *dev = to_mdev(ibdev); 572 int err = 0; 573 574 if (active_width & MLX5_IB_WIDTH_1X) { 575 *ib_width = IB_WIDTH_1X; 576 } else if (active_width & MLX5_IB_WIDTH_2X) { 577 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n", 578 (int)active_width); 579 err = -EINVAL; 580 } else if (active_width & MLX5_IB_WIDTH_4X) { 581 *ib_width = IB_WIDTH_4X; 582 } else if (active_width & MLX5_IB_WIDTH_8X) { 583 *ib_width = IB_WIDTH_8X; 584 } else if (active_width & MLX5_IB_WIDTH_12X) { 585 *ib_width = IB_WIDTH_12X; 586 } else { 587 mlx5_ib_dbg(dev, "Invalid active_width %d\n", 588 (int)active_width); 589 err = -EINVAL; 590 } 591 592 return err; 593 } 594 595 static int mlx5_mtu_to_ib_mtu(int mtu) 596 { 597 switch (mtu) { 598 case 256: return 1; 599 case 512: return 2; 600 case 1024: return 3; 601 case 2048: return 4; 602 case 4096: return 5; 603 default: 604 pr_warn("invalid mtu\n"); 605 return -1; 606 } 607 } 608 609 enum ib_max_vl_num { 610 __IB_MAX_VL_0 = 1, 611 __IB_MAX_VL_0_1 = 2, 612 __IB_MAX_VL_0_3 = 3, 613 __IB_MAX_VL_0_7 = 4, 614 __IB_MAX_VL_0_14 = 5, 615 }; 616 617 enum mlx5_vl_hw_cap { 618 MLX5_VL_HW_0 = 1, 619 MLX5_VL_HW_0_1 = 2, 620 MLX5_VL_HW_0_2 = 3, 621 MLX5_VL_HW_0_3 = 4, 622 MLX5_VL_HW_0_4 = 5, 623 MLX5_VL_HW_0_5 = 6, 624 MLX5_VL_HW_0_6 = 7, 625 MLX5_VL_HW_0_7 = 8, 626 MLX5_VL_HW_0_14 = 15 627 }; 628 629 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 630 u8 *max_vl_num) 631 { 632 switch (vl_hw_cap) { 633 case MLX5_VL_HW_0: 634 *max_vl_num = __IB_MAX_VL_0; 635 break; 636 case MLX5_VL_HW_0_1: 637 *max_vl_num = __IB_MAX_VL_0_1; 638 break; 639 case MLX5_VL_HW_0_3: 640 *max_vl_num = __IB_MAX_VL_0_3; 641 break; 642 case MLX5_VL_HW_0_7: 643 *max_vl_num = __IB_MAX_VL_0_7; 644 break; 645 case MLX5_VL_HW_0_14: 646 *max_vl_num = __IB_MAX_VL_0_14; 647 break; 648 649 default: 650 return -EINVAL; 651 } 652 653 return 0; 654 } 655 656 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port, 657 struct ib_port_attr *props) 658 { 659 struct mlx5_ib_dev *dev = to_mdev(ibdev); 660 struct mlx5_core_dev *mdev = dev->mdev; 661 struct mlx5_hca_vport_context *rep; 662 int max_mtu; 663 int oper_mtu; 664 int err; 665 u8 ib_link_width_oper; 666 u8 vl_hw_cap; 667 668 rep = kzalloc(sizeof(*rep), GFP_KERNEL); 669 if (!rep) { 670 err = -ENOMEM; 671 goto out; 672 } 673 674 memset(props, 0, sizeof(*props)); 675 676 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); 677 if (err) 678 goto out; 679 680 props->lid = rep->lid; 681 props->lmc = rep->lmc; 682 props->sm_lid = rep->sm_lid; 683 props->sm_sl = rep->sm_sl; 684 props->state = rep->vport_state; 685 props->phys_state = rep->port_physical_state; 686 props->port_cap_flags = rep->cap_mask1; 687 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 688 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 689 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 690 props->bad_pkey_cntr = rep->pkey_violation_counter; 691 props->qkey_viol_cntr = rep->qkey_violation_counter; 692 props->subnet_timeout = rep->subnet_timeout; 693 props->init_type_reply = rep->init_type_reply; 694 695 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port); 696 if (err) 697 goto out; 698 699 err = translate_active_width(ibdev, ib_link_width_oper, 700 &props->active_width); 701 if (err) 702 goto out; 703 err = mlx5_query_port_proto_oper(mdev, &props->active_speed, MLX5_PTYS_IB, 704 port); 705 if (err) 706 goto out; 707 708 mlx5_query_port_max_mtu(mdev, &max_mtu, port); 709 710 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); 711 712 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); 713 714 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); 715 716 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); 717 if (err) 718 goto out; 719 720 err = translate_max_vl_num(ibdev, vl_hw_cap, 721 &props->max_vl_num); 722 out: 723 kfree(rep); 724 return err; 725 } 726 727 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 728 struct ib_port_attr *props) 729 { 730 switch (mlx5_get_vport_access_method(ibdev)) { 731 case MLX5_VPORT_ACCESS_METHOD_MAD: 732 return mlx5_query_mad_ifc_port(ibdev, port, props); 733 734 case MLX5_VPORT_ACCESS_METHOD_HCA: 735 return mlx5_query_hca_port(ibdev, port, props); 736 737 case MLX5_VPORT_ACCESS_METHOD_NIC: 738 return mlx5_query_port_roce(ibdev, port, props); 739 740 default: 741 return -EINVAL; 742 } 743 } 744 745 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 746 union ib_gid *gid) 747 { 748 struct mlx5_ib_dev *dev = to_mdev(ibdev); 749 struct mlx5_core_dev *mdev = dev->mdev; 750 751 switch (mlx5_get_vport_access_method(ibdev)) { 752 case MLX5_VPORT_ACCESS_METHOD_MAD: 753 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 754 755 case MLX5_VPORT_ACCESS_METHOD_HCA: 756 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); 757 758 default: 759 return -EINVAL; 760 } 761 762 } 763 764 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 765 u16 *pkey) 766 { 767 struct mlx5_ib_dev *dev = to_mdev(ibdev); 768 struct mlx5_core_dev *mdev = dev->mdev; 769 770 switch (mlx5_get_vport_access_method(ibdev)) { 771 case MLX5_VPORT_ACCESS_METHOD_MAD: 772 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 773 774 case MLX5_VPORT_ACCESS_METHOD_HCA: 775 case MLX5_VPORT_ACCESS_METHOD_NIC: 776 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index, 777 pkey); 778 default: 779 return -EINVAL; 780 } 781 } 782 783 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 784 struct ib_device_modify *props) 785 { 786 struct mlx5_ib_dev *dev = to_mdev(ibdev); 787 struct mlx5_reg_node_desc in; 788 struct mlx5_reg_node_desc out; 789 int err; 790 791 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 792 return -EOPNOTSUPP; 793 794 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 795 return 0; 796 797 /* 798 * If possible, pass node desc to FW, so it can generate 799 * a 144 trap. If cmd fails, just ignore. 800 */ 801 memcpy(&in, props->node_desc, 64); 802 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 803 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 804 if (err) 805 return err; 806 807 memcpy(ibdev->node_desc, props->node_desc, 64); 808 809 return err; 810 } 811 812 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, 813 struct ib_port_modify *props) 814 { 815 struct mlx5_ib_dev *dev = to_mdev(ibdev); 816 struct ib_port_attr attr; 817 u32 tmp; 818 int err; 819 820 mutex_lock(&dev->cap_mask_mutex); 821 822 err = mlx5_ib_query_port(ibdev, port, &attr); 823 if (err) 824 goto out; 825 826 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 827 ~props->clr_port_cap_mask; 828 829 err = mlx5_set_port_caps(dev->mdev, port, tmp); 830 831 out: 832 mutex_unlock(&dev->cap_mask_mutex); 833 return err; 834 } 835 836 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev, 837 struct ib_udata *udata) 838 { 839 struct mlx5_ib_dev *dev = to_mdev(ibdev); 840 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 841 struct mlx5_ib_alloc_ucontext_resp resp = {}; 842 struct mlx5_ib_ucontext *context; 843 struct mlx5_uuar_info *uuari; 844 struct mlx5_uar *uars; 845 int gross_uuars; 846 int num_uars; 847 int ver; 848 int uuarn; 849 int err; 850 int i; 851 size_t reqlen; 852 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 853 max_cqe_version); 854 855 if (!dev->ib_active) 856 return ERR_PTR(-EAGAIN); 857 858 if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr)) 859 return ERR_PTR(-EINVAL); 860 861 reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr); 862 if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 863 ver = 0; 864 else if (reqlen >= min_req_v2) 865 ver = 2; 866 else 867 return ERR_PTR(-EINVAL); 868 869 err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req))); 870 if (err) 871 return ERR_PTR(err); 872 873 if (req.flags) 874 return ERR_PTR(-EINVAL); 875 876 if (req.total_num_uuars > MLX5_MAX_UUARS) 877 return ERR_PTR(-ENOMEM); 878 879 if (req.total_num_uuars == 0) 880 return ERR_PTR(-EINVAL); 881 882 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 883 return ERR_PTR(-EOPNOTSUPP); 884 885 if (reqlen > sizeof(req) && 886 !ib_is_udata_cleared(udata, sizeof(req), 887 reqlen - sizeof(req))) 888 return ERR_PTR(-EOPNOTSUPP); 889 890 req.total_num_uuars = ALIGN(req.total_num_uuars, 891 MLX5_NON_FP_BF_REGS_PER_PAGE); 892 if (req.num_low_latency_uuars > req.total_num_uuars - 1) 893 return ERR_PTR(-EINVAL); 894 895 num_uars = req.total_num_uuars / MLX5_NON_FP_BF_REGS_PER_PAGE; 896 gross_uuars = num_uars * MLX5_BF_REGS_PER_PAGE; 897 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 898 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size); 899 resp.cache_line_size = L1_CACHE_BYTES; 900 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 901 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 902 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 903 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 904 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 905 resp.cqe_version = min_t(__u8, 906 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 907 req.max_cqe_version); 908 resp.response_length = min(offsetof(typeof(resp), response_length) + 909 sizeof(resp.response_length), udata->outlen); 910 911 context = kzalloc(sizeof(*context), GFP_KERNEL); 912 if (!context) 913 return ERR_PTR(-ENOMEM); 914 915 uuari = &context->uuari; 916 mutex_init(&uuari->lock); 917 uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL); 918 if (!uars) { 919 err = -ENOMEM; 920 goto out_ctx; 921 } 922 923 uuari->bitmap = kcalloc(BITS_TO_LONGS(gross_uuars), 924 sizeof(*uuari->bitmap), 925 GFP_KERNEL); 926 if (!uuari->bitmap) { 927 err = -ENOMEM; 928 goto out_uar_ctx; 929 } 930 /* 931 * clear all fast path uuars 932 */ 933 for (i = 0; i < gross_uuars; i++) { 934 uuarn = i & 3; 935 if (uuarn == 2 || uuarn == 3) 936 set_bit(i, uuari->bitmap); 937 } 938 939 uuari->count = kcalloc(gross_uuars, sizeof(*uuari->count), GFP_KERNEL); 940 if (!uuari->count) { 941 err = -ENOMEM; 942 goto out_bitmap; 943 } 944 945 for (i = 0; i < num_uars; i++) { 946 err = mlx5_cmd_alloc_uar(dev->mdev, &uars[i].index); 947 if (err) 948 goto out_count; 949 } 950 951 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 952 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range; 953 #endif 954 955 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) { 956 err = mlx5_core_alloc_transport_domain(dev->mdev, 957 &context->tdn); 958 if (err) 959 goto out_uars; 960 } 961 962 INIT_LIST_HEAD(&context->db_page_list); 963 mutex_init(&context->db_page_mutex); 964 965 resp.tot_uuars = req.total_num_uuars; 966 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports); 967 968 if (field_avail(typeof(resp), cqe_version, udata->outlen)) 969 resp.response_length += sizeof(resp.cqe_version); 970 971 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) { 972 resp.comp_mask |= 973 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 974 resp.hca_core_clock_offset = 975 offsetof(struct mlx5_init_seg, internal_timer_h) % 976 PAGE_SIZE; 977 resp.response_length += sizeof(resp.hca_core_clock_offset) + 978 sizeof(resp.reserved2) + 979 sizeof(resp.reserved3); 980 } 981 982 err = ib_copy_to_udata(udata, &resp, resp.response_length); 983 if (err) 984 goto out_td; 985 986 uuari->ver = ver; 987 uuari->num_low_latency_uuars = req.num_low_latency_uuars; 988 uuari->uars = uars; 989 uuari->num_uars = num_uars; 990 context->cqe_version = resp.cqe_version; 991 992 return &context->ibucontext; 993 994 out_td: 995 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 996 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn); 997 998 out_uars: 999 for (i--; i >= 0; i--) 1000 mlx5_cmd_free_uar(dev->mdev, uars[i].index); 1001 out_count: 1002 kfree(uuari->count); 1003 1004 out_bitmap: 1005 kfree(uuari->bitmap); 1006 1007 out_uar_ctx: 1008 kfree(uars); 1009 1010 out_ctx: 1011 kfree(context); 1012 return ERR_PTR(err); 1013 } 1014 1015 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1016 { 1017 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1018 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1019 struct mlx5_uuar_info *uuari = &context->uuari; 1020 int i; 1021 1022 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1023 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn); 1024 1025 for (i = 0; i < uuari->num_uars; i++) { 1026 if (mlx5_cmd_free_uar(dev->mdev, uuari->uars[i].index)) 1027 mlx5_ib_warn(dev, "failed to free UAR 0x%x\n", uuari->uars[i].index); 1028 } 1029 1030 kfree(uuari->count); 1031 kfree(uuari->bitmap); 1032 kfree(uuari->uars); 1033 kfree(context); 1034 1035 return 0; 1036 } 1037 1038 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index) 1039 { 1040 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + index; 1041 } 1042 1043 static int get_command(unsigned long offset) 1044 { 1045 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 1046 } 1047 1048 static int get_arg(unsigned long offset) 1049 { 1050 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 1051 } 1052 1053 static int get_index(unsigned long offset) 1054 { 1055 return get_arg(offset); 1056 } 1057 1058 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 1059 { 1060 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1061 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1062 struct mlx5_uuar_info *uuari = &context->uuari; 1063 unsigned long command; 1064 unsigned long idx; 1065 phys_addr_t pfn; 1066 1067 command = get_command(vma->vm_pgoff); 1068 switch (command) { 1069 case MLX5_IB_MMAP_REGULAR_PAGE: 1070 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1071 return -EINVAL; 1072 1073 idx = get_index(vma->vm_pgoff); 1074 if (idx >= uuari->num_uars) 1075 return -EINVAL; 1076 1077 pfn = uar_index2pfn(dev, uuari->uars[idx].index); 1078 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn 0x%llx\n", idx, 1079 (unsigned long long)pfn); 1080 1081 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); 1082 if (io_remap_pfn_range(vma, vma->vm_start, pfn, 1083 PAGE_SIZE, vma->vm_page_prot)) 1084 return -EAGAIN; 1085 1086 mlx5_ib_dbg(dev, "mapped WC at 0x%lx, PA 0x%llx\n", 1087 vma->vm_start, 1088 (unsigned long long)pfn << PAGE_SHIFT); 1089 break; 1090 1091 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 1092 return -ENOSYS; 1093 1094 case MLX5_IB_MMAP_CORE_CLOCK: 1095 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1096 return -EINVAL; 1097 1098 if (vma->vm_flags & (VM_WRITE | VM_EXEC)) 1099 return -EPERM; 1100 1101 /* Don't expose to user-space information it shouldn't have */ 1102 if (PAGE_SIZE > 4096) 1103 return -EOPNOTSUPP; 1104 1105 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 1106 pfn = (dev->mdev->iseg_base + 1107 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 1108 PAGE_SHIFT; 1109 if (io_remap_pfn_range(vma, vma->vm_start, pfn, 1110 PAGE_SIZE, vma->vm_page_prot)) 1111 return -EAGAIN; 1112 1113 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n", 1114 vma->vm_start, 1115 (unsigned long long)pfn << PAGE_SHIFT); 1116 break; 1117 1118 default: 1119 return -EINVAL; 1120 } 1121 1122 return 0; 1123 } 1124 1125 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev, 1126 struct ib_ucontext *context, 1127 struct ib_udata *udata) 1128 { 1129 struct mlx5_ib_alloc_pd_resp resp; 1130 struct mlx5_ib_pd *pd; 1131 int err; 1132 1133 pd = kmalloc(sizeof(*pd), GFP_KERNEL); 1134 if (!pd) 1135 return ERR_PTR(-ENOMEM); 1136 1137 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn); 1138 if (err) { 1139 kfree(pd); 1140 return ERR_PTR(err); 1141 } 1142 1143 if (context) { 1144 resp.pdn = pd->pdn; 1145 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 1146 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn); 1147 kfree(pd); 1148 return ERR_PTR(-EFAULT); 1149 } 1150 } 1151 1152 return &pd->ibpd; 1153 } 1154 1155 static int mlx5_ib_dealloc_pd(struct ib_pd *pd) 1156 { 1157 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 1158 struct mlx5_ib_pd *mpd = to_mpd(pd); 1159 1160 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn); 1161 kfree(mpd); 1162 1163 return 0; 1164 } 1165 1166 static bool outer_header_zero(u32 *match_criteria) 1167 { 1168 int size = MLX5_ST_SZ_BYTES(fte_match_param); 1169 char *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_criteria, 1170 outer_headers); 1171 1172 return outer_headers_c[0] == 0 && !memcmp(outer_headers_c, 1173 outer_headers_c + 1, 1174 size - 1); 1175 } 1176 1177 static int parse_flow_attr(u32 *match_c, u32 *match_v, 1178 union ib_flow_spec *ib_spec) 1179 { 1180 void *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 1181 outer_headers); 1182 void *outer_headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 1183 outer_headers); 1184 switch (ib_spec->type) { 1185 case IB_FLOW_SPEC_ETH: 1186 if (ib_spec->size != sizeof(ib_spec->eth)) 1187 return -EINVAL; 1188 1189 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1190 dmac_47_16), 1191 ib_spec->eth.mask.dst_mac); 1192 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1193 dmac_47_16), 1194 ib_spec->eth.val.dst_mac); 1195 1196 if (ib_spec->eth.mask.vlan_tag) { 1197 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1198 vlan_tag, 1); 1199 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1200 vlan_tag, 1); 1201 1202 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1203 first_vid, ntohs(ib_spec->eth.mask.vlan_tag)); 1204 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1205 first_vid, ntohs(ib_spec->eth.val.vlan_tag)); 1206 1207 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1208 first_cfi, 1209 ntohs(ib_spec->eth.mask.vlan_tag) >> 12); 1210 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1211 first_cfi, 1212 ntohs(ib_spec->eth.val.vlan_tag) >> 12); 1213 1214 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1215 first_prio, 1216 ntohs(ib_spec->eth.mask.vlan_tag) >> 13); 1217 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1218 first_prio, 1219 ntohs(ib_spec->eth.val.vlan_tag) >> 13); 1220 } 1221 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1222 ethertype, ntohs(ib_spec->eth.mask.ether_type)); 1223 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1224 ethertype, ntohs(ib_spec->eth.val.ether_type)); 1225 break; 1226 case IB_FLOW_SPEC_IPV4: 1227 if (ib_spec->size != sizeof(ib_spec->ipv4)) 1228 return -EINVAL; 1229 1230 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1231 ethertype, 0xffff); 1232 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1233 ethertype, ETH_P_IP); 1234 1235 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1236 src_ipv4_src_ipv6.ipv4_layout.ipv4), 1237 &ib_spec->ipv4.mask.src_ip, 1238 sizeof(ib_spec->ipv4.mask.src_ip)); 1239 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1240 src_ipv4_src_ipv6.ipv4_layout.ipv4), 1241 &ib_spec->ipv4.val.src_ip, 1242 sizeof(ib_spec->ipv4.val.src_ip)); 1243 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1244 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 1245 &ib_spec->ipv4.mask.dst_ip, 1246 sizeof(ib_spec->ipv4.mask.dst_ip)); 1247 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1248 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 1249 &ib_spec->ipv4.val.dst_ip, 1250 sizeof(ib_spec->ipv4.val.dst_ip)); 1251 break; 1252 case IB_FLOW_SPEC_TCP: 1253 if (ib_spec->size != sizeof(ib_spec->tcp_udp)) 1254 return -EINVAL; 1255 1256 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol, 1257 0xff); 1258 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol, 1259 IPPROTO_TCP); 1260 1261 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_sport, 1262 ntohs(ib_spec->tcp_udp.mask.src_port)); 1263 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_sport, 1264 ntohs(ib_spec->tcp_udp.val.src_port)); 1265 1266 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_dport, 1267 ntohs(ib_spec->tcp_udp.mask.dst_port)); 1268 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_dport, 1269 ntohs(ib_spec->tcp_udp.val.dst_port)); 1270 break; 1271 case IB_FLOW_SPEC_UDP: 1272 if (ib_spec->size != sizeof(ib_spec->tcp_udp)) 1273 return -EINVAL; 1274 1275 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol, 1276 0xff); 1277 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol, 1278 IPPROTO_UDP); 1279 1280 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_sport, 1281 ntohs(ib_spec->tcp_udp.mask.src_port)); 1282 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_sport, 1283 ntohs(ib_spec->tcp_udp.val.src_port)); 1284 1285 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_dport, 1286 ntohs(ib_spec->tcp_udp.mask.dst_port)); 1287 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_dport, 1288 ntohs(ib_spec->tcp_udp.val.dst_port)); 1289 break; 1290 default: 1291 return -EINVAL; 1292 } 1293 1294 return 0; 1295 } 1296 1297 /* If a flow could catch both multicast and unicast packets, 1298 * it won't fall into the multicast flow steering table and this rule 1299 * could steal other multicast packets. 1300 */ 1301 static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr) 1302 { 1303 struct ib_flow_spec_eth *eth_spec; 1304 1305 if (ib_attr->type != IB_FLOW_ATTR_NORMAL || 1306 ib_attr->size < sizeof(struct ib_flow_attr) + 1307 sizeof(struct ib_flow_spec_eth) || 1308 ib_attr->num_of_specs < 1) 1309 return false; 1310 1311 eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1); 1312 if (eth_spec->type != IB_FLOW_SPEC_ETH || 1313 eth_spec->size != sizeof(*eth_spec)) 1314 return false; 1315 1316 return is_multicast_ether_addr(eth_spec->mask.dst_mac) && 1317 is_multicast_ether_addr(eth_spec->val.dst_mac); 1318 } 1319 1320 static bool is_valid_attr(struct ib_flow_attr *flow_attr) 1321 { 1322 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1); 1323 bool has_ipv4_spec = false; 1324 bool eth_type_ipv4 = true; 1325 unsigned int spec_index; 1326 1327 /* Validate that ethertype is correct */ 1328 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 1329 if (ib_spec->type == IB_FLOW_SPEC_ETH && 1330 ib_spec->eth.mask.ether_type) { 1331 if (!((ib_spec->eth.mask.ether_type == htons(0xffff)) && 1332 ib_spec->eth.val.ether_type == htons(ETH_P_IP))) 1333 eth_type_ipv4 = false; 1334 } else if (ib_spec->type == IB_FLOW_SPEC_IPV4) { 1335 has_ipv4_spec = true; 1336 } 1337 ib_spec = (void *)ib_spec + ib_spec->size; 1338 } 1339 return !has_ipv4_spec || eth_type_ipv4; 1340 } 1341 1342 static void put_flow_table(struct mlx5_ib_dev *dev, 1343 struct mlx5_ib_flow_prio *prio, bool ft_added) 1344 { 1345 prio->refcount -= !!ft_added; 1346 if (!prio->refcount) { 1347 mlx5_destroy_flow_table(prio->flow_table); 1348 prio->flow_table = NULL; 1349 } 1350 } 1351 1352 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id) 1353 { 1354 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device); 1355 struct mlx5_ib_flow_handler *handler = container_of(flow_id, 1356 struct mlx5_ib_flow_handler, 1357 ibflow); 1358 struct mlx5_ib_flow_handler *iter, *tmp; 1359 1360 mutex_lock(&dev->flow_db.lock); 1361 1362 list_for_each_entry_safe(iter, tmp, &handler->list, list) { 1363 mlx5_del_flow_rule(iter->rule); 1364 list_del(&iter->list); 1365 kfree(iter); 1366 } 1367 1368 mlx5_del_flow_rule(handler->rule); 1369 put_flow_table(dev, &dev->flow_db.prios[handler->prio], true); 1370 mutex_unlock(&dev->flow_db.lock); 1371 1372 kfree(handler); 1373 1374 return 0; 1375 } 1376 1377 #define MLX5_FS_MAX_TYPES 10 1378 #define MLX5_FS_MAX_ENTRIES 32000UL 1379 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev, 1380 struct ib_flow_attr *flow_attr) 1381 { 1382 struct mlx5_flow_namespace *ns = NULL; 1383 struct mlx5_ib_flow_prio *prio; 1384 struct mlx5_flow_table *ft; 1385 int num_entries; 1386 int num_groups; 1387 int priority; 1388 int err = 0; 1389 1390 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 1391 if (flow_is_multicast_only(flow_attr)) 1392 priority = MLX5_IB_FLOW_MCAST_PRIO; 1393 else 1394 priority = flow_attr->priority; 1395 ns = mlx5_get_flow_namespace(dev->mdev, 1396 MLX5_FLOW_NAMESPACE_BYPASS); 1397 num_entries = MLX5_FS_MAX_ENTRIES; 1398 num_groups = MLX5_FS_MAX_TYPES; 1399 prio = &dev->flow_db.prios[priority]; 1400 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 1401 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 1402 ns = mlx5_get_flow_namespace(dev->mdev, 1403 MLX5_FLOW_NAMESPACE_LEFTOVERS); 1404 build_leftovers_ft_param(&priority, 1405 &num_entries, 1406 &num_groups); 1407 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO]; 1408 } 1409 1410 if (!ns) 1411 return ERR_PTR(-ENOTSUPP); 1412 1413 ft = prio->flow_table; 1414 if (!ft) { 1415 ft = mlx5_create_auto_grouped_flow_table(ns, priority, 1416 num_entries, 1417 num_groups); 1418 1419 if (!IS_ERR(ft)) { 1420 prio->refcount = 0; 1421 prio->flow_table = ft; 1422 } else { 1423 err = PTR_ERR(ft); 1424 } 1425 } 1426 1427 return err ? ERR_PTR(err) : prio; 1428 } 1429 1430 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev, 1431 struct mlx5_ib_flow_prio *ft_prio, 1432 struct ib_flow_attr *flow_attr, 1433 struct mlx5_flow_destination *dst) 1434 { 1435 struct mlx5_flow_table *ft = ft_prio->flow_table; 1436 struct mlx5_ib_flow_handler *handler; 1437 void *ib_flow = flow_attr + 1; 1438 u8 match_criteria_enable = 0; 1439 unsigned int spec_index; 1440 u32 *match_c; 1441 u32 *match_v; 1442 int err = 0; 1443 1444 if (!is_valid_attr(flow_attr)) 1445 return ERR_PTR(-EINVAL); 1446 1447 match_c = kzalloc(MLX5_ST_SZ_BYTES(fte_match_param), GFP_KERNEL); 1448 match_v = kzalloc(MLX5_ST_SZ_BYTES(fte_match_param), GFP_KERNEL); 1449 handler = kzalloc(sizeof(*handler), GFP_KERNEL); 1450 if (!handler || !match_c || !match_v) { 1451 err = -ENOMEM; 1452 goto free; 1453 } 1454 1455 INIT_LIST_HEAD(&handler->list); 1456 1457 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 1458 err = parse_flow_attr(match_c, match_v, ib_flow); 1459 if (err < 0) 1460 goto free; 1461 1462 ib_flow += ((union ib_flow_spec *)ib_flow)->size; 1463 } 1464 1465 /* Outer header support only */ 1466 match_criteria_enable = (!outer_header_zero(match_c)) << 0; 1467 handler->rule = mlx5_add_flow_rule(ft, match_criteria_enable, 1468 match_c, match_v, 1469 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST, 1470 MLX5_FS_DEFAULT_FLOW_TAG, 1471 dst); 1472 1473 if (IS_ERR(handler->rule)) { 1474 err = PTR_ERR(handler->rule); 1475 goto free; 1476 } 1477 1478 handler->prio = ft_prio - dev->flow_db.prios; 1479 1480 ft_prio->flow_table = ft; 1481 free: 1482 if (err) 1483 kfree(handler); 1484 kfree(match_c); 1485 kfree(match_v); 1486 return err ? ERR_PTR(err) : handler; 1487 } 1488 1489 enum { 1490 LEFTOVERS_MC, 1491 LEFTOVERS_UC, 1492 }; 1493 1494 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev, 1495 struct mlx5_ib_flow_prio *ft_prio, 1496 struct ib_flow_attr *flow_attr, 1497 struct mlx5_flow_destination *dst) 1498 { 1499 struct mlx5_ib_flow_handler *handler_ucast = NULL; 1500 struct mlx5_ib_flow_handler *handler = NULL; 1501 1502 static struct { 1503 struct ib_flow_attr flow_attr; 1504 struct ib_flow_spec_eth eth_flow; 1505 } leftovers_specs[] = { 1506 [LEFTOVERS_MC] = { 1507 .flow_attr = { 1508 .num_of_specs = 1, 1509 .size = sizeof(leftovers_specs[0]) 1510 }, 1511 .eth_flow = { 1512 .type = IB_FLOW_SPEC_ETH, 1513 .size = sizeof(struct ib_flow_spec_eth), 1514 .mask = {.dst_mac = {0x1} }, 1515 .val = {.dst_mac = {0x1} } 1516 } 1517 }, 1518 [LEFTOVERS_UC] = { 1519 .flow_attr = { 1520 .num_of_specs = 1, 1521 .size = sizeof(leftovers_specs[0]) 1522 }, 1523 .eth_flow = { 1524 .type = IB_FLOW_SPEC_ETH, 1525 .size = sizeof(struct ib_flow_spec_eth), 1526 .mask = {.dst_mac = {0x1} }, 1527 .val = {.dst_mac = {} } 1528 } 1529 } 1530 }; 1531 1532 handler = create_flow_rule(dev, ft_prio, 1533 &leftovers_specs[LEFTOVERS_MC].flow_attr, 1534 dst); 1535 if (!IS_ERR(handler) && 1536 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) { 1537 handler_ucast = create_flow_rule(dev, ft_prio, 1538 &leftovers_specs[LEFTOVERS_UC].flow_attr, 1539 dst); 1540 if (IS_ERR(handler_ucast)) { 1541 kfree(handler); 1542 handler = handler_ucast; 1543 } else { 1544 list_add(&handler_ucast->list, &handler->list); 1545 } 1546 } 1547 1548 return handler; 1549 } 1550 1551 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp, 1552 struct ib_flow_attr *flow_attr, 1553 int domain) 1554 { 1555 struct mlx5_ib_dev *dev = to_mdev(qp->device); 1556 struct mlx5_ib_flow_handler *handler = NULL; 1557 struct mlx5_flow_destination *dst = NULL; 1558 struct mlx5_ib_flow_prio *ft_prio; 1559 int err; 1560 1561 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) 1562 return ERR_PTR(-ENOSPC); 1563 1564 if (domain != IB_FLOW_DOMAIN_USER || 1565 flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) || 1566 flow_attr->flags) 1567 return ERR_PTR(-EINVAL); 1568 1569 dst = kzalloc(sizeof(*dst), GFP_KERNEL); 1570 if (!dst) 1571 return ERR_PTR(-ENOMEM); 1572 1573 mutex_lock(&dev->flow_db.lock); 1574 1575 ft_prio = get_flow_table(dev, flow_attr); 1576 if (IS_ERR(ft_prio)) { 1577 err = PTR_ERR(ft_prio); 1578 goto unlock; 1579 } 1580 1581 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR; 1582 dst->tir_num = to_mqp(qp)->raw_packet_qp.rq.tirn; 1583 1584 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 1585 handler = create_flow_rule(dev, ft_prio, flow_attr, 1586 dst); 1587 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 1588 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 1589 handler = create_leftovers_rule(dev, ft_prio, flow_attr, 1590 dst); 1591 } else { 1592 err = -EINVAL; 1593 goto destroy_ft; 1594 } 1595 1596 if (IS_ERR(handler)) { 1597 err = PTR_ERR(handler); 1598 handler = NULL; 1599 goto destroy_ft; 1600 } 1601 1602 ft_prio->refcount++; 1603 mutex_unlock(&dev->flow_db.lock); 1604 kfree(dst); 1605 1606 return &handler->ibflow; 1607 1608 destroy_ft: 1609 put_flow_table(dev, ft_prio, false); 1610 unlock: 1611 mutex_unlock(&dev->flow_db.lock); 1612 kfree(dst); 1613 kfree(handler); 1614 return ERR_PTR(err); 1615 } 1616 1617 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 1618 { 1619 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 1620 int err; 1621 1622 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num); 1623 if (err) 1624 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 1625 ibqp->qp_num, gid->raw); 1626 1627 return err; 1628 } 1629 1630 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 1631 { 1632 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 1633 int err; 1634 1635 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num); 1636 if (err) 1637 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 1638 ibqp->qp_num, gid->raw); 1639 1640 return err; 1641 } 1642 1643 static int init_node_data(struct mlx5_ib_dev *dev) 1644 { 1645 int err; 1646 1647 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 1648 if (err) 1649 return err; 1650 1651 dev->mdev->rev_id = dev->mdev->pdev->revision; 1652 1653 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 1654 } 1655 1656 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr, 1657 char *buf) 1658 { 1659 struct mlx5_ib_dev *dev = 1660 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 1661 1662 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages); 1663 } 1664 1665 static ssize_t show_reg_pages(struct device *device, 1666 struct device_attribute *attr, char *buf) 1667 { 1668 struct mlx5_ib_dev *dev = 1669 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 1670 1671 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 1672 } 1673 1674 static ssize_t show_hca(struct device *device, struct device_attribute *attr, 1675 char *buf) 1676 { 1677 struct mlx5_ib_dev *dev = 1678 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 1679 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device); 1680 } 1681 1682 static ssize_t show_fw_ver(struct device *device, struct device_attribute *attr, 1683 char *buf) 1684 { 1685 struct mlx5_ib_dev *dev = 1686 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 1687 return sprintf(buf, "%d.%d.%d\n", fw_rev_maj(dev->mdev), 1688 fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev)); 1689 } 1690 1691 static ssize_t show_rev(struct device *device, struct device_attribute *attr, 1692 char *buf) 1693 { 1694 struct mlx5_ib_dev *dev = 1695 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 1696 return sprintf(buf, "%x\n", dev->mdev->rev_id); 1697 } 1698 1699 static ssize_t show_board(struct device *device, struct device_attribute *attr, 1700 char *buf) 1701 { 1702 struct mlx5_ib_dev *dev = 1703 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 1704 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 1705 dev->mdev->board_id); 1706 } 1707 1708 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL); 1709 static DEVICE_ATTR(fw_ver, S_IRUGO, show_fw_ver, NULL); 1710 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL); 1711 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL); 1712 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL); 1713 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL); 1714 1715 static struct device_attribute *mlx5_class_attributes[] = { 1716 &dev_attr_hw_rev, 1717 &dev_attr_fw_ver, 1718 &dev_attr_hca_type, 1719 &dev_attr_board_id, 1720 &dev_attr_fw_pages, 1721 &dev_attr_reg_pages, 1722 }; 1723 1724 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context, 1725 enum mlx5_dev_event event, unsigned long param) 1726 { 1727 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context; 1728 struct ib_event ibev; 1729 1730 u8 port = 0; 1731 1732 switch (event) { 1733 case MLX5_DEV_EVENT_SYS_ERROR: 1734 ibdev->ib_active = false; 1735 ibev.event = IB_EVENT_DEVICE_FATAL; 1736 break; 1737 1738 case MLX5_DEV_EVENT_PORT_UP: 1739 ibev.event = IB_EVENT_PORT_ACTIVE; 1740 port = (u8)param; 1741 break; 1742 1743 case MLX5_DEV_EVENT_PORT_DOWN: 1744 ibev.event = IB_EVENT_PORT_ERR; 1745 port = (u8)param; 1746 break; 1747 1748 case MLX5_DEV_EVENT_PORT_INITIALIZED: 1749 /* not used by ULPs */ 1750 return; 1751 1752 case MLX5_DEV_EVENT_LID_CHANGE: 1753 ibev.event = IB_EVENT_LID_CHANGE; 1754 port = (u8)param; 1755 break; 1756 1757 case MLX5_DEV_EVENT_PKEY_CHANGE: 1758 ibev.event = IB_EVENT_PKEY_CHANGE; 1759 port = (u8)param; 1760 break; 1761 1762 case MLX5_DEV_EVENT_GUID_CHANGE: 1763 ibev.event = IB_EVENT_GID_CHANGE; 1764 port = (u8)param; 1765 break; 1766 1767 case MLX5_DEV_EVENT_CLIENT_REREG: 1768 ibev.event = IB_EVENT_CLIENT_REREGISTER; 1769 port = (u8)param; 1770 break; 1771 } 1772 1773 ibev.device = &ibdev->ib_dev; 1774 ibev.element.port_num = port; 1775 1776 if (port < 1 || port > ibdev->num_ports) { 1777 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port); 1778 return; 1779 } 1780 1781 if (ibdev->ib_active) 1782 ib_dispatch_event(&ibev); 1783 } 1784 1785 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 1786 { 1787 int port; 1788 1789 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) 1790 mlx5_query_ext_port_caps(dev, port); 1791 } 1792 1793 static int get_port_caps(struct mlx5_ib_dev *dev) 1794 { 1795 struct ib_device_attr *dprops = NULL; 1796 struct ib_port_attr *pprops = NULL; 1797 int err = -ENOMEM; 1798 int port; 1799 struct ib_udata uhw = {.inlen = 0, .outlen = 0}; 1800 1801 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL); 1802 if (!pprops) 1803 goto out; 1804 1805 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL); 1806 if (!dprops) 1807 goto out; 1808 1809 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw); 1810 if (err) { 1811 mlx5_ib_warn(dev, "query_device failed %d\n", err); 1812 goto out; 1813 } 1814 1815 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) { 1816 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops); 1817 if (err) { 1818 mlx5_ib_warn(dev, "query_port %d failed %d\n", 1819 port, err); 1820 break; 1821 } 1822 dev->mdev->port_caps[port - 1].pkey_table_len = 1823 dprops->max_pkeys; 1824 dev->mdev->port_caps[port - 1].gid_table_len = 1825 pprops->gid_tbl_len; 1826 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n", 1827 dprops->max_pkeys, pprops->gid_tbl_len); 1828 } 1829 1830 out: 1831 kfree(pprops); 1832 kfree(dprops); 1833 1834 return err; 1835 } 1836 1837 static void destroy_umrc_res(struct mlx5_ib_dev *dev) 1838 { 1839 int err; 1840 1841 err = mlx5_mr_cache_cleanup(dev); 1842 if (err) 1843 mlx5_ib_warn(dev, "mr cache cleanup failed\n"); 1844 1845 mlx5_ib_destroy_qp(dev->umrc.qp); 1846 ib_destroy_cq(dev->umrc.cq); 1847 ib_dealloc_pd(dev->umrc.pd); 1848 } 1849 1850 enum { 1851 MAX_UMR_WR = 128, 1852 }; 1853 1854 static int create_umr_res(struct mlx5_ib_dev *dev) 1855 { 1856 struct ib_qp_init_attr *init_attr = NULL; 1857 struct ib_qp_attr *attr = NULL; 1858 struct ib_pd *pd; 1859 struct ib_cq *cq; 1860 struct ib_qp *qp; 1861 struct ib_cq_init_attr cq_attr = {}; 1862 int ret; 1863 1864 attr = kzalloc(sizeof(*attr), GFP_KERNEL); 1865 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL); 1866 if (!attr || !init_attr) { 1867 ret = -ENOMEM; 1868 goto error_0; 1869 } 1870 1871 pd = ib_alloc_pd(&dev->ib_dev); 1872 if (IS_ERR(pd)) { 1873 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n"); 1874 ret = PTR_ERR(pd); 1875 goto error_0; 1876 } 1877 1878 cq_attr.cqe = 128; 1879 cq = ib_create_cq(&dev->ib_dev, mlx5_umr_cq_handler, NULL, NULL, 1880 &cq_attr); 1881 if (IS_ERR(cq)) { 1882 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n"); 1883 ret = PTR_ERR(cq); 1884 goto error_2; 1885 } 1886 ib_req_notify_cq(cq, IB_CQ_NEXT_COMP); 1887 1888 init_attr->send_cq = cq; 1889 init_attr->recv_cq = cq; 1890 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR; 1891 init_attr->cap.max_send_wr = MAX_UMR_WR; 1892 init_attr->cap.max_send_sge = 1; 1893 init_attr->qp_type = MLX5_IB_QPT_REG_UMR; 1894 init_attr->port_num = 1; 1895 qp = mlx5_ib_create_qp(pd, init_attr, NULL); 1896 if (IS_ERR(qp)) { 1897 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n"); 1898 ret = PTR_ERR(qp); 1899 goto error_3; 1900 } 1901 qp->device = &dev->ib_dev; 1902 qp->real_qp = qp; 1903 qp->uobject = NULL; 1904 qp->qp_type = MLX5_IB_QPT_REG_UMR; 1905 1906 attr->qp_state = IB_QPS_INIT; 1907 attr->port_num = 1; 1908 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX | 1909 IB_QP_PORT, NULL); 1910 if (ret) { 1911 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n"); 1912 goto error_4; 1913 } 1914 1915 memset(attr, 0, sizeof(*attr)); 1916 attr->qp_state = IB_QPS_RTR; 1917 attr->path_mtu = IB_MTU_256; 1918 1919 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 1920 if (ret) { 1921 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n"); 1922 goto error_4; 1923 } 1924 1925 memset(attr, 0, sizeof(*attr)); 1926 attr->qp_state = IB_QPS_RTS; 1927 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 1928 if (ret) { 1929 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n"); 1930 goto error_4; 1931 } 1932 1933 dev->umrc.qp = qp; 1934 dev->umrc.cq = cq; 1935 dev->umrc.pd = pd; 1936 1937 sema_init(&dev->umrc.sem, MAX_UMR_WR); 1938 ret = mlx5_mr_cache_init(dev); 1939 if (ret) { 1940 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 1941 goto error_4; 1942 } 1943 1944 kfree(attr); 1945 kfree(init_attr); 1946 1947 return 0; 1948 1949 error_4: 1950 mlx5_ib_destroy_qp(qp); 1951 1952 error_3: 1953 ib_destroy_cq(cq); 1954 1955 error_2: 1956 ib_dealloc_pd(pd); 1957 1958 error_0: 1959 kfree(attr); 1960 kfree(init_attr); 1961 return ret; 1962 } 1963 1964 static int create_dev_resources(struct mlx5_ib_resources *devr) 1965 { 1966 struct ib_srq_init_attr attr; 1967 struct mlx5_ib_dev *dev; 1968 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 1969 int ret = 0; 1970 1971 dev = container_of(devr, struct mlx5_ib_dev, devr); 1972 1973 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL); 1974 if (IS_ERR(devr->p0)) { 1975 ret = PTR_ERR(devr->p0); 1976 goto error0; 1977 } 1978 devr->p0->device = &dev->ib_dev; 1979 devr->p0->uobject = NULL; 1980 atomic_set(&devr->p0->usecnt, 0); 1981 1982 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL); 1983 if (IS_ERR(devr->c0)) { 1984 ret = PTR_ERR(devr->c0); 1985 goto error1; 1986 } 1987 devr->c0->device = &dev->ib_dev; 1988 devr->c0->uobject = NULL; 1989 devr->c0->comp_handler = NULL; 1990 devr->c0->event_handler = NULL; 1991 devr->c0->cq_context = NULL; 1992 atomic_set(&devr->c0->usecnt, 0); 1993 1994 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 1995 if (IS_ERR(devr->x0)) { 1996 ret = PTR_ERR(devr->x0); 1997 goto error2; 1998 } 1999 devr->x0->device = &dev->ib_dev; 2000 devr->x0->inode = NULL; 2001 atomic_set(&devr->x0->usecnt, 0); 2002 mutex_init(&devr->x0->tgt_qp_mutex); 2003 INIT_LIST_HEAD(&devr->x0->tgt_qp_list); 2004 2005 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 2006 if (IS_ERR(devr->x1)) { 2007 ret = PTR_ERR(devr->x1); 2008 goto error3; 2009 } 2010 devr->x1->device = &dev->ib_dev; 2011 devr->x1->inode = NULL; 2012 atomic_set(&devr->x1->usecnt, 0); 2013 mutex_init(&devr->x1->tgt_qp_mutex); 2014 INIT_LIST_HEAD(&devr->x1->tgt_qp_list); 2015 2016 memset(&attr, 0, sizeof(attr)); 2017 attr.attr.max_sge = 1; 2018 attr.attr.max_wr = 1; 2019 attr.srq_type = IB_SRQT_XRC; 2020 attr.ext.xrc.cq = devr->c0; 2021 attr.ext.xrc.xrcd = devr->x0; 2022 2023 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 2024 if (IS_ERR(devr->s0)) { 2025 ret = PTR_ERR(devr->s0); 2026 goto error4; 2027 } 2028 devr->s0->device = &dev->ib_dev; 2029 devr->s0->pd = devr->p0; 2030 devr->s0->uobject = NULL; 2031 devr->s0->event_handler = NULL; 2032 devr->s0->srq_context = NULL; 2033 devr->s0->srq_type = IB_SRQT_XRC; 2034 devr->s0->ext.xrc.xrcd = devr->x0; 2035 devr->s0->ext.xrc.cq = devr->c0; 2036 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt); 2037 atomic_inc(&devr->s0->ext.xrc.cq->usecnt); 2038 atomic_inc(&devr->p0->usecnt); 2039 atomic_set(&devr->s0->usecnt, 0); 2040 2041 memset(&attr, 0, sizeof(attr)); 2042 attr.attr.max_sge = 1; 2043 attr.attr.max_wr = 1; 2044 attr.srq_type = IB_SRQT_BASIC; 2045 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 2046 if (IS_ERR(devr->s1)) { 2047 ret = PTR_ERR(devr->s1); 2048 goto error5; 2049 } 2050 devr->s1->device = &dev->ib_dev; 2051 devr->s1->pd = devr->p0; 2052 devr->s1->uobject = NULL; 2053 devr->s1->event_handler = NULL; 2054 devr->s1->srq_context = NULL; 2055 devr->s1->srq_type = IB_SRQT_BASIC; 2056 devr->s1->ext.xrc.cq = devr->c0; 2057 atomic_inc(&devr->p0->usecnt); 2058 atomic_set(&devr->s0->usecnt, 0); 2059 2060 return 0; 2061 2062 error5: 2063 mlx5_ib_destroy_srq(devr->s0); 2064 error4: 2065 mlx5_ib_dealloc_xrcd(devr->x1); 2066 error3: 2067 mlx5_ib_dealloc_xrcd(devr->x0); 2068 error2: 2069 mlx5_ib_destroy_cq(devr->c0); 2070 error1: 2071 mlx5_ib_dealloc_pd(devr->p0); 2072 error0: 2073 return ret; 2074 } 2075 2076 static void destroy_dev_resources(struct mlx5_ib_resources *devr) 2077 { 2078 mlx5_ib_destroy_srq(devr->s1); 2079 mlx5_ib_destroy_srq(devr->s0); 2080 mlx5_ib_dealloc_xrcd(devr->x0); 2081 mlx5_ib_dealloc_xrcd(devr->x1); 2082 mlx5_ib_destroy_cq(devr->c0); 2083 mlx5_ib_dealloc_pd(devr->p0); 2084 } 2085 2086 static u32 get_core_cap_flags(struct ib_device *ibdev) 2087 { 2088 struct mlx5_ib_dev *dev = to_mdev(ibdev); 2089 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 2090 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 2091 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 2092 u32 ret = 0; 2093 2094 if (ll == IB_LINK_LAYER_INFINIBAND) 2095 return RDMA_CORE_PORT_IBA_IB; 2096 2097 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 2098 return 0; 2099 2100 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 2101 return 0; 2102 2103 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 2104 ret |= RDMA_CORE_PORT_IBA_ROCE; 2105 2106 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 2107 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 2108 2109 return ret; 2110 } 2111 2112 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num, 2113 struct ib_port_immutable *immutable) 2114 { 2115 struct ib_port_attr attr; 2116 int err; 2117 2118 err = mlx5_ib_query_port(ibdev, port_num, &attr); 2119 if (err) 2120 return err; 2121 2122 immutable->pkey_tbl_len = attr.pkey_tbl_len; 2123 immutable->gid_tbl_len = attr.gid_tbl_len; 2124 immutable->core_cap_flags = get_core_cap_flags(ibdev); 2125 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 2126 2127 return 0; 2128 } 2129 2130 static int mlx5_enable_roce(struct mlx5_ib_dev *dev) 2131 { 2132 int err; 2133 2134 dev->roce.nb.notifier_call = mlx5_netdev_event; 2135 err = register_netdevice_notifier(&dev->roce.nb); 2136 if (err) 2137 return err; 2138 2139 err = mlx5_nic_vport_enable_roce(dev->mdev); 2140 if (err) 2141 goto err_unregister_netdevice_notifier; 2142 2143 return 0; 2144 2145 err_unregister_netdevice_notifier: 2146 unregister_netdevice_notifier(&dev->roce.nb); 2147 return err; 2148 } 2149 2150 static void mlx5_disable_roce(struct mlx5_ib_dev *dev) 2151 { 2152 mlx5_nic_vport_disable_roce(dev->mdev); 2153 unregister_netdevice_notifier(&dev->roce.nb); 2154 } 2155 2156 static void *mlx5_ib_add(struct mlx5_core_dev *mdev) 2157 { 2158 struct mlx5_ib_dev *dev; 2159 enum rdma_link_layer ll; 2160 int port_type_cap; 2161 int err; 2162 int i; 2163 2164 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 2165 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 2166 2167 if ((ll == IB_LINK_LAYER_ETHERNET) && !MLX5_CAP_GEN(mdev, roce)) 2168 return NULL; 2169 2170 printk_once(KERN_INFO "%s", mlx5_version); 2171 2172 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev)); 2173 if (!dev) 2174 return NULL; 2175 2176 dev->mdev = mdev; 2177 2178 rwlock_init(&dev->roce.netdev_lock); 2179 err = get_port_caps(dev); 2180 if (err) 2181 goto err_dealloc; 2182 2183 if (mlx5_use_mad_ifc(dev)) 2184 get_ext_port_caps(dev); 2185 2186 MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock); 2187 2188 strlcpy(dev->ib_dev.name, "mlx5_%d", IB_DEVICE_NAME_MAX); 2189 dev->ib_dev.owner = THIS_MODULE; 2190 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 2191 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 2192 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports); 2193 dev->ib_dev.phys_port_cnt = dev->num_ports; 2194 dev->ib_dev.num_comp_vectors = 2195 dev->mdev->priv.eq_table.num_comp_vectors; 2196 dev->ib_dev.dma_device = &mdev->pdev->dev; 2197 2198 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION; 2199 dev->ib_dev.uverbs_cmd_mask = 2200 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | 2201 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | 2202 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | 2203 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | 2204 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | 2205 (1ull << IB_USER_VERBS_CMD_REG_MR) | 2206 (1ull << IB_USER_VERBS_CMD_DEREG_MR) | 2207 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 2208 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | 2209 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) | 2210 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | 2211 (1ull << IB_USER_VERBS_CMD_CREATE_QP) | 2212 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | 2213 (1ull << IB_USER_VERBS_CMD_QUERY_QP) | 2214 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | 2215 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) | 2216 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) | 2217 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | 2218 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | 2219 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | 2220 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | 2221 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) | 2222 (1ull << IB_USER_VERBS_CMD_OPEN_QP); 2223 dev->ib_dev.uverbs_ex_cmd_mask = 2224 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) | 2225 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) | 2226 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP); 2227 2228 dev->ib_dev.query_device = mlx5_ib_query_device; 2229 dev->ib_dev.query_port = mlx5_ib_query_port; 2230 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer; 2231 if (ll == IB_LINK_LAYER_ETHERNET) 2232 dev->ib_dev.get_netdev = mlx5_ib_get_netdev; 2233 dev->ib_dev.query_gid = mlx5_ib_query_gid; 2234 dev->ib_dev.add_gid = mlx5_ib_add_gid; 2235 dev->ib_dev.del_gid = mlx5_ib_del_gid; 2236 dev->ib_dev.query_pkey = mlx5_ib_query_pkey; 2237 dev->ib_dev.modify_device = mlx5_ib_modify_device; 2238 dev->ib_dev.modify_port = mlx5_ib_modify_port; 2239 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext; 2240 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext; 2241 dev->ib_dev.mmap = mlx5_ib_mmap; 2242 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd; 2243 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd; 2244 dev->ib_dev.create_ah = mlx5_ib_create_ah; 2245 dev->ib_dev.query_ah = mlx5_ib_query_ah; 2246 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah; 2247 dev->ib_dev.create_srq = mlx5_ib_create_srq; 2248 dev->ib_dev.modify_srq = mlx5_ib_modify_srq; 2249 dev->ib_dev.query_srq = mlx5_ib_query_srq; 2250 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq; 2251 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv; 2252 dev->ib_dev.create_qp = mlx5_ib_create_qp; 2253 dev->ib_dev.modify_qp = mlx5_ib_modify_qp; 2254 dev->ib_dev.query_qp = mlx5_ib_query_qp; 2255 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp; 2256 dev->ib_dev.post_send = mlx5_ib_post_send; 2257 dev->ib_dev.post_recv = mlx5_ib_post_recv; 2258 dev->ib_dev.create_cq = mlx5_ib_create_cq; 2259 dev->ib_dev.modify_cq = mlx5_ib_modify_cq; 2260 dev->ib_dev.resize_cq = mlx5_ib_resize_cq; 2261 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq; 2262 dev->ib_dev.poll_cq = mlx5_ib_poll_cq; 2263 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq; 2264 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr; 2265 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr; 2266 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr; 2267 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach; 2268 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach; 2269 dev->ib_dev.process_mad = mlx5_ib_process_mad; 2270 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr; 2271 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg; 2272 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status; 2273 dev->ib_dev.get_port_immutable = mlx5_port_immutable; 2274 2275 mlx5_ib_internal_fill_odp_caps(dev); 2276 2277 if (MLX5_CAP_GEN(mdev, xrc)) { 2278 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd; 2279 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd; 2280 dev->ib_dev.uverbs_cmd_mask |= 2281 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) | 2282 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD); 2283 } 2284 2285 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) == 2286 IB_LINK_LAYER_ETHERNET) { 2287 dev->ib_dev.create_flow = mlx5_ib_create_flow; 2288 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow; 2289 dev->ib_dev.uverbs_ex_cmd_mask |= 2290 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) | 2291 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW); 2292 } 2293 err = init_node_data(dev); 2294 if (err) 2295 goto err_dealloc; 2296 2297 mutex_init(&dev->flow_db.lock); 2298 mutex_init(&dev->cap_mask_mutex); 2299 2300 if (ll == IB_LINK_LAYER_ETHERNET) { 2301 err = mlx5_enable_roce(dev); 2302 if (err) 2303 goto err_dealloc; 2304 } 2305 2306 err = create_dev_resources(&dev->devr); 2307 if (err) 2308 goto err_disable_roce; 2309 2310 err = mlx5_ib_odp_init_one(dev); 2311 if (err) 2312 goto err_rsrc; 2313 2314 err = ib_register_device(&dev->ib_dev, NULL); 2315 if (err) 2316 goto err_odp; 2317 2318 err = create_umr_res(dev); 2319 if (err) 2320 goto err_dev; 2321 2322 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) { 2323 err = device_create_file(&dev->ib_dev.dev, 2324 mlx5_class_attributes[i]); 2325 if (err) 2326 goto err_umrc; 2327 } 2328 2329 dev->ib_active = true; 2330 2331 return dev; 2332 2333 err_umrc: 2334 destroy_umrc_res(dev); 2335 2336 err_dev: 2337 ib_unregister_device(&dev->ib_dev); 2338 2339 err_odp: 2340 mlx5_ib_odp_remove_one(dev); 2341 2342 err_rsrc: 2343 destroy_dev_resources(&dev->devr); 2344 2345 err_disable_roce: 2346 if (ll == IB_LINK_LAYER_ETHERNET) 2347 mlx5_disable_roce(dev); 2348 2349 err_dealloc: 2350 ib_dealloc_device((struct ib_device *)dev); 2351 2352 return NULL; 2353 } 2354 2355 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context) 2356 { 2357 struct mlx5_ib_dev *dev = context; 2358 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1); 2359 2360 ib_unregister_device(&dev->ib_dev); 2361 destroy_umrc_res(dev); 2362 mlx5_ib_odp_remove_one(dev); 2363 destroy_dev_resources(&dev->devr); 2364 if (ll == IB_LINK_LAYER_ETHERNET) 2365 mlx5_disable_roce(dev); 2366 ib_dealloc_device(&dev->ib_dev); 2367 } 2368 2369 static struct mlx5_interface mlx5_ib_interface = { 2370 .add = mlx5_ib_add, 2371 .remove = mlx5_ib_remove, 2372 .event = mlx5_ib_event, 2373 .protocol = MLX5_INTERFACE_PROTOCOL_IB, 2374 }; 2375 2376 static int __init mlx5_ib_init(void) 2377 { 2378 int err; 2379 2380 if (deprecated_prof_sel != 2) 2381 pr_warn("prof_sel is deprecated for mlx5_ib, set it for mlx5_core\n"); 2382 2383 err = mlx5_ib_odp_init(); 2384 if (err) 2385 return err; 2386 2387 err = mlx5_register_interface(&mlx5_ib_interface); 2388 if (err) 2389 goto clean_odp; 2390 2391 return err; 2392 2393 clean_odp: 2394 mlx5_ib_odp_cleanup(); 2395 return err; 2396 } 2397 2398 static void __exit mlx5_ib_cleanup(void) 2399 { 2400 mlx5_unregister_interface(&mlx5_ib_interface); 2401 mlx5_ib_odp_cleanup(); 2402 } 2403 2404 module_init(mlx5_ib_init); 2405 module_exit(mlx5_ib_cleanup); 2406