1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/highmem.h> 34 #include <linux/module.h> 35 #include <linux/init.h> 36 #include <linux/errno.h> 37 #include <linux/pci.h> 38 #include <linux/dma-mapping.h> 39 #include <linux/slab.h> 40 #if defined(CONFIG_X86) 41 #include <asm/pat.h> 42 #endif 43 #include <linux/sched.h> 44 #include <linux/sched/mm.h> 45 #include <linux/sched/task.h> 46 #include <linux/delay.h> 47 #include <rdma/ib_user_verbs.h> 48 #include <rdma/ib_addr.h> 49 #include <rdma/ib_cache.h> 50 #include <linux/mlx5/port.h> 51 #include <linux/mlx5/vport.h> 52 #include <linux/list.h> 53 #include <rdma/ib_smi.h> 54 #include <rdma/ib_umem.h> 55 #include <linux/in.h> 56 #include <linux/etherdevice.h> 57 #include <linux/mlx5/fs.h> 58 #include <linux/mlx5/vport.h> 59 #include "mlx5_ib.h" 60 #include "cmd.h" 61 62 #define DRIVER_NAME "mlx5_ib" 63 #define DRIVER_VERSION "2.2-1" 64 #define DRIVER_RELDATE "Feb 2014" 65 66 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 67 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver"); 68 MODULE_LICENSE("Dual BSD/GPL"); 69 MODULE_VERSION(DRIVER_VERSION); 70 71 static char mlx5_version[] = 72 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v" 73 DRIVER_VERSION " (" DRIVER_RELDATE ")\n"; 74 75 enum { 76 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 77 }; 78 79 static enum rdma_link_layer 80 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 81 { 82 switch (port_type_cap) { 83 case MLX5_CAP_PORT_TYPE_IB: 84 return IB_LINK_LAYER_INFINIBAND; 85 case MLX5_CAP_PORT_TYPE_ETH: 86 return IB_LINK_LAYER_ETHERNET; 87 default: 88 return IB_LINK_LAYER_UNSPECIFIED; 89 } 90 } 91 92 static enum rdma_link_layer 93 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num) 94 { 95 struct mlx5_ib_dev *dev = to_mdev(device); 96 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 97 98 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 99 } 100 101 static int mlx5_netdev_event(struct notifier_block *this, 102 unsigned long event, void *ptr) 103 { 104 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 105 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev, 106 roce.nb); 107 108 switch (event) { 109 case NETDEV_REGISTER: 110 case NETDEV_UNREGISTER: 111 write_lock(&ibdev->roce.netdev_lock); 112 if (ndev->dev.parent == &ibdev->mdev->pdev->dev) 113 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ? 114 NULL : ndev; 115 write_unlock(&ibdev->roce.netdev_lock); 116 break; 117 118 case NETDEV_UP: 119 case NETDEV_DOWN: { 120 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(ibdev->mdev); 121 struct net_device *upper = NULL; 122 123 if (lag_ndev) { 124 upper = netdev_master_upper_dev_get(lag_ndev); 125 dev_put(lag_ndev); 126 } 127 128 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev)) 129 && ibdev->ib_active) { 130 struct ib_event ibev = { }; 131 132 ibev.device = &ibdev->ib_dev; 133 ibev.event = (event == NETDEV_UP) ? 134 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 135 ibev.element.port_num = 1; 136 ib_dispatch_event(&ibev); 137 } 138 break; 139 } 140 141 default: 142 break; 143 } 144 145 return NOTIFY_DONE; 146 } 147 148 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device, 149 u8 port_num) 150 { 151 struct mlx5_ib_dev *ibdev = to_mdev(device); 152 struct net_device *ndev; 153 154 ndev = mlx5_lag_get_roce_netdev(ibdev->mdev); 155 if (ndev) 156 return ndev; 157 158 /* Ensure ndev does not disappear before we invoke dev_hold() 159 */ 160 read_lock(&ibdev->roce.netdev_lock); 161 ndev = ibdev->roce.netdev; 162 if (ndev) 163 dev_hold(ndev); 164 read_unlock(&ibdev->roce.netdev_lock); 165 166 return ndev; 167 } 168 169 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num, 170 struct ib_port_attr *props) 171 { 172 struct mlx5_ib_dev *dev = to_mdev(device); 173 struct net_device *ndev, *upper; 174 enum ib_mtu ndev_ib_mtu; 175 u16 qkey_viol_cntr; 176 177 /* props being zeroed by the caller, avoid zeroing it here */ 178 179 props->port_cap_flags |= IB_PORT_CM_SUP; 180 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS; 181 182 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 183 roce_address_table_size); 184 props->max_mtu = IB_MTU_4096; 185 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 186 props->pkey_tbl_len = 1; 187 props->state = IB_PORT_DOWN; 188 props->phys_state = 3; 189 190 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr); 191 props->qkey_viol_cntr = qkey_viol_cntr; 192 193 ndev = mlx5_ib_get_netdev(device, port_num); 194 if (!ndev) 195 return 0; 196 197 if (mlx5_lag_is_active(dev->mdev)) { 198 rcu_read_lock(); 199 upper = netdev_master_upper_dev_get_rcu(ndev); 200 if (upper) { 201 dev_put(ndev); 202 ndev = upper; 203 dev_hold(ndev); 204 } 205 rcu_read_unlock(); 206 } 207 208 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 209 props->state = IB_PORT_ACTIVE; 210 props->phys_state = 5; 211 } 212 213 ndev_ib_mtu = iboe_get_mtu(ndev->mtu); 214 215 dev_put(ndev); 216 217 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 218 219 props->active_width = IB_WIDTH_4X; /* TODO */ 220 props->active_speed = IB_SPEED_QDR; /* TODO */ 221 222 return 0; 223 } 224 225 static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid, 226 const struct ib_gid_attr *attr, 227 void *mlx5_addr) 228 { 229 #define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v) 230 char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr, 231 source_l3_address); 232 void *mlx5_addr_mac = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr, 233 source_mac_47_32); 234 235 if (!gid) 236 return; 237 238 ether_addr_copy(mlx5_addr_mac, attr->ndev->dev_addr); 239 240 if (is_vlan_dev(attr->ndev)) { 241 MLX5_SET_RA(mlx5_addr, vlan_valid, 1); 242 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_dev_vlan_id(attr->ndev)); 243 } 244 245 switch (attr->gid_type) { 246 case IB_GID_TYPE_IB: 247 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1); 248 break; 249 case IB_GID_TYPE_ROCE_UDP_ENCAP: 250 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2); 251 break; 252 253 default: 254 WARN_ON(true); 255 } 256 257 if (attr->gid_type != IB_GID_TYPE_IB) { 258 if (ipv6_addr_v4mapped((void *)gid)) 259 MLX5_SET_RA(mlx5_addr, roce_l3_type, 260 MLX5_ROCE_L3_TYPE_IPV4); 261 else 262 MLX5_SET_RA(mlx5_addr, roce_l3_type, 263 MLX5_ROCE_L3_TYPE_IPV6); 264 } 265 266 if ((attr->gid_type == IB_GID_TYPE_IB) || 267 !ipv6_addr_v4mapped((void *)gid)) 268 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid)); 269 else 270 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4); 271 } 272 273 static int set_roce_addr(struct ib_device *device, u8 port_num, 274 unsigned int index, 275 const union ib_gid *gid, 276 const struct ib_gid_attr *attr) 277 { 278 struct mlx5_ib_dev *dev = to_mdev(device); 279 u32 in[MLX5_ST_SZ_DW(set_roce_address_in)] = {0}; 280 u32 out[MLX5_ST_SZ_DW(set_roce_address_out)] = {0}; 281 void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address); 282 enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num); 283 284 if (ll != IB_LINK_LAYER_ETHERNET) 285 return -EINVAL; 286 287 ib_gid_to_mlx5_roce_addr(gid, attr, in_addr); 288 289 MLX5_SET(set_roce_address_in, in, roce_address_index, index); 290 MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS); 291 return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out)); 292 } 293 294 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num, 295 unsigned int index, const union ib_gid *gid, 296 const struct ib_gid_attr *attr, 297 __always_unused void **context) 298 { 299 return set_roce_addr(device, port_num, index, gid, attr); 300 } 301 302 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num, 303 unsigned int index, __always_unused void **context) 304 { 305 return set_roce_addr(device, port_num, index, NULL, NULL); 306 } 307 308 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num, 309 int index) 310 { 311 struct ib_gid_attr attr; 312 union ib_gid gid; 313 314 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr)) 315 return 0; 316 317 if (!attr.ndev) 318 return 0; 319 320 dev_put(attr.ndev); 321 322 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 323 return 0; 324 325 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 326 } 327 328 int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num, 329 int index, enum ib_gid_type *gid_type) 330 { 331 struct ib_gid_attr attr; 332 union ib_gid gid; 333 int ret; 334 335 ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr); 336 if (ret) 337 return ret; 338 339 if (!attr.ndev) 340 return -ENODEV; 341 342 dev_put(attr.ndev); 343 344 *gid_type = attr.gid_type; 345 346 return 0; 347 } 348 349 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 350 { 351 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 352 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 353 return 0; 354 } 355 356 enum { 357 MLX5_VPORT_ACCESS_METHOD_MAD, 358 MLX5_VPORT_ACCESS_METHOD_HCA, 359 MLX5_VPORT_ACCESS_METHOD_NIC, 360 }; 361 362 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 363 { 364 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 365 return MLX5_VPORT_ACCESS_METHOD_MAD; 366 367 if (mlx5_ib_port_link_layer(ibdev, 1) == 368 IB_LINK_LAYER_ETHERNET) 369 return MLX5_VPORT_ACCESS_METHOD_NIC; 370 371 return MLX5_VPORT_ACCESS_METHOD_HCA; 372 } 373 374 static void get_atomic_caps(struct mlx5_ib_dev *dev, 375 struct ib_device_attr *props) 376 { 377 u8 tmp; 378 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 379 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 380 u8 atomic_req_8B_endianness_mode = 381 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode); 382 383 /* Check if HW supports 8 bytes standard atomic operations and capable 384 * of host endianness respond 385 */ 386 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 387 if (((atomic_operations & tmp) == tmp) && 388 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 389 (atomic_req_8B_endianness_mode)) { 390 props->atomic_cap = IB_ATOMIC_HCA; 391 } else { 392 props->atomic_cap = IB_ATOMIC_NONE; 393 } 394 } 395 396 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 397 __be64 *sys_image_guid) 398 { 399 struct mlx5_ib_dev *dev = to_mdev(ibdev); 400 struct mlx5_core_dev *mdev = dev->mdev; 401 u64 tmp; 402 int err; 403 404 switch (mlx5_get_vport_access_method(ibdev)) { 405 case MLX5_VPORT_ACCESS_METHOD_MAD: 406 return mlx5_query_mad_ifc_system_image_guid(ibdev, 407 sys_image_guid); 408 409 case MLX5_VPORT_ACCESS_METHOD_HCA: 410 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 411 break; 412 413 case MLX5_VPORT_ACCESS_METHOD_NIC: 414 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 415 break; 416 417 default: 418 return -EINVAL; 419 } 420 421 if (!err) 422 *sys_image_guid = cpu_to_be64(tmp); 423 424 return err; 425 426 } 427 428 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 429 u16 *max_pkeys) 430 { 431 struct mlx5_ib_dev *dev = to_mdev(ibdev); 432 struct mlx5_core_dev *mdev = dev->mdev; 433 434 switch (mlx5_get_vport_access_method(ibdev)) { 435 case MLX5_VPORT_ACCESS_METHOD_MAD: 436 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 437 438 case MLX5_VPORT_ACCESS_METHOD_HCA: 439 case MLX5_VPORT_ACCESS_METHOD_NIC: 440 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 441 pkey_table_size)); 442 return 0; 443 444 default: 445 return -EINVAL; 446 } 447 } 448 449 static int mlx5_query_vendor_id(struct ib_device *ibdev, 450 u32 *vendor_id) 451 { 452 struct mlx5_ib_dev *dev = to_mdev(ibdev); 453 454 switch (mlx5_get_vport_access_method(ibdev)) { 455 case MLX5_VPORT_ACCESS_METHOD_MAD: 456 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 457 458 case MLX5_VPORT_ACCESS_METHOD_HCA: 459 case MLX5_VPORT_ACCESS_METHOD_NIC: 460 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 461 462 default: 463 return -EINVAL; 464 } 465 } 466 467 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 468 __be64 *node_guid) 469 { 470 u64 tmp; 471 int err; 472 473 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 474 case MLX5_VPORT_ACCESS_METHOD_MAD: 475 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 476 477 case MLX5_VPORT_ACCESS_METHOD_HCA: 478 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 479 break; 480 481 case MLX5_VPORT_ACCESS_METHOD_NIC: 482 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 483 break; 484 485 default: 486 return -EINVAL; 487 } 488 489 if (!err) 490 *node_guid = cpu_to_be64(tmp); 491 492 return err; 493 } 494 495 struct mlx5_reg_node_desc { 496 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 497 }; 498 499 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 500 { 501 struct mlx5_reg_node_desc in; 502 503 if (mlx5_use_mad_ifc(dev)) 504 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 505 506 memset(&in, 0, sizeof(in)); 507 508 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 509 sizeof(struct mlx5_reg_node_desc), 510 MLX5_REG_NODE_DESC, 0, 0); 511 } 512 513 static int mlx5_ib_query_device(struct ib_device *ibdev, 514 struct ib_device_attr *props, 515 struct ib_udata *uhw) 516 { 517 struct mlx5_ib_dev *dev = to_mdev(ibdev); 518 struct mlx5_core_dev *mdev = dev->mdev; 519 int err = -ENOMEM; 520 int max_sq_desc; 521 int max_rq_sg; 522 int max_sq_sg; 523 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 524 struct mlx5_ib_query_device_resp resp = {}; 525 size_t resp_len; 526 u64 max_tso; 527 528 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 529 if (uhw->outlen && uhw->outlen < resp_len) 530 return -EINVAL; 531 else 532 resp.response_length = resp_len; 533 534 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) 535 return -EINVAL; 536 537 memset(props, 0, sizeof(*props)); 538 err = mlx5_query_system_image_guid(ibdev, 539 &props->sys_image_guid); 540 if (err) 541 return err; 542 543 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys); 544 if (err) 545 return err; 546 547 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 548 if (err) 549 return err; 550 551 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 552 (fw_rev_min(dev->mdev) << 16) | 553 fw_rev_sub(dev->mdev); 554 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 555 IB_DEVICE_PORT_ACTIVE_EVENT | 556 IB_DEVICE_SYS_IMAGE_GUID | 557 IB_DEVICE_RC_RNR_NAK_GEN; 558 559 if (MLX5_CAP_GEN(mdev, pkv)) 560 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 561 if (MLX5_CAP_GEN(mdev, qkv)) 562 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 563 if (MLX5_CAP_GEN(mdev, apm)) 564 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 565 if (MLX5_CAP_GEN(mdev, xrc)) 566 props->device_cap_flags |= IB_DEVICE_XRC; 567 if (MLX5_CAP_GEN(mdev, imaicl)) { 568 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 569 IB_DEVICE_MEM_WINDOW_TYPE_2B; 570 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 571 /* We support 'Gappy' memory registration too */ 572 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG; 573 } 574 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 575 if (MLX5_CAP_GEN(mdev, sho)) { 576 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER; 577 /* At this stage no support for signature handover */ 578 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 579 IB_PROT_T10DIF_TYPE_2 | 580 IB_PROT_T10DIF_TYPE_3; 581 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 582 IB_GUARD_T10DIF_CSUM; 583 } 584 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 585 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 586 587 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) { 588 if (MLX5_CAP_ETH(mdev, csum_cap)) { 589 /* Legacy bit to support old userspace libraries */ 590 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 591 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM; 592 } 593 594 if (MLX5_CAP_ETH(dev->mdev, vlan_cap)) 595 props->raw_packet_caps |= 596 IB_RAW_PACKET_CAP_CVLAN_STRIPPING; 597 598 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) { 599 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 600 if (max_tso) { 601 resp.tso_caps.max_tso = 1 << max_tso; 602 resp.tso_caps.supported_qpts |= 603 1 << IB_QPT_RAW_PACKET; 604 resp.response_length += sizeof(resp.tso_caps); 605 } 606 } 607 608 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) { 609 resp.rss_caps.rx_hash_function = 610 MLX5_RX_HASH_FUNC_TOEPLITZ; 611 resp.rss_caps.rx_hash_fields_mask = 612 MLX5_RX_HASH_SRC_IPV4 | 613 MLX5_RX_HASH_DST_IPV4 | 614 MLX5_RX_HASH_SRC_IPV6 | 615 MLX5_RX_HASH_DST_IPV6 | 616 MLX5_RX_HASH_SRC_PORT_TCP | 617 MLX5_RX_HASH_DST_PORT_TCP | 618 MLX5_RX_HASH_SRC_PORT_UDP | 619 MLX5_RX_HASH_DST_PORT_UDP; 620 resp.response_length += sizeof(resp.rss_caps); 621 } 622 } else { 623 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) 624 resp.response_length += sizeof(resp.tso_caps); 625 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) 626 resp.response_length += sizeof(resp.rss_caps); 627 } 628 629 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 630 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 631 props->device_cap_flags |= IB_DEVICE_UD_TSO; 632 } 633 634 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 635 MLX5_CAP_ETH(dev->mdev, scatter_fcs)) { 636 /* Legacy bit to support old userspace libraries */ 637 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 638 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; 639 } 640 641 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 642 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 643 644 props->vendor_part_id = mdev->pdev->device; 645 props->hw_ver = mdev->pdev->revision; 646 647 props->max_mr_size = ~0ull; 648 props->page_size_cap = ~(min_page_size - 1); 649 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 650 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 651 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 652 sizeof(struct mlx5_wqe_data_seg); 653 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512); 654 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) - 655 sizeof(struct mlx5_wqe_raddr_seg)) / 656 sizeof(struct mlx5_wqe_data_seg); 657 props->max_sge = min(max_rq_sg, max_sq_sg); 658 props->max_sge_rd = MLX5_MAX_SGE_RD; 659 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 660 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 661 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 662 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 663 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 664 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 665 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 666 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 667 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 668 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 669 props->max_srq_sge = max_rq_sg - 1; 670 props->max_fast_reg_page_list_len = 671 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 672 get_atomic_caps(dev, props); 673 props->masked_atomic_cap = IB_ATOMIC_NONE; 674 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 675 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 676 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 677 props->max_mcast_grp; 678 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */ 679 props->max_ah = INT_MAX; 680 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 681 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 682 683 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 684 if (MLX5_CAP_GEN(mdev, pg)) 685 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING; 686 props->odp_caps = dev->odp_caps; 687 #endif 688 689 if (MLX5_CAP_GEN(mdev, cd)) 690 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL; 691 692 if (!mlx5_core_is_pf(mdev)) 693 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION; 694 695 if (mlx5_ib_port_link_layer(ibdev, 1) == 696 IB_LINK_LAYER_ETHERNET) { 697 props->rss_caps.max_rwq_indirection_tables = 698 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 699 props->rss_caps.max_rwq_indirection_table_size = 700 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 701 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 702 props->max_wq_type_rq = 703 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 704 } 705 706 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) { 707 resp.cqe_comp_caps.max_num = 708 MLX5_CAP_GEN(dev->mdev, cqe_compression) ? 709 MLX5_CAP_GEN(dev->mdev, cqe_compression_max_num) : 0; 710 resp.cqe_comp_caps.supported_format = 711 MLX5_IB_CQE_RES_FORMAT_HASH | 712 MLX5_IB_CQE_RES_FORMAT_CSUM; 713 resp.response_length += sizeof(resp.cqe_comp_caps); 714 } 715 716 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen)) { 717 if (MLX5_CAP_QOS(mdev, packet_pacing) && 718 MLX5_CAP_GEN(mdev, qos)) { 719 resp.packet_pacing_caps.qp_rate_limit_max = 720 MLX5_CAP_QOS(mdev, packet_pacing_max_rate); 721 resp.packet_pacing_caps.qp_rate_limit_min = 722 MLX5_CAP_QOS(mdev, packet_pacing_min_rate); 723 resp.packet_pacing_caps.supported_qpts |= 724 1 << IB_QPT_RAW_PACKET; 725 } 726 resp.response_length += sizeof(resp.packet_pacing_caps); 727 } 728 729 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes, 730 uhw->outlen)) { 731 resp.mlx5_ib_support_multi_pkt_send_wqes = 732 MLX5_CAP_ETH(mdev, multi_pkt_send_wqe); 733 resp.response_length += 734 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes); 735 } 736 737 if (field_avail(typeof(resp), reserved, uhw->outlen)) 738 resp.response_length += sizeof(resp.reserved); 739 740 if (uhw->outlen) { 741 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 742 743 if (err) 744 return err; 745 } 746 747 return 0; 748 } 749 750 enum mlx5_ib_width { 751 MLX5_IB_WIDTH_1X = 1 << 0, 752 MLX5_IB_WIDTH_2X = 1 << 1, 753 MLX5_IB_WIDTH_4X = 1 << 2, 754 MLX5_IB_WIDTH_8X = 1 << 3, 755 MLX5_IB_WIDTH_12X = 1 << 4 756 }; 757 758 static int translate_active_width(struct ib_device *ibdev, u8 active_width, 759 u8 *ib_width) 760 { 761 struct mlx5_ib_dev *dev = to_mdev(ibdev); 762 int err = 0; 763 764 if (active_width & MLX5_IB_WIDTH_1X) { 765 *ib_width = IB_WIDTH_1X; 766 } else if (active_width & MLX5_IB_WIDTH_2X) { 767 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n", 768 (int)active_width); 769 err = -EINVAL; 770 } else if (active_width & MLX5_IB_WIDTH_4X) { 771 *ib_width = IB_WIDTH_4X; 772 } else if (active_width & MLX5_IB_WIDTH_8X) { 773 *ib_width = IB_WIDTH_8X; 774 } else if (active_width & MLX5_IB_WIDTH_12X) { 775 *ib_width = IB_WIDTH_12X; 776 } else { 777 mlx5_ib_dbg(dev, "Invalid active_width %d\n", 778 (int)active_width); 779 err = -EINVAL; 780 } 781 782 return err; 783 } 784 785 static int mlx5_mtu_to_ib_mtu(int mtu) 786 { 787 switch (mtu) { 788 case 256: return 1; 789 case 512: return 2; 790 case 1024: return 3; 791 case 2048: return 4; 792 case 4096: return 5; 793 default: 794 pr_warn("invalid mtu\n"); 795 return -1; 796 } 797 } 798 799 enum ib_max_vl_num { 800 __IB_MAX_VL_0 = 1, 801 __IB_MAX_VL_0_1 = 2, 802 __IB_MAX_VL_0_3 = 3, 803 __IB_MAX_VL_0_7 = 4, 804 __IB_MAX_VL_0_14 = 5, 805 }; 806 807 enum mlx5_vl_hw_cap { 808 MLX5_VL_HW_0 = 1, 809 MLX5_VL_HW_0_1 = 2, 810 MLX5_VL_HW_0_2 = 3, 811 MLX5_VL_HW_0_3 = 4, 812 MLX5_VL_HW_0_4 = 5, 813 MLX5_VL_HW_0_5 = 6, 814 MLX5_VL_HW_0_6 = 7, 815 MLX5_VL_HW_0_7 = 8, 816 MLX5_VL_HW_0_14 = 15 817 }; 818 819 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 820 u8 *max_vl_num) 821 { 822 switch (vl_hw_cap) { 823 case MLX5_VL_HW_0: 824 *max_vl_num = __IB_MAX_VL_0; 825 break; 826 case MLX5_VL_HW_0_1: 827 *max_vl_num = __IB_MAX_VL_0_1; 828 break; 829 case MLX5_VL_HW_0_3: 830 *max_vl_num = __IB_MAX_VL_0_3; 831 break; 832 case MLX5_VL_HW_0_7: 833 *max_vl_num = __IB_MAX_VL_0_7; 834 break; 835 case MLX5_VL_HW_0_14: 836 *max_vl_num = __IB_MAX_VL_0_14; 837 break; 838 839 default: 840 return -EINVAL; 841 } 842 843 return 0; 844 } 845 846 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port, 847 struct ib_port_attr *props) 848 { 849 struct mlx5_ib_dev *dev = to_mdev(ibdev); 850 struct mlx5_core_dev *mdev = dev->mdev; 851 struct mlx5_hca_vport_context *rep; 852 u16 max_mtu; 853 u16 oper_mtu; 854 int err; 855 u8 ib_link_width_oper; 856 u8 vl_hw_cap; 857 858 rep = kzalloc(sizeof(*rep), GFP_KERNEL); 859 if (!rep) { 860 err = -ENOMEM; 861 goto out; 862 } 863 864 /* props being zeroed by the caller, avoid zeroing it here */ 865 866 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); 867 if (err) 868 goto out; 869 870 props->lid = rep->lid; 871 props->lmc = rep->lmc; 872 props->sm_lid = rep->sm_lid; 873 props->sm_sl = rep->sm_sl; 874 props->state = rep->vport_state; 875 props->phys_state = rep->port_physical_state; 876 props->port_cap_flags = rep->cap_mask1; 877 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 878 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 879 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 880 props->bad_pkey_cntr = rep->pkey_violation_counter; 881 props->qkey_viol_cntr = rep->qkey_violation_counter; 882 props->subnet_timeout = rep->subnet_timeout; 883 props->init_type_reply = rep->init_type_reply; 884 props->grh_required = rep->grh_required; 885 886 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port); 887 if (err) 888 goto out; 889 890 err = translate_active_width(ibdev, ib_link_width_oper, 891 &props->active_width); 892 if (err) 893 goto out; 894 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port); 895 if (err) 896 goto out; 897 898 mlx5_query_port_max_mtu(mdev, &max_mtu, port); 899 900 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); 901 902 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); 903 904 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); 905 906 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); 907 if (err) 908 goto out; 909 910 err = translate_max_vl_num(ibdev, vl_hw_cap, 911 &props->max_vl_num); 912 out: 913 kfree(rep); 914 return err; 915 } 916 917 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 918 struct ib_port_attr *props) 919 { 920 switch (mlx5_get_vport_access_method(ibdev)) { 921 case MLX5_VPORT_ACCESS_METHOD_MAD: 922 return mlx5_query_mad_ifc_port(ibdev, port, props); 923 924 case MLX5_VPORT_ACCESS_METHOD_HCA: 925 return mlx5_query_hca_port(ibdev, port, props); 926 927 case MLX5_VPORT_ACCESS_METHOD_NIC: 928 return mlx5_query_port_roce(ibdev, port, props); 929 930 default: 931 return -EINVAL; 932 } 933 } 934 935 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 936 union ib_gid *gid) 937 { 938 struct mlx5_ib_dev *dev = to_mdev(ibdev); 939 struct mlx5_core_dev *mdev = dev->mdev; 940 941 switch (mlx5_get_vport_access_method(ibdev)) { 942 case MLX5_VPORT_ACCESS_METHOD_MAD: 943 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 944 945 case MLX5_VPORT_ACCESS_METHOD_HCA: 946 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); 947 948 default: 949 return -EINVAL; 950 } 951 952 } 953 954 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 955 u16 *pkey) 956 { 957 struct mlx5_ib_dev *dev = to_mdev(ibdev); 958 struct mlx5_core_dev *mdev = dev->mdev; 959 960 switch (mlx5_get_vport_access_method(ibdev)) { 961 case MLX5_VPORT_ACCESS_METHOD_MAD: 962 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 963 964 case MLX5_VPORT_ACCESS_METHOD_HCA: 965 case MLX5_VPORT_ACCESS_METHOD_NIC: 966 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index, 967 pkey); 968 default: 969 return -EINVAL; 970 } 971 } 972 973 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 974 struct ib_device_modify *props) 975 { 976 struct mlx5_ib_dev *dev = to_mdev(ibdev); 977 struct mlx5_reg_node_desc in; 978 struct mlx5_reg_node_desc out; 979 int err; 980 981 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 982 return -EOPNOTSUPP; 983 984 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 985 return 0; 986 987 /* 988 * If possible, pass node desc to FW, so it can generate 989 * a 144 trap. If cmd fails, just ignore. 990 */ 991 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 992 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 993 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 994 if (err) 995 return err; 996 997 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 998 999 return err; 1000 } 1001 1002 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask, 1003 u32 value) 1004 { 1005 struct mlx5_hca_vport_context ctx = {}; 1006 int err; 1007 1008 err = mlx5_query_hca_vport_context(dev->mdev, 0, 1009 port_num, 0, &ctx); 1010 if (err) 1011 return err; 1012 1013 if (~ctx.cap_mask1_perm & mask) { 1014 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n", 1015 mask, ctx.cap_mask1_perm); 1016 return -EINVAL; 1017 } 1018 1019 ctx.cap_mask1 = value; 1020 ctx.cap_mask1_perm = mask; 1021 err = mlx5_core_modify_hca_vport_context(dev->mdev, 0, 1022 port_num, 0, &ctx); 1023 1024 return err; 1025 } 1026 1027 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, 1028 struct ib_port_modify *props) 1029 { 1030 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1031 struct ib_port_attr attr; 1032 u32 tmp; 1033 int err; 1034 u32 change_mask; 1035 u32 value; 1036 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) == 1037 IB_LINK_LAYER_INFINIBAND); 1038 1039 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) { 1040 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask; 1041 value = ~props->clr_port_cap_mask | props->set_port_cap_mask; 1042 return set_port_caps_atomic(dev, port, change_mask, value); 1043 } 1044 1045 mutex_lock(&dev->cap_mask_mutex); 1046 1047 err = ib_query_port(ibdev, port, &attr); 1048 if (err) 1049 goto out; 1050 1051 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 1052 ~props->clr_port_cap_mask; 1053 1054 err = mlx5_set_port_caps(dev->mdev, port, tmp); 1055 1056 out: 1057 mutex_unlock(&dev->cap_mask_mutex); 1058 return err; 1059 } 1060 1061 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps) 1062 { 1063 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n", 1064 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n"); 1065 } 1066 1067 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k, 1068 struct mlx5_ib_alloc_ucontext_req_v2 *req, 1069 u32 *num_sys_pages) 1070 { 1071 int uars_per_sys_page; 1072 int bfregs_per_sys_page; 1073 int ref_bfregs = req->total_num_bfregs; 1074 1075 if (req->total_num_bfregs == 0) 1076 return -EINVAL; 1077 1078 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE); 1079 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE); 1080 1081 if (req->total_num_bfregs > MLX5_MAX_BFREGS) 1082 return -ENOMEM; 1083 1084 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k); 1085 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR; 1086 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page); 1087 *num_sys_pages = req->total_num_bfregs / bfregs_per_sys_page; 1088 1089 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1) 1090 return -EINVAL; 1091 1092 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, alloated %d, using %d sys pages\n", 1093 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no", 1094 lib_uar_4k ? "yes" : "no", ref_bfregs, 1095 req->total_num_bfregs, *num_sys_pages); 1096 1097 return 0; 1098 } 1099 1100 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1101 { 1102 struct mlx5_bfreg_info *bfregi; 1103 int err; 1104 int i; 1105 1106 bfregi = &context->bfregi; 1107 for (i = 0; i < bfregi->num_sys_pages; i++) { 1108 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]); 1109 if (err) 1110 goto error; 1111 1112 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]); 1113 } 1114 return 0; 1115 1116 error: 1117 for (--i; i >= 0; i--) 1118 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i])) 1119 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1120 1121 return err; 1122 } 1123 1124 static int deallocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1125 { 1126 struct mlx5_bfreg_info *bfregi; 1127 int err; 1128 int i; 1129 1130 bfregi = &context->bfregi; 1131 for (i = 0; i < bfregi->num_sys_pages; i++) { 1132 err = mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]); 1133 if (err) { 1134 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1135 return err; 1136 } 1137 } 1138 return 0; 1139 } 1140 1141 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev, 1142 struct ib_udata *udata) 1143 { 1144 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1145 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 1146 struct mlx5_ib_alloc_ucontext_resp resp = {}; 1147 struct mlx5_ib_ucontext *context; 1148 struct mlx5_bfreg_info *bfregi; 1149 int ver; 1150 int err; 1151 size_t reqlen; 1152 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 1153 max_cqe_version); 1154 bool lib_uar_4k; 1155 1156 if (!dev->ib_active) 1157 return ERR_PTR(-EAGAIN); 1158 1159 if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr)) 1160 return ERR_PTR(-EINVAL); 1161 1162 reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr); 1163 if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 1164 ver = 0; 1165 else if (reqlen >= min_req_v2) 1166 ver = 2; 1167 else 1168 return ERR_PTR(-EINVAL); 1169 1170 err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req))); 1171 if (err) 1172 return ERR_PTR(err); 1173 1174 if (req.flags) 1175 return ERR_PTR(-EINVAL); 1176 1177 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 1178 return ERR_PTR(-EOPNOTSUPP); 1179 1180 req.total_num_bfregs = ALIGN(req.total_num_bfregs, 1181 MLX5_NON_FP_BFREGS_PER_UAR); 1182 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1) 1183 return ERR_PTR(-EINVAL); 1184 1185 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 1186 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf)) 1187 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size); 1188 resp.cache_line_size = cache_line_size(); 1189 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 1190 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 1191 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1192 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1193 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 1194 resp.cqe_version = min_t(__u8, 1195 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 1196 req.max_cqe_version); 1197 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1198 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT; 1199 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1200 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1; 1201 resp.response_length = min(offsetof(typeof(resp), response_length) + 1202 sizeof(resp.response_length), udata->outlen); 1203 1204 context = kzalloc(sizeof(*context), GFP_KERNEL); 1205 if (!context) 1206 return ERR_PTR(-ENOMEM); 1207 1208 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR; 1209 bfregi = &context->bfregi; 1210 1211 /* updates req->total_num_bfregs */ 1212 err = calc_total_bfregs(dev, lib_uar_4k, &req, &bfregi->num_sys_pages); 1213 if (err) 1214 goto out_ctx; 1215 1216 mutex_init(&bfregi->lock); 1217 bfregi->lib_uar_4k = lib_uar_4k; 1218 bfregi->count = kcalloc(req.total_num_bfregs, sizeof(*bfregi->count), 1219 GFP_KERNEL); 1220 if (!bfregi->count) { 1221 err = -ENOMEM; 1222 goto out_ctx; 1223 } 1224 1225 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages, 1226 sizeof(*bfregi->sys_pages), 1227 GFP_KERNEL); 1228 if (!bfregi->sys_pages) { 1229 err = -ENOMEM; 1230 goto out_count; 1231 } 1232 1233 err = allocate_uars(dev, context); 1234 if (err) 1235 goto out_sys_pages; 1236 1237 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1238 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range; 1239 #endif 1240 1241 context->upd_xlt_page = __get_free_page(GFP_KERNEL); 1242 if (!context->upd_xlt_page) { 1243 err = -ENOMEM; 1244 goto out_uars; 1245 } 1246 mutex_init(&context->upd_xlt_page_mutex); 1247 1248 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) { 1249 err = mlx5_core_alloc_transport_domain(dev->mdev, 1250 &context->tdn); 1251 if (err) 1252 goto out_page; 1253 } 1254 1255 INIT_LIST_HEAD(&context->vma_private_list); 1256 INIT_LIST_HEAD(&context->db_page_list); 1257 mutex_init(&context->db_page_mutex); 1258 1259 resp.tot_bfregs = req.total_num_bfregs; 1260 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports); 1261 1262 if (field_avail(typeof(resp), cqe_version, udata->outlen)) 1263 resp.response_length += sizeof(resp.cqe_version); 1264 1265 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) { 1266 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 1267 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 1268 resp.response_length += sizeof(resp.cmds_supp_uhw); 1269 } 1270 1271 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) { 1272 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) { 1273 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline); 1274 resp.eth_min_inline++; 1275 } 1276 resp.response_length += sizeof(resp.eth_min_inline); 1277 } 1278 1279 /* 1280 * We don't want to expose information from the PCI bar that is located 1281 * after 4096 bytes, so if the arch only supports larger pages, let's 1282 * pretend we don't support reading the HCA's core clock. This is also 1283 * forced by mmap function. 1284 */ 1285 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) { 1286 if (PAGE_SIZE <= 4096) { 1287 resp.comp_mask |= 1288 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 1289 resp.hca_core_clock_offset = 1290 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE; 1291 } 1292 resp.response_length += sizeof(resp.hca_core_clock_offset) + 1293 sizeof(resp.reserved2); 1294 } 1295 1296 if (field_avail(typeof(resp), log_uar_size, udata->outlen)) 1297 resp.response_length += sizeof(resp.log_uar_size); 1298 1299 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen)) 1300 resp.response_length += sizeof(resp.num_uars_per_page); 1301 1302 err = ib_copy_to_udata(udata, &resp, resp.response_length); 1303 if (err) 1304 goto out_td; 1305 1306 bfregi->ver = ver; 1307 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs; 1308 context->cqe_version = resp.cqe_version; 1309 context->lib_caps = req.lib_caps; 1310 print_lib_caps(dev, context->lib_caps); 1311 1312 return &context->ibucontext; 1313 1314 out_td: 1315 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1316 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn); 1317 1318 out_page: 1319 free_page(context->upd_xlt_page); 1320 1321 out_uars: 1322 deallocate_uars(dev, context); 1323 1324 out_sys_pages: 1325 kfree(bfregi->sys_pages); 1326 1327 out_count: 1328 kfree(bfregi->count); 1329 1330 out_ctx: 1331 kfree(context); 1332 1333 return ERR_PTR(err); 1334 } 1335 1336 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1337 { 1338 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1339 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1340 struct mlx5_bfreg_info *bfregi; 1341 1342 bfregi = &context->bfregi; 1343 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1344 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn); 1345 1346 free_page(context->upd_xlt_page); 1347 deallocate_uars(dev, context); 1348 kfree(bfregi->sys_pages); 1349 kfree(bfregi->count); 1350 kfree(context); 1351 1352 return 0; 1353 } 1354 1355 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, 1356 struct mlx5_bfreg_info *bfregi, 1357 int idx) 1358 { 1359 int fw_uars_per_page; 1360 1361 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1; 1362 1363 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + 1364 bfregi->sys_pages[idx] / fw_uars_per_page; 1365 } 1366 1367 static int get_command(unsigned long offset) 1368 { 1369 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 1370 } 1371 1372 static int get_arg(unsigned long offset) 1373 { 1374 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 1375 } 1376 1377 static int get_index(unsigned long offset) 1378 { 1379 return get_arg(offset); 1380 } 1381 1382 static void mlx5_ib_vma_open(struct vm_area_struct *area) 1383 { 1384 /* vma_open is called when a new VMA is created on top of our VMA. This 1385 * is done through either mremap flow or split_vma (usually due to 1386 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA, 1387 * as this VMA is strongly hardware related. Therefore we set the 1388 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from 1389 * calling us again and trying to do incorrect actions. We assume that 1390 * the original VMA size is exactly a single page, and therefore all 1391 * "splitting" operation will not happen to it. 1392 */ 1393 area->vm_ops = NULL; 1394 } 1395 1396 static void mlx5_ib_vma_close(struct vm_area_struct *area) 1397 { 1398 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data; 1399 1400 /* It's guaranteed that all VMAs opened on a FD are closed before the 1401 * file itself is closed, therefore no sync is needed with the regular 1402 * closing flow. (e.g. mlx5 ib_dealloc_ucontext) 1403 * However need a sync with accessing the vma as part of 1404 * mlx5_ib_disassociate_ucontext. 1405 * The close operation is usually called under mm->mmap_sem except when 1406 * process is exiting. 1407 * The exiting case is handled explicitly as part of 1408 * mlx5_ib_disassociate_ucontext. 1409 */ 1410 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data; 1411 1412 /* setting the vma context pointer to null in the mlx5_ib driver's 1413 * private data, to protect a race condition in 1414 * mlx5_ib_disassociate_ucontext(). 1415 */ 1416 mlx5_ib_vma_priv_data->vma = NULL; 1417 list_del(&mlx5_ib_vma_priv_data->list); 1418 kfree(mlx5_ib_vma_priv_data); 1419 } 1420 1421 static const struct vm_operations_struct mlx5_ib_vm_ops = { 1422 .open = mlx5_ib_vma_open, 1423 .close = mlx5_ib_vma_close 1424 }; 1425 1426 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma, 1427 struct mlx5_ib_ucontext *ctx) 1428 { 1429 struct mlx5_ib_vma_private_data *vma_prv; 1430 struct list_head *vma_head = &ctx->vma_private_list; 1431 1432 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL); 1433 if (!vma_prv) 1434 return -ENOMEM; 1435 1436 vma_prv->vma = vma; 1437 vma->vm_private_data = vma_prv; 1438 vma->vm_ops = &mlx5_ib_vm_ops; 1439 1440 list_add(&vma_prv->list, vma_head); 1441 1442 return 0; 1443 } 1444 1445 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 1446 { 1447 int ret; 1448 struct vm_area_struct *vma; 1449 struct mlx5_ib_vma_private_data *vma_private, *n; 1450 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1451 struct task_struct *owning_process = NULL; 1452 struct mm_struct *owning_mm = NULL; 1453 1454 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID); 1455 if (!owning_process) 1456 return; 1457 1458 owning_mm = get_task_mm(owning_process); 1459 if (!owning_mm) { 1460 pr_info("no mm, disassociate ucontext is pending task termination\n"); 1461 while (1) { 1462 put_task_struct(owning_process); 1463 usleep_range(1000, 2000); 1464 owning_process = get_pid_task(ibcontext->tgid, 1465 PIDTYPE_PID); 1466 if (!owning_process || 1467 owning_process->state == TASK_DEAD) { 1468 pr_info("disassociate ucontext done, task was terminated\n"); 1469 /* in case task was dead need to release the 1470 * task struct. 1471 */ 1472 if (owning_process) 1473 put_task_struct(owning_process); 1474 return; 1475 } 1476 } 1477 } 1478 1479 /* need to protect from a race on closing the vma as part of 1480 * mlx5_ib_vma_close. 1481 */ 1482 down_write(&owning_mm->mmap_sem); 1483 list_for_each_entry_safe(vma_private, n, &context->vma_private_list, 1484 list) { 1485 vma = vma_private->vma; 1486 ret = zap_vma_ptes(vma, vma->vm_start, 1487 PAGE_SIZE); 1488 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__); 1489 /* context going to be destroyed, should 1490 * not access ops any more. 1491 */ 1492 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE); 1493 vma->vm_ops = NULL; 1494 list_del(&vma_private->list); 1495 kfree(vma_private); 1496 } 1497 up_write(&owning_mm->mmap_sem); 1498 mmput(owning_mm); 1499 put_task_struct(owning_process); 1500 } 1501 1502 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 1503 { 1504 switch (cmd) { 1505 case MLX5_IB_MMAP_WC_PAGE: 1506 return "WC"; 1507 case MLX5_IB_MMAP_REGULAR_PAGE: 1508 return "best effort WC"; 1509 case MLX5_IB_MMAP_NC_PAGE: 1510 return "NC"; 1511 default: 1512 return NULL; 1513 } 1514 } 1515 1516 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 1517 struct vm_area_struct *vma, 1518 struct mlx5_ib_ucontext *context) 1519 { 1520 struct mlx5_bfreg_info *bfregi = &context->bfregi; 1521 int err; 1522 unsigned long idx; 1523 phys_addr_t pfn, pa; 1524 pgprot_t prot; 1525 int uars_per_page; 1526 1527 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1528 return -EINVAL; 1529 1530 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k); 1531 idx = get_index(vma->vm_pgoff); 1532 if (idx % uars_per_page || 1533 idx * uars_per_page >= bfregi->num_sys_pages) { 1534 mlx5_ib_warn(dev, "invalid uar index %lu\n", idx); 1535 return -EINVAL; 1536 } 1537 1538 switch (cmd) { 1539 case MLX5_IB_MMAP_WC_PAGE: 1540 /* Some architectures don't support WC memory */ 1541 #if defined(CONFIG_X86) 1542 if (!pat_enabled()) 1543 return -EPERM; 1544 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU))) 1545 return -EPERM; 1546 #endif 1547 /* fall through */ 1548 case MLX5_IB_MMAP_REGULAR_PAGE: 1549 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 1550 prot = pgprot_writecombine(vma->vm_page_prot); 1551 break; 1552 case MLX5_IB_MMAP_NC_PAGE: 1553 prot = pgprot_noncached(vma->vm_page_prot); 1554 break; 1555 default: 1556 return -EINVAL; 1557 } 1558 1559 pfn = uar_index2pfn(dev, bfregi, idx); 1560 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 1561 1562 vma->vm_page_prot = prot; 1563 err = io_remap_pfn_range(vma, vma->vm_start, pfn, 1564 PAGE_SIZE, vma->vm_page_prot); 1565 if (err) { 1566 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n", 1567 err, vma->vm_start, &pfn, mmap_cmd2str(cmd)); 1568 return -EAGAIN; 1569 } 1570 1571 pa = pfn << PAGE_SHIFT; 1572 mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd), 1573 vma->vm_start, &pa); 1574 1575 return mlx5_ib_set_vma_data(vma, context); 1576 } 1577 1578 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 1579 { 1580 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1581 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1582 unsigned long command; 1583 phys_addr_t pfn; 1584 1585 command = get_command(vma->vm_pgoff); 1586 switch (command) { 1587 case MLX5_IB_MMAP_WC_PAGE: 1588 case MLX5_IB_MMAP_NC_PAGE: 1589 case MLX5_IB_MMAP_REGULAR_PAGE: 1590 return uar_mmap(dev, command, vma, context); 1591 1592 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 1593 return -ENOSYS; 1594 1595 case MLX5_IB_MMAP_CORE_CLOCK: 1596 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1597 return -EINVAL; 1598 1599 if (vma->vm_flags & VM_WRITE) 1600 return -EPERM; 1601 1602 /* Don't expose to user-space information it shouldn't have */ 1603 if (PAGE_SIZE > 4096) 1604 return -EOPNOTSUPP; 1605 1606 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 1607 pfn = (dev->mdev->iseg_base + 1608 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 1609 PAGE_SHIFT; 1610 if (io_remap_pfn_range(vma, vma->vm_start, pfn, 1611 PAGE_SIZE, vma->vm_page_prot)) 1612 return -EAGAIN; 1613 1614 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n", 1615 vma->vm_start, 1616 (unsigned long long)pfn << PAGE_SHIFT); 1617 break; 1618 1619 default: 1620 return -EINVAL; 1621 } 1622 1623 return 0; 1624 } 1625 1626 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev, 1627 struct ib_ucontext *context, 1628 struct ib_udata *udata) 1629 { 1630 struct mlx5_ib_alloc_pd_resp resp; 1631 struct mlx5_ib_pd *pd; 1632 int err; 1633 1634 pd = kmalloc(sizeof(*pd), GFP_KERNEL); 1635 if (!pd) 1636 return ERR_PTR(-ENOMEM); 1637 1638 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn); 1639 if (err) { 1640 kfree(pd); 1641 return ERR_PTR(err); 1642 } 1643 1644 if (context) { 1645 resp.pdn = pd->pdn; 1646 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 1647 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn); 1648 kfree(pd); 1649 return ERR_PTR(-EFAULT); 1650 } 1651 } 1652 1653 return &pd->ibpd; 1654 } 1655 1656 static int mlx5_ib_dealloc_pd(struct ib_pd *pd) 1657 { 1658 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 1659 struct mlx5_ib_pd *mpd = to_mpd(pd); 1660 1661 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn); 1662 kfree(mpd); 1663 1664 return 0; 1665 } 1666 1667 enum { 1668 MATCH_CRITERIA_ENABLE_OUTER_BIT, 1669 MATCH_CRITERIA_ENABLE_MISC_BIT, 1670 MATCH_CRITERIA_ENABLE_INNER_BIT 1671 }; 1672 1673 #define HEADER_IS_ZERO(match_criteria, headers) \ 1674 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \ 1675 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \ 1676 1677 static u8 get_match_criteria_enable(u32 *match_criteria) 1678 { 1679 u8 match_criteria_enable; 1680 1681 match_criteria_enable = 1682 (!HEADER_IS_ZERO(match_criteria, outer_headers)) << 1683 MATCH_CRITERIA_ENABLE_OUTER_BIT; 1684 match_criteria_enable |= 1685 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) << 1686 MATCH_CRITERIA_ENABLE_MISC_BIT; 1687 match_criteria_enable |= 1688 (!HEADER_IS_ZERO(match_criteria, inner_headers)) << 1689 MATCH_CRITERIA_ENABLE_INNER_BIT; 1690 1691 return match_criteria_enable; 1692 } 1693 1694 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val) 1695 { 1696 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask); 1697 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val); 1698 } 1699 1700 static void set_flow_label(void *misc_c, void *misc_v, u8 mask, u8 val, 1701 bool inner) 1702 { 1703 if (inner) { 1704 MLX5_SET(fte_match_set_misc, 1705 misc_c, inner_ipv6_flow_label, mask); 1706 MLX5_SET(fte_match_set_misc, 1707 misc_v, inner_ipv6_flow_label, val); 1708 } else { 1709 MLX5_SET(fte_match_set_misc, 1710 misc_c, outer_ipv6_flow_label, mask); 1711 MLX5_SET(fte_match_set_misc, 1712 misc_v, outer_ipv6_flow_label, val); 1713 } 1714 } 1715 1716 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val) 1717 { 1718 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask); 1719 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val); 1720 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2); 1721 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2); 1722 } 1723 1724 #define LAST_ETH_FIELD vlan_tag 1725 #define LAST_IB_FIELD sl 1726 #define LAST_IPV4_FIELD tos 1727 #define LAST_IPV6_FIELD traffic_class 1728 #define LAST_TCP_UDP_FIELD src_port 1729 #define LAST_TUNNEL_FIELD tunnel_id 1730 #define LAST_FLOW_TAG_FIELD tag_id 1731 #define LAST_DROP_FIELD size 1732 1733 /* Field is the last supported field */ 1734 #define FIELDS_NOT_SUPPORTED(filter, field)\ 1735 memchr_inv((void *)&filter.field +\ 1736 sizeof(filter.field), 0,\ 1737 sizeof(filter) -\ 1738 offsetof(typeof(filter), field) -\ 1739 sizeof(filter.field)) 1740 1741 #define IPV4_VERSION 4 1742 #define IPV6_VERSION 6 1743 static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c, 1744 u32 *match_v, const union ib_flow_spec *ib_spec, 1745 u32 *tag_id, bool *is_drop) 1746 { 1747 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c, 1748 misc_parameters); 1749 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v, 1750 misc_parameters); 1751 void *headers_c; 1752 void *headers_v; 1753 int match_ipv; 1754 1755 if (ib_spec->type & IB_FLOW_SPEC_INNER) { 1756 headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 1757 inner_headers); 1758 headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 1759 inner_headers); 1760 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 1761 ft_field_support.inner_ip_version); 1762 } else { 1763 headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 1764 outer_headers); 1765 headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 1766 outer_headers); 1767 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 1768 ft_field_support.outer_ip_version); 1769 } 1770 1771 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) { 1772 case IB_FLOW_SPEC_ETH: 1773 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD)) 1774 return -EOPNOTSUPP; 1775 1776 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 1777 dmac_47_16), 1778 ib_spec->eth.mask.dst_mac); 1779 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1780 dmac_47_16), 1781 ib_spec->eth.val.dst_mac); 1782 1783 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 1784 smac_47_16), 1785 ib_spec->eth.mask.src_mac); 1786 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1787 smac_47_16), 1788 ib_spec->eth.val.src_mac); 1789 1790 if (ib_spec->eth.mask.vlan_tag) { 1791 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1792 cvlan_tag, 1); 1793 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1794 cvlan_tag, 1); 1795 1796 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1797 first_vid, ntohs(ib_spec->eth.mask.vlan_tag)); 1798 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1799 first_vid, ntohs(ib_spec->eth.val.vlan_tag)); 1800 1801 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1802 first_cfi, 1803 ntohs(ib_spec->eth.mask.vlan_tag) >> 12); 1804 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1805 first_cfi, 1806 ntohs(ib_spec->eth.val.vlan_tag) >> 12); 1807 1808 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1809 first_prio, 1810 ntohs(ib_spec->eth.mask.vlan_tag) >> 13); 1811 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1812 first_prio, 1813 ntohs(ib_spec->eth.val.vlan_tag) >> 13); 1814 } 1815 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1816 ethertype, ntohs(ib_spec->eth.mask.ether_type)); 1817 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1818 ethertype, ntohs(ib_spec->eth.val.ether_type)); 1819 break; 1820 case IB_FLOW_SPEC_IPV4: 1821 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD)) 1822 return -EOPNOTSUPP; 1823 1824 if (match_ipv) { 1825 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1826 ip_version, 0xf); 1827 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1828 ip_version, IPV4_VERSION); 1829 } else { 1830 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1831 ethertype, 0xffff); 1832 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1833 ethertype, ETH_P_IP); 1834 } 1835 1836 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 1837 src_ipv4_src_ipv6.ipv4_layout.ipv4), 1838 &ib_spec->ipv4.mask.src_ip, 1839 sizeof(ib_spec->ipv4.mask.src_ip)); 1840 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1841 src_ipv4_src_ipv6.ipv4_layout.ipv4), 1842 &ib_spec->ipv4.val.src_ip, 1843 sizeof(ib_spec->ipv4.val.src_ip)); 1844 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 1845 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 1846 &ib_spec->ipv4.mask.dst_ip, 1847 sizeof(ib_spec->ipv4.mask.dst_ip)); 1848 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1849 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 1850 &ib_spec->ipv4.val.dst_ip, 1851 sizeof(ib_spec->ipv4.val.dst_ip)); 1852 1853 set_tos(headers_c, headers_v, 1854 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos); 1855 1856 set_proto(headers_c, headers_v, 1857 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto); 1858 break; 1859 case IB_FLOW_SPEC_IPV6: 1860 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD)) 1861 return -EOPNOTSUPP; 1862 1863 if (match_ipv) { 1864 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1865 ip_version, 0xf); 1866 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1867 ip_version, IPV6_VERSION); 1868 } else { 1869 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1870 ethertype, 0xffff); 1871 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1872 ethertype, ETH_P_IPV6); 1873 } 1874 1875 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 1876 src_ipv4_src_ipv6.ipv6_layout.ipv6), 1877 &ib_spec->ipv6.mask.src_ip, 1878 sizeof(ib_spec->ipv6.mask.src_ip)); 1879 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1880 src_ipv4_src_ipv6.ipv6_layout.ipv6), 1881 &ib_spec->ipv6.val.src_ip, 1882 sizeof(ib_spec->ipv6.val.src_ip)); 1883 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 1884 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 1885 &ib_spec->ipv6.mask.dst_ip, 1886 sizeof(ib_spec->ipv6.mask.dst_ip)); 1887 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1888 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 1889 &ib_spec->ipv6.val.dst_ip, 1890 sizeof(ib_spec->ipv6.val.dst_ip)); 1891 1892 set_tos(headers_c, headers_v, 1893 ib_spec->ipv6.mask.traffic_class, 1894 ib_spec->ipv6.val.traffic_class); 1895 1896 set_proto(headers_c, headers_v, 1897 ib_spec->ipv6.mask.next_hdr, 1898 ib_spec->ipv6.val.next_hdr); 1899 1900 set_flow_label(misc_params_c, misc_params_v, 1901 ntohl(ib_spec->ipv6.mask.flow_label), 1902 ntohl(ib_spec->ipv6.val.flow_label), 1903 ib_spec->type & IB_FLOW_SPEC_INNER); 1904 1905 break; 1906 case IB_FLOW_SPEC_TCP: 1907 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 1908 LAST_TCP_UDP_FIELD)) 1909 return -EOPNOTSUPP; 1910 1911 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol, 1912 0xff); 1913 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, 1914 IPPROTO_TCP); 1915 1916 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport, 1917 ntohs(ib_spec->tcp_udp.mask.src_port)); 1918 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport, 1919 ntohs(ib_spec->tcp_udp.val.src_port)); 1920 1921 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport, 1922 ntohs(ib_spec->tcp_udp.mask.dst_port)); 1923 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport, 1924 ntohs(ib_spec->tcp_udp.val.dst_port)); 1925 break; 1926 case IB_FLOW_SPEC_UDP: 1927 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 1928 LAST_TCP_UDP_FIELD)) 1929 return -EOPNOTSUPP; 1930 1931 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol, 1932 0xff); 1933 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, 1934 IPPROTO_UDP); 1935 1936 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport, 1937 ntohs(ib_spec->tcp_udp.mask.src_port)); 1938 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport, 1939 ntohs(ib_spec->tcp_udp.val.src_port)); 1940 1941 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport, 1942 ntohs(ib_spec->tcp_udp.mask.dst_port)); 1943 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, 1944 ntohs(ib_spec->tcp_udp.val.dst_port)); 1945 break; 1946 case IB_FLOW_SPEC_VXLAN_TUNNEL: 1947 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask, 1948 LAST_TUNNEL_FIELD)) 1949 return -EOPNOTSUPP; 1950 1951 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni, 1952 ntohl(ib_spec->tunnel.mask.tunnel_id)); 1953 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni, 1954 ntohl(ib_spec->tunnel.val.tunnel_id)); 1955 break; 1956 case IB_FLOW_SPEC_ACTION_TAG: 1957 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag, 1958 LAST_FLOW_TAG_FIELD)) 1959 return -EOPNOTSUPP; 1960 if (ib_spec->flow_tag.tag_id >= BIT(24)) 1961 return -EINVAL; 1962 1963 *tag_id = ib_spec->flow_tag.tag_id; 1964 break; 1965 case IB_FLOW_SPEC_ACTION_DROP: 1966 if (FIELDS_NOT_SUPPORTED(ib_spec->drop, 1967 LAST_DROP_FIELD)) 1968 return -EOPNOTSUPP; 1969 *is_drop = true; 1970 break; 1971 default: 1972 return -EINVAL; 1973 } 1974 1975 return 0; 1976 } 1977 1978 /* If a flow could catch both multicast and unicast packets, 1979 * it won't fall into the multicast flow steering table and this rule 1980 * could steal other multicast packets. 1981 */ 1982 static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr) 1983 { 1984 struct ib_flow_spec_eth *eth_spec; 1985 1986 if (ib_attr->type != IB_FLOW_ATTR_NORMAL || 1987 ib_attr->size < sizeof(struct ib_flow_attr) + 1988 sizeof(struct ib_flow_spec_eth) || 1989 ib_attr->num_of_specs < 1) 1990 return false; 1991 1992 eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1); 1993 if (eth_spec->type != IB_FLOW_SPEC_ETH || 1994 eth_spec->size != sizeof(*eth_spec)) 1995 return false; 1996 1997 return is_multicast_ether_addr(eth_spec->mask.dst_mac) && 1998 is_multicast_ether_addr(eth_spec->val.dst_mac); 1999 } 2000 2001 static bool is_valid_ethertype(struct mlx5_core_dev *mdev, 2002 const struct ib_flow_attr *flow_attr, 2003 bool check_inner) 2004 { 2005 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1); 2006 int match_ipv = check_inner ? 2007 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2008 ft_field_support.inner_ip_version) : 2009 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2010 ft_field_support.outer_ip_version); 2011 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0; 2012 bool ipv4_spec_valid, ipv6_spec_valid; 2013 unsigned int ip_spec_type = 0; 2014 bool has_ethertype = false; 2015 unsigned int spec_index; 2016 bool mask_valid = true; 2017 u16 eth_type = 0; 2018 bool type_valid; 2019 2020 /* Validate that ethertype is correct */ 2021 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 2022 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) && 2023 ib_spec->eth.mask.ether_type) { 2024 mask_valid = (ib_spec->eth.mask.ether_type == 2025 htons(0xffff)); 2026 has_ethertype = true; 2027 eth_type = ntohs(ib_spec->eth.val.ether_type); 2028 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) || 2029 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) { 2030 ip_spec_type = ib_spec->type; 2031 } 2032 ib_spec = (void *)ib_spec + ib_spec->size; 2033 } 2034 2035 type_valid = (!has_ethertype) || (!ip_spec_type); 2036 if (!type_valid && mask_valid) { 2037 ipv4_spec_valid = (eth_type == ETH_P_IP) && 2038 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit)); 2039 ipv6_spec_valid = (eth_type == ETH_P_IPV6) && 2040 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit)); 2041 2042 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) || 2043 (((eth_type == ETH_P_MPLS_UC) || 2044 (eth_type == ETH_P_MPLS_MC)) && match_ipv); 2045 } 2046 2047 return type_valid; 2048 } 2049 2050 static bool is_valid_attr(struct mlx5_core_dev *mdev, 2051 const struct ib_flow_attr *flow_attr) 2052 { 2053 return is_valid_ethertype(mdev, flow_attr, false) && 2054 is_valid_ethertype(mdev, flow_attr, true); 2055 } 2056 2057 static void put_flow_table(struct mlx5_ib_dev *dev, 2058 struct mlx5_ib_flow_prio *prio, bool ft_added) 2059 { 2060 prio->refcount -= !!ft_added; 2061 if (!prio->refcount) { 2062 mlx5_destroy_flow_table(prio->flow_table); 2063 prio->flow_table = NULL; 2064 } 2065 } 2066 2067 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id) 2068 { 2069 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device); 2070 struct mlx5_ib_flow_handler *handler = container_of(flow_id, 2071 struct mlx5_ib_flow_handler, 2072 ibflow); 2073 struct mlx5_ib_flow_handler *iter, *tmp; 2074 2075 mutex_lock(&dev->flow_db.lock); 2076 2077 list_for_each_entry_safe(iter, tmp, &handler->list, list) { 2078 mlx5_del_flow_rules(iter->rule); 2079 put_flow_table(dev, iter->prio, true); 2080 list_del(&iter->list); 2081 kfree(iter); 2082 } 2083 2084 mlx5_del_flow_rules(handler->rule); 2085 put_flow_table(dev, handler->prio, true); 2086 mutex_unlock(&dev->flow_db.lock); 2087 2088 kfree(handler); 2089 2090 return 0; 2091 } 2092 2093 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap) 2094 { 2095 priority *= 2; 2096 if (!dont_trap) 2097 priority++; 2098 return priority; 2099 } 2100 2101 enum flow_table_type { 2102 MLX5_IB_FT_RX, 2103 MLX5_IB_FT_TX 2104 }; 2105 2106 #define MLX5_FS_MAX_TYPES 6 2107 #define MLX5_FS_MAX_ENTRIES BIT(16) 2108 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev, 2109 struct ib_flow_attr *flow_attr, 2110 enum flow_table_type ft_type) 2111 { 2112 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP; 2113 struct mlx5_flow_namespace *ns = NULL; 2114 struct mlx5_ib_flow_prio *prio; 2115 struct mlx5_flow_table *ft; 2116 int max_table_size; 2117 int num_entries; 2118 int num_groups; 2119 int priority; 2120 int err = 0; 2121 2122 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 2123 log_max_ft_size)); 2124 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 2125 if (flow_is_multicast_only(flow_attr) && 2126 !dont_trap) 2127 priority = MLX5_IB_FLOW_MCAST_PRIO; 2128 else 2129 priority = ib_prio_to_core_prio(flow_attr->priority, 2130 dont_trap); 2131 ns = mlx5_get_flow_namespace(dev->mdev, 2132 MLX5_FLOW_NAMESPACE_BYPASS); 2133 num_entries = MLX5_FS_MAX_ENTRIES; 2134 num_groups = MLX5_FS_MAX_TYPES; 2135 prio = &dev->flow_db.prios[priority]; 2136 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 2137 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 2138 ns = mlx5_get_flow_namespace(dev->mdev, 2139 MLX5_FLOW_NAMESPACE_LEFTOVERS); 2140 build_leftovers_ft_param(&priority, 2141 &num_entries, 2142 &num_groups); 2143 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO]; 2144 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 2145 if (!MLX5_CAP_FLOWTABLE(dev->mdev, 2146 allow_sniffer_and_nic_rx_shared_tir)) 2147 return ERR_PTR(-ENOTSUPP); 2148 2149 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ? 2150 MLX5_FLOW_NAMESPACE_SNIFFER_RX : 2151 MLX5_FLOW_NAMESPACE_SNIFFER_TX); 2152 2153 prio = &dev->flow_db.sniffer[ft_type]; 2154 priority = 0; 2155 num_entries = 1; 2156 num_groups = 1; 2157 } 2158 2159 if (!ns) 2160 return ERR_PTR(-ENOTSUPP); 2161 2162 if (num_entries > max_table_size) 2163 return ERR_PTR(-ENOMEM); 2164 2165 ft = prio->flow_table; 2166 if (!ft) { 2167 ft = mlx5_create_auto_grouped_flow_table(ns, priority, 2168 num_entries, 2169 num_groups, 2170 0, 0); 2171 2172 if (!IS_ERR(ft)) { 2173 prio->refcount = 0; 2174 prio->flow_table = ft; 2175 } else { 2176 err = PTR_ERR(ft); 2177 } 2178 } 2179 2180 return err ? ERR_PTR(err) : prio; 2181 } 2182 2183 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev, 2184 struct mlx5_ib_flow_prio *ft_prio, 2185 const struct ib_flow_attr *flow_attr, 2186 struct mlx5_flow_destination *dst) 2187 { 2188 struct mlx5_flow_table *ft = ft_prio->flow_table; 2189 struct mlx5_ib_flow_handler *handler; 2190 struct mlx5_flow_act flow_act = {0}; 2191 struct mlx5_flow_spec *spec; 2192 struct mlx5_flow_destination *rule_dst = dst; 2193 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr); 2194 unsigned int spec_index; 2195 u32 flow_tag = MLX5_FS_DEFAULT_FLOW_TAG; 2196 bool is_drop = false; 2197 int err = 0; 2198 int dest_num = 1; 2199 2200 if (!is_valid_attr(dev->mdev, flow_attr)) 2201 return ERR_PTR(-EINVAL); 2202 2203 spec = mlx5_vzalloc(sizeof(*spec)); 2204 handler = kzalloc(sizeof(*handler), GFP_KERNEL); 2205 if (!handler || !spec) { 2206 err = -ENOMEM; 2207 goto free; 2208 } 2209 2210 INIT_LIST_HEAD(&handler->list); 2211 2212 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 2213 err = parse_flow_attr(dev->mdev, spec->match_criteria, 2214 spec->match_value, 2215 ib_flow, &flow_tag, &is_drop); 2216 if (err < 0) 2217 goto free; 2218 2219 ib_flow += ((union ib_flow_spec *)ib_flow)->size; 2220 } 2221 2222 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria); 2223 if (is_drop) { 2224 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_DROP; 2225 rule_dst = NULL; 2226 dest_num = 0; 2227 } else { 2228 flow_act.action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST : 2229 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO; 2230 } 2231 2232 if (flow_tag != MLX5_FS_DEFAULT_FLOW_TAG && 2233 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 2234 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) { 2235 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n", 2236 flow_tag, flow_attr->type); 2237 err = -EINVAL; 2238 goto free; 2239 } 2240 flow_act.flow_tag = flow_tag; 2241 handler->rule = mlx5_add_flow_rules(ft, spec, 2242 &flow_act, 2243 rule_dst, dest_num); 2244 2245 if (IS_ERR(handler->rule)) { 2246 err = PTR_ERR(handler->rule); 2247 goto free; 2248 } 2249 2250 ft_prio->refcount++; 2251 handler->prio = ft_prio; 2252 2253 ft_prio->flow_table = ft; 2254 free: 2255 if (err) 2256 kfree(handler); 2257 kvfree(spec); 2258 return err ? ERR_PTR(err) : handler; 2259 } 2260 2261 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev, 2262 struct mlx5_ib_flow_prio *ft_prio, 2263 struct ib_flow_attr *flow_attr, 2264 struct mlx5_flow_destination *dst) 2265 { 2266 struct mlx5_ib_flow_handler *handler_dst = NULL; 2267 struct mlx5_ib_flow_handler *handler = NULL; 2268 2269 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL); 2270 if (!IS_ERR(handler)) { 2271 handler_dst = create_flow_rule(dev, ft_prio, 2272 flow_attr, dst); 2273 if (IS_ERR(handler_dst)) { 2274 mlx5_del_flow_rules(handler->rule); 2275 ft_prio->refcount--; 2276 kfree(handler); 2277 handler = handler_dst; 2278 } else { 2279 list_add(&handler_dst->list, &handler->list); 2280 } 2281 } 2282 2283 return handler; 2284 } 2285 enum { 2286 LEFTOVERS_MC, 2287 LEFTOVERS_UC, 2288 }; 2289 2290 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev, 2291 struct mlx5_ib_flow_prio *ft_prio, 2292 struct ib_flow_attr *flow_attr, 2293 struct mlx5_flow_destination *dst) 2294 { 2295 struct mlx5_ib_flow_handler *handler_ucast = NULL; 2296 struct mlx5_ib_flow_handler *handler = NULL; 2297 2298 static struct { 2299 struct ib_flow_attr flow_attr; 2300 struct ib_flow_spec_eth eth_flow; 2301 } leftovers_specs[] = { 2302 [LEFTOVERS_MC] = { 2303 .flow_attr = { 2304 .num_of_specs = 1, 2305 .size = sizeof(leftovers_specs[0]) 2306 }, 2307 .eth_flow = { 2308 .type = IB_FLOW_SPEC_ETH, 2309 .size = sizeof(struct ib_flow_spec_eth), 2310 .mask = {.dst_mac = {0x1} }, 2311 .val = {.dst_mac = {0x1} } 2312 } 2313 }, 2314 [LEFTOVERS_UC] = { 2315 .flow_attr = { 2316 .num_of_specs = 1, 2317 .size = sizeof(leftovers_specs[0]) 2318 }, 2319 .eth_flow = { 2320 .type = IB_FLOW_SPEC_ETH, 2321 .size = sizeof(struct ib_flow_spec_eth), 2322 .mask = {.dst_mac = {0x1} }, 2323 .val = {.dst_mac = {} } 2324 } 2325 } 2326 }; 2327 2328 handler = create_flow_rule(dev, ft_prio, 2329 &leftovers_specs[LEFTOVERS_MC].flow_attr, 2330 dst); 2331 if (!IS_ERR(handler) && 2332 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) { 2333 handler_ucast = create_flow_rule(dev, ft_prio, 2334 &leftovers_specs[LEFTOVERS_UC].flow_attr, 2335 dst); 2336 if (IS_ERR(handler_ucast)) { 2337 mlx5_del_flow_rules(handler->rule); 2338 ft_prio->refcount--; 2339 kfree(handler); 2340 handler = handler_ucast; 2341 } else { 2342 list_add(&handler_ucast->list, &handler->list); 2343 } 2344 } 2345 2346 return handler; 2347 } 2348 2349 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev, 2350 struct mlx5_ib_flow_prio *ft_rx, 2351 struct mlx5_ib_flow_prio *ft_tx, 2352 struct mlx5_flow_destination *dst) 2353 { 2354 struct mlx5_ib_flow_handler *handler_rx; 2355 struct mlx5_ib_flow_handler *handler_tx; 2356 int err; 2357 static const struct ib_flow_attr flow_attr = { 2358 .num_of_specs = 0, 2359 .size = sizeof(flow_attr) 2360 }; 2361 2362 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst); 2363 if (IS_ERR(handler_rx)) { 2364 err = PTR_ERR(handler_rx); 2365 goto err; 2366 } 2367 2368 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst); 2369 if (IS_ERR(handler_tx)) { 2370 err = PTR_ERR(handler_tx); 2371 goto err_tx; 2372 } 2373 2374 list_add(&handler_tx->list, &handler_rx->list); 2375 2376 return handler_rx; 2377 2378 err_tx: 2379 mlx5_del_flow_rules(handler_rx->rule); 2380 ft_rx->refcount--; 2381 kfree(handler_rx); 2382 err: 2383 return ERR_PTR(err); 2384 } 2385 2386 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp, 2387 struct ib_flow_attr *flow_attr, 2388 int domain) 2389 { 2390 struct mlx5_ib_dev *dev = to_mdev(qp->device); 2391 struct mlx5_ib_qp *mqp = to_mqp(qp); 2392 struct mlx5_ib_flow_handler *handler = NULL; 2393 struct mlx5_flow_destination *dst = NULL; 2394 struct mlx5_ib_flow_prio *ft_prio_tx = NULL; 2395 struct mlx5_ib_flow_prio *ft_prio; 2396 int err; 2397 2398 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) 2399 return ERR_PTR(-ENOMEM); 2400 2401 if (domain != IB_FLOW_DOMAIN_USER || 2402 flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) || 2403 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP)) 2404 return ERR_PTR(-EINVAL); 2405 2406 dst = kzalloc(sizeof(*dst), GFP_KERNEL); 2407 if (!dst) 2408 return ERR_PTR(-ENOMEM); 2409 2410 mutex_lock(&dev->flow_db.lock); 2411 2412 ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX); 2413 if (IS_ERR(ft_prio)) { 2414 err = PTR_ERR(ft_prio); 2415 goto unlock; 2416 } 2417 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 2418 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX); 2419 if (IS_ERR(ft_prio_tx)) { 2420 err = PTR_ERR(ft_prio_tx); 2421 ft_prio_tx = NULL; 2422 goto destroy_ft; 2423 } 2424 } 2425 2426 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR; 2427 if (mqp->flags & MLX5_IB_QP_RSS) 2428 dst->tir_num = mqp->rss_qp.tirn; 2429 else 2430 dst->tir_num = mqp->raw_packet_qp.rq.tirn; 2431 2432 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 2433 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) { 2434 handler = create_dont_trap_rule(dev, ft_prio, 2435 flow_attr, dst); 2436 } else { 2437 handler = create_flow_rule(dev, ft_prio, flow_attr, 2438 dst); 2439 } 2440 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 2441 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 2442 handler = create_leftovers_rule(dev, ft_prio, flow_attr, 2443 dst); 2444 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 2445 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst); 2446 } else { 2447 err = -EINVAL; 2448 goto destroy_ft; 2449 } 2450 2451 if (IS_ERR(handler)) { 2452 err = PTR_ERR(handler); 2453 handler = NULL; 2454 goto destroy_ft; 2455 } 2456 2457 mutex_unlock(&dev->flow_db.lock); 2458 kfree(dst); 2459 2460 return &handler->ibflow; 2461 2462 destroy_ft: 2463 put_flow_table(dev, ft_prio, false); 2464 if (ft_prio_tx) 2465 put_flow_table(dev, ft_prio_tx, false); 2466 unlock: 2467 mutex_unlock(&dev->flow_db.lock); 2468 kfree(dst); 2469 kfree(handler); 2470 return ERR_PTR(err); 2471 } 2472 2473 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2474 { 2475 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2476 int err; 2477 2478 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num); 2479 if (err) 2480 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 2481 ibqp->qp_num, gid->raw); 2482 2483 return err; 2484 } 2485 2486 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2487 { 2488 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2489 int err; 2490 2491 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num); 2492 if (err) 2493 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 2494 ibqp->qp_num, gid->raw); 2495 2496 return err; 2497 } 2498 2499 static int init_node_data(struct mlx5_ib_dev *dev) 2500 { 2501 int err; 2502 2503 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 2504 if (err) 2505 return err; 2506 2507 dev->mdev->rev_id = dev->mdev->pdev->revision; 2508 2509 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 2510 } 2511 2512 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr, 2513 char *buf) 2514 { 2515 struct mlx5_ib_dev *dev = 2516 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2517 2518 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages); 2519 } 2520 2521 static ssize_t show_reg_pages(struct device *device, 2522 struct device_attribute *attr, char *buf) 2523 { 2524 struct mlx5_ib_dev *dev = 2525 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2526 2527 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 2528 } 2529 2530 static ssize_t show_hca(struct device *device, struct device_attribute *attr, 2531 char *buf) 2532 { 2533 struct mlx5_ib_dev *dev = 2534 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2535 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device); 2536 } 2537 2538 static ssize_t show_rev(struct device *device, struct device_attribute *attr, 2539 char *buf) 2540 { 2541 struct mlx5_ib_dev *dev = 2542 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2543 return sprintf(buf, "%x\n", dev->mdev->rev_id); 2544 } 2545 2546 static ssize_t show_board(struct device *device, struct device_attribute *attr, 2547 char *buf) 2548 { 2549 struct mlx5_ib_dev *dev = 2550 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2551 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 2552 dev->mdev->board_id); 2553 } 2554 2555 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL); 2556 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL); 2557 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL); 2558 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL); 2559 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL); 2560 2561 static struct device_attribute *mlx5_class_attributes[] = { 2562 &dev_attr_hw_rev, 2563 &dev_attr_hca_type, 2564 &dev_attr_board_id, 2565 &dev_attr_fw_pages, 2566 &dev_attr_reg_pages, 2567 }; 2568 2569 static void pkey_change_handler(struct work_struct *work) 2570 { 2571 struct mlx5_ib_port_resources *ports = 2572 container_of(work, struct mlx5_ib_port_resources, 2573 pkey_change_work); 2574 2575 mutex_lock(&ports->devr->mutex); 2576 mlx5_ib_gsi_pkey_change(ports->gsi); 2577 mutex_unlock(&ports->devr->mutex); 2578 } 2579 2580 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 2581 { 2582 struct mlx5_ib_qp *mqp; 2583 struct mlx5_ib_cq *send_mcq, *recv_mcq; 2584 struct mlx5_core_cq *mcq; 2585 struct list_head cq_armed_list; 2586 unsigned long flags_qp; 2587 unsigned long flags_cq; 2588 unsigned long flags; 2589 2590 INIT_LIST_HEAD(&cq_armed_list); 2591 2592 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 2593 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 2594 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 2595 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 2596 if (mqp->sq.tail != mqp->sq.head) { 2597 send_mcq = to_mcq(mqp->ibqp.send_cq); 2598 spin_lock_irqsave(&send_mcq->lock, flags_cq); 2599 if (send_mcq->mcq.comp && 2600 mqp->ibqp.send_cq->comp_handler) { 2601 if (!send_mcq->mcq.reset_notify_added) { 2602 send_mcq->mcq.reset_notify_added = 1; 2603 list_add_tail(&send_mcq->mcq.reset_notify, 2604 &cq_armed_list); 2605 } 2606 } 2607 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 2608 } 2609 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 2610 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 2611 /* no handling is needed for SRQ */ 2612 if (!mqp->ibqp.srq) { 2613 if (mqp->rq.tail != mqp->rq.head) { 2614 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 2615 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 2616 if (recv_mcq->mcq.comp && 2617 mqp->ibqp.recv_cq->comp_handler) { 2618 if (!recv_mcq->mcq.reset_notify_added) { 2619 recv_mcq->mcq.reset_notify_added = 1; 2620 list_add_tail(&recv_mcq->mcq.reset_notify, 2621 &cq_armed_list); 2622 } 2623 } 2624 spin_unlock_irqrestore(&recv_mcq->lock, 2625 flags_cq); 2626 } 2627 } 2628 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 2629 } 2630 /*At that point all inflight post send were put to be executed as of we 2631 * lock/unlock above locks Now need to arm all involved CQs. 2632 */ 2633 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 2634 mcq->comp(mcq); 2635 } 2636 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 2637 } 2638 2639 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context, 2640 enum mlx5_dev_event event, unsigned long param) 2641 { 2642 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context; 2643 struct ib_event ibev; 2644 bool fatal = false; 2645 u8 port = 0; 2646 2647 switch (event) { 2648 case MLX5_DEV_EVENT_SYS_ERROR: 2649 ibev.event = IB_EVENT_DEVICE_FATAL; 2650 mlx5_ib_handle_internal_error(ibdev); 2651 fatal = true; 2652 break; 2653 2654 case MLX5_DEV_EVENT_PORT_UP: 2655 case MLX5_DEV_EVENT_PORT_DOWN: 2656 case MLX5_DEV_EVENT_PORT_INITIALIZED: 2657 port = (u8)param; 2658 2659 /* In RoCE, port up/down events are handled in 2660 * mlx5_netdev_event(). 2661 */ 2662 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2663 IB_LINK_LAYER_ETHERNET) 2664 return; 2665 2666 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ? 2667 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 2668 break; 2669 2670 case MLX5_DEV_EVENT_LID_CHANGE: 2671 ibev.event = IB_EVENT_LID_CHANGE; 2672 port = (u8)param; 2673 break; 2674 2675 case MLX5_DEV_EVENT_PKEY_CHANGE: 2676 ibev.event = IB_EVENT_PKEY_CHANGE; 2677 port = (u8)param; 2678 2679 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 2680 break; 2681 2682 case MLX5_DEV_EVENT_GUID_CHANGE: 2683 ibev.event = IB_EVENT_GID_CHANGE; 2684 port = (u8)param; 2685 break; 2686 2687 case MLX5_DEV_EVENT_CLIENT_REREG: 2688 ibev.event = IB_EVENT_CLIENT_REREGISTER; 2689 port = (u8)param; 2690 break; 2691 default: 2692 return; 2693 } 2694 2695 ibev.device = &ibdev->ib_dev; 2696 ibev.element.port_num = port; 2697 2698 if (port < 1 || port > ibdev->num_ports) { 2699 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port); 2700 return; 2701 } 2702 2703 if (ibdev->ib_active) 2704 ib_dispatch_event(&ibev); 2705 2706 if (fatal) 2707 ibdev->ib_active = false; 2708 } 2709 2710 static int set_has_smi_cap(struct mlx5_ib_dev *dev) 2711 { 2712 struct mlx5_hca_vport_context vport_ctx; 2713 int err; 2714 int port; 2715 2716 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) { 2717 dev->mdev->port_caps[port - 1].has_smi = false; 2718 if (MLX5_CAP_GEN(dev->mdev, port_type) == 2719 MLX5_CAP_PORT_TYPE_IB) { 2720 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) { 2721 err = mlx5_query_hca_vport_context(dev->mdev, 0, 2722 port, 0, 2723 &vport_ctx); 2724 if (err) { 2725 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n", 2726 port, err); 2727 return err; 2728 } 2729 dev->mdev->port_caps[port - 1].has_smi = 2730 vport_ctx.has_smi; 2731 } else { 2732 dev->mdev->port_caps[port - 1].has_smi = true; 2733 } 2734 } 2735 } 2736 return 0; 2737 } 2738 2739 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 2740 { 2741 int port; 2742 2743 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) 2744 mlx5_query_ext_port_caps(dev, port); 2745 } 2746 2747 static int get_port_caps(struct mlx5_ib_dev *dev) 2748 { 2749 struct ib_device_attr *dprops = NULL; 2750 struct ib_port_attr *pprops = NULL; 2751 int err = -ENOMEM; 2752 int port; 2753 struct ib_udata uhw = {.inlen = 0, .outlen = 0}; 2754 2755 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL); 2756 if (!pprops) 2757 goto out; 2758 2759 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL); 2760 if (!dprops) 2761 goto out; 2762 2763 err = set_has_smi_cap(dev); 2764 if (err) 2765 goto out; 2766 2767 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw); 2768 if (err) { 2769 mlx5_ib_warn(dev, "query_device failed %d\n", err); 2770 goto out; 2771 } 2772 2773 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) { 2774 memset(pprops, 0, sizeof(*pprops)); 2775 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops); 2776 if (err) { 2777 mlx5_ib_warn(dev, "query_port %d failed %d\n", 2778 port, err); 2779 break; 2780 } 2781 dev->mdev->port_caps[port - 1].pkey_table_len = 2782 dprops->max_pkeys; 2783 dev->mdev->port_caps[port - 1].gid_table_len = 2784 pprops->gid_tbl_len; 2785 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n", 2786 dprops->max_pkeys, pprops->gid_tbl_len); 2787 } 2788 2789 out: 2790 kfree(pprops); 2791 kfree(dprops); 2792 2793 return err; 2794 } 2795 2796 static void destroy_umrc_res(struct mlx5_ib_dev *dev) 2797 { 2798 int err; 2799 2800 err = mlx5_mr_cache_cleanup(dev); 2801 if (err) 2802 mlx5_ib_warn(dev, "mr cache cleanup failed\n"); 2803 2804 mlx5_ib_destroy_qp(dev->umrc.qp); 2805 ib_free_cq(dev->umrc.cq); 2806 ib_dealloc_pd(dev->umrc.pd); 2807 } 2808 2809 enum { 2810 MAX_UMR_WR = 128, 2811 }; 2812 2813 static int create_umr_res(struct mlx5_ib_dev *dev) 2814 { 2815 struct ib_qp_init_attr *init_attr = NULL; 2816 struct ib_qp_attr *attr = NULL; 2817 struct ib_pd *pd; 2818 struct ib_cq *cq; 2819 struct ib_qp *qp; 2820 int ret; 2821 2822 attr = kzalloc(sizeof(*attr), GFP_KERNEL); 2823 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL); 2824 if (!attr || !init_attr) { 2825 ret = -ENOMEM; 2826 goto error_0; 2827 } 2828 2829 pd = ib_alloc_pd(&dev->ib_dev, 0); 2830 if (IS_ERR(pd)) { 2831 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n"); 2832 ret = PTR_ERR(pd); 2833 goto error_0; 2834 } 2835 2836 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ); 2837 if (IS_ERR(cq)) { 2838 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n"); 2839 ret = PTR_ERR(cq); 2840 goto error_2; 2841 } 2842 2843 init_attr->send_cq = cq; 2844 init_attr->recv_cq = cq; 2845 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR; 2846 init_attr->cap.max_send_wr = MAX_UMR_WR; 2847 init_attr->cap.max_send_sge = 1; 2848 init_attr->qp_type = MLX5_IB_QPT_REG_UMR; 2849 init_attr->port_num = 1; 2850 qp = mlx5_ib_create_qp(pd, init_attr, NULL); 2851 if (IS_ERR(qp)) { 2852 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n"); 2853 ret = PTR_ERR(qp); 2854 goto error_3; 2855 } 2856 qp->device = &dev->ib_dev; 2857 qp->real_qp = qp; 2858 qp->uobject = NULL; 2859 qp->qp_type = MLX5_IB_QPT_REG_UMR; 2860 2861 attr->qp_state = IB_QPS_INIT; 2862 attr->port_num = 1; 2863 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX | 2864 IB_QP_PORT, NULL); 2865 if (ret) { 2866 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n"); 2867 goto error_4; 2868 } 2869 2870 memset(attr, 0, sizeof(*attr)); 2871 attr->qp_state = IB_QPS_RTR; 2872 attr->path_mtu = IB_MTU_256; 2873 2874 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 2875 if (ret) { 2876 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n"); 2877 goto error_4; 2878 } 2879 2880 memset(attr, 0, sizeof(*attr)); 2881 attr->qp_state = IB_QPS_RTS; 2882 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 2883 if (ret) { 2884 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n"); 2885 goto error_4; 2886 } 2887 2888 dev->umrc.qp = qp; 2889 dev->umrc.cq = cq; 2890 dev->umrc.pd = pd; 2891 2892 sema_init(&dev->umrc.sem, MAX_UMR_WR); 2893 ret = mlx5_mr_cache_init(dev); 2894 if (ret) { 2895 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 2896 goto error_4; 2897 } 2898 2899 kfree(attr); 2900 kfree(init_attr); 2901 2902 return 0; 2903 2904 error_4: 2905 mlx5_ib_destroy_qp(qp); 2906 2907 error_3: 2908 ib_free_cq(cq); 2909 2910 error_2: 2911 ib_dealloc_pd(pd); 2912 2913 error_0: 2914 kfree(attr); 2915 kfree(init_attr); 2916 return ret; 2917 } 2918 2919 static int create_dev_resources(struct mlx5_ib_resources *devr) 2920 { 2921 struct ib_srq_init_attr attr; 2922 struct mlx5_ib_dev *dev; 2923 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 2924 int port; 2925 int ret = 0; 2926 2927 dev = container_of(devr, struct mlx5_ib_dev, devr); 2928 2929 mutex_init(&devr->mutex); 2930 2931 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL); 2932 if (IS_ERR(devr->p0)) { 2933 ret = PTR_ERR(devr->p0); 2934 goto error0; 2935 } 2936 devr->p0->device = &dev->ib_dev; 2937 devr->p0->uobject = NULL; 2938 atomic_set(&devr->p0->usecnt, 0); 2939 2940 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL); 2941 if (IS_ERR(devr->c0)) { 2942 ret = PTR_ERR(devr->c0); 2943 goto error1; 2944 } 2945 devr->c0->device = &dev->ib_dev; 2946 devr->c0->uobject = NULL; 2947 devr->c0->comp_handler = NULL; 2948 devr->c0->event_handler = NULL; 2949 devr->c0->cq_context = NULL; 2950 atomic_set(&devr->c0->usecnt, 0); 2951 2952 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 2953 if (IS_ERR(devr->x0)) { 2954 ret = PTR_ERR(devr->x0); 2955 goto error2; 2956 } 2957 devr->x0->device = &dev->ib_dev; 2958 devr->x0->inode = NULL; 2959 atomic_set(&devr->x0->usecnt, 0); 2960 mutex_init(&devr->x0->tgt_qp_mutex); 2961 INIT_LIST_HEAD(&devr->x0->tgt_qp_list); 2962 2963 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 2964 if (IS_ERR(devr->x1)) { 2965 ret = PTR_ERR(devr->x1); 2966 goto error3; 2967 } 2968 devr->x1->device = &dev->ib_dev; 2969 devr->x1->inode = NULL; 2970 atomic_set(&devr->x1->usecnt, 0); 2971 mutex_init(&devr->x1->tgt_qp_mutex); 2972 INIT_LIST_HEAD(&devr->x1->tgt_qp_list); 2973 2974 memset(&attr, 0, sizeof(attr)); 2975 attr.attr.max_sge = 1; 2976 attr.attr.max_wr = 1; 2977 attr.srq_type = IB_SRQT_XRC; 2978 attr.ext.xrc.cq = devr->c0; 2979 attr.ext.xrc.xrcd = devr->x0; 2980 2981 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 2982 if (IS_ERR(devr->s0)) { 2983 ret = PTR_ERR(devr->s0); 2984 goto error4; 2985 } 2986 devr->s0->device = &dev->ib_dev; 2987 devr->s0->pd = devr->p0; 2988 devr->s0->uobject = NULL; 2989 devr->s0->event_handler = NULL; 2990 devr->s0->srq_context = NULL; 2991 devr->s0->srq_type = IB_SRQT_XRC; 2992 devr->s0->ext.xrc.xrcd = devr->x0; 2993 devr->s0->ext.xrc.cq = devr->c0; 2994 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt); 2995 atomic_inc(&devr->s0->ext.xrc.cq->usecnt); 2996 atomic_inc(&devr->p0->usecnt); 2997 atomic_set(&devr->s0->usecnt, 0); 2998 2999 memset(&attr, 0, sizeof(attr)); 3000 attr.attr.max_sge = 1; 3001 attr.attr.max_wr = 1; 3002 attr.srq_type = IB_SRQT_BASIC; 3003 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 3004 if (IS_ERR(devr->s1)) { 3005 ret = PTR_ERR(devr->s1); 3006 goto error5; 3007 } 3008 devr->s1->device = &dev->ib_dev; 3009 devr->s1->pd = devr->p0; 3010 devr->s1->uobject = NULL; 3011 devr->s1->event_handler = NULL; 3012 devr->s1->srq_context = NULL; 3013 devr->s1->srq_type = IB_SRQT_BASIC; 3014 devr->s1->ext.xrc.cq = devr->c0; 3015 atomic_inc(&devr->p0->usecnt); 3016 atomic_set(&devr->s0->usecnt, 0); 3017 3018 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) { 3019 INIT_WORK(&devr->ports[port].pkey_change_work, 3020 pkey_change_handler); 3021 devr->ports[port].devr = devr; 3022 } 3023 3024 return 0; 3025 3026 error5: 3027 mlx5_ib_destroy_srq(devr->s0); 3028 error4: 3029 mlx5_ib_dealloc_xrcd(devr->x1); 3030 error3: 3031 mlx5_ib_dealloc_xrcd(devr->x0); 3032 error2: 3033 mlx5_ib_destroy_cq(devr->c0); 3034 error1: 3035 mlx5_ib_dealloc_pd(devr->p0); 3036 error0: 3037 return ret; 3038 } 3039 3040 static void destroy_dev_resources(struct mlx5_ib_resources *devr) 3041 { 3042 struct mlx5_ib_dev *dev = 3043 container_of(devr, struct mlx5_ib_dev, devr); 3044 int port; 3045 3046 mlx5_ib_destroy_srq(devr->s1); 3047 mlx5_ib_destroy_srq(devr->s0); 3048 mlx5_ib_dealloc_xrcd(devr->x0); 3049 mlx5_ib_dealloc_xrcd(devr->x1); 3050 mlx5_ib_destroy_cq(devr->c0); 3051 mlx5_ib_dealloc_pd(devr->p0); 3052 3053 /* Make sure no change P_Key work items are still executing */ 3054 for (port = 0; port < dev->num_ports; ++port) 3055 cancel_work_sync(&devr->ports[port].pkey_change_work); 3056 } 3057 3058 static u32 get_core_cap_flags(struct ib_device *ibdev) 3059 { 3060 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3061 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 3062 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 3063 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 3064 u32 ret = 0; 3065 3066 if (ll == IB_LINK_LAYER_INFINIBAND) 3067 return RDMA_CORE_PORT_IBA_IB; 3068 3069 ret = RDMA_CORE_PORT_RAW_PACKET; 3070 3071 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 3072 return ret; 3073 3074 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 3075 return ret; 3076 3077 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 3078 ret |= RDMA_CORE_PORT_IBA_ROCE; 3079 3080 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 3081 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 3082 3083 return ret; 3084 } 3085 3086 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num, 3087 struct ib_port_immutable *immutable) 3088 { 3089 struct ib_port_attr attr; 3090 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3091 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num); 3092 int err; 3093 3094 immutable->core_cap_flags = get_core_cap_flags(ibdev); 3095 3096 err = ib_query_port(ibdev, port_num, &attr); 3097 if (err) 3098 return err; 3099 3100 immutable->pkey_tbl_len = attr.pkey_tbl_len; 3101 immutable->gid_tbl_len = attr.gid_tbl_len; 3102 immutable->core_cap_flags = get_core_cap_flags(ibdev); 3103 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce)) 3104 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 3105 3106 return 0; 3107 } 3108 3109 static void get_dev_fw_str(struct ib_device *ibdev, char *str, 3110 size_t str_len) 3111 { 3112 struct mlx5_ib_dev *dev = 3113 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 3114 snprintf(str, str_len, "%d.%d.%04d", fw_rev_maj(dev->mdev), 3115 fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev)); 3116 } 3117 3118 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev) 3119 { 3120 struct mlx5_core_dev *mdev = dev->mdev; 3121 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev, 3122 MLX5_FLOW_NAMESPACE_LAG); 3123 struct mlx5_flow_table *ft; 3124 int err; 3125 3126 if (!ns || !mlx5_lag_is_active(mdev)) 3127 return 0; 3128 3129 err = mlx5_cmd_create_vport_lag(mdev); 3130 if (err) 3131 return err; 3132 3133 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0); 3134 if (IS_ERR(ft)) { 3135 err = PTR_ERR(ft); 3136 goto err_destroy_vport_lag; 3137 } 3138 3139 dev->flow_db.lag_demux_ft = ft; 3140 return 0; 3141 3142 err_destroy_vport_lag: 3143 mlx5_cmd_destroy_vport_lag(mdev); 3144 return err; 3145 } 3146 3147 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev) 3148 { 3149 struct mlx5_core_dev *mdev = dev->mdev; 3150 3151 if (dev->flow_db.lag_demux_ft) { 3152 mlx5_destroy_flow_table(dev->flow_db.lag_demux_ft); 3153 dev->flow_db.lag_demux_ft = NULL; 3154 3155 mlx5_cmd_destroy_vport_lag(mdev); 3156 } 3157 } 3158 3159 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev) 3160 { 3161 int err; 3162 3163 dev->roce.nb.notifier_call = mlx5_netdev_event; 3164 err = register_netdevice_notifier(&dev->roce.nb); 3165 if (err) { 3166 dev->roce.nb.notifier_call = NULL; 3167 return err; 3168 } 3169 3170 return 0; 3171 } 3172 3173 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev) 3174 { 3175 if (dev->roce.nb.notifier_call) { 3176 unregister_netdevice_notifier(&dev->roce.nb); 3177 dev->roce.nb.notifier_call = NULL; 3178 } 3179 } 3180 3181 static int mlx5_enable_eth(struct mlx5_ib_dev *dev) 3182 { 3183 int err; 3184 3185 err = mlx5_add_netdev_notifier(dev); 3186 if (err) 3187 return err; 3188 3189 if (MLX5_CAP_GEN(dev->mdev, roce)) { 3190 err = mlx5_nic_vport_enable_roce(dev->mdev); 3191 if (err) 3192 goto err_unregister_netdevice_notifier; 3193 } 3194 3195 err = mlx5_eth_lag_init(dev); 3196 if (err) 3197 goto err_disable_roce; 3198 3199 return 0; 3200 3201 err_disable_roce: 3202 if (MLX5_CAP_GEN(dev->mdev, roce)) 3203 mlx5_nic_vport_disable_roce(dev->mdev); 3204 3205 err_unregister_netdevice_notifier: 3206 mlx5_remove_netdev_notifier(dev); 3207 return err; 3208 } 3209 3210 static void mlx5_disable_eth(struct mlx5_ib_dev *dev) 3211 { 3212 mlx5_eth_lag_cleanup(dev); 3213 if (MLX5_CAP_GEN(dev->mdev, roce)) 3214 mlx5_nic_vport_disable_roce(dev->mdev); 3215 } 3216 3217 struct mlx5_ib_counter { 3218 const char *name; 3219 size_t offset; 3220 }; 3221 3222 #define INIT_Q_COUNTER(_name) \ 3223 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)} 3224 3225 static const struct mlx5_ib_counter basic_q_cnts[] = { 3226 INIT_Q_COUNTER(rx_write_requests), 3227 INIT_Q_COUNTER(rx_read_requests), 3228 INIT_Q_COUNTER(rx_atomic_requests), 3229 INIT_Q_COUNTER(out_of_buffer), 3230 }; 3231 3232 static const struct mlx5_ib_counter out_of_seq_q_cnts[] = { 3233 INIT_Q_COUNTER(out_of_sequence), 3234 }; 3235 3236 static const struct mlx5_ib_counter retrans_q_cnts[] = { 3237 INIT_Q_COUNTER(duplicate_request), 3238 INIT_Q_COUNTER(rnr_nak_retry_err), 3239 INIT_Q_COUNTER(packet_seq_err), 3240 INIT_Q_COUNTER(implied_nak_seq_err), 3241 INIT_Q_COUNTER(local_ack_timeout_err), 3242 }; 3243 3244 #define INIT_CONG_COUNTER(_name) \ 3245 { .name = #_name, .offset = \ 3246 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)} 3247 3248 static const struct mlx5_ib_counter cong_cnts[] = { 3249 INIT_CONG_COUNTER(rp_cnp_ignored), 3250 INIT_CONG_COUNTER(rp_cnp_handled), 3251 INIT_CONG_COUNTER(np_ecn_marked_roce_packets), 3252 INIT_CONG_COUNTER(np_cnp_sent), 3253 }; 3254 3255 static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev) 3256 { 3257 unsigned int i; 3258 3259 for (i = 0; i < dev->num_ports; i++) { 3260 mlx5_core_dealloc_q_counter(dev->mdev, 3261 dev->port[i].cnts.set_id); 3262 kfree(dev->port[i].cnts.names); 3263 kfree(dev->port[i].cnts.offsets); 3264 } 3265 } 3266 3267 static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev, 3268 struct mlx5_ib_counters *cnts) 3269 { 3270 u32 num_counters; 3271 3272 num_counters = ARRAY_SIZE(basic_q_cnts); 3273 3274 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) 3275 num_counters += ARRAY_SIZE(out_of_seq_q_cnts); 3276 3277 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) 3278 num_counters += ARRAY_SIZE(retrans_q_cnts); 3279 cnts->num_q_counters = num_counters; 3280 3281 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 3282 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts); 3283 num_counters += ARRAY_SIZE(cong_cnts); 3284 } 3285 3286 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL); 3287 if (!cnts->names) 3288 return -ENOMEM; 3289 3290 cnts->offsets = kcalloc(num_counters, 3291 sizeof(cnts->offsets), GFP_KERNEL); 3292 if (!cnts->offsets) 3293 goto err_names; 3294 3295 return 0; 3296 3297 err_names: 3298 kfree(cnts->names); 3299 return -ENOMEM; 3300 } 3301 3302 static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev, 3303 const char **names, 3304 size_t *offsets) 3305 { 3306 int i; 3307 int j = 0; 3308 3309 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) { 3310 names[j] = basic_q_cnts[i].name; 3311 offsets[j] = basic_q_cnts[i].offset; 3312 } 3313 3314 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) { 3315 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) { 3316 names[j] = out_of_seq_q_cnts[i].name; 3317 offsets[j] = out_of_seq_q_cnts[i].offset; 3318 } 3319 } 3320 3321 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) { 3322 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) { 3323 names[j] = retrans_q_cnts[i].name; 3324 offsets[j] = retrans_q_cnts[i].offset; 3325 } 3326 } 3327 3328 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 3329 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) { 3330 names[j] = cong_cnts[i].name; 3331 offsets[j] = cong_cnts[i].offset; 3332 } 3333 } 3334 } 3335 3336 static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev) 3337 { 3338 int i; 3339 int ret; 3340 3341 for (i = 0; i < dev->num_ports; i++) { 3342 struct mlx5_ib_port *port = &dev->port[i]; 3343 3344 ret = mlx5_core_alloc_q_counter(dev->mdev, 3345 &port->cnts.set_id); 3346 if (ret) { 3347 mlx5_ib_warn(dev, 3348 "couldn't allocate queue counter for port %d, err %d\n", 3349 i + 1, ret); 3350 goto dealloc_counters; 3351 } 3352 3353 ret = __mlx5_ib_alloc_counters(dev, &port->cnts); 3354 if (ret) 3355 goto dealloc_counters; 3356 3357 mlx5_ib_fill_counters(dev, port->cnts.names, 3358 port->cnts.offsets); 3359 } 3360 3361 return 0; 3362 3363 dealloc_counters: 3364 while (--i >= 0) 3365 mlx5_core_dealloc_q_counter(dev->mdev, 3366 dev->port[i].cnts.set_id); 3367 3368 return ret; 3369 } 3370 3371 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev, 3372 u8 port_num) 3373 { 3374 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3375 struct mlx5_ib_port *port = &dev->port[port_num - 1]; 3376 3377 /* We support only per port stats */ 3378 if (port_num == 0) 3379 return NULL; 3380 3381 return rdma_alloc_hw_stats_struct(port->cnts.names, 3382 port->cnts.num_q_counters + 3383 port->cnts.num_cong_counters, 3384 RDMA_HW_STATS_DEFAULT_LIFESPAN); 3385 } 3386 3387 static int mlx5_ib_query_q_counters(struct mlx5_ib_dev *dev, 3388 struct mlx5_ib_port *port, 3389 struct rdma_hw_stats *stats) 3390 { 3391 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out); 3392 void *out; 3393 __be32 val; 3394 int ret, i; 3395 3396 out = mlx5_vzalloc(outlen); 3397 if (!out) 3398 return -ENOMEM; 3399 3400 ret = mlx5_core_query_q_counter(dev->mdev, 3401 port->cnts.set_id, 0, 3402 out, outlen); 3403 if (ret) 3404 goto free; 3405 3406 for (i = 0; i < port->cnts.num_q_counters; i++) { 3407 val = *(__be32 *)(out + port->cnts.offsets[i]); 3408 stats->value[i] = (u64)be32_to_cpu(val); 3409 } 3410 3411 free: 3412 kvfree(out); 3413 return ret; 3414 } 3415 3416 static int mlx5_ib_query_cong_counters(struct mlx5_ib_dev *dev, 3417 struct mlx5_ib_port *port, 3418 struct rdma_hw_stats *stats) 3419 { 3420 int outlen = MLX5_ST_SZ_BYTES(query_cong_statistics_out); 3421 void *out; 3422 int ret, i; 3423 int offset = port->cnts.num_q_counters; 3424 3425 out = mlx5_vzalloc(outlen); 3426 if (!out) 3427 return -ENOMEM; 3428 3429 ret = mlx5_cmd_query_cong_counter(dev->mdev, false, out, outlen); 3430 if (ret) 3431 goto free; 3432 3433 for (i = 0; i < port->cnts.num_cong_counters; i++) { 3434 stats->value[i + offset] = 3435 be64_to_cpup((__be64 *)(out + 3436 port->cnts.offsets[i + offset])); 3437 } 3438 3439 free: 3440 kvfree(out); 3441 return ret; 3442 } 3443 3444 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev, 3445 struct rdma_hw_stats *stats, 3446 u8 port_num, int index) 3447 { 3448 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3449 struct mlx5_ib_port *port = &dev->port[port_num - 1]; 3450 int ret, num_counters; 3451 3452 if (!stats) 3453 return -EINVAL; 3454 3455 ret = mlx5_ib_query_q_counters(dev, port, stats); 3456 if (ret) 3457 return ret; 3458 num_counters = port->cnts.num_q_counters; 3459 3460 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 3461 ret = mlx5_ib_query_cong_counters(dev, port, stats); 3462 if (ret) 3463 return ret; 3464 num_counters += port->cnts.num_cong_counters; 3465 } 3466 3467 return num_counters; 3468 } 3469 3470 static void *mlx5_ib_add(struct mlx5_core_dev *mdev) 3471 { 3472 struct mlx5_ib_dev *dev; 3473 enum rdma_link_layer ll; 3474 int port_type_cap; 3475 const char *name; 3476 int err; 3477 int i; 3478 3479 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 3480 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 3481 3482 printk_once(KERN_INFO "%s", mlx5_version); 3483 3484 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev)); 3485 if (!dev) 3486 return NULL; 3487 3488 dev->mdev = mdev; 3489 3490 dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port), 3491 GFP_KERNEL); 3492 if (!dev->port) 3493 goto err_dealloc; 3494 3495 rwlock_init(&dev->roce.netdev_lock); 3496 err = get_port_caps(dev); 3497 if (err) 3498 goto err_free_port; 3499 3500 if (mlx5_use_mad_ifc(dev)) 3501 get_ext_port_caps(dev); 3502 3503 if (!mlx5_lag_is_active(mdev)) 3504 name = "mlx5_%d"; 3505 else 3506 name = "mlx5_bond_%d"; 3507 3508 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX); 3509 dev->ib_dev.owner = THIS_MODULE; 3510 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 3511 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 3512 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports); 3513 dev->ib_dev.phys_port_cnt = dev->num_ports; 3514 dev->ib_dev.num_comp_vectors = 3515 dev->mdev->priv.eq_table.num_comp_vectors; 3516 dev->ib_dev.dev.parent = &mdev->pdev->dev; 3517 3518 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION; 3519 dev->ib_dev.uverbs_cmd_mask = 3520 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | 3521 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | 3522 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | 3523 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | 3524 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | 3525 (1ull << IB_USER_VERBS_CMD_CREATE_AH) | 3526 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) | 3527 (1ull << IB_USER_VERBS_CMD_REG_MR) | 3528 (1ull << IB_USER_VERBS_CMD_REREG_MR) | 3529 (1ull << IB_USER_VERBS_CMD_DEREG_MR) | 3530 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 3531 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | 3532 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) | 3533 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | 3534 (1ull << IB_USER_VERBS_CMD_CREATE_QP) | 3535 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | 3536 (1ull << IB_USER_VERBS_CMD_QUERY_QP) | 3537 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | 3538 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) | 3539 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) | 3540 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | 3541 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | 3542 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | 3543 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | 3544 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) | 3545 (1ull << IB_USER_VERBS_CMD_OPEN_QP); 3546 dev->ib_dev.uverbs_ex_cmd_mask = 3547 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) | 3548 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) | 3549 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) | 3550 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP); 3551 3552 dev->ib_dev.query_device = mlx5_ib_query_device; 3553 dev->ib_dev.query_port = mlx5_ib_query_port; 3554 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer; 3555 if (ll == IB_LINK_LAYER_ETHERNET) 3556 dev->ib_dev.get_netdev = mlx5_ib_get_netdev; 3557 dev->ib_dev.query_gid = mlx5_ib_query_gid; 3558 dev->ib_dev.add_gid = mlx5_ib_add_gid; 3559 dev->ib_dev.del_gid = mlx5_ib_del_gid; 3560 dev->ib_dev.query_pkey = mlx5_ib_query_pkey; 3561 dev->ib_dev.modify_device = mlx5_ib_modify_device; 3562 dev->ib_dev.modify_port = mlx5_ib_modify_port; 3563 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext; 3564 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext; 3565 dev->ib_dev.mmap = mlx5_ib_mmap; 3566 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd; 3567 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd; 3568 dev->ib_dev.create_ah = mlx5_ib_create_ah; 3569 dev->ib_dev.query_ah = mlx5_ib_query_ah; 3570 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah; 3571 dev->ib_dev.create_srq = mlx5_ib_create_srq; 3572 dev->ib_dev.modify_srq = mlx5_ib_modify_srq; 3573 dev->ib_dev.query_srq = mlx5_ib_query_srq; 3574 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq; 3575 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv; 3576 dev->ib_dev.create_qp = mlx5_ib_create_qp; 3577 dev->ib_dev.modify_qp = mlx5_ib_modify_qp; 3578 dev->ib_dev.query_qp = mlx5_ib_query_qp; 3579 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp; 3580 dev->ib_dev.post_send = mlx5_ib_post_send; 3581 dev->ib_dev.post_recv = mlx5_ib_post_recv; 3582 dev->ib_dev.create_cq = mlx5_ib_create_cq; 3583 dev->ib_dev.modify_cq = mlx5_ib_modify_cq; 3584 dev->ib_dev.resize_cq = mlx5_ib_resize_cq; 3585 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq; 3586 dev->ib_dev.poll_cq = mlx5_ib_poll_cq; 3587 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq; 3588 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr; 3589 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr; 3590 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr; 3591 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr; 3592 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach; 3593 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach; 3594 dev->ib_dev.process_mad = mlx5_ib_process_mad; 3595 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr; 3596 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg; 3597 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status; 3598 dev->ib_dev.get_port_immutable = mlx5_port_immutable; 3599 dev->ib_dev.get_dev_fw_str = get_dev_fw_str; 3600 if (mlx5_core_is_pf(mdev)) { 3601 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config; 3602 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state; 3603 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats; 3604 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid; 3605 } 3606 3607 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext; 3608 3609 mlx5_ib_internal_fill_odp_caps(dev); 3610 3611 if (MLX5_CAP_GEN(mdev, imaicl)) { 3612 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw; 3613 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw; 3614 dev->ib_dev.uverbs_cmd_mask |= 3615 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) | 3616 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW); 3617 } 3618 3619 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) { 3620 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats; 3621 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats; 3622 } 3623 3624 if (MLX5_CAP_GEN(mdev, xrc)) { 3625 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd; 3626 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd; 3627 dev->ib_dev.uverbs_cmd_mask |= 3628 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) | 3629 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD); 3630 } 3631 3632 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) == 3633 IB_LINK_LAYER_ETHERNET) { 3634 dev->ib_dev.create_flow = mlx5_ib_create_flow; 3635 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow; 3636 dev->ib_dev.create_wq = mlx5_ib_create_wq; 3637 dev->ib_dev.modify_wq = mlx5_ib_modify_wq; 3638 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq; 3639 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table; 3640 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table; 3641 dev->ib_dev.uverbs_ex_cmd_mask |= 3642 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) | 3643 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW) | 3644 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) | 3645 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) | 3646 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) | 3647 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) | 3648 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL); 3649 } 3650 err = init_node_data(dev); 3651 if (err) 3652 goto err_free_port; 3653 3654 mutex_init(&dev->flow_db.lock); 3655 mutex_init(&dev->cap_mask_mutex); 3656 INIT_LIST_HEAD(&dev->qp_list); 3657 spin_lock_init(&dev->reset_flow_resource_lock); 3658 3659 if (ll == IB_LINK_LAYER_ETHERNET) { 3660 err = mlx5_enable_eth(dev); 3661 if (err) 3662 goto err_free_port; 3663 } 3664 3665 err = create_dev_resources(&dev->devr); 3666 if (err) 3667 goto err_disable_eth; 3668 3669 err = mlx5_ib_odp_init_one(dev); 3670 if (err) 3671 goto err_rsrc; 3672 3673 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) { 3674 err = mlx5_ib_alloc_counters(dev); 3675 if (err) 3676 goto err_odp; 3677 } 3678 3679 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev); 3680 if (!dev->mdev->priv.uar) 3681 goto err_cnt; 3682 3683 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false); 3684 if (err) 3685 goto err_uar_page; 3686 3687 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true); 3688 if (err) 3689 goto err_bfreg; 3690 3691 err = ib_register_device(&dev->ib_dev, NULL); 3692 if (err) 3693 goto err_fp_bfreg; 3694 3695 err = create_umr_res(dev); 3696 if (err) 3697 goto err_dev; 3698 3699 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) { 3700 err = device_create_file(&dev->ib_dev.dev, 3701 mlx5_class_attributes[i]); 3702 if (err) 3703 goto err_umrc; 3704 } 3705 3706 dev->ib_active = true; 3707 3708 return dev; 3709 3710 err_umrc: 3711 destroy_umrc_res(dev); 3712 3713 err_dev: 3714 ib_unregister_device(&dev->ib_dev); 3715 3716 err_fp_bfreg: 3717 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 3718 3719 err_bfreg: 3720 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 3721 3722 err_uar_page: 3723 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar); 3724 3725 err_cnt: 3726 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) 3727 mlx5_ib_dealloc_counters(dev); 3728 3729 err_odp: 3730 mlx5_ib_odp_remove_one(dev); 3731 3732 err_rsrc: 3733 destroy_dev_resources(&dev->devr); 3734 3735 err_disable_eth: 3736 if (ll == IB_LINK_LAYER_ETHERNET) { 3737 mlx5_disable_eth(dev); 3738 mlx5_remove_netdev_notifier(dev); 3739 } 3740 3741 err_free_port: 3742 kfree(dev->port); 3743 3744 err_dealloc: 3745 ib_dealloc_device((struct ib_device *)dev); 3746 3747 return NULL; 3748 } 3749 3750 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context) 3751 { 3752 struct mlx5_ib_dev *dev = context; 3753 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1); 3754 3755 mlx5_remove_netdev_notifier(dev); 3756 ib_unregister_device(&dev->ib_dev); 3757 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 3758 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 3759 mlx5_put_uars_page(dev->mdev, mdev->priv.uar); 3760 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) 3761 mlx5_ib_dealloc_counters(dev); 3762 destroy_umrc_res(dev); 3763 mlx5_ib_odp_remove_one(dev); 3764 destroy_dev_resources(&dev->devr); 3765 if (ll == IB_LINK_LAYER_ETHERNET) 3766 mlx5_disable_eth(dev); 3767 kfree(dev->port); 3768 ib_dealloc_device(&dev->ib_dev); 3769 } 3770 3771 static struct mlx5_interface mlx5_ib_interface = { 3772 .add = mlx5_ib_add, 3773 .remove = mlx5_ib_remove, 3774 .event = mlx5_ib_event, 3775 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 3776 .pfault = mlx5_ib_pfault, 3777 #endif 3778 .protocol = MLX5_INTERFACE_PROTOCOL_IB, 3779 }; 3780 3781 static int __init mlx5_ib_init(void) 3782 { 3783 int err; 3784 3785 mlx5_ib_odp_init(); 3786 3787 err = mlx5_register_interface(&mlx5_ib_interface); 3788 3789 return err; 3790 } 3791 3792 static void __exit mlx5_ib_cleanup(void) 3793 { 3794 mlx5_unregister_interface(&mlx5_ib_interface); 3795 } 3796 3797 module_init(mlx5_ib_init); 3798 module_exit(mlx5_ib_cleanup); 3799