1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/debugfs.h> 34 #include <linux/highmem.h> 35 #include <linux/module.h> 36 #include <linux/init.h> 37 #include <linux/errno.h> 38 #include <linux/pci.h> 39 #include <linux/dma-mapping.h> 40 #include <linux/slab.h> 41 #if defined(CONFIG_X86) 42 #include <asm/pat.h> 43 #endif 44 #include <linux/sched.h> 45 #include <linux/sched/mm.h> 46 #include <linux/sched/task.h> 47 #include <linux/delay.h> 48 #include <rdma/ib_user_verbs.h> 49 #include <rdma/ib_addr.h> 50 #include <rdma/ib_cache.h> 51 #include <linux/mlx5/port.h> 52 #include <linux/mlx5/vport.h> 53 #include <linux/list.h> 54 #include <rdma/ib_smi.h> 55 #include <rdma/ib_umem.h> 56 #include <linux/in.h> 57 #include <linux/etherdevice.h> 58 #include <linux/mlx5/fs.h> 59 #include <linux/mlx5/vport.h> 60 #include "mlx5_ib.h" 61 #include "cmd.h" 62 #include <linux/mlx5/vport.h> 63 64 #define DRIVER_NAME "mlx5_ib" 65 #define DRIVER_VERSION "5.0-0" 66 67 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 68 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver"); 69 MODULE_LICENSE("Dual BSD/GPL"); 70 71 static char mlx5_version[] = 72 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v" 73 DRIVER_VERSION "\n"; 74 75 enum { 76 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 77 }; 78 79 static enum rdma_link_layer 80 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 81 { 82 switch (port_type_cap) { 83 case MLX5_CAP_PORT_TYPE_IB: 84 return IB_LINK_LAYER_INFINIBAND; 85 case MLX5_CAP_PORT_TYPE_ETH: 86 return IB_LINK_LAYER_ETHERNET; 87 default: 88 return IB_LINK_LAYER_UNSPECIFIED; 89 } 90 } 91 92 static enum rdma_link_layer 93 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num) 94 { 95 struct mlx5_ib_dev *dev = to_mdev(device); 96 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 97 98 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 99 } 100 101 static int get_port_state(struct ib_device *ibdev, 102 u8 port_num, 103 enum ib_port_state *state) 104 { 105 struct ib_port_attr attr; 106 int ret; 107 108 memset(&attr, 0, sizeof(attr)); 109 ret = mlx5_ib_query_port(ibdev, port_num, &attr); 110 if (!ret) 111 *state = attr.state; 112 return ret; 113 } 114 115 static int mlx5_netdev_event(struct notifier_block *this, 116 unsigned long event, void *ptr) 117 { 118 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 119 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev, 120 roce.nb); 121 122 switch (event) { 123 case NETDEV_REGISTER: 124 case NETDEV_UNREGISTER: 125 write_lock(&ibdev->roce.netdev_lock); 126 if (ndev->dev.parent == &ibdev->mdev->pdev->dev) 127 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ? 128 NULL : ndev; 129 write_unlock(&ibdev->roce.netdev_lock); 130 break; 131 132 case NETDEV_CHANGE: 133 case NETDEV_UP: 134 case NETDEV_DOWN: { 135 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(ibdev->mdev); 136 struct net_device *upper = NULL; 137 138 if (lag_ndev) { 139 upper = netdev_master_upper_dev_get(lag_ndev); 140 dev_put(lag_ndev); 141 } 142 143 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev)) 144 && ibdev->ib_active) { 145 struct ib_event ibev = { }; 146 enum ib_port_state port_state; 147 148 if (get_port_state(&ibdev->ib_dev, 1, &port_state)) 149 return NOTIFY_DONE; 150 151 if (ibdev->roce.last_port_state == port_state) 152 return NOTIFY_DONE; 153 154 ibdev->roce.last_port_state = port_state; 155 ibev.device = &ibdev->ib_dev; 156 if (port_state == IB_PORT_DOWN) 157 ibev.event = IB_EVENT_PORT_ERR; 158 else if (port_state == IB_PORT_ACTIVE) 159 ibev.event = IB_EVENT_PORT_ACTIVE; 160 else 161 return NOTIFY_DONE; 162 163 ibev.element.port_num = 1; 164 ib_dispatch_event(&ibev); 165 } 166 break; 167 } 168 169 default: 170 break; 171 } 172 173 return NOTIFY_DONE; 174 } 175 176 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device, 177 u8 port_num) 178 { 179 struct mlx5_ib_dev *ibdev = to_mdev(device); 180 struct net_device *ndev; 181 182 ndev = mlx5_lag_get_roce_netdev(ibdev->mdev); 183 if (ndev) 184 return ndev; 185 186 /* Ensure ndev does not disappear before we invoke dev_hold() 187 */ 188 read_lock(&ibdev->roce.netdev_lock); 189 ndev = ibdev->roce.netdev; 190 if (ndev) 191 dev_hold(ndev); 192 read_unlock(&ibdev->roce.netdev_lock); 193 194 return ndev; 195 } 196 197 static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed, 198 u8 *active_width) 199 { 200 switch (eth_proto_oper) { 201 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII): 202 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX): 203 case MLX5E_PROT_MASK(MLX5E_100BASE_TX): 204 case MLX5E_PROT_MASK(MLX5E_1000BASE_T): 205 *active_width = IB_WIDTH_1X; 206 *active_speed = IB_SPEED_SDR; 207 break; 208 case MLX5E_PROT_MASK(MLX5E_10GBASE_T): 209 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4): 210 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4): 211 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR): 212 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR): 213 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR): 214 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER): 215 *active_width = IB_WIDTH_1X; 216 *active_speed = IB_SPEED_QDR; 217 break; 218 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR): 219 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR): 220 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR): 221 *active_width = IB_WIDTH_1X; 222 *active_speed = IB_SPEED_EDR; 223 break; 224 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4): 225 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4): 226 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4): 227 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4): 228 *active_width = IB_WIDTH_4X; 229 *active_speed = IB_SPEED_QDR; 230 break; 231 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2): 232 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2): 233 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2): 234 *active_width = IB_WIDTH_1X; 235 *active_speed = IB_SPEED_HDR; 236 break; 237 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4): 238 *active_width = IB_WIDTH_4X; 239 *active_speed = IB_SPEED_FDR; 240 break; 241 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4): 242 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4): 243 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4): 244 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4): 245 *active_width = IB_WIDTH_4X; 246 *active_speed = IB_SPEED_EDR; 247 break; 248 default: 249 return -EINVAL; 250 } 251 252 return 0; 253 } 254 255 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num, 256 struct ib_port_attr *props) 257 { 258 struct mlx5_ib_dev *dev = to_mdev(device); 259 struct mlx5_core_dev *mdev = dev->mdev; 260 struct net_device *ndev, *upper; 261 enum ib_mtu ndev_ib_mtu; 262 u16 qkey_viol_cntr; 263 u32 eth_prot_oper; 264 int err; 265 266 /* Possible bad flows are checked before filling out props so in case 267 * of an error it will still be zeroed out. 268 */ 269 err = mlx5_query_port_eth_proto_oper(mdev, ð_prot_oper, port_num); 270 if (err) 271 return err; 272 273 translate_eth_proto_oper(eth_prot_oper, &props->active_speed, 274 &props->active_width); 275 276 props->port_cap_flags |= IB_PORT_CM_SUP; 277 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS; 278 279 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 280 roce_address_table_size); 281 props->max_mtu = IB_MTU_4096; 282 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 283 props->pkey_tbl_len = 1; 284 props->state = IB_PORT_DOWN; 285 props->phys_state = 3; 286 287 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr); 288 props->qkey_viol_cntr = qkey_viol_cntr; 289 290 ndev = mlx5_ib_get_netdev(device, port_num); 291 if (!ndev) 292 return 0; 293 294 if (mlx5_lag_is_active(dev->mdev)) { 295 rcu_read_lock(); 296 upper = netdev_master_upper_dev_get_rcu(ndev); 297 if (upper) { 298 dev_put(ndev); 299 ndev = upper; 300 dev_hold(ndev); 301 } 302 rcu_read_unlock(); 303 } 304 305 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 306 props->state = IB_PORT_ACTIVE; 307 props->phys_state = 5; 308 } 309 310 ndev_ib_mtu = iboe_get_mtu(ndev->mtu); 311 312 dev_put(ndev); 313 314 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 315 return 0; 316 } 317 318 static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num, 319 unsigned int index, const union ib_gid *gid, 320 const struct ib_gid_attr *attr) 321 { 322 enum ib_gid_type gid_type = IB_GID_TYPE_IB; 323 u8 roce_version = 0; 324 u8 roce_l3_type = 0; 325 bool vlan = false; 326 u8 mac[ETH_ALEN]; 327 u16 vlan_id = 0; 328 329 if (gid) { 330 gid_type = attr->gid_type; 331 ether_addr_copy(mac, attr->ndev->dev_addr); 332 333 if (is_vlan_dev(attr->ndev)) { 334 vlan = true; 335 vlan_id = vlan_dev_vlan_id(attr->ndev); 336 } 337 } 338 339 switch (gid_type) { 340 case IB_GID_TYPE_IB: 341 roce_version = MLX5_ROCE_VERSION_1; 342 break; 343 case IB_GID_TYPE_ROCE_UDP_ENCAP: 344 roce_version = MLX5_ROCE_VERSION_2; 345 if (ipv6_addr_v4mapped((void *)gid)) 346 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4; 347 else 348 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6; 349 break; 350 351 default: 352 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type); 353 } 354 355 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version, 356 roce_l3_type, gid->raw, mac, vlan, 357 vlan_id); 358 } 359 360 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num, 361 unsigned int index, const union ib_gid *gid, 362 const struct ib_gid_attr *attr, 363 __always_unused void **context) 364 { 365 return set_roce_addr(to_mdev(device), port_num, index, gid, attr); 366 } 367 368 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num, 369 unsigned int index, __always_unused void **context) 370 { 371 return set_roce_addr(to_mdev(device), port_num, index, NULL, NULL); 372 } 373 374 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num, 375 int index) 376 { 377 struct ib_gid_attr attr; 378 union ib_gid gid; 379 380 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr)) 381 return 0; 382 383 if (!attr.ndev) 384 return 0; 385 386 dev_put(attr.ndev); 387 388 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 389 return 0; 390 391 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 392 } 393 394 int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num, 395 int index, enum ib_gid_type *gid_type) 396 { 397 struct ib_gid_attr attr; 398 union ib_gid gid; 399 int ret; 400 401 ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr); 402 if (ret) 403 return ret; 404 405 if (!attr.ndev) 406 return -ENODEV; 407 408 dev_put(attr.ndev); 409 410 *gid_type = attr.gid_type; 411 412 return 0; 413 } 414 415 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 416 { 417 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 418 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 419 return 0; 420 } 421 422 enum { 423 MLX5_VPORT_ACCESS_METHOD_MAD, 424 MLX5_VPORT_ACCESS_METHOD_HCA, 425 MLX5_VPORT_ACCESS_METHOD_NIC, 426 }; 427 428 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 429 { 430 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 431 return MLX5_VPORT_ACCESS_METHOD_MAD; 432 433 if (mlx5_ib_port_link_layer(ibdev, 1) == 434 IB_LINK_LAYER_ETHERNET) 435 return MLX5_VPORT_ACCESS_METHOD_NIC; 436 437 return MLX5_VPORT_ACCESS_METHOD_HCA; 438 } 439 440 static void get_atomic_caps(struct mlx5_ib_dev *dev, 441 struct ib_device_attr *props) 442 { 443 u8 tmp; 444 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 445 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 446 u8 atomic_req_8B_endianness_mode = 447 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode); 448 449 /* Check if HW supports 8 bytes standard atomic operations and capable 450 * of host endianness respond 451 */ 452 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 453 if (((atomic_operations & tmp) == tmp) && 454 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 455 (atomic_req_8B_endianness_mode)) { 456 props->atomic_cap = IB_ATOMIC_HCA; 457 } else { 458 props->atomic_cap = IB_ATOMIC_NONE; 459 } 460 } 461 462 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 463 __be64 *sys_image_guid) 464 { 465 struct mlx5_ib_dev *dev = to_mdev(ibdev); 466 struct mlx5_core_dev *mdev = dev->mdev; 467 u64 tmp; 468 int err; 469 470 switch (mlx5_get_vport_access_method(ibdev)) { 471 case MLX5_VPORT_ACCESS_METHOD_MAD: 472 return mlx5_query_mad_ifc_system_image_guid(ibdev, 473 sys_image_guid); 474 475 case MLX5_VPORT_ACCESS_METHOD_HCA: 476 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 477 break; 478 479 case MLX5_VPORT_ACCESS_METHOD_NIC: 480 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 481 break; 482 483 default: 484 return -EINVAL; 485 } 486 487 if (!err) 488 *sys_image_guid = cpu_to_be64(tmp); 489 490 return err; 491 492 } 493 494 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 495 u16 *max_pkeys) 496 { 497 struct mlx5_ib_dev *dev = to_mdev(ibdev); 498 struct mlx5_core_dev *mdev = dev->mdev; 499 500 switch (mlx5_get_vport_access_method(ibdev)) { 501 case MLX5_VPORT_ACCESS_METHOD_MAD: 502 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 503 504 case MLX5_VPORT_ACCESS_METHOD_HCA: 505 case MLX5_VPORT_ACCESS_METHOD_NIC: 506 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 507 pkey_table_size)); 508 return 0; 509 510 default: 511 return -EINVAL; 512 } 513 } 514 515 static int mlx5_query_vendor_id(struct ib_device *ibdev, 516 u32 *vendor_id) 517 { 518 struct mlx5_ib_dev *dev = to_mdev(ibdev); 519 520 switch (mlx5_get_vport_access_method(ibdev)) { 521 case MLX5_VPORT_ACCESS_METHOD_MAD: 522 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 523 524 case MLX5_VPORT_ACCESS_METHOD_HCA: 525 case MLX5_VPORT_ACCESS_METHOD_NIC: 526 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 527 528 default: 529 return -EINVAL; 530 } 531 } 532 533 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 534 __be64 *node_guid) 535 { 536 u64 tmp; 537 int err; 538 539 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 540 case MLX5_VPORT_ACCESS_METHOD_MAD: 541 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 542 543 case MLX5_VPORT_ACCESS_METHOD_HCA: 544 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 545 break; 546 547 case MLX5_VPORT_ACCESS_METHOD_NIC: 548 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 549 break; 550 551 default: 552 return -EINVAL; 553 } 554 555 if (!err) 556 *node_guid = cpu_to_be64(tmp); 557 558 return err; 559 } 560 561 struct mlx5_reg_node_desc { 562 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 563 }; 564 565 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 566 { 567 struct mlx5_reg_node_desc in; 568 569 if (mlx5_use_mad_ifc(dev)) 570 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 571 572 memset(&in, 0, sizeof(in)); 573 574 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 575 sizeof(struct mlx5_reg_node_desc), 576 MLX5_REG_NODE_DESC, 0, 0); 577 } 578 579 static int mlx5_ib_query_device(struct ib_device *ibdev, 580 struct ib_device_attr *props, 581 struct ib_udata *uhw) 582 { 583 struct mlx5_ib_dev *dev = to_mdev(ibdev); 584 struct mlx5_core_dev *mdev = dev->mdev; 585 int err = -ENOMEM; 586 int max_sq_desc; 587 int max_rq_sg; 588 int max_sq_sg; 589 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 590 struct mlx5_ib_query_device_resp resp = {}; 591 size_t resp_len; 592 u64 max_tso; 593 594 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 595 if (uhw->outlen && uhw->outlen < resp_len) 596 return -EINVAL; 597 else 598 resp.response_length = resp_len; 599 600 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) 601 return -EINVAL; 602 603 memset(props, 0, sizeof(*props)); 604 err = mlx5_query_system_image_guid(ibdev, 605 &props->sys_image_guid); 606 if (err) 607 return err; 608 609 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys); 610 if (err) 611 return err; 612 613 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 614 if (err) 615 return err; 616 617 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 618 (fw_rev_min(dev->mdev) << 16) | 619 fw_rev_sub(dev->mdev); 620 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 621 IB_DEVICE_PORT_ACTIVE_EVENT | 622 IB_DEVICE_SYS_IMAGE_GUID | 623 IB_DEVICE_RC_RNR_NAK_GEN; 624 625 if (MLX5_CAP_GEN(mdev, pkv)) 626 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 627 if (MLX5_CAP_GEN(mdev, qkv)) 628 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 629 if (MLX5_CAP_GEN(mdev, apm)) 630 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 631 if (MLX5_CAP_GEN(mdev, xrc)) 632 props->device_cap_flags |= IB_DEVICE_XRC; 633 if (MLX5_CAP_GEN(mdev, imaicl)) { 634 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 635 IB_DEVICE_MEM_WINDOW_TYPE_2B; 636 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 637 /* We support 'Gappy' memory registration too */ 638 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG; 639 } 640 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 641 if (MLX5_CAP_GEN(mdev, sho)) { 642 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER; 643 /* At this stage no support for signature handover */ 644 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 645 IB_PROT_T10DIF_TYPE_2 | 646 IB_PROT_T10DIF_TYPE_3; 647 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 648 IB_GUARD_T10DIF_CSUM; 649 } 650 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 651 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 652 653 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) { 654 if (MLX5_CAP_ETH(mdev, csum_cap)) { 655 /* Legacy bit to support old userspace libraries */ 656 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 657 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM; 658 } 659 660 if (MLX5_CAP_ETH(dev->mdev, vlan_cap)) 661 props->raw_packet_caps |= 662 IB_RAW_PACKET_CAP_CVLAN_STRIPPING; 663 664 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) { 665 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 666 if (max_tso) { 667 resp.tso_caps.max_tso = 1 << max_tso; 668 resp.tso_caps.supported_qpts |= 669 1 << IB_QPT_RAW_PACKET; 670 resp.response_length += sizeof(resp.tso_caps); 671 } 672 } 673 674 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) { 675 resp.rss_caps.rx_hash_function = 676 MLX5_RX_HASH_FUNC_TOEPLITZ; 677 resp.rss_caps.rx_hash_fields_mask = 678 MLX5_RX_HASH_SRC_IPV4 | 679 MLX5_RX_HASH_DST_IPV4 | 680 MLX5_RX_HASH_SRC_IPV6 | 681 MLX5_RX_HASH_DST_IPV6 | 682 MLX5_RX_HASH_SRC_PORT_TCP | 683 MLX5_RX_HASH_DST_PORT_TCP | 684 MLX5_RX_HASH_SRC_PORT_UDP | 685 MLX5_RX_HASH_DST_PORT_UDP; 686 resp.response_length += sizeof(resp.rss_caps); 687 } 688 } else { 689 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) 690 resp.response_length += sizeof(resp.tso_caps); 691 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) 692 resp.response_length += sizeof(resp.rss_caps); 693 } 694 695 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 696 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 697 props->device_cap_flags |= IB_DEVICE_UD_TSO; 698 } 699 700 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) && 701 MLX5_CAP_GEN(dev->mdev, general_notification_event)) 702 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP; 703 704 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 705 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap)) 706 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 707 708 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 709 MLX5_CAP_ETH(dev->mdev, scatter_fcs)) { 710 /* Legacy bit to support old userspace libraries */ 711 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 712 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; 713 } 714 715 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 716 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 717 718 props->vendor_part_id = mdev->pdev->device; 719 props->hw_ver = mdev->pdev->revision; 720 721 props->max_mr_size = ~0ull; 722 props->page_size_cap = ~(min_page_size - 1); 723 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 724 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 725 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 726 sizeof(struct mlx5_wqe_data_seg); 727 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512); 728 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) - 729 sizeof(struct mlx5_wqe_raddr_seg)) / 730 sizeof(struct mlx5_wqe_data_seg); 731 props->max_sge = min(max_rq_sg, max_sq_sg); 732 props->max_sge_rd = MLX5_MAX_SGE_RD; 733 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 734 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 735 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 736 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 737 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 738 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 739 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 740 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 741 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 742 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 743 props->max_srq_sge = max_rq_sg - 1; 744 props->max_fast_reg_page_list_len = 745 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 746 get_atomic_caps(dev, props); 747 props->masked_atomic_cap = IB_ATOMIC_NONE; 748 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 749 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 750 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 751 props->max_mcast_grp; 752 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */ 753 props->max_ah = INT_MAX; 754 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 755 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 756 757 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 758 if (MLX5_CAP_GEN(mdev, pg)) 759 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING; 760 props->odp_caps = dev->odp_caps; 761 #endif 762 763 if (MLX5_CAP_GEN(mdev, cd)) 764 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL; 765 766 if (!mlx5_core_is_pf(mdev)) 767 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION; 768 769 if (mlx5_ib_port_link_layer(ibdev, 1) == 770 IB_LINK_LAYER_ETHERNET) { 771 props->rss_caps.max_rwq_indirection_tables = 772 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 773 props->rss_caps.max_rwq_indirection_table_size = 774 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 775 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 776 props->max_wq_type_rq = 777 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 778 } 779 780 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) { 781 resp.cqe_comp_caps.max_num = 782 MLX5_CAP_GEN(dev->mdev, cqe_compression) ? 783 MLX5_CAP_GEN(dev->mdev, cqe_compression_max_num) : 0; 784 resp.cqe_comp_caps.supported_format = 785 MLX5_IB_CQE_RES_FORMAT_HASH | 786 MLX5_IB_CQE_RES_FORMAT_CSUM; 787 resp.response_length += sizeof(resp.cqe_comp_caps); 788 } 789 790 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen)) { 791 if (MLX5_CAP_QOS(mdev, packet_pacing) && 792 MLX5_CAP_GEN(mdev, qos)) { 793 resp.packet_pacing_caps.qp_rate_limit_max = 794 MLX5_CAP_QOS(mdev, packet_pacing_max_rate); 795 resp.packet_pacing_caps.qp_rate_limit_min = 796 MLX5_CAP_QOS(mdev, packet_pacing_min_rate); 797 resp.packet_pacing_caps.supported_qpts |= 798 1 << IB_QPT_RAW_PACKET; 799 } 800 resp.response_length += sizeof(resp.packet_pacing_caps); 801 } 802 803 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes, 804 uhw->outlen)) { 805 resp.mlx5_ib_support_multi_pkt_send_wqes = 806 MLX5_CAP_ETH(mdev, multi_pkt_send_wqe); 807 resp.response_length += 808 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes); 809 } 810 811 if (field_avail(typeof(resp), reserved, uhw->outlen)) 812 resp.response_length += sizeof(resp.reserved); 813 814 if (uhw->outlen) { 815 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 816 817 if (err) 818 return err; 819 } 820 821 return 0; 822 } 823 824 enum mlx5_ib_width { 825 MLX5_IB_WIDTH_1X = 1 << 0, 826 MLX5_IB_WIDTH_2X = 1 << 1, 827 MLX5_IB_WIDTH_4X = 1 << 2, 828 MLX5_IB_WIDTH_8X = 1 << 3, 829 MLX5_IB_WIDTH_12X = 1 << 4 830 }; 831 832 static int translate_active_width(struct ib_device *ibdev, u8 active_width, 833 u8 *ib_width) 834 { 835 struct mlx5_ib_dev *dev = to_mdev(ibdev); 836 int err = 0; 837 838 if (active_width & MLX5_IB_WIDTH_1X) { 839 *ib_width = IB_WIDTH_1X; 840 } else if (active_width & MLX5_IB_WIDTH_2X) { 841 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n", 842 (int)active_width); 843 err = -EINVAL; 844 } else if (active_width & MLX5_IB_WIDTH_4X) { 845 *ib_width = IB_WIDTH_4X; 846 } else if (active_width & MLX5_IB_WIDTH_8X) { 847 *ib_width = IB_WIDTH_8X; 848 } else if (active_width & MLX5_IB_WIDTH_12X) { 849 *ib_width = IB_WIDTH_12X; 850 } else { 851 mlx5_ib_dbg(dev, "Invalid active_width %d\n", 852 (int)active_width); 853 err = -EINVAL; 854 } 855 856 return err; 857 } 858 859 static int mlx5_mtu_to_ib_mtu(int mtu) 860 { 861 switch (mtu) { 862 case 256: return 1; 863 case 512: return 2; 864 case 1024: return 3; 865 case 2048: return 4; 866 case 4096: return 5; 867 default: 868 pr_warn("invalid mtu\n"); 869 return -1; 870 } 871 } 872 873 enum ib_max_vl_num { 874 __IB_MAX_VL_0 = 1, 875 __IB_MAX_VL_0_1 = 2, 876 __IB_MAX_VL_0_3 = 3, 877 __IB_MAX_VL_0_7 = 4, 878 __IB_MAX_VL_0_14 = 5, 879 }; 880 881 enum mlx5_vl_hw_cap { 882 MLX5_VL_HW_0 = 1, 883 MLX5_VL_HW_0_1 = 2, 884 MLX5_VL_HW_0_2 = 3, 885 MLX5_VL_HW_0_3 = 4, 886 MLX5_VL_HW_0_4 = 5, 887 MLX5_VL_HW_0_5 = 6, 888 MLX5_VL_HW_0_6 = 7, 889 MLX5_VL_HW_0_7 = 8, 890 MLX5_VL_HW_0_14 = 15 891 }; 892 893 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 894 u8 *max_vl_num) 895 { 896 switch (vl_hw_cap) { 897 case MLX5_VL_HW_0: 898 *max_vl_num = __IB_MAX_VL_0; 899 break; 900 case MLX5_VL_HW_0_1: 901 *max_vl_num = __IB_MAX_VL_0_1; 902 break; 903 case MLX5_VL_HW_0_3: 904 *max_vl_num = __IB_MAX_VL_0_3; 905 break; 906 case MLX5_VL_HW_0_7: 907 *max_vl_num = __IB_MAX_VL_0_7; 908 break; 909 case MLX5_VL_HW_0_14: 910 *max_vl_num = __IB_MAX_VL_0_14; 911 break; 912 913 default: 914 return -EINVAL; 915 } 916 917 return 0; 918 } 919 920 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port, 921 struct ib_port_attr *props) 922 { 923 struct mlx5_ib_dev *dev = to_mdev(ibdev); 924 struct mlx5_core_dev *mdev = dev->mdev; 925 struct mlx5_hca_vport_context *rep; 926 u16 max_mtu; 927 u16 oper_mtu; 928 int err; 929 u8 ib_link_width_oper; 930 u8 vl_hw_cap; 931 932 rep = kzalloc(sizeof(*rep), GFP_KERNEL); 933 if (!rep) { 934 err = -ENOMEM; 935 goto out; 936 } 937 938 /* props being zeroed by the caller, avoid zeroing it here */ 939 940 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); 941 if (err) 942 goto out; 943 944 props->lid = rep->lid; 945 props->lmc = rep->lmc; 946 props->sm_lid = rep->sm_lid; 947 props->sm_sl = rep->sm_sl; 948 props->state = rep->vport_state; 949 props->phys_state = rep->port_physical_state; 950 props->port_cap_flags = rep->cap_mask1; 951 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 952 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 953 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 954 props->bad_pkey_cntr = rep->pkey_violation_counter; 955 props->qkey_viol_cntr = rep->qkey_violation_counter; 956 props->subnet_timeout = rep->subnet_timeout; 957 props->init_type_reply = rep->init_type_reply; 958 props->grh_required = rep->grh_required; 959 960 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port); 961 if (err) 962 goto out; 963 964 err = translate_active_width(ibdev, ib_link_width_oper, 965 &props->active_width); 966 if (err) 967 goto out; 968 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port); 969 if (err) 970 goto out; 971 972 mlx5_query_port_max_mtu(mdev, &max_mtu, port); 973 974 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); 975 976 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); 977 978 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); 979 980 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); 981 if (err) 982 goto out; 983 984 err = translate_max_vl_num(ibdev, vl_hw_cap, 985 &props->max_vl_num); 986 out: 987 kfree(rep); 988 return err; 989 } 990 991 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 992 struct ib_port_attr *props) 993 { 994 unsigned int count; 995 int ret; 996 997 switch (mlx5_get_vport_access_method(ibdev)) { 998 case MLX5_VPORT_ACCESS_METHOD_MAD: 999 ret = mlx5_query_mad_ifc_port(ibdev, port, props); 1000 break; 1001 1002 case MLX5_VPORT_ACCESS_METHOD_HCA: 1003 ret = mlx5_query_hca_port(ibdev, port, props); 1004 break; 1005 1006 case MLX5_VPORT_ACCESS_METHOD_NIC: 1007 ret = mlx5_query_port_roce(ibdev, port, props); 1008 break; 1009 1010 default: 1011 ret = -EINVAL; 1012 } 1013 1014 if (!ret && props) { 1015 count = mlx5_core_reserved_gids_count(to_mdev(ibdev)->mdev); 1016 props->gid_tbl_len -= count; 1017 } 1018 return ret; 1019 } 1020 1021 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 1022 union ib_gid *gid) 1023 { 1024 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1025 struct mlx5_core_dev *mdev = dev->mdev; 1026 1027 switch (mlx5_get_vport_access_method(ibdev)) { 1028 case MLX5_VPORT_ACCESS_METHOD_MAD: 1029 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 1030 1031 case MLX5_VPORT_ACCESS_METHOD_HCA: 1032 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); 1033 1034 default: 1035 return -EINVAL; 1036 } 1037 1038 } 1039 1040 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 1041 u16 *pkey) 1042 { 1043 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1044 struct mlx5_core_dev *mdev = dev->mdev; 1045 1046 switch (mlx5_get_vport_access_method(ibdev)) { 1047 case MLX5_VPORT_ACCESS_METHOD_MAD: 1048 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 1049 1050 case MLX5_VPORT_ACCESS_METHOD_HCA: 1051 case MLX5_VPORT_ACCESS_METHOD_NIC: 1052 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index, 1053 pkey); 1054 default: 1055 return -EINVAL; 1056 } 1057 } 1058 1059 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 1060 struct ib_device_modify *props) 1061 { 1062 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1063 struct mlx5_reg_node_desc in; 1064 struct mlx5_reg_node_desc out; 1065 int err; 1066 1067 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 1068 return -EOPNOTSUPP; 1069 1070 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 1071 return 0; 1072 1073 /* 1074 * If possible, pass node desc to FW, so it can generate 1075 * a 144 trap. If cmd fails, just ignore. 1076 */ 1077 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1078 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 1079 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 1080 if (err) 1081 return err; 1082 1083 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1084 1085 return err; 1086 } 1087 1088 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask, 1089 u32 value) 1090 { 1091 struct mlx5_hca_vport_context ctx = {}; 1092 int err; 1093 1094 err = mlx5_query_hca_vport_context(dev->mdev, 0, 1095 port_num, 0, &ctx); 1096 if (err) 1097 return err; 1098 1099 if (~ctx.cap_mask1_perm & mask) { 1100 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n", 1101 mask, ctx.cap_mask1_perm); 1102 return -EINVAL; 1103 } 1104 1105 ctx.cap_mask1 = value; 1106 ctx.cap_mask1_perm = mask; 1107 err = mlx5_core_modify_hca_vport_context(dev->mdev, 0, 1108 port_num, 0, &ctx); 1109 1110 return err; 1111 } 1112 1113 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, 1114 struct ib_port_modify *props) 1115 { 1116 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1117 struct ib_port_attr attr; 1118 u32 tmp; 1119 int err; 1120 u32 change_mask; 1121 u32 value; 1122 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) == 1123 IB_LINK_LAYER_INFINIBAND); 1124 1125 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) { 1126 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask; 1127 value = ~props->clr_port_cap_mask | props->set_port_cap_mask; 1128 return set_port_caps_atomic(dev, port, change_mask, value); 1129 } 1130 1131 mutex_lock(&dev->cap_mask_mutex); 1132 1133 err = ib_query_port(ibdev, port, &attr); 1134 if (err) 1135 goto out; 1136 1137 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 1138 ~props->clr_port_cap_mask; 1139 1140 err = mlx5_set_port_caps(dev->mdev, port, tmp); 1141 1142 out: 1143 mutex_unlock(&dev->cap_mask_mutex); 1144 return err; 1145 } 1146 1147 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps) 1148 { 1149 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n", 1150 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n"); 1151 } 1152 1153 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k, 1154 struct mlx5_ib_alloc_ucontext_req_v2 *req, 1155 u32 *num_sys_pages) 1156 { 1157 int uars_per_sys_page; 1158 int bfregs_per_sys_page; 1159 int ref_bfregs = req->total_num_bfregs; 1160 1161 if (req->total_num_bfregs == 0) 1162 return -EINVAL; 1163 1164 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE); 1165 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE); 1166 1167 if (req->total_num_bfregs > MLX5_MAX_BFREGS) 1168 return -ENOMEM; 1169 1170 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k); 1171 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR; 1172 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page); 1173 *num_sys_pages = req->total_num_bfregs / bfregs_per_sys_page; 1174 1175 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1) 1176 return -EINVAL; 1177 1178 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, using %d sys pages\n", 1179 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no", 1180 lib_uar_4k ? "yes" : "no", ref_bfregs, 1181 req->total_num_bfregs, *num_sys_pages); 1182 1183 return 0; 1184 } 1185 1186 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1187 { 1188 struct mlx5_bfreg_info *bfregi; 1189 int err; 1190 int i; 1191 1192 bfregi = &context->bfregi; 1193 for (i = 0; i < bfregi->num_sys_pages; i++) { 1194 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]); 1195 if (err) 1196 goto error; 1197 1198 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]); 1199 } 1200 return 0; 1201 1202 error: 1203 for (--i; i >= 0; i--) 1204 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i])) 1205 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1206 1207 return err; 1208 } 1209 1210 static int deallocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1211 { 1212 struct mlx5_bfreg_info *bfregi; 1213 int err; 1214 int i; 1215 1216 bfregi = &context->bfregi; 1217 for (i = 0; i < bfregi->num_sys_pages; i++) { 1218 err = mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]); 1219 if (err) { 1220 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1221 return err; 1222 } 1223 } 1224 return 0; 1225 } 1226 1227 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn) 1228 { 1229 int err; 1230 1231 err = mlx5_core_alloc_transport_domain(dev->mdev, tdn); 1232 if (err) 1233 return err; 1234 1235 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1236 !MLX5_CAP_GEN(dev->mdev, disable_local_lb)) 1237 return err; 1238 1239 mutex_lock(&dev->lb_mutex); 1240 dev->user_td++; 1241 1242 if (dev->user_td == 2) 1243 err = mlx5_nic_vport_update_local_lb(dev->mdev, true); 1244 1245 mutex_unlock(&dev->lb_mutex); 1246 return err; 1247 } 1248 1249 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn) 1250 { 1251 mlx5_core_dealloc_transport_domain(dev->mdev, tdn); 1252 1253 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1254 !MLX5_CAP_GEN(dev->mdev, disable_local_lb)) 1255 return; 1256 1257 mutex_lock(&dev->lb_mutex); 1258 dev->user_td--; 1259 1260 if (dev->user_td < 2) 1261 mlx5_nic_vport_update_local_lb(dev->mdev, false); 1262 1263 mutex_unlock(&dev->lb_mutex); 1264 } 1265 1266 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev, 1267 struct ib_udata *udata) 1268 { 1269 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1270 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 1271 struct mlx5_ib_alloc_ucontext_resp resp = {}; 1272 struct mlx5_ib_ucontext *context; 1273 struct mlx5_bfreg_info *bfregi; 1274 int ver; 1275 int err; 1276 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 1277 max_cqe_version); 1278 bool lib_uar_4k; 1279 1280 if (!dev->ib_active) 1281 return ERR_PTR(-EAGAIN); 1282 1283 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 1284 ver = 0; 1285 else if (udata->inlen >= min_req_v2) 1286 ver = 2; 1287 else 1288 return ERR_PTR(-EINVAL); 1289 1290 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req))); 1291 if (err) 1292 return ERR_PTR(err); 1293 1294 if (req.flags) 1295 return ERR_PTR(-EINVAL); 1296 1297 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 1298 return ERR_PTR(-EOPNOTSUPP); 1299 1300 req.total_num_bfregs = ALIGN(req.total_num_bfregs, 1301 MLX5_NON_FP_BFREGS_PER_UAR); 1302 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1) 1303 return ERR_PTR(-EINVAL); 1304 1305 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 1306 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf)) 1307 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size); 1308 resp.cache_line_size = cache_line_size(); 1309 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 1310 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 1311 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1312 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1313 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 1314 resp.cqe_version = min_t(__u8, 1315 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 1316 req.max_cqe_version); 1317 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1318 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT; 1319 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1320 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1; 1321 resp.response_length = min(offsetof(typeof(resp), response_length) + 1322 sizeof(resp.response_length), udata->outlen); 1323 1324 context = kzalloc(sizeof(*context), GFP_KERNEL); 1325 if (!context) 1326 return ERR_PTR(-ENOMEM); 1327 1328 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR; 1329 bfregi = &context->bfregi; 1330 1331 /* updates req->total_num_bfregs */ 1332 err = calc_total_bfregs(dev, lib_uar_4k, &req, &bfregi->num_sys_pages); 1333 if (err) 1334 goto out_ctx; 1335 1336 mutex_init(&bfregi->lock); 1337 bfregi->lib_uar_4k = lib_uar_4k; 1338 bfregi->count = kcalloc(req.total_num_bfregs, sizeof(*bfregi->count), 1339 GFP_KERNEL); 1340 if (!bfregi->count) { 1341 err = -ENOMEM; 1342 goto out_ctx; 1343 } 1344 1345 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages, 1346 sizeof(*bfregi->sys_pages), 1347 GFP_KERNEL); 1348 if (!bfregi->sys_pages) { 1349 err = -ENOMEM; 1350 goto out_count; 1351 } 1352 1353 err = allocate_uars(dev, context); 1354 if (err) 1355 goto out_sys_pages; 1356 1357 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1358 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range; 1359 #endif 1360 1361 context->upd_xlt_page = __get_free_page(GFP_KERNEL); 1362 if (!context->upd_xlt_page) { 1363 err = -ENOMEM; 1364 goto out_uars; 1365 } 1366 mutex_init(&context->upd_xlt_page_mutex); 1367 1368 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) { 1369 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn); 1370 if (err) 1371 goto out_page; 1372 } 1373 1374 INIT_LIST_HEAD(&context->vma_private_list); 1375 INIT_LIST_HEAD(&context->db_page_list); 1376 mutex_init(&context->db_page_mutex); 1377 1378 resp.tot_bfregs = req.total_num_bfregs; 1379 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports); 1380 1381 if (field_avail(typeof(resp), cqe_version, udata->outlen)) 1382 resp.response_length += sizeof(resp.cqe_version); 1383 1384 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) { 1385 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 1386 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 1387 resp.response_length += sizeof(resp.cmds_supp_uhw); 1388 } 1389 1390 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) { 1391 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) { 1392 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline); 1393 resp.eth_min_inline++; 1394 } 1395 resp.response_length += sizeof(resp.eth_min_inline); 1396 } 1397 1398 /* 1399 * We don't want to expose information from the PCI bar that is located 1400 * after 4096 bytes, so if the arch only supports larger pages, let's 1401 * pretend we don't support reading the HCA's core clock. This is also 1402 * forced by mmap function. 1403 */ 1404 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) { 1405 if (PAGE_SIZE <= 4096) { 1406 resp.comp_mask |= 1407 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 1408 resp.hca_core_clock_offset = 1409 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE; 1410 } 1411 resp.response_length += sizeof(resp.hca_core_clock_offset) + 1412 sizeof(resp.reserved2); 1413 } 1414 1415 if (field_avail(typeof(resp), log_uar_size, udata->outlen)) 1416 resp.response_length += sizeof(resp.log_uar_size); 1417 1418 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen)) 1419 resp.response_length += sizeof(resp.num_uars_per_page); 1420 1421 err = ib_copy_to_udata(udata, &resp, resp.response_length); 1422 if (err) 1423 goto out_td; 1424 1425 bfregi->ver = ver; 1426 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs; 1427 context->cqe_version = resp.cqe_version; 1428 context->lib_caps = req.lib_caps; 1429 print_lib_caps(dev, context->lib_caps); 1430 1431 return &context->ibucontext; 1432 1433 out_td: 1434 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1435 mlx5_ib_dealloc_transport_domain(dev, context->tdn); 1436 1437 out_page: 1438 free_page(context->upd_xlt_page); 1439 1440 out_uars: 1441 deallocate_uars(dev, context); 1442 1443 out_sys_pages: 1444 kfree(bfregi->sys_pages); 1445 1446 out_count: 1447 kfree(bfregi->count); 1448 1449 out_ctx: 1450 kfree(context); 1451 1452 return ERR_PTR(err); 1453 } 1454 1455 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1456 { 1457 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1458 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1459 struct mlx5_bfreg_info *bfregi; 1460 1461 bfregi = &context->bfregi; 1462 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1463 mlx5_ib_dealloc_transport_domain(dev, context->tdn); 1464 1465 free_page(context->upd_xlt_page); 1466 deallocate_uars(dev, context); 1467 kfree(bfregi->sys_pages); 1468 kfree(bfregi->count); 1469 kfree(context); 1470 1471 return 0; 1472 } 1473 1474 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, 1475 struct mlx5_bfreg_info *bfregi, 1476 int idx) 1477 { 1478 int fw_uars_per_page; 1479 1480 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1; 1481 1482 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + 1483 bfregi->sys_pages[idx] / fw_uars_per_page; 1484 } 1485 1486 static int get_command(unsigned long offset) 1487 { 1488 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 1489 } 1490 1491 static int get_arg(unsigned long offset) 1492 { 1493 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 1494 } 1495 1496 static int get_index(unsigned long offset) 1497 { 1498 return get_arg(offset); 1499 } 1500 1501 static void mlx5_ib_vma_open(struct vm_area_struct *area) 1502 { 1503 /* vma_open is called when a new VMA is created on top of our VMA. This 1504 * is done through either mremap flow or split_vma (usually due to 1505 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA, 1506 * as this VMA is strongly hardware related. Therefore we set the 1507 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from 1508 * calling us again and trying to do incorrect actions. We assume that 1509 * the original VMA size is exactly a single page, and therefore all 1510 * "splitting" operation will not happen to it. 1511 */ 1512 area->vm_ops = NULL; 1513 } 1514 1515 static void mlx5_ib_vma_close(struct vm_area_struct *area) 1516 { 1517 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data; 1518 1519 /* It's guaranteed that all VMAs opened on a FD are closed before the 1520 * file itself is closed, therefore no sync is needed with the regular 1521 * closing flow. (e.g. mlx5 ib_dealloc_ucontext) 1522 * However need a sync with accessing the vma as part of 1523 * mlx5_ib_disassociate_ucontext. 1524 * The close operation is usually called under mm->mmap_sem except when 1525 * process is exiting. 1526 * The exiting case is handled explicitly as part of 1527 * mlx5_ib_disassociate_ucontext. 1528 */ 1529 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data; 1530 1531 /* setting the vma context pointer to null in the mlx5_ib driver's 1532 * private data, to protect a race condition in 1533 * mlx5_ib_disassociate_ucontext(). 1534 */ 1535 mlx5_ib_vma_priv_data->vma = NULL; 1536 list_del(&mlx5_ib_vma_priv_data->list); 1537 kfree(mlx5_ib_vma_priv_data); 1538 } 1539 1540 static const struct vm_operations_struct mlx5_ib_vm_ops = { 1541 .open = mlx5_ib_vma_open, 1542 .close = mlx5_ib_vma_close 1543 }; 1544 1545 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma, 1546 struct mlx5_ib_ucontext *ctx) 1547 { 1548 struct mlx5_ib_vma_private_data *vma_prv; 1549 struct list_head *vma_head = &ctx->vma_private_list; 1550 1551 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL); 1552 if (!vma_prv) 1553 return -ENOMEM; 1554 1555 vma_prv->vma = vma; 1556 vma->vm_private_data = vma_prv; 1557 vma->vm_ops = &mlx5_ib_vm_ops; 1558 1559 list_add(&vma_prv->list, vma_head); 1560 1561 return 0; 1562 } 1563 1564 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 1565 { 1566 int ret; 1567 struct vm_area_struct *vma; 1568 struct mlx5_ib_vma_private_data *vma_private, *n; 1569 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1570 struct task_struct *owning_process = NULL; 1571 struct mm_struct *owning_mm = NULL; 1572 1573 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID); 1574 if (!owning_process) 1575 return; 1576 1577 owning_mm = get_task_mm(owning_process); 1578 if (!owning_mm) { 1579 pr_info("no mm, disassociate ucontext is pending task termination\n"); 1580 while (1) { 1581 put_task_struct(owning_process); 1582 usleep_range(1000, 2000); 1583 owning_process = get_pid_task(ibcontext->tgid, 1584 PIDTYPE_PID); 1585 if (!owning_process || 1586 owning_process->state == TASK_DEAD) { 1587 pr_info("disassociate ucontext done, task was terminated\n"); 1588 /* in case task was dead need to release the 1589 * task struct. 1590 */ 1591 if (owning_process) 1592 put_task_struct(owning_process); 1593 return; 1594 } 1595 } 1596 } 1597 1598 /* need to protect from a race on closing the vma as part of 1599 * mlx5_ib_vma_close. 1600 */ 1601 down_write(&owning_mm->mmap_sem); 1602 list_for_each_entry_safe(vma_private, n, &context->vma_private_list, 1603 list) { 1604 vma = vma_private->vma; 1605 ret = zap_vma_ptes(vma, vma->vm_start, 1606 PAGE_SIZE); 1607 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__); 1608 /* context going to be destroyed, should 1609 * not access ops any more. 1610 */ 1611 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE); 1612 vma->vm_ops = NULL; 1613 list_del(&vma_private->list); 1614 kfree(vma_private); 1615 } 1616 up_write(&owning_mm->mmap_sem); 1617 mmput(owning_mm); 1618 put_task_struct(owning_process); 1619 } 1620 1621 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 1622 { 1623 switch (cmd) { 1624 case MLX5_IB_MMAP_WC_PAGE: 1625 return "WC"; 1626 case MLX5_IB_MMAP_REGULAR_PAGE: 1627 return "best effort WC"; 1628 case MLX5_IB_MMAP_NC_PAGE: 1629 return "NC"; 1630 default: 1631 return NULL; 1632 } 1633 } 1634 1635 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 1636 struct vm_area_struct *vma, 1637 struct mlx5_ib_ucontext *context) 1638 { 1639 struct mlx5_bfreg_info *bfregi = &context->bfregi; 1640 int err; 1641 unsigned long idx; 1642 phys_addr_t pfn, pa; 1643 pgprot_t prot; 1644 int uars_per_page; 1645 1646 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1647 return -EINVAL; 1648 1649 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k); 1650 idx = get_index(vma->vm_pgoff); 1651 if (idx % uars_per_page || 1652 idx * uars_per_page >= bfregi->num_sys_pages) { 1653 mlx5_ib_warn(dev, "invalid uar index %lu\n", idx); 1654 return -EINVAL; 1655 } 1656 1657 switch (cmd) { 1658 case MLX5_IB_MMAP_WC_PAGE: 1659 /* Some architectures don't support WC memory */ 1660 #if defined(CONFIG_X86) 1661 if (!pat_enabled()) 1662 return -EPERM; 1663 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU))) 1664 return -EPERM; 1665 #endif 1666 /* fall through */ 1667 case MLX5_IB_MMAP_REGULAR_PAGE: 1668 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 1669 prot = pgprot_writecombine(vma->vm_page_prot); 1670 break; 1671 case MLX5_IB_MMAP_NC_PAGE: 1672 prot = pgprot_noncached(vma->vm_page_prot); 1673 break; 1674 default: 1675 return -EINVAL; 1676 } 1677 1678 pfn = uar_index2pfn(dev, bfregi, idx); 1679 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 1680 1681 vma->vm_page_prot = prot; 1682 err = io_remap_pfn_range(vma, vma->vm_start, pfn, 1683 PAGE_SIZE, vma->vm_page_prot); 1684 if (err) { 1685 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n", 1686 err, vma->vm_start, &pfn, mmap_cmd2str(cmd)); 1687 return -EAGAIN; 1688 } 1689 1690 pa = pfn << PAGE_SHIFT; 1691 mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd), 1692 vma->vm_start, &pa); 1693 1694 return mlx5_ib_set_vma_data(vma, context); 1695 } 1696 1697 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 1698 { 1699 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1700 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1701 unsigned long command; 1702 phys_addr_t pfn; 1703 1704 command = get_command(vma->vm_pgoff); 1705 switch (command) { 1706 case MLX5_IB_MMAP_WC_PAGE: 1707 case MLX5_IB_MMAP_NC_PAGE: 1708 case MLX5_IB_MMAP_REGULAR_PAGE: 1709 return uar_mmap(dev, command, vma, context); 1710 1711 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 1712 return -ENOSYS; 1713 1714 case MLX5_IB_MMAP_CORE_CLOCK: 1715 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1716 return -EINVAL; 1717 1718 if (vma->vm_flags & VM_WRITE) 1719 return -EPERM; 1720 1721 /* Don't expose to user-space information it shouldn't have */ 1722 if (PAGE_SIZE > 4096) 1723 return -EOPNOTSUPP; 1724 1725 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 1726 pfn = (dev->mdev->iseg_base + 1727 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 1728 PAGE_SHIFT; 1729 if (io_remap_pfn_range(vma, vma->vm_start, pfn, 1730 PAGE_SIZE, vma->vm_page_prot)) 1731 return -EAGAIN; 1732 1733 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n", 1734 vma->vm_start, 1735 (unsigned long long)pfn << PAGE_SHIFT); 1736 break; 1737 1738 default: 1739 return -EINVAL; 1740 } 1741 1742 return 0; 1743 } 1744 1745 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev, 1746 struct ib_ucontext *context, 1747 struct ib_udata *udata) 1748 { 1749 struct mlx5_ib_alloc_pd_resp resp; 1750 struct mlx5_ib_pd *pd; 1751 int err; 1752 1753 pd = kmalloc(sizeof(*pd), GFP_KERNEL); 1754 if (!pd) 1755 return ERR_PTR(-ENOMEM); 1756 1757 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn); 1758 if (err) { 1759 kfree(pd); 1760 return ERR_PTR(err); 1761 } 1762 1763 if (context) { 1764 resp.pdn = pd->pdn; 1765 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 1766 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn); 1767 kfree(pd); 1768 return ERR_PTR(-EFAULT); 1769 } 1770 } 1771 1772 return &pd->ibpd; 1773 } 1774 1775 static int mlx5_ib_dealloc_pd(struct ib_pd *pd) 1776 { 1777 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 1778 struct mlx5_ib_pd *mpd = to_mpd(pd); 1779 1780 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn); 1781 kfree(mpd); 1782 1783 return 0; 1784 } 1785 1786 enum { 1787 MATCH_CRITERIA_ENABLE_OUTER_BIT, 1788 MATCH_CRITERIA_ENABLE_MISC_BIT, 1789 MATCH_CRITERIA_ENABLE_INNER_BIT 1790 }; 1791 1792 #define HEADER_IS_ZERO(match_criteria, headers) \ 1793 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \ 1794 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \ 1795 1796 static u8 get_match_criteria_enable(u32 *match_criteria) 1797 { 1798 u8 match_criteria_enable; 1799 1800 match_criteria_enable = 1801 (!HEADER_IS_ZERO(match_criteria, outer_headers)) << 1802 MATCH_CRITERIA_ENABLE_OUTER_BIT; 1803 match_criteria_enable |= 1804 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) << 1805 MATCH_CRITERIA_ENABLE_MISC_BIT; 1806 match_criteria_enable |= 1807 (!HEADER_IS_ZERO(match_criteria, inner_headers)) << 1808 MATCH_CRITERIA_ENABLE_INNER_BIT; 1809 1810 return match_criteria_enable; 1811 } 1812 1813 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val) 1814 { 1815 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask); 1816 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val); 1817 } 1818 1819 static void set_flow_label(void *misc_c, void *misc_v, u8 mask, u8 val, 1820 bool inner) 1821 { 1822 if (inner) { 1823 MLX5_SET(fte_match_set_misc, 1824 misc_c, inner_ipv6_flow_label, mask); 1825 MLX5_SET(fte_match_set_misc, 1826 misc_v, inner_ipv6_flow_label, val); 1827 } else { 1828 MLX5_SET(fte_match_set_misc, 1829 misc_c, outer_ipv6_flow_label, mask); 1830 MLX5_SET(fte_match_set_misc, 1831 misc_v, outer_ipv6_flow_label, val); 1832 } 1833 } 1834 1835 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val) 1836 { 1837 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask); 1838 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val); 1839 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2); 1840 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2); 1841 } 1842 1843 #define LAST_ETH_FIELD vlan_tag 1844 #define LAST_IB_FIELD sl 1845 #define LAST_IPV4_FIELD tos 1846 #define LAST_IPV6_FIELD traffic_class 1847 #define LAST_TCP_UDP_FIELD src_port 1848 #define LAST_TUNNEL_FIELD tunnel_id 1849 #define LAST_FLOW_TAG_FIELD tag_id 1850 #define LAST_DROP_FIELD size 1851 1852 /* Field is the last supported field */ 1853 #define FIELDS_NOT_SUPPORTED(filter, field)\ 1854 memchr_inv((void *)&filter.field +\ 1855 sizeof(filter.field), 0,\ 1856 sizeof(filter) -\ 1857 offsetof(typeof(filter), field) -\ 1858 sizeof(filter.field)) 1859 1860 #define IPV4_VERSION 4 1861 #define IPV6_VERSION 6 1862 static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c, 1863 u32 *match_v, const union ib_flow_spec *ib_spec, 1864 u32 *tag_id, bool *is_drop) 1865 { 1866 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c, 1867 misc_parameters); 1868 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v, 1869 misc_parameters); 1870 void *headers_c; 1871 void *headers_v; 1872 int match_ipv; 1873 1874 if (ib_spec->type & IB_FLOW_SPEC_INNER) { 1875 headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 1876 inner_headers); 1877 headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 1878 inner_headers); 1879 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 1880 ft_field_support.inner_ip_version); 1881 } else { 1882 headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 1883 outer_headers); 1884 headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 1885 outer_headers); 1886 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 1887 ft_field_support.outer_ip_version); 1888 } 1889 1890 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) { 1891 case IB_FLOW_SPEC_ETH: 1892 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD)) 1893 return -EOPNOTSUPP; 1894 1895 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 1896 dmac_47_16), 1897 ib_spec->eth.mask.dst_mac); 1898 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1899 dmac_47_16), 1900 ib_spec->eth.val.dst_mac); 1901 1902 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 1903 smac_47_16), 1904 ib_spec->eth.mask.src_mac); 1905 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1906 smac_47_16), 1907 ib_spec->eth.val.src_mac); 1908 1909 if (ib_spec->eth.mask.vlan_tag) { 1910 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1911 cvlan_tag, 1); 1912 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1913 cvlan_tag, 1); 1914 1915 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1916 first_vid, ntohs(ib_spec->eth.mask.vlan_tag)); 1917 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1918 first_vid, ntohs(ib_spec->eth.val.vlan_tag)); 1919 1920 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1921 first_cfi, 1922 ntohs(ib_spec->eth.mask.vlan_tag) >> 12); 1923 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1924 first_cfi, 1925 ntohs(ib_spec->eth.val.vlan_tag) >> 12); 1926 1927 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1928 first_prio, 1929 ntohs(ib_spec->eth.mask.vlan_tag) >> 13); 1930 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1931 first_prio, 1932 ntohs(ib_spec->eth.val.vlan_tag) >> 13); 1933 } 1934 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1935 ethertype, ntohs(ib_spec->eth.mask.ether_type)); 1936 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1937 ethertype, ntohs(ib_spec->eth.val.ether_type)); 1938 break; 1939 case IB_FLOW_SPEC_IPV4: 1940 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD)) 1941 return -EOPNOTSUPP; 1942 1943 if (match_ipv) { 1944 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1945 ip_version, 0xf); 1946 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1947 ip_version, IPV4_VERSION); 1948 } else { 1949 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1950 ethertype, 0xffff); 1951 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1952 ethertype, ETH_P_IP); 1953 } 1954 1955 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 1956 src_ipv4_src_ipv6.ipv4_layout.ipv4), 1957 &ib_spec->ipv4.mask.src_ip, 1958 sizeof(ib_spec->ipv4.mask.src_ip)); 1959 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1960 src_ipv4_src_ipv6.ipv4_layout.ipv4), 1961 &ib_spec->ipv4.val.src_ip, 1962 sizeof(ib_spec->ipv4.val.src_ip)); 1963 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 1964 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 1965 &ib_spec->ipv4.mask.dst_ip, 1966 sizeof(ib_spec->ipv4.mask.dst_ip)); 1967 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1968 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 1969 &ib_spec->ipv4.val.dst_ip, 1970 sizeof(ib_spec->ipv4.val.dst_ip)); 1971 1972 set_tos(headers_c, headers_v, 1973 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos); 1974 1975 set_proto(headers_c, headers_v, 1976 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto); 1977 break; 1978 case IB_FLOW_SPEC_IPV6: 1979 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD)) 1980 return -EOPNOTSUPP; 1981 1982 if (match_ipv) { 1983 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1984 ip_version, 0xf); 1985 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1986 ip_version, IPV6_VERSION); 1987 } else { 1988 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1989 ethertype, 0xffff); 1990 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1991 ethertype, ETH_P_IPV6); 1992 } 1993 1994 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 1995 src_ipv4_src_ipv6.ipv6_layout.ipv6), 1996 &ib_spec->ipv6.mask.src_ip, 1997 sizeof(ib_spec->ipv6.mask.src_ip)); 1998 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1999 src_ipv4_src_ipv6.ipv6_layout.ipv6), 2000 &ib_spec->ipv6.val.src_ip, 2001 sizeof(ib_spec->ipv6.val.src_ip)); 2002 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2003 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 2004 &ib_spec->ipv6.mask.dst_ip, 2005 sizeof(ib_spec->ipv6.mask.dst_ip)); 2006 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2007 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 2008 &ib_spec->ipv6.val.dst_ip, 2009 sizeof(ib_spec->ipv6.val.dst_ip)); 2010 2011 set_tos(headers_c, headers_v, 2012 ib_spec->ipv6.mask.traffic_class, 2013 ib_spec->ipv6.val.traffic_class); 2014 2015 set_proto(headers_c, headers_v, 2016 ib_spec->ipv6.mask.next_hdr, 2017 ib_spec->ipv6.val.next_hdr); 2018 2019 set_flow_label(misc_params_c, misc_params_v, 2020 ntohl(ib_spec->ipv6.mask.flow_label), 2021 ntohl(ib_spec->ipv6.val.flow_label), 2022 ib_spec->type & IB_FLOW_SPEC_INNER); 2023 2024 break; 2025 case IB_FLOW_SPEC_TCP: 2026 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 2027 LAST_TCP_UDP_FIELD)) 2028 return -EOPNOTSUPP; 2029 2030 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol, 2031 0xff); 2032 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, 2033 IPPROTO_TCP); 2034 2035 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport, 2036 ntohs(ib_spec->tcp_udp.mask.src_port)); 2037 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport, 2038 ntohs(ib_spec->tcp_udp.val.src_port)); 2039 2040 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport, 2041 ntohs(ib_spec->tcp_udp.mask.dst_port)); 2042 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport, 2043 ntohs(ib_spec->tcp_udp.val.dst_port)); 2044 break; 2045 case IB_FLOW_SPEC_UDP: 2046 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 2047 LAST_TCP_UDP_FIELD)) 2048 return -EOPNOTSUPP; 2049 2050 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol, 2051 0xff); 2052 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, 2053 IPPROTO_UDP); 2054 2055 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport, 2056 ntohs(ib_spec->tcp_udp.mask.src_port)); 2057 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport, 2058 ntohs(ib_spec->tcp_udp.val.src_port)); 2059 2060 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport, 2061 ntohs(ib_spec->tcp_udp.mask.dst_port)); 2062 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, 2063 ntohs(ib_spec->tcp_udp.val.dst_port)); 2064 break; 2065 case IB_FLOW_SPEC_VXLAN_TUNNEL: 2066 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask, 2067 LAST_TUNNEL_FIELD)) 2068 return -EOPNOTSUPP; 2069 2070 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni, 2071 ntohl(ib_spec->tunnel.mask.tunnel_id)); 2072 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni, 2073 ntohl(ib_spec->tunnel.val.tunnel_id)); 2074 break; 2075 case IB_FLOW_SPEC_ACTION_TAG: 2076 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag, 2077 LAST_FLOW_TAG_FIELD)) 2078 return -EOPNOTSUPP; 2079 if (ib_spec->flow_tag.tag_id >= BIT(24)) 2080 return -EINVAL; 2081 2082 *tag_id = ib_spec->flow_tag.tag_id; 2083 break; 2084 case IB_FLOW_SPEC_ACTION_DROP: 2085 if (FIELDS_NOT_SUPPORTED(ib_spec->drop, 2086 LAST_DROP_FIELD)) 2087 return -EOPNOTSUPP; 2088 *is_drop = true; 2089 break; 2090 default: 2091 return -EINVAL; 2092 } 2093 2094 return 0; 2095 } 2096 2097 /* If a flow could catch both multicast and unicast packets, 2098 * it won't fall into the multicast flow steering table and this rule 2099 * could steal other multicast packets. 2100 */ 2101 static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr) 2102 { 2103 union ib_flow_spec *flow_spec; 2104 2105 if (ib_attr->type != IB_FLOW_ATTR_NORMAL || 2106 ib_attr->num_of_specs < 1) 2107 return false; 2108 2109 flow_spec = (union ib_flow_spec *)(ib_attr + 1); 2110 if (flow_spec->type == IB_FLOW_SPEC_IPV4) { 2111 struct ib_flow_spec_ipv4 *ipv4_spec; 2112 2113 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec; 2114 if (ipv4_is_multicast(ipv4_spec->val.dst_ip)) 2115 return true; 2116 2117 return false; 2118 } 2119 2120 if (flow_spec->type == IB_FLOW_SPEC_ETH) { 2121 struct ib_flow_spec_eth *eth_spec; 2122 2123 eth_spec = (struct ib_flow_spec_eth *)flow_spec; 2124 return is_multicast_ether_addr(eth_spec->mask.dst_mac) && 2125 is_multicast_ether_addr(eth_spec->val.dst_mac); 2126 } 2127 2128 return false; 2129 } 2130 2131 static bool is_valid_ethertype(struct mlx5_core_dev *mdev, 2132 const struct ib_flow_attr *flow_attr, 2133 bool check_inner) 2134 { 2135 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1); 2136 int match_ipv = check_inner ? 2137 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2138 ft_field_support.inner_ip_version) : 2139 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2140 ft_field_support.outer_ip_version); 2141 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0; 2142 bool ipv4_spec_valid, ipv6_spec_valid; 2143 unsigned int ip_spec_type = 0; 2144 bool has_ethertype = false; 2145 unsigned int spec_index; 2146 bool mask_valid = true; 2147 u16 eth_type = 0; 2148 bool type_valid; 2149 2150 /* Validate that ethertype is correct */ 2151 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 2152 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) && 2153 ib_spec->eth.mask.ether_type) { 2154 mask_valid = (ib_spec->eth.mask.ether_type == 2155 htons(0xffff)); 2156 has_ethertype = true; 2157 eth_type = ntohs(ib_spec->eth.val.ether_type); 2158 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) || 2159 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) { 2160 ip_spec_type = ib_spec->type; 2161 } 2162 ib_spec = (void *)ib_spec + ib_spec->size; 2163 } 2164 2165 type_valid = (!has_ethertype) || (!ip_spec_type); 2166 if (!type_valid && mask_valid) { 2167 ipv4_spec_valid = (eth_type == ETH_P_IP) && 2168 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit)); 2169 ipv6_spec_valid = (eth_type == ETH_P_IPV6) && 2170 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit)); 2171 2172 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) || 2173 (((eth_type == ETH_P_MPLS_UC) || 2174 (eth_type == ETH_P_MPLS_MC)) && match_ipv); 2175 } 2176 2177 return type_valid; 2178 } 2179 2180 static bool is_valid_attr(struct mlx5_core_dev *mdev, 2181 const struct ib_flow_attr *flow_attr) 2182 { 2183 return is_valid_ethertype(mdev, flow_attr, false) && 2184 is_valid_ethertype(mdev, flow_attr, true); 2185 } 2186 2187 static void put_flow_table(struct mlx5_ib_dev *dev, 2188 struct mlx5_ib_flow_prio *prio, bool ft_added) 2189 { 2190 prio->refcount -= !!ft_added; 2191 if (!prio->refcount) { 2192 mlx5_destroy_flow_table(prio->flow_table); 2193 prio->flow_table = NULL; 2194 } 2195 } 2196 2197 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id) 2198 { 2199 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device); 2200 struct mlx5_ib_flow_handler *handler = container_of(flow_id, 2201 struct mlx5_ib_flow_handler, 2202 ibflow); 2203 struct mlx5_ib_flow_handler *iter, *tmp; 2204 2205 mutex_lock(&dev->flow_db.lock); 2206 2207 list_for_each_entry_safe(iter, tmp, &handler->list, list) { 2208 mlx5_del_flow_rules(iter->rule); 2209 put_flow_table(dev, iter->prio, true); 2210 list_del(&iter->list); 2211 kfree(iter); 2212 } 2213 2214 mlx5_del_flow_rules(handler->rule); 2215 put_flow_table(dev, handler->prio, true); 2216 mutex_unlock(&dev->flow_db.lock); 2217 2218 kfree(handler); 2219 2220 return 0; 2221 } 2222 2223 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap) 2224 { 2225 priority *= 2; 2226 if (!dont_trap) 2227 priority++; 2228 return priority; 2229 } 2230 2231 enum flow_table_type { 2232 MLX5_IB_FT_RX, 2233 MLX5_IB_FT_TX 2234 }; 2235 2236 #define MLX5_FS_MAX_TYPES 6 2237 #define MLX5_FS_MAX_ENTRIES BIT(16) 2238 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev, 2239 struct ib_flow_attr *flow_attr, 2240 enum flow_table_type ft_type) 2241 { 2242 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP; 2243 struct mlx5_flow_namespace *ns = NULL; 2244 struct mlx5_ib_flow_prio *prio; 2245 struct mlx5_flow_table *ft; 2246 int max_table_size; 2247 int num_entries; 2248 int num_groups; 2249 int priority; 2250 int err = 0; 2251 2252 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 2253 log_max_ft_size)); 2254 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 2255 if (flow_is_multicast_only(flow_attr) && 2256 !dont_trap) 2257 priority = MLX5_IB_FLOW_MCAST_PRIO; 2258 else 2259 priority = ib_prio_to_core_prio(flow_attr->priority, 2260 dont_trap); 2261 ns = mlx5_get_flow_namespace(dev->mdev, 2262 MLX5_FLOW_NAMESPACE_BYPASS); 2263 num_entries = MLX5_FS_MAX_ENTRIES; 2264 num_groups = MLX5_FS_MAX_TYPES; 2265 prio = &dev->flow_db.prios[priority]; 2266 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 2267 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 2268 ns = mlx5_get_flow_namespace(dev->mdev, 2269 MLX5_FLOW_NAMESPACE_LEFTOVERS); 2270 build_leftovers_ft_param(&priority, 2271 &num_entries, 2272 &num_groups); 2273 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO]; 2274 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 2275 if (!MLX5_CAP_FLOWTABLE(dev->mdev, 2276 allow_sniffer_and_nic_rx_shared_tir)) 2277 return ERR_PTR(-ENOTSUPP); 2278 2279 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ? 2280 MLX5_FLOW_NAMESPACE_SNIFFER_RX : 2281 MLX5_FLOW_NAMESPACE_SNIFFER_TX); 2282 2283 prio = &dev->flow_db.sniffer[ft_type]; 2284 priority = 0; 2285 num_entries = 1; 2286 num_groups = 1; 2287 } 2288 2289 if (!ns) 2290 return ERR_PTR(-ENOTSUPP); 2291 2292 if (num_entries > max_table_size) 2293 return ERR_PTR(-ENOMEM); 2294 2295 ft = prio->flow_table; 2296 if (!ft) { 2297 ft = mlx5_create_auto_grouped_flow_table(ns, priority, 2298 num_entries, 2299 num_groups, 2300 0, 0); 2301 2302 if (!IS_ERR(ft)) { 2303 prio->refcount = 0; 2304 prio->flow_table = ft; 2305 } else { 2306 err = PTR_ERR(ft); 2307 } 2308 } 2309 2310 return err ? ERR_PTR(err) : prio; 2311 } 2312 2313 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev, 2314 struct mlx5_ib_flow_prio *ft_prio, 2315 const struct ib_flow_attr *flow_attr, 2316 struct mlx5_flow_destination *dst) 2317 { 2318 struct mlx5_flow_table *ft = ft_prio->flow_table; 2319 struct mlx5_ib_flow_handler *handler; 2320 struct mlx5_flow_act flow_act = {0}; 2321 struct mlx5_flow_spec *spec; 2322 struct mlx5_flow_destination *rule_dst = dst; 2323 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr); 2324 unsigned int spec_index; 2325 u32 flow_tag = MLX5_FS_DEFAULT_FLOW_TAG; 2326 bool is_drop = false; 2327 int err = 0; 2328 int dest_num = 1; 2329 2330 if (!is_valid_attr(dev->mdev, flow_attr)) 2331 return ERR_PTR(-EINVAL); 2332 2333 spec = kvzalloc(sizeof(*spec), GFP_KERNEL); 2334 handler = kzalloc(sizeof(*handler), GFP_KERNEL); 2335 if (!handler || !spec) { 2336 err = -ENOMEM; 2337 goto free; 2338 } 2339 2340 INIT_LIST_HEAD(&handler->list); 2341 2342 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 2343 err = parse_flow_attr(dev->mdev, spec->match_criteria, 2344 spec->match_value, 2345 ib_flow, &flow_tag, &is_drop); 2346 if (err < 0) 2347 goto free; 2348 2349 ib_flow += ((union ib_flow_spec *)ib_flow)->size; 2350 } 2351 2352 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria); 2353 if (is_drop) { 2354 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_DROP; 2355 rule_dst = NULL; 2356 dest_num = 0; 2357 } else { 2358 flow_act.action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST : 2359 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO; 2360 } 2361 2362 if (flow_tag != MLX5_FS_DEFAULT_FLOW_TAG && 2363 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 2364 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) { 2365 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n", 2366 flow_tag, flow_attr->type); 2367 err = -EINVAL; 2368 goto free; 2369 } 2370 flow_act.flow_tag = flow_tag; 2371 handler->rule = mlx5_add_flow_rules(ft, spec, 2372 &flow_act, 2373 rule_dst, dest_num); 2374 2375 if (IS_ERR(handler->rule)) { 2376 err = PTR_ERR(handler->rule); 2377 goto free; 2378 } 2379 2380 ft_prio->refcount++; 2381 handler->prio = ft_prio; 2382 2383 ft_prio->flow_table = ft; 2384 free: 2385 if (err) 2386 kfree(handler); 2387 kvfree(spec); 2388 return err ? ERR_PTR(err) : handler; 2389 } 2390 2391 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev, 2392 struct mlx5_ib_flow_prio *ft_prio, 2393 struct ib_flow_attr *flow_attr, 2394 struct mlx5_flow_destination *dst) 2395 { 2396 struct mlx5_ib_flow_handler *handler_dst = NULL; 2397 struct mlx5_ib_flow_handler *handler = NULL; 2398 2399 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL); 2400 if (!IS_ERR(handler)) { 2401 handler_dst = create_flow_rule(dev, ft_prio, 2402 flow_attr, dst); 2403 if (IS_ERR(handler_dst)) { 2404 mlx5_del_flow_rules(handler->rule); 2405 ft_prio->refcount--; 2406 kfree(handler); 2407 handler = handler_dst; 2408 } else { 2409 list_add(&handler_dst->list, &handler->list); 2410 } 2411 } 2412 2413 return handler; 2414 } 2415 enum { 2416 LEFTOVERS_MC, 2417 LEFTOVERS_UC, 2418 }; 2419 2420 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev, 2421 struct mlx5_ib_flow_prio *ft_prio, 2422 struct ib_flow_attr *flow_attr, 2423 struct mlx5_flow_destination *dst) 2424 { 2425 struct mlx5_ib_flow_handler *handler_ucast = NULL; 2426 struct mlx5_ib_flow_handler *handler = NULL; 2427 2428 static struct { 2429 struct ib_flow_attr flow_attr; 2430 struct ib_flow_spec_eth eth_flow; 2431 } leftovers_specs[] = { 2432 [LEFTOVERS_MC] = { 2433 .flow_attr = { 2434 .num_of_specs = 1, 2435 .size = sizeof(leftovers_specs[0]) 2436 }, 2437 .eth_flow = { 2438 .type = IB_FLOW_SPEC_ETH, 2439 .size = sizeof(struct ib_flow_spec_eth), 2440 .mask = {.dst_mac = {0x1} }, 2441 .val = {.dst_mac = {0x1} } 2442 } 2443 }, 2444 [LEFTOVERS_UC] = { 2445 .flow_attr = { 2446 .num_of_specs = 1, 2447 .size = sizeof(leftovers_specs[0]) 2448 }, 2449 .eth_flow = { 2450 .type = IB_FLOW_SPEC_ETH, 2451 .size = sizeof(struct ib_flow_spec_eth), 2452 .mask = {.dst_mac = {0x1} }, 2453 .val = {.dst_mac = {} } 2454 } 2455 } 2456 }; 2457 2458 handler = create_flow_rule(dev, ft_prio, 2459 &leftovers_specs[LEFTOVERS_MC].flow_attr, 2460 dst); 2461 if (!IS_ERR(handler) && 2462 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) { 2463 handler_ucast = create_flow_rule(dev, ft_prio, 2464 &leftovers_specs[LEFTOVERS_UC].flow_attr, 2465 dst); 2466 if (IS_ERR(handler_ucast)) { 2467 mlx5_del_flow_rules(handler->rule); 2468 ft_prio->refcount--; 2469 kfree(handler); 2470 handler = handler_ucast; 2471 } else { 2472 list_add(&handler_ucast->list, &handler->list); 2473 } 2474 } 2475 2476 return handler; 2477 } 2478 2479 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev, 2480 struct mlx5_ib_flow_prio *ft_rx, 2481 struct mlx5_ib_flow_prio *ft_tx, 2482 struct mlx5_flow_destination *dst) 2483 { 2484 struct mlx5_ib_flow_handler *handler_rx; 2485 struct mlx5_ib_flow_handler *handler_tx; 2486 int err; 2487 static const struct ib_flow_attr flow_attr = { 2488 .num_of_specs = 0, 2489 .size = sizeof(flow_attr) 2490 }; 2491 2492 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst); 2493 if (IS_ERR(handler_rx)) { 2494 err = PTR_ERR(handler_rx); 2495 goto err; 2496 } 2497 2498 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst); 2499 if (IS_ERR(handler_tx)) { 2500 err = PTR_ERR(handler_tx); 2501 goto err_tx; 2502 } 2503 2504 list_add(&handler_tx->list, &handler_rx->list); 2505 2506 return handler_rx; 2507 2508 err_tx: 2509 mlx5_del_flow_rules(handler_rx->rule); 2510 ft_rx->refcount--; 2511 kfree(handler_rx); 2512 err: 2513 return ERR_PTR(err); 2514 } 2515 2516 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp, 2517 struct ib_flow_attr *flow_attr, 2518 int domain) 2519 { 2520 struct mlx5_ib_dev *dev = to_mdev(qp->device); 2521 struct mlx5_ib_qp *mqp = to_mqp(qp); 2522 struct mlx5_ib_flow_handler *handler = NULL; 2523 struct mlx5_flow_destination *dst = NULL; 2524 struct mlx5_ib_flow_prio *ft_prio_tx = NULL; 2525 struct mlx5_ib_flow_prio *ft_prio; 2526 int err; 2527 2528 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) 2529 return ERR_PTR(-ENOMEM); 2530 2531 if (domain != IB_FLOW_DOMAIN_USER || 2532 flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) || 2533 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP)) 2534 return ERR_PTR(-EINVAL); 2535 2536 dst = kzalloc(sizeof(*dst), GFP_KERNEL); 2537 if (!dst) 2538 return ERR_PTR(-ENOMEM); 2539 2540 mutex_lock(&dev->flow_db.lock); 2541 2542 ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX); 2543 if (IS_ERR(ft_prio)) { 2544 err = PTR_ERR(ft_prio); 2545 goto unlock; 2546 } 2547 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 2548 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX); 2549 if (IS_ERR(ft_prio_tx)) { 2550 err = PTR_ERR(ft_prio_tx); 2551 ft_prio_tx = NULL; 2552 goto destroy_ft; 2553 } 2554 } 2555 2556 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR; 2557 if (mqp->flags & MLX5_IB_QP_RSS) 2558 dst->tir_num = mqp->rss_qp.tirn; 2559 else 2560 dst->tir_num = mqp->raw_packet_qp.rq.tirn; 2561 2562 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 2563 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) { 2564 handler = create_dont_trap_rule(dev, ft_prio, 2565 flow_attr, dst); 2566 } else { 2567 handler = create_flow_rule(dev, ft_prio, flow_attr, 2568 dst); 2569 } 2570 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 2571 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 2572 handler = create_leftovers_rule(dev, ft_prio, flow_attr, 2573 dst); 2574 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 2575 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst); 2576 } else { 2577 err = -EINVAL; 2578 goto destroy_ft; 2579 } 2580 2581 if (IS_ERR(handler)) { 2582 err = PTR_ERR(handler); 2583 handler = NULL; 2584 goto destroy_ft; 2585 } 2586 2587 mutex_unlock(&dev->flow_db.lock); 2588 kfree(dst); 2589 2590 return &handler->ibflow; 2591 2592 destroy_ft: 2593 put_flow_table(dev, ft_prio, false); 2594 if (ft_prio_tx) 2595 put_flow_table(dev, ft_prio_tx, false); 2596 unlock: 2597 mutex_unlock(&dev->flow_db.lock); 2598 kfree(dst); 2599 kfree(handler); 2600 return ERR_PTR(err); 2601 } 2602 2603 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2604 { 2605 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2606 struct mlx5_ib_qp *mqp = to_mqp(ibqp); 2607 int err; 2608 2609 if (mqp->flags & MLX5_IB_QP_UNDERLAY) { 2610 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n"); 2611 return -EOPNOTSUPP; 2612 } 2613 2614 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num); 2615 if (err) 2616 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 2617 ibqp->qp_num, gid->raw); 2618 2619 return err; 2620 } 2621 2622 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2623 { 2624 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2625 int err; 2626 2627 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num); 2628 if (err) 2629 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 2630 ibqp->qp_num, gid->raw); 2631 2632 return err; 2633 } 2634 2635 static int init_node_data(struct mlx5_ib_dev *dev) 2636 { 2637 int err; 2638 2639 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 2640 if (err) 2641 return err; 2642 2643 dev->mdev->rev_id = dev->mdev->pdev->revision; 2644 2645 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 2646 } 2647 2648 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr, 2649 char *buf) 2650 { 2651 struct mlx5_ib_dev *dev = 2652 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2653 2654 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages); 2655 } 2656 2657 static ssize_t show_reg_pages(struct device *device, 2658 struct device_attribute *attr, char *buf) 2659 { 2660 struct mlx5_ib_dev *dev = 2661 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2662 2663 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 2664 } 2665 2666 static ssize_t show_hca(struct device *device, struct device_attribute *attr, 2667 char *buf) 2668 { 2669 struct mlx5_ib_dev *dev = 2670 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2671 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device); 2672 } 2673 2674 static ssize_t show_rev(struct device *device, struct device_attribute *attr, 2675 char *buf) 2676 { 2677 struct mlx5_ib_dev *dev = 2678 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2679 return sprintf(buf, "%x\n", dev->mdev->rev_id); 2680 } 2681 2682 static ssize_t show_board(struct device *device, struct device_attribute *attr, 2683 char *buf) 2684 { 2685 struct mlx5_ib_dev *dev = 2686 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2687 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 2688 dev->mdev->board_id); 2689 } 2690 2691 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL); 2692 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL); 2693 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL); 2694 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL); 2695 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL); 2696 2697 static struct device_attribute *mlx5_class_attributes[] = { 2698 &dev_attr_hw_rev, 2699 &dev_attr_hca_type, 2700 &dev_attr_board_id, 2701 &dev_attr_fw_pages, 2702 &dev_attr_reg_pages, 2703 }; 2704 2705 static void pkey_change_handler(struct work_struct *work) 2706 { 2707 struct mlx5_ib_port_resources *ports = 2708 container_of(work, struct mlx5_ib_port_resources, 2709 pkey_change_work); 2710 2711 mutex_lock(&ports->devr->mutex); 2712 mlx5_ib_gsi_pkey_change(ports->gsi); 2713 mutex_unlock(&ports->devr->mutex); 2714 } 2715 2716 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 2717 { 2718 struct mlx5_ib_qp *mqp; 2719 struct mlx5_ib_cq *send_mcq, *recv_mcq; 2720 struct mlx5_core_cq *mcq; 2721 struct list_head cq_armed_list; 2722 unsigned long flags_qp; 2723 unsigned long flags_cq; 2724 unsigned long flags; 2725 2726 INIT_LIST_HEAD(&cq_armed_list); 2727 2728 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 2729 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 2730 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 2731 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 2732 if (mqp->sq.tail != mqp->sq.head) { 2733 send_mcq = to_mcq(mqp->ibqp.send_cq); 2734 spin_lock_irqsave(&send_mcq->lock, flags_cq); 2735 if (send_mcq->mcq.comp && 2736 mqp->ibqp.send_cq->comp_handler) { 2737 if (!send_mcq->mcq.reset_notify_added) { 2738 send_mcq->mcq.reset_notify_added = 1; 2739 list_add_tail(&send_mcq->mcq.reset_notify, 2740 &cq_armed_list); 2741 } 2742 } 2743 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 2744 } 2745 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 2746 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 2747 /* no handling is needed for SRQ */ 2748 if (!mqp->ibqp.srq) { 2749 if (mqp->rq.tail != mqp->rq.head) { 2750 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 2751 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 2752 if (recv_mcq->mcq.comp && 2753 mqp->ibqp.recv_cq->comp_handler) { 2754 if (!recv_mcq->mcq.reset_notify_added) { 2755 recv_mcq->mcq.reset_notify_added = 1; 2756 list_add_tail(&recv_mcq->mcq.reset_notify, 2757 &cq_armed_list); 2758 } 2759 } 2760 spin_unlock_irqrestore(&recv_mcq->lock, 2761 flags_cq); 2762 } 2763 } 2764 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 2765 } 2766 /*At that point all inflight post send were put to be executed as of we 2767 * lock/unlock above locks Now need to arm all involved CQs. 2768 */ 2769 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 2770 mcq->comp(mcq); 2771 } 2772 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 2773 } 2774 2775 static void delay_drop_handler(struct work_struct *work) 2776 { 2777 int err; 2778 struct mlx5_ib_delay_drop *delay_drop = 2779 container_of(work, struct mlx5_ib_delay_drop, 2780 delay_drop_work); 2781 2782 atomic_inc(&delay_drop->events_cnt); 2783 2784 mutex_lock(&delay_drop->lock); 2785 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev, 2786 delay_drop->timeout); 2787 if (err) { 2788 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n", 2789 delay_drop->timeout); 2790 delay_drop->activate = false; 2791 } 2792 mutex_unlock(&delay_drop->lock); 2793 } 2794 2795 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context, 2796 enum mlx5_dev_event event, unsigned long param) 2797 { 2798 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context; 2799 struct ib_event ibev; 2800 bool fatal = false; 2801 u8 port = 0; 2802 2803 switch (event) { 2804 case MLX5_DEV_EVENT_SYS_ERROR: 2805 ibev.event = IB_EVENT_DEVICE_FATAL; 2806 mlx5_ib_handle_internal_error(ibdev); 2807 fatal = true; 2808 break; 2809 2810 case MLX5_DEV_EVENT_PORT_UP: 2811 case MLX5_DEV_EVENT_PORT_DOWN: 2812 case MLX5_DEV_EVENT_PORT_INITIALIZED: 2813 port = (u8)param; 2814 2815 /* In RoCE, port up/down events are handled in 2816 * mlx5_netdev_event(). 2817 */ 2818 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2819 IB_LINK_LAYER_ETHERNET) 2820 return; 2821 2822 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ? 2823 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 2824 break; 2825 2826 case MLX5_DEV_EVENT_LID_CHANGE: 2827 ibev.event = IB_EVENT_LID_CHANGE; 2828 port = (u8)param; 2829 break; 2830 2831 case MLX5_DEV_EVENT_PKEY_CHANGE: 2832 ibev.event = IB_EVENT_PKEY_CHANGE; 2833 port = (u8)param; 2834 2835 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 2836 break; 2837 2838 case MLX5_DEV_EVENT_GUID_CHANGE: 2839 ibev.event = IB_EVENT_GID_CHANGE; 2840 port = (u8)param; 2841 break; 2842 2843 case MLX5_DEV_EVENT_CLIENT_REREG: 2844 ibev.event = IB_EVENT_CLIENT_REREGISTER; 2845 port = (u8)param; 2846 break; 2847 case MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT: 2848 schedule_work(&ibdev->delay_drop.delay_drop_work); 2849 goto out; 2850 default: 2851 goto out; 2852 } 2853 2854 ibev.device = &ibdev->ib_dev; 2855 ibev.element.port_num = port; 2856 2857 if (port < 1 || port > ibdev->num_ports) { 2858 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port); 2859 goto out; 2860 } 2861 2862 if (ibdev->ib_active) 2863 ib_dispatch_event(&ibev); 2864 2865 if (fatal) 2866 ibdev->ib_active = false; 2867 2868 out: 2869 return; 2870 } 2871 2872 static int set_has_smi_cap(struct mlx5_ib_dev *dev) 2873 { 2874 struct mlx5_hca_vport_context vport_ctx; 2875 int err; 2876 int port; 2877 2878 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) { 2879 dev->mdev->port_caps[port - 1].has_smi = false; 2880 if (MLX5_CAP_GEN(dev->mdev, port_type) == 2881 MLX5_CAP_PORT_TYPE_IB) { 2882 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) { 2883 err = mlx5_query_hca_vport_context(dev->mdev, 0, 2884 port, 0, 2885 &vport_ctx); 2886 if (err) { 2887 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n", 2888 port, err); 2889 return err; 2890 } 2891 dev->mdev->port_caps[port - 1].has_smi = 2892 vport_ctx.has_smi; 2893 } else { 2894 dev->mdev->port_caps[port - 1].has_smi = true; 2895 } 2896 } 2897 } 2898 return 0; 2899 } 2900 2901 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 2902 { 2903 int port; 2904 2905 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) 2906 mlx5_query_ext_port_caps(dev, port); 2907 } 2908 2909 static int get_port_caps(struct mlx5_ib_dev *dev) 2910 { 2911 struct ib_device_attr *dprops = NULL; 2912 struct ib_port_attr *pprops = NULL; 2913 int err = -ENOMEM; 2914 int port; 2915 struct ib_udata uhw = {.inlen = 0, .outlen = 0}; 2916 2917 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL); 2918 if (!pprops) 2919 goto out; 2920 2921 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL); 2922 if (!dprops) 2923 goto out; 2924 2925 err = set_has_smi_cap(dev); 2926 if (err) 2927 goto out; 2928 2929 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw); 2930 if (err) { 2931 mlx5_ib_warn(dev, "query_device failed %d\n", err); 2932 goto out; 2933 } 2934 2935 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) { 2936 memset(pprops, 0, sizeof(*pprops)); 2937 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops); 2938 if (err) { 2939 mlx5_ib_warn(dev, "query_port %d failed %d\n", 2940 port, err); 2941 break; 2942 } 2943 dev->mdev->port_caps[port - 1].pkey_table_len = 2944 dprops->max_pkeys; 2945 dev->mdev->port_caps[port - 1].gid_table_len = 2946 pprops->gid_tbl_len; 2947 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n", 2948 dprops->max_pkeys, pprops->gid_tbl_len); 2949 } 2950 2951 out: 2952 kfree(pprops); 2953 kfree(dprops); 2954 2955 return err; 2956 } 2957 2958 static void destroy_umrc_res(struct mlx5_ib_dev *dev) 2959 { 2960 int err; 2961 2962 err = mlx5_mr_cache_cleanup(dev); 2963 if (err) 2964 mlx5_ib_warn(dev, "mr cache cleanup failed\n"); 2965 2966 mlx5_ib_destroy_qp(dev->umrc.qp); 2967 ib_free_cq(dev->umrc.cq); 2968 ib_dealloc_pd(dev->umrc.pd); 2969 } 2970 2971 enum { 2972 MAX_UMR_WR = 128, 2973 }; 2974 2975 static int create_umr_res(struct mlx5_ib_dev *dev) 2976 { 2977 struct ib_qp_init_attr *init_attr = NULL; 2978 struct ib_qp_attr *attr = NULL; 2979 struct ib_pd *pd; 2980 struct ib_cq *cq; 2981 struct ib_qp *qp; 2982 int ret; 2983 2984 attr = kzalloc(sizeof(*attr), GFP_KERNEL); 2985 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL); 2986 if (!attr || !init_attr) { 2987 ret = -ENOMEM; 2988 goto error_0; 2989 } 2990 2991 pd = ib_alloc_pd(&dev->ib_dev, 0); 2992 if (IS_ERR(pd)) { 2993 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n"); 2994 ret = PTR_ERR(pd); 2995 goto error_0; 2996 } 2997 2998 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ); 2999 if (IS_ERR(cq)) { 3000 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n"); 3001 ret = PTR_ERR(cq); 3002 goto error_2; 3003 } 3004 3005 init_attr->send_cq = cq; 3006 init_attr->recv_cq = cq; 3007 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR; 3008 init_attr->cap.max_send_wr = MAX_UMR_WR; 3009 init_attr->cap.max_send_sge = 1; 3010 init_attr->qp_type = MLX5_IB_QPT_REG_UMR; 3011 init_attr->port_num = 1; 3012 qp = mlx5_ib_create_qp(pd, init_attr, NULL); 3013 if (IS_ERR(qp)) { 3014 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n"); 3015 ret = PTR_ERR(qp); 3016 goto error_3; 3017 } 3018 qp->device = &dev->ib_dev; 3019 qp->real_qp = qp; 3020 qp->uobject = NULL; 3021 qp->qp_type = MLX5_IB_QPT_REG_UMR; 3022 3023 attr->qp_state = IB_QPS_INIT; 3024 attr->port_num = 1; 3025 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX | 3026 IB_QP_PORT, NULL); 3027 if (ret) { 3028 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n"); 3029 goto error_4; 3030 } 3031 3032 memset(attr, 0, sizeof(*attr)); 3033 attr->qp_state = IB_QPS_RTR; 3034 attr->path_mtu = IB_MTU_256; 3035 3036 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 3037 if (ret) { 3038 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n"); 3039 goto error_4; 3040 } 3041 3042 memset(attr, 0, sizeof(*attr)); 3043 attr->qp_state = IB_QPS_RTS; 3044 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 3045 if (ret) { 3046 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n"); 3047 goto error_4; 3048 } 3049 3050 dev->umrc.qp = qp; 3051 dev->umrc.cq = cq; 3052 dev->umrc.pd = pd; 3053 3054 sema_init(&dev->umrc.sem, MAX_UMR_WR); 3055 ret = mlx5_mr_cache_init(dev); 3056 if (ret) { 3057 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 3058 goto error_4; 3059 } 3060 3061 kfree(attr); 3062 kfree(init_attr); 3063 3064 return 0; 3065 3066 error_4: 3067 mlx5_ib_destroy_qp(qp); 3068 3069 error_3: 3070 ib_free_cq(cq); 3071 3072 error_2: 3073 ib_dealloc_pd(pd); 3074 3075 error_0: 3076 kfree(attr); 3077 kfree(init_attr); 3078 return ret; 3079 } 3080 3081 static u8 mlx5_get_umr_fence(u8 umr_fence_cap) 3082 { 3083 switch (umr_fence_cap) { 3084 case MLX5_CAP_UMR_FENCE_NONE: 3085 return MLX5_FENCE_MODE_NONE; 3086 case MLX5_CAP_UMR_FENCE_SMALL: 3087 return MLX5_FENCE_MODE_INITIATOR_SMALL; 3088 default: 3089 return MLX5_FENCE_MODE_STRONG_ORDERING; 3090 } 3091 } 3092 3093 static int create_dev_resources(struct mlx5_ib_resources *devr) 3094 { 3095 struct ib_srq_init_attr attr; 3096 struct mlx5_ib_dev *dev; 3097 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 3098 int port; 3099 int ret = 0; 3100 3101 dev = container_of(devr, struct mlx5_ib_dev, devr); 3102 3103 mutex_init(&devr->mutex); 3104 3105 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL); 3106 if (IS_ERR(devr->p0)) { 3107 ret = PTR_ERR(devr->p0); 3108 goto error0; 3109 } 3110 devr->p0->device = &dev->ib_dev; 3111 devr->p0->uobject = NULL; 3112 atomic_set(&devr->p0->usecnt, 0); 3113 3114 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL); 3115 if (IS_ERR(devr->c0)) { 3116 ret = PTR_ERR(devr->c0); 3117 goto error1; 3118 } 3119 devr->c0->device = &dev->ib_dev; 3120 devr->c0->uobject = NULL; 3121 devr->c0->comp_handler = NULL; 3122 devr->c0->event_handler = NULL; 3123 devr->c0->cq_context = NULL; 3124 atomic_set(&devr->c0->usecnt, 0); 3125 3126 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 3127 if (IS_ERR(devr->x0)) { 3128 ret = PTR_ERR(devr->x0); 3129 goto error2; 3130 } 3131 devr->x0->device = &dev->ib_dev; 3132 devr->x0->inode = NULL; 3133 atomic_set(&devr->x0->usecnt, 0); 3134 mutex_init(&devr->x0->tgt_qp_mutex); 3135 INIT_LIST_HEAD(&devr->x0->tgt_qp_list); 3136 3137 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 3138 if (IS_ERR(devr->x1)) { 3139 ret = PTR_ERR(devr->x1); 3140 goto error3; 3141 } 3142 devr->x1->device = &dev->ib_dev; 3143 devr->x1->inode = NULL; 3144 atomic_set(&devr->x1->usecnt, 0); 3145 mutex_init(&devr->x1->tgt_qp_mutex); 3146 INIT_LIST_HEAD(&devr->x1->tgt_qp_list); 3147 3148 memset(&attr, 0, sizeof(attr)); 3149 attr.attr.max_sge = 1; 3150 attr.attr.max_wr = 1; 3151 attr.srq_type = IB_SRQT_XRC; 3152 attr.ext.xrc.cq = devr->c0; 3153 attr.ext.xrc.xrcd = devr->x0; 3154 3155 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 3156 if (IS_ERR(devr->s0)) { 3157 ret = PTR_ERR(devr->s0); 3158 goto error4; 3159 } 3160 devr->s0->device = &dev->ib_dev; 3161 devr->s0->pd = devr->p0; 3162 devr->s0->uobject = NULL; 3163 devr->s0->event_handler = NULL; 3164 devr->s0->srq_context = NULL; 3165 devr->s0->srq_type = IB_SRQT_XRC; 3166 devr->s0->ext.xrc.xrcd = devr->x0; 3167 devr->s0->ext.xrc.cq = devr->c0; 3168 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt); 3169 atomic_inc(&devr->s0->ext.xrc.cq->usecnt); 3170 atomic_inc(&devr->p0->usecnt); 3171 atomic_set(&devr->s0->usecnt, 0); 3172 3173 memset(&attr, 0, sizeof(attr)); 3174 attr.attr.max_sge = 1; 3175 attr.attr.max_wr = 1; 3176 attr.srq_type = IB_SRQT_BASIC; 3177 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 3178 if (IS_ERR(devr->s1)) { 3179 ret = PTR_ERR(devr->s1); 3180 goto error5; 3181 } 3182 devr->s1->device = &dev->ib_dev; 3183 devr->s1->pd = devr->p0; 3184 devr->s1->uobject = NULL; 3185 devr->s1->event_handler = NULL; 3186 devr->s1->srq_context = NULL; 3187 devr->s1->srq_type = IB_SRQT_BASIC; 3188 devr->s1->ext.xrc.cq = devr->c0; 3189 atomic_inc(&devr->p0->usecnt); 3190 atomic_set(&devr->s0->usecnt, 0); 3191 3192 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) { 3193 INIT_WORK(&devr->ports[port].pkey_change_work, 3194 pkey_change_handler); 3195 devr->ports[port].devr = devr; 3196 } 3197 3198 return 0; 3199 3200 error5: 3201 mlx5_ib_destroy_srq(devr->s0); 3202 error4: 3203 mlx5_ib_dealloc_xrcd(devr->x1); 3204 error3: 3205 mlx5_ib_dealloc_xrcd(devr->x0); 3206 error2: 3207 mlx5_ib_destroy_cq(devr->c0); 3208 error1: 3209 mlx5_ib_dealloc_pd(devr->p0); 3210 error0: 3211 return ret; 3212 } 3213 3214 static void destroy_dev_resources(struct mlx5_ib_resources *devr) 3215 { 3216 struct mlx5_ib_dev *dev = 3217 container_of(devr, struct mlx5_ib_dev, devr); 3218 int port; 3219 3220 mlx5_ib_destroy_srq(devr->s1); 3221 mlx5_ib_destroy_srq(devr->s0); 3222 mlx5_ib_dealloc_xrcd(devr->x0); 3223 mlx5_ib_dealloc_xrcd(devr->x1); 3224 mlx5_ib_destroy_cq(devr->c0); 3225 mlx5_ib_dealloc_pd(devr->p0); 3226 3227 /* Make sure no change P_Key work items are still executing */ 3228 for (port = 0; port < dev->num_ports; ++port) 3229 cancel_work_sync(&devr->ports[port].pkey_change_work); 3230 } 3231 3232 static u32 get_core_cap_flags(struct ib_device *ibdev) 3233 { 3234 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3235 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 3236 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 3237 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 3238 u32 ret = 0; 3239 3240 if (ll == IB_LINK_LAYER_INFINIBAND) 3241 return RDMA_CORE_PORT_IBA_IB; 3242 3243 ret = RDMA_CORE_PORT_RAW_PACKET; 3244 3245 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 3246 return ret; 3247 3248 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 3249 return ret; 3250 3251 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 3252 ret |= RDMA_CORE_PORT_IBA_ROCE; 3253 3254 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 3255 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 3256 3257 return ret; 3258 } 3259 3260 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num, 3261 struct ib_port_immutable *immutable) 3262 { 3263 struct ib_port_attr attr; 3264 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3265 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num); 3266 int err; 3267 3268 immutable->core_cap_flags = get_core_cap_flags(ibdev); 3269 3270 err = ib_query_port(ibdev, port_num, &attr); 3271 if (err) 3272 return err; 3273 3274 immutable->pkey_tbl_len = attr.pkey_tbl_len; 3275 immutable->gid_tbl_len = attr.gid_tbl_len; 3276 immutable->core_cap_flags = get_core_cap_flags(ibdev); 3277 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce)) 3278 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 3279 3280 return 0; 3281 } 3282 3283 static void get_dev_fw_str(struct ib_device *ibdev, char *str) 3284 { 3285 struct mlx5_ib_dev *dev = 3286 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 3287 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d", 3288 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev), 3289 fw_rev_sub(dev->mdev)); 3290 } 3291 3292 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev) 3293 { 3294 struct mlx5_core_dev *mdev = dev->mdev; 3295 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev, 3296 MLX5_FLOW_NAMESPACE_LAG); 3297 struct mlx5_flow_table *ft; 3298 int err; 3299 3300 if (!ns || !mlx5_lag_is_active(mdev)) 3301 return 0; 3302 3303 err = mlx5_cmd_create_vport_lag(mdev); 3304 if (err) 3305 return err; 3306 3307 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0); 3308 if (IS_ERR(ft)) { 3309 err = PTR_ERR(ft); 3310 goto err_destroy_vport_lag; 3311 } 3312 3313 dev->flow_db.lag_demux_ft = ft; 3314 return 0; 3315 3316 err_destroy_vport_lag: 3317 mlx5_cmd_destroy_vport_lag(mdev); 3318 return err; 3319 } 3320 3321 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev) 3322 { 3323 struct mlx5_core_dev *mdev = dev->mdev; 3324 3325 if (dev->flow_db.lag_demux_ft) { 3326 mlx5_destroy_flow_table(dev->flow_db.lag_demux_ft); 3327 dev->flow_db.lag_demux_ft = NULL; 3328 3329 mlx5_cmd_destroy_vport_lag(mdev); 3330 } 3331 } 3332 3333 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev) 3334 { 3335 int err; 3336 3337 dev->roce.nb.notifier_call = mlx5_netdev_event; 3338 err = register_netdevice_notifier(&dev->roce.nb); 3339 if (err) { 3340 dev->roce.nb.notifier_call = NULL; 3341 return err; 3342 } 3343 3344 return 0; 3345 } 3346 3347 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev) 3348 { 3349 if (dev->roce.nb.notifier_call) { 3350 unregister_netdevice_notifier(&dev->roce.nb); 3351 dev->roce.nb.notifier_call = NULL; 3352 } 3353 } 3354 3355 static int mlx5_enable_eth(struct mlx5_ib_dev *dev) 3356 { 3357 int err; 3358 3359 err = mlx5_add_netdev_notifier(dev); 3360 if (err) 3361 return err; 3362 3363 if (MLX5_CAP_GEN(dev->mdev, roce)) { 3364 err = mlx5_nic_vport_enable_roce(dev->mdev); 3365 if (err) 3366 goto err_unregister_netdevice_notifier; 3367 } 3368 3369 err = mlx5_eth_lag_init(dev); 3370 if (err) 3371 goto err_disable_roce; 3372 3373 return 0; 3374 3375 err_disable_roce: 3376 if (MLX5_CAP_GEN(dev->mdev, roce)) 3377 mlx5_nic_vport_disable_roce(dev->mdev); 3378 3379 err_unregister_netdevice_notifier: 3380 mlx5_remove_netdev_notifier(dev); 3381 return err; 3382 } 3383 3384 static void mlx5_disable_eth(struct mlx5_ib_dev *dev) 3385 { 3386 mlx5_eth_lag_cleanup(dev); 3387 if (MLX5_CAP_GEN(dev->mdev, roce)) 3388 mlx5_nic_vport_disable_roce(dev->mdev); 3389 } 3390 3391 struct mlx5_ib_counter { 3392 const char *name; 3393 size_t offset; 3394 }; 3395 3396 #define INIT_Q_COUNTER(_name) \ 3397 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)} 3398 3399 static const struct mlx5_ib_counter basic_q_cnts[] = { 3400 INIT_Q_COUNTER(rx_write_requests), 3401 INIT_Q_COUNTER(rx_read_requests), 3402 INIT_Q_COUNTER(rx_atomic_requests), 3403 INIT_Q_COUNTER(out_of_buffer), 3404 }; 3405 3406 static const struct mlx5_ib_counter out_of_seq_q_cnts[] = { 3407 INIT_Q_COUNTER(out_of_sequence), 3408 }; 3409 3410 static const struct mlx5_ib_counter retrans_q_cnts[] = { 3411 INIT_Q_COUNTER(duplicate_request), 3412 INIT_Q_COUNTER(rnr_nak_retry_err), 3413 INIT_Q_COUNTER(packet_seq_err), 3414 INIT_Q_COUNTER(implied_nak_seq_err), 3415 INIT_Q_COUNTER(local_ack_timeout_err), 3416 }; 3417 3418 #define INIT_CONG_COUNTER(_name) \ 3419 { .name = #_name, .offset = \ 3420 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)} 3421 3422 static const struct mlx5_ib_counter cong_cnts[] = { 3423 INIT_CONG_COUNTER(rp_cnp_ignored), 3424 INIT_CONG_COUNTER(rp_cnp_handled), 3425 INIT_CONG_COUNTER(np_ecn_marked_roce_packets), 3426 INIT_CONG_COUNTER(np_cnp_sent), 3427 }; 3428 3429 static const struct mlx5_ib_counter extended_err_cnts[] = { 3430 INIT_Q_COUNTER(resp_local_length_error), 3431 INIT_Q_COUNTER(resp_cqe_error), 3432 INIT_Q_COUNTER(req_cqe_error), 3433 INIT_Q_COUNTER(req_remote_invalid_request), 3434 INIT_Q_COUNTER(req_remote_access_errors), 3435 INIT_Q_COUNTER(resp_remote_access_errors), 3436 INIT_Q_COUNTER(resp_cqe_flush_error), 3437 INIT_Q_COUNTER(req_cqe_flush_error), 3438 }; 3439 3440 static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev) 3441 { 3442 unsigned int i; 3443 3444 for (i = 0; i < dev->num_ports; i++) { 3445 mlx5_core_dealloc_q_counter(dev->mdev, 3446 dev->port[i].cnts.set_id); 3447 kfree(dev->port[i].cnts.names); 3448 kfree(dev->port[i].cnts.offsets); 3449 } 3450 } 3451 3452 static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev, 3453 struct mlx5_ib_counters *cnts) 3454 { 3455 u32 num_counters; 3456 3457 num_counters = ARRAY_SIZE(basic_q_cnts); 3458 3459 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) 3460 num_counters += ARRAY_SIZE(out_of_seq_q_cnts); 3461 3462 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) 3463 num_counters += ARRAY_SIZE(retrans_q_cnts); 3464 3465 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) 3466 num_counters += ARRAY_SIZE(extended_err_cnts); 3467 3468 cnts->num_q_counters = num_counters; 3469 3470 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 3471 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts); 3472 num_counters += ARRAY_SIZE(cong_cnts); 3473 } 3474 3475 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL); 3476 if (!cnts->names) 3477 return -ENOMEM; 3478 3479 cnts->offsets = kcalloc(num_counters, 3480 sizeof(cnts->offsets), GFP_KERNEL); 3481 if (!cnts->offsets) 3482 goto err_names; 3483 3484 return 0; 3485 3486 err_names: 3487 kfree(cnts->names); 3488 return -ENOMEM; 3489 } 3490 3491 static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev, 3492 const char **names, 3493 size_t *offsets) 3494 { 3495 int i; 3496 int j = 0; 3497 3498 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) { 3499 names[j] = basic_q_cnts[i].name; 3500 offsets[j] = basic_q_cnts[i].offset; 3501 } 3502 3503 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) { 3504 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) { 3505 names[j] = out_of_seq_q_cnts[i].name; 3506 offsets[j] = out_of_seq_q_cnts[i].offset; 3507 } 3508 } 3509 3510 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) { 3511 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) { 3512 names[j] = retrans_q_cnts[i].name; 3513 offsets[j] = retrans_q_cnts[i].offset; 3514 } 3515 } 3516 3517 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) { 3518 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) { 3519 names[j] = extended_err_cnts[i].name; 3520 offsets[j] = extended_err_cnts[i].offset; 3521 } 3522 } 3523 3524 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 3525 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) { 3526 names[j] = cong_cnts[i].name; 3527 offsets[j] = cong_cnts[i].offset; 3528 } 3529 } 3530 } 3531 3532 static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev) 3533 { 3534 int i; 3535 int ret; 3536 3537 for (i = 0; i < dev->num_ports; i++) { 3538 struct mlx5_ib_port *port = &dev->port[i]; 3539 3540 ret = mlx5_core_alloc_q_counter(dev->mdev, 3541 &port->cnts.set_id); 3542 if (ret) { 3543 mlx5_ib_warn(dev, 3544 "couldn't allocate queue counter for port %d, err %d\n", 3545 i + 1, ret); 3546 goto dealloc_counters; 3547 } 3548 3549 ret = __mlx5_ib_alloc_counters(dev, &port->cnts); 3550 if (ret) 3551 goto dealloc_counters; 3552 3553 mlx5_ib_fill_counters(dev, port->cnts.names, 3554 port->cnts.offsets); 3555 } 3556 3557 return 0; 3558 3559 dealloc_counters: 3560 while (--i >= 0) 3561 mlx5_core_dealloc_q_counter(dev->mdev, 3562 dev->port[i].cnts.set_id); 3563 3564 return ret; 3565 } 3566 3567 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev, 3568 u8 port_num) 3569 { 3570 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3571 struct mlx5_ib_port *port = &dev->port[port_num - 1]; 3572 3573 /* We support only per port stats */ 3574 if (port_num == 0) 3575 return NULL; 3576 3577 return rdma_alloc_hw_stats_struct(port->cnts.names, 3578 port->cnts.num_q_counters + 3579 port->cnts.num_cong_counters, 3580 RDMA_HW_STATS_DEFAULT_LIFESPAN); 3581 } 3582 3583 static int mlx5_ib_query_q_counters(struct mlx5_ib_dev *dev, 3584 struct mlx5_ib_port *port, 3585 struct rdma_hw_stats *stats) 3586 { 3587 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out); 3588 void *out; 3589 __be32 val; 3590 int ret, i; 3591 3592 out = kvzalloc(outlen, GFP_KERNEL); 3593 if (!out) 3594 return -ENOMEM; 3595 3596 ret = mlx5_core_query_q_counter(dev->mdev, 3597 port->cnts.set_id, 0, 3598 out, outlen); 3599 if (ret) 3600 goto free; 3601 3602 for (i = 0; i < port->cnts.num_q_counters; i++) { 3603 val = *(__be32 *)(out + port->cnts.offsets[i]); 3604 stats->value[i] = (u64)be32_to_cpu(val); 3605 } 3606 3607 free: 3608 kvfree(out); 3609 return ret; 3610 } 3611 3612 static int mlx5_ib_query_cong_counters(struct mlx5_ib_dev *dev, 3613 struct mlx5_ib_port *port, 3614 struct rdma_hw_stats *stats) 3615 { 3616 int outlen = MLX5_ST_SZ_BYTES(query_cong_statistics_out); 3617 void *out; 3618 int ret, i; 3619 int offset = port->cnts.num_q_counters; 3620 3621 out = kvzalloc(outlen, GFP_KERNEL); 3622 if (!out) 3623 return -ENOMEM; 3624 3625 ret = mlx5_cmd_query_cong_counter(dev->mdev, false, out, outlen); 3626 if (ret) 3627 goto free; 3628 3629 for (i = 0; i < port->cnts.num_cong_counters; i++) { 3630 stats->value[i + offset] = 3631 be64_to_cpup((__be64 *)(out + 3632 port->cnts.offsets[i + offset])); 3633 } 3634 3635 free: 3636 kvfree(out); 3637 return ret; 3638 } 3639 3640 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev, 3641 struct rdma_hw_stats *stats, 3642 u8 port_num, int index) 3643 { 3644 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3645 struct mlx5_ib_port *port = &dev->port[port_num - 1]; 3646 int ret, num_counters; 3647 3648 if (!stats) 3649 return -EINVAL; 3650 3651 ret = mlx5_ib_query_q_counters(dev, port, stats); 3652 if (ret) 3653 return ret; 3654 num_counters = port->cnts.num_q_counters; 3655 3656 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 3657 ret = mlx5_ib_query_cong_counters(dev, port, stats); 3658 if (ret) 3659 return ret; 3660 num_counters += port->cnts.num_cong_counters; 3661 } 3662 3663 return num_counters; 3664 } 3665 3666 static void mlx5_ib_free_rdma_netdev(struct net_device *netdev) 3667 { 3668 return mlx5_rdma_netdev_free(netdev); 3669 } 3670 3671 static struct net_device* 3672 mlx5_ib_alloc_rdma_netdev(struct ib_device *hca, 3673 u8 port_num, 3674 enum rdma_netdev_t type, 3675 const char *name, 3676 unsigned char name_assign_type, 3677 void (*setup)(struct net_device *)) 3678 { 3679 struct net_device *netdev; 3680 struct rdma_netdev *rn; 3681 3682 if (type != RDMA_NETDEV_IPOIB) 3683 return ERR_PTR(-EOPNOTSUPP); 3684 3685 netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca, 3686 name, setup); 3687 if (likely(!IS_ERR_OR_NULL(netdev))) { 3688 rn = netdev_priv(netdev); 3689 rn->free_rdma_netdev = mlx5_ib_free_rdma_netdev; 3690 } 3691 return netdev; 3692 } 3693 3694 static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev) 3695 { 3696 if (!dev->delay_drop.dbg) 3697 return; 3698 debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs); 3699 kfree(dev->delay_drop.dbg); 3700 dev->delay_drop.dbg = NULL; 3701 } 3702 3703 static void cancel_delay_drop(struct mlx5_ib_dev *dev) 3704 { 3705 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 3706 return; 3707 3708 cancel_work_sync(&dev->delay_drop.delay_drop_work); 3709 delay_drop_debugfs_cleanup(dev); 3710 } 3711 3712 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf, 3713 size_t count, loff_t *pos) 3714 { 3715 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3716 char lbuf[20]; 3717 int len; 3718 3719 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout); 3720 return simple_read_from_buffer(buf, count, pos, lbuf, len); 3721 } 3722 3723 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf, 3724 size_t count, loff_t *pos) 3725 { 3726 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3727 u32 timeout; 3728 u32 var; 3729 3730 if (kstrtouint_from_user(buf, count, 0, &var)) 3731 return -EFAULT; 3732 3733 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 3734 1000); 3735 if (timeout != var) 3736 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n", 3737 timeout); 3738 3739 delay_drop->timeout = timeout; 3740 3741 return count; 3742 } 3743 3744 static const struct file_operations fops_delay_drop_timeout = { 3745 .owner = THIS_MODULE, 3746 .open = simple_open, 3747 .write = delay_drop_timeout_write, 3748 .read = delay_drop_timeout_read, 3749 }; 3750 3751 static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev) 3752 { 3753 struct mlx5_ib_dbg_delay_drop *dbg; 3754 3755 if (!mlx5_debugfs_root) 3756 return 0; 3757 3758 dbg = kzalloc(sizeof(*dbg), GFP_KERNEL); 3759 if (!dbg) 3760 return -ENOMEM; 3761 3762 dbg->dir_debugfs = 3763 debugfs_create_dir("delay_drop", 3764 dev->mdev->priv.dbg_root); 3765 if (!dbg->dir_debugfs) 3766 return -ENOMEM; 3767 3768 dbg->events_cnt_debugfs = 3769 debugfs_create_atomic_t("num_timeout_events", 0400, 3770 dbg->dir_debugfs, 3771 &dev->delay_drop.events_cnt); 3772 if (!dbg->events_cnt_debugfs) 3773 goto out_debugfs; 3774 3775 dbg->rqs_cnt_debugfs = 3776 debugfs_create_atomic_t("num_rqs", 0400, 3777 dbg->dir_debugfs, 3778 &dev->delay_drop.rqs_cnt); 3779 if (!dbg->rqs_cnt_debugfs) 3780 goto out_debugfs; 3781 3782 dbg->timeout_debugfs = 3783 debugfs_create_file("timeout", 0600, 3784 dbg->dir_debugfs, 3785 &dev->delay_drop, 3786 &fops_delay_drop_timeout); 3787 if (!dbg->timeout_debugfs) 3788 goto out_debugfs; 3789 3790 return 0; 3791 3792 out_debugfs: 3793 delay_drop_debugfs_cleanup(dev); 3794 return -ENOMEM; 3795 } 3796 3797 static void init_delay_drop(struct mlx5_ib_dev *dev) 3798 { 3799 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 3800 return; 3801 3802 mutex_init(&dev->delay_drop.lock); 3803 dev->delay_drop.dev = dev; 3804 dev->delay_drop.activate = false; 3805 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000; 3806 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler); 3807 atomic_set(&dev->delay_drop.rqs_cnt, 0); 3808 atomic_set(&dev->delay_drop.events_cnt, 0); 3809 3810 if (delay_drop_debugfs_init(dev)) 3811 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n"); 3812 } 3813 3814 const struct cpumask *mlx5_ib_get_vector_affinity(struct ib_device *ibdev, 3815 int comp_vector) 3816 { 3817 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3818 3819 return mlx5_get_vector_affinity(dev->mdev, comp_vector); 3820 } 3821 3822 static void *mlx5_ib_add(struct mlx5_core_dev *mdev) 3823 { 3824 struct mlx5_ib_dev *dev; 3825 enum rdma_link_layer ll; 3826 int port_type_cap; 3827 const char *name; 3828 int err; 3829 int i; 3830 3831 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 3832 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 3833 3834 printk_once(KERN_INFO "%s", mlx5_version); 3835 3836 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev)); 3837 if (!dev) 3838 return NULL; 3839 3840 dev->mdev = mdev; 3841 3842 dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port), 3843 GFP_KERNEL); 3844 if (!dev->port) 3845 goto err_dealloc; 3846 3847 rwlock_init(&dev->roce.netdev_lock); 3848 err = get_port_caps(dev); 3849 if (err) 3850 goto err_free_port; 3851 3852 if (mlx5_use_mad_ifc(dev)) 3853 get_ext_port_caps(dev); 3854 3855 if (!mlx5_lag_is_active(mdev)) 3856 name = "mlx5_%d"; 3857 else 3858 name = "mlx5_bond_%d"; 3859 3860 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX); 3861 dev->ib_dev.owner = THIS_MODULE; 3862 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 3863 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 3864 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports); 3865 dev->ib_dev.phys_port_cnt = dev->num_ports; 3866 dev->ib_dev.num_comp_vectors = 3867 dev->mdev->priv.eq_table.num_comp_vectors; 3868 dev->ib_dev.dev.parent = &mdev->pdev->dev; 3869 3870 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION; 3871 dev->ib_dev.uverbs_cmd_mask = 3872 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | 3873 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | 3874 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | 3875 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | 3876 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | 3877 (1ull << IB_USER_VERBS_CMD_CREATE_AH) | 3878 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) | 3879 (1ull << IB_USER_VERBS_CMD_REG_MR) | 3880 (1ull << IB_USER_VERBS_CMD_REREG_MR) | 3881 (1ull << IB_USER_VERBS_CMD_DEREG_MR) | 3882 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 3883 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | 3884 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) | 3885 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | 3886 (1ull << IB_USER_VERBS_CMD_CREATE_QP) | 3887 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | 3888 (1ull << IB_USER_VERBS_CMD_QUERY_QP) | 3889 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | 3890 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) | 3891 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) | 3892 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | 3893 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | 3894 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | 3895 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | 3896 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) | 3897 (1ull << IB_USER_VERBS_CMD_OPEN_QP); 3898 dev->ib_dev.uverbs_ex_cmd_mask = 3899 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) | 3900 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) | 3901 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) | 3902 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP); 3903 3904 dev->ib_dev.query_device = mlx5_ib_query_device; 3905 dev->ib_dev.query_port = mlx5_ib_query_port; 3906 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer; 3907 if (ll == IB_LINK_LAYER_ETHERNET) 3908 dev->ib_dev.get_netdev = mlx5_ib_get_netdev; 3909 dev->ib_dev.query_gid = mlx5_ib_query_gid; 3910 dev->ib_dev.add_gid = mlx5_ib_add_gid; 3911 dev->ib_dev.del_gid = mlx5_ib_del_gid; 3912 dev->ib_dev.query_pkey = mlx5_ib_query_pkey; 3913 dev->ib_dev.modify_device = mlx5_ib_modify_device; 3914 dev->ib_dev.modify_port = mlx5_ib_modify_port; 3915 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext; 3916 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext; 3917 dev->ib_dev.mmap = mlx5_ib_mmap; 3918 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd; 3919 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd; 3920 dev->ib_dev.create_ah = mlx5_ib_create_ah; 3921 dev->ib_dev.query_ah = mlx5_ib_query_ah; 3922 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah; 3923 dev->ib_dev.create_srq = mlx5_ib_create_srq; 3924 dev->ib_dev.modify_srq = mlx5_ib_modify_srq; 3925 dev->ib_dev.query_srq = mlx5_ib_query_srq; 3926 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq; 3927 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv; 3928 dev->ib_dev.create_qp = mlx5_ib_create_qp; 3929 dev->ib_dev.modify_qp = mlx5_ib_modify_qp; 3930 dev->ib_dev.query_qp = mlx5_ib_query_qp; 3931 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp; 3932 dev->ib_dev.post_send = mlx5_ib_post_send; 3933 dev->ib_dev.post_recv = mlx5_ib_post_recv; 3934 dev->ib_dev.create_cq = mlx5_ib_create_cq; 3935 dev->ib_dev.modify_cq = mlx5_ib_modify_cq; 3936 dev->ib_dev.resize_cq = mlx5_ib_resize_cq; 3937 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq; 3938 dev->ib_dev.poll_cq = mlx5_ib_poll_cq; 3939 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq; 3940 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr; 3941 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr; 3942 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr; 3943 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr; 3944 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach; 3945 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach; 3946 dev->ib_dev.process_mad = mlx5_ib_process_mad; 3947 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr; 3948 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg; 3949 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status; 3950 dev->ib_dev.get_port_immutable = mlx5_port_immutable; 3951 dev->ib_dev.get_dev_fw_str = get_dev_fw_str; 3952 dev->ib_dev.get_vector_affinity = mlx5_ib_get_vector_affinity; 3953 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads)) 3954 dev->ib_dev.alloc_rdma_netdev = mlx5_ib_alloc_rdma_netdev; 3955 3956 if (mlx5_core_is_pf(mdev)) { 3957 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config; 3958 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state; 3959 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats; 3960 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid; 3961 } 3962 3963 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext; 3964 3965 mlx5_ib_internal_fill_odp_caps(dev); 3966 3967 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence)); 3968 3969 if (MLX5_CAP_GEN(mdev, imaicl)) { 3970 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw; 3971 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw; 3972 dev->ib_dev.uverbs_cmd_mask |= 3973 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) | 3974 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW); 3975 } 3976 3977 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) { 3978 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats; 3979 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats; 3980 } 3981 3982 if (MLX5_CAP_GEN(mdev, xrc)) { 3983 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd; 3984 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd; 3985 dev->ib_dev.uverbs_cmd_mask |= 3986 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) | 3987 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD); 3988 } 3989 3990 dev->ib_dev.create_flow = mlx5_ib_create_flow; 3991 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow; 3992 dev->ib_dev.uverbs_ex_cmd_mask |= 3993 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) | 3994 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW); 3995 3996 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) == 3997 IB_LINK_LAYER_ETHERNET) { 3998 dev->ib_dev.create_wq = mlx5_ib_create_wq; 3999 dev->ib_dev.modify_wq = mlx5_ib_modify_wq; 4000 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq; 4001 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table; 4002 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table; 4003 dev->ib_dev.uverbs_ex_cmd_mask |= 4004 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) | 4005 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) | 4006 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) | 4007 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) | 4008 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL); 4009 } 4010 err = init_node_data(dev); 4011 if (err) 4012 goto err_free_port; 4013 4014 mutex_init(&dev->flow_db.lock); 4015 mutex_init(&dev->cap_mask_mutex); 4016 INIT_LIST_HEAD(&dev->qp_list); 4017 spin_lock_init(&dev->reset_flow_resource_lock); 4018 4019 if (ll == IB_LINK_LAYER_ETHERNET) { 4020 err = mlx5_enable_eth(dev); 4021 if (err) 4022 goto err_free_port; 4023 dev->roce.last_port_state = IB_PORT_DOWN; 4024 } 4025 4026 err = create_dev_resources(&dev->devr); 4027 if (err) 4028 goto err_disable_eth; 4029 4030 err = mlx5_ib_odp_init_one(dev); 4031 if (err) 4032 goto err_rsrc; 4033 4034 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) { 4035 err = mlx5_ib_alloc_counters(dev); 4036 if (err) 4037 goto err_odp; 4038 } 4039 4040 err = mlx5_ib_init_cong_debugfs(dev); 4041 if (err) 4042 goto err_cnt; 4043 4044 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev); 4045 if (!dev->mdev->priv.uar) 4046 goto err_cong; 4047 4048 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false); 4049 if (err) 4050 goto err_uar_page; 4051 4052 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true); 4053 if (err) 4054 goto err_bfreg; 4055 4056 err = ib_register_device(&dev->ib_dev, NULL); 4057 if (err) 4058 goto err_fp_bfreg; 4059 4060 err = create_umr_res(dev); 4061 if (err) 4062 goto err_dev; 4063 4064 init_delay_drop(dev); 4065 4066 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) { 4067 err = device_create_file(&dev->ib_dev.dev, 4068 mlx5_class_attributes[i]); 4069 if (err) 4070 goto err_delay_drop; 4071 } 4072 4073 if ((MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && 4074 MLX5_CAP_GEN(mdev, disable_local_lb)) 4075 mutex_init(&dev->lb_mutex); 4076 4077 dev->ib_active = true; 4078 4079 return dev; 4080 4081 err_delay_drop: 4082 cancel_delay_drop(dev); 4083 destroy_umrc_res(dev); 4084 4085 err_dev: 4086 ib_unregister_device(&dev->ib_dev); 4087 4088 err_fp_bfreg: 4089 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 4090 4091 err_bfreg: 4092 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4093 4094 err_uar_page: 4095 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar); 4096 4097 err_cnt: 4098 mlx5_ib_cleanup_cong_debugfs(dev); 4099 err_cong: 4100 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) 4101 mlx5_ib_dealloc_counters(dev); 4102 4103 err_odp: 4104 mlx5_ib_odp_remove_one(dev); 4105 4106 err_rsrc: 4107 destroy_dev_resources(&dev->devr); 4108 4109 err_disable_eth: 4110 if (ll == IB_LINK_LAYER_ETHERNET) { 4111 mlx5_disable_eth(dev); 4112 mlx5_remove_netdev_notifier(dev); 4113 } 4114 4115 err_free_port: 4116 kfree(dev->port); 4117 4118 err_dealloc: 4119 ib_dealloc_device((struct ib_device *)dev); 4120 4121 return NULL; 4122 } 4123 4124 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context) 4125 { 4126 struct mlx5_ib_dev *dev = context; 4127 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1); 4128 4129 cancel_delay_drop(dev); 4130 mlx5_remove_netdev_notifier(dev); 4131 ib_unregister_device(&dev->ib_dev); 4132 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 4133 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4134 mlx5_put_uars_page(dev->mdev, mdev->priv.uar); 4135 mlx5_ib_cleanup_cong_debugfs(dev); 4136 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) 4137 mlx5_ib_dealloc_counters(dev); 4138 destroy_umrc_res(dev); 4139 mlx5_ib_odp_remove_one(dev); 4140 destroy_dev_resources(&dev->devr); 4141 if (ll == IB_LINK_LAYER_ETHERNET) 4142 mlx5_disable_eth(dev); 4143 kfree(dev->port); 4144 ib_dealloc_device(&dev->ib_dev); 4145 } 4146 4147 static struct mlx5_interface mlx5_ib_interface = { 4148 .add = mlx5_ib_add, 4149 .remove = mlx5_ib_remove, 4150 .event = mlx5_ib_event, 4151 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 4152 .pfault = mlx5_ib_pfault, 4153 #endif 4154 .protocol = MLX5_INTERFACE_PROTOCOL_IB, 4155 }; 4156 4157 static int __init mlx5_ib_init(void) 4158 { 4159 int err; 4160 4161 mlx5_ib_odp_init(); 4162 4163 err = mlx5_register_interface(&mlx5_ib_interface); 4164 4165 return err; 4166 } 4167 4168 static void __exit mlx5_ib_cleanup(void) 4169 { 4170 mlx5_unregister_interface(&mlx5_ib_interface); 4171 } 4172 4173 module_init(mlx5_ib_init); 4174 module_exit(mlx5_ib_cleanup); 4175