1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/debugfs.h> 34 #include <linux/highmem.h> 35 #include <linux/module.h> 36 #include <linux/init.h> 37 #include <linux/errno.h> 38 #include <linux/pci.h> 39 #include <linux/dma-mapping.h> 40 #include <linux/slab.h> 41 #if defined(CONFIG_X86) 42 #include <asm/pat.h> 43 #endif 44 #include <linux/sched.h> 45 #include <linux/sched/mm.h> 46 #include <linux/sched/task.h> 47 #include <linux/delay.h> 48 #include <rdma/ib_user_verbs.h> 49 #include <rdma/ib_addr.h> 50 #include <rdma/ib_cache.h> 51 #include <linux/mlx5/port.h> 52 #include <linux/mlx5/vport.h> 53 #include <linux/list.h> 54 #include <rdma/ib_smi.h> 55 #include <rdma/ib_umem.h> 56 #include <linux/in.h> 57 #include <linux/etherdevice.h> 58 #include <linux/mlx5/fs.h> 59 #include <linux/mlx5/vport.h> 60 #include "mlx5_ib.h" 61 #include "cmd.h" 62 #include <linux/mlx5/vport.h> 63 64 #define DRIVER_NAME "mlx5_ib" 65 #define DRIVER_VERSION "5.0-0" 66 67 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 68 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver"); 69 MODULE_LICENSE("Dual BSD/GPL"); 70 71 static char mlx5_version[] = 72 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v" 73 DRIVER_VERSION "\n"; 74 75 enum { 76 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 77 }; 78 79 static enum rdma_link_layer 80 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 81 { 82 switch (port_type_cap) { 83 case MLX5_CAP_PORT_TYPE_IB: 84 return IB_LINK_LAYER_INFINIBAND; 85 case MLX5_CAP_PORT_TYPE_ETH: 86 return IB_LINK_LAYER_ETHERNET; 87 default: 88 return IB_LINK_LAYER_UNSPECIFIED; 89 } 90 } 91 92 static enum rdma_link_layer 93 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num) 94 { 95 struct mlx5_ib_dev *dev = to_mdev(device); 96 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 97 98 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 99 } 100 101 static int get_port_state(struct ib_device *ibdev, 102 u8 port_num, 103 enum ib_port_state *state) 104 { 105 struct ib_port_attr attr; 106 int ret; 107 108 memset(&attr, 0, sizeof(attr)); 109 ret = mlx5_ib_query_port(ibdev, port_num, &attr); 110 if (!ret) 111 *state = attr.state; 112 return ret; 113 } 114 115 static int mlx5_netdev_event(struct notifier_block *this, 116 unsigned long event, void *ptr) 117 { 118 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 119 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev, 120 roce.nb); 121 122 switch (event) { 123 case NETDEV_REGISTER: 124 case NETDEV_UNREGISTER: 125 write_lock(&ibdev->roce.netdev_lock); 126 if (ndev->dev.parent == &ibdev->mdev->pdev->dev) 127 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ? 128 NULL : ndev; 129 write_unlock(&ibdev->roce.netdev_lock); 130 break; 131 132 case NETDEV_CHANGE: 133 case NETDEV_UP: 134 case NETDEV_DOWN: { 135 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(ibdev->mdev); 136 struct net_device *upper = NULL; 137 138 if (lag_ndev) { 139 upper = netdev_master_upper_dev_get(lag_ndev); 140 dev_put(lag_ndev); 141 } 142 143 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev)) 144 && ibdev->ib_active) { 145 struct ib_event ibev = { }; 146 enum ib_port_state port_state; 147 148 if (get_port_state(&ibdev->ib_dev, 1, &port_state)) 149 return NOTIFY_DONE; 150 151 if (ibdev->roce.last_port_state == port_state) 152 return NOTIFY_DONE; 153 154 ibdev->roce.last_port_state = port_state; 155 ibev.device = &ibdev->ib_dev; 156 if (port_state == IB_PORT_DOWN) 157 ibev.event = IB_EVENT_PORT_ERR; 158 else if (port_state == IB_PORT_ACTIVE) 159 ibev.event = IB_EVENT_PORT_ACTIVE; 160 else 161 return NOTIFY_DONE; 162 163 ibev.element.port_num = 1; 164 ib_dispatch_event(&ibev); 165 } 166 break; 167 } 168 169 default: 170 break; 171 } 172 173 return NOTIFY_DONE; 174 } 175 176 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device, 177 u8 port_num) 178 { 179 struct mlx5_ib_dev *ibdev = to_mdev(device); 180 struct net_device *ndev; 181 182 ndev = mlx5_lag_get_roce_netdev(ibdev->mdev); 183 if (ndev) 184 return ndev; 185 186 /* Ensure ndev does not disappear before we invoke dev_hold() 187 */ 188 read_lock(&ibdev->roce.netdev_lock); 189 ndev = ibdev->roce.netdev; 190 if (ndev) 191 dev_hold(ndev); 192 read_unlock(&ibdev->roce.netdev_lock); 193 194 return ndev; 195 } 196 197 static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed, 198 u8 *active_width) 199 { 200 switch (eth_proto_oper) { 201 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII): 202 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX): 203 case MLX5E_PROT_MASK(MLX5E_100BASE_TX): 204 case MLX5E_PROT_MASK(MLX5E_1000BASE_T): 205 *active_width = IB_WIDTH_1X; 206 *active_speed = IB_SPEED_SDR; 207 break; 208 case MLX5E_PROT_MASK(MLX5E_10GBASE_T): 209 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4): 210 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4): 211 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR): 212 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR): 213 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR): 214 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER): 215 *active_width = IB_WIDTH_1X; 216 *active_speed = IB_SPEED_QDR; 217 break; 218 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR): 219 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR): 220 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR): 221 *active_width = IB_WIDTH_1X; 222 *active_speed = IB_SPEED_EDR; 223 break; 224 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4): 225 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4): 226 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4): 227 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4): 228 *active_width = IB_WIDTH_4X; 229 *active_speed = IB_SPEED_QDR; 230 break; 231 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2): 232 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2): 233 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2): 234 *active_width = IB_WIDTH_1X; 235 *active_speed = IB_SPEED_HDR; 236 break; 237 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4): 238 *active_width = IB_WIDTH_4X; 239 *active_speed = IB_SPEED_FDR; 240 break; 241 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4): 242 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4): 243 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4): 244 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4): 245 *active_width = IB_WIDTH_4X; 246 *active_speed = IB_SPEED_EDR; 247 break; 248 default: 249 return -EINVAL; 250 } 251 252 return 0; 253 } 254 255 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num, 256 struct ib_port_attr *props) 257 { 258 struct mlx5_ib_dev *dev = to_mdev(device); 259 struct mlx5_core_dev *mdev = dev->mdev; 260 struct net_device *ndev, *upper; 261 enum ib_mtu ndev_ib_mtu; 262 u16 qkey_viol_cntr; 263 u32 eth_prot_oper; 264 int err; 265 266 /* Possible bad flows are checked before filling out props so in case 267 * of an error it will still be zeroed out. 268 */ 269 err = mlx5_query_port_eth_proto_oper(mdev, ð_prot_oper, port_num); 270 if (err) 271 return err; 272 273 translate_eth_proto_oper(eth_prot_oper, &props->active_speed, 274 &props->active_width); 275 276 props->port_cap_flags |= IB_PORT_CM_SUP; 277 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS; 278 279 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 280 roce_address_table_size); 281 props->max_mtu = IB_MTU_4096; 282 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 283 props->pkey_tbl_len = 1; 284 props->state = IB_PORT_DOWN; 285 props->phys_state = 3; 286 287 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr); 288 props->qkey_viol_cntr = qkey_viol_cntr; 289 290 ndev = mlx5_ib_get_netdev(device, port_num); 291 if (!ndev) 292 return 0; 293 294 if (mlx5_lag_is_active(dev->mdev)) { 295 rcu_read_lock(); 296 upper = netdev_master_upper_dev_get_rcu(ndev); 297 if (upper) { 298 dev_put(ndev); 299 ndev = upper; 300 dev_hold(ndev); 301 } 302 rcu_read_unlock(); 303 } 304 305 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 306 props->state = IB_PORT_ACTIVE; 307 props->phys_state = 5; 308 } 309 310 ndev_ib_mtu = iboe_get_mtu(ndev->mtu); 311 312 dev_put(ndev); 313 314 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 315 return 0; 316 } 317 318 static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num, 319 unsigned int index, const union ib_gid *gid, 320 const struct ib_gid_attr *attr) 321 { 322 enum ib_gid_type gid_type = IB_GID_TYPE_IB; 323 u8 roce_version = 0; 324 u8 roce_l3_type = 0; 325 bool vlan = false; 326 u8 mac[ETH_ALEN]; 327 u16 vlan_id = 0; 328 329 if (gid) { 330 gid_type = attr->gid_type; 331 ether_addr_copy(mac, attr->ndev->dev_addr); 332 333 if (is_vlan_dev(attr->ndev)) { 334 vlan = true; 335 vlan_id = vlan_dev_vlan_id(attr->ndev); 336 } 337 } 338 339 switch (gid_type) { 340 case IB_GID_TYPE_IB: 341 roce_version = MLX5_ROCE_VERSION_1; 342 break; 343 case IB_GID_TYPE_ROCE_UDP_ENCAP: 344 roce_version = MLX5_ROCE_VERSION_2; 345 if (ipv6_addr_v4mapped((void *)gid)) 346 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4; 347 else 348 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6; 349 break; 350 351 default: 352 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type); 353 } 354 355 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version, 356 roce_l3_type, gid->raw, mac, vlan, 357 vlan_id); 358 } 359 360 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num, 361 unsigned int index, const union ib_gid *gid, 362 const struct ib_gid_attr *attr, 363 __always_unused void **context) 364 { 365 return set_roce_addr(to_mdev(device), port_num, index, gid, attr); 366 } 367 368 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num, 369 unsigned int index, __always_unused void **context) 370 { 371 return set_roce_addr(to_mdev(device), port_num, index, NULL, NULL); 372 } 373 374 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num, 375 int index) 376 { 377 struct ib_gid_attr attr; 378 union ib_gid gid; 379 380 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr)) 381 return 0; 382 383 if (!attr.ndev) 384 return 0; 385 386 dev_put(attr.ndev); 387 388 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 389 return 0; 390 391 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 392 } 393 394 int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num, 395 int index, enum ib_gid_type *gid_type) 396 { 397 struct ib_gid_attr attr; 398 union ib_gid gid; 399 int ret; 400 401 ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr); 402 if (ret) 403 return ret; 404 405 if (!attr.ndev) 406 return -ENODEV; 407 408 dev_put(attr.ndev); 409 410 *gid_type = attr.gid_type; 411 412 return 0; 413 } 414 415 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 416 { 417 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 418 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 419 return 0; 420 } 421 422 enum { 423 MLX5_VPORT_ACCESS_METHOD_MAD, 424 MLX5_VPORT_ACCESS_METHOD_HCA, 425 MLX5_VPORT_ACCESS_METHOD_NIC, 426 }; 427 428 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 429 { 430 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 431 return MLX5_VPORT_ACCESS_METHOD_MAD; 432 433 if (mlx5_ib_port_link_layer(ibdev, 1) == 434 IB_LINK_LAYER_ETHERNET) 435 return MLX5_VPORT_ACCESS_METHOD_NIC; 436 437 return MLX5_VPORT_ACCESS_METHOD_HCA; 438 } 439 440 static void get_atomic_caps(struct mlx5_ib_dev *dev, 441 struct ib_device_attr *props) 442 { 443 u8 tmp; 444 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 445 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 446 u8 atomic_req_8B_endianness_mode = 447 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode); 448 449 /* Check if HW supports 8 bytes standard atomic operations and capable 450 * of host endianness respond 451 */ 452 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 453 if (((atomic_operations & tmp) == tmp) && 454 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 455 (atomic_req_8B_endianness_mode)) { 456 props->atomic_cap = IB_ATOMIC_HCA; 457 } else { 458 props->atomic_cap = IB_ATOMIC_NONE; 459 } 460 } 461 462 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 463 __be64 *sys_image_guid) 464 { 465 struct mlx5_ib_dev *dev = to_mdev(ibdev); 466 struct mlx5_core_dev *mdev = dev->mdev; 467 u64 tmp; 468 int err; 469 470 switch (mlx5_get_vport_access_method(ibdev)) { 471 case MLX5_VPORT_ACCESS_METHOD_MAD: 472 return mlx5_query_mad_ifc_system_image_guid(ibdev, 473 sys_image_guid); 474 475 case MLX5_VPORT_ACCESS_METHOD_HCA: 476 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 477 break; 478 479 case MLX5_VPORT_ACCESS_METHOD_NIC: 480 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 481 break; 482 483 default: 484 return -EINVAL; 485 } 486 487 if (!err) 488 *sys_image_guid = cpu_to_be64(tmp); 489 490 return err; 491 492 } 493 494 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 495 u16 *max_pkeys) 496 { 497 struct mlx5_ib_dev *dev = to_mdev(ibdev); 498 struct mlx5_core_dev *mdev = dev->mdev; 499 500 switch (mlx5_get_vport_access_method(ibdev)) { 501 case MLX5_VPORT_ACCESS_METHOD_MAD: 502 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 503 504 case MLX5_VPORT_ACCESS_METHOD_HCA: 505 case MLX5_VPORT_ACCESS_METHOD_NIC: 506 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 507 pkey_table_size)); 508 return 0; 509 510 default: 511 return -EINVAL; 512 } 513 } 514 515 static int mlx5_query_vendor_id(struct ib_device *ibdev, 516 u32 *vendor_id) 517 { 518 struct mlx5_ib_dev *dev = to_mdev(ibdev); 519 520 switch (mlx5_get_vport_access_method(ibdev)) { 521 case MLX5_VPORT_ACCESS_METHOD_MAD: 522 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 523 524 case MLX5_VPORT_ACCESS_METHOD_HCA: 525 case MLX5_VPORT_ACCESS_METHOD_NIC: 526 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 527 528 default: 529 return -EINVAL; 530 } 531 } 532 533 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 534 __be64 *node_guid) 535 { 536 u64 tmp; 537 int err; 538 539 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 540 case MLX5_VPORT_ACCESS_METHOD_MAD: 541 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 542 543 case MLX5_VPORT_ACCESS_METHOD_HCA: 544 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 545 break; 546 547 case MLX5_VPORT_ACCESS_METHOD_NIC: 548 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 549 break; 550 551 default: 552 return -EINVAL; 553 } 554 555 if (!err) 556 *node_guid = cpu_to_be64(tmp); 557 558 return err; 559 } 560 561 struct mlx5_reg_node_desc { 562 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 563 }; 564 565 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 566 { 567 struct mlx5_reg_node_desc in; 568 569 if (mlx5_use_mad_ifc(dev)) 570 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 571 572 memset(&in, 0, sizeof(in)); 573 574 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 575 sizeof(struct mlx5_reg_node_desc), 576 MLX5_REG_NODE_DESC, 0, 0); 577 } 578 579 static int mlx5_ib_query_device(struct ib_device *ibdev, 580 struct ib_device_attr *props, 581 struct ib_udata *uhw) 582 { 583 struct mlx5_ib_dev *dev = to_mdev(ibdev); 584 struct mlx5_core_dev *mdev = dev->mdev; 585 int err = -ENOMEM; 586 int max_sq_desc; 587 int max_rq_sg; 588 int max_sq_sg; 589 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 590 struct mlx5_ib_query_device_resp resp = {}; 591 size_t resp_len; 592 u64 max_tso; 593 594 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 595 if (uhw->outlen && uhw->outlen < resp_len) 596 return -EINVAL; 597 else 598 resp.response_length = resp_len; 599 600 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) 601 return -EINVAL; 602 603 memset(props, 0, sizeof(*props)); 604 err = mlx5_query_system_image_guid(ibdev, 605 &props->sys_image_guid); 606 if (err) 607 return err; 608 609 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys); 610 if (err) 611 return err; 612 613 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 614 if (err) 615 return err; 616 617 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 618 (fw_rev_min(dev->mdev) << 16) | 619 fw_rev_sub(dev->mdev); 620 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 621 IB_DEVICE_PORT_ACTIVE_EVENT | 622 IB_DEVICE_SYS_IMAGE_GUID | 623 IB_DEVICE_RC_RNR_NAK_GEN; 624 625 if (MLX5_CAP_GEN(mdev, pkv)) 626 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 627 if (MLX5_CAP_GEN(mdev, qkv)) 628 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 629 if (MLX5_CAP_GEN(mdev, apm)) 630 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 631 if (MLX5_CAP_GEN(mdev, xrc)) 632 props->device_cap_flags |= IB_DEVICE_XRC; 633 if (MLX5_CAP_GEN(mdev, imaicl)) { 634 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 635 IB_DEVICE_MEM_WINDOW_TYPE_2B; 636 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 637 /* We support 'Gappy' memory registration too */ 638 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG; 639 } 640 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 641 if (MLX5_CAP_GEN(mdev, sho)) { 642 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER; 643 /* At this stage no support for signature handover */ 644 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 645 IB_PROT_T10DIF_TYPE_2 | 646 IB_PROT_T10DIF_TYPE_3; 647 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 648 IB_GUARD_T10DIF_CSUM; 649 } 650 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 651 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 652 653 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) { 654 if (MLX5_CAP_ETH(mdev, csum_cap)) { 655 /* Legacy bit to support old userspace libraries */ 656 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 657 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM; 658 } 659 660 if (MLX5_CAP_ETH(dev->mdev, vlan_cap)) 661 props->raw_packet_caps |= 662 IB_RAW_PACKET_CAP_CVLAN_STRIPPING; 663 664 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) { 665 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 666 if (max_tso) { 667 resp.tso_caps.max_tso = 1 << max_tso; 668 resp.tso_caps.supported_qpts |= 669 1 << IB_QPT_RAW_PACKET; 670 resp.response_length += sizeof(resp.tso_caps); 671 } 672 } 673 674 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) { 675 resp.rss_caps.rx_hash_function = 676 MLX5_RX_HASH_FUNC_TOEPLITZ; 677 resp.rss_caps.rx_hash_fields_mask = 678 MLX5_RX_HASH_SRC_IPV4 | 679 MLX5_RX_HASH_DST_IPV4 | 680 MLX5_RX_HASH_SRC_IPV6 | 681 MLX5_RX_HASH_DST_IPV6 | 682 MLX5_RX_HASH_SRC_PORT_TCP | 683 MLX5_RX_HASH_DST_PORT_TCP | 684 MLX5_RX_HASH_SRC_PORT_UDP | 685 MLX5_RX_HASH_DST_PORT_UDP; 686 resp.response_length += sizeof(resp.rss_caps); 687 } 688 } else { 689 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) 690 resp.response_length += sizeof(resp.tso_caps); 691 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) 692 resp.response_length += sizeof(resp.rss_caps); 693 } 694 695 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 696 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 697 props->device_cap_flags |= IB_DEVICE_UD_TSO; 698 } 699 700 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) && 701 MLX5_CAP_GEN(dev->mdev, general_notification_event)) 702 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP; 703 704 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 705 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap)) 706 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 707 708 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 709 MLX5_CAP_ETH(dev->mdev, scatter_fcs)) { 710 /* Legacy bit to support old userspace libraries */ 711 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 712 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; 713 } 714 715 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 716 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 717 718 if (MLX5_CAP_GEN(mdev, end_pad)) 719 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING; 720 721 props->vendor_part_id = mdev->pdev->device; 722 props->hw_ver = mdev->pdev->revision; 723 724 props->max_mr_size = ~0ull; 725 props->page_size_cap = ~(min_page_size - 1); 726 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 727 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 728 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 729 sizeof(struct mlx5_wqe_data_seg); 730 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512); 731 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) - 732 sizeof(struct mlx5_wqe_raddr_seg)) / 733 sizeof(struct mlx5_wqe_data_seg); 734 props->max_sge = min(max_rq_sg, max_sq_sg); 735 props->max_sge_rd = MLX5_MAX_SGE_RD; 736 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 737 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 738 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 739 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 740 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 741 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 742 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 743 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 744 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 745 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 746 props->max_srq_sge = max_rq_sg - 1; 747 props->max_fast_reg_page_list_len = 748 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 749 get_atomic_caps(dev, props); 750 props->masked_atomic_cap = IB_ATOMIC_NONE; 751 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 752 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 753 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 754 props->max_mcast_grp; 755 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */ 756 props->max_ah = INT_MAX; 757 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 758 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 759 760 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 761 if (MLX5_CAP_GEN(mdev, pg)) 762 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING; 763 props->odp_caps = dev->odp_caps; 764 #endif 765 766 if (MLX5_CAP_GEN(mdev, cd)) 767 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL; 768 769 if (!mlx5_core_is_pf(mdev)) 770 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION; 771 772 if (mlx5_ib_port_link_layer(ibdev, 1) == 773 IB_LINK_LAYER_ETHERNET) { 774 props->rss_caps.max_rwq_indirection_tables = 775 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 776 props->rss_caps.max_rwq_indirection_table_size = 777 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 778 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 779 props->max_wq_type_rq = 780 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 781 } 782 783 if (MLX5_CAP_GEN(mdev, tag_matching)) { 784 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE; 785 props->tm_caps.max_num_tags = 786 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1; 787 props->tm_caps.flags = IB_TM_CAP_RC; 788 props->tm_caps.max_ops = 789 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 790 props->tm_caps.max_sge = MLX5_TM_MAX_SGE; 791 } 792 793 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) { 794 resp.cqe_comp_caps.max_num = 795 MLX5_CAP_GEN(dev->mdev, cqe_compression) ? 796 MLX5_CAP_GEN(dev->mdev, cqe_compression_max_num) : 0; 797 resp.cqe_comp_caps.supported_format = 798 MLX5_IB_CQE_RES_FORMAT_HASH | 799 MLX5_IB_CQE_RES_FORMAT_CSUM; 800 resp.response_length += sizeof(resp.cqe_comp_caps); 801 } 802 803 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen)) { 804 if (MLX5_CAP_QOS(mdev, packet_pacing) && 805 MLX5_CAP_GEN(mdev, qos)) { 806 resp.packet_pacing_caps.qp_rate_limit_max = 807 MLX5_CAP_QOS(mdev, packet_pacing_max_rate); 808 resp.packet_pacing_caps.qp_rate_limit_min = 809 MLX5_CAP_QOS(mdev, packet_pacing_min_rate); 810 resp.packet_pacing_caps.supported_qpts |= 811 1 << IB_QPT_RAW_PACKET; 812 } 813 resp.response_length += sizeof(resp.packet_pacing_caps); 814 } 815 816 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes, 817 uhw->outlen)) { 818 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe)) 819 resp.mlx5_ib_support_multi_pkt_send_wqes = 820 MLX5_IB_ALLOW_MPW; 821 822 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe)) 823 resp.mlx5_ib_support_multi_pkt_send_wqes |= 824 MLX5_IB_SUPPORT_EMPW; 825 826 resp.response_length += 827 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes); 828 } 829 830 if (field_avail(typeof(resp), flags, uhw->outlen)) { 831 resp.response_length += sizeof(resp.flags); 832 833 if (MLX5_CAP_GEN(mdev, cqe_compression_128)) 834 resp.flags |= 835 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP; 836 837 if (MLX5_CAP_GEN(mdev, cqe_128_always)) 838 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD; 839 } 840 841 if (field_avail(typeof(resp), sw_parsing_caps, 842 uhw->outlen)) { 843 resp.response_length += sizeof(resp.sw_parsing_caps); 844 if (MLX5_CAP_ETH(mdev, swp)) { 845 resp.sw_parsing_caps.sw_parsing_offloads |= 846 MLX5_IB_SW_PARSING; 847 848 if (MLX5_CAP_ETH(mdev, swp_csum)) 849 resp.sw_parsing_caps.sw_parsing_offloads |= 850 MLX5_IB_SW_PARSING_CSUM; 851 852 if (MLX5_CAP_ETH(mdev, swp_lso)) 853 resp.sw_parsing_caps.sw_parsing_offloads |= 854 MLX5_IB_SW_PARSING_LSO; 855 856 if (resp.sw_parsing_caps.sw_parsing_offloads) 857 resp.sw_parsing_caps.supported_qpts = 858 BIT(IB_QPT_RAW_PACKET); 859 } 860 } 861 862 if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen)) { 863 resp.response_length += sizeof(resp.striding_rq_caps); 864 if (MLX5_CAP_GEN(mdev, striding_rq)) { 865 resp.striding_rq_caps.min_single_stride_log_num_of_bytes = 866 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES; 867 resp.striding_rq_caps.max_single_stride_log_num_of_bytes = 868 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES; 869 resp.striding_rq_caps.min_single_wqe_log_num_of_strides = 870 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 871 resp.striding_rq_caps.max_single_wqe_log_num_of_strides = 872 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES; 873 resp.striding_rq_caps.supported_qpts = 874 BIT(IB_QPT_RAW_PACKET); 875 } 876 } 877 878 if (field_avail(typeof(resp), tunnel_offloads_caps, 879 uhw->outlen)) { 880 resp.response_length += sizeof(resp.tunnel_offloads_caps); 881 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan)) 882 resp.tunnel_offloads_caps |= 883 MLX5_IB_TUNNELED_OFFLOADS_VXLAN; 884 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx)) 885 resp.tunnel_offloads_caps |= 886 MLX5_IB_TUNNELED_OFFLOADS_GENEVE; 887 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) 888 resp.tunnel_offloads_caps |= 889 MLX5_IB_TUNNELED_OFFLOADS_GRE; 890 } 891 892 if (uhw->outlen) { 893 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 894 895 if (err) 896 return err; 897 } 898 899 return 0; 900 } 901 902 enum mlx5_ib_width { 903 MLX5_IB_WIDTH_1X = 1 << 0, 904 MLX5_IB_WIDTH_2X = 1 << 1, 905 MLX5_IB_WIDTH_4X = 1 << 2, 906 MLX5_IB_WIDTH_8X = 1 << 3, 907 MLX5_IB_WIDTH_12X = 1 << 4 908 }; 909 910 static int translate_active_width(struct ib_device *ibdev, u8 active_width, 911 u8 *ib_width) 912 { 913 struct mlx5_ib_dev *dev = to_mdev(ibdev); 914 int err = 0; 915 916 if (active_width & MLX5_IB_WIDTH_1X) { 917 *ib_width = IB_WIDTH_1X; 918 } else if (active_width & MLX5_IB_WIDTH_2X) { 919 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n", 920 (int)active_width); 921 err = -EINVAL; 922 } else if (active_width & MLX5_IB_WIDTH_4X) { 923 *ib_width = IB_WIDTH_4X; 924 } else if (active_width & MLX5_IB_WIDTH_8X) { 925 *ib_width = IB_WIDTH_8X; 926 } else if (active_width & MLX5_IB_WIDTH_12X) { 927 *ib_width = IB_WIDTH_12X; 928 } else { 929 mlx5_ib_dbg(dev, "Invalid active_width %d\n", 930 (int)active_width); 931 err = -EINVAL; 932 } 933 934 return err; 935 } 936 937 static int mlx5_mtu_to_ib_mtu(int mtu) 938 { 939 switch (mtu) { 940 case 256: return 1; 941 case 512: return 2; 942 case 1024: return 3; 943 case 2048: return 4; 944 case 4096: return 5; 945 default: 946 pr_warn("invalid mtu\n"); 947 return -1; 948 } 949 } 950 951 enum ib_max_vl_num { 952 __IB_MAX_VL_0 = 1, 953 __IB_MAX_VL_0_1 = 2, 954 __IB_MAX_VL_0_3 = 3, 955 __IB_MAX_VL_0_7 = 4, 956 __IB_MAX_VL_0_14 = 5, 957 }; 958 959 enum mlx5_vl_hw_cap { 960 MLX5_VL_HW_0 = 1, 961 MLX5_VL_HW_0_1 = 2, 962 MLX5_VL_HW_0_2 = 3, 963 MLX5_VL_HW_0_3 = 4, 964 MLX5_VL_HW_0_4 = 5, 965 MLX5_VL_HW_0_5 = 6, 966 MLX5_VL_HW_0_6 = 7, 967 MLX5_VL_HW_0_7 = 8, 968 MLX5_VL_HW_0_14 = 15 969 }; 970 971 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 972 u8 *max_vl_num) 973 { 974 switch (vl_hw_cap) { 975 case MLX5_VL_HW_0: 976 *max_vl_num = __IB_MAX_VL_0; 977 break; 978 case MLX5_VL_HW_0_1: 979 *max_vl_num = __IB_MAX_VL_0_1; 980 break; 981 case MLX5_VL_HW_0_3: 982 *max_vl_num = __IB_MAX_VL_0_3; 983 break; 984 case MLX5_VL_HW_0_7: 985 *max_vl_num = __IB_MAX_VL_0_7; 986 break; 987 case MLX5_VL_HW_0_14: 988 *max_vl_num = __IB_MAX_VL_0_14; 989 break; 990 991 default: 992 return -EINVAL; 993 } 994 995 return 0; 996 } 997 998 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port, 999 struct ib_port_attr *props) 1000 { 1001 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1002 struct mlx5_core_dev *mdev = dev->mdev; 1003 struct mlx5_hca_vport_context *rep; 1004 u16 max_mtu; 1005 u16 oper_mtu; 1006 int err; 1007 u8 ib_link_width_oper; 1008 u8 vl_hw_cap; 1009 1010 rep = kzalloc(sizeof(*rep), GFP_KERNEL); 1011 if (!rep) { 1012 err = -ENOMEM; 1013 goto out; 1014 } 1015 1016 /* props being zeroed by the caller, avoid zeroing it here */ 1017 1018 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); 1019 if (err) 1020 goto out; 1021 1022 props->lid = rep->lid; 1023 props->lmc = rep->lmc; 1024 props->sm_lid = rep->sm_lid; 1025 props->sm_sl = rep->sm_sl; 1026 props->state = rep->vport_state; 1027 props->phys_state = rep->port_physical_state; 1028 props->port_cap_flags = rep->cap_mask1; 1029 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 1030 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 1031 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 1032 props->bad_pkey_cntr = rep->pkey_violation_counter; 1033 props->qkey_viol_cntr = rep->qkey_violation_counter; 1034 props->subnet_timeout = rep->subnet_timeout; 1035 props->init_type_reply = rep->init_type_reply; 1036 props->grh_required = rep->grh_required; 1037 1038 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port); 1039 if (err) 1040 goto out; 1041 1042 err = translate_active_width(ibdev, ib_link_width_oper, 1043 &props->active_width); 1044 if (err) 1045 goto out; 1046 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port); 1047 if (err) 1048 goto out; 1049 1050 mlx5_query_port_max_mtu(mdev, &max_mtu, port); 1051 1052 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); 1053 1054 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); 1055 1056 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); 1057 1058 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); 1059 if (err) 1060 goto out; 1061 1062 err = translate_max_vl_num(ibdev, vl_hw_cap, 1063 &props->max_vl_num); 1064 out: 1065 kfree(rep); 1066 return err; 1067 } 1068 1069 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 1070 struct ib_port_attr *props) 1071 { 1072 unsigned int count; 1073 int ret; 1074 1075 switch (mlx5_get_vport_access_method(ibdev)) { 1076 case MLX5_VPORT_ACCESS_METHOD_MAD: 1077 ret = mlx5_query_mad_ifc_port(ibdev, port, props); 1078 break; 1079 1080 case MLX5_VPORT_ACCESS_METHOD_HCA: 1081 ret = mlx5_query_hca_port(ibdev, port, props); 1082 break; 1083 1084 case MLX5_VPORT_ACCESS_METHOD_NIC: 1085 ret = mlx5_query_port_roce(ibdev, port, props); 1086 break; 1087 1088 default: 1089 ret = -EINVAL; 1090 } 1091 1092 if (!ret && props) { 1093 count = mlx5_core_reserved_gids_count(to_mdev(ibdev)->mdev); 1094 props->gid_tbl_len -= count; 1095 } 1096 return ret; 1097 } 1098 1099 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 1100 union ib_gid *gid) 1101 { 1102 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1103 struct mlx5_core_dev *mdev = dev->mdev; 1104 1105 switch (mlx5_get_vport_access_method(ibdev)) { 1106 case MLX5_VPORT_ACCESS_METHOD_MAD: 1107 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 1108 1109 case MLX5_VPORT_ACCESS_METHOD_HCA: 1110 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); 1111 1112 default: 1113 return -EINVAL; 1114 } 1115 1116 } 1117 1118 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 1119 u16 *pkey) 1120 { 1121 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1122 struct mlx5_core_dev *mdev = dev->mdev; 1123 1124 switch (mlx5_get_vport_access_method(ibdev)) { 1125 case MLX5_VPORT_ACCESS_METHOD_MAD: 1126 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 1127 1128 case MLX5_VPORT_ACCESS_METHOD_HCA: 1129 case MLX5_VPORT_ACCESS_METHOD_NIC: 1130 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index, 1131 pkey); 1132 default: 1133 return -EINVAL; 1134 } 1135 } 1136 1137 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 1138 struct ib_device_modify *props) 1139 { 1140 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1141 struct mlx5_reg_node_desc in; 1142 struct mlx5_reg_node_desc out; 1143 int err; 1144 1145 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 1146 return -EOPNOTSUPP; 1147 1148 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 1149 return 0; 1150 1151 /* 1152 * If possible, pass node desc to FW, so it can generate 1153 * a 144 trap. If cmd fails, just ignore. 1154 */ 1155 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1156 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 1157 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 1158 if (err) 1159 return err; 1160 1161 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1162 1163 return err; 1164 } 1165 1166 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask, 1167 u32 value) 1168 { 1169 struct mlx5_hca_vport_context ctx = {}; 1170 int err; 1171 1172 err = mlx5_query_hca_vport_context(dev->mdev, 0, 1173 port_num, 0, &ctx); 1174 if (err) 1175 return err; 1176 1177 if (~ctx.cap_mask1_perm & mask) { 1178 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n", 1179 mask, ctx.cap_mask1_perm); 1180 return -EINVAL; 1181 } 1182 1183 ctx.cap_mask1 = value; 1184 ctx.cap_mask1_perm = mask; 1185 err = mlx5_core_modify_hca_vport_context(dev->mdev, 0, 1186 port_num, 0, &ctx); 1187 1188 return err; 1189 } 1190 1191 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, 1192 struct ib_port_modify *props) 1193 { 1194 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1195 struct ib_port_attr attr; 1196 u32 tmp; 1197 int err; 1198 u32 change_mask; 1199 u32 value; 1200 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) == 1201 IB_LINK_LAYER_INFINIBAND); 1202 1203 /* CM layer calls ib_modify_port() regardless of the link layer. For 1204 * Ethernet ports, qkey violation and Port capabilities are meaningless. 1205 */ 1206 if (!is_ib) 1207 return 0; 1208 1209 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) { 1210 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask; 1211 value = ~props->clr_port_cap_mask | props->set_port_cap_mask; 1212 return set_port_caps_atomic(dev, port, change_mask, value); 1213 } 1214 1215 mutex_lock(&dev->cap_mask_mutex); 1216 1217 err = ib_query_port(ibdev, port, &attr); 1218 if (err) 1219 goto out; 1220 1221 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 1222 ~props->clr_port_cap_mask; 1223 1224 err = mlx5_set_port_caps(dev->mdev, port, tmp); 1225 1226 out: 1227 mutex_unlock(&dev->cap_mask_mutex); 1228 return err; 1229 } 1230 1231 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps) 1232 { 1233 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n", 1234 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n"); 1235 } 1236 1237 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k, 1238 struct mlx5_ib_alloc_ucontext_req_v2 *req, 1239 u32 *num_sys_pages) 1240 { 1241 int uars_per_sys_page; 1242 int bfregs_per_sys_page; 1243 int ref_bfregs = req->total_num_bfregs; 1244 1245 if (req->total_num_bfregs == 0) 1246 return -EINVAL; 1247 1248 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE); 1249 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE); 1250 1251 if (req->total_num_bfregs > MLX5_MAX_BFREGS) 1252 return -ENOMEM; 1253 1254 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k); 1255 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR; 1256 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page); 1257 *num_sys_pages = req->total_num_bfregs / bfregs_per_sys_page; 1258 1259 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1) 1260 return -EINVAL; 1261 1262 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, using %d sys pages\n", 1263 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no", 1264 lib_uar_4k ? "yes" : "no", ref_bfregs, 1265 req->total_num_bfregs, *num_sys_pages); 1266 1267 return 0; 1268 } 1269 1270 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1271 { 1272 struct mlx5_bfreg_info *bfregi; 1273 int err; 1274 int i; 1275 1276 bfregi = &context->bfregi; 1277 for (i = 0; i < bfregi->num_sys_pages; i++) { 1278 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]); 1279 if (err) 1280 goto error; 1281 1282 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]); 1283 } 1284 return 0; 1285 1286 error: 1287 for (--i; i >= 0; i--) 1288 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i])) 1289 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1290 1291 return err; 1292 } 1293 1294 static int deallocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1295 { 1296 struct mlx5_bfreg_info *bfregi; 1297 int err; 1298 int i; 1299 1300 bfregi = &context->bfregi; 1301 for (i = 0; i < bfregi->num_sys_pages; i++) { 1302 err = mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]); 1303 if (err) { 1304 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1305 return err; 1306 } 1307 } 1308 return 0; 1309 } 1310 1311 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn) 1312 { 1313 int err; 1314 1315 err = mlx5_core_alloc_transport_domain(dev->mdev, tdn); 1316 if (err) 1317 return err; 1318 1319 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1320 !MLX5_CAP_GEN(dev->mdev, disable_local_lb)) 1321 return err; 1322 1323 mutex_lock(&dev->lb_mutex); 1324 dev->user_td++; 1325 1326 if (dev->user_td == 2) 1327 err = mlx5_nic_vport_update_local_lb(dev->mdev, true); 1328 1329 mutex_unlock(&dev->lb_mutex); 1330 return err; 1331 } 1332 1333 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn) 1334 { 1335 mlx5_core_dealloc_transport_domain(dev->mdev, tdn); 1336 1337 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1338 !MLX5_CAP_GEN(dev->mdev, disable_local_lb)) 1339 return; 1340 1341 mutex_lock(&dev->lb_mutex); 1342 dev->user_td--; 1343 1344 if (dev->user_td < 2) 1345 mlx5_nic_vport_update_local_lb(dev->mdev, false); 1346 1347 mutex_unlock(&dev->lb_mutex); 1348 } 1349 1350 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev, 1351 struct ib_udata *udata) 1352 { 1353 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1354 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 1355 struct mlx5_ib_alloc_ucontext_resp resp = {}; 1356 struct mlx5_ib_ucontext *context; 1357 struct mlx5_bfreg_info *bfregi; 1358 int ver; 1359 int err; 1360 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 1361 max_cqe_version); 1362 bool lib_uar_4k; 1363 1364 if (!dev->ib_active) 1365 return ERR_PTR(-EAGAIN); 1366 1367 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 1368 ver = 0; 1369 else if (udata->inlen >= min_req_v2) 1370 ver = 2; 1371 else 1372 return ERR_PTR(-EINVAL); 1373 1374 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req))); 1375 if (err) 1376 return ERR_PTR(err); 1377 1378 if (req.flags) 1379 return ERR_PTR(-EINVAL); 1380 1381 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 1382 return ERR_PTR(-EOPNOTSUPP); 1383 1384 req.total_num_bfregs = ALIGN(req.total_num_bfregs, 1385 MLX5_NON_FP_BFREGS_PER_UAR); 1386 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1) 1387 return ERR_PTR(-EINVAL); 1388 1389 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 1390 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf)) 1391 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size); 1392 resp.cache_line_size = cache_line_size(); 1393 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 1394 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 1395 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1396 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1397 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 1398 resp.cqe_version = min_t(__u8, 1399 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 1400 req.max_cqe_version); 1401 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1402 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT; 1403 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1404 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1; 1405 resp.response_length = min(offsetof(typeof(resp), response_length) + 1406 sizeof(resp.response_length), udata->outlen); 1407 1408 context = kzalloc(sizeof(*context), GFP_KERNEL); 1409 if (!context) 1410 return ERR_PTR(-ENOMEM); 1411 1412 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR; 1413 bfregi = &context->bfregi; 1414 1415 /* updates req->total_num_bfregs */ 1416 err = calc_total_bfregs(dev, lib_uar_4k, &req, &bfregi->num_sys_pages); 1417 if (err) 1418 goto out_ctx; 1419 1420 mutex_init(&bfregi->lock); 1421 bfregi->lib_uar_4k = lib_uar_4k; 1422 bfregi->count = kcalloc(req.total_num_bfregs, sizeof(*bfregi->count), 1423 GFP_KERNEL); 1424 if (!bfregi->count) { 1425 err = -ENOMEM; 1426 goto out_ctx; 1427 } 1428 1429 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages, 1430 sizeof(*bfregi->sys_pages), 1431 GFP_KERNEL); 1432 if (!bfregi->sys_pages) { 1433 err = -ENOMEM; 1434 goto out_count; 1435 } 1436 1437 err = allocate_uars(dev, context); 1438 if (err) 1439 goto out_sys_pages; 1440 1441 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1442 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range; 1443 #endif 1444 1445 context->upd_xlt_page = __get_free_page(GFP_KERNEL); 1446 if (!context->upd_xlt_page) { 1447 err = -ENOMEM; 1448 goto out_uars; 1449 } 1450 mutex_init(&context->upd_xlt_page_mutex); 1451 1452 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) { 1453 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn); 1454 if (err) 1455 goto out_page; 1456 } 1457 1458 INIT_LIST_HEAD(&context->vma_private_list); 1459 INIT_LIST_HEAD(&context->db_page_list); 1460 mutex_init(&context->db_page_mutex); 1461 1462 resp.tot_bfregs = req.total_num_bfregs; 1463 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports); 1464 1465 if (field_avail(typeof(resp), cqe_version, udata->outlen)) 1466 resp.response_length += sizeof(resp.cqe_version); 1467 1468 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) { 1469 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 1470 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 1471 resp.response_length += sizeof(resp.cmds_supp_uhw); 1472 } 1473 1474 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) { 1475 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) { 1476 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline); 1477 resp.eth_min_inline++; 1478 } 1479 resp.response_length += sizeof(resp.eth_min_inline); 1480 } 1481 1482 /* 1483 * We don't want to expose information from the PCI bar that is located 1484 * after 4096 bytes, so if the arch only supports larger pages, let's 1485 * pretend we don't support reading the HCA's core clock. This is also 1486 * forced by mmap function. 1487 */ 1488 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) { 1489 if (PAGE_SIZE <= 4096) { 1490 resp.comp_mask |= 1491 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 1492 resp.hca_core_clock_offset = 1493 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE; 1494 } 1495 resp.response_length += sizeof(resp.hca_core_clock_offset) + 1496 sizeof(resp.reserved2); 1497 } 1498 1499 if (field_avail(typeof(resp), log_uar_size, udata->outlen)) 1500 resp.response_length += sizeof(resp.log_uar_size); 1501 1502 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen)) 1503 resp.response_length += sizeof(resp.num_uars_per_page); 1504 1505 err = ib_copy_to_udata(udata, &resp, resp.response_length); 1506 if (err) 1507 goto out_td; 1508 1509 bfregi->ver = ver; 1510 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs; 1511 context->cqe_version = resp.cqe_version; 1512 context->lib_caps = req.lib_caps; 1513 print_lib_caps(dev, context->lib_caps); 1514 1515 return &context->ibucontext; 1516 1517 out_td: 1518 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1519 mlx5_ib_dealloc_transport_domain(dev, context->tdn); 1520 1521 out_page: 1522 free_page(context->upd_xlt_page); 1523 1524 out_uars: 1525 deallocate_uars(dev, context); 1526 1527 out_sys_pages: 1528 kfree(bfregi->sys_pages); 1529 1530 out_count: 1531 kfree(bfregi->count); 1532 1533 out_ctx: 1534 kfree(context); 1535 1536 return ERR_PTR(err); 1537 } 1538 1539 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1540 { 1541 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1542 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1543 struct mlx5_bfreg_info *bfregi; 1544 1545 bfregi = &context->bfregi; 1546 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1547 mlx5_ib_dealloc_transport_domain(dev, context->tdn); 1548 1549 free_page(context->upd_xlt_page); 1550 deallocate_uars(dev, context); 1551 kfree(bfregi->sys_pages); 1552 kfree(bfregi->count); 1553 kfree(context); 1554 1555 return 0; 1556 } 1557 1558 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, 1559 struct mlx5_bfreg_info *bfregi, 1560 int idx) 1561 { 1562 int fw_uars_per_page; 1563 1564 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1; 1565 1566 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + 1567 bfregi->sys_pages[idx] / fw_uars_per_page; 1568 } 1569 1570 static int get_command(unsigned long offset) 1571 { 1572 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 1573 } 1574 1575 static int get_arg(unsigned long offset) 1576 { 1577 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 1578 } 1579 1580 static int get_index(unsigned long offset) 1581 { 1582 return get_arg(offset); 1583 } 1584 1585 static void mlx5_ib_vma_open(struct vm_area_struct *area) 1586 { 1587 /* vma_open is called when a new VMA is created on top of our VMA. This 1588 * is done through either mremap flow or split_vma (usually due to 1589 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA, 1590 * as this VMA is strongly hardware related. Therefore we set the 1591 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from 1592 * calling us again and trying to do incorrect actions. We assume that 1593 * the original VMA size is exactly a single page, and therefore all 1594 * "splitting" operation will not happen to it. 1595 */ 1596 area->vm_ops = NULL; 1597 } 1598 1599 static void mlx5_ib_vma_close(struct vm_area_struct *area) 1600 { 1601 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data; 1602 1603 /* It's guaranteed that all VMAs opened on a FD are closed before the 1604 * file itself is closed, therefore no sync is needed with the regular 1605 * closing flow. (e.g. mlx5 ib_dealloc_ucontext) 1606 * However need a sync with accessing the vma as part of 1607 * mlx5_ib_disassociate_ucontext. 1608 * The close operation is usually called under mm->mmap_sem except when 1609 * process is exiting. 1610 * The exiting case is handled explicitly as part of 1611 * mlx5_ib_disassociate_ucontext. 1612 */ 1613 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data; 1614 1615 /* setting the vma context pointer to null in the mlx5_ib driver's 1616 * private data, to protect a race condition in 1617 * mlx5_ib_disassociate_ucontext(). 1618 */ 1619 mlx5_ib_vma_priv_data->vma = NULL; 1620 list_del(&mlx5_ib_vma_priv_data->list); 1621 kfree(mlx5_ib_vma_priv_data); 1622 } 1623 1624 static const struct vm_operations_struct mlx5_ib_vm_ops = { 1625 .open = mlx5_ib_vma_open, 1626 .close = mlx5_ib_vma_close 1627 }; 1628 1629 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma, 1630 struct mlx5_ib_ucontext *ctx) 1631 { 1632 struct mlx5_ib_vma_private_data *vma_prv; 1633 struct list_head *vma_head = &ctx->vma_private_list; 1634 1635 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL); 1636 if (!vma_prv) 1637 return -ENOMEM; 1638 1639 vma_prv->vma = vma; 1640 vma->vm_private_data = vma_prv; 1641 vma->vm_ops = &mlx5_ib_vm_ops; 1642 1643 list_add(&vma_prv->list, vma_head); 1644 1645 return 0; 1646 } 1647 1648 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 1649 { 1650 int ret; 1651 struct vm_area_struct *vma; 1652 struct mlx5_ib_vma_private_data *vma_private, *n; 1653 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1654 struct task_struct *owning_process = NULL; 1655 struct mm_struct *owning_mm = NULL; 1656 1657 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID); 1658 if (!owning_process) 1659 return; 1660 1661 owning_mm = get_task_mm(owning_process); 1662 if (!owning_mm) { 1663 pr_info("no mm, disassociate ucontext is pending task termination\n"); 1664 while (1) { 1665 put_task_struct(owning_process); 1666 usleep_range(1000, 2000); 1667 owning_process = get_pid_task(ibcontext->tgid, 1668 PIDTYPE_PID); 1669 if (!owning_process || 1670 owning_process->state == TASK_DEAD) { 1671 pr_info("disassociate ucontext done, task was terminated\n"); 1672 /* in case task was dead need to release the 1673 * task struct. 1674 */ 1675 if (owning_process) 1676 put_task_struct(owning_process); 1677 return; 1678 } 1679 } 1680 } 1681 1682 /* need to protect from a race on closing the vma as part of 1683 * mlx5_ib_vma_close. 1684 */ 1685 down_write(&owning_mm->mmap_sem); 1686 list_for_each_entry_safe(vma_private, n, &context->vma_private_list, 1687 list) { 1688 vma = vma_private->vma; 1689 ret = zap_vma_ptes(vma, vma->vm_start, 1690 PAGE_SIZE); 1691 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__); 1692 /* context going to be destroyed, should 1693 * not access ops any more. 1694 */ 1695 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE); 1696 vma->vm_ops = NULL; 1697 list_del(&vma_private->list); 1698 kfree(vma_private); 1699 } 1700 up_write(&owning_mm->mmap_sem); 1701 mmput(owning_mm); 1702 put_task_struct(owning_process); 1703 } 1704 1705 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 1706 { 1707 switch (cmd) { 1708 case MLX5_IB_MMAP_WC_PAGE: 1709 return "WC"; 1710 case MLX5_IB_MMAP_REGULAR_PAGE: 1711 return "best effort WC"; 1712 case MLX5_IB_MMAP_NC_PAGE: 1713 return "NC"; 1714 default: 1715 return NULL; 1716 } 1717 } 1718 1719 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 1720 struct vm_area_struct *vma, 1721 struct mlx5_ib_ucontext *context) 1722 { 1723 struct mlx5_bfreg_info *bfregi = &context->bfregi; 1724 int err; 1725 unsigned long idx; 1726 phys_addr_t pfn, pa; 1727 pgprot_t prot; 1728 int uars_per_page; 1729 1730 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1731 return -EINVAL; 1732 1733 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k); 1734 idx = get_index(vma->vm_pgoff); 1735 if (idx % uars_per_page || 1736 idx * uars_per_page >= bfregi->num_sys_pages) { 1737 mlx5_ib_warn(dev, "invalid uar index %lu\n", idx); 1738 return -EINVAL; 1739 } 1740 1741 switch (cmd) { 1742 case MLX5_IB_MMAP_WC_PAGE: 1743 /* Some architectures don't support WC memory */ 1744 #if defined(CONFIG_X86) 1745 if (!pat_enabled()) 1746 return -EPERM; 1747 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU))) 1748 return -EPERM; 1749 #endif 1750 /* fall through */ 1751 case MLX5_IB_MMAP_REGULAR_PAGE: 1752 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 1753 prot = pgprot_writecombine(vma->vm_page_prot); 1754 break; 1755 case MLX5_IB_MMAP_NC_PAGE: 1756 prot = pgprot_noncached(vma->vm_page_prot); 1757 break; 1758 default: 1759 return -EINVAL; 1760 } 1761 1762 pfn = uar_index2pfn(dev, bfregi, idx); 1763 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 1764 1765 vma->vm_page_prot = prot; 1766 err = io_remap_pfn_range(vma, vma->vm_start, pfn, 1767 PAGE_SIZE, vma->vm_page_prot); 1768 if (err) { 1769 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n", 1770 err, vma->vm_start, &pfn, mmap_cmd2str(cmd)); 1771 return -EAGAIN; 1772 } 1773 1774 pa = pfn << PAGE_SHIFT; 1775 mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd), 1776 vma->vm_start, &pa); 1777 1778 return mlx5_ib_set_vma_data(vma, context); 1779 } 1780 1781 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 1782 { 1783 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1784 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1785 unsigned long command; 1786 phys_addr_t pfn; 1787 1788 command = get_command(vma->vm_pgoff); 1789 switch (command) { 1790 case MLX5_IB_MMAP_WC_PAGE: 1791 case MLX5_IB_MMAP_NC_PAGE: 1792 case MLX5_IB_MMAP_REGULAR_PAGE: 1793 return uar_mmap(dev, command, vma, context); 1794 1795 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 1796 return -ENOSYS; 1797 1798 case MLX5_IB_MMAP_CORE_CLOCK: 1799 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1800 return -EINVAL; 1801 1802 if (vma->vm_flags & VM_WRITE) 1803 return -EPERM; 1804 1805 /* Don't expose to user-space information it shouldn't have */ 1806 if (PAGE_SIZE > 4096) 1807 return -EOPNOTSUPP; 1808 1809 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 1810 pfn = (dev->mdev->iseg_base + 1811 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 1812 PAGE_SHIFT; 1813 if (io_remap_pfn_range(vma, vma->vm_start, pfn, 1814 PAGE_SIZE, vma->vm_page_prot)) 1815 return -EAGAIN; 1816 1817 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n", 1818 vma->vm_start, 1819 (unsigned long long)pfn << PAGE_SHIFT); 1820 break; 1821 1822 default: 1823 return -EINVAL; 1824 } 1825 1826 return 0; 1827 } 1828 1829 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev, 1830 struct ib_ucontext *context, 1831 struct ib_udata *udata) 1832 { 1833 struct mlx5_ib_alloc_pd_resp resp; 1834 struct mlx5_ib_pd *pd; 1835 int err; 1836 1837 pd = kmalloc(sizeof(*pd), GFP_KERNEL); 1838 if (!pd) 1839 return ERR_PTR(-ENOMEM); 1840 1841 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn); 1842 if (err) { 1843 kfree(pd); 1844 return ERR_PTR(err); 1845 } 1846 1847 if (context) { 1848 resp.pdn = pd->pdn; 1849 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 1850 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn); 1851 kfree(pd); 1852 return ERR_PTR(-EFAULT); 1853 } 1854 } 1855 1856 return &pd->ibpd; 1857 } 1858 1859 static int mlx5_ib_dealloc_pd(struct ib_pd *pd) 1860 { 1861 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 1862 struct mlx5_ib_pd *mpd = to_mpd(pd); 1863 1864 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn); 1865 kfree(mpd); 1866 1867 return 0; 1868 } 1869 1870 enum { 1871 MATCH_CRITERIA_ENABLE_OUTER_BIT, 1872 MATCH_CRITERIA_ENABLE_MISC_BIT, 1873 MATCH_CRITERIA_ENABLE_INNER_BIT 1874 }; 1875 1876 #define HEADER_IS_ZERO(match_criteria, headers) \ 1877 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \ 1878 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \ 1879 1880 static u8 get_match_criteria_enable(u32 *match_criteria) 1881 { 1882 u8 match_criteria_enable; 1883 1884 match_criteria_enable = 1885 (!HEADER_IS_ZERO(match_criteria, outer_headers)) << 1886 MATCH_CRITERIA_ENABLE_OUTER_BIT; 1887 match_criteria_enable |= 1888 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) << 1889 MATCH_CRITERIA_ENABLE_MISC_BIT; 1890 match_criteria_enable |= 1891 (!HEADER_IS_ZERO(match_criteria, inner_headers)) << 1892 MATCH_CRITERIA_ENABLE_INNER_BIT; 1893 1894 return match_criteria_enable; 1895 } 1896 1897 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val) 1898 { 1899 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask); 1900 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val); 1901 } 1902 1903 static void set_flow_label(void *misc_c, void *misc_v, u8 mask, u8 val, 1904 bool inner) 1905 { 1906 if (inner) { 1907 MLX5_SET(fte_match_set_misc, 1908 misc_c, inner_ipv6_flow_label, mask); 1909 MLX5_SET(fte_match_set_misc, 1910 misc_v, inner_ipv6_flow_label, val); 1911 } else { 1912 MLX5_SET(fte_match_set_misc, 1913 misc_c, outer_ipv6_flow_label, mask); 1914 MLX5_SET(fte_match_set_misc, 1915 misc_v, outer_ipv6_flow_label, val); 1916 } 1917 } 1918 1919 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val) 1920 { 1921 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask); 1922 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val); 1923 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2); 1924 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2); 1925 } 1926 1927 #define LAST_ETH_FIELD vlan_tag 1928 #define LAST_IB_FIELD sl 1929 #define LAST_IPV4_FIELD tos 1930 #define LAST_IPV6_FIELD traffic_class 1931 #define LAST_TCP_UDP_FIELD src_port 1932 #define LAST_TUNNEL_FIELD tunnel_id 1933 #define LAST_FLOW_TAG_FIELD tag_id 1934 #define LAST_DROP_FIELD size 1935 1936 /* Field is the last supported field */ 1937 #define FIELDS_NOT_SUPPORTED(filter, field)\ 1938 memchr_inv((void *)&filter.field +\ 1939 sizeof(filter.field), 0,\ 1940 sizeof(filter) -\ 1941 offsetof(typeof(filter), field) -\ 1942 sizeof(filter.field)) 1943 1944 #define IPV4_VERSION 4 1945 #define IPV6_VERSION 6 1946 static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c, 1947 u32 *match_v, const union ib_flow_spec *ib_spec, 1948 u32 *tag_id, bool *is_drop) 1949 { 1950 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c, 1951 misc_parameters); 1952 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v, 1953 misc_parameters); 1954 void *headers_c; 1955 void *headers_v; 1956 int match_ipv; 1957 1958 if (ib_spec->type & IB_FLOW_SPEC_INNER) { 1959 headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 1960 inner_headers); 1961 headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 1962 inner_headers); 1963 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 1964 ft_field_support.inner_ip_version); 1965 } else { 1966 headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 1967 outer_headers); 1968 headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 1969 outer_headers); 1970 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 1971 ft_field_support.outer_ip_version); 1972 } 1973 1974 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) { 1975 case IB_FLOW_SPEC_ETH: 1976 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD)) 1977 return -EOPNOTSUPP; 1978 1979 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 1980 dmac_47_16), 1981 ib_spec->eth.mask.dst_mac); 1982 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1983 dmac_47_16), 1984 ib_spec->eth.val.dst_mac); 1985 1986 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 1987 smac_47_16), 1988 ib_spec->eth.mask.src_mac); 1989 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1990 smac_47_16), 1991 ib_spec->eth.val.src_mac); 1992 1993 if (ib_spec->eth.mask.vlan_tag) { 1994 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1995 cvlan_tag, 1); 1996 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1997 cvlan_tag, 1); 1998 1999 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2000 first_vid, ntohs(ib_spec->eth.mask.vlan_tag)); 2001 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2002 first_vid, ntohs(ib_spec->eth.val.vlan_tag)); 2003 2004 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2005 first_cfi, 2006 ntohs(ib_spec->eth.mask.vlan_tag) >> 12); 2007 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2008 first_cfi, 2009 ntohs(ib_spec->eth.val.vlan_tag) >> 12); 2010 2011 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2012 first_prio, 2013 ntohs(ib_spec->eth.mask.vlan_tag) >> 13); 2014 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2015 first_prio, 2016 ntohs(ib_spec->eth.val.vlan_tag) >> 13); 2017 } 2018 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2019 ethertype, ntohs(ib_spec->eth.mask.ether_type)); 2020 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2021 ethertype, ntohs(ib_spec->eth.val.ether_type)); 2022 break; 2023 case IB_FLOW_SPEC_IPV4: 2024 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD)) 2025 return -EOPNOTSUPP; 2026 2027 if (match_ipv) { 2028 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2029 ip_version, 0xf); 2030 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2031 ip_version, IPV4_VERSION); 2032 } else { 2033 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2034 ethertype, 0xffff); 2035 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2036 ethertype, ETH_P_IP); 2037 } 2038 2039 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2040 src_ipv4_src_ipv6.ipv4_layout.ipv4), 2041 &ib_spec->ipv4.mask.src_ip, 2042 sizeof(ib_spec->ipv4.mask.src_ip)); 2043 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2044 src_ipv4_src_ipv6.ipv4_layout.ipv4), 2045 &ib_spec->ipv4.val.src_ip, 2046 sizeof(ib_spec->ipv4.val.src_ip)); 2047 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2048 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 2049 &ib_spec->ipv4.mask.dst_ip, 2050 sizeof(ib_spec->ipv4.mask.dst_ip)); 2051 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2052 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 2053 &ib_spec->ipv4.val.dst_ip, 2054 sizeof(ib_spec->ipv4.val.dst_ip)); 2055 2056 set_tos(headers_c, headers_v, 2057 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos); 2058 2059 set_proto(headers_c, headers_v, 2060 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto); 2061 break; 2062 case IB_FLOW_SPEC_IPV6: 2063 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD)) 2064 return -EOPNOTSUPP; 2065 2066 if (match_ipv) { 2067 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2068 ip_version, 0xf); 2069 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2070 ip_version, IPV6_VERSION); 2071 } else { 2072 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2073 ethertype, 0xffff); 2074 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2075 ethertype, ETH_P_IPV6); 2076 } 2077 2078 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2079 src_ipv4_src_ipv6.ipv6_layout.ipv6), 2080 &ib_spec->ipv6.mask.src_ip, 2081 sizeof(ib_spec->ipv6.mask.src_ip)); 2082 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2083 src_ipv4_src_ipv6.ipv6_layout.ipv6), 2084 &ib_spec->ipv6.val.src_ip, 2085 sizeof(ib_spec->ipv6.val.src_ip)); 2086 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2087 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 2088 &ib_spec->ipv6.mask.dst_ip, 2089 sizeof(ib_spec->ipv6.mask.dst_ip)); 2090 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2091 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 2092 &ib_spec->ipv6.val.dst_ip, 2093 sizeof(ib_spec->ipv6.val.dst_ip)); 2094 2095 set_tos(headers_c, headers_v, 2096 ib_spec->ipv6.mask.traffic_class, 2097 ib_spec->ipv6.val.traffic_class); 2098 2099 set_proto(headers_c, headers_v, 2100 ib_spec->ipv6.mask.next_hdr, 2101 ib_spec->ipv6.val.next_hdr); 2102 2103 set_flow_label(misc_params_c, misc_params_v, 2104 ntohl(ib_spec->ipv6.mask.flow_label), 2105 ntohl(ib_spec->ipv6.val.flow_label), 2106 ib_spec->type & IB_FLOW_SPEC_INNER); 2107 2108 break; 2109 case IB_FLOW_SPEC_TCP: 2110 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 2111 LAST_TCP_UDP_FIELD)) 2112 return -EOPNOTSUPP; 2113 2114 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol, 2115 0xff); 2116 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, 2117 IPPROTO_TCP); 2118 2119 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport, 2120 ntohs(ib_spec->tcp_udp.mask.src_port)); 2121 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport, 2122 ntohs(ib_spec->tcp_udp.val.src_port)); 2123 2124 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport, 2125 ntohs(ib_spec->tcp_udp.mask.dst_port)); 2126 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport, 2127 ntohs(ib_spec->tcp_udp.val.dst_port)); 2128 break; 2129 case IB_FLOW_SPEC_UDP: 2130 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 2131 LAST_TCP_UDP_FIELD)) 2132 return -EOPNOTSUPP; 2133 2134 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol, 2135 0xff); 2136 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, 2137 IPPROTO_UDP); 2138 2139 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport, 2140 ntohs(ib_spec->tcp_udp.mask.src_port)); 2141 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport, 2142 ntohs(ib_spec->tcp_udp.val.src_port)); 2143 2144 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport, 2145 ntohs(ib_spec->tcp_udp.mask.dst_port)); 2146 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, 2147 ntohs(ib_spec->tcp_udp.val.dst_port)); 2148 break; 2149 case IB_FLOW_SPEC_VXLAN_TUNNEL: 2150 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask, 2151 LAST_TUNNEL_FIELD)) 2152 return -EOPNOTSUPP; 2153 2154 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni, 2155 ntohl(ib_spec->tunnel.mask.tunnel_id)); 2156 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni, 2157 ntohl(ib_spec->tunnel.val.tunnel_id)); 2158 break; 2159 case IB_FLOW_SPEC_ACTION_TAG: 2160 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag, 2161 LAST_FLOW_TAG_FIELD)) 2162 return -EOPNOTSUPP; 2163 if (ib_spec->flow_tag.tag_id >= BIT(24)) 2164 return -EINVAL; 2165 2166 *tag_id = ib_spec->flow_tag.tag_id; 2167 break; 2168 case IB_FLOW_SPEC_ACTION_DROP: 2169 if (FIELDS_NOT_SUPPORTED(ib_spec->drop, 2170 LAST_DROP_FIELD)) 2171 return -EOPNOTSUPP; 2172 *is_drop = true; 2173 break; 2174 default: 2175 return -EINVAL; 2176 } 2177 2178 return 0; 2179 } 2180 2181 /* If a flow could catch both multicast and unicast packets, 2182 * it won't fall into the multicast flow steering table and this rule 2183 * could steal other multicast packets. 2184 */ 2185 static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr) 2186 { 2187 union ib_flow_spec *flow_spec; 2188 2189 if (ib_attr->type != IB_FLOW_ATTR_NORMAL || 2190 ib_attr->num_of_specs < 1) 2191 return false; 2192 2193 flow_spec = (union ib_flow_spec *)(ib_attr + 1); 2194 if (flow_spec->type == IB_FLOW_SPEC_IPV4) { 2195 struct ib_flow_spec_ipv4 *ipv4_spec; 2196 2197 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec; 2198 if (ipv4_is_multicast(ipv4_spec->val.dst_ip)) 2199 return true; 2200 2201 return false; 2202 } 2203 2204 if (flow_spec->type == IB_FLOW_SPEC_ETH) { 2205 struct ib_flow_spec_eth *eth_spec; 2206 2207 eth_spec = (struct ib_flow_spec_eth *)flow_spec; 2208 return is_multicast_ether_addr(eth_spec->mask.dst_mac) && 2209 is_multicast_ether_addr(eth_spec->val.dst_mac); 2210 } 2211 2212 return false; 2213 } 2214 2215 static bool is_valid_ethertype(struct mlx5_core_dev *mdev, 2216 const struct ib_flow_attr *flow_attr, 2217 bool check_inner) 2218 { 2219 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1); 2220 int match_ipv = check_inner ? 2221 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2222 ft_field_support.inner_ip_version) : 2223 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2224 ft_field_support.outer_ip_version); 2225 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0; 2226 bool ipv4_spec_valid, ipv6_spec_valid; 2227 unsigned int ip_spec_type = 0; 2228 bool has_ethertype = false; 2229 unsigned int spec_index; 2230 bool mask_valid = true; 2231 u16 eth_type = 0; 2232 bool type_valid; 2233 2234 /* Validate that ethertype is correct */ 2235 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 2236 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) && 2237 ib_spec->eth.mask.ether_type) { 2238 mask_valid = (ib_spec->eth.mask.ether_type == 2239 htons(0xffff)); 2240 has_ethertype = true; 2241 eth_type = ntohs(ib_spec->eth.val.ether_type); 2242 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) || 2243 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) { 2244 ip_spec_type = ib_spec->type; 2245 } 2246 ib_spec = (void *)ib_spec + ib_spec->size; 2247 } 2248 2249 type_valid = (!has_ethertype) || (!ip_spec_type); 2250 if (!type_valid && mask_valid) { 2251 ipv4_spec_valid = (eth_type == ETH_P_IP) && 2252 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit)); 2253 ipv6_spec_valid = (eth_type == ETH_P_IPV6) && 2254 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit)); 2255 2256 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) || 2257 (((eth_type == ETH_P_MPLS_UC) || 2258 (eth_type == ETH_P_MPLS_MC)) && match_ipv); 2259 } 2260 2261 return type_valid; 2262 } 2263 2264 static bool is_valid_attr(struct mlx5_core_dev *mdev, 2265 const struct ib_flow_attr *flow_attr) 2266 { 2267 return is_valid_ethertype(mdev, flow_attr, false) && 2268 is_valid_ethertype(mdev, flow_attr, true); 2269 } 2270 2271 static void put_flow_table(struct mlx5_ib_dev *dev, 2272 struct mlx5_ib_flow_prio *prio, bool ft_added) 2273 { 2274 prio->refcount -= !!ft_added; 2275 if (!prio->refcount) { 2276 mlx5_destroy_flow_table(prio->flow_table); 2277 prio->flow_table = NULL; 2278 } 2279 } 2280 2281 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id) 2282 { 2283 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device); 2284 struct mlx5_ib_flow_handler *handler = container_of(flow_id, 2285 struct mlx5_ib_flow_handler, 2286 ibflow); 2287 struct mlx5_ib_flow_handler *iter, *tmp; 2288 2289 mutex_lock(&dev->flow_db.lock); 2290 2291 list_for_each_entry_safe(iter, tmp, &handler->list, list) { 2292 mlx5_del_flow_rules(iter->rule); 2293 put_flow_table(dev, iter->prio, true); 2294 list_del(&iter->list); 2295 kfree(iter); 2296 } 2297 2298 mlx5_del_flow_rules(handler->rule); 2299 put_flow_table(dev, handler->prio, true); 2300 mutex_unlock(&dev->flow_db.lock); 2301 2302 kfree(handler); 2303 2304 return 0; 2305 } 2306 2307 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap) 2308 { 2309 priority *= 2; 2310 if (!dont_trap) 2311 priority++; 2312 return priority; 2313 } 2314 2315 enum flow_table_type { 2316 MLX5_IB_FT_RX, 2317 MLX5_IB_FT_TX 2318 }; 2319 2320 #define MLX5_FS_MAX_TYPES 6 2321 #define MLX5_FS_MAX_ENTRIES BIT(16) 2322 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev, 2323 struct ib_flow_attr *flow_attr, 2324 enum flow_table_type ft_type) 2325 { 2326 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP; 2327 struct mlx5_flow_namespace *ns = NULL; 2328 struct mlx5_ib_flow_prio *prio; 2329 struct mlx5_flow_table *ft; 2330 int max_table_size; 2331 int num_entries; 2332 int num_groups; 2333 int priority; 2334 int err = 0; 2335 2336 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 2337 log_max_ft_size)); 2338 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 2339 if (flow_is_multicast_only(flow_attr) && 2340 !dont_trap) 2341 priority = MLX5_IB_FLOW_MCAST_PRIO; 2342 else 2343 priority = ib_prio_to_core_prio(flow_attr->priority, 2344 dont_trap); 2345 ns = mlx5_get_flow_namespace(dev->mdev, 2346 MLX5_FLOW_NAMESPACE_BYPASS); 2347 num_entries = MLX5_FS_MAX_ENTRIES; 2348 num_groups = MLX5_FS_MAX_TYPES; 2349 prio = &dev->flow_db.prios[priority]; 2350 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 2351 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 2352 ns = mlx5_get_flow_namespace(dev->mdev, 2353 MLX5_FLOW_NAMESPACE_LEFTOVERS); 2354 build_leftovers_ft_param(&priority, 2355 &num_entries, 2356 &num_groups); 2357 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO]; 2358 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 2359 if (!MLX5_CAP_FLOWTABLE(dev->mdev, 2360 allow_sniffer_and_nic_rx_shared_tir)) 2361 return ERR_PTR(-ENOTSUPP); 2362 2363 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ? 2364 MLX5_FLOW_NAMESPACE_SNIFFER_RX : 2365 MLX5_FLOW_NAMESPACE_SNIFFER_TX); 2366 2367 prio = &dev->flow_db.sniffer[ft_type]; 2368 priority = 0; 2369 num_entries = 1; 2370 num_groups = 1; 2371 } 2372 2373 if (!ns) 2374 return ERR_PTR(-ENOTSUPP); 2375 2376 if (num_entries > max_table_size) 2377 return ERR_PTR(-ENOMEM); 2378 2379 ft = prio->flow_table; 2380 if (!ft) { 2381 ft = mlx5_create_auto_grouped_flow_table(ns, priority, 2382 num_entries, 2383 num_groups, 2384 0, 0); 2385 2386 if (!IS_ERR(ft)) { 2387 prio->refcount = 0; 2388 prio->flow_table = ft; 2389 } else { 2390 err = PTR_ERR(ft); 2391 } 2392 } 2393 2394 return err ? ERR_PTR(err) : prio; 2395 } 2396 2397 static void set_underlay_qp(struct mlx5_ib_dev *dev, 2398 struct mlx5_flow_spec *spec, 2399 u32 underlay_qpn) 2400 { 2401 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, 2402 spec->match_criteria, 2403 misc_parameters); 2404 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, 2405 misc_parameters); 2406 2407 if (underlay_qpn && 2408 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 2409 ft_field_support.bth_dst_qp)) { 2410 MLX5_SET(fte_match_set_misc, 2411 misc_params_v, bth_dst_qp, underlay_qpn); 2412 MLX5_SET(fte_match_set_misc, 2413 misc_params_c, bth_dst_qp, 0xffffff); 2414 } 2415 } 2416 2417 static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev, 2418 struct mlx5_ib_flow_prio *ft_prio, 2419 const struct ib_flow_attr *flow_attr, 2420 struct mlx5_flow_destination *dst, 2421 u32 underlay_qpn) 2422 { 2423 struct mlx5_flow_table *ft = ft_prio->flow_table; 2424 struct mlx5_ib_flow_handler *handler; 2425 struct mlx5_flow_act flow_act = {0}; 2426 struct mlx5_flow_spec *spec; 2427 struct mlx5_flow_destination *rule_dst = dst; 2428 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr); 2429 unsigned int spec_index; 2430 u32 flow_tag = MLX5_FS_DEFAULT_FLOW_TAG; 2431 bool is_drop = false; 2432 int err = 0; 2433 int dest_num = 1; 2434 2435 if (!is_valid_attr(dev->mdev, flow_attr)) 2436 return ERR_PTR(-EINVAL); 2437 2438 spec = kvzalloc(sizeof(*spec), GFP_KERNEL); 2439 handler = kzalloc(sizeof(*handler), GFP_KERNEL); 2440 if (!handler || !spec) { 2441 err = -ENOMEM; 2442 goto free; 2443 } 2444 2445 INIT_LIST_HEAD(&handler->list); 2446 2447 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 2448 err = parse_flow_attr(dev->mdev, spec->match_criteria, 2449 spec->match_value, 2450 ib_flow, &flow_tag, &is_drop); 2451 if (err < 0) 2452 goto free; 2453 2454 ib_flow += ((union ib_flow_spec *)ib_flow)->size; 2455 } 2456 2457 if (!flow_is_multicast_only(flow_attr)) 2458 set_underlay_qp(dev, spec, underlay_qpn); 2459 2460 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria); 2461 if (is_drop) { 2462 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_DROP; 2463 rule_dst = NULL; 2464 dest_num = 0; 2465 } else { 2466 flow_act.action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST : 2467 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO; 2468 } 2469 2470 if (flow_tag != MLX5_FS_DEFAULT_FLOW_TAG && 2471 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 2472 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) { 2473 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n", 2474 flow_tag, flow_attr->type); 2475 err = -EINVAL; 2476 goto free; 2477 } 2478 flow_act.flow_tag = flow_tag; 2479 handler->rule = mlx5_add_flow_rules(ft, spec, 2480 &flow_act, 2481 rule_dst, dest_num); 2482 2483 if (IS_ERR(handler->rule)) { 2484 err = PTR_ERR(handler->rule); 2485 goto free; 2486 } 2487 2488 ft_prio->refcount++; 2489 handler->prio = ft_prio; 2490 2491 ft_prio->flow_table = ft; 2492 free: 2493 if (err) 2494 kfree(handler); 2495 kvfree(spec); 2496 return err ? ERR_PTR(err) : handler; 2497 } 2498 2499 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev, 2500 struct mlx5_ib_flow_prio *ft_prio, 2501 const struct ib_flow_attr *flow_attr, 2502 struct mlx5_flow_destination *dst) 2503 { 2504 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0); 2505 } 2506 2507 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev, 2508 struct mlx5_ib_flow_prio *ft_prio, 2509 struct ib_flow_attr *flow_attr, 2510 struct mlx5_flow_destination *dst) 2511 { 2512 struct mlx5_ib_flow_handler *handler_dst = NULL; 2513 struct mlx5_ib_flow_handler *handler = NULL; 2514 2515 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL); 2516 if (!IS_ERR(handler)) { 2517 handler_dst = create_flow_rule(dev, ft_prio, 2518 flow_attr, dst); 2519 if (IS_ERR(handler_dst)) { 2520 mlx5_del_flow_rules(handler->rule); 2521 ft_prio->refcount--; 2522 kfree(handler); 2523 handler = handler_dst; 2524 } else { 2525 list_add(&handler_dst->list, &handler->list); 2526 } 2527 } 2528 2529 return handler; 2530 } 2531 enum { 2532 LEFTOVERS_MC, 2533 LEFTOVERS_UC, 2534 }; 2535 2536 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev, 2537 struct mlx5_ib_flow_prio *ft_prio, 2538 struct ib_flow_attr *flow_attr, 2539 struct mlx5_flow_destination *dst) 2540 { 2541 struct mlx5_ib_flow_handler *handler_ucast = NULL; 2542 struct mlx5_ib_flow_handler *handler = NULL; 2543 2544 static struct { 2545 struct ib_flow_attr flow_attr; 2546 struct ib_flow_spec_eth eth_flow; 2547 } leftovers_specs[] = { 2548 [LEFTOVERS_MC] = { 2549 .flow_attr = { 2550 .num_of_specs = 1, 2551 .size = sizeof(leftovers_specs[0]) 2552 }, 2553 .eth_flow = { 2554 .type = IB_FLOW_SPEC_ETH, 2555 .size = sizeof(struct ib_flow_spec_eth), 2556 .mask = {.dst_mac = {0x1} }, 2557 .val = {.dst_mac = {0x1} } 2558 } 2559 }, 2560 [LEFTOVERS_UC] = { 2561 .flow_attr = { 2562 .num_of_specs = 1, 2563 .size = sizeof(leftovers_specs[0]) 2564 }, 2565 .eth_flow = { 2566 .type = IB_FLOW_SPEC_ETH, 2567 .size = sizeof(struct ib_flow_spec_eth), 2568 .mask = {.dst_mac = {0x1} }, 2569 .val = {.dst_mac = {} } 2570 } 2571 } 2572 }; 2573 2574 handler = create_flow_rule(dev, ft_prio, 2575 &leftovers_specs[LEFTOVERS_MC].flow_attr, 2576 dst); 2577 if (!IS_ERR(handler) && 2578 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) { 2579 handler_ucast = create_flow_rule(dev, ft_prio, 2580 &leftovers_specs[LEFTOVERS_UC].flow_attr, 2581 dst); 2582 if (IS_ERR(handler_ucast)) { 2583 mlx5_del_flow_rules(handler->rule); 2584 ft_prio->refcount--; 2585 kfree(handler); 2586 handler = handler_ucast; 2587 } else { 2588 list_add(&handler_ucast->list, &handler->list); 2589 } 2590 } 2591 2592 return handler; 2593 } 2594 2595 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev, 2596 struct mlx5_ib_flow_prio *ft_rx, 2597 struct mlx5_ib_flow_prio *ft_tx, 2598 struct mlx5_flow_destination *dst) 2599 { 2600 struct mlx5_ib_flow_handler *handler_rx; 2601 struct mlx5_ib_flow_handler *handler_tx; 2602 int err; 2603 static const struct ib_flow_attr flow_attr = { 2604 .num_of_specs = 0, 2605 .size = sizeof(flow_attr) 2606 }; 2607 2608 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst); 2609 if (IS_ERR(handler_rx)) { 2610 err = PTR_ERR(handler_rx); 2611 goto err; 2612 } 2613 2614 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst); 2615 if (IS_ERR(handler_tx)) { 2616 err = PTR_ERR(handler_tx); 2617 goto err_tx; 2618 } 2619 2620 list_add(&handler_tx->list, &handler_rx->list); 2621 2622 return handler_rx; 2623 2624 err_tx: 2625 mlx5_del_flow_rules(handler_rx->rule); 2626 ft_rx->refcount--; 2627 kfree(handler_rx); 2628 err: 2629 return ERR_PTR(err); 2630 } 2631 2632 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp, 2633 struct ib_flow_attr *flow_attr, 2634 int domain) 2635 { 2636 struct mlx5_ib_dev *dev = to_mdev(qp->device); 2637 struct mlx5_ib_qp *mqp = to_mqp(qp); 2638 struct mlx5_ib_flow_handler *handler = NULL; 2639 struct mlx5_flow_destination *dst = NULL; 2640 struct mlx5_ib_flow_prio *ft_prio_tx = NULL; 2641 struct mlx5_ib_flow_prio *ft_prio; 2642 int err; 2643 int underlay_qpn; 2644 2645 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) 2646 return ERR_PTR(-ENOMEM); 2647 2648 if (domain != IB_FLOW_DOMAIN_USER || 2649 flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) || 2650 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP)) 2651 return ERR_PTR(-EINVAL); 2652 2653 dst = kzalloc(sizeof(*dst), GFP_KERNEL); 2654 if (!dst) 2655 return ERR_PTR(-ENOMEM); 2656 2657 mutex_lock(&dev->flow_db.lock); 2658 2659 ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX); 2660 if (IS_ERR(ft_prio)) { 2661 err = PTR_ERR(ft_prio); 2662 goto unlock; 2663 } 2664 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 2665 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX); 2666 if (IS_ERR(ft_prio_tx)) { 2667 err = PTR_ERR(ft_prio_tx); 2668 ft_prio_tx = NULL; 2669 goto destroy_ft; 2670 } 2671 } 2672 2673 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR; 2674 if (mqp->flags & MLX5_IB_QP_RSS) 2675 dst->tir_num = mqp->rss_qp.tirn; 2676 else 2677 dst->tir_num = mqp->raw_packet_qp.rq.tirn; 2678 2679 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 2680 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) { 2681 handler = create_dont_trap_rule(dev, ft_prio, 2682 flow_attr, dst); 2683 } else { 2684 underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ? 2685 mqp->underlay_qpn : 0; 2686 handler = _create_flow_rule(dev, ft_prio, flow_attr, 2687 dst, underlay_qpn); 2688 } 2689 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 2690 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 2691 handler = create_leftovers_rule(dev, ft_prio, flow_attr, 2692 dst); 2693 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 2694 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst); 2695 } else { 2696 err = -EINVAL; 2697 goto destroy_ft; 2698 } 2699 2700 if (IS_ERR(handler)) { 2701 err = PTR_ERR(handler); 2702 handler = NULL; 2703 goto destroy_ft; 2704 } 2705 2706 mutex_unlock(&dev->flow_db.lock); 2707 kfree(dst); 2708 2709 return &handler->ibflow; 2710 2711 destroy_ft: 2712 put_flow_table(dev, ft_prio, false); 2713 if (ft_prio_tx) 2714 put_flow_table(dev, ft_prio_tx, false); 2715 unlock: 2716 mutex_unlock(&dev->flow_db.lock); 2717 kfree(dst); 2718 kfree(handler); 2719 return ERR_PTR(err); 2720 } 2721 2722 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2723 { 2724 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2725 struct mlx5_ib_qp *mqp = to_mqp(ibqp); 2726 int err; 2727 2728 if (mqp->flags & MLX5_IB_QP_UNDERLAY) { 2729 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n"); 2730 return -EOPNOTSUPP; 2731 } 2732 2733 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num); 2734 if (err) 2735 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 2736 ibqp->qp_num, gid->raw); 2737 2738 return err; 2739 } 2740 2741 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2742 { 2743 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2744 int err; 2745 2746 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num); 2747 if (err) 2748 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 2749 ibqp->qp_num, gid->raw); 2750 2751 return err; 2752 } 2753 2754 static int init_node_data(struct mlx5_ib_dev *dev) 2755 { 2756 int err; 2757 2758 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 2759 if (err) 2760 return err; 2761 2762 dev->mdev->rev_id = dev->mdev->pdev->revision; 2763 2764 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 2765 } 2766 2767 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr, 2768 char *buf) 2769 { 2770 struct mlx5_ib_dev *dev = 2771 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2772 2773 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages); 2774 } 2775 2776 static ssize_t show_reg_pages(struct device *device, 2777 struct device_attribute *attr, char *buf) 2778 { 2779 struct mlx5_ib_dev *dev = 2780 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2781 2782 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 2783 } 2784 2785 static ssize_t show_hca(struct device *device, struct device_attribute *attr, 2786 char *buf) 2787 { 2788 struct mlx5_ib_dev *dev = 2789 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2790 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device); 2791 } 2792 2793 static ssize_t show_rev(struct device *device, struct device_attribute *attr, 2794 char *buf) 2795 { 2796 struct mlx5_ib_dev *dev = 2797 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2798 return sprintf(buf, "%x\n", dev->mdev->rev_id); 2799 } 2800 2801 static ssize_t show_board(struct device *device, struct device_attribute *attr, 2802 char *buf) 2803 { 2804 struct mlx5_ib_dev *dev = 2805 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2806 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 2807 dev->mdev->board_id); 2808 } 2809 2810 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL); 2811 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL); 2812 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL); 2813 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL); 2814 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL); 2815 2816 static struct device_attribute *mlx5_class_attributes[] = { 2817 &dev_attr_hw_rev, 2818 &dev_attr_hca_type, 2819 &dev_attr_board_id, 2820 &dev_attr_fw_pages, 2821 &dev_attr_reg_pages, 2822 }; 2823 2824 static void pkey_change_handler(struct work_struct *work) 2825 { 2826 struct mlx5_ib_port_resources *ports = 2827 container_of(work, struct mlx5_ib_port_resources, 2828 pkey_change_work); 2829 2830 mutex_lock(&ports->devr->mutex); 2831 mlx5_ib_gsi_pkey_change(ports->gsi); 2832 mutex_unlock(&ports->devr->mutex); 2833 } 2834 2835 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 2836 { 2837 struct mlx5_ib_qp *mqp; 2838 struct mlx5_ib_cq *send_mcq, *recv_mcq; 2839 struct mlx5_core_cq *mcq; 2840 struct list_head cq_armed_list; 2841 unsigned long flags_qp; 2842 unsigned long flags_cq; 2843 unsigned long flags; 2844 2845 INIT_LIST_HEAD(&cq_armed_list); 2846 2847 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 2848 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 2849 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 2850 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 2851 if (mqp->sq.tail != mqp->sq.head) { 2852 send_mcq = to_mcq(mqp->ibqp.send_cq); 2853 spin_lock_irqsave(&send_mcq->lock, flags_cq); 2854 if (send_mcq->mcq.comp && 2855 mqp->ibqp.send_cq->comp_handler) { 2856 if (!send_mcq->mcq.reset_notify_added) { 2857 send_mcq->mcq.reset_notify_added = 1; 2858 list_add_tail(&send_mcq->mcq.reset_notify, 2859 &cq_armed_list); 2860 } 2861 } 2862 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 2863 } 2864 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 2865 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 2866 /* no handling is needed for SRQ */ 2867 if (!mqp->ibqp.srq) { 2868 if (mqp->rq.tail != mqp->rq.head) { 2869 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 2870 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 2871 if (recv_mcq->mcq.comp && 2872 mqp->ibqp.recv_cq->comp_handler) { 2873 if (!recv_mcq->mcq.reset_notify_added) { 2874 recv_mcq->mcq.reset_notify_added = 1; 2875 list_add_tail(&recv_mcq->mcq.reset_notify, 2876 &cq_armed_list); 2877 } 2878 } 2879 spin_unlock_irqrestore(&recv_mcq->lock, 2880 flags_cq); 2881 } 2882 } 2883 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 2884 } 2885 /*At that point all inflight post send were put to be executed as of we 2886 * lock/unlock above locks Now need to arm all involved CQs. 2887 */ 2888 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 2889 mcq->comp(mcq); 2890 } 2891 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 2892 } 2893 2894 static void delay_drop_handler(struct work_struct *work) 2895 { 2896 int err; 2897 struct mlx5_ib_delay_drop *delay_drop = 2898 container_of(work, struct mlx5_ib_delay_drop, 2899 delay_drop_work); 2900 2901 atomic_inc(&delay_drop->events_cnt); 2902 2903 mutex_lock(&delay_drop->lock); 2904 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev, 2905 delay_drop->timeout); 2906 if (err) { 2907 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n", 2908 delay_drop->timeout); 2909 delay_drop->activate = false; 2910 } 2911 mutex_unlock(&delay_drop->lock); 2912 } 2913 2914 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context, 2915 enum mlx5_dev_event event, unsigned long param) 2916 { 2917 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context; 2918 struct ib_event ibev; 2919 bool fatal = false; 2920 u8 port = 0; 2921 2922 switch (event) { 2923 case MLX5_DEV_EVENT_SYS_ERROR: 2924 ibev.event = IB_EVENT_DEVICE_FATAL; 2925 mlx5_ib_handle_internal_error(ibdev); 2926 fatal = true; 2927 break; 2928 2929 case MLX5_DEV_EVENT_PORT_UP: 2930 case MLX5_DEV_EVENT_PORT_DOWN: 2931 case MLX5_DEV_EVENT_PORT_INITIALIZED: 2932 port = (u8)param; 2933 2934 /* In RoCE, port up/down events are handled in 2935 * mlx5_netdev_event(). 2936 */ 2937 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2938 IB_LINK_LAYER_ETHERNET) 2939 return; 2940 2941 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ? 2942 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 2943 break; 2944 2945 case MLX5_DEV_EVENT_LID_CHANGE: 2946 ibev.event = IB_EVENT_LID_CHANGE; 2947 port = (u8)param; 2948 break; 2949 2950 case MLX5_DEV_EVENT_PKEY_CHANGE: 2951 ibev.event = IB_EVENT_PKEY_CHANGE; 2952 port = (u8)param; 2953 2954 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 2955 break; 2956 2957 case MLX5_DEV_EVENT_GUID_CHANGE: 2958 ibev.event = IB_EVENT_GID_CHANGE; 2959 port = (u8)param; 2960 break; 2961 2962 case MLX5_DEV_EVENT_CLIENT_REREG: 2963 ibev.event = IB_EVENT_CLIENT_REREGISTER; 2964 port = (u8)param; 2965 break; 2966 case MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT: 2967 schedule_work(&ibdev->delay_drop.delay_drop_work); 2968 goto out; 2969 default: 2970 goto out; 2971 } 2972 2973 ibev.device = &ibdev->ib_dev; 2974 ibev.element.port_num = port; 2975 2976 if (port < 1 || port > ibdev->num_ports) { 2977 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port); 2978 goto out; 2979 } 2980 2981 if (ibdev->ib_active) 2982 ib_dispatch_event(&ibev); 2983 2984 if (fatal) 2985 ibdev->ib_active = false; 2986 2987 out: 2988 return; 2989 } 2990 2991 static int set_has_smi_cap(struct mlx5_ib_dev *dev) 2992 { 2993 struct mlx5_hca_vport_context vport_ctx; 2994 int err; 2995 int port; 2996 2997 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) { 2998 dev->mdev->port_caps[port - 1].has_smi = false; 2999 if (MLX5_CAP_GEN(dev->mdev, port_type) == 3000 MLX5_CAP_PORT_TYPE_IB) { 3001 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) { 3002 err = mlx5_query_hca_vport_context(dev->mdev, 0, 3003 port, 0, 3004 &vport_ctx); 3005 if (err) { 3006 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n", 3007 port, err); 3008 return err; 3009 } 3010 dev->mdev->port_caps[port - 1].has_smi = 3011 vport_ctx.has_smi; 3012 } else { 3013 dev->mdev->port_caps[port - 1].has_smi = true; 3014 } 3015 } 3016 } 3017 return 0; 3018 } 3019 3020 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 3021 { 3022 int port; 3023 3024 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) 3025 mlx5_query_ext_port_caps(dev, port); 3026 } 3027 3028 static int get_port_caps(struct mlx5_ib_dev *dev) 3029 { 3030 struct ib_device_attr *dprops = NULL; 3031 struct ib_port_attr *pprops = NULL; 3032 int err = -ENOMEM; 3033 int port; 3034 struct ib_udata uhw = {.inlen = 0, .outlen = 0}; 3035 3036 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL); 3037 if (!pprops) 3038 goto out; 3039 3040 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL); 3041 if (!dprops) 3042 goto out; 3043 3044 err = set_has_smi_cap(dev); 3045 if (err) 3046 goto out; 3047 3048 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw); 3049 if (err) { 3050 mlx5_ib_warn(dev, "query_device failed %d\n", err); 3051 goto out; 3052 } 3053 3054 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) { 3055 memset(pprops, 0, sizeof(*pprops)); 3056 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops); 3057 if (err) { 3058 mlx5_ib_warn(dev, "query_port %d failed %d\n", 3059 port, err); 3060 break; 3061 } 3062 dev->mdev->port_caps[port - 1].pkey_table_len = 3063 dprops->max_pkeys; 3064 dev->mdev->port_caps[port - 1].gid_table_len = 3065 pprops->gid_tbl_len; 3066 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n", 3067 dprops->max_pkeys, pprops->gid_tbl_len); 3068 } 3069 3070 out: 3071 kfree(pprops); 3072 kfree(dprops); 3073 3074 return err; 3075 } 3076 3077 static void destroy_umrc_res(struct mlx5_ib_dev *dev) 3078 { 3079 int err; 3080 3081 err = mlx5_mr_cache_cleanup(dev); 3082 if (err) 3083 mlx5_ib_warn(dev, "mr cache cleanup failed\n"); 3084 3085 mlx5_ib_destroy_qp(dev->umrc.qp); 3086 ib_free_cq(dev->umrc.cq); 3087 ib_dealloc_pd(dev->umrc.pd); 3088 } 3089 3090 enum { 3091 MAX_UMR_WR = 128, 3092 }; 3093 3094 static int create_umr_res(struct mlx5_ib_dev *dev) 3095 { 3096 struct ib_qp_init_attr *init_attr = NULL; 3097 struct ib_qp_attr *attr = NULL; 3098 struct ib_pd *pd; 3099 struct ib_cq *cq; 3100 struct ib_qp *qp; 3101 int ret; 3102 3103 attr = kzalloc(sizeof(*attr), GFP_KERNEL); 3104 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL); 3105 if (!attr || !init_attr) { 3106 ret = -ENOMEM; 3107 goto error_0; 3108 } 3109 3110 pd = ib_alloc_pd(&dev->ib_dev, 0); 3111 if (IS_ERR(pd)) { 3112 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n"); 3113 ret = PTR_ERR(pd); 3114 goto error_0; 3115 } 3116 3117 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ); 3118 if (IS_ERR(cq)) { 3119 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n"); 3120 ret = PTR_ERR(cq); 3121 goto error_2; 3122 } 3123 3124 init_attr->send_cq = cq; 3125 init_attr->recv_cq = cq; 3126 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR; 3127 init_attr->cap.max_send_wr = MAX_UMR_WR; 3128 init_attr->cap.max_send_sge = 1; 3129 init_attr->qp_type = MLX5_IB_QPT_REG_UMR; 3130 init_attr->port_num = 1; 3131 qp = mlx5_ib_create_qp(pd, init_attr, NULL); 3132 if (IS_ERR(qp)) { 3133 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n"); 3134 ret = PTR_ERR(qp); 3135 goto error_3; 3136 } 3137 qp->device = &dev->ib_dev; 3138 qp->real_qp = qp; 3139 qp->uobject = NULL; 3140 qp->qp_type = MLX5_IB_QPT_REG_UMR; 3141 3142 attr->qp_state = IB_QPS_INIT; 3143 attr->port_num = 1; 3144 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX | 3145 IB_QP_PORT, NULL); 3146 if (ret) { 3147 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n"); 3148 goto error_4; 3149 } 3150 3151 memset(attr, 0, sizeof(*attr)); 3152 attr->qp_state = IB_QPS_RTR; 3153 attr->path_mtu = IB_MTU_256; 3154 3155 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 3156 if (ret) { 3157 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n"); 3158 goto error_4; 3159 } 3160 3161 memset(attr, 0, sizeof(*attr)); 3162 attr->qp_state = IB_QPS_RTS; 3163 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 3164 if (ret) { 3165 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n"); 3166 goto error_4; 3167 } 3168 3169 dev->umrc.qp = qp; 3170 dev->umrc.cq = cq; 3171 dev->umrc.pd = pd; 3172 3173 sema_init(&dev->umrc.sem, MAX_UMR_WR); 3174 ret = mlx5_mr_cache_init(dev); 3175 if (ret) { 3176 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 3177 goto error_4; 3178 } 3179 3180 kfree(attr); 3181 kfree(init_attr); 3182 3183 return 0; 3184 3185 error_4: 3186 mlx5_ib_destroy_qp(qp); 3187 3188 error_3: 3189 ib_free_cq(cq); 3190 3191 error_2: 3192 ib_dealloc_pd(pd); 3193 3194 error_0: 3195 kfree(attr); 3196 kfree(init_attr); 3197 return ret; 3198 } 3199 3200 static u8 mlx5_get_umr_fence(u8 umr_fence_cap) 3201 { 3202 switch (umr_fence_cap) { 3203 case MLX5_CAP_UMR_FENCE_NONE: 3204 return MLX5_FENCE_MODE_NONE; 3205 case MLX5_CAP_UMR_FENCE_SMALL: 3206 return MLX5_FENCE_MODE_INITIATOR_SMALL; 3207 default: 3208 return MLX5_FENCE_MODE_STRONG_ORDERING; 3209 } 3210 } 3211 3212 static int create_dev_resources(struct mlx5_ib_resources *devr) 3213 { 3214 struct ib_srq_init_attr attr; 3215 struct mlx5_ib_dev *dev; 3216 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 3217 int port; 3218 int ret = 0; 3219 3220 dev = container_of(devr, struct mlx5_ib_dev, devr); 3221 3222 mutex_init(&devr->mutex); 3223 3224 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL); 3225 if (IS_ERR(devr->p0)) { 3226 ret = PTR_ERR(devr->p0); 3227 goto error0; 3228 } 3229 devr->p0->device = &dev->ib_dev; 3230 devr->p0->uobject = NULL; 3231 atomic_set(&devr->p0->usecnt, 0); 3232 3233 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL); 3234 if (IS_ERR(devr->c0)) { 3235 ret = PTR_ERR(devr->c0); 3236 goto error1; 3237 } 3238 devr->c0->device = &dev->ib_dev; 3239 devr->c0->uobject = NULL; 3240 devr->c0->comp_handler = NULL; 3241 devr->c0->event_handler = NULL; 3242 devr->c0->cq_context = NULL; 3243 atomic_set(&devr->c0->usecnt, 0); 3244 3245 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 3246 if (IS_ERR(devr->x0)) { 3247 ret = PTR_ERR(devr->x0); 3248 goto error2; 3249 } 3250 devr->x0->device = &dev->ib_dev; 3251 devr->x0->inode = NULL; 3252 atomic_set(&devr->x0->usecnt, 0); 3253 mutex_init(&devr->x0->tgt_qp_mutex); 3254 INIT_LIST_HEAD(&devr->x0->tgt_qp_list); 3255 3256 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 3257 if (IS_ERR(devr->x1)) { 3258 ret = PTR_ERR(devr->x1); 3259 goto error3; 3260 } 3261 devr->x1->device = &dev->ib_dev; 3262 devr->x1->inode = NULL; 3263 atomic_set(&devr->x1->usecnt, 0); 3264 mutex_init(&devr->x1->tgt_qp_mutex); 3265 INIT_LIST_HEAD(&devr->x1->tgt_qp_list); 3266 3267 memset(&attr, 0, sizeof(attr)); 3268 attr.attr.max_sge = 1; 3269 attr.attr.max_wr = 1; 3270 attr.srq_type = IB_SRQT_XRC; 3271 attr.ext.cq = devr->c0; 3272 attr.ext.xrc.xrcd = devr->x0; 3273 3274 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 3275 if (IS_ERR(devr->s0)) { 3276 ret = PTR_ERR(devr->s0); 3277 goto error4; 3278 } 3279 devr->s0->device = &dev->ib_dev; 3280 devr->s0->pd = devr->p0; 3281 devr->s0->uobject = NULL; 3282 devr->s0->event_handler = NULL; 3283 devr->s0->srq_context = NULL; 3284 devr->s0->srq_type = IB_SRQT_XRC; 3285 devr->s0->ext.xrc.xrcd = devr->x0; 3286 devr->s0->ext.cq = devr->c0; 3287 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt); 3288 atomic_inc(&devr->s0->ext.cq->usecnt); 3289 atomic_inc(&devr->p0->usecnt); 3290 atomic_set(&devr->s0->usecnt, 0); 3291 3292 memset(&attr, 0, sizeof(attr)); 3293 attr.attr.max_sge = 1; 3294 attr.attr.max_wr = 1; 3295 attr.srq_type = IB_SRQT_BASIC; 3296 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 3297 if (IS_ERR(devr->s1)) { 3298 ret = PTR_ERR(devr->s1); 3299 goto error5; 3300 } 3301 devr->s1->device = &dev->ib_dev; 3302 devr->s1->pd = devr->p0; 3303 devr->s1->uobject = NULL; 3304 devr->s1->event_handler = NULL; 3305 devr->s1->srq_context = NULL; 3306 devr->s1->srq_type = IB_SRQT_BASIC; 3307 devr->s1->ext.cq = devr->c0; 3308 atomic_inc(&devr->p0->usecnt); 3309 atomic_set(&devr->s1->usecnt, 0); 3310 3311 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) { 3312 INIT_WORK(&devr->ports[port].pkey_change_work, 3313 pkey_change_handler); 3314 devr->ports[port].devr = devr; 3315 } 3316 3317 return 0; 3318 3319 error5: 3320 mlx5_ib_destroy_srq(devr->s0); 3321 error4: 3322 mlx5_ib_dealloc_xrcd(devr->x1); 3323 error3: 3324 mlx5_ib_dealloc_xrcd(devr->x0); 3325 error2: 3326 mlx5_ib_destroy_cq(devr->c0); 3327 error1: 3328 mlx5_ib_dealloc_pd(devr->p0); 3329 error0: 3330 return ret; 3331 } 3332 3333 static void destroy_dev_resources(struct mlx5_ib_resources *devr) 3334 { 3335 struct mlx5_ib_dev *dev = 3336 container_of(devr, struct mlx5_ib_dev, devr); 3337 int port; 3338 3339 mlx5_ib_destroy_srq(devr->s1); 3340 mlx5_ib_destroy_srq(devr->s0); 3341 mlx5_ib_dealloc_xrcd(devr->x0); 3342 mlx5_ib_dealloc_xrcd(devr->x1); 3343 mlx5_ib_destroy_cq(devr->c0); 3344 mlx5_ib_dealloc_pd(devr->p0); 3345 3346 /* Make sure no change P_Key work items are still executing */ 3347 for (port = 0; port < dev->num_ports; ++port) 3348 cancel_work_sync(&devr->ports[port].pkey_change_work); 3349 } 3350 3351 static u32 get_core_cap_flags(struct ib_device *ibdev) 3352 { 3353 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3354 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 3355 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 3356 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 3357 u32 ret = 0; 3358 3359 if (ll == IB_LINK_LAYER_INFINIBAND) 3360 return RDMA_CORE_PORT_IBA_IB; 3361 3362 ret = RDMA_CORE_PORT_RAW_PACKET; 3363 3364 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 3365 return ret; 3366 3367 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 3368 return ret; 3369 3370 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 3371 ret |= RDMA_CORE_PORT_IBA_ROCE; 3372 3373 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 3374 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 3375 3376 return ret; 3377 } 3378 3379 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num, 3380 struct ib_port_immutable *immutable) 3381 { 3382 struct ib_port_attr attr; 3383 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3384 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num); 3385 int err; 3386 3387 immutable->core_cap_flags = get_core_cap_flags(ibdev); 3388 3389 err = ib_query_port(ibdev, port_num, &attr); 3390 if (err) 3391 return err; 3392 3393 immutable->pkey_tbl_len = attr.pkey_tbl_len; 3394 immutable->gid_tbl_len = attr.gid_tbl_len; 3395 immutable->core_cap_flags = get_core_cap_flags(ibdev); 3396 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce)) 3397 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 3398 3399 return 0; 3400 } 3401 3402 static void get_dev_fw_str(struct ib_device *ibdev, char *str) 3403 { 3404 struct mlx5_ib_dev *dev = 3405 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 3406 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d", 3407 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev), 3408 fw_rev_sub(dev->mdev)); 3409 } 3410 3411 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev) 3412 { 3413 struct mlx5_core_dev *mdev = dev->mdev; 3414 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev, 3415 MLX5_FLOW_NAMESPACE_LAG); 3416 struct mlx5_flow_table *ft; 3417 int err; 3418 3419 if (!ns || !mlx5_lag_is_active(mdev)) 3420 return 0; 3421 3422 err = mlx5_cmd_create_vport_lag(mdev); 3423 if (err) 3424 return err; 3425 3426 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0); 3427 if (IS_ERR(ft)) { 3428 err = PTR_ERR(ft); 3429 goto err_destroy_vport_lag; 3430 } 3431 3432 dev->flow_db.lag_demux_ft = ft; 3433 return 0; 3434 3435 err_destroy_vport_lag: 3436 mlx5_cmd_destroy_vport_lag(mdev); 3437 return err; 3438 } 3439 3440 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev) 3441 { 3442 struct mlx5_core_dev *mdev = dev->mdev; 3443 3444 if (dev->flow_db.lag_demux_ft) { 3445 mlx5_destroy_flow_table(dev->flow_db.lag_demux_ft); 3446 dev->flow_db.lag_demux_ft = NULL; 3447 3448 mlx5_cmd_destroy_vport_lag(mdev); 3449 } 3450 } 3451 3452 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev) 3453 { 3454 int err; 3455 3456 dev->roce.nb.notifier_call = mlx5_netdev_event; 3457 err = register_netdevice_notifier(&dev->roce.nb); 3458 if (err) { 3459 dev->roce.nb.notifier_call = NULL; 3460 return err; 3461 } 3462 3463 return 0; 3464 } 3465 3466 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev) 3467 { 3468 if (dev->roce.nb.notifier_call) { 3469 unregister_netdevice_notifier(&dev->roce.nb); 3470 dev->roce.nb.notifier_call = NULL; 3471 } 3472 } 3473 3474 static int mlx5_enable_eth(struct mlx5_ib_dev *dev) 3475 { 3476 int err; 3477 3478 err = mlx5_add_netdev_notifier(dev); 3479 if (err) 3480 return err; 3481 3482 if (MLX5_CAP_GEN(dev->mdev, roce)) { 3483 err = mlx5_nic_vport_enable_roce(dev->mdev); 3484 if (err) 3485 goto err_unregister_netdevice_notifier; 3486 } 3487 3488 err = mlx5_eth_lag_init(dev); 3489 if (err) 3490 goto err_disable_roce; 3491 3492 return 0; 3493 3494 err_disable_roce: 3495 if (MLX5_CAP_GEN(dev->mdev, roce)) 3496 mlx5_nic_vport_disable_roce(dev->mdev); 3497 3498 err_unregister_netdevice_notifier: 3499 mlx5_remove_netdev_notifier(dev); 3500 return err; 3501 } 3502 3503 static void mlx5_disable_eth(struct mlx5_ib_dev *dev) 3504 { 3505 mlx5_eth_lag_cleanup(dev); 3506 if (MLX5_CAP_GEN(dev->mdev, roce)) 3507 mlx5_nic_vport_disable_roce(dev->mdev); 3508 } 3509 3510 struct mlx5_ib_counter { 3511 const char *name; 3512 size_t offset; 3513 }; 3514 3515 #define INIT_Q_COUNTER(_name) \ 3516 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)} 3517 3518 static const struct mlx5_ib_counter basic_q_cnts[] = { 3519 INIT_Q_COUNTER(rx_write_requests), 3520 INIT_Q_COUNTER(rx_read_requests), 3521 INIT_Q_COUNTER(rx_atomic_requests), 3522 INIT_Q_COUNTER(out_of_buffer), 3523 }; 3524 3525 static const struct mlx5_ib_counter out_of_seq_q_cnts[] = { 3526 INIT_Q_COUNTER(out_of_sequence), 3527 }; 3528 3529 static const struct mlx5_ib_counter retrans_q_cnts[] = { 3530 INIT_Q_COUNTER(duplicate_request), 3531 INIT_Q_COUNTER(rnr_nak_retry_err), 3532 INIT_Q_COUNTER(packet_seq_err), 3533 INIT_Q_COUNTER(implied_nak_seq_err), 3534 INIT_Q_COUNTER(local_ack_timeout_err), 3535 }; 3536 3537 #define INIT_CONG_COUNTER(_name) \ 3538 { .name = #_name, .offset = \ 3539 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)} 3540 3541 static const struct mlx5_ib_counter cong_cnts[] = { 3542 INIT_CONG_COUNTER(rp_cnp_ignored), 3543 INIT_CONG_COUNTER(rp_cnp_handled), 3544 INIT_CONG_COUNTER(np_ecn_marked_roce_packets), 3545 INIT_CONG_COUNTER(np_cnp_sent), 3546 }; 3547 3548 static const struct mlx5_ib_counter extended_err_cnts[] = { 3549 INIT_Q_COUNTER(resp_local_length_error), 3550 INIT_Q_COUNTER(resp_cqe_error), 3551 INIT_Q_COUNTER(req_cqe_error), 3552 INIT_Q_COUNTER(req_remote_invalid_request), 3553 INIT_Q_COUNTER(req_remote_access_errors), 3554 INIT_Q_COUNTER(resp_remote_access_errors), 3555 INIT_Q_COUNTER(resp_cqe_flush_error), 3556 INIT_Q_COUNTER(req_cqe_flush_error), 3557 }; 3558 3559 static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev) 3560 { 3561 unsigned int i; 3562 3563 for (i = 0; i < dev->num_ports; i++) { 3564 mlx5_core_dealloc_q_counter(dev->mdev, 3565 dev->port[i].cnts.set_id); 3566 kfree(dev->port[i].cnts.names); 3567 kfree(dev->port[i].cnts.offsets); 3568 } 3569 } 3570 3571 static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev, 3572 struct mlx5_ib_counters *cnts) 3573 { 3574 u32 num_counters; 3575 3576 num_counters = ARRAY_SIZE(basic_q_cnts); 3577 3578 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) 3579 num_counters += ARRAY_SIZE(out_of_seq_q_cnts); 3580 3581 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) 3582 num_counters += ARRAY_SIZE(retrans_q_cnts); 3583 3584 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) 3585 num_counters += ARRAY_SIZE(extended_err_cnts); 3586 3587 cnts->num_q_counters = num_counters; 3588 3589 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 3590 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts); 3591 num_counters += ARRAY_SIZE(cong_cnts); 3592 } 3593 3594 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL); 3595 if (!cnts->names) 3596 return -ENOMEM; 3597 3598 cnts->offsets = kcalloc(num_counters, 3599 sizeof(cnts->offsets), GFP_KERNEL); 3600 if (!cnts->offsets) 3601 goto err_names; 3602 3603 return 0; 3604 3605 err_names: 3606 kfree(cnts->names); 3607 return -ENOMEM; 3608 } 3609 3610 static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev, 3611 const char **names, 3612 size_t *offsets) 3613 { 3614 int i; 3615 int j = 0; 3616 3617 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) { 3618 names[j] = basic_q_cnts[i].name; 3619 offsets[j] = basic_q_cnts[i].offset; 3620 } 3621 3622 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) { 3623 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) { 3624 names[j] = out_of_seq_q_cnts[i].name; 3625 offsets[j] = out_of_seq_q_cnts[i].offset; 3626 } 3627 } 3628 3629 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) { 3630 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) { 3631 names[j] = retrans_q_cnts[i].name; 3632 offsets[j] = retrans_q_cnts[i].offset; 3633 } 3634 } 3635 3636 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) { 3637 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) { 3638 names[j] = extended_err_cnts[i].name; 3639 offsets[j] = extended_err_cnts[i].offset; 3640 } 3641 } 3642 3643 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 3644 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) { 3645 names[j] = cong_cnts[i].name; 3646 offsets[j] = cong_cnts[i].offset; 3647 } 3648 } 3649 } 3650 3651 static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev) 3652 { 3653 int i; 3654 int ret; 3655 3656 for (i = 0; i < dev->num_ports; i++) { 3657 struct mlx5_ib_port *port = &dev->port[i]; 3658 3659 ret = mlx5_core_alloc_q_counter(dev->mdev, 3660 &port->cnts.set_id); 3661 if (ret) { 3662 mlx5_ib_warn(dev, 3663 "couldn't allocate queue counter for port %d, err %d\n", 3664 i + 1, ret); 3665 goto dealloc_counters; 3666 } 3667 3668 ret = __mlx5_ib_alloc_counters(dev, &port->cnts); 3669 if (ret) 3670 goto dealloc_counters; 3671 3672 mlx5_ib_fill_counters(dev, port->cnts.names, 3673 port->cnts.offsets); 3674 } 3675 3676 return 0; 3677 3678 dealloc_counters: 3679 while (--i >= 0) 3680 mlx5_core_dealloc_q_counter(dev->mdev, 3681 dev->port[i].cnts.set_id); 3682 3683 return ret; 3684 } 3685 3686 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev, 3687 u8 port_num) 3688 { 3689 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3690 struct mlx5_ib_port *port = &dev->port[port_num - 1]; 3691 3692 /* We support only per port stats */ 3693 if (port_num == 0) 3694 return NULL; 3695 3696 return rdma_alloc_hw_stats_struct(port->cnts.names, 3697 port->cnts.num_q_counters + 3698 port->cnts.num_cong_counters, 3699 RDMA_HW_STATS_DEFAULT_LIFESPAN); 3700 } 3701 3702 static int mlx5_ib_query_q_counters(struct mlx5_ib_dev *dev, 3703 struct mlx5_ib_port *port, 3704 struct rdma_hw_stats *stats) 3705 { 3706 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out); 3707 void *out; 3708 __be32 val; 3709 int ret, i; 3710 3711 out = kvzalloc(outlen, GFP_KERNEL); 3712 if (!out) 3713 return -ENOMEM; 3714 3715 ret = mlx5_core_query_q_counter(dev->mdev, 3716 port->cnts.set_id, 0, 3717 out, outlen); 3718 if (ret) 3719 goto free; 3720 3721 for (i = 0; i < port->cnts.num_q_counters; i++) { 3722 val = *(__be32 *)(out + port->cnts.offsets[i]); 3723 stats->value[i] = (u64)be32_to_cpu(val); 3724 } 3725 3726 free: 3727 kvfree(out); 3728 return ret; 3729 } 3730 3731 static int mlx5_ib_query_cong_counters(struct mlx5_ib_dev *dev, 3732 struct mlx5_ib_port *port, 3733 struct rdma_hw_stats *stats) 3734 { 3735 int outlen = MLX5_ST_SZ_BYTES(query_cong_statistics_out); 3736 void *out; 3737 int ret, i; 3738 int offset = port->cnts.num_q_counters; 3739 3740 out = kvzalloc(outlen, GFP_KERNEL); 3741 if (!out) 3742 return -ENOMEM; 3743 3744 ret = mlx5_cmd_query_cong_counter(dev->mdev, false, out, outlen); 3745 if (ret) 3746 goto free; 3747 3748 for (i = 0; i < port->cnts.num_cong_counters; i++) { 3749 stats->value[i + offset] = 3750 be64_to_cpup((__be64 *)(out + 3751 port->cnts.offsets[i + offset])); 3752 } 3753 3754 free: 3755 kvfree(out); 3756 return ret; 3757 } 3758 3759 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev, 3760 struct rdma_hw_stats *stats, 3761 u8 port_num, int index) 3762 { 3763 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3764 struct mlx5_ib_port *port = &dev->port[port_num - 1]; 3765 int ret, num_counters; 3766 3767 if (!stats) 3768 return -EINVAL; 3769 3770 ret = mlx5_ib_query_q_counters(dev, port, stats); 3771 if (ret) 3772 return ret; 3773 num_counters = port->cnts.num_q_counters; 3774 3775 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 3776 ret = mlx5_ib_query_cong_counters(dev, port, stats); 3777 if (ret) 3778 return ret; 3779 num_counters += port->cnts.num_cong_counters; 3780 } 3781 3782 return num_counters; 3783 } 3784 3785 static void mlx5_ib_free_rdma_netdev(struct net_device *netdev) 3786 { 3787 return mlx5_rdma_netdev_free(netdev); 3788 } 3789 3790 static struct net_device* 3791 mlx5_ib_alloc_rdma_netdev(struct ib_device *hca, 3792 u8 port_num, 3793 enum rdma_netdev_t type, 3794 const char *name, 3795 unsigned char name_assign_type, 3796 void (*setup)(struct net_device *)) 3797 { 3798 struct net_device *netdev; 3799 struct rdma_netdev *rn; 3800 3801 if (type != RDMA_NETDEV_IPOIB) 3802 return ERR_PTR(-EOPNOTSUPP); 3803 3804 netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca, 3805 name, setup); 3806 if (likely(!IS_ERR_OR_NULL(netdev))) { 3807 rn = netdev_priv(netdev); 3808 rn->free_rdma_netdev = mlx5_ib_free_rdma_netdev; 3809 } 3810 return netdev; 3811 } 3812 3813 static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev) 3814 { 3815 if (!dev->delay_drop.dbg) 3816 return; 3817 debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs); 3818 kfree(dev->delay_drop.dbg); 3819 dev->delay_drop.dbg = NULL; 3820 } 3821 3822 static void cancel_delay_drop(struct mlx5_ib_dev *dev) 3823 { 3824 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 3825 return; 3826 3827 cancel_work_sync(&dev->delay_drop.delay_drop_work); 3828 delay_drop_debugfs_cleanup(dev); 3829 } 3830 3831 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf, 3832 size_t count, loff_t *pos) 3833 { 3834 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3835 char lbuf[20]; 3836 int len; 3837 3838 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout); 3839 return simple_read_from_buffer(buf, count, pos, lbuf, len); 3840 } 3841 3842 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf, 3843 size_t count, loff_t *pos) 3844 { 3845 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3846 u32 timeout; 3847 u32 var; 3848 3849 if (kstrtouint_from_user(buf, count, 0, &var)) 3850 return -EFAULT; 3851 3852 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 3853 1000); 3854 if (timeout != var) 3855 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n", 3856 timeout); 3857 3858 delay_drop->timeout = timeout; 3859 3860 return count; 3861 } 3862 3863 static const struct file_operations fops_delay_drop_timeout = { 3864 .owner = THIS_MODULE, 3865 .open = simple_open, 3866 .write = delay_drop_timeout_write, 3867 .read = delay_drop_timeout_read, 3868 }; 3869 3870 static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev) 3871 { 3872 struct mlx5_ib_dbg_delay_drop *dbg; 3873 3874 if (!mlx5_debugfs_root) 3875 return 0; 3876 3877 dbg = kzalloc(sizeof(*dbg), GFP_KERNEL); 3878 if (!dbg) 3879 return -ENOMEM; 3880 3881 dev->delay_drop.dbg = dbg; 3882 3883 dbg->dir_debugfs = 3884 debugfs_create_dir("delay_drop", 3885 dev->mdev->priv.dbg_root); 3886 if (!dbg->dir_debugfs) 3887 goto out_debugfs; 3888 3889 dbg->events_cnt_debugfs = 3890 debugfs_create_atomic_t("num_timeout_events", 0400, 3891 dbg->dir_debugfs, 3892 &dev->delay_drop.events_cnt); 3893 if (!dbg->events_cnt_debugfs) 3894 goto out_debugfs; 3895 3896 dbg->rqs_cnt_debugfs = 3897 debugfs_create_atomic_t("num_rqs", 0400, 3898 dbg->dir_debugfs, 3899 &dev->delay_drop.rqs_cnt); 3900 if (!dbg->rqs_cnt_debugfs) 3901 goto out_debugfs; 3902 3903 dbg->timeout_debugfs = 3904 debugfs_create_file("timeout", 0600, 3905 dbg->dir_debugfs, 3906 &dev->delay_drop, 3907 &fops_delay_drop_timeout); 3908 if (!dbg->timeout_debugfs) 3909 goto out_debugfs; 3910 3911 return 0; 3912 3913 out_debugfs: 3914 delay_drop_debugfs_cleanup(dev); 3915 return -ENOMEM; 3916 } 3917 3918 static void init_delay_drop(struct mlx5_ib_dev *dev) 3919 { 3920 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 3921 return; 3922 3923 mutex_init(&dev->delay_drop.lock); 3924 dev->delay_drop.dev = dev; 3925 dev->delay_drop.activate = false; 3926 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000; 3927 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler); 3928 atomic_set(&dev->delay_drop.rqs_cnt, 0); 3929 atomic_set(&dev->delay_drop.events_cnt, 0); 3930 3931 if (delay_drop_debugfs_init(dev)) 3932 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n"); 3933 } 3934 3935 static const struct cpumask * 3936 mlx5_ib_get_vector_affinity(struct ib_device *ibdev, int comp_vector) 3937 { 3938 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3939 3940 return mlx5_get_vector_affinity(dev->mdev, comp_vector); 3941 } 3942 3943 static void *mlx5_ib_add(struct mlx5_core_dev *mdev) 3944 { 3945 struct mlx5_ib_dev *dev; 3946 enum rdma_link_layer ll; 3947 int port_type_cap; 3948 const char *name; 3949 int err; 3950 int i; 3951 3952 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 3953 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 3954 3955 printk_once(KERN_INFO "%s", mlx5_version); 3956 3957 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev)); 3958 if (!dev) 3959 return NULL; 3960 3961 dev->mdev = mdev; 3962 3963 dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port), 3964 GFP_KERNEL); 3965 if (!dev->port) 3966 goto err_dealloc; 3967 3968 rwlock_init(&dev->roce.netdev_lock); 3969 err = get_port_caps(dev); 3970 if (err) 3971 goto err_free_port; 3972 3973 if (mlx5_use_mad_ifc(dev)) 3974 get_ext_port_caps(dev); 3975 3976 if (!mlx5_lag_is_active(mdev)) 3977 name = "mlx5_%d"; 3978 else 3979 name = "mlx5_bond_%d"; 3980 3981 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX); 3982 dev->ib_dev.owner = THIS_MODULE; 3983 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 3984 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 3985 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports); 3986 dev->ib_dev.phys_port_cnt = dev->num_ports; 3987 dev->ib_dev.num_comp_vectors = 3988 dev->mdev->priv.eq_table.num_comp_vectors; 3989 dev->ib_dev.dev.parent = &mdev->pdev->dev; 3990 3991 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION; 3992 dev->ib_dev.uverbs_cmd_mask = 3993 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | 3994 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | 3995 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | 3996 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | 3997 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | 3998 (1ull << IB_USER_VERBS_CMD_CREATE_AH) | 3999 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) | 4000 (1ull << IB_USER_VERBS_CMD_REG_MR) | 4001 (1ull << IB_USER_VERBS_CMD_REREG_MR) | 4002 (1ull << IB_USER_VERBS_CMD_DEREG_MR) | 4003 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 4004 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | 4005 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) | 4006 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | 4007 (1ull << IB_USER_VERBS_CMD_CREATE_QP) | 4008 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | 4009 (1ull << IB_USER_VERBS_CMD_QUERY_QP) | 4010 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | 4011 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) | 4012 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) | 4013 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | 4014 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | 4015 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | 4016 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | 4017 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) | 4018 (1ull << IB_USER_VERBS_CMD_OPEN_QP); 4019 dev->ib_dev.uverbs_ex_cmd_mask = 4020 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) | 4021 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) | 4022 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) | 4023 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP); 4024 4025 dev->ib_dev.query_device = mlx5_ib_query_device; 4026 dev->ib_dev.query_port = mlx5_ib_query_port; 4027 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer; 4028 if (ll == IB_LINK_LAYER_ETHERNET) 4029 dev->ib_dev.get_netdev = mlx5_ib_get_netdev; 4030 dev->ib_dev.query_gid = mlx5_ib_query_gid; 4031 dev->ib_dev.add_gid = mlx5_ib_add_gid; 4032 dev->ib_dev.del_gid = mlx5_ib_del_gid; 4033 dev->ib_dev.query_pkey = mlx5_ib_query_pkey; 4034 dev->ib_dev.modify_device = mlx5_ib_modify_device; 4035 dev->ib_dev.modify_port = mlx5_ib_modify_port; 4036 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext; 4037 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext; 4038 dev->ib_dev.mmap = mlx5_ib_mmap; 4039 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd; 4040 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd; 4041 dev->ib_dev.create_ah = mlx5_ib_create_ah; 4042 dev->ib_dev.query_ah = mlx5_ib_query_ah; 4043 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah; 4044 dev->ib_dev.create_srq = mlx5_ib_create_srq; 4045 dev->ib_dev.modify_srq = mlx5_ib_modify_srq; 4046 dev->ib_dev.query_srq = mlx5_ib_query_srq; 4047 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq; 4048 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv; 4049 dev->ib_dev.create_qp = mlx5_ib_create_qp; 4050 dev->ib_dev.modify_qp = mlx5_ib_modify_qp; 4051 dev->ib_dev.query_qp = mlx5_ib_query_qp; 4052 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp; 4053 dev->ib_dev.post_send = mlx5_ib_post_send; 4054 dev->ib_dev.post_recv = mlx5_ib_post_recv; 4055 dev->ib_dev.create_cq = mlx5_ib_create_cq; 4056 dev->ib_dev.modify_cq = mlx5_ib_modify_cq; 4057 dev->ib_dev.resize_cq = mlx5_ib_resize_cq; 4058 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq; 4059 dev->ib_dev.poll_cq = mlx5_ib_poll_cq; 4060 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq; 4061 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr; 4062 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr; 4063 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr; 4064 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr; 4065 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach; 4066 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach; 4067 dev->ib_dev.process_mad = mlx5_ib_process_mad; 4068 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr; 4069 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg; 4070 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status; 4071 dev->ib_dev.get_port_immutable = mlx5_port_immutable; 4072 dev->ib_dev.get_dev_fw_str = get_dev_fw_str; 4073 dev->ib_dev.get_vector_affinity = mlx5_ib_get_vector_affinity; 4074 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads)) 4075 dev->ib_dev.alloc_rdma_netdev = mlx5_ib_alloc_rdma_netdev; 4076 4077 if (mlx5_core_is_pf(mdev)) { 4078 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config; 4079 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state; 4080 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats; 4081 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid; 4082 } 4083 4084 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext; 4085 4086 mlx5_ib_internal_fill_odp_caps(dev); 4087 4088 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence)); 4089 4090 if (MLX5_CAP_GEN(mdev, imaicl)) { 4091 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw; 4092 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw; 4093 dev->ib_dev.uverbs_cmd_mask |= 4094 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) | 4095 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW); 4096 } 4097 4098 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) { 4099 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats; 4100 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats; 4101 } 4102 4103 if (MLX5_CAP_GEN(mdev, xrc)) { 4104 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd; 4105 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd; 4106 dev->ib_dev.uverbs_cmd_mask |= 4107 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) | 4108 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD); 4109 } 4110 4111 dev->ib_dev.create_flow = mlx5_ib_create_flow; 4112 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow; 4113 dev->ib_dev.uverbs_ex_cmd_mask |= 4114 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) | 4115 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW); 4116 4117 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) == 4118 IB_LINK_LAYER_ETHERNET) { 4119 dev->ib_dev.create_wq = mlx5_ib_create_wq; 4120 dev->ib_dev.modify_wq = mlx5_ib_modify_wq; 4121 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq; 4122 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table; 4123 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table; 4124 dev->ib_dev.uverbs_ex_cmd_mask |= 4125 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) | 4126 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) | 4127 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) | 4128 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) | 4129 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL); 4130 } 4131 err = init_node_data(dev); 4132 if (err) 4133 goto err_free_port; 4134 4135 mutex_init(&dev->flow_db.lock); 4136 mutex_init(&dev->cap_mask_mutex); 4137 INIT_LIST_HEAD(&dev->qp_list); 4138 spin_lock_init(&dev->reset_flow_resource_lock); 4139 4140 if (ll == IB_LINK_LAYER_ETHERNET) { 4141 err = mlx5_enable_eth(dev); 4142 if (err) 4143 goto err_free_port; 4144 dev->roce.last_port_state = IB_PORT_DOWN; 4145 } 4146 4147 err = create_dev_resources(&dev->devr); 4148 if (err) 4149 goto err_disable_eth; 4150 4151 err = mlx5_ib_odp_init_one(dev); 4152 if (err) 4153 goto err_rsrc; 4154 4155 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) { 4156 err = mlx5_ib_alloc_counters(dev); 4157 if (err) 4158 goto err_odp; 4159 } 4160 4161 err = mlx5_ib_init_cong_debugfs(dev); 4162 if (err) 4163 goto err_cnt; 4164 4165 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev); 4166 if (!dev->mdev->priv.uar) 4167 goto err_cong; 4168 4169 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false); 4170 if (err) 4171 goto err_uar_page; 4172 4173 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true); 4174 if (err) 4175 goto err_bfreg; 4176 4177 err = ib_register_device(&dev->ib_dev, NULL); 4178 if (err) 4179 goto err_fp_bfreg; 4180 4181 err = create_umr_res(dev); 4182 if (err) 4183 goto err_dev; 4184 4185 init_delay_drop(dev); 4186 4187 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) { 4188 err = device_create_file(&dev->ib_dev.dev, 4189 mlx5_class_attributes[i]); 4190 if (err) 4191 goto err_delay_drop; 4192 } 4193 4194 if ((MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && 4195 MLX5_CAP_GEN(mdev, disable_local_lb)) 4196 mutex_init(&dev->lb_mutex); 4197 4198 dev->ib_active = true; 4199 4200 return dev; 4201 4202 err_delay_drop: 4203 cancel_delay_drop(dev); 4204 destroy_umrc_res(dev); 4205 4206 err_dev: 4207 ib_unregister_device(&dev->ib_dev); 4208 4209 err_fp_bfreg: 4210 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 4211 4212 err_bfreg: 4213 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4214 4215 err_uar_page: 4216 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar); 4217 4218 err_cong: 4219 mlx5_ib_cleanup_cong_debugfs(dev); 4220 err_cnt: 4221 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) 4222 mlx5_ib_dealloc_counters(dev); 4223 4224 err_odp: 4225 mlx5_ib_odp_remove_one(dev); 4226 4227 err_rsrc: 4228 destroy_dev_resources(&dev->devr); 4229 4230 err_disable_eth: 4231 if (ll == IB_LINK_LAYER_ETHERNET) { 4232 mlx5_disable_eth(dev); 4233 mlx5_remove_netdev_notifier(dev); 4234 } 4235 4236 err_free_port: 4237 kfree(dev->port); 4238 4239 err_dealloc: 4240 ib_dealloc_device((struct ib_device *)dev); 4241 4242 return NULL; 4243 } 4244 4245 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context) 4246 { 4247 struct mlx5_ib_dev *dev = context; 4248 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1); 4249 4250 cancel_delay_drop(dev); 4251 mlx5_remove_netdev_notifier(dev); 4252 ib_unregister_device(&dev->ib_dev); 4253 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 4254 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4255 mlx5_put_uars_page(dev->mdev, mdev->priv.uar); 4256 mlx5_ib_cleanup_cong_debugfs(dev); 4257 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) 4258 mlx5_ib_dealloc_counters(dev); 4259 destroy_umrc_res(dev); 4260 mlx5_ib_odp_remove_one(dev); 4261 destroy_dev_resources(&dev->devr); 4262 if (ll == IB_LINK_LAYER_ETHERNET) 4263 mlx5_disable_eth(dev); 4264 kfree(dev->port); 4265 ib_dealloc_device(&dev->ib_dev); 4266 } 4267 4268 static struct mlx5_interface mlx5_ib_interface = { 4269 .add = mlx5_ib_add, 4270 .remove = mlx5_ib_remove, 4271 .event = mlx5_ib_event, 4272 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 4273 .pfault = mlx5_ib_pfault, 4274 #endif 4275 .protocol = MLX5_INTERFACE_PROTOCOL_IB, 4276 }; 4277 4278 static int __init mlx5_ib_init(void) 4279 { 4280 int err; 4281 4282 mlx5_ib_odp_init(); 4283 4284 err = mlx5_register_interface(&mlx5_ib_interface); 4285 4286 return err; 4287 } 4288 4289 static void __exit mlx5_ib_cleanup(void) 4290 { 4291 mlx5_unregister_interface(&mlx5_ib_interface); 4292 } 4293 4294 module_init(mlx5_ib_init); 4295 module_exit(mlx5_ib_cleanup); 4296