1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/debugfs.h> 34 #include <linux/highmem.h> 35 #include <linux/module.h> 36 #include <linux/init.h> 37 #include <linux/errno.h> 38 #include <linux/pci.h> 39 #include <linux/dma-mapping.h> 40 #include <linux/slab.h> 41 #include <linux/bitmap.h> 42 #if defined(CONFIG_X86) 43 #include <asm/pat.h> 44 #endif 45 #include <linux/sched.h> 46 #include <linux/sched/mm.h> 47 #include <linux/sched/task.h> 48 #include <linux/delay.h> 49 #include <rdma/ib_user_verbs.h> 50 #include <rdma/ib_addr.h> 51 #include <rdma/ib_cache.h> 52 #include <linux/mlx5/port.h> 53 #include <linux/mlx5/vport.h> 54 #include <linux/mlx5/fs.h> 55 #include <linux/list.h> 56 #include <rdma/ib_smi.h> 57 #include <rdma/ib_umem.h> 58 #include <linux/in.h> 59 #include <linux/etherdevice.h> 60 #include "mlx5_ib.h" 61 #include "ib_rep.h" 62 #include "cmd.h" 63 #include <linux/mlx5/fs_helpers.h> 64 #include <linux/mlx5/accel.h> 65 #include <rdma/uverbs_std_types.h> 66 #include <rdma/mlx5_user_ioctl_verbs.h> 67 #include <rdma/mlx5_user_ioctl_cmds.h> 68 69 #define UVERBS_MODULE_NAME mlx5_ib 70 #include <rdma/uverbs_named_ioctl.h> 71 72 #define DRIVER_NAME "mlx5_ib" 73 #define DRIVER_VERSION "5.0-0" 74 75 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 76 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver"); 77 MODULE_LICENSE("Dual BSD/GPL"); 78 79 static char mlx5_version[] = 80 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v" 81 DRIVER_VERSION "\n"; 82 83 struct mlx5_ib_event_work { 84 struct work_struct work; 85 struct mlx5_core_dev *dev; 86 void *context; 87 enum mlx5_dev_event event; 88 unsigned long param; 89 }; 90 91 enum { 92 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 93 }; 94 95 static struct workqueue_struct *mlx5_ib_event_wq; 96 static LIST_HEAD(mlx5_ib_unaffiliated_port_list); 97 static LIST_HEAD(mlx5_ib_dev_list); 98 /* 99 * This mutex should be held when accessing either of the above lists 100 */ 101 static DEFINE_MUTEX(mlx5_ib_multiport_mutex); 102 103 /* We can't use an array for xlt_emergency_page because dma_map_single 104 * doesn't work on kernel modules memory 105 */ 106 static unsigned long xlt_emergency_page; 107 static struct mutex xlt_emergency_page_mutex; 108 109 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi) 110 { 111 struct mlx5_ib_dev *dev; 112 113 mutex_lock(&mlx5_ib_multiport_mutex); 114 dev = mpi->ibdev; 115 mutex_unlock(&mlx5_ib_multiport_mutex); 116 return dev; 117 } 118 119 static enum rdma_link_layer 120 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 121 { 122 switch (port_type_cap) { 123 case MLX5_CAP_PORT_TYPE_IB: 124 return IB_LINK_LAYER_INFINIBAND; 125 case MLX5_CAP_PORT_TYPE_ETH: 126 return IB_LINK_LAYER_ETHERNET; 127 default: 128 return IB_LINK_LAYER_UNSPECIFIED; 129 } 130 } 131 132 static enum rdma_link_layer 133 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num) 134 { 135 struct mlx5_ib_dev *dev = to_mdev(device); 136 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 137 138 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 139 } 140 141 static int get_port_state(struct ib_device *ibdev, 142 u8 port_num, 143 enum ib_port_state *state) 144 { 145 struct ib_port_attr attr; 146 int ret; 147 148 memset(&attr, 0, sizeof(attr)); 149 ret = ibdev->query_port(ibdev, port_num, &attr); 150 if (!ret) 151 *state = attr.state; 152 return ret; 153 } 154 155 static int mlx5_netdev_event(struct notifier_block *this, 156 unsigned long event, void *ptr) 157 { 158 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb); 159 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 160 u8 port_num = roce->native_port_num; 161 struct mlx5_core_dev *mdev; 162 struct mlx5_ib_dev *ibdev; 163 164 ibdev = roce->dev; 165 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 166 if (!mdev) 167 return NOTIFY_DONE; 168 169 switch (event) { 170 case NETDEV_REGISTER: 171 case NETDEV_UNREGISTER: 172 write_lock(&roce->netdev_lock); 173 if (ibdev->rep) { 174 struct mlx5_eswitch *esw = ibdev->mdev->priv.eswitch; 175 struct net_device *rep_ndev; 176 177 rep_ndev = mlx5_ib_get_rep_netdev(esw, 178 ibdev->rep->vport); 179 if (rep_ndev == ndev) 180 roce->netdev = (event == NETDEV_UNREGISTER) ? 181 NULL : ndev; 182 } else if (ndev->dev.parent == &mdev->pdev->dev) { 183 roce->netdev = (event == NETDEV_UNREGISTER) ? 184 NULL : ndev; 185 } 186 write_unlock(&roce->netdev_lock); 187 break; 188 189 case NETDEV_CHANGE: 190 case NETDEV_UP: 191 case NETDEV_DOWN: { 192 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev); 193 struct net_device *upper = NULL; 194 195 if (lag_ndev) { 196 upper = netdev_master_upper_dev_get(lag_ndev); 197 dev_put(lag_ndev); 198 } 199 200 if ((upper == ndev || (!upper && ndev == roce->netdev)) 201 && ibdev->ib_active) { 202 struct ib_event ibev = { }; 203 enum ib_port_state port_state; 204 205 if (get_port_state(&ibdev->ib_dev, port_num, 206 &port_state)) 207 goto done; 208 209 if (roce->last_port_state == port_state) 210 goto done; 211 212 roce->last_port_state = port_state; 213 ibev.device = &ibdev->ib_dev; 214 if (port_state == IB_PORT_DOWN) 215 ibev.event = IB_EVENT_PORT_ERR; 216 else if (port_state == IB_PORT_ACTIVE) 217 ibev.event = IB_EVENT_PORT_ACTIVE; 218 else 219 goto done; 220 221 ibev.element.port_num = port_num; 222 ib_dispatch_event(&ibev); 223 } 224 break; 225 } 226 227 default: 228 break; 229 } 230 done: 231 mlx5_ib_put_native_port_mdev(ibdev, port_num); 232 return NOTIFY_DONE; 233 } 234 235 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device, 236 u8 port_num) 237 { 238 struct mlx5_ib_dev *ibdev = to_mdev(device); 239 struct net_device *ndev; 240 struct mlx5_core_dev *mdev; 241 242 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 243 if (!mdev) 244 return NULL; 245 246 ndev = mlx5_lag_get_roce_netdev(mdev); 247 if (ndev) 248 goto out; 249 250 /* Ensure ndev does not disappear before we invoke dev_hold() 251 */ 252 read_lock(&ibdev->roce[port_num - 1].netdev_lock); 253 ndev = ibdev->roce[port_num - 1].netdev; 254 if (ndev) 255 dev_hold(ndev); 256 read_unlock(&ibdev->roce[port_num - 1].netdev_lock); 257 258 out: 259 mlx5_ib_put_native_port_mdev(ibdev, port_num); 260 return ndev; 261 } 262 263 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev, 264 u8 ib_port_num, 265 u8 *native_port_num) 266 { 267 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 268 ib_port_num); 269 struct mlx5_core_dev *mdev = NULL; 270 struct mlx5_ib_multiport_info *mpi; 271 struct mlx5_ib_port *port; 272 273 if (!mlx5_core_mp_enabled(ibdev->mdev) || 274 ll != IB_LINK_LAYER_ETHERNET) { 275 if (native_port_num) 276 *native_port_num = ib_port_num; 277 return ibdev->mdev; 278 } 279 280 if (native_port_num) 281 *native_port_num = 1; 282 283 port = &ibdev->port[ib_port_num - 1]; 284 if (!port) 285 return NULL; 286 287 spin_lock(&port->mp.mpi_lock); 288 mpi = ibdev->port[ib_port_num - 1].mp.mpi; 289 if (mpi && !mpi->unaffiliate) { 290 mdev = mpi->mdev; 291 /* If it's the master no need to refcount, it'll exist 292 * as long as the ib_dev exists. 293 */ 294 if (!mpi->is_master) 295 mpi->mdev_refcnt++; 296 } 297 spin_unlock(&port->mp.mpi_lock); 298 299 return mdev; 300 } 301 302 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num) 303 { 304 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 305 port_num); 306 struct mlx5_ib_multiport_info *mpi; 307 struct mlx5_ib_port *port; 308 309 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 310 return; 311 312 port = &ibdev->port[port_num - 1]; 313 314 spin_lock(&port->mp.mpi_lock); 315 mpi = ibdev->port[port_num - 1].mp.mpi; 316 if (mpi->is_master) 317 goto out; 318 319 mpi->mdev_refcnt--; 320 if (mpi->unaffiliate) 321 complete(&mpi->unref_comp); 322 out: 323 spin_unlock(&port->mp.mpi_lock); 324 } 325 326 static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed, 327 u8 *active_width) 328 { 329 switch (eth_proto_oper) { 330 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII): 331 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX): 332 case MLX5E_PROT_MASK(MLX5E_100BASE_TX): 333 case MLX5E_PROT_MASK(MLX5E_1000BASE_T): 334 *active_width = IB_WIDTH_1X; 335 *active_speed = IB_SPEED_SDR; 336 break; 337 case MLX5E_PROT_MASK(MLX5E_10GBASE_T): 338 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4): 339 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4): 340 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR): 341 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR): 342 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR): 343 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER): 344 *active_width = IB_WIDTH_1X; 345 *active_speed = IB_SPEED_QDR; 346 break; 347 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR): 348 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR): 349 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR): 350 *active_width = IB_WIDTH_1X; 351 *active_speed = IB_SPEED_EDR; 352 break; 353 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4): 354 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4): 355 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4): 356 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4): 357 *active_width = IB_WIDTH_4X; 358 *active_speed = IB_SPEED_QDR; 359 break; 360 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2): 361 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2): 362 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2): 363 *active_width = IB_WIDTH_1X; 364 *active_speed = IB_SPEED_HDR; 365 break; 366 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4): 367 *active_width = IB_WIDTH_4X; 368 *active_speed = IB_SPEED_FDR; 369 break; 370 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4): 371 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4): 372 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4): 373 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4): 374 *active_width = IB_WIDTH_4X; 375 *active_speed = IB_SPEED_EDR; 376 break; 377 default: 378 return -EINVAL; 379 } 380 381 return 0; 382 } 383 384 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num, 385 struct ib_port_attr *props) 386 { 387 struct mlx5_ib_dev *dev = to_mdev(device); 388 struct mlx5_core_dev *mdev; 389 struct net_device *ndev, *upper; 390 enum ib_mtu ndev_ib_mtu; 391 bool put_mdev = true; 392 u16 qkey_viol_cntr; 393 u32 eth_prot_oper; 394 u8 mdev_port_num; 395 int err; 396 397 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 398 if (!mdev) { 399 /* This means the port isn't affiliated yet. Get the 400 * info for the master port instead. 401 */ 402 put_mdev = false; 403 mdev = dev->mdev; 404 mdev_port_num = 1; 405 port_num = 1; 406 } 407 408 /* Possible bad flows are checked before filling out props so in case 409 * of an error it will still be zeroed out. 410 */ 411 err = mlx5_query_port_eth_proto_oper(mdev, ð_prot_oper, 412 mdev_port_num); 413 if (err) 414 goto out; 415 416 props->active_width = IB_WIDTH_4X; 417 props->active_speed = IB_SPEED_QDR; 418 419 translate_eth_proto_oper(eth_prot_oper, &props->active_speed, 420 &props->active_width); 421 422 props->port_cap_flags |= IB_PORT_CM_SUP; 423 props->ip_gids = true; 424 425 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 426 roce_address_table_size); 427 props->max_mtu = IB_MTU_4096; 428 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 429 props->pkey_tbl_len = 1; 430 props->state = IB_PORT_DOWN; 431 props->phys_state = 3; 432 433 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr); 434 props->qkey_viol_cntr = qkey_viol_cntr; 435 436 /* If this is a stub query for an unaffiliated port stop here */ 437 if (!put_mdev) 438 goto out; 439 440 ndev = mlx5_ib_get_netdev(device, port_num); 441 if (!ndev) 442 goto out; 443 444 if (mlx5_lag_is_active(dev->mdev)) { 445 rcu_read_lock(); 446 upper = netdev_master_upper_dev_get_rcu(ndev); 447 if (upper) { 448 dev_put(ndev); 449 ndev = upper; 450 dev_hold(ndev); 451 } 452 rcu_read_unlock(); 453 } 454 455 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 456 props->state = IB_PORT_ACTIVE; 457 props->phys_state = 5; 458 } 459 460 ndev_ib_mtu = iboe_get_mtu(ndev->mtu); 461 462 dev_put(ndev); 463 464 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 465 out: 466 if (put_mdev) 467 mlx5_ib_put_native_port_mdev(dev, port_num); 468 return err; 469 } 470 471 static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num, 472 unsigned int index, const union ib_gid *gid, 473 const struct ib_gid_attr *attr) 474 { 475 enum ib_gid_type gid_type = IB_GID_TYPE_IB; 476 u8 roce_version = 0; 477 u8 roce_l3_type = 0; 478 bool vlan = false; 479 u8 mac[ETH_ALEN]; 480 u16 vlan_id = 0; 481 482 if (gid) { 483 gid_type = attr->gid_type; 484 ether_addr_copy(mac, attr->ndev->dev_addr); 485 486 if (is_vlan_dev(attr->ndev)) { 487 vlan = true; 488 vlan_id = vlan_dev_vlan_id(attr->ndev); 489 } 490 } 491 492 switch (gid_type) { 493 case IB_GID_TYPE_IB: 494 roce_version = MLX5_ROCE_VERSION_1; 495 break; 496 case IB_GID_TYPE_ROCE_UDP_ENCAP: 497 roce_version = MLX5_ROCE_VERSION_2; 498 if (ipv6_addr_v4mapped((void *)gid)) 499 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4; 500 else 501 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6; 502 break; 503 504 default: 505 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type); 506 } 507 508 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version, 509 roce_l3_type, gid->raw, mac, vlan, 510 vlan_id, port_num); 511 } 512 513 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr, 514 __always_unused void **context) 515 { 516 return set_roce_addr(to_mdev(attr->device), attr->port_num, 517 attr->index, &attr->gid, attr); 518 } 519 520 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr, 521 __always_unused void **context) 522 { 523 return set_roce_addr(to_mdev(attr->device), attr->port_num, 524 attr->index, NULL, NULL); 525 } 526 527 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, 528 const struct ib_gid_attr *attr) 529 { 530 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 531 return 0; 532 533 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 534 } 535 536 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 537 { 538 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 539 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 540 return 0; 541 } 542 543 enum { 544 MLX5_VPORT_ACCESS_METHOD_MAD, 545 MLX5_VPORT_ACCESS_METHOD_HCA, 546 MLX5_VPORT_ACCESS_METHOD_NIC, 547 }; 548 549 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 550 { 551 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 552 return MLX5_VPORT_ACCESS_METHOD_MAD; 553 554 if (mlx5_ib_port_link_layer(ibdev, 1) == 555 IB_LINK_LAYER_ETHERNET) 556 return MLX5_VPORT_ACCESS_METHOD_NIC; 557 558 return MLX5_VPORT_ACCESS_METHOD_HCA; 559 } 560 561 static void get_atomic_caps(struct mlx5_ib_dev *dev, 562 u8 atomic_size_qp, 563 struct ib_device_attr *props) 564 { 565 u8 tmp; 566 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 567 u8 atomic_req_8B_endianness_mode = 568 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode); 569 570 /* Check if HW supports 8 bytes standard atomic operations and capable 571 * of host endianness respond 572 */ 573 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 574 if (((atomic_operations & tmp) == tmp) && 575 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 576 (atomic_req_8B_endianness_mode)) { 577 props->atomic_cap = IB_ATOMIC_HCA; 578 } else { 579 props->atomic_cap = IB_ATOMIC_NONE; 580 } 581 } 582 583 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev, 584 struct ib_device_attr *props) 585 { 586 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 587 588 get_atomic_caps(dev, atomic_size_qp, props); 589 } 590 591 static void get_atomic_caps_dc(struct mlx5_ib_dev *dev, 592 struct ib_device_attr *props) 593 { 594 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc); 595 596 get_atomic_caps(dev, atomic_size_qp, props); 597 } 598 599 bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev) 600 { 601 struct ib_device_attr props = {}; 602 603 get_atomic_caps_dc(dev, &props); 604 return (props.atomic_cap == IB_ATOMIC_HCA) ? true : false; 605 } 606 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 607 __be64 *sys_image_guid) 608 { 609 struct mlx5_ib_dev *dev = to_mdev(ibdev); 610 struct mlx5_core_dev *mdev = dev->mdev; 611 u64 tmp; 612 int err; 613 614 switch (mlx5_get_vport_access_method(ibdev)) { 615 case MLX5_VPORT_ACCESS_METHOD_MAD: 616 return mlx5_query_mad_ifc_system_image_guid(ibdev, 617 sys_image_guid); 618 619 case MLX5_VPORT_ACCESS_METHOD_HCA: 620 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 621 break; 622 623 case MLX5_VPORT_ACCESS_METHOD_NIC: 624 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 625 break; 626 627 default: 628 return -EINVAL; 629 } 630 631 if (!err) 632 *sys_image_guid = cpu_to_be64(tmp); 633 634 return err; 635 636 } 637 638 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 639 u16 *max_pkeys) 640 { 641 struct mlx5_ib_dev *dev = to_mdev(ibdev); 642 struct mlx5_core_dev *mdev = dev->mdev; 643 644 switch (mlx5_get_vport_access_method(ibdev)) { 645 case MLX5_VPORT_ACCESS_METHOD_MAD: 646 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 647 648 case MLX5_VPORT_ACCESS_METHOD_HCA: 649 case MLX5_VPORT_ACCESS_METHOD_NIC: 650 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 651 pkey_table_size)); 652 return 0; 653 654 default: 655 return -EINVAL; 656 } 657 } 658 659 static int mlx5_query_vendor_id(struct ib_device *ibdev, 660 u32 *vendor_id) 661 { 662 struct mlx5_ib_dev *dev = to_mdev(ibdev); 663 664 switch (mlx5_get_vport_access_method(ibdev)) { 665 case MLX5_VPORT_ACCESS_METHOD_MAD: 666 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 667 668 case MLX5_VPORT_ACCESS_METHOD_HCA: 669 case MLX5_VPORT_ACCESS_METHOD_NIC: 670 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 671 672 default: 673 return -EINVAL; 674 } 675 } 676 677 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 678 __be64 *node_guid) 679 { 680 u64 tmp; 681 int err; 682 683 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 684 case MLX5_VPORT_ACCESS_METHOD_MAD: 685 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 686 687 case MLX5_VPORT_ACCESS_METHOD_HCA: 688 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 689 break; 690 691 case MLX5_VPORT_ACCESS_METHOD_NIC: 692 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 693 break; 694 695 default: 696 return -EINVAL; 697 } 698 699 if (!err) 700 *node_guid = cpu_to_be64(tmp); 701 702 return err; 703 } 704 705 struct mlx5_reg_node_desc { 706 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 707 }; 708 709 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 710 { 711 struct mlx5_reg_node_desc in; 712 713 if (mlx5_use_mad_ifc(dev)) 714 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 715 716 memset(&in, 0, sizeof(in)); 717 718 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 719 sizeof(struct mlx5_reg_node_desc), 720 MLX5_REG_NODE_DESC, 0, 0); 721 } 722 723 static int mlx5_ib_query_device(struct ib_device *ibdev, 724 struct ib_device_attr *props, 725 struct ib_udata *uhw) 726 { 727 struct mlx5_ib_dev *dev = to_mdev(ibdev); 728 struct mlx5_core_dev *mdev = dev->mdev; 729 int err = -ENOMEM; 730 int max_sq_desc; 731 int max_rq_sg; 732 int max_sq_sg; 733 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 734 bool raw_support = !mlx5_core_mp_enabled(mdev); 735 struct mlx5_ib_query_device_resp resp = {}; 736 size_t resp_len; 737 u64 max_tso; 738 739 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 740 if (uhw->outlen && uhw->outlen < resp_len) 741 return -EINVAL; 742 else 743 resp.response_length = resp_len; 744 745 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) 746 return -EINVAL; 747 748 memset(props, 0, sizeof(*props)); 749 err = mlx5_query_system_image_guid(ibdev, 750 &props->sys_image_guid); 751 if (err) 752 return err; 753 754 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys); 755 if (err) 756 return err; 757 758 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 759 if (err) 760 return err; 761 762 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 763 (fw_rev_min(dev->mdev) << 16) | 764 fw_rev_sub(dev->mdev); 765 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 766 IB_DEVICE_PORT_ACTIVE_EVENT | 767 IB_DEVICE_SYS_IMAGE_GUID | 768 IB_DEVICE_RC_RNR_NAK_GEN; 769 770 if (MLX5_CAP_GEN(mdev, pkv)) 771 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 772 if (MLX5_CAP_GEN(mdev, qkv)) 773 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 774 if (MLX5_CAP_GEN(mdev, apm)) 775 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 776 if (MLX5_CAP_GEN(mdev, xrc)) 777 props->device_cap_flags |= IB_DEVICE_XRC; 778 if (MLX5_CAP_GEN(mdev, imaicl)) { 779 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 780 IB_DEVICE_MEM_WINDOW_TYPE_2B; 781 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 782 /* We support 'Gappy' memory registration too */ 783 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG; 784 } 785 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 786 if (MLX5_CAP_GEN(mdev, sho)) { 787 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER; 788 /* At this stage no support for signature handover */ 789 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 790 IB_PROT_T10DIF_TYPE_2 | 791 IB_PROT_T10DIF_TYPE_3; 792 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 793 IB_GUARD_T10DIF_CSUM; 794 } 795 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 796 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 797 798 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) { 799 if (MLX5_CAP_ETH(mdev, csum_cap)) { 800 /* Legacy bit to support old userspace libraries */ 801 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 802 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM; 803 } 804 805 if (MLX5_CAP_ETH(dev->mdev, vlan_cap)) 806 props->raw_packet_caps |= 807 IB_RAW_PACKET_CAP_CVLAN_STRIPPING; 808 809 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) { 810 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 811 if (max_tso) { 812 resp.tso_caps.max_tso = 1 << max_tso; 813 resp.tso_caps.supported_qpts |= 814 1 << IB_QPT_RAW_PACKET; 815 resp.response_length += sizeof(resp.tso_caps); 816 } 817 } 818 819 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) { 820 resp.rss_caps.rx_hash_function = 821 MLX5_RX_HASH_FUNC_TOEPLITZ; 822 resp.rss_caps.rx_hash_fields_mask = 823 MLX5_RX_HASH_SRC_IPV4 | 824 MLX5_RX_HASH_DST_IPV4 | 825 MLX5_RX_HASH_SRC_IPV6 | 826 MLX5_RX_HASH_DST_IPV6 | 827 MLX5_RX_HASH_SRC_PORT_TCP | 828 MLX5_RX_HASH_DST_PORT_TCP | 829 MLX5_RX_HASH_SRC_PORT_UDP | 830 MLX5_RX_HASH_DST_PORT_UDP | 831 MLX5_RX_HASH_INNER; 832 if (mlx5_accel_ipsec_device_caps(dev->mdev) & 833 MLX5_ACCEL_IPSEC_CAP_DEVICE) 834 resp.rss_caps.rx_hash_fields_mask |= 835 MLX5_RX_HASH_IPSEC_SPI; 836 resp.response_length += sizeof(resp.rss_caps); 837 } 838 } else { 839 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) 840 resp.response_length += sizeof(resp.tso_caps); 841 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) 842 resp.response_length += sizeof(resp.rss_caps); 843 } 844 845 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 846 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 847 props->device_cap_flags |= IB_DEVICE_UD_TSO; 848 } 849 850 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) && 851 MLX5_CAP_GEN(dev->mdev, general_notification_event) && 852 raw_support) 853 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP; 854 855 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 856 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap)) 857 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 858 859 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 860 MLX5_CAP_ETH(dev->mdev, scatter_fcs) && 861 raw_support) { 862 /* Legacy bit to support old userspace libraries */ 863 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 864 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; 865 } 866 867 if (MLX5_CAP_DEV_MEM(mdev, memic)) { 868 props->max_dm_size = 869 MLX5_CAP_DEV_MEM(mdev, max_memic_size); 870 } 871 872 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 873 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 874 875 if (MLX5_CAP_GEN(mdev, end_pad)) 876 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING; 877 878 props->vendor_part_id = mdev->pdev->device; 879 props->hw_ver = mdev->pdev->revision; 880 881 props->max_mr_size = ~0ull; 882 props->page_size_cap = ~(min_page_size - 1); 883 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 884 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 885 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 886 sizeof(struct mlx5_wqe_data_seg); 887 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512); 888 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) - 889 sizeof(struct mlx5_wqe_raddr_seg)) / 890 sizeof(struct mlx5_wqe_data_seg); 891 props->max_send_sge = max_sq_sg; 892 props->max_recv_sge = max_rq_sg; 893 props->max_sge_rd = MLX5_MAX_SGE_RD; 894 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 895 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 896 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 897 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 898 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 899 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 900 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 901 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 902 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 903 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 904 props->max_srq_sge = max_rq_sg - 1; 905 props->max_fast_reg_page_list_len = 906 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 907 get_atomic_caps_qp(dev, props); 908 props->masked_atomic_cap = IB_ATOMIC_NONE; 909 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 910 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 911 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 912 props->max_mcast_grp; 913 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */ 914 props->max_ah = INT_MAX; 915 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 916 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 917 918 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 919 if (MLX5_CAP_GEN(mdev, pg)) 920 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING; 921 props->odp_caps = dev->odp_caps; 922 #endif 923 924 if (MLX5_CAP_GEN(mdev, cd)) 925 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL; 926 927 if (!mlx5_core_is_pf(mdev)) 928 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION; 929 930 if (mlx5_ib_port_link_layer(ibdev, 1) == 931 IB_LINK_LAYER_ETHERNET && raw_support) { 932 props->rss_caps.max_rwq_indirection_tables = 933 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 934 props->rss_caps.max_rwq_indirection_table_size = 935 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 936 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 937 props->max_wq_type_rq = 938 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 939 } 940 941 if (MLX5_CAP_GEN(mdev, tag_matching)) { 942 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE; 943 props->tm_caps.max_num_tags = 944 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1; 945 props->tm_caps.flags = IB_TM_CAP_RC; 946 props->tm_caps.max_ops = 947 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 948 props->tm_caps.max_sge = MLX5_TM_MAX_SGE; 949 } 950 951 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) { 952 props->cq_caps.max_cq_moderation_count = 953 MLX5_MAX_CQ_COUNT; 954 props->cq_caps.max_cq_moderation_period = 955 MLX5_MAX_CQ_PERIOD; 956 } 957 958 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) { 959 resp.response_length += sizeof(resp.cqe_comp_caps); 960 961 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) { 962 resp.cqe_comp_caps.max_num = 963 MLX5_CAP_GEN(dev->mdev, 964 cqe_compression_max_num); 965 966 resp.cqe_comp_caps.supported_format = 967 MLX5_IB_CQE_RES_FORMAT_HASH | 968 MLX5_IB_CQE_RES_FORMAT_CSUM; 969 970 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index)) 971 resp.cqe_comp_caps.supported_format |= 972 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX; 973 } 974 } 975 976 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen) && 977 raw_support) { 978 if (MLX5_CAP_QOS(mdev, packet_pacing) && 979 MLX5_CAP_GEN(mdev, qos)) { 980 resp.packet_pacing_caps.qp_rate_limit_max = 981 MLX5_CAP_QOS(mdev, packet_pacing_max_rate); 982 resp.packet_pacing_caps.qp_rate_limit_min = 983 MLX5_CAP_QOS(mdev, packet_pacing_min_rate); 984 resp.packet_pacing_caps.supported_qpts |= 985 1 << IB_QPT_RAW_PACKET; 986 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) && 987 MLX5_CAP_QOS(mdev, packet_pacing_typical_size)) 988 resp.packet_pacing_caps.cap_flags |= 989 MLX5_IB_PP_SUPPORT_BURST; 990 } 991 resp.response_length += sizeof(resp.packet_pacing_caps); 992 } 993 994 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes, 995 uhw->outlen)) { 996 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe)) 997 resp.mlx5_ib_support_multi_pkt_send_wqes = 998 MLX5_IB_ALLOW_MPW; 999 1000 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe)) 1001 resp.mlx5_ib_support_multi_pkt_send_wqes |= 1002 MLX5_IB_SUPPORT_EMPW; 1003 1004 resp.response_length += 1005 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes); 1006 } 1007 1008 if (field_avail(typeof(resp), flags, uhw->outlen)) { 1009 resp.response_length += sizeof(resp.flags); 1010 1011 if (MLX5_CAP_GEN(mdev, cqe_compression_128)) 1012 resp.flags |= 1013 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP; 1014 1015 if (MLX5_CAP_GEN(mdev, cqe_128_always)) 1016 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD; 1017 } 1018 1019 if (field_avail(typeof(resp), sw_parsing_caps, 1020 uhw->outlen)) { 1021 resp.response_length += sizeof(resp.sw_parsing_caps); 1022 if (MLX5_CAP_ETH(mdev, swp)) { 1023 resp.sw_parsing_caps.sw_parsing_offloads |= 1024 MLX5_IB_SW_PARSING; 1025 1026 if (MLX5_CAP_ETH(mdev, swp_csum)) 1027 resp.sw_parsing_caps.sw_parsing_offloads |= 1028 MLX5_IB_SW_PARSING_CSUM; 1029 1030 if (MLX5_CAP_ETH(mdev, swp_lso)) 1031 resp.sw_parsing_caps.sw_parsing_offloads |= 1032 MLX5_IB_SW_PARSING_LSO; 1033 1034 if (resp.sw_parsing_caps.sw_parsing_offloads) 1035 resp.sw_parsing_caps.supported_qpts = 1036 BIT(IB_QPT_RAW_PACKET); 1037 } 1038 } 1039 1040 if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen) && 1041 raw_support) { 1042 resp.response_length += sizeof(resp.striding_rq_caps); 1043 if (MLX5_CAP_GEN(mdev, striding_rq)) { 1044 resp.striding_rq_caps.min_single_stride_log_num_of_bytes = 1045 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES; 1046 resp.striding_rq_caps.max_single_stride_log_num_of_bytes = 1047 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES; 1048 resp.striding_rq_caps.min_single_wqe_log_num_of_strides = 1049 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1050 resp.striding_rq_caps.max_single_wqe_log_num_of_strides = 1051 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES; 1052 resp.striding_rq_caps.supported_qpts = 1053 BIT(IB_QPT_RAW_PACKET); 1054 } 1055 } 1056 1057 if (field_avail(typeof(resp), tunnel_offloads_caps, 1058 uhw->outlen)) { 1059 resp.response_length += sizeof(resp.tunnel_offloads_caps); 1060 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan)) 1061 resp.tunnel_offloads_caps |= 1062 MLX5_IB_TUNNELED_OFFLOADS_VXLAN; 1063 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx)) 1064 resp.tunnel_offloads_caps |= 1065 MLX5_IB_TUNNELED_OFFLOADS_GENEVE; 1066 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) 1067 resp.tunnel_offloads_caps |= 1068 MLX5_IB_TUNNELED_OFFLOADS_GRE; 1069 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) & 1070 MLX5_FLEX_PROTO_CW_MPLS_GRE) 1071 resp.tunnel_offloads_caps |= 1072 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE; 1073 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) & 1074 MLX5_FLEX_PROTO_CW_MPLS_UDP) 1075 resp.tunnel_offloads_caps |= 1076 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP; 1077 } 1078 1079 if (uhw->outlen) { 1080 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 1081 1082 if (err) 1083 return err; 1084 } 1085 1086 return 0; 1087 } 1088 1089 enum mlx5_ib_width { 1090 MLX5_IB_WIDTH_1X = 1 << 0, 1091 MLX5_IB_WIDTH_2X = 1 << 1, 1092 MLX5_IB_WIDTH_4X = 1 << 2, 1093 MLX5_IB_WIDTH_8X = 1 << 3, 1094 MLX5_IB_WIDTH_12X = 1 << 4 1095 }; 1096 1097 static int translate_active_width(struct ib_device *ibdev, u8 active_width, 1098 u8 *ib_width) 1099 { 1100 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1101 int err = 0; 1102 1103 if (active_width & MLX5_IB_WIDTH_1X) { 1104 *ib_width = IB_WIDTH_1X; 1105 } else if (active_width & MLX5_IB_WIDTH_2X) { 1106 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n", 1107 (int)active_width); 1108 err = -EINVAL; 1109 } else if (active_width & MLX5_IB_WIDTH_4X) { 1110 *ib_width = IB_WIDTH_4X; 1111 } else if (active_width & MLX5_IB_WIDTH_8X) { 1112 *ib_width = IB_WIDTH_8X; 1113 } else if (active_width & MLX5_IB_WIDTH_12X) { 1114 *ib_width = IB_WIDTH_12X; 1115 } else { 1116 mlx5_ib_dbg(dev, "Invalid active_width %d\n", 1117 (int)active_width); 1118 err = -EINVAL; 1119 } 1120 1121 return err; 1122 } 1123 1124 static int mlx5_mtu_to_ib_mtu(int mtu) 1125 { 1126 switch (mtu) { 1127 case 256: return 1; 1128 case 512: return 2; 1129 case 1024: return 3; 1130 case 2048: return 4; 1131 case 4096: return 5; 1132 default: 1133 pr_warn("invalid mtu\n"); 1134 return -1; 1135 } 1136 } 1137 1138 enum ib_max_vl_num { 1139 __IB_MAX_VL_0 = 1, 1140 __IB_MAX_VL_0_1 = 2, 1141 __IB_MAX_VL_0_3 = 3, 1142 __IB_MAX_VL_0_7 = 4, 1143 __IB_MAX_VL_0_14 = 5, 1144 }; 1145 1146 enum mlx5_vl_hw_cap { 1147 MLX5_VL_HW_0 = 1, 1148 MLX5_VL_HW_0_1 = 2, 1149 MLX5_VL_HW_0_2 = 3, 1150 MLX5_VL_HW_0_3 = 4, 1151 MLX5_VL_HW_0_4 = 5, 1152 MLX5_VL_HW_0_5 = 6, 1153 MLX5_VL_HW_0_6 = 7, 1154 MLX5_VL_HW_0_7 = 8, 1155 MLX5_VL_HW_0_14 = 15 1156 }; 1157 1158 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 1159 u8 *max_vl_num) 1160 { 1161 switch (vl_hw_cap) { 1162 case MLX5_VL_HW_0: 1163 *max_vl_num = __IB_MAX_VL_0; 1164 break; 1165 case MLX5_VL_HW_0_1: 1166 *max_vl_num = __IB_MAX_VL_0_1; 1167 break; 1168 case MLX5_VL_HW_0_3: 1169 *max_vl_num = __IB_MAX_VL_0_3; 1170 break; 1171 case MLX5_VL_HW_0_7: 1172 *max_vl_num = __IB_MAX_VL_0_7; 1173 break; 1174 case MLX5_VL_HW_0_14: 1175 *max_vl_num = __IB_MAX_VL_0_14; 1176 break; 1177 1178 default: 1179 return -EINVAL; 1180 } 1181 1182 return 0; 1183 } 1184 1185 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port, 1186 struct ib_port_attr *props) 1187 { 1188 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1189 struct mlx5_core_dev *mdev = dev->mdev; 1190 struct mlx5_hca_vport_context *rep; 1191 u16 max_mtu; 1192 u16 oper_mtu; 1193 int err; 1194 u8 ib_link_width_oper; 1195 u8 vl_hw_cap; 1196 1197 rep = kzalloc(sizeof(*rep), GFP_KERNEL); 1198 if (!rep) { 1199 err = -ENOMEM; 1200 goto out; 1201 } 1202 1203 /* props being zeroed by the caller, avoid zeroing it here */ 1204 1205 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); 1206 if (err) 1207 goto out; 1208 1209 props->lid = rep->lid; 1210 props->lmc = rep->lmc; 1211 props->sm_lid = rep->sm_lid; 1212 props->sm_sl = rep->sm_sl; 1213 props->state = rep->vport_state; 1214 props->phys_state = rep->port_physical_state; 1215 props->port_cap_flags = rep->cap_mask1; 1216 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 1217 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 1218 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 1219 props->bad_pkey_cntr = rep->pkey_violation_counter; 1220 props->qkey_viol_cntr = rep->qkey_violation_counter; 1221 props->subnet_timeout = rep->subnet_timeout; 1222 props->init_type_reply = rep->init_type_reply; 1223 1224 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port); 1225 if (err) 1226 goto out; 1227 1228 err = translate_active_width(ibdev, ib_link_width_oper, 1229 &props->active_width); 1230 if (err) 1231 goto out; 1232 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port); 1233 if (err) 1234 goto out; 1235 1236 mlx5_query_port_max_mtu(mdev, &max_mtu, port); 1237 1238 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); 1239 1240 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); 1241 1242 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); 1243 1244 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); 1245 if (err) 1246 goto out; 1247 1248 err = translate_max_vl_num(ibdev, vl_hw_cap, 1249 &props->max_vl_num); 1250 out: 1251 kfree(rep); 1252 return err; 1253 } 1254 1255 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 1256 struct ib_port_attr *props) 1257 { 1258 unsigned int count; 1259 int ret; 1260 1261 switch (mlx5_get_vport_access_method(ibdev)) { 1262 case MLX5_VPORT_ACCESS_METHOD_MAD: 1263 ret = mlx5_query_mad_ifc_port(ibdev, port, props); 1264 break; 1265 1266 case MLX5_VPORT_ACCESS_METHOD_HCA: 1267 ret = mlx5_query_hca_port(ibdev, port, props); 1268 break; 1269 1270 case MLX5_VPORT_ACCESS_METHOD_NIC: 1271 ret = mlx5_query_port_roce(ibdev, port, props); 1272 break; 1273 1274 default: 1275 ret = -EINVAL; 1276 } 1277 1278 if (!ret && props) { 1279 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1280 struct mlx5_core_dev *mdev; 1281 bool put_mdev = true; 1282 1283 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL); 1284 if (!mdev) { 1285 /* If the port isn't affiliated yet query the master. 1286 * The master and slave will have the same values. 1287 */ 1288 mdev = dev->mdev; 1289 port = 1; 1290 put_mdev = false; 1291 } 1292 count = mlx5_core_reserved_gids_count(mdev); 1293 if (put_mdev) 1294 mlx5_ib_put_native_port_mdev(dev, port); 1295 props->gid_tbl_len -= count; 1296 } 1297 return ret; 1298 } 1299 1300 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port, 1301 struct ib_port_attr *props) 1302 { 1303 int ret; 1304 1305 /* Only link layer == ethernet is valid for representors */ 1306 ret = mlx5_query_port_roce(ibdev, port, props); 1307 if (ret || !props) 1308 return ret; 1309 1310 /* We don't support GIDS */ 1311 props->gid_tbl_len = 0; 1312 1313 return ret; 1314 } 1315 1316 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 1317 union ib_gid *gid) 1318 { 1319 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1320 struct mlx5_core_dev *mdev = dev->mdev; 1321 1322 switch (mlx5_get_vport_access_method(ibdev)) { 1323 case MLX5_VPORT_ACCESS_METHOD_MAD: 1324 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 1325 1326 case MLX5_VPORT_ACCESS_METHOD_HCA: 1327 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); 1328 1329 default: 1330 return -EINVAL; 1331 } 1332 1333 } 1334 1335 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port, 1336 u16 index, u16 *pkey) 1337 { 1338 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1339 struct mlx5_core_dev *mdev; 1340 bool put_mdev = true; 1341 u8 mdev_port_num; 1342 int err; 1343 1344 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num); 1345 if (!mdev) { 1346 /* The port isn't affiliated yet, get the PKey from the master 1347 * port. For RoCE the PKey tables will be the same. 1348 */ 1349 put_mdev = false; 1350 mdev = dev->mdev; 1351 mdev_port_num = 1; 1352 } 1353 1354 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0, 1355 index, pkey); 1356 if (put_mdev) 1357 mlx5_ib_put_native_port_mdev(dev, port); 1358 1359 return err; 1360 } 1361 1362 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 1363 u16 *pkey) 1364 { 1365 switch (mlx5_get_vport_access_method(ibdev)) { 1366 case MLX5_VPORT_ACCESS_METHOD_MAD: 1367 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 1368 1369 case MLX5_VPORT_ACCESS_METHOD_HCA: 1370 case MLX5_VPORT_ACCESS_METHOD_NIC: 1371 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey); 1372 default: 1373 return -EINVAL; 1374 } 1375 } 1376 1377 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 1378 struct ib_device_modify *props) 1379 { 1380 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1381 struct mlx5_reg_node_desc in; 1382 struct mlx5_reg_node_desc out; 1383 int err; 1384 1385 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 1386 return -EOPNOTSUPP; 1387 1388 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 1389 return 0; 1390 1391 /* 1392 * If possible, pass node desc to FW, so it can generate 1393 * a 144 trap. If cmd fails, just ignore. 1394 */ 1395 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1396 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 1397 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 1398 if (err) 1399 return err; 1400 1401 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1402 1403 return err; 1404 } 1405 1406 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask, 1407 u32 value) 1408 { 1409 struct mlx5_hca_vport_context ctx = {}; 1410 struct mlx5_core_dev *mdev; 1411 u8 mdev_port_num; 1412 int err; 1413 1414 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 1415 if (!mdev) 1416 return -ENODEV; 1417 1418 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx); 1419 if (err) 1420 goto out; 1421 1422 if (~ctx.cap_mask1_perm & mask) { 1423 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n", 1424 mask, ctx.cap_mask1_perm); 1425 err = -EINVAL; 1426 goto out; 1427 } 1428 1429 ctx.cap_mask1 = value; 1430 ctx.cap_mask1_perm = mask; 1431 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num, 1432 0, &ctx); 1433 1434 out: 1435 mlx5_ib_put_native_port_mdev(dev, port_num); 1436 1437 return err; 1438 } 1439 1440 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, 1441 struct ib_port_modify *props) 1442 { 1443 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1444 struct ib_port_attr attr; 1445 u32 tmp; 1446 int err; 1447 u32 change_mask; 1448 u32 value; 1449 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) == 1450 IB_LINK_LAYER_INFINIBAND); 1451 1452 /* CM layer calls ib_modify_port() regardless of the link layer. For 1453 * Ethernet ports, qkey violation and Port capabilities are meaningless. 1454 */ 1455 if (!is_ib) 1456 return 0; 1457 1458 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) { 1459 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask; 1460 value = ~props->clr_port_cap_mask | props->set_port_cap_mask; 1461 return set_port_caps_atomic(dev, port, change_mask, value); 1462 } 1463 1464 mutex_lock(&dev->cap_mask_mutex); 1465 1466 err = ib_query_port(ibdev, port, &attr); 1467 if (err) 1468 goto out; 1469 1470 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 1471 ~props->clr_port_cap_mask; 1472 1473 err = mlx5_set_port_caps(dev->mdev, port, tmp); 1474 1475 out: 1476 mutex_unlock(&dev->cap_mask_mutex); 1477 return err; 1478 } 1479 1480 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps) 1481 { 1482 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n", 1483 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n"); 1484 } 1485 1486 static u16 calc_dynamic_bfregs(int uars_per_sys_page) 1487 { 1488 /* Large page with non 4k uar support might limit the dynamic size */ 1489 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096) 1490 return MLX5_MIN_DYN_BFREGS; 1491 1492 return MLX5_MAX_DYN_BFREGS; 1493 } 1494 1495 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k, 1496 struct mlx5_ib_alloc_ucontext_req_v2 *req, 1497 struct mlx5_bfreg_info *bfregi) 1498 { 1499 int uars_per_sys_page; 1500 int bfregs_per_sys_page; 1501 int ref_bfregs = req->total_num_bfregs; 1502 1503 if (req->total_num_bfregs == 0) 1504 return -EINVAL; 1505 1506 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE); 1507 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE); 1508 1509 if (req->total_num_bfregs > MLX5_MAX_BFREGS) 1510 return -ENOMEM; 1511 1512 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k); 1513 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR; 1514 /* This holds the required static allocation asked by the user */ 1515 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page); 1516 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1) 1517 return -EINVAL; 1518 1519 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page; 1520 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page); 1521 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs; 1522 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page; 1523 1524 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n", 1525 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no", 1526 lib_uar_4k ? "yes" : "no", ref_bfregs, 1527 req->total_num_bfregs, bfregi->total_num_bfregs, 1528 bfregi->num_sys_pages); 1529 1530 return 0; 1531 } 1532 1533 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1534 { 1535 struct mlx5_bfreg_info *bfregi; 1536 int err; 1537 int i; 1538 1539 bfregi = &context->bfregi; 1540 for (i = 0; i < bfregi->num_static_sys_pages; i++) { 1541 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]); 1542 if (err) 1543 goto error; 1544 1545 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]); 1546 } 1547 1548 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++) 1549 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX; 1550 1551 return 0; 1552 1553 error: 1554 for (--i; i >= 0; i--) 1555 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i])) 1556 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1557 1558 return err; 1559 } 1560 1561 static void deallocate_uars(struct mlx5_ib_dev *dev, 1562 struct mlx5_ib_ucontext *context) 1563 { 1564 struct mlx5_bfreg_info *bfregi; 1565 int i; 1566 1567 bfregi = &context->bfregi; 1568 for (i = 0; i < bfregi->num_sys_pages; i++) 1569 if (i < bfregi->num_static_sys_pages || 1570 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) 1571 mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]); 1572 } 1573 1574 static int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev) 1575 { 1576 int err = 0; 1577 1578 mutex_lock(&dev->lb.mutex); 1579 dev->lb.user_td++; 1580 1581 if (dev->lb.user_td == 2) 1582 err = mlx5_nic_vport_update_local_lb(dev->mdev, true); 1583 1584 mutex_unlock(&dev->lb.mutex); 1585 1586 return err; 1587 } 1588 1589 static void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev) 1590 { 1591 mutex_lock(&dev->lb.mutex); 1592 dev->lb.user_td--; 1593 1594 if (dev->lb.user_td < 2) 1595 mlx5_nic_vport_update_local_lb(dev->mdev, false); 1596 1597 mutex_unlock(&dev->lb.mutex); 1598 } 1599 1600 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn) 1601 { 1602 int err; 1603 1604 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1605 return 0; 1606 1607 err = mlx5_core_alloc_transport_domain(dev->mdev, tdn); 1608 if (err) 1609 return err; 1610 1611 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1612 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1613 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1614 return err; 1615 1616 return mlx5_ib_enable_lb(dev); 1617 } 1618 1619 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn) 1620 { 1621 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1622 return; 1623 1624 mlx5_core_dealloc_transport_domain(dev->mdev, tdn); 1625 1626 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1627 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1628 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1629 return; 1630 1631 mlx5_ib_disable_lb(dev); 1632 } 1633 1634 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev, 1635 struct ib_udata *udata) 1636 { 1637 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1638 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 1639 struct mlx5_ib_alloc_ucontext_resp resp = {}; 1640 struct mlx5_core_dev *mdev = dev->mdev; 1641 struct mlx5_ib_ucontext *context; 1642 struct mlx5_bfreg_info *bfregi; 1643 int ver; 1644 int err; 1645 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 1646 max_cqe_version); 1647 u32 dump_fill_mkey; 1648 bool lib_uar_4k; 1649 1650 if (!dev->ib_active) 1651 return ERR_PTR(-EAGAIN); 1652 1653 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 1654 ver = 0; 1655 else if (udata->inlen >= min_req_v2) 1656 ver = 2; 1657 else 1658 return ERR_PTR(-EINVAL); 1659 1660 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req))); 1661 if (err) 1662 return ERR_PTR(err); 1663 1664 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX) 1665 return ERR_PTR(-EOPNOTSUPP); 1666 1667 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 1668 return ERR_PTR(-EOPNOTSUPP); 1669 1670 req.total_num_bfregs = ALIGN(req.total_num_bfregs, 1671 MLX5_NON_FP_BFREGS_PER_UAR); 1672 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1) 1673 return ERR_PTR(-EINVAL); 1674 1675 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 1676 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf)) 1677 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size); 1678 resp.cache_line_size = cache_line_size(); 1679 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 1680 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 1681 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1682 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1683 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 1684 resp.cqe_version = min_t(__u8, 1685 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 1686 req.max_cqe_version); 1687 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1688 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT; 1689 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1690 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1; 1691 resp.response_length = min(offsetof(typeof(resp), response_length) + 1692 sizeof(resp.response_length), udata->outlen); 1693 1694 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE) { 1695 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_EGRESS)) 1696 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM; 1697 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA) 1698 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA; 1699 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi)) 1700 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING; 1701 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN) 1702 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN; 1703 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */ 1704 } 1705 1706 context = kzalloc(sizeof(*context), GFP_KERNEL); 1707 if (!context) 1708 return ERR_PTR(-ENOMEM); 1709 1710 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR; 1711 bfregi = &context->bfregi; 1712 1713 /* updates req->total_num_bfregs */ 1714 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi); 1715 if (err) 1716 goto out_ctx; 1717 1718 mutex_init(&bfregi->lock); 1719 bfregi->lib_uar_4k = lib_uar_4k; 1720 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count), 1721 GFP_KERNEL); 1722 if (!bfregi->count) { 1723 err = -ENOMEM; 1724 goto out_ctx; 1725 } 1726 1727 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages, 1728 sizeof(*bfregi->sys_pages), 1729 GFP_KERNEL); 1730 if (!bfregi->sys_pages) { 1731 err = -ENOMEM; 1732 goto out_count; 1733 } 1734 1735 err = allocate_uars(dev, context); 1736 if (err) 1737 goto out_sys_pages; 1738 1739 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1740 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range; 1741 #endif 1742 1743 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn); 1744 if (err) 1745 goto out_uars; 1746 1747 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) { 1748 /* Block DEVX on Infiniband as of SELinux */ 1749 if (mlx5_ib_port_link_layer(ibdev, 1) != IB_LINK_LAYER_ETHERNET) { 1750 err = -EPERM; 1751 goto out_td; 1752 } 1753 1754 err = mlx5_ib_devx_create(dev, context); 1755 if (err) 1756 goto out_td; 1757 } 1758 1759 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) { 1760 err = mlx5_cmd_dump_fill_mkey(dev->mdev, &dump_fill_mkey); 1761 if (err) 1762 goto out_mdev; 1763 } 1764 1765 INIT_LIST_HEAD(&context->vma_private_list); 1766 mutex_init(&context->vma_private_list_mutex); 1767 INIT_LIST_HEAD(&context->db_page_list); 1768 mutex_init(&context->db_page_mutex); 1769 1770 resp.tot_bfregs = req.total_num_bfregs; 1771 resp.num_ports = dev->num_ports; 1772 1773 if (field_avail(typeof(resp), cqe_version, udata->outlen)) 1774 resp.response_length += sizeof(resp.cqe_version); 1775 1776 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) { 1777 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 1778 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 1779 resp.response_length += sizeof(resp.cmds_supp_uhw); 1780 } 1781 1782 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) { 1783 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) { 1784 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline); 1785 resp.eth_min_inline++; 1786 } 1787 resp.response_length += sizeof(resp.eth_min_inline); 1788 } 1789 1790 if (field_avail(typeof(resp), clock_info_versions, udata->outlen)) { 1791 if (mdev->clock_info) 1792 resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1); 1793 resp.response_length += sizeof(resp.clock_info_versions); 1794 } 1795 1796 /* 1797 * We don't want to expose information from the PCI bar that is located 1798 * after 4096 bytes, so if the arch only supports larger pages, let's 1799 * pretend we don't support reading the HCA's core clock. This is also 1800 * forced by mmap function. 1801 */ 1802 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) { 1803 if (PAGE_SIZE <= 4096) { 1804 resp.comp_mask |= 1805 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 1806 resp.hca_core_clock_offset = 1807 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE; 1808 } 1809 resp.response_length += sizeof(resp.hca_core_clock_offset); 1810 } 1811 1812 if (field_avail(typeof(resp), log_uar_size, udata->outlen)) 1813 resp.response_length += sizeof(resp.log_uar_size); 1814 1815 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen)) 1816 resp.response_length += sizeof(resp.num_uars_per_page); 1817 1818 if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) { 1819 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs; 1820 resp.response_length += sizeof(resp.num_dyn_bfregs); 1821 } 1822 1823 if (field_avail(typeof(resp), dump_fill_mkey, udata->outlen)) { 1824 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) { 1825 resp.dump_fill_mkey = dump_fill_mkey; 1826 resp.comp_mask |= 1827 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY; 1828 } 1829 resp.response_length += sizeof(resp.dump_fill_mkey); 1830 } 1831 1832 err = ib_copy_to_udata(udata, &resp, resp.response_length); 1833 if (err) 1834 goto out_mdev; 1835 1836 bfregi->ver = ver; 1837 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs; 1838 context->cqe_version = resp.cqe_version; 1839 context->lib_caps = req.lib_caps; 1840 print_lib_caps(dev, context->lib_caps); 1841 1842 return &context->ibucontext; 1843 1844 out_mdev: 1845 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) 1846 mlx5_ib_devx_destroy(dev, context); 1847 out_td: 1848 mlx5_ib_dealloc_transport_domain(dev, context->tdn); 1849 1850 out_uars: 1851 deallocate_uars(dev, context); 1852 1853 out_sys_pages: 1854 kfree(bfregi->sys_pages); 1855 1856 out_count: 1857 kfree(bfregi->count); 1858 1859 out_ctx: 1860 kfree(context); 1861 1862 return ERR_PTR(err); 1863 } 1864 1865 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1866 { 1867 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1868 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1869 struct mlx5_bfreg_info *bfregi; 1870 1871 if (context->devx_uid) 1872 mlx5_ib_devx_destroy(dev, context); 1873 1874 bfregi = &context->bfregi; 1875 mlx5_ib_dealloc_transport_domain(dev, context->tdn); 1876 1877 deallocate_uars(dev, context); 1878 kfree(bfregi->sys_pages); 1879 kfree(bfregi->count); 1880 kfree(context); 1881 1882 return 0; 1883 } 1884 1885 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, 1886 int uar_idx) 1887 { 1888 int fw_uars_per_page; 1889 1890 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1; 1891 1892 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + uar_idx / fw_uars_per_page; 1893 } 1894 1895 static int get_command(unsigned long offset) 1896 { 1897 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 1898 } 1899 1900 static int get_arg(unsigned long offset) 1901 { 1902 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 1903 } 1904 1905 static int get_index(unsigned long offset) 1906 { 1907 return get_arg(offset); 1908 } 1909 1910 /* Index resides in an extra byte to enable larger values than 255 */ 1911 static int get_extended_index(unsigned long offset) 1912 { 1913 return get_arg(offset) | ((offset >> 16) & 0xff) << 8; 1914 } 1915 1916 static void mlx5_ib_vma_open(struct vm_area_struct *area) 1917 { 1918 /* vma_open is called when a new VMA is created on top of our VMA. This 1919 * is done through either mremap flow or split_vma (usually due to 1920 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA, 1921 * as this VMA is strongly hardware related. Therefore we set the 1922 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from 1923 * calling us again and trying to do incorrect actions. We assume that 1924 * the original VMA size is exactly a single page, and therefore all 1925 * "splitting" operation will not happen to it. 1926 */ 1927 area->vm_ops = NULL; 1928 } 1929 1930 static void mlx5_ib_vma_close(struct vm_area_struct *area) 1931 { 1932 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data; 1933 1934 /* It's guaranteed that all VMAs opened on a FD are closed before the 1935 * file itself is closed, therefore no sync is needed with the regular 1936 * closing flow. (e.g. mlx5 ib_dealloc_ucontext) 1937 * However need a sync with accessing the vma as part of 1938 * mlx5_ib_disassociate_ucontext. 1939 * The close operation is usually called under mm->mmap_sem except when 1940 * process is exiting. 1941 * The exiting case is handled explicitly as part of 1942 * mlx5_ib_disassociate_ucontext. 1943 */ 1944 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data; 1945 1946 /* setting the vma context pointer to null in the mlx5_ib driver's 1947 * private data, to protect a race condition in 1948 * mlx5_ib_disassociate_ucontext(). 1949 */ 1950 mlx5_ib_vma_priv_data->vma = NULL; 1951 mutex_lock(mlx5_ib_vma_priv_data->vma_private_list_mutex); 1952 list_del(&mlx5_ib_vma_priv_data->list); 1953 mutex_unlock(mlx5_ib_vma_priv_data->vma_private_list_mutex); 1954 kfree(mlx5_ib_vma_priv_data); 1955 } 1956 1957 static const struct vm_operations_struct mlx5_ib_vm_ops = { 1958 .open = mlx5_ib_vma_open, 1959 .close = mlx5_ib_vma_close 1960 }; 1961 1962 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma, 1963 struct mlx5_ib_ucontext *ctx) 1964 { 1965 struct mlx5_ib_vma_private_data *vma_prv; 1966 struct list_head *vma_head = &ctx->vma_private_list; 1967 1968 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL); 1969 if (!vma_prv) 1970 return -ENOMEM; 1971 1972 vma_prv->vma = vma; 1973 vma_prv->vma_private_list_mutex = &ctx->vma_private_list_mutex; 1974 vma->vm_private_data = vma_prv; 1975 vma->vm_ops = &mlx5_ib_vm_ops; 1976 1977 mutex_lock(&ctx->vma_private_list_mutex); 1978 list_add(&vma_prv->list, vma_head); 1979 mutex_unlock(&ctx->vma_private_list_mutex); 1980 1981 return 0; 1982 } 1983 1984 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 1985 { 1986 struct vm_area_struct *vma; 1987 struct mlx5_ib_vma_private_data *vma_private, *n; 1988 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1989 1990 mutex_lock(&context->vma_private_list_mutex); 1991 list_for_each_entry_safe(vma_private, n, &context->vma_private_list, 1992 list) { 1993 vma = vma_private->vma; 1994 zap_vma_ptes(vma, vma->vm_start, PAGE_SIZE); 1995 /* context going to be destroyed, should 1996 * not access ops any more. 1997 */ 1998 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE); 1999 vma->vm_ops = NULL; 2000 list_del(&vma_private->list); 2001 kfree(vma_private); 2002 } 2003 mutex_unlock(&context->vma_private_list_mutex); 2004 } 2005 2006 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 2007 { 2008 switch (cmd) { 2009 case MLX5_IB_MMAP_WC_PAGE: 2010 return "WC"; 2011 case MLX5_IB_MMAP_REGULAR_PAGE: 2012 return "best effort WC"; 2013 case MLX5_IB_MMAP_NC_PAGE: 2014 return "NC"; 2015 case MLX5_IB_MMAP_DEVICE_MEM: 2016 return "Device Memory"; 2017 default: 2018 return NULL; 2019 } 2020 } 2021 2022 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev, 2023 struct vm_area_struct *vma, 2024 struct mlx5_ib_ucontext *context) 2025 { 2026 phys_addr_t pfn; 2027 int err; 2028 2029 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2030 return -EINVAL; 2031 2032 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1) 2033 return -EOPNOTSUPP; 2034 2035 if (vma->vm_flags & VM_WRITE) 2036 return -EPERM; 2037 2038 if (!dev->mdev->clock_info_page) 2039 return -EOPNOTSUPP; 2040 2041 pfn = page_to_pfn(dev->mdev->clock_info_page); 2042 err = remap_pfn_range(vma, vma->vm_start, pfn, PAGE_SIZE, 2043 vma->vm_page_prot); 2044 if (err) 2045 return err; 2046 2047 return mlx5_ib_set_vma_data(vma, context); 2048 } 2049 2050 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 2051 struct vm_area_struct *vma, 2052 struct mlx5_ib_ucontext *context) 2053 { 2054 struct mlx5_bfreg_info *bfregi = &context->bfregi; 2055 int err; 2056 unsigned long idx; 2057 phys_addr_t pfn; 2058 pgprot_t prot; 2059 u32 bfreg_dyn_idx = 0; 2060 u32 uar_index; 2061 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC); 2062 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages : 2063 bfregi->num_static_sys_pages; 2064 2065 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2066 return -EINVAL; 2067 2068 if (dyn_uar) 2069 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages; 2070 else 2071 idx = get_index(vma->vm_pgoff); 2072 2073 if (idx >= max_valid_idx) { 2074 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n", 2075 idx, max_valid_idx); 2076 return -EINVAL; 2077 } 2078 2079 switch (cmd) { 2080 case MLX5_IB_MMAP_WC_PAGE: 2081 case MLX5_IB_MMAP_ALLOC_WC: 2082 /* Some architectures don't support WC memory */ 2083 #if defined(CONFIG_X86) 2084 if (!pat_enabled()) 2085 return -EPERM; 2086 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU))) 2087 return -EPERM; 2088 #endif 2089 /* fall through */ 2090 case MLX5_IB_MMAP_REGULAR_PAGE: 2091 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 2092 prot = pgprot_writecombine(vma->vm_page_prot); 2093 break; 2094 case MLX5_IB_MMAP_NC_PAGE: 2095 prot = pgprot_noncached(vma->vm_page_prot); 2096 break; 2097 default: 2098 return -EINVAL; 2099 } 2100 2101 if (dyn_uar) { 2102 int uars_per_page; 2103 2104 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k); 2105 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR); 2106 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) { 2107 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n", 2108 bfreg_dyn_idx, bfregi->total_num_bfregs); 2109 return -EINVAL; 2110 } 2111 2112 mutex_lock(&bfregi->lock); 2113 /* Fail if uar already allocated, first bfreg index of each 2114 * page holds its count. 2115 */ 2116 if (bfregi->count[bfreg_dyn_idx]) { 2117 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx); 2118 mutex_unlock(&bfregi->lock); 2119 return -EINVAL; 2120 } 2121 2122 bfregi->count[bfreg_dyn_idx]++; 2123 mutex_unlock(&bfregi->lock); 2124 2125 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index); 2126 if (err) { 2127 mlx5_ib_warn(dev, "UAR alloc failed\n"); 2128 goto free_bfreg; 2129 } 2130 } else { 2131 uar_index = bfregi->sys_pages[idx]; 2132 } 2133 2134 pfn = uar_index2pfn(dev, uar_index); 2135 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 2136 2137 vma->vm_page_prot = prot; 2138 err = io_remap_pfn_range(vma, vma->vm_start, pfn, 2139 PAGE_SIZE, vma->vm_page_prot); 2140 if (err) { 2141 mlx5_ib_err(dev, 2142 "io_remap_pfn_range failed with error=%d, mmap_cmd=%s\n", 2143 err, mmap_cmd2str(cmd)); 2144 err = -EAGAIN; 2145 goto err; 2146 } 2147 2148 err = mlx5_ib_set_vma_data(vma, context); 2149 if (err) 2150 goto err; 2151 2152 if (dyn_uar) 2153 bfregi->sys_pages[idx] = uar_index; 2154 return 0; 2155 2156 err: 2157 if (!dyn_uar) 2158 return err; 2159 2160 mlx5_cmd_free_uar(dev->mdev, idx); 2161 2162 free_bfreg: 2163 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx); 2164 2165 return err; 2166 } 2167 2168 static int dm_mmap(struct ib_ucontext *context, struct vm_area_struct *vma) 2169 { 2170 struct mlx5_ib_ucontext *mctx = to_mucontext(context); 2171 struct mlx5_ib_dev *dev = to_mdev(context->device); 2172 u16 page_idx = get_extended_index(vma->vm_pgoff); 2173 size_t map_size = vma->vm_end - vma->vm_start; 2174 u32 npages = map_size >> PAGE_SHIFT; 2175 phys_addr_t pfn; 2176 pgprot_t prot; 2177 2178 if (find_next_zero_bit(mctx->dm_pages, page_idx + npages, page_idx) != 2179 page_idx + npages) 2180 return -EINVAL; 2181 2182 pfn = ((pci_resource_start(dev->mdev->pdev, 0) + 2183 MLX5_CAP64_DEV_MEM(dev->mdev, memic_bar_start_addr)) >> 2184 PAGE_SHIFT) + 2185 page_idx; 2186 prot = pgprot_writecombine(vma->vm_page_prot); 2187 vma->vm_page_prot = prot; 2188 2189 if (io_remap_pfn_range(vma, vma->vm_start, pfn, map_size, 2190 vma->vm_page_prot)) 2191 return -EAGAIN; 2192 2193 return mlx5_ib_set_vma_data(vma, mctx); 2194 } 2195 2196 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 2197 { 2198 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2199 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2200 unsigned long command; 2201 phys_addr_t pfn; 2202 2203 command = get_command(vma->vm_pgoff); 2204 switch (command) { 2205 case MLX5_IB_MMAP_WC_PAGE: 2206 case MLX5_IB_MMAP_NC_PAGE: 2207 case MLX5_IB_MMAP_REGULAR_PAGE: 2208 case MLX5_IB_MMAP_ALLOC_WC: 2209 return uar_mmap(dev, command, vma, context); 2210 2211 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 2212 return -ENOSYS; 2213 2214 case MLX5_IB_MMAP_CORE_CLOCK: 2215 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2216 return -EINVAL; 2217 2218 if (vma->vm_flags & VM_WRITE) 2219 return -EPERM; 2220 2221 /* Don't expose to user-space information it shouldn't have */ 2222 if (PAGE_SIZE > 4096) 2223 return -EOPNOTSUPP; 2224 2225 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 2226 pfn = (dev->mdev->iseg_base + 2227 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 2228 PAGE_SHIFT; 2229 if (io_remap_pfn_range(vma, vma->vm_start, pfn, 2230 PAGE_SIZE, vma->vm_page_prot)) 2231 return -EAGAIN; 2232 break; 2233 case MLX5_IB_MMAP_CLOCK_INFO: 2234 return mlx5_ib_mmap_clock_info_page(dev, vma, context); 2235 2236 case MLX5_IB_MMAP_DEVICE_MEM: 2237 return dm_mmap(ibcontext, vma); 2238 2239 default: 2240 return -EINVAL; 2241 } 2242 2243 return 0; 2244 } 2245 2246 struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev, 2247 struct ib_ucontext *context, 2248 struct ib_dm_alloc_attr *attr, 2249 struct uverbs_attr_bundle *attrs) 2250 { 2251 u64 act_size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE); 2252 struct mlx5_memic *memic = &to_mdev(ibdev)->memic; 2253 phys_addr_t memic_addr; 2254 struct mlx5_ib_dm *dm; 2255 u64 start_offset; 2256 u32 page_idx; 2257 int err; 2258 2259 dm = kzalloc(sizeof(*dm), GFP_KERNEL); 2260 if (!dm) 2261 return ERR_PTR(-ENOMEM); 2262 2263 mlx5_ib_dbg(to_mdev(ibdev), "alloc_memic req: user_length=0x%llx act_length=0x%llx log_alignment=%d\n", 2264 attr->length, act_size, attr->alignment); 2265 2266 err = mlx5_cmd_alloc_memic(memic, &memic_addr, 2267 act_size, attr->alignment); 2268 if (err) 2269 goto err_free; 2270 2271 start_offset = memic_addr & ~PAGE_MASK; 2272 page_idx = (memic_addr - pci_resource_start(memic->dev->pdev, 0) - 2273 MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >> 2274 PAGE_SHIFT; 2275 2276 err = uverbs_copy_to(attrs, 2277 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET, 2278 &start_offset, sizeof(start_offset)); 2279 if (err) 2280 goto err_dealloc; 2281 2282 err = uverbs_copy_to(attrs, 2283 MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX, 2284 &page_idx, sizeof(page_idx)); 2285 if (err) 2286 goto err_dealloc; 2287 2288 bitmap_set(to_mucontext(context)->dm_pages, page_idx, 2289 DIV_ROUND_UP(act_size, PAGE_SIZE)); 2290 2291 dm->dev_addr = memic_addr; 2292 2293 return &dm->ibdm; 2294 2295 err_dealloc: 2296 mlx5_cmd_dealloc_memic(memic, memic_addr, 2297 act_size); 2298 err_free: 2299 kfree(dm); 2300 return ERR_PTR(err); 2301 } 2302 2303 int mlx5_ib_dealloc_dm(struct ib_dm *ibdm) 2304 { 2305 struct mlx5_memic *memic = &to_mdev(ibdm->device)->memic; 2306 struct mlx5_ib_dm *dm = to_mdm(ibdm); 2307 u64 act_size = roundup(dm->ibdm.length, MLX5_MEMIC_BASE_SIZE); 2308 u32 page_idx; 2309 int ret; 2310 2311 ret = mlx5_cmd_dealloc_memic(memic, dm->dev_addr, act_size); 2312 if (ret) 2313 return ret; 2314 2315 page_idx = (dm->dev_addr - pci_resource_start(memic->dev->pdev, 0) - 2316 MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >> 2317 PAGE_SHIFT; 2318 bitmap_clear(to_mucontext(ibdm->uobject->context)->dm_pages, 2319 page_idx, 2320 DIV_ROUND_UP(act_size, PAGE_SIZE)); 2321 2322 kfree(dm); 2323 2324 return 0; 2325 } 2326 2327 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev, 2328 struct ib_ucontext *context, 2329 struct ib_udata *udata) 2330 { 2331 struct mlx5_ib_alloc_pd_resp resp; 2332 struct mlx5_ib_pd *pd; 2333 int err; 2334 2335 pd = kmalloc(sizeof(*pd), GFP_KERNEL); 2336 if (!pd) 2337 return ERR_PTR(-ENOMEM); 2338 2339 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn); 2340 if (err) { 2341 kfree(pd); 2342 return ERR_PTR(err); 2343 } 2344 2345 if (context) { 2346 resp.pdn = pd->pdn; 2347 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 2348 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn); 2349 kfree(pd); 2350 return ERR_PTR(-EFAULT); 2351 } 2352 } 2353 2354 return &pd->ibpd; 2355 } 2356 2357 static int mlx5_ib_dealloc_pd(struct ib_pd *pd) 2358 { 2359 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 2360 struct mlx5_ib_pd *mpd = to_mpd(pd); 2361 2362 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn); 2363 kfree(mpd); 2364 2365 return 0; 2366 } 2367 2368 enum { 2369 MATCH_CRITERIA_ENABLE_OUTER_BIT, 2370 MATCH_CRITERIA_ENABLE_MISC_BIT, 2371 MATCH_CRITERIA_ENABLE_INNER_BIT, 2372 MATCH_CRITERIA_ENABLE_MISC2_BIT 2373 }; 2374 2375 #define HEADER_IS_ZERO(match_criteria, headers) \ 2376 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \ 2377 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \ 2378 2379 static u8 get_match_criteria_enable(u32 *match_criteria) 2380 { 2381 u8 match_criteria_enable; 2382 2383 match_criteria_enable = 2384 (!HEADER_IS_ZERO(match_criteria, outer_headers)) << 2385 MATCH_CRITERIA_ENABLE_OUTER_BIT; 2386 match_criteria_enable |= 2387 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) << 2388 MATCH_CRITERIA_ENABLE_MISC_BIT; 2389 match_criteria_enable |= 2390 (!HEADER_IS_ZERO(match_criteria, inner_headers)) << 2391 MATCH_CRITERIA_ENABLE_INNER_BIT; 2392 match_criteria_enable |= 2393 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) << 2394 MATCH_CRITERIA_ENABLE_MISC2_BIT; 2395 2396 return match_criteria_enable; 2397 } 2398 2399 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val) 2400 { 2401 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask); 2402 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val); 2403 } 2404 2405 static void set_flow_label(void *misc_c, void *misc_v, u32 mask, u32 val, 2406 bool inner) 2407 { 2408 if (inner) { 2409 MLX5_SET(fte_match_set_misc, 2410 misc_c, inner_ipv6_flow_label, mask); 2411 MLX5_SET(fte_match_set_misc, 2412 misc_v, inner_ipv6_flow_label, val); 2413 } else { 2414 MLX5_SET(fte_match_set_misc, 2415 misc_c, outer_ipv6_flow_label, mask); 2416 MLX5_SET(fte_match_set_misc, 2417 misc_v, outer_ipv6_flow_label, val); 2418 } 2419 } 2420 2421 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val) 2422 { 2423 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask); 2424 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val); 2425 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2); 2426 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2); 2427 } 2428 2429 static int check_mpls_supp_fields(u32 field_support, const __be32 *set_mask) 2430 { 2431 if (MLX5_GET(fte_match_mpls, set_mask, mpls_label) && 2432 !(field_support & MLX5_FIELD_SUPPORT_MPLS_LABEL)) 2433 return -EOPNOTSUPP; 2434 2435 if (MLX5_GET(fte_match_mpls, set_mask, mpls_exp) && 2436 !(field_support & MLX5_FIELD_SUPPORT_MPLS_EXP)) 2437 return -EOPNOTSUPP; 2438 2439 if (MLX5_GET(fte_match_mpls, set_mask, mpls_s_bos) && 2440 !(field_support & MLX5_FIELD_SUPPORT_MPLS_S_BOS)) 2441 return -EOPNOTSUPP; 2442 2443 if (MLX5_GET(fte_match_mpls, set_mask, mpls_ttl) && 2444 !(field_support & MLX5_FIELD_SUPPORT_MPLS_TTL)) 2445 return -EOPNOTSUPP; 2446 2447 return 0; 2448 } 2449 2450 #define LAST_ETH_FIELD vlan_tag 2451 #define LAST_IB_FIELD sl 2452 #define LAST_IPV4_FIELD tos 2453 #define LAST_IPV6_FIELD traffic_class 2454 #define LAST_TCP_UDP_FIELD src_port 2455 #define LAST_TUNNEL_FIELD tunnel_id 2456 #define LAST_FLOW_TAG_FIELD tag_id 2457 #define LAST_DROP_FIELD size 2458 #define LAST_COUNTERS_FIELD counters 2459 2460 /* Field is the last supported field */ 2461 #define FIELDS_NOT_SUPPORTED(filter, field)\ 2462 memchr_inv((void *)&filter.field +\ 2463 sizeof(filter.field), 0,\ 2464 sizeof(filter) -\ 2465 offsetof(typeof(filter), field) -\ 2466 sizeof(filter.field)) 2467 2468 static int parse_flow_flow_action(const union ib_flow_spec *ib_spec, 2469 const struct ib_flow_attr *flow_attr, 2470 struct mlx5_flow_act *action) 2471 { 2472 struct mlx5_ib_flow_action *maction = to_mflow_act(ib_spec->action.act); 2473 2474 switch (maction->ib_action.type) { 2475 case IB_FLOW_ACTION_ESP: 2476 /* Currently only AES_GCM keymat is supported by the driver */ 2477 action->esp_id = (uintptr_t)maction->esp_aes_gcm.ctx; 2478 action->action |= flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS ? 2479 MLX5_FLOW_CONTEXT_ACTION_ENCRYPT : 2480 MLX5_FLOW_CONTEXT_ACTION_DECRYPT; 2481 return 0; 2482 default: 2483 return -EOPNOTSUPP; 2484 } 2485 } 2486 2487 static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c, 2488 u32 *match_v, const union ib_flow_spec *ib_spec, 2489 const struct ib_flow_attr *flow_attr, 2490 struct mlx5_flow_act *action, u32 prev_type) 2491 { 2492 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c, 2493 misc_parameters); 2494 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v, 2495 misc_parameters); 2496 void *misc_params2_c = MLX5_ADDR_OF(fte_match_param, match_c, 2497 misc_parameters_2); 2498 void *misc_params2_v = MLX5_ADDR_OF(fte_match_param, match_v, 2499 misc_parameters_2); 2500 void *headers_c; 2501 void *headers_v; 2502 int match_ipv; 2503 int ret; 2504 2505 if (ib_spec->type & IB_FLOW_SPEC_INNER) { 2506 headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 2507 inner_headers); 2508 headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 2509 inner_headers); 2510 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2511 ft_field_support.inner_ip_version); 2512 } else { 2513 headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 2514 outer_headers); 2515 headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 2516 outer_headers); 2517 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2518 ft_field_support.outer_ip_version); 2519 } 2520 2521 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) { 2522 case IB_FLOW_SPEC_ETH: 2523 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD)) 2524 return -EOPNOTSUPP; 2525 2526 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2527 dmac_47_16), 2528 ib_spec->eth.mask.dst_mac); 2529 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2530 dmac_47_16), 2531 ib_spec->eth.val.dst_mac); 2532 2533 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2534 smac_47_16), 2535 ib_spec->eth.mask.src_mac); 2536 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2537 smac_47_16), 2538 ib_spec->eth.val.src_mac); 2539 2540 if (ib_spec->eth.mask.vlan_tag) { 2541 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2542 cvlan_tag, 1); 2543 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2544 cvlan_tag, 1); 2545 2546 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2547 first_vid, ntohs(ib_spec->eth.mask.vlan_tag)); 2548 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2549 first_vid, ntohs(ib_spec->eth.val.vlan_tag)); 2550 2551 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2552 first_cfi, 2553 ntohs(ib_spec->eth.mask.vlan_tag) >> 12); 2554 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2555 first_cfi, 2556 ntohs(ib_spec->eth.val.vlan_tag) >> 12); 2557 2558 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2559 first_prio, 2560 ntohs(ib_spec->eth.mask.vlan_tag) >> 13); 2561 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2562 first_prio, 2563 ntohs(ib_spec->eth.val.vlan_tag) >> 13); 2564 } 2565 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2566 ethertype, ntohs(ib_spec->eth.mask.ether_type)); 2567 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2568 ethertype, ntohs(ib_spec->eth.val.ether_type)); 2569 break; 2570 case IB_FLOW_SPEC_IPV4: 2571 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD)) 2572 return -EOPNOTSUPP; 2573 2574 if (match_ipv) { 2575 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2576 ip_version, 0xf); 2577 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2578 ip_version, MLX5_FS_IPV4_VERSION); 2579 } else { 2580 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2581 ethertype, 0xffff); 2582 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2583 ethertype, ETH_P_IP); 2584 } 2585 2586 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2587 src_ipv4_src_ipv6.ipv4_layout.ipv4), 2588 &ib_spec->ipv4.mask.src_ip, 2589 sizeof(ib_spec->ipv4.mask.src_ip)); 2590 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2591 src_ipv4_src_ipv6.ipv4_layout.ipv4), 2592 &ib_spec->ipv4.val.src_ip, 2593 sizeof(ib_spec->ipv4.val.src_ip)); 2594 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2595 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 2596 &ib_spec->ipv4.mask.dst_ip, 2597 sizeof(ib_spec->ipv4.mask.dst_ip)); 2598 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2599 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 2600 &ib_spec->ipv4.val.dst_ip, 2601 sizeof(ib_spec->ipv4.val.dst_ip)); 2602 2603 set_tos(headers_c, headers_v, 2604 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos); 2605 2606 set_proto(headers_c, headers_v, 2607 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto); 2608 break; 2609 case IB_FLOW_SPEC_IPV6: 2610 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD)) 2611 return -EOPNOTSUPP; 2612 2613 if (match_ipv) { 2614 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2615 ip_version, 0xf); 2616 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2617 ip_version, MLX5_FS_IPV6_VERSION); 2618 } else { 2619 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2620 ethertype, 0xffff); 2621 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2622 ethertype, ETH_P_IPV6); 2623 } 2624 2625 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2626 src_ipv4_src_ipv6.ipv6_layout.ipv6), 2627 &ib_spec->ipv6.mask.src_ip, 2628 sizeof(ib_spec->ipv6.mask.src_ip)); 2629 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2630 src_ipv4_src_ipv6.ipv6_layout.ipv6), 2631 &ib_spec->ipv6.val.src_ip, 2632 sizeof(ib_spec->ipv6.val.src_ip)); 2633 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2634 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 2635 &ib_spec->ipv6.mask.dst_ip, 2636 sizeof(ib_spec->ipv6.mask.dst_ip)); 2637 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2638 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 2639 &ib_spec->ipv6.val.dst_ip, 2640 sizeof(ib_spec->ipv6.val.dst_ip)); 2641 2642 set_tos(headers_c, headers_v, 2643 ib_spec->ipv6.mask.traffic_class, 2644 ib_spec->ipv6.val.traffic_class); 2645 2646 set_proto(headers_c, headers_v, 2647 ib_spec->ipv6.mask.next_hdr, 2648 ib_spec->ipv6.val.next_hdr); 2649 2650 set_flow_label(misc_params_c, misc_params_v, 2651 ntohl(ib_spec->ipv6.mask.flow_label), 2652 ntohl(ib_spec->ipv6.val.flow_label), 2653 ib_spec->type & IB_FLOW_SPEC_INNER); 2654 break; 2655 case IB_FLOW_SPEC_ESP: 2656 if (ib_spec->esp.mask.seq) 2657 return -EOPNOTSUPP; 2658 2659 MLX5_SET(fte_match_set_misc, misc_params_c, outer_esp_spi, 2660 ntohl(ib_spec->esp.mask.spi)); 2661 MLX5_SET(fte_match_set_misc, misc_params_v, outer_esp_spi, 2662 ntohl(ib_spec->esp.val.spi)); 2663 break; 2664 case IB_FLOW_SPEC_TCP: 2665 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 2666 LAST_TCP_UDP_FIELD)) 2667 return -EOPNOTSUPP; 2668 2669 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol, 2670 0xff); 2671 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, 2672 IPPROTO_TCP); 2673 2674 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport, 2675 ntohs(ib_spec->tcp_udp.mask.src_port)); 2676 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport, 2677 ntohs(ib_spec->tcp_udp.val.src_port)); 2678 2679 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport, 2680 ntohs(ib_spec->tcp_udp.mask.dst_port)); 2681 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport, 2682 ntohs(ib_spec->tcp_udp.val.dst_port)); 2683 break; 2684 case IB_FLOW_SPEC_UDP: 2685 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 2686 LAST_TCP_UDP_FIELD)) 2687 return -EOPNOTSUPP; 2688 2689 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol, 2690 0xff); 2691 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, 2692 IPPROTO_UDP); 2693 2694 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport, 2695 ntohs(ib_spec->tcp_udp.mask.src_port)); 2696 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport, 2697 ntohs(ib_spec->tcp_udp.val.src_port)); 2698 2699 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport, 2700 ntohs(ib_spec->tcp_udp.mask.dst_port)); 2701 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, 2702 ntohs(ib_spec->tcp_udp.val.dst_port)); 2703 break; 2704 case IB_FLOW_SPEC_GRE: 2705 if (ib_spec->gre.mask.c_ks_res0_ver) 2706 return -EOPNOTSUPP; 2707 2708 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol, 2709 0xff); 2710 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, 2711 IPPROTO_GRE); 2712 2713 MLX5_SET(fte_match_set_misc, misc_params_c, gre_protocol, 2714 ntohs(ib_spec->gre.mask.protocol)); 2715 MLX5_SET(fte_match_set_misc, misc_params_v, gre_protocol, 2716 ntohs(ib_spec->gre.val.protocol)); 2717 2718 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_c, 2719 gre_key_h), 2720 &ib_spec->gre.mask.key, 2721 sizeof(ib_spec->gre.mask.key)); 2722 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_v, 2723 gre_key_h), 2724 &ib_spec->gre.val.key, 2725 sizeof(ib_spec->gre.val.key)); 2726 break; 2727 case IB_FLOW_SPEC_MPLS: 2728 switch (prev_type) { 2729 case IB_FLOW_SPEC_UDP: 2730 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2731 ft_field_support.outer_first_mpls_over_udp), 2732 &ib_spec->mpls.mask.tag)) 2733 return -EOPNOTSUPP; 2734 2735 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v, 2736 outer_first_mpls_over_udp), 2737 &ib_spec->mpls.val.tag, 2738 sizeof(ib_spec->mpls.val.tag)); 2739 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c, 2740 outer_first_mpls_over_udp), 2741 &ib_spec->mpls.mask.tag, 2742 sizeof(ib_spec->mpls.mask.tag)); 2743 break; 2744 case IB_FLOW_SPEC_GRE: 2745 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2746 ft_field_support.outer_first_mpls_over_gre), 2747 &ib_spec->mpls.mask.tag)) 2748 return -EOPNOTSUPP; 2749 2750 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v, 2751 outer_first_mpls_over_gre), 2752 &ib_spec->mpls.val.tag, 2753 sizeof(ib_spec->mpls.val.tag)); 2754 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c, 2755 outer_first_mpls_over_gre), 2756 &ib_spec->mpls.mask.tag, 2757 sizeof(ib_spec->mpls.mask.tag)); 2758 break; 2759 default: 2760 if (ib_spec->type & IB_FLOW_SPEC_INNER) { 2761 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2762 ft_field_support.inner_first_mpls), 2763 &ib_spec->mpls.mask.tag)) 2764 return -EOPNOTSUPP; 2765 2766 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v, 2767 inner_first_mpls), 2768 &ib_spec->mpls.val.tag, 2769 sizeof(ib_spec->mpls.val.tag)); 2770 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c, 2771 inner_first_mpls), 2772 &ib_spec->mpls.mask.tag, 2773 sizeof(ib_spec->mpls.mask.tag)); 2774 } else { 2775 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2776 ft_field_support.outer_first_mpls), 2777 &ib_spec->mpls.mask.tag)) 2778 return -EOPNOTSUPP; 2779 2780 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v, 2781 outer_first_mpls), 2782 &ib_spec->mpls.val.tag, 2783 sizeof(ib_spec->mpls.val.tag)); 2784 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c, 2785 outer_first_mpls), 2786 &ib_spec->mpls.mask.tag, 2787 sizeof(ib_spec->mpls.mask.tag)); 2788 } 2789 } 2790 break; 2791 case IB_FLOW_SPEC_VXLAN_TUNNEL: 2792 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask, 2793 LAST_TUNNEL_FIELD)) 2794 return -EOPNOTSUPP; 2795 2796 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni, 2797 ntohl(ib_spec->tunnel.mask.tunnel_id)); 2798 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni, 2799 ntohl(ib_spec->tunnel.val.tunnel_id)); 2800 break; 2801 case IB_FLOW_SPEC_ACTION_TAG: 2802 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag, 2803 LAST_FLOW_TAG_FIELD)) 2804 return -EOPNOTSUPP; 2805 if (ib_spec->flow_tag.tag_id >= BIT(24)) 2806 return -EINVAL; 2807 2808 action->flow_tag = ib_spec->flow_tag.tag_id; 2809 action->has_flow_tag = true; 2810 break; 2811 case IB_FLOW_SPEC_ACTION_DROP: 2812 if (FIELDS_NOT_SUPPORTED(ib_spec->drop, 2813 LAST_DROP_FIELD)) 2814 return -EOPNOTSUPP; 2815 action->action |= MLX5_FLOW_CONTEXT_ACTION_DROP; 2816 break; 2817 case IB_FLOW_SPEC_ACTION_HANDLE: 2818 ret = parse_flow_flow_action(ib_spec, flow_attr, action); 2819 if (ret) 2820 return ret; 2821 break; 2822 case IB_FLOW_SPEC_ACTION_COUNT: 2823 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_count, 2824 LAST_COUNTERS_FIELD)) 2825 return -EOPNOTSUPP; 2826 2827 /* for now support only one counters spec per flow */ 2828 if (action->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) 2829 return -EINVAL; 2830 2831 action->counters = ib_spec->flow_count.counters; 2832 action->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT; 2833 break; 2834 default: 2835 return -EINVAL; 2836 } 2837 2838 return 0; 2839 } 2840 2841 /* If a flow could catch both multicast and unicast packets, 2842 * it won't fall into the multicast flow steering table and this rule 2843 * could steal other multicast packets. 2844 */ 2845 static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr) 2846 { 2847 union ib_flow_spec *flow_spec; 2848 2849 if (ib_attr->type != IB_FLOW_ATTR_NORMAL || 2850 ib_attr->num_of_specs < 1) 2851 return false; 2852 2853 flow_spec = (union ib_flow_spec *)(ib_attr + 1); 2854 if (flow_spec->type == IB_FLOW_SPEC_IPV4) { 2855 struct ib_flow_spec_ipv4 *ipv4_spec; 2856 2857 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec; 2858 if (ipv4_is_multicast(ipv4_spec->val.dst_ip)) 2859 return true; 2860 2861 return false; 2862 } 2863 2864 if (flow_spec->type == IB_FLOW_SPEC_ETH) { 2865 struct ib_flow_spec_eth *eth_spec; 2866 2867 eth_spec = (struct ib_flow_spec_eth *)flow_spec; 2868 return is_multicast_ether_addr(eth_spec->mask.dst_mac) && 2869 is_multicast_ether_addr(eth_spec->val.dst_mac); 2870 } 2871 2872 return false; 2873 } 2874 2875 enum valid_spec { 2876 VALID_SPEC_INVALID, 2877 VALID_SPEC_VALID, 2878 VALID_SPEC_NA, 2879 }; 2880 2881 static enum valid_spec 2882 is_valid_esp_aes_gcm(struct mlx5_core_dev *mdev, 2883 const struct mlx5_flow_spec *spec, 2884 const struct mlx5_flow_act *flow_act, 2885 bool egress) 2886 { 2887 const u32 *match_c = spec->match_criteria; 2888 bool is_crypto = 2889 (flow_act->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT | 2890 MLX5_FLOW_CONTEXT_ACTION_DECRYPT)); 2891 bool is_ipsec = mlx5_fs_is_ipsec_flow(match_c); 2892 bool is_drop = flow_act->action & MLX5_FLOW_CONTEXT_ACTION_DROP; 2893 2894 /* 2895 * Currently only crypto is supported in egress, when regular egress 2896 * rules would be supported, always return VALID_SPEC_NA. 2897 */ 2898 if (!is_crypto) 2899 return egress ? VALID_SPEC_INVALID : VALID_SPEC_NA; 2900 2901 return is_crypto && is_ipsec && 2902 (!egress || (!is_drop && !flow_act->has_flow_tag)) ? 2903 VALID_SPEC_VALID : VALID_SPEC_INVALID; 2904 } 2905 2906 static bool is_valid_spec(struct mlx5_core_dev *mdev, 2907 const struct mlx5_flow_spec *spec, 2908 const struct mlx5_flow_act *flow_act, 2909 bool egress) 2910 { 2911 /* We curretly only support ipsec egress flow */ 2912 return is_valid_esp_aes_gcm(mdev, spec, flow_act, egress) != VALID_SPEC_INVALID; 2913 } 2914 2915 static bool is_valid_ethertype(struct mlx5_core_dev *mdev, 2916 const struct ib_flow_attr *flow_attr, 2917 bool check_inner) 2918 { 2919 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1); 2920 int match_ipv = check_inner ? 2921 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2922 ft_field_support.inner_ip_version) : 2923 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2924 ft_field_support.outer_ip_version); 2925 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0; 2926 bool ipv4_spec_valid, ipv6_spec_valid; 2927 unsigned int ip_spec_type = 0; 2928 bool has_ethertype = false; 2929 unsigned int spec_index; 2930 bool mask_valid = true; 2931 u16 eth_type = 0; 2932 bool type_valid; 2933 2934 /* Validate that ethertype is correct */ 2935 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 2936 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) && 2937 ib_spec->eth.mask.ether_type) { 2938 mask_valid = (ib_spec->eth.mask.ether_type == 2939 htons(0xffff)); 2940 has_ethertype = true; 2941 eth_type = ntohs(ib_spec->eth.val.ether_type); 2942 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) || 2943 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) { 2944 ip_spec_type = ib_spec->type; 2945 } 2946 ib_spec = (void *)ib_spec + ib_spec->size; 2947 } 2948 2949 type_valid = (!has_ethertype) || (!ip_spec_type); 2950 if (!type_valid && mask_valid) { 2951 ipv4_spec_valid = (eth_type == ETH_P_IP) && 2952 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit)); 2953 ipv6_spec_valid = (eth_type == ETH_P_IPV6) && 2954 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit)); 2955 2956 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) || 2957 (((eth_type == ETH_P_MPLS_UC) || 2958 (eth_type == ETH_P_MPLS_MC)) && match_ipv); 2959 } 2960 2961 return type_valid; 2962 } 2963 2964 static bool is_valid_attr(struct mlx5_core_dev *mdev, 2965 const struct ib_flow_attr *flow_attr) 2966 { 2967 return is_valid_ethertype(mdev, flow_attr, false) && 2968 is_valid_ethertype(mdev, flow_attr, true); 2969 } 2970 2971 static void put_flow_table(struct mlx5_ib_dev *dev, 2972 struct mlx5_ib_flow_prio *prio, bool ft_added) 2973 { 2974 prio->refcount -= !!ft_added; 2975 if (!prio->refcount) { 2976 mlx5_destroy_flow_table(prio->flow_table); 2977 prio->flow_table = NULL; 2978 } 2979 } 2980 2981 static void counters_clear_description(struct ib_counters *counters) 2982 { 2983 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters); 2984 2985 mutex_lock(&mcounters->mcntrs_mutex); 2986 kfree(mcounters->counters_data); 2987 mcounters->counters_data = NULL; 2988 mcounters->cntrs_max_index = 0; 2989 mutex_unlock(&mcounters->mcntrs_mutex); 2990 } 2991 2992 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id) 2993 { 2994 struct mlx5_ib_flow_handler *handler = container_of(flow_id, 2995 struct mlx5_ib_flow_handler, 2996 ibflow); 2997 struct mlx5_ib_flow_handler *iter, *tmp; 2998 struct mlx5_ib_dev *dev = handler->dev; 2999 3000 mutex_lock(&dev->flow_db->lock); 3001 3002 list_for_each_entry_safe(iter, tmp, &handler->list, list) { 3003 mlx5_del_flow_rules(iter->rule); 3004 put_flow_table(dev, iter->prio, true); 3005 list_del(&iter->list); 3006 kfree(iter); 3007 } 3008 3009 mlx5_del_flow_rules(handler->rule); 3010 put_flow_table(dev, handler->prio, true); 3011 if (handler->ibcounters && 3012 atomic_read(&handler->ibcounters->usecnt) == 1) 3013 counters_clear_description(handler->ibcounters); 3014 3015 mutex_unlock(&dev->flow_db->lock); 3016 if (handler->flow_matcher) 3017 atomic_dec(&handler->flow_matcher->usecnt); 3018 kfree(handler); 3019 3020 return 0; 3021 } 3022 3023 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap) 3024 { 3025 priority *= 2; 3026 if (!dont_trap) 3027 priority++; 3028 return priority; 3029 } 3030 3031 enum flow_table_type { 3032 MLX5_IB_FT_RX, 3033 MLX5_IB_FT_TX 3034 }; 3035 3036 #define MLX5_FS_MAX_TYPES 6 3037 #define MLX5_FS_MAX_ENTRIES BIT(16) 3038 3039 static struct mlx5_ib_flow_prio *_get_prio(struct mlx5_flow_namespace *ns, 3040 struct mlx5_ib_flow_prio *prio, 3041 int priority, 3042 int num_entries, int num_groups) 3043 { 3044 struct mlx5_flow_table *ft; 3045 3046 ft = mlx5_create_auto_grouped_flow_table(ns, priority, 3047 num_entries, 3048 num_groups, 3049 0, 0); 3050 if (IS_ERR(ft)) 3051 return ERR_CAST(ft); 3052 3053 prio->flow_table = ft; 3054 prio->refcount = 0; 3055 return prio; 3056 } 3057 3058 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev, 3059 struct ib_flow_attr *flow_attr, 3060 enum flow_table_type ft_type) 3061 { 3062 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP; 3063 struct mlx5_flow_namespace *ns = NULL; 3064 struct mlx5_ib_flow_prio *prio; 3065 struct mlx5_flow_table *ft; 3066 int max_table_size; 3067 int num_entries; 3068 int num_groups; 3069 int priority; 3070 3071 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 3072 log_max_ft_size)); 3073 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 3074 if (ft_type == MLX5_IB_FT_TX) 3075 priority = 0; 3076 else if (flow_is_multicast_only(flow_attr) && 3077 !dont_trap) 3078 priority = MLX5_IB_FLOW_MCAST_PRIO; 3079 else 3080 priority = ib_prio_to_core_prio(flow_attr->priority, 3081 dont_trap); 3082 ns = mlx5_get_flow_namespace(dev->mdev, 3083 ft_type == MLX5_IB_FT_TX ? 3084 MLX5_FLOW_NAMESPACE_EGRESS : 3085 MLX5_FLOW_NAMESPACE_BYPASS); 3086 num_entries = MLX5_FS_MAX_ENTRIES; 3087 num_groups = MLX5_FS_MAX_TYPES; 3088 prio = &dev->flow_db->prios[priority]; 3089 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 3090 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 3091 ns = mlx5_get_flow_namespace(dev->mdev, 3092 MLX5_FLOW_NAMESPACE_LEFTOVERS); 3093 build_leftovers_ft_param(&priority, 3094 &num_entries, 3095 &num_groups); 3096 prio = &dev->flow_db->prios[MLX5_IB_FLOW_LEFTOVERS_PRIO]; 3097 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 3098 if (!MLX5_CAP_FLOWTABLE(dev->mdev, 3099 allow_sniffer_and_nic_rx_shared_tir)) 3100 return ERR_PTR(-ENOTSUPP); 3101 3102 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ? 3103 MLX5_FLOW_NAMESPACE_SNIFFER_RX : 3104 MLX5_FLOW_NAMESPACE_SNIFFER_TX); 3105 3106 prio = &dev->flow_db->sniffer[ft_type]; 3107 priority = 0; 3108 num_entries = 1; 3109 num_groups = 1; 3110 } 3111 3112 if (!ns) 3113 return ERR_PTR(-ENOTSUPP); 3114 3115 if (num_entries > max_table_size) 3116 return ERR_PTR(-ENOMEM); 3117 3118 ft = prio->flow_table; 3119 if (!ft) 3120 return _get_prio(ns, prio, priority, num_entries, num_groups); 3121 3122 return prio; 3123 } 3124 3125 static void set_underlay_qp(struct mlx5_ib_dev *dev, 3126 struct mlx5_flow_spec *spec, 3127 u32 underlay_qpn) 3128 { 3129 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, 3130 spec->match_criteria, 3131 misc_parameters); 3132 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, 3133 misc_parameters); 3134 3135 if (underlay_qpn && 3136 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 3137 ft_field_support.bth_dst_qp)) { 3138 MLX5_SET(fte_match_set_misc, 3139 misc_params_v, bth_dst_qp, underlay_qpn); 3140 MLX5_SET(fte_match_set_misc, 3141 misc_params_c, bth_dst_qp, 0xffffff); 3142 } 3143 } 3144 3145 static int read_flow_counters(struct ib_device *ibdev, 3146 struct mlx5_read_counters_attr *read_attr) 3147 { 3148 struct mlx5_fc *fc = read_attr->hw_cntrs_hndl; 3149 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3150 3151 return mlx5_fc_query(dev->mdev, fc, 3152 &read_attr->out[IB_COUNTER_PACKETS], 3153 &read_attr->out[IB_COUNTER_BYTES]); 3154 } 3155 3156 /* flow counters currently expose two counters packets and bytes */ 3157 #define FLOW_COUNTERS_NUM 2 3158 static int counters_set_description(struct ib_counters *counters, 3159 enum mlx5_ib_counters_type counters_type, 3160 struct mlx5_ib_flow_counters_desc *desc_data, 3161 u32 ncounters) 3162 { 3163 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters); 3164 u32 cntrs_max_index = 0; 3165 int i; 3166 3167 if (counters_type != MLX5_IB_COUNTERS_FLOW) 3168 return -EINVAL; 3169 3170 /* init the fields for the object */ 3171 mcounters->type = counters_type; 3172 mcounters->read_counters = read_flow_counters; 3173 mcounters->counters_num = FLOW_COUNTERS_NUM; 3174 mcounters->ncounters = ncounters; 3175 /* each counter entry have both description and index pair */ 3176 for (i = 0; i < ncounters; i++) { 3177 if (desc_data[i].description > IB_COUNTER_BYTES) 3178 return -EINVAL; 3179 3180 if (cntrs_max_index <= desc_data[i].index) 3181 cntrs_max_index = desc_data[i].index + 1; 3182 } 3183 3184 mutex_lock(&mcounters->mcntrs_mutex); 3185 mcounters->counters_data = desc_data; 3186 mcounters->cntrs_max_index = cntrs_max_index; 3187 mutex_unlock(&mcounters->mcntrs_mutex); 3188 3189 return 0; 3190 } 3191 3192 #define MAX_COUNTERS_NUM (USHRT_MAX / (sizeof(u32) * 2)) 3193 static int flow_counters_set_data(struct ib_counters *ibcounters, 3194 struct mlx5_ib_create_flow *ucmd) 3195 { 3196 struct mlx5_ib_mcounters *mcounters = to_mcounters(ibcounters); 3197 struct mlx5_ib_flow_counters_data *cntrs_data = NULL; 3198 struct mlx5_ib_flow_counters_desc *desc_data = NULL; 3199 bool hw_hndl = false; 3200 int ret = 0; 3201 3202 if (ucmd && ucmd->ncounters_data != 0) { 3203 cntrs_data = ucmd->data; 3204 if (cntrs_data->ncounters > MAX_COUNTERS_NUM) 3205 return -EINVAL; 3206 3207 desc_data = kcalloc(cntrs_data->ncounters, 3208 sizeof(*desc_data), 3209 GFP_KERNEL); 3210 if (!desc_data) 3211 return -ENOMEM; 3212 3213 if (copy_from_user(desc_data, 3214 u64_to_user_ptr(cntrs_data->counters_data), 3215 sizeof(*desc_data) * cntrs_data->ncounters)) { 3216 ret = -EFAULT; 3217 goto free; 3218 } 3219 } 3220 3221 if (!mcounters->hw_cntrs_hndl) { 3222 mcounters->hw_cntrs_hndl = mlx5_fc_create( 3223 to_mdev(ibcounters->device)->mdev, false); 3224 if (IS_ERR(mcounters->hw_cntrs_hndl)) { 3225 ret = PTR_ERR(mcounters->hw_cntrs_hndl); 3226 goto free; 3227 } 3228 hw_hndl = true; 3229 } 3230 3231 if (desc_data) { 3232 /* counters already bound to at least one flow */ 3233 if (mcounters->cntrs_max_index) { 3234 ret = -EINVAL; 3235 goto free_hndl; 3236 } 3237 3238 ret = counters_set_description(ibcounters, 3239 MLX5_IB_COUNTERS_FLOW, 3240 desc_data, 3241 cntrs_data->ncounters); 3242 if (ret) 3243 goto free_hndl; 3244 3245 } else if (!mcounters->cntrs_max_index) { 3246 /* counters not bound yet, must have udata passed */ 3247 ret = -EINVAL; 3248 goto free_hndl; 3249 } 3250 3251 return 0; 3252 3253 free_hndl: 3254 if (hw_hndl) { 3255 mlx5_fc_destroy(to_mdev(ibcounters->device)->mdev, 3256 mcounters->hw_cntrs_hndl); 3257 mcounters->hw_cntrs_hndl = NULL; 3258 } 3259 free: 3260 kfree(desc_data); 3261 return ret; 3262 } 3263 3264 static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev, 3265 struct mlx5_ib_flow_prio *ft_prio, 3266 const struct ib_flow_attr *flow_attr, 3267 struct mlx5_flow_destination *dst, 3268 u32 underlay_qpn, 3269 struct mlx5_ib_create_flow *ucmd) 3270 { 3271 struct mlx5_flow_table *ft = ft_prio->flow_table; 3272 struct mlx5_ib_flow_handler *handler; 3273 struct mlx5_flow_act flow_act = {.flow_tag = MLX5_FS_DEFAULT_FLOW_TAG}; 3274 struct mlx5_flow_spec *spec; 3275 struct mlx5_flow_destination dest_arr[2] = {}; 3276 struct mlx5_flow_destination *rule_dst = dest_arr; 3277 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr); 3278 unsigned int spec_index; 3279 u32 prev_type = 0; 3280 int err = 0; 3281 int dest_num = 0; 3282 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS; 3283 3284 if (!is_valid_attr(dev->mdev, flow_attr)) 3285 return ERR_PTR(-EINVAL); 3286 3287 spec = kvzalloc(sizeof(*spec), GFP_KERNEL); 3288 handler = kzalloc(sizeof(*handler), GFP_KERNEL); 3289 if (!handler || !spec) { 3290 err = -ENOMEM; 3291 goto free; 3292 } 3293 3294 INIT_LIST_HEAD(&handler->list); 3295 if (dst) { 3296 memcpy(&dest_arr[0], dst, sizeof(*dst)); 3297 dest_num++; 3298 } 3299 3300 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 3301 err = parse_flow_attr(dev->mdev, spec->match_criteria, 3302 spec->match_value, 3303 ib_flow, flow_attr, &flow_act, 3304 prev_type); 3305 if (err < 0) 3306 goto free; 3307 3308 prev_type = ((union ib_flow_spec *)ib_flow)->type; 3309 ib_flow += ((union ib_flow_spec *)ib_flow)->size; 3310 } 3311 3312 if (!flow_is_multicast_only(flow_attr)) 3313 set_underlay_qp(dev, spec, underlay_qpn); 3314 3315 if (dev->rep) { 3316 void *misc; 3317 3318 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, 3319 misc_parameters); 3320 MLX5_SET(fte_match_set_misc, misc, source_port, 3321 dev->rep->vport); 3322 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, 3323 misc_parameters); 3324 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port); 3325 } 3326 3327 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria); 3328 3329 if (is_egress && 3330 !is_valid_spec(dev->mdev, spec, &flow_act, is_egress)) { 3331 err = -EINVAL; 3332 goto free; 3333 } 3334 3335 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) { 3336 err = flow_counters_set_data(flow_act.counters, ucmd); 3337 if (err) 3338 goto free; 3339 3340 handler->ibcounters = flow_act.counters; 3341 dest_arr[dest_num].type = 3342 MLX5_FLOW_DESTINATION_TYPE_COUNTER; 3343 dest_arr[dest_num].counter = 3344 to_mcounters(flow_act.counters)->hw_cntrs_hndl; 3345 dest_num++; 3346 } 3347 3348 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP) { 3349 if (!(flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT)) { 3350 rule_dst = NULL; 3351 dest_num = 0; 3352 } 3353 } else { 3354 if (is_egress) 3355 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW; 3356 else 3357 flow_act.action |= 3358 dest_num ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST : 3359 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO; 3360 } 3361 3362 if (flow_act.has_flow_tag && 3363 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 3364 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) { 3365 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n", 3366 flow_act.flow_tag, flow_attr->type); 3367 err = -EINVAL; 3368 goto free; 3369 } 3370 handler->rule = mlx5_add_flow_rules(ft, spec, 3371 &flow_act, 3372 rule_dst, dest_num); 3373 3374 if (IS_ERR(handler->rule)) { 3375 err = PTR_ERR(handler->rule); 3376 goto free; 3377 } 3378 3379 ft_prio->refcount++; 3380 handler->prio = ft_prio; 3381 handler->dev = dev; 3382 3383 ft_prio->flow_table = ft; 3384 free: 3385 if (err && handler) { 3386 if (handler->ibcounters && 3387 atomic_read(&handler->ibcounters->usecnt) == 1) 3388 counters_clear_description(handler->ibcounters); 3389 kfree(handler); 3390 } 3391 kvfree(spec); 3392 return err ? ERR_PTR(err) : handler; 3393 } 3394 3395 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev, 3396 struct mlx5_ib_flow_prio *ft_prio, 3397 const struct ib_flow_attr *flow_attr, 3398 struct mlx5_flow_destination *dst) 3399 { 3400 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0, NULL); 3401 } 3402 3403 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev, 3404 struct mlx5_ib_flow_prio *ft_prio, 3405 struct ib_flow_attr *flow_attr, 3406 struct mlx5_flow_destination *dst) 3407 { 3408 struct mlx5_ib_flow_handler *handler_dst = NULL; 3409 struct mlx5_ib_flow_handler *handler = NULL; 3410 3411 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL); 3412 if (!IS_ERR(handler)) { 3413 handler_dst = create_flow_rule(dev, ft_prio, 3414 flow_attr, dst); 3415 if (IS_ERR(handler_dst)) { 3416 mlx5_del_flow_rules(handler->rule); 3417 ft_prio->refcount--; 3418 kfree(handler); 3419 handler = handler_dst; 3420 } else { 3421 list_add(&handler_dst->list, &handler->list); 3422 } 3423 } 3424 3425 return handler; 3426 } 3427 enum { 3428 LEFTOVERS_MC, 3429 LEFTOVERS_UC, 3430 }; 3431 3432 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev, 3433 struct mlx5_ib_flow_prio *ft_prio, 3434 struct ib_flow_attr *flow_attr, 3435 struct mlx5_flow_destination *dst) 3436 { 3437 struct mlx5_ib_flow_handler *handler_ucast = NULL; 3438 struct mlx5_ib_flow_handler *handler = NULL; 3439 3440 static struct { 3441 struct ib_flow_attr flow_attr; 3442 struct ib_flow_spec_eth eth_flow; 3443 } leftovers_specs[] = { 3444 [LEFTOVERS_MC] = { 3445 .flow_attr = { 3446 .num_of_specs = 1, 3447 .size = sizeof(leftovers_specs[0]) 3448 }, 3449 .eth_flow = { 3450 .type = IB_FLOW_SPEC_ETH, 3451 .size = sizeof(struct ib_flow_spec_eth), 3452 .mask = {.dst_mac = {0x1} }, 3453 .val = {.dst_mac = {0x1} } 3454 } 3455 }, 3456 [LEFTOVERS_UC] = { 3457 .flow_attr = { 3458 .num_of_specs = 1, 3459 .size = sizeof(leftovers_specs[0]) 3460 }, 3461 .eth_flow = { 3462 .type = IB_FLOW_SPEC_ETH, 3463 .size = sizeof(struct ib_flow_spec_eth), 3464 .mask = {.dst_mac = {0x1} }, 3465 .val = {.dst_mac = {} } 3466 } 3467 } 3468 }; 3469 3470 handler = create_flow_rule(dev, ft_prio, 3471 &leftovers_specs[LEFTOVERS_MC].flow_attr, 3472 dst); 3473 if (!IS_ERR(handler) && 3474 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) { 3475 handler_ucast = create_flow_rule(dev, ft_prio, 3476 &leftovers_specs[LEFTOVERS_UC].flow_attr, 3477 dst); 3478 if (IS_ERR(handler_ucast)) { 3479 mlx5_del_flow_rules(handler->rule); 3480 ft_prio->refcount--; 3481 kfree(handler); 3482 handler = handler_ucast; 3483 } else { 3484 list_add(&handler_ucast->list, &handler->list); 3485 } 3486 } 3487 3488 return handler; 3489 } 3490 3491 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev, 3492 struct mlx5_ib_flow_prio *ft_rx, 3493 struct mlx5_ib_flow_prio *ft_tx, 3494 struct mlx5_flow_destination *dst) 3495 { 3496 struct mlx5_ib_flow_handler *handler_rx; 3497 struct mlx5_ib_flow_handler *handler_tx; 3498 int err; 3499 static const struct ib_flow_attr flow_attr = { 3500 .num_of_specs = 0, 3501 .size = sizeof(flow_attr) 3502 }; 3503 3504 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst); 3505 if (IS_ERR(handler_rx)) { 3506 err = PTR_ERR(handler_rx); 3507 goto err; 3508 } 3509 3510 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst); 3511 if (IS_ERR(handler_tx)) { 3512 err = PTR_ERR(handler_tx); 3513 goto err_tx; 3514 } 3515 3516 list_add(&handler_tx->list, &handler_rx->list); 3517 3518 return handler_rx; 3519 3520 err_tx: 3521 mlx5_del_flow_rules(handler_rx->rule); 3522 ft_rx->refcount--; 3523 kfree(handler_rx); 3524 err: 3525 return ERR_PTR(err); 3526 } 3527 3528 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp, 3529 struct ib_flow_attr *flow_attr, 3530 int domain, 3531 struct ib_udata *udata) 3532 { 3533 struct mlx5_ib_dev *dev = to_mdev(qp->device); 3534 struct mlx5_ib_qp *mqp = to_mqp(qp); 3535 struct mlx5_ib_flow_handler *handler = NULL; 3536 struct mlx5_flow_destination *dst = NULL; 3537 struct mlx5_ib_flow_prio *ft_prio_tx = NULL; 3538 struct mlx5_ib_flow_prio *ft_prio; 3539 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS; 3540 struct mlx5_ib_create_flow *ucmd = NULL, ucmd_hdr; 3541 size_t min_ucmd_sz, required_ucmd_sz; 3542 int err; 3543 int underlay_qpn; 3544 3545 if (udata && udata->inlen) { 3546 min_ucmd_sz = offsetof(typeof(ucmd_hdr), reserved) + 3547 sizeof(ucmd_hdr.reserved); 3548 if (udata->inlen < min_ucmd_sz) 3549 return ERR_PTR(-EOPNOTSUPP); 3550 3551 err = ib_copy_from_udata(&ucmd_hdr, udata, min_ucmd_sz); 3552 if (err) 3553 return ERR_PTR(err); 3554 3555 /* currently supports only one counters data */ 3556 if (ucmd_hdr.ncounters_data > 1) 3557 return ERR_PTR(-EINVAL); 3558 3559 required_ucmd_sz = min_ucmd_sz + 3560 sizeof(struct mlx5_ib_flow_counters_data) * 3561 ucmd_hdr.ncounters_data; 3562 if (udata->inlen > required_ucmd_sz && 3563 !ib_is_udata_cleared(udata, required_ucmd_sz, 3564 udata->inlen - required_ucmd_sz)) 3565 return ERR_PTR(-EOPNOTSUPP); 3566 3567 ucmd = kzalloc(required_ucmd_sz, GFP_KERNEL); 3568 if (!ucmd) 3569 return ERR_PTR(-ENOMEM); 3570 3571 err = ib_copy_from_udata(ucmd, udata, required_ucmd_sz); 3572 if (err) 3573 goto free_ucmd; 3574 } 3575 3576 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) { 3577 err = -ENOMEM; 3578 goto free_ucmd; 3579 } 3580 3581 if (domain != IB_FLOW_DOMAIN_USER || 3582 flow_attr->port > dev->num_ports || 3583 (flow_attr->flags & ~(IB_FLOW_ATTR_FLAGS_DONT_TRAP | 3584 IB_FLOW_ATTR_FLAGS_EGRESS))) { 3585 err = -EINVAL; 3586 goto free_ucmd; 3587 } 3588 3589 if (is_egress && 3590 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 3591 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) { 3592 err = -EINVAL; 3593 goto free_ucmd; 3594 } 3595 3596 dst = kzalloc(sizeof(*dst), GFP_KERNEL); 3597 if (!dst) { 3598 err = -ENOMEM; 3599 goto free_ucmd; 3600 } 3601 3602 mutex_lock(&dev->flow_db->lock); 3603 3604 ft_prio = get_flow_table(dev, flow_attr, 3605 is_egress ? MLX5_IB_FT_TX : MLX5_IB_FT_RX); 3606 if (IS_ERR(ft_prio)) { 3607 err = PTR_ERR(ft_prio); 3608 goto unlock; 3609 } 3610 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 3611 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX); 3612 if (IS_ERR(ft_prio_tx)) { 3613 err = PTR_ERR(ft_prio_tx); 3614 ft_prio_tx = NULL; 3615 goto destroy_ft; 3616 } 3617 } 3618 3619 if (is_egress) { 3620 dst->type = MLX5_FLOW_DESTINATION_TYPE_PORT; 3621 } else { 3622 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR; 3623 if (mqp->flags & MLX5_IB_QP_RSS) 3624 dst->tir_num = mqp->rss_qp.tirn; 3625 else 3626 dst->tir_num = mqp->raw_packet_qp.rq.tirn; 3627 } 3628 3629 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 3630 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) { 3631 handler = create_dont_trap_rule(dev, ft_prio, 3632 flow_attr, dst); 3633 } else { 3634 underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ? 3635 mqp->underlay_qpn : 0; 3636 handler = _create_flow_rule(dev, ft_prio, flow_attr, 3637 dst, underlay_qpn, ucmd); 3638 } 3639 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 3640 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 3641 handler = create_leftovers_rule(dev, ft_prio, flow_attr, 3642 dst); 3643 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 3644 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst); 3645 } else { 3646 err = -EINVAL; 3647 goto destroy_ft; 3648 } 3649 3650 if (IS_ERR(handler)) { 3651 err = PTR_ERR(handler); 3652 handler = NULL; 3653 goto destroy_ft; 3654 } 3655 3656 mutex_unlock(&dev->flow_db->lock); 3657 kfree(dst); 3658 kfree(ucmd); 3659 3660 return &handler->ibflow; 3661 3662 destroy_ft: 3663 put_flow_table(dev, ft_prio, false); 3664 if (ft_prio_tx) 3665 put_flow_table(dev, ft_prio_tx, false); 3666 unlock: 3667 mutex_unlock(&dev->flow_db->lock); 3668 kfree(dst); 3669 free_ucmd: 3670 kfree(ucmd); 3671 return ERR_PTR(err); 3672 } 3673 3674 static struct mlx5_ib_flow_prio *_get_flow_table(struct mlx5_ib_dev *dev, 3675 int priority, bool mcast) 3676 { 3677 int max_table_size; 3678 struct mlx5_flow_namespace *ns = NULL; 3679 struct mlx5_ib_flow_prio *prio; 3680 3681 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 3682 log_max_ft_size)); 3683 if (max_table_size < MLX5_FS_MAX_ENTRIES) 3684 return ERR_PTR(-ENOMEM); 3685 3686 if (mcast) 3687 priority = MLX5_IB_FLOW_MCAST_PRIO; 3688 else 3689 priority = ib_prio_to_core_prio(priority, false); 3690 3691 ns = mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS); 3692 if (!ns) 3693 return ERR_PTR(-ENOTSUPP); 3694 3695 prio = &dev->flow_db->prios[priority]; 3696 3697 if (prio->flow_table) 3698 return prio; 3699 3700 return _get_prio(ns, prio, priority, MLX5_FS_MAX_ENTRIES, 3701 MLX5_FS_MAX_TYPES); 3702 } 3703 3704 static struct mlx5_ib_flow_handler * 3705 _create_raw_flow_rule(struct mlx5_ib_dev *dev, 3706 struct mlx5_ib_flow_prio *ft_prio, 3707 struct mlx5_flow_destination *dst, 3708 struct mlx5_ib_flow_matcher *fs_matcher, 3709 void *cmd_in, int inlen) 3710 { 3711 struct mlx5_ib_flow_handler *handler; 3712 struct mlx5_flow_act flow_act = {.flow_tag = MLX5_FS_DEFAULT_FLOW_TAG}; 3713 struct mlx5_flow_spec *spec; 3714 struct mlx5_flow_table *ft = ft_prio->flow_table; 3715 int err = 0; 3716 3717 spec = kvzalloc(sizeof(*spec), GFP_KERNEL); 3718 handler = kzalloc(sizeof(*handler), GFP_KERNEL); 3719 if (!handler || !spec) { 3720 err = -ENOMEM; 3721 goto free; 3722 } 3723 3724 INIT_LIST_HEAD(&handler->list); 3725 3726 memcpy(spec->match_value, cmd_in, inlen); 3727 memcpy(spec->match_criteria, fs_matcher->matcher_mask.match_params, 3728 fs_matcher->mask_len); 3729 spec->match_criteria_enable = fs_matcher->match_criteria_enable; 3730 3731 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; 3732 handler->rule = mlx5_add_flow_rules(ft, spec, 3733 &flow_act, dst, 1); 3734 3735 if (IS_ERR(handler->rule)) { 3736 err = PTR_ERR(handler->rule); 3737 goto free; 3738 } 3739 3740 ft_prio->refcount++; 3741 handler->prio = ft_prio; 3742 handler->dev = dev; 3743 ft_prio->flow_table = ft; 3744 3745 free: 3746 if (err) 3747 kfree(handler); 3748 kvfree(spec); 3749 return err ? ERR_PTR(err) : handler; 3750 } 3751 3752 static bool raw_fs_is_multicast(struct mlx5_ib_flow_matcher *fs_matcher, 3753 void *match_v) 3754 { 3755 void *match_c; 3756 void *match_v_set_lyr_2_4, *match_c_set_lyr_2_4; 3757 void *dmac, *dmac_mask; 3758 void *ipv4, *ipv4_mask; 3759 3760 if (!(fs_matcher->match_criteria_enable & 3761 (1 << MATCH_CRITERIA_ENABLE_OUTER_BIT))) 3762 return false; 3763 3764 match_c = fs_matcher->matcher_mask.match_params; 3765 match_v_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_v, 3766 outer_headers); 3767 match_c_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_c, 3768 outer_headers); 3769 3770 dmac = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4, 3771 dmac_47_16); 3772 dmac_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4, 3773 dmac_47_16); 3774 3775 if (is_multicast_ether_addr(dmac) && 3776 is_multicast_ether_addr(dmac_mask)) 3777 return true; 3778 3779 ipv4 = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4, 3780 dst_ipv4_dst_ipv6.ipv4_layout.ipv4); 3781 3782 ipv4_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4, 3783 dst_ipv4_dst_ipv6.ipv4_layout.ipv4); 3784 3785 if (ipv4_is_multicast(*(__be32 *)(ipv4)) && 3786 ipv4_is_multicast(*(__be32 *)(ipv4_mask))) 3787 return true; 3788 3789 return false; 3790 } 3791 3792 struct mlx5_ib_flow_handler * 3793 mlx5_ib_raw_fs_rule_add(struct mlx5_ib_dev *dev, 3794 struct mlx5_ib_flow_matcher *fs_matcher, 3795 void *cmd_in, int inlen, int dest_id, 3796 int dest_type) 3797 { 3798 struct mlx5_flow_destination *dst; 3799 struct mlx5_ib_flow_prio *ft_prio; 3800 int priority = fs_matcher->priority; 3801 struct mlx5_ib_flow_handler *handler; 3802 bool mcast; 3803 int err; 3804 3805 if (fs_matcher->flow_type != MLX5_IB_FLOW_TYPE_NORMAL) 3806 return ERR_PTR(-EOPNOTSUPP); 3807 3808 if (fs_matcher->priority > MLX5_IB_FLOW_LAST_PRIO) 3809 return ERR_PTR(-ENOMEM); 3810 3811 dst = kzalloc(sizeof(*dst), GFP_KERNEL); 3812 if (!dst) 3813 return ERR_PTR(-ENOMEM); 3814 3815 mcast = raw_fs_is_multicast(fs_matcher, cmd_in); 3816 mutex_lock(&dev->flow_db->lock); 3817 3818 ft_prio = _get_flow_table(dev, priority, mcast); 3819 if (IS_ERR(ft_prio)) { 3820 err = PTR_ERR(ft_prio); 3821 goto unlock; 3822 } 3823 3824 if (dest_type == MLX5_FLOW_DESTINATION_TYPE_TIR) { 3825 dst->type = dest_type; 3826 dst->tir_num = dest_id; 3827 } else { 3828 dst->type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM; 3829 dst->ft_num = dest_id; 3830 } 3831 3832 handler = _create_raw_flow_rule(dev, ft_prio, dst, fs_matcher, cmd_in, 3833 inlen); 3834 3835 if (IS_ERR(handler)) { 3836 err = PTR_ERR(handler); 3837 goto destroy_ft; 3838 } 3839 3840 mutex_unlock(&dev->flow_db->lock); 3841 atomic_inc(&fs_matcher->usecnt); 3842 handler->flow_matcher = fs_matcher; 3843 3844 kfree(dst); 3845 3846 return handler; 3847 3848 destroy_ft: 3849 put_flow_table(dev, ft_prio, false); 3850 unlock: 3851 mutex_unlock(&dev->flow_db->lock); 3852 kfree(dst); 3853 3854 return ERR_PTR(err); 3855 } 3856 3857 static u32 mlx5_ib_flow_action_flags_to_accel_xfrm_flags(u32 mlx5_flags) 3858 { 3859 u32 flags = 0; 3860 3861 if (mlx5_flags & MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA) 3862 flags |= MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA; 3863 3864 return flags; 3865 } 3866 3867 #define MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA 3868 static struct ib_flow_action * 3869 mlx5_ib_create_flow_action_esp(struct ib_device *device, 3870 const struct ib_flow_action_attrs_esp *attr, 3871 struct uverbs_attr_bundle *attrs) 3872 { 3873 struct mlx5_ib_dev *mdev = to_mdev(device); 3874 struct ib_uverbs_flow_action_esp_keymat_aes_gcm *aes_gcm; 3875 struct mlx5_accel_esp_xfrm_attrs accel_attrs = {}; 3876 struct mlx5_ib_flow_action *action; 3877 u64 action_flags; 3878 u64 flags; 3879 int err = 0; 3880 3881 err = uverbs_get_flags64( 3882 &action_flags, attrs, MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS, 3883 ((MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED << 1) - 1)); 3884 if (err) 3885 return ERR_PTR(err); 3886 3887 flags = mlx5_ib_flow_action_flags_to_accel_xfrm_flags(action_flags); 3888 3889 /* We current only support a subset of the standard features. Only a 3890 * keymat of type AES_GCM, with icv_len == 16, iv_algo == SEQ and esn 3891 * (with overlap). Full offload mode isn't supported. 3892 */ 3893 if (!attr->keymat || attr->replay || attr->encap || 3894 attr->spi || attr->seq || attr->tfc_pad || 3895 attr->hard_limit_pkts || 3896 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED | 3897 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT))) 3898 return ERR_PTR(-EOPNOTSUPP); 3899 3900 if (attr->keymat->protocol != 3901 IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM) 3902 return ERR_PTR(-EOPNOTSUPP); 3903 3904 aes_gcm = &attr->keymat->keymat.aes_gcm; 3905 3906 if (aes_gcm->icv_len != 16 || 3907 aes_gcm->iv_algo != IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ) 3908 return ERR_PTR(-EOPNOTSUPP); 3909 3910 action = kmalloc(sizeof(*action), GFP_KERNEL); 3911 if (!action) 3912 return ERR_PTR(-ENOMEM); 3913 3914 action->esp_aes_gcm.ib_flags = attr->flags; 3915 memcpy(&accel_attrs.keymat.aes_gcm.aes_key, &aes_gcm->aes_key, 3916 sizeof(accel_attrs.keymat.aes_gcm.aes_key)); 3917 accel_attrs.keymat.aes_gcm.key_len = aes_gcm->key_len * 8; 3918 memcpy(&accel_attrs.keymat.aes_gcm.salt, &aes_gcm->salt, 3919 sizeof(accel_attrs.keymat.aes_gcm.salt)); 3920 memcpy(&accel_attrs.keymat.aes_gcm.seq_iv, &aes_gcm->iv, 3921 sizeof(accel_attrs.keymat.aes_gcm.seq_iv)); 3922 accel_attrs.keymat.aes_gcm.icv_len = aes_gcm->icv_len * 8; 3923 accel_attrs.keymat.aes_gcm.iv_algo = MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ; 3924 accel_attrs.keymat_type = MLX5_ACCEL_ESP_KEYMAT_AES_GCM; 3925 3926 accel_attrs.esn = attr->esn; 3927 if (attr->flags & IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) 3928 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED; 3929 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW) 3930 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP; 3931 3932 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT) 3933 accel_attrs.action |= MLX5_ACCEL_ESP_ACTION_ENCRYPT; 3934 3935 action->esp_aes_gcm.ctx = 3936 mlx5_accel_esp_create_xfrm(mdev->mdev, &accel_attrs, flags); 3937 if (IS_ERR(action->esp_aes_gcm.ctx)) { 3938 err = PTR_ERR(action->esp_aes_gcm.ctx); 3939 goto err_parse; 3940 } 3941 3942 action->esp_aes_gcm.ib_flags = attr->flags; 3943 3944 return &action->ib_action; 3945 3946 err_parse: 3947 kfree(action); 3948 return ERR_PTR(err); 3949 } 3950 3951 static int 3952 mlx5_ib_modify_flow_action_esp(struct ib_flow_action *action, 3953 const struct ib_flow_action_attrs_esp *attr, 3954 struct uverbs_attr_bundle *attrs) 3955 { 3956 struct mlx5_ib_flow_action *maction = to_mflow_act(action); 3957 struct mlx5_accel_esp_xfrm_attrs accel_attrs; 3958 int err = 0; 3959 3960 if (attr->keymat || attr->replay || attr->encap || 3961 attr->spi || attr->seq || attr->tfc_pad || 3962 attr->hard_limit_pkts || 3963 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED | 3964 IB_FLOW_ACTION_ESP_FLAGS_MOD_ESP_ATTRS | 3965 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW))) 3966 return -EOPNOTSUPP; 3967 3968 /* Only the ESN value or the MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP can 3969 * be modified. 3970 */ 3971 if (!(maction->esp_aes_gcm.ib_flags & 3972 IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) && 3973 attr->flags & (IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED | 3974 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)) 3975 return -EINVAL; 3976 3977 memcpy(&accel_attrs, &maction->esp_aes_gcm.ctx->attrs, 3978 sizeof(accel_attrs)); 3979 3980 accel_attrs.esn = attr->esn; 3981 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW) 3982 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP; 3983 else 3984 accel_attrs.flags &= ~MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP; 3985 3986 err = mlx5_accel_esp_modify_xfrm(maction->esp_aes_gcm.ctx, 3987 &accel_attrs); 3988 if (err) 3989 return err; 3990 3991 maction->esp_aes_gcm.ib_flags &= 3992 ~IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW; 3993 maction->esp_aes_gcm.ib_flags |= 3994 attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW; 3995 3996 return 0; 3997 } 3998 3999 static int mlx5_ib_destroy_flow_action(struct ib_flow_action *action) 4000 { 4001 struct mlx5_ib_flow_action *maction = to_mflow_act(action); 4002 4003 switch (action->type) { 4004 case IB_FLOW_ACTION_ESP: 4005 /* 4006 * We only support aes_gcm by now, so we implicitly know this is 4007 * the underline crypto. 4008 */ 4009 mlx5_accel_esp_destroy_xfrm(maction->esp_aes_gcm.ctx); 4010 break; 4011 default: 4012 WARN_ON(true); 4013 break; 4014 } 4015 4016 kfree(maction); 4017 return 0; 4018 } 4019 4020 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 4021 { 4022 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4023 struct mlx5_ib_qp *mqp = to_mqp(ibqp); 4024 int err; 4025 4026 if (mqp->flags & MLX5_IB_QP_UNDERLAY) { 4027 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n"); 4028 return -EOPNOTSUPP; 4029 } 4030 4031 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num); 4032 if (err) 4033 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 4034 ibqp->qp_num, gid->raw); 4035 4036 return err; 4037 } 4038 4039 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 4040 { 4041 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4042 int err; 4043 4044 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num); 4045 if (err) 4046 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 4047 ibqp->qp_num, gid->raw); 4048 4049 return err; 4050 } 4051 4052 static int init_node_data(struct mlx5_ib_dev *dev) 4053 { 4054 int err; 4055 4056 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 4057 if (err) 4058 return err; 4059 4060 dev->mdev->rev_id = dev->mdev->pdev->revision; 4061 4062 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 4063 } 4064 4065 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr, 4066 char *buf) 4067 { 4068 struct mlx5_ib_dev *dev = 4069 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 4070 4071 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages); 4072 } 4073 4074 static ssize_t show_reg_pages(struct device *device, 4075 struct device_attribute *attr, char *buf) 4076 { 4077 struct mlx5_ib_dev *dev = 4078 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 4079 4080 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 4081 } 4082 4083 static ssize_t show_hca(struct device *device, struct device_attribute *attr, 4084 char *buf) 4085 { 4086 struct mlx5_ib_dev *dev = 4087 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 4088 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device); 4089 } 4090 4091 static ssize_t show_rev(struct device *device, struct device_attribute *attr, 4092 char *buf) 4093 { 4094 struct mlx5_ib_dev *dev = 4095 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 4096 return sprintf(buf, "%x\n", dev->mdev->rev_id); 4097 } 4098 4099 static ssize_t show_board(struct device *device, struct device_attribute *attr, 4100 char *buf) 4101 { 4102 struct mlx5_ib_dev *dev = 4103 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 4104 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 4105 dev->mdev->board_id); 4106 } 4107 4108 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL); 4109 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL); 4110 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL); 4111 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL); 4112 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL); 4113 4114 static struct device_attribute *mlx5_class_attributes[] = { 4115 &dev_attr_hw_rev, 4116 &dev_attr_hca_type, 4117 &dev_attr_board_id, 4118 &dev_attr_fw_pages, 4119 &dev_attr_reg_pages, 4120 }; 4121 4122 static void pkey_change_handler(struct work_struct *work) 4123 { 4124 struct mlx5_ib_port_resources *ports = 4125 container_of(work, struct mlx5_ib_port_resources, 4126 pkey_change_work); 4127 4128 mutex_lock(&ports->devr->mutex); 4129 mlx5_ib_gsi_pkey_change(ports->gsi); 4130 mutex_unlock(&ports->devr->mutex); 4131 } 4132 4133 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 4134 { 4135 struct mlx5_ib_qp *mqp; 4136 struct mlx5_ib_cq *send_mcq, *recv_mcq; 4137 struct mlx5_core_cq *mcq; 4138 struct list_head cq_armed_list; 4139 unsigned long flags_qp; 4140 unsigned long flags_cq; 4141 unsigned long flags; 4142 4143 INIT_LIST_HEAD(&cq_armed_list); 4144 4145 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 4146 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 4147 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 4148 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 4149 if (mqp->sq.tail != mqp->sq.head) { 4150 send_mcq = to_mcq(mqp->ibqp.send_cq); 4151 spin_lock_irqsave(&send_mcq->lock, flags_cq); 4152 if (send_mcq->mcq.comp && 4153 mqp->ibqp.send_cq->comp_handler) { 4154 if (!send_mcq->mcq.reset_notify_added) { 4155 send_mcq->mcq.reset_notify_added = 1; 4156 list_add_tail(&send_mcq->mcq.reset_notify, 4157 &cq_armed_list); 4158 } 4159 } 4160 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 4161 } 4162 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 4163 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 4164 /* no handling is needed for SRQ */ 4165 if (!mqp->ibqp.srq) { 4166 if (mqp->rq.tail != mqp->rq.head) { 4167 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 4168 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 4169 if (recv_mcq->mcq.comp && 4170 mqp->ibqp.recv_cq->comp_handler) { 4171 if (!recv_mcq->mcq.reset_notify_added) { 4172 recv_mcq->mcq.reset_notify_added = 1; 4173 list_add_tail(&recv_mcq->mcq.reset_notify, 4174 &cq_armed_list); 4175 } 4176 } 4177 spin_unlock_irqrestore(&recv_mcq->lock, 4178 flags_cq); 4179 } 4180 } 4181 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 4182 } 4183 /*At that point all inflight post send were put to be executed as of we 4184 * lock/unlock above locks Now need to arm all involved CQs. 4185 */ 4186 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 4187 mcq->comp(mcq); 4188 } 4189 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 4190 } 4191 4192 static void delay_drop_handler(struct work_struct *work) 4193 { 4194 int err; 4195 struct mlx5_ib_delay_drop *delay_drop = 4196 container_of(work, struct mlx5_ib_delay_drop, 4197 delay_drop_work); 4198 4199 atomic_inc(&delay_drop->events_cnt); 4200 4201 mutex_lock(&delay_drop->lock); 4202 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev, 4203 delay_drop->timeout); 4204 if (err) { 4205 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n", 4206 delay_drop->timeout); 4207 delay_drop->activate = false; 4208 } 4209 mutex_unlock(&delay_drop->lock); 4210 } 4211 4212 static void mlx5_ib_handle_event(struct work_struct *_work) 4213 { 4214 struct mlx5_ib_event_work *work = 4215 container_of(_work, struct mlx5_ib_event_work, work); 4216 struct mlx5_ib_dev *ibdev; 4217 struct ib_event ibev; 4218 bool fatal = false; 4219 u8 port = (u8)work->param; 4220 4221 if (mlx5_core_is_mp_slave(work->dev)) { 4222 ibdev = mlx5_ib_get_ibdev_from_mpi(work->context); 4223 if (!ibdev) 4224 goto out; 4225 } else { 4226 ibdev = work->context; 4227 } 4228 4229 switch (work->event) { 4230 case MLX5_DEV_EVENT_SYS_ERROR: 4231 ibev.event = IB_EVENT_DEVICE_FATAL; 4232 mlx5_ib_handle_internal_error(ibdev); 4233 fatal = true; 4234 break; 4235 4236 case MLX5_DEV_EVENT_PORT_UP: 4237 case MLX5_DEV_EVENT_PORT_DOWN: 4238 case MLX5_DEV_EVENT_PORT_INITIALIZED: 4239 /* In RoCE, port up/down events are handled in 4240 * mlx5_netdev_event(). 4241 */ 4242 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 4243 IB_LINK_LAYER_ETHERNET) 4244 goto out; 4245 4246 ibev.event = (work->event == MLX5_DEV_EVENT_PORT_UP) ? 4247 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 4248 break; 4249 4250 case MLX5_DEV_EVENT_LID_CHANGE: 4251 ibev.event = IB_EVENT_LID_CHANGE; 4252 break; 4253 4254 case MLX5_DEV_EVENT_PKEY_CHANGE: 4255 ibev.event = IB_EVENT_PKEY_CHANGE; 4256 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 4257 break; 4258 4259 case MLX5_DEV_EVENT_GUID_CHANGE: 4260 ibev.event = IB_EVENT_GID_CHANGE; 4261 break; 4262 4263 case MLX5_DEV_EVENT_CLIENT_REREG: 4264 ibev.event = IB_EVENT_CLIENT_REREGISTER; 4265 break; 4266 case MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT: 4267 schedule_work(&ibdev->delay_drop.delay_drop_work); 4268 goto out; 4269 default: 4270 goto out; 4271 } 4272 4273 ibev.device = &ibdev->ib_dev; 4274 ibev.element.port_num = port; 4275 4276 if (!rdma_is_port_valid(&ibdev->ib_dev, port)) { 4277 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port); 4278 goto out; 4279 } 4280 4281 if (ibdev->ib_active) 4282 ib_dispatch_event(&ibev); 4283 4284 if (fatal) 4285 ibdev->ib_active = false; 4286 out: 4287 kfree(work); 4288 } 4289 4290 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context, 4291 enum mlx5_dev_event event, unsigned long param) 4292 { 4293 struct mlx5_ib_event_work *work; 4294 4295 work = kmalloc(sizeof(*work), GFP_ATOMIC); 4296 if (!work) 4297 return; 4298 4299 INIT_WORK(&work->work, mlx5_ib_handle_event); 4300 work->dev = dev; 4301 work->param = param; 4302 work->context = context; 4303 work->event = event; 4304 4305 queue_work(mlx5_ib_event_wq, &work->work); 4306 } 4307 4308 static int set_has_smi_cap(struct mlx5_ib_dev *dev) 4309 { 4310 struct mlx5_hca_vport_context vport_ctx; 4311 int err; 4312 int port; 4313 4314 for (port = 1; port <= dev->num_ports; port++) { 4315 dev->mdev->port_caps[port - 1].has_smi = false; 4316 if (MLX5_CAP_GEN(dev->mdev, port_type) == 4317 MLX5_CAP_PORT_TYPE_IB) { 4318 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) { 4319 err = mlx5_query_hca_vport_context(dev->mdev, 0, 4320 port, 0, 4321 &vport_ctx); 4322 if (err) { 4323 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n", 4324 port, err); 4325 return err; 4326 } 4327 dev->mdev->port_caps[port - 1].has_smi = 4328 vport_ctx.has_smi; 4329 } else { 4330 dev->mdev->port_caps[port - 1].has_smi = true; 4331 } 4332 } 4333 } 4334 return 0; 4335 } 4336 4337 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 4338 { 4339 int port; 4340 4341 for (port = 1; port <= dev->num_ports; port++) 4342 mlx5_query_ext_port_caps(dev, port); 4343 } 4344 4345 static int get_port_caps(struct mlx5_ib_dev *dev, u8 port) 4346 { 4347 struct ib_device_attr *dprops = NULL; 4348 struct ib_port_attr *pprops = NULL; 4349 int err = -ENOMEM; 4350 struct ib_udata uhw = {.inlen = 0, .outlen = 0}; 4351 4352 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL); 4353 if (!pprops) 4354 goto out; 4355 4356 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL); 4357 if (!dprops) 4358 goto out; 4359 4360 err = set_has_smi_cap(dev); 4361 if (err) 4362 goto out; 4363 4364 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw); 4365 if (err) { 4366 mlx5_ib_warn(dev, "query_device failed %d\n", err); 4367 goto out; 4368 } 4369 4370 memset(pprops, 0, sizeof(*pprops)); 4371 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops); 4372 if (err) { 4373 mlx5_ib_warn(dev, "query_port %d failed %d\n", 4374 port, err); 4375 goto out; 4376 } 4377 4378 dev->mdev->port_caps[port - 1].pkey_table_len = 4379 dprops->max_pkeys; 4380 dev->mdev->port_caps[port - 1].gid_table_len = 4381 pprops->gid_tbl_len; 4382 mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n", 4383 port, dprops->max_pkeys, pprops->gid_tbl_len); 4384 4385 out: 4386 kfree(pprops); 4387 kfree(dprops); 4388 4389 return err; 4390 } 4391 4392 static void destroy_umrc_res(struct mlx5_ib_dev *dev) 4393 { 4394 int err; 4395 4396 err = mlx5_mr_cache_cleanup(dev); 4397 if (err) 4398 mlx5_ib_warn(dev, "mr cache cleanup failed\n"); 4399 4400 if (dev->umrc.qp) 4401 mlx5_ib_destroy_qp(dev->umrc.qp); 4402 if (dev->umrc.cq) 4403 ib_free_cq(dev->umrc.cq); 4404 if (dev->umrc.pd) 4405 ib_dealloc_pd(dev->umrc.pd); 4406 } 4407 4408 enum { 4409 MAX_UMR_WR = 128, 4410 }; 4411 4412 static int create_umr_res(struct mlx5_ib_dev *dev) 4413 { 4414 struct ib_qp_init_attr *init_attr = NULL; 4415 struct ib_qp_attr *attr = NULL; 4416 struct ib_pd *pd; 4417 struct ib_cq *cq; 4418 struct ib_qp *qp; 4419 int ret; 4420 4421 attr = kzalloc(sizeof(*attr), GFP_KERNEL); 4422 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL); 4423 if (!attr || !init_attr) { 4424 ret = -ENOMEM; 4425 goto error_0; 4426 } 4427 4428 pd = ib_alloc_pd(&dev->ib_dev, 0); 4429 if (IS_ERR(pd)) { 4430 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n"); 4431 ret = PTR_ERR(pd); 4432 goto error_0; 4433 } 4434 4435 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ); 4436 if (IS_ERR(cq)) { 4437 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n"); 4438 ret = PTR_ERR(cq); 4439 goto error_2; 4440 } 4441 4442 init_attr->send_cq = cq; 4443 init_attr->recv_cq = cq; 4444 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR; 4445 init_attr->cap.max_send_wr = MAX_UMR_WR; 4446 init_attr->cap.max_send_sge = 1; 4447 init_attr->qp_type = MLX5_IB_QPT_REG_UMR; 4448 init_attr->port_num = 1; 4449 qp = mlx5_ib_create_qp(pd, init_attr, NULL); 4450 if (IS_ERR(qp)) { 4451 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n"); 4452 ret = PTR_ERR(qp); 4453 goto error_3; 4454 } 4455 qp->device = &dev->ib_dev; 4456 qp->real_qp = qp; 4457 qp->uobject = NULL; 4458 qp->qp_type = MLX5_IB_QPT_REG_UMR; 4459 qp->send_cq = init_attr->send_cq; 4460 qp->recv_cq = init_attr->recv_cq; 4461 4462 attr->qp_state = IB_QPS_INIT; 4463 attr->port_num = 1; 4464 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX | 4465 IB_QP_PORT, NULL); 4466 if (ret) { 4467 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n"); 4468 goto error_4; 4469 } 4470 4471 memset(attr, 0, sizeof(*attr)); 4472 attr->qp_state = IB_QPS_RTR; 4473 attr->path_mtu = IB_MTU_256; 4474 4475 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 4476 if (ret) { 4477 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n"); 4478 goto error_4; 4479 } 4480 4481 memset(attr, 0, sizeof(*attr)); 4482 attr->qp_state = IB_QPS_RTS; 4483 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 4484 if (ret) { 4485 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n"); 4486 goto error_4; 4487 } 4488 4489 dev->umrc.qp = qp; 4490 dev->umrc.cq = cq; 4491 dev->umrc.pd = pd; 4492 4493 sema_init(&dev->umrc.sem, MAX_UMR_WR); 4494 ret = mlx5_mr_cache_init(dev); 4495 if (ret) { 4496 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 4497 goto error_4; 4498 } 4499 4500 kfree(attr); 4501 kfree(init_attr); 4502 4503 return 0; 4504 4505 error_4: 4506 mlx5_ib_destroy_qp(qp); 4507 dev->umrc.qp = NULL; 4508 4509 error_3: 4510 ib_free_cq(cq); 4511 dev->umrc.cq = NULL; 4512 4513 error_2: 4514 ib_dealloc_pd(pd); 4515 dev->umrc.pd = NULL; 4516 4517 error_0: 4518 kfree(attr); 4519 kfree(init_attr); 4520 return ret; 4521 } 4522 4523 static u8 mlx5_get_umr_fence(u8 umr_fence_cap) 4524 { 4525 switch (umr_fence_cap) { 4526 case MLX5_CAP_UMR_FENCE_NONE: 4527 return MLX5_FENCE_MODE_NONE; 4528 case MLX5_CAP_UMR_FENCE_SMALL: 4529 return MLX5_FENCE_MODE_INITIATOR_SMALL; 4530 default: 4531 return MLX5_FENCE_MODE_STRONG_ORDERING; 4532 } 4533 } 4534 4535 static int create_dev_resources(struct mlx5_ib_resources *devr) 4536 { 4537 struct ib_srq_init_attr attr; 4538 struct mlx5_ib_dev *dev; 4539 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 4540 int port; 4541 int ret = 0; 4542 4543 dev = container_of(devr, struct mlx5_ib_dev, devr); 4544 4545 mutex_init(&devr->mutex); 4546 4547 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL); 4548 if (IS_ERR(devr->p0)) { 4549 ret = PTR_ERR(devr->p0); 4550 goto error0; 4551 } 4552 devr->p0->device = &dev->ib_dev; 4553 devr->p0->uobject = NULL; 4554 atomic_set(&devr->p0->usecnt, 0); 4555 4556 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL); 4557 if (IS_ERR(devr->c0)) { 4558 ret = PTR_ERR(devr->c0); 4559 goto error1; 4560 } 4561 devr->c0->device = &dev->ib_dev; 4562 devr->c0->uobject = NULL; 4563 devr->c0->comp_handler = NULL; 4564 devr->c0->event_handler = NULL; 4565 devr->c0->cq_context = NULL; 4566 atomic_set(&devr->c0->usecnt, 0); 4567 4568 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 4569 if (IS_ERR(devr->x0)) { 4570 ret = PTR_ERR(devr->x0); 4571 goto error2; 4572 } 4573 devr->x0->device = &dev->ib_dev; 4574 devr->x0->inode = NULL; 4575 atomic_set(&devr->x0->usecnt, 0); 4576 mutex_init(&devr->x0->tgt_qp_mutex); 4577 INIT_LIST_HEAD(&devr->x0->tgt_qp_list); 4578 4579 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 4580 if (IS_ERR(devr->x1)) { 4581 ret = PTR_ERR(devr->x1); 4582 goto error3; 4583 } 4584 devr->x1->device = &dev->ib_dev; 4585 devr->x1->inode = NULL; 4586 atomic_set(&devr->x1->usecnt, 0); 4587 mutex_init(&devr->x1->tgt_qp_mutex); 4588 INIT_LIST_HEAD(&devr->x1->tgt_qp_list); 4589 4590 memset(&attr, 0, sizeof(attr)); 4591 attr.attr.max_sge = 1; 4592 attr.attr.max_wr = 1; 4593 attr.srq_type = IB_SRQT_XRC; 4594 attr.ext.cq = devr->c0; 4595 attr.ext.xrc.xrcd = devr->x0; 4596 4597 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 4598 if (IS_ERR(devr->s0)) { 4599 ret = PTR_ERR(devr->s0); 4600 goto error4; 4601 } 4602 devr->s0->device = &dev->ib_dev; 4603 devr->s0->pd = devr->p0; 4604 devr->s0->uobject = NULL; 4605 devr->s0->event_handler = NULL; 4606 devr->s0->srq_context = NULL; 4607 devr->s0->srq_type = IB_SRQT_XRC; 4608 devr->s0->ext.xrc.xrcd = devr->x0; 4609 devr->s0->ext.cq = devr->c0; 4610 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt); 4611 atomic_inc(&devr->s0->ext.cq->usecnt); 4612 atomic_inc(&devr->p0->usecnt); 4613 atomic_set(&devr->s0->usecnt, 0); 4614 4615 memset(&attr, 0, sizeof(attr)); 4616 attr.attr.max_sge = 1; 4617 attr.attr.max_wr = 1; 4618 attr.srq_type = IB_SRQT_BASIC; 4619 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 4620 if (IS_ERR(devr->s1)) { 4621 ret = PTR_ERR(devr->s1); 4622 goto error5; 4623 } 4624 devr->s1->device = &dev->ib_dev; 4625 devr->s1->pd = devr->p0; 4626 devr->s1->uobject = NULL; 4627 devr->s1->event_handler = NULL; 4628 devr->s1->srq_context = NULL; 4629 devr->s1->srq_type = IB_SRQT_BASIC; 4630 devr->s1->ext.cq = devr->c0; 4631 atomic_inc(&devr->p0->usecnt); 4632 atomic_set(&devr->s1->usecnt, 0); 4633 4634 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) { 4635 INIT_WORK(&devr->ports[port].pkey_change_work, 4636 pkey_change_handler); 4637 devr->ports[port].devr = devr; 4638 } 4639 4640 return 0; 4641 4642 error5: 4643 mlx5_ib_destroy_srq(devr->s0); 4644 error4: 4645 mlx5_ib_dealloc_xrcd(devr->x1); 4646 error3: 4647 mlx5_ib_dealloc_xrcd(devr->x0); 4648 error2: 4649 mlx5_ib_destroy_cq(devr->c0); 4650 error1: 4651 mlx5_ib_dealloc_pd(devr->p0); 4652 error0: 4653 return ret; 4654 } 4655 4656 static void destroy_dev_resources(struct mlx5_ib_resources *devr) 4657 { 4658 struct mlx5_ib_dev *dev = 4659 container_of(devr, struct mlx5_ib_dev, devr); 4660 int port; 4661 4662 mlx5_ib_destroy_srq(devr->s1); 4663 mlx5_ib_destroy_srq(devr->s0); 4664 mlx5_ib_dealloc_xrcd(devr->x0); 4665 mlx5_ib_dealloc_xrcd(devr->x1); 4666 mlx5_ib_destroy_cq(devr->c0); 4667 mlx5_ib_dealloc_pd(devr->p0); 4668 4669 /* Make sure no change P_Key work items are still executing */ 4670 for (port = 0; port < dev->num_ports; ++port) 4671 cancel_work_sync(&devr->ports[port].pkey_change_work); 4672 } 4673 4674 static u32 get_core_cap_flags(struct ib_device *ibdev, 4675 struct mlx5_hca_vport_context *rep) 4676 { 4677 struct mlx5_ib_dev *dev = to_mdev(ibdev); 4678 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 4679 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 4680 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 4681 bool raw_support = !mlx5_core_mp_enabled(dev->mdev); 4682 u32 ret = 0; 4683 4684 if (rep->grh_required) 4685 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED; 4686 4687 if (ll == IB_LINK_LAYER_INFINIBAND) 4688 return ret | RDMA_CORE_PORT_IBA_IB; 4689 4690 if (raw_support) 4691 ret |= RDMA_CORE_PORT_RAW_PACKET; 4692 4693 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 4694 return ret; 4695 4696 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 4697 return ret; 4698 4699 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 4700 ret |= RDMA_CORE_PORT_IBA_ROCE; 4701 4702 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 4703 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 4704 4705 return ret; 4706 } 4707 4708 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num, 4709 struct ib_port_immutable *immutable) 4710 { 4711 struct ib_port_attr attr; 4712 struct mlx5_ib_dev *dev = to_mdev(ibdev); 4713 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num); 4714 struct mlx5_hca_vport_context rep = {0}; 4715 int err; 4716 4717 err = ib_query_port(ibdev, port_num, &attr); 4718 if (err) 4719 return err; 4720 4721 if (ll == IB_LINK_LAYER_INFINIBAND) { 4722 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0, 4723 &rep); 4724 if (err) 4725 return err; 4726 } 4727 4728 immutable->pkey_tbl_len = attr.pkey_tbl_len; 4729 immutable->gid_tbl_len = attr.gid_tbl_len; 4730 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep); 4731 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce)) 4732 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 4733 4734 return 0; 4735 } 4736 4737 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num, 4738 struct ib_port_immutable *immutable) 4739 { 4740 struct ib_port_attr attr; 4741 int err; 4742 4743 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 4744 4745 err = ib_query_port(ibdev, port_num, &attr); 4746 if (err) 4747 return err; 4748 4749 immutable->pkey_tbl_len = attr.pkey_tbl_len; 4750 immutable->gid_tbl_len = attr.gid_tbl_len; 4751 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 4752 4753 return 0; 4754 } 4755 4756 static void get_dev_fw_str(struct ib_device *ibdev, char *str) 4757 { 4758 struct mlx5_ib_dev *dev = 4759 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 4760 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d", 4761 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev), 4762 fw_rev_sub(dev->mdev)); 4763 } 4764 4765 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev) 4766 { 4767 struct mlx5_core_dev *mdev = dev->mdev; 4768 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev, 4769 MLX5_FLOW_NAMESPACE_LAG); 4770 struct mlx5_flow_table *ft; 4771 int err; 4772 4773 if (!ns || !mlx5_lag_is_active(mdev)) 4774 return 0; 4775 4776 err = mlx5_cmd_create_vport_lag(mdev); 4777 if (err) 4778 return err; 4779 4780 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0); 4781 if (IS_ERR(ft)) { 4782 err = PTR_ERR(ft); 4783 goto err_destroy_vport_lag; 4784 } 4785 4786 dev->flow_db->lag_demux_ft = ft; 4787 return 0; 4788 4789 err_destroy_vport_lag: 4790 mlx5_cmd_destroy_vport_lag(mdev); 4791 return err; 4792 } 4793 4794 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev) 4795 { 4796 struct mlx5_core_dev *mdev = dev->mdev; 4797 4798 if (dev->flow_db->lag_demux_ft) { 4799 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft); 4800 dev->flow_db->lag_demux_ft = NULL; 4801 4802 mlx5_cmd_destroy_vport_lag(mdev); 4803 } 4804 } 4805 4806 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num) 4807 { 4808 int err; 4809 4810 dev->roce[port_num].nb.notifier_call = mlx5_netdev_event; 4811 err = register_netdevice_notifier(&dev->roce[port_num].nb); 4812 if (err) { 4813 dev->roce[port_num].nb.notifier_call = NULL; 4814 return err; 4815 } 4816 4817 return 0; 4818 } 4819 4820 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num) 4821 { 4822 if (dev->roce[port_num].nb.notifier_call) { 4823 unregister_netdevice_notifier(&dev->roce[port_num].nb); 4824 dev->roce[port_num].nb.notifier_call = NULL; 4825 } 4826 } 4827 4828 static int mlx5_enable_eth(struct mlx5_ib_dev *dev) 4829 { 4830 int err; 4831 4832 if (MLX5_CAP_GEN(dev->mdev, roce)) { 4833 err = mlx5_nic_vport_enable_roce(dev->mdev); 4834 if (err) 4835 return err; 4836 } 4837 4838 err = mlx5_eth_lag_init(dev); 4839 if (err) 4840 goto err_disable_roce; 4841 4842 return 0; 4843 4844 err_disable_roce: 4845 if (MLX5_CAP_GEN(dev->mdev, roce)) 4846 mlx5_nic_vport_disable_roce(dev->mdev); 4847 4848 return err; 4849 } 4850 4851 static void mlx5_disable_eth(struct mlx5_ib_dev *dev) 4852 { 4853 mlx5_eth_lag_cleanup(dev); 4854 if (MLX5_CAP_GEN(dev->mdev, roce)) 4855 mlx5_nic_vport_disable_roce(dev->mdev); 4856 } 4857 4858 struct mlx5_ib_counter { 4859 const char *name; 4860 size_t offset; 4861 }; 4862 4863 #define INIT_Q_COUNTER(_name) \ 4864 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)} 4865 4866 static const struct mlx5_ib_counter basic_q_cnts[] = { 4867 INIT_Q_COUNTER(rx_write_requests), 4868 INIT_Q_COUNTER(rx_read_requests), 4869 INIT_Q_COUNTER(rx_atomic_requests), 4870 INIT_Q_COUNTER(out_of_buffer), 4871 }; 4872 4873 static const struct mlx5_ib_counter out_of_seq_q_cnts[] = { 4874 INIT_Q_COUNTER(out_of_sequence), 4875 }; 4876 4877 static const struct mlx5_ib_counter retrans_q_cnts[] = { 4878 INIT_Q_COUNTER(duplicate_request), 4879 INIT_Q_COUNTER(rnr_nak_retry_err), 4880 INIT_Q_COUNTER(packet_seq_err), 4881 INIT_Q_COUNTER(implied_nak_seq_err), 4882 INIT_Q_COUNTER(local_ack_timeout_err), 4883 }; 4884 4885 #define INIT_CONG_COUNTER(_name) \ 4886 { .name = #_name, .offset = \ 4887 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)} 4888 4889 static const struct mlx5_ib_counter cong_cnts[] = { 4890 INIT_CONG_COUNTER(rp_cnp_ignored), 4891 INIT_CONG_COUNTER(rp_cnp_handled), 4892 INIT_CONG_COUNTER(np_ecn_marked_roce_packets), 4893 INIT_CONG_COUNTER(np_cnp_sent), 4894 }; 4895 4896 static const struct mlx5_ib_counter extended_err_cnts[] = { 4897 INIT_Q_COUNTER(resp_local_length_error), 4898 INIT_Q_COUNTER(resp_cqe_error), 4899 INIT_Q_COUNTER(req_cqe_error), 4900 INIT_Q_COUNTER(req_remote_invalid_request), 4901 INIT_Q_COUNTER(req_remote_access_errors), 4902 INIT_Q_COUNTER(resp_remote_access_errors), 4903 INIT_Q_COUNTER(resp_cqe_flush_error), 4904 INIT_Q_COUNTER(req_cqe_flush_error), 4905 }; 4906 4907 #define INIT_EXT_PPCNT_COUNTER(_name) \ 4908 { .name = #_name, .offset = \ 4909 MLX5_BYTE_OFF(ppcnt_reg, \ 4910 counter_set.eth_extended_cntrs_grp_data_layout._name##_high)} 4911 4912 static const struct mlx5_ib_counter ext_ppcnt_cnts[] = { 4913 INIT_EXT_PPCNT_COUNTER(rx_icrc_encapsulated), 4914 }; 4915 4916 static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev) 4917 { 4918 int i; 4919 4920 for (i = 0; i < dev->num_ports; i++) { 4921 if (dev->port[i].cnts.set_id_valid) 4922 mlx5_core_dealloc_q_counter(dev->mdev, 4923 dev->port[i].cnts.set_id); 4924 kfree(dev->port[i].cnts.names); 4925 kfree(dev->port[i].cnts.offsets); 4926 } 4927 } 4928 4929 static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev, 4930 struct mlx5_ib_counters *cnts) 4931 { 4932 u32 num_counters; 4933 4934 num_counters = ARRAY_SIZE(basic_q_cnts); 4935 4936 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) 4937 num_counters += ARRAY_SIZE(out_of_seq_q_cnts); 4938 4939 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) 4940 num_counters += ARRAY_SIZE(retrans_q_cnts); 4941 4942 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) 4943 num_counters += ARRAY_SIZE(extended_err_cnts); 4944 4945 cnts->num_q_counters = num_counters; 4946 4947 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 4948 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts); 4949 num_counters += ARRAY_SIZE(cong_cnts); 4950 } 4951 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) { 4952 cnts->num_ext_ppcnt_counters = ARRAY_SIZE(ext_ppcnt_cnts); 4953 num_counters += ARRAY_SIZE(ext_ppcnt_cnts); 4954 } 4955 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL); 4956 if (!cnts->names) 4957 return -ENOMEM; 4958 4959 cnts->offsets = kcalloc(num_counters, 4960 sizeof(cnts->offsets), GFP_KERNEL); 4961 if (!cnts->offsets) 4962 goto err_names; 4963 4964 return 0; 4965 4966 err_names: 4967 kfree(cnts->names); 4968 cnts->names = NULL; 4969 return -ENOMEM; 4970 } 4971 4972 static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev, 4973 const char **names, 4974 size_t *offsets) 4975 { 4976 int i; 4977 int j = 0; 4978 4979 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) { 4980 names[j] = basic_q_cnts[i].name; 4981 offsets[j] = basic_q_cnts[i].offset; 4982 } 4983 4984 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) { 4985 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) { 4986 names[j] = out_of_seq_q_cnts[i].name; 4987 offsets[j] = out_of_seq_q_cnts[i].offset; 4988 } 4989 } 4990 4991 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) { 4992 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) { 4993 names[j] = retrans_q_cnts[i].name; 4994 offsets[j] = retrans_q_cnts[i].offset; 4995 } 4996 } 4997 4998 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) { 4999 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) { 5000 names[j] = extended_err_cnts[i].name; 5001 offsets[j] = extended_err_cnts[i].offset; 5002 } 5003 } 5004 5005 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 5006 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) { 5007 names[j] = cong_cnts[i].name; 5008 offsets[j] = cong_cnts[i].offset; 5009 } 5010 } 5011 5012 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) { 5013 for (i = 0; i < ARRAY_SIZE(ext_ppcnt_cnts); i++, j++) { 5014 names[j] = ext_ppcnt_cnts[i].name; 5015 offsets[j] = ext_ppcnt_cnts[i].offset; 5016 } 5017 } 5018 } 5019 5020 static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev) 5021 { 5022 int err = 0; 5023 int i; 5024 5025 for (i = 0; i < dev->num_ports; i++) { 5026 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts); 5027 if (err) 5028 goto err_alloc; 5029 5030 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names, 5031 dev->port[i].cnts.offsets); 5032 5033 err = mlx5_core_alloc_q_counter(dev->mdev, 5034 &dev->port[i].cnts.set_id); 5035 if (err) { 5036 mlx5_ib_warn(dev, 5037 "couldn't allocate queue counter for port %d, err %d\n", 5038 i + 1, err); 5039 goto err_alloc; 5040 } 5041 dev->port[i].cnts.set_id_valid = true; 5042 } 5043 5044 return 0; 5045 5046 err_alloc: 5047 mlx5_ib_dealloc_counters(dev); 5048 return err; 5049 } 5050 5051 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev, 5052 u8 port_num) 5053 { 5054 struct mlx5_ib_dev *dev = to_mdev(ibdev); 5055 struct mlx5_ib_port *port = &dev->port[port_num - 1]; 5056 5057 /* We support only per port stats */ 5058 if (port_num == 0) 5059 return NULL; 5060 5061 return rdma_alloc_hw_stats_struct(port->cnts.names, 5062 port->cnts.num_q_counters + 5063 port->cnts.num_cong_counters + 5064 port->cnts.num_ext_ppcnt_counters, 5065 RDMA_HW_STATS_DEFAULT_LIFESPAN); 5066 } 5067 5068 static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev, 5069 struct mlx5_ib_port *port, 5070 struct rdma_hw_stats *stats) 5071 { 5072 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out); 5073 void *out; 5074 __be32 val; 5075 int ret, i; 5076 5077 out = kvzalloc(outlen, GFP_KERNEL); 5078 if (!out) 5079 return -ENOMEM; 5080 5081 ret = mlx5_core_query_q_counter(mdev, 5082 port->cnts.set_id, 0, 5083 out, outlen); 5084 if (ret) 5085 goto free; 5086 5087 for (i = 0; i < port->cnts.num_q_counters; i++) { 5088 val = *(__be32 *)(out + port->cnts.offsets[i]); 5089 stats->value[i] = (u64)be32_to_cpu(val); 5090 } 5091 5092 free: 5093 kvfree(out); 5094 return ret; 5095 } 5096 5097 static int mlx5_ib_query_ext_ppcnt_counters(struct mlx5_ib_dev *dev, 5098 struct mlx5_ib_port *port, 5099 struct rdma_hw_stats *stats) 5100 { 5101 int offset = port->cnts.num_q_counters + port->cnts.num_cong_counters; 5102 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg); 5103 int ret, i; 5104 void *out; 5105 5106 out = kvzalloc(sz, GFP_KERNEL); 5107 if (!out) 5108 return -ENOMEM; 5109 5110 ret = mlx5_cmd_query_ext_ppcnt_counters(dev->mdev, out); 5111 if (ret) 5112 goto free; 5113 5114 for (i = 0; i < port->cnts.num_ext_ppcnt_counters; i++) { 5115 stats->value[i + offset] = 5116 be64_to_cpup((__be64 *)(out + 5117 port->cnts.offsets[i + offset])); 5118 } 5119 5120 free: 5121 kvfree(out); 5122 return ret; 5123 } 5124 5125 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev, 5126 struct rdma_hw_stats *stats, 5127 u8 port_num, int index) 5128 { 5129 struct mlx5_ib_dev *dev = to_mdev(ibdev); 5130 struct mlx5_ib_port *port = &dev->port[port_num - 1]; 5131 struct mlx5_core_dev *mdev; 5132 int ret, num_counters; 5133 u8 mdev_port_num; 5134 5135 if (!stats) 5136 return -EINVAL; 5137 5138 num_counters = port->cnts.num_q_counters + 5139 port->cnts.num_cong_counters + 5140 port->cnts.num_ext_ppcnt_counters; 5141 5142 /* q_counters are per IB device, query the master mdev */ 5143 ret = mlx5_ib_query_q_counters(dev->mdev, port, stats); 5144 if (ret) 5145 return ret; 5146 5147 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) { 5148 ret = mlx5_ib_query_ext_ppcnt_counters(dev, port, stats); 5149 if (ret) 5150 return ret; 5151 } 5152 5153 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 5154 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, 5155 &mdev_port_num); 5156 if (!mdev) { 5157 /* If port is not affiliated yet, its in down state 5158 * which doesn't have any counters yet, so it would be 5159 * zero. So no need to read from the HCA. 5160 */ 5161 goto done; 5162 } 5163 ret = mlx5_lag_query_cong_counters(dev->mdev, 5164 stats->value + 5165 port->cnts.num_q_counters, 5166 port->cnts.num_cong_counters, 5167 port->cnts.offsets + 5168 port->cnts.num_q_counters); 5169 5170 mlx5_ib_put_native_port_mdev(dev, port_num); 5171 if (ret) 5172 return ret; 5173 } 5174 5175 done: 5176 return num_counters; 5177 } 5178 5179 static struct net_device* 5180 mlx5_ib_alloc_rdma_netdev(struct ib_device *hca, 5181 u8 port_num, 5182 enum rdma_netdev_t type, 5183 const char *name, 5184 unsigned char name_assign_type, 5185 void (*setup)(struct net_device *)) 5186 { 5187 struct net_device *netdev; 5188 5189 if (type != RDMA_NETDEV_IPOIB) 5190 return ERR_PTR(-EOPNOTSUPP); 5191 5192 netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca, 5193 name, setup); 5194 return netdev; 5195 } 5196 5197 static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev) 5198 { 5199 if (!dev->delay_drop.dbg) 5200 return; 5201 debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs); 5202 kfree(dev->delay_drop.dbg); 5203 dev->delay_drop.dbg = NULL; 5204 } 5205 5206 static void cancel_delay_drop(struct mlx5_ib_dev *dev) 5207 { 5208 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 5209 return; 5210 5211 cancel_work_sync(&dev->delay_drop.delay_drop_work); 5212 delay_drop_debugfs_cleanup(dev); 5213 } 5214 5215 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf, 5216 size_t count, loff_t *pos) 5217 { 5218 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 5219 char lbuf[20]; 5220 int len; 5221 5222 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout); 5223 return simple_read_from_buffer(buf, count, pos, lbuf, len); 5224 } 5225 5226 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf, 5227 size_t count, loff_t *pos) 5228 { 5229 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 5230 u32 timeout; 5231 u32 var; 5232 5233 if (kstrtouint_from_user(buf, count, 0, &var)) 5234 return -EFAULT; 5235 5236 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 5237 1000); 5238 if (timeout != var) 5239 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n", 5240 timeout); 5241 5242 delay_drop->timeout = timeout; 5243 5244 return count; 5245 } 5246 5247 static const struct file_operations fops_delay_drop_timeout = { 5248 .owner = THIS_MODULE, 5249 .open = simple_open, 5250 .write = delay_drop_timeout_write, 5251 .read = delay_drop_timeout_read, 5252 }; 5253 5254 static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev) 5255 { 5256 struct mlx5_ib_dbg_delay_drop *dbg; 5257 5258 if (!mlx5_debugfs_root) 5259 return 0; 5260 5261 dbg = kzalloc(sizeof(*dbg), GFP_KERNEL); 5262 if (!dbg) 5263 return -ENOMEM; 5264 5265 dev->delay_drop.dbg = dbg; 5266 5267 dbg->dir_debugfs = 5268 debugfs_create_dir("delay_drop", 5269 dev->mdev->priv.dbg_root); 5270 if (!dbg->dir_debugfs) 5271 goto out_debugfs; 5272 5273 dbg->events_cnt_debugfs = 5274 debugfs_create_atomic_t("num_timeout_events", 0400, 5275 dbg->dir_debugfs, 5276 &dev->delay_drop.events_cnt); 5277 if (!dbg->events_cnt_debugfs) 5278 goto out_debugfs; 5279 5280 dbg->rqs_cnt_debugfs = 5281 debugfs_create_atomic_t("num_rqs", 0400, 5282 dbg->dir_debugfs, 5283 &dev->delay_drop.rqs_cnt); 5284 if (!dbg->rqs_cnt_debugfs) 5285 goto out_debugfs; 5286 5287 dbg->timeout_debugfs = 5288 debugfs_create_file("timeout", 0600, 5289 dbg->dir_debugfs, 5290 &dev->delay_drop, 5291 &fops_delay_drop_timeout); 5292 if (!dbg->timeout_debugfs) 5293 goto out_debugfs; 5294 5295 return 0; 5296 5297 out_debugfs: 5298 delay_drop_debugfs_cleanup(dev); 5299 return -ENOMEM; 5300 } 5301 5302 static void init_delay_drop(struct mlx5_ib_dev *dev) 5303 { 5304 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 5305 return; 5306 5307 mutex_init(&dev->delay_drop.lock); 5308 dev->delay_drop.dev = dev; 5309 dev->delay_drop.activate = false; 5310 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000; 5311 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler); 5312 atomic_set(&dev->delay_drop.rqs_cnt, 0); 5313 atomic_set(&dev->delay_drop.events_cnt, 0); 5314 5315 if (delay_drop_debugfs_init(dev)) 5316 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n"); 5317 } 5318 5319 static const struct cpumask * 5320 mlx5_ib_get_vector_affinity(struct ib_device *ibdev, int comp_vector) 5321 { 5322 struct mlx5_ib_dev *dev = to_mdev(ibdev); 5323 5324 return mlx5_get_vector_affinity_hint(dev->mdev, comp_vector); 5325 } 5326 5327 /* The mlx5_ib_multiport_mutex should be held when calling this function */ 5328 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev, 5329 struct mlx5_ib_multiport_info *mpi) 5330 { 5331 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 5332 struct mlx5_ib_port *port = &ibdev->port[port_num]; 5333 int comps; 5334 int err; 5335 int i; 5336 5337 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num); 5338 5339 spin_lock(&port->mp.mpi_lock); 5340 if (!mpi->ibdev) { 5341 spin_unlock(&port->mp.mpi_lock); 5342 return; 5343 } 5344 mpi->ibdev = NULL; 5345 5346 spin_unlock(&port->mp.mpi_lock); 5347 mlx5_remove_netdev_notifier(ibdev, port_num); 5348 spin_lock(&port->mp.mpi_lock); 5349 5350 comps = mpi->mdev_refcnt; 5351 if (comps) { 5352 mpi->unaffiliate = true; 5353 init_completion(&mpi->unref_comp); 5354 spin_unlock(&port->mp.mpi_lock); 5355 5356 for (i = 0; i < comps; i++) 5357 wait_for_completion(&mpi->unref_comp); 5358 5359 spin_lock(&port->mp.mpi_lock); 5360 mpi->unaffiliate = false; 5361 } 5362 5363 port->mp.mpi = NULL; 5364 5365 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 5366 5367 spin_unlock(&port->mp.mpi_lock); 5368 5369 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev); 5370 5371 mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1); 5372 /* Log an error, still needed to cleanup the pointers and add 5373 * it back to the list. 5374 */ 5375 if (err) 5376 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n", 5377 port_num + 1); 5378 5379 ibdev->roce[port_num].last_port_state = IB_PORT_DOWN; 5380 } 5381 5382 /* The mlx5_ib_multiport_mutex should be held when calling this function */ 5383 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev, 5384 struct mlx5_ib_multiport_info *mpi) 5385 { 5386 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 5387 int err; 5388 5389 spin_lock(&ibdev->port[port_num].mp.mpi_lock); 5390 if (ibdev->port[port_num].mp.mpi) { 5391 mlx5_ib_dbg(ibdev, "port %d already affiliated.\n", 5392 port_num + 1); 5393 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 5394 return false; 5395 } 5396 5397 ibdev->port[port_num].mp.mpi = mpi; 5398 mpi->ibdev = ibdev; 5399 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 5400 5401 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev); 5402 if (err) 5403 goto unbind; 5404 5405 err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev)); 5406 if (err) 5407 goto unbind; 5408 5409 err = mlx5_add_netdev_notifier(ibdev, port_num); 5410 if (err) { 5411 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n", 5412 port_num + 1); 5413 goto unbind; 5414 } 5415 5416 err = mlx5_ib_init_cong_debugfs(ibdev, port_num); 5417 if (err) 5418 goto unbind; 5419 5420 return true; 5421 5422 unbind: 5423 mlx5_ib_unbind_slave_port(ibdev, mpi); 5424 return false; 5425 } 5426 5427 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev) 5428 { 5429 int port_num = mlx5_core_native_port_num(dev->mdev) - 1; 5430 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 5431 port_num + 1); 5432 struct mlx5_ib_multiport_info *mpi; 5433 int err; 5434 int i; 5435 5436 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 5437 return 0; 5438 5439 err = mlx5_query_nic_vport_system_image_guid(dev->mdev, 5440 &dev->sys_image_guid); 5441 if (err) 5442 return err; 5443 5444 err = mlx5_nic_vport_enable_roce(dev->mdev); 5445 if (err) 5446 return err; 5447 5448 mutex_lock(&mlx5_ib_multiport_mutex); 5449 for (i = 0; i < dev->num_ports; i++) { 5450 bool bound = false; 5451 5452 /* build a stub multiport info struct for the native port. */ 5453 if (i == port_num) { 5454 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 5455 if (!mpi) { 5456 mutex_unlock(&mlx5_ib_multiport_mutex); 5457 mlx5_nic_vport_disable_roce(dev->mdev); 5458 return -ENOMEM; 5459 } 5460 5461 mpi->is_master = true; 5462 mpi->mdev = dev->mdev; 5463 mpi->sys_image_guid = dev->sys_image_guid; 5464 dev->port[i].mp.mpi = mpi; 5465 mpi->ibdev = dev; 5466 mpi = NULL; 5467 continue; 5468 } 5469 5470 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list, 5471 list) { 5472 if (dev->sys_image_guid == mpi->sys_image_guid && 5473 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) { 5474 bound = mlx5_ib_bind_slave_port(dev, mpi); 5475 } 5476 5477 if (bound) { 5478 dev_dbg(&mpi->mdev->pdev->dev, "removing port from unaffiliated list.\n"); 5479 mlx5_ib_dbg(dev, "port %d bound\n", i + 1); 5480 list_del(&mpi->list); 5481 break; 5482 } 5483 } 5484 if (!bound) { 5485 get_port_caps(dev, i + 1); 5486 mlx5_ib_dbg(dev, "no free port found for port %d\n", 5487 i + 1); 5488 } 5489 } 5490 5491 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list); 5492 mutex_unlock(&mlx5_ib_multiport_mutex); 5493 return err; 5494 } 5495 5496 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev) 5497 { 5498 int port_num = mlx5_core_native_port_num(dev->mdev) - 1; 5499 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 5500 port_num + 1); 5501 int i; 5502 5503 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 5504 return; 5505 5506 mutex_lock(&mlx5_ib_multiport_mutex); 5507 for (i = 0; i < dev->num_ports; i++) { 5508 if (dev->port[i].mp.mpi) { 5509 /* Destroy the native port stub */ 5510 if (i == port_num) { 5511 kfree(dev->port[i].mp.mpi); 5512 dev->port[i].mp.mpi = NULL; 5513 } else { 5514 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1); 5515 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi); 5516 } 5517 } 5518 } 5519 5520 mlx5_ib_dbg(dev, "removing from devlist\n"); 5521 list_del(&dev->ib_dev_list); 5522 mutex_unlock(&mlx5_ib_multiport_mutex); 5523 5524 mlx5_nic_vport_disable_roce(dev->mdev); 5525 } 5526 5527 ADD_UVERBS_ATTRIBUTES_SIMPLE( 5528 mlx5_ib_dm, 5529 UVERBS_OBJECT_DM, 5530 UVERBS_METHOD_DM_ALLOC, 5531 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET, 5532 UVERBS_ATTR_TYPE(u64), 5533 UA_MANDATORY), 5534 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX, 5535 UVERBS_ATTR_TYPE(u16), 5536 UA_MANDATORY)); 5537 5538 ADD_UVERBS_ATTRIBUTES_SIMPLE( 5539 mlx5_ib_flow_action, 5540 UVERBS_OBJECT_FLOW_ACTION, 5541 UVERBS_METHOD_FLOW_ACTION_ESP_CREATE, 5542 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS, 5543 enum mlx5_ib_uapi_flow_action_flags)); 5544 5545 static int populate_specs_root(struct mlx5_ib_dev *dev) 5546 { 5547 const struct uverbs_object_tree_def **trees = dev->driver_trees; 5548 size_t num_trees = 0; 5549 5550 if (mlx5_accel_ipsec_device_caps(dev->mdev) & 5551 MLX5_ACCEL_IPSEC_CAP_DEVICE) 5552 trees[num_trees++] = &mlx5_ib_flow_action; 5553 5554 if (MLX5_CAP_DEV_MEM(dev->mdev, memic)) 5555 trees[num_trees++] = &mlx5_ib_dm; 5556 5557 if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 5558 MLX5_GENERAL_OBJ_TYPES_CAP_UCTX) 5559 trees[num_trees++] = mlx5_ib_get_devx_tree(); 5560 5561 num_trees += mlx5_ib_get_flow_trees(trees + num_trees); 5562 5563 WARN_ON(num_trees >= ARRAY_SIZE(dev->driver_trees)); 5564 trees[num_trees] = NULL; 5565 dev->ib_dev.driver_specs = trees; 5566 5567 return 0; 5568 } 5569 5570 static int mlx5_ib_read_counters(struct ib_counters *counters, 5571 struct ib_counters_read_attr *read_attr, 5572 struct uverbs_attr_bundle *attrs) 5573 { 5574 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters); 5575 struct mlx5_read_counters_attr mread_attr = {}; 5576 struct mlx5_ib_flow_counters_desc *desc; 5577 int ret, i; 5578 5579 mutex_lock(&mcounters->mcntrs_mutex); 5580 if (mcounters->cntrs_max_index > read_attr->ncounters) { 5581 ret = -EINVAL; 5582 goto err_bound; 5583 } 5584 5585 mread_attr.out = kcalloc(mcounters->counters_num, sizeof(u64), 5586 GFP_KERNEL); 5587 if (!mread_attr.out) { 5588 ret = -ENOMEM; 5589 goto err_bound; 5590 } 5591 5592 mread_attr.hw_cntrs_hndl = mcounters->hw_cntrs_hndl; 5593 mread_attr.flags = read_attr->flags; 5594 ret = mcounters->read_counters(counters->device, &mread_attr); 5595 if (ret) 5596 goto err_read; 5597 5598 /* do the pass over the counters data array to assign according to the 5599 * descriptions and indexing pairs 5600 */ 5601 desc = mcounters->counters_data; 5602 for (i = 0; i < mcounters->ncounters; i++) 5603 read_attr->counters_buff[desc[i].index] += mread_attr.out[desc[i].description]; 5604 5605 err_read: 5606 kfree(mread_attr.out); 5607 err_bound: 5608 mutex_unlock(&mcounters->mcntrs_mutex); 5609 return ret; 5610 } 5611 5612 static int mlx5_ib_destroy_counters(struct ib_counters *counters) 5613 { 5614 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters); 5615 5616 counters_clear_description(counters); 5617 if (mcounters->hw_cntrs_hndl) 5618 mlx5_fc_destroy(to_mdev(counters->device)->mdev, 5619 mcounters->hw_cntrs_hndl); 5620 5621 kfree(mcounters); 5622 5623 return 0; 5624 } 5625 5626 static struct ib_counters *mlx5_ib_create_counters(struct ib_device *device, 5627 struct uverbs_attr_bundle *attrs) 5628 { 5629 struct mlx5_ib_mcounters *mcounters; 5630 5631 mcounters = kzalloc(sizeof(*mcounters), GFP_KERNEL); 5632 if (!mcounters) 5633 return ERR_PTR(-ENOMEM); 5634 5635 mutex_init(&mcounters->mcntrs_mutex); 5636 5637 return &mcounters->ibcntrs; 5638 } 5639 5640 void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev) 5641 { 5642 mlx5_ib_cleanup_multiport_master(dev); 5643 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 5644 cleanup_srcu_struct(&dev->mr_srcu); 5645 #endif 5646 kfree(dev->port); 5647 } 5648 5649 int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev) 5650 { 5651 struct mlx5_core_dev *mdev = dev->mdev; 5652 const char *name; 5653 int err; 5654 int i; 5655 5656 dev->port = kcalloc(dev->num_ports, sizeof(*dev->port), 5657 GFP_KERNEL); 5658 if (!dev->port) 5659 return -ENOMEM; 5660 5661 for (i = 0; i < dev->num_ports; i++) { 5662 spin_lock_init(&dev->port[i].mp.mpi_lock); 5663 rwlock_init(&dev->roce[i].netdev_lock); 5664 } 5665 5666 err = mlx5_ib_init_multiport_master(dev); 5667 if (err) 5668 goto err_free_port; 5669 5670 if (!mlx5_core_mp_enabled(mdev)) { 5671 for (i = 1; i <= dev->num_ports; i++) { 5672 err = get_port_caps(dev, i); 5673 if (err) 5674 break; 5675 } 5676 } else { 5677 err = get_port_caps(dev, mlx5_core_native_port_num(mdev)); 5678 } 5679 if (err) 5680 goto err_mp; 5681 5682 if (mlx5_use_mad_ifc(dev)) 5683 get_ext_port_caps(dev); 5684 5685 if (!mlx5_lag_is_active(mdev)) 5686 name = "mlx5_%d"; 5687 else 5688 name = "mlx5_bond_%d"; 5689 5690 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX); 5691 dev->ib_dev.owner = THIS_MODULE; 5692 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 5693 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 5694 dev->ib_dev.phys_port_cnt = dev->num_ports; 5695 dev->ib_dev.num_comp_vectors = 5696 dev->mdev->priv.eq_table.num_comp_vectors; 5697 dev->ib_dev.dev.parent = &mdev->pdev->dev; 5698 5699 mutex_init(&dev->cap_mask_mutex); 5700 INIT_LIST_HEAD(&dev->qp_list); 5701 spin_lock_init(&dev->reset_flow_resource_lock); 5702 5703 spin_lock_init(&dev->memic.memic_lock); 5704 dev->memic.dev = mdev; 5705 5706 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 5707 err = init_srcu_struct(&dev->mr_srcu); 5708 if (err) 5709 goto err_free_port; 5710 #endif 5711 5712 return 0; 5713 err_mp: 5714 mlx5_ib_cleanup_multiport_master(dev); 5715 5716 err_free_port: 5717 kfree(dev->port); 5718 5719 return -ENOMEM; 5720 } 5721 5722 static int mlx5_ib_stage_flow_db_init(struct mlx5_ib_dev *dev) 5723 { 5724 dev->flow_db = kzalloc(sizeof(*dev->flow_db), GFP_KERNEL); 5725 5726 if (!dev->flow_db) 5727 return -ENOMEM; 5728 5729 mutex_init(&dev->flow_db->lock); 5730 5731 return 0; 5732 } 5733 5734 int mlx5_ib_stage_rep_flow_db_init(struct mlx5_ib_dev *dev) 5735 { 5736 struct mlx5_ib_dev *nic_dev; 5737 5738 nic_dev = mlx5_ib_get_uplink_ibdev(dev->mdev->priv.eswitch); 5739 5740 if (!nic_dev) 5741 return -EINVAL; 5742 5743 dev->flow_db = nic_dev->flow_db; 5744 5745 return 0; 5746 } 5747 5748 static void mlx5_ib_stage_flow_db_cleanup(struct mlx5_ib_dev *dev) 5749 { 5750 kfree(dev->flow_db); 5751 } 5752 5753 int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev) 5754 { 5755 struct mlx5_core_dev *mdev = dev->mdev; 5756 int err; 5757 5758 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION; 5759 dev->ib_dev.uverbs_cmd_mask = 5760 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | 5761 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | 5762 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | 5763 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | 5764 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | 5765 (1ull << IB_USER_VERBS_CMD_CREATE_AH) | 5766 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) | 5767 (1ull << IB_USER_VERBS_CMD_REG_MR) | 5768 (1ull << IB_USER_VERBS_CMD_REREG_MR) | 5769 (1ull << IB_USER_VERBS_CMD_DEREG_MR) | 5770 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 5771 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | 5772 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) | 5773 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | 5774 (1ull << IB_USER_VERBS_CMD_CREATE_QP) | 5775 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | 5776 (1ull << IB_USER_VERBS_CMD_QUERY_QP) | 5777 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | 5778 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) | 5779 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) | 5780 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | 5781 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | 5782 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | 5783 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | 5784 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) | 5785 (1ull << IB_USER_VERBS_CMD_OPEN_QP); 5786 dev->ib_dev.uverbs_ex_cmd_mask = 5787 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) | 5788 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) | 5789 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) | 5790 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP) | 5791 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ); 5792 5793 dev->ib_dev.query_device = mlx5_ib_query_device; 5794 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer; 5795 dev->ib_dev.query_gid = mlx5_ib_query_gid; 5796 dev->ib_dev.add_gid = mlx5_ib_add_gid; 5797 dev->ib_dev.del_gid = mlx5_ib_del_gid; 5798 dev->ib_dev.query_pkey = mlx5_ib_query_pkey; 5799 dev->ib_dev.modify_device = mlx5_ib_modify_device; 5800 dev->ib_dev.modify_port = mlx5_ib_modify_port; 5801 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext; 5802 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext; 5803 dev->ib_dev.mmap = mlx5_ib_mmap; 5804 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd; 5805 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd; 5806 dev->ib_dev.create_ah = mlx5_ib_create_ah; 5807 dev->ib_dev.query_ah = mlx5_ib_query_ah; 5808 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah; 5809 dev->ib_dev.create_srq = mlx5_ib_create_srq; 5810 dev->ib_dev.modify_srq = mlx5_ib_modify_srq; 5811 dev->ib_dev.query_srq = mlx5_ib_query_srq; 5812 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq; 5813 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv; 5814 dev->ib_dev.create_qp = mlx5_ib_create_qp; 5815 dev->ib_dev.modify_qp = mlx5_ib_modify_qp; 5816 dev->ib_dev.query_qp = mlx5_ib_query_qp; 5817 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp; 5818 dev->ib_dev.drain_sq = mlx5_ib_drain_sq; 5819 dev->ib_dev.drain_rq = mlx5_ib_drain_rq; 5820 dev->ib_dev.post_send = mlx5_ib_post_send; 5821 dev->ib_dev.post_recv = mlx5_ib_post_recv; 5822 dev->ib_dev.create_cq = mlx5_ib_create_cq; 5823 dev->ib_dev.modify_cq = mlx5_ib_modify_cq; 5824 dev->ib_dev.resize_cq = mlx5_ib_resize_cq; 5825 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq; 5826 dev->ib_dev.poll_cq = mlx5_ib_poll_cq; 5827 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq; 5828 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr; 5829 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr; 5830 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr; 5831 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr; 5832 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach; 5833 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach; 5834 dev->ib_dev.process_mad = mlx5_ib_process_mad; 5835 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr; 5836 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg; 5837 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status; 5838 dev->ib_dev.get_dev_fw_str = get_dev_fw_str; 5839 dev->ib_dev.get_vector_affinity = mlx5_ib_get_vector_affinity; 5840 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads)) 5841 dev->ib_dev.alloc_rdma_netdev = mlx5_ib_alloc_rdma_netdev; 5842 5843 if (mlx5_core_is_pf(mdev)) { 5844 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config; 5845 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state; 5846 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats; 5847 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid; 5848 } 5849 5850 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext; 5851 5852 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence)); 5853 5854 if (MLX5_CAP_GEN(mdev, imaicl)) { 5855 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw; 5856 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw; 5857 dev->ib_dev.uverbs_cmd_mask |= 5858 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) | 5859 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW); 5860 } 5861 5862 if (MLX5_CAP_GEN(mdev, xrc)) { 5863 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd; 5864 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd; 5865 dev->ib_dev.uverbs_cmd_mask |= 5866 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) | 5867 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD); 5868 } 5869 5870 if (MLX5_CAP_DEV_MEM(mdev, memic)) { 5871 dev->ib_dev.alloc_dm = mlx5_ib_alloc_dm; 5872 dev->ib_dev.dealloc_dm = mlx5_ib_dealloc_dm; 5873 dev->ib_dev.reg_dm_mr = mlx5_ib_reg_dm_mr; 5874 } 5875 5876 dev->ib_dev.create_flow = mlx5_ib_create_flow; 5877 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow; 5878 dev->ib_dev.uverbs_ex_cmd_mask |= 5879 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) | 5880 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW); 5881 dev->ib_dev.create_flow_action_esp = mlx5_ib_create_flow_action_esp; 5882 dev->ib_dev.destroy_flow_action = mlx5_ib_destroy_flow_action; 5883 dev->ib_dev.modify_flow_action_esp = mlx5_ib_modify_flow_action_esp; 5884 dev->ib_dev.driver_id = RDMA_DRIVER_MLX5; 5885 dev->ib_dev.create_counters = mlx5_ib_create_counters; 5886 dev->ib_dev.destroy_counters = mlx5_ib_destroy_counters; 5887 dev->ib_dev.read_counters = mlx5_ib_read_counters; 5888 5889 err = init_node_data(dev); 5890 if (err) 5891 return err; 5892 5893 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && 5894 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) || 5895 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 5896 mutex_init(&dev->lb.mutex); 5897 5898 return 0; 5899 } 5900 5901 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev) 5902 { 5903 dev->ib_dev.get_port_immutable = mlx5_port_immutable; 5904 dev->ib_dev.query_port = mlx5_ib_query_port; 5905 5906 return 0; 5907 } 5908 5909 int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev) 5910 { 5911 dev->ib_dev.get_port_immutable = mlx5_port_rep_immutable; 5912 dev->ib_dev.query_port = mlx5_ib_rep_query_port; 5913 5914 return 0; 5915 } 5916 5917 static int mlx5_ib_stage_common_roce_init(struct mlx5_ib_dev *dev) 5918 { 5919 u8 port_num; 5920 int i; 5921 5922 for (i = 0; i < dev->num_ports; i++) { 5923 dev->roce[i].dev = dev; 5924 dev->roce[i].native_port_num = i + 1; 5925 dev->roce[i].last_port_state = IB_PORT_DOWN; 5926 } 5927 5928 dev->ib_dev.get_netdev = mlx5_ib_get_netdev; 5929 dev->ib_dev.create_wq = mlx5_ib_create_wq; 5930 dev->ib_dev.modify_wq = mlx5_ib_modify_wq; 5931 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq; 5932 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table; 5933 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table; 5934 5935 dev->ib_dev.uverbs_ex_cmd_mask |= 5936 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) | 5937 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) | 5938 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) | 5939 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) | 5940 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL); 5941 5942 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 5943 5944 return mlx5_add_netdev_notifier(dev, port_num); 5945 } 5946 5947 static void mlx5_ib_stage_common_roce_cleanup(struct mlx5_ib_dev *dev) 5948 { 5949 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 5950 5951 mlx5_remove_netdev_notifier(dev, port_num); 5952 } 5953 5954 int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev) 5955 { 5956 struct mlx5_core_dev *mdev = dev->mdev; 5957 enum rdma_link_layer ll; 5958 int port_type_cap; 5959 int err = 0; 5960 5961 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 5962 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 5963 5964 if (ll == IB_LINK_LAYER_ETHERNET) 5965 err = mlx5_ib_stage_common_roce_init(dev); 5966 5967 return err; 5968 } 5969 5970 void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev) 5971 { 5972 mlx5_ib_stage_common_roce_cleanup(dev); 5973 } 5974 5975 static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev) 5976 { 5977 struct mlx5_core_dev *mdev = dev->mdev; 5978 enum rdma_link_layer ll; 5979 int port_type_cap; 5980 int err; 5981 5982 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 5983 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 5984 5985 if (ll == IB_LINK_LAYER_ETHERNET) { 5986 err = mlx5_ib_stage_common_roce_init(dev); 5987 if (err) 5988 return err; 5989 5990 err = mlx5_enable_eth(dev); 5991 if (err) 5992 goto cleanup; 5993 } 5994 5995 return 0; 5996 cleanup: 5997 mlx5_ib_stage_common_roce_cleanup(dev); 5998 5999 return err; 6000 } 6001 6002 static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev) 6003 { 6004 struct mlx5_core_dev *mdev = dev->mdev; 6005 enum rdma_link_layer ll; 6006 int port_type_cap; 6007 6008 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 6009 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 6010 6011 if (ll == IB_LINK_LAYER_ETHERNET) { 6012 mlx5_disable_eth(dev); 6013 mlx5_ib_stage_common_roce_cleanup(dev); 6014 } 6015 } 6016 6017 int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev) 6018 { 6019 return create_dev_resources(&dev->devr); 6020 } 6021 6022 void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev) 6023 { 6024 destroy_dev_resources(&dev->devr); 6025 } 6026 6027 static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev) 6028 { 6029 mlx5_ib_internal_fill_odp_caps(dev); 6030 6031 return mlx5_ib_odp_init_one(dev); 6032 } 6033 6034 int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev) 6035 { 6036 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) { 6037 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats; 6038 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats; 6039 6040 return mlx5_ib_alloc_counters(dev); 6041 } 6042 6043 return 0; 6044 } 6045 6046 void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev) 6047 { 6048 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) 6049 mlx5_ib_dealloc_counters(dev); 6050 } 6051 6052 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev) 6053 { 6054 return mlx5_ib_init_cong_debugfs(dev, 6055 mlx5_core_native_port_num(dev->mdev) - 1); 6056 } 6057 6058 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev) 6059 { 6060 mlx5_ib_cleanup_cong_debugfs(dev, 6061 mlx5_core_native_port_num(dev->mdev) - 1); 6062 } 6063 6064 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev) 6065 { 6066 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev); 6067 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar); 6068 } 6069 6070 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev) 6071 { 6072 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar); 6073 } 6074 6075 int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev) 6076 { 6077 int err; 6078 6079 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false); 6080 if (err) 6081 return err; 6082 6083 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true); 6084 if (err) 6085 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 6086 6087 return err; 6088 } 6089 6090 void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev) 6091 { 6092 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 6093 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 6094 } 6095 6096 static int mlx5_ib_stage_populate_specs(struct mlx5_ib_dev *dev) 6097 { 6098 return populate_specs_root(dev); 6099 } 6100 6101 int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev) 6102 { 6103 return ib_register_device(&dev->ib_dev, NULL); 6104 } 6105 6106 void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev) 6107 { 6108 destroy_umrc_res(dev); 6109 } 6110 6111 void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev) 6112 { 6113 ib_unregister_device(&dev->ib_dev); 6114 } 6115 6116 int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev) 6117 { 6118 return create_umr_res(dev); 6119 } 6120 6121 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev) 6122 { 6123 init_delay_drop(dev); 6124 6125 return 0; 6126 } 6127 6128 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev) 6129 { 6130 cancel_delay_drop(dev); 6131 } 6132 6133 int mlx5_ib_stage_class_attr_init(struct mlx5_ib_dev *dev) 6134 { 6135 int err; 6136 int i; 6137 6138 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) { 6139 err = device_create_file(&dev->ib_dev.dev, 6140 mlx5_class_attributes[i]); 6141 if (err) 6142 return err; 6143 } 6144 6145 return 0; 6146 } 6147 6148 static int mlx5_ib_stage_rep_reg_init(struct mlx5_ib_dev *dev) 6149 { 6150 mlx5_ib_register_vport_reps(dev); 6151 6152 return 0; 6153 } 6154 6155 static void mlx5_ib_stage_rep_reg_cleanup(struct mlx5_ib_dev *dev) 6156 { 6157 mlx5_ib_unregister_vport_reps(dev); 6158 } 6159 6160 void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 6161 const struct mlx5_ib_profile *profile, 6162 int stage) 6163 { 6164 /* Number of stages to cleanup */ 6165 while (stage) { 6166 stage--; 6167 if (profile->stage[stage].cleanup) 6168 profile->stage[stage].cleanup(dev); 6169 } 6170 6171 ib_dealloc_device((struct ib_device *)dev); 6172 } 6173 6174 void *__mlx5_ib_add(struct mlx5_ib_dev *dev, 6175 const struct mlx5_ib_profile *profile) 6176 { 6177 int err; 6178 int i; 6179 6180 printk_once(KERN_INFO "%s", mlx5_version); 6181 6182 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) { 6183 if (profile->stage[i].init) { 6184 err = profile->stage[i].init(dev); 6185 if (err) 6186 goto err_out; 6187 } 6188 } 6189 6190 dev->profile = profile; 6191 dev->ib_active = true; 6192 6193 return dev; 6194 6195 err_out: 6196 __mlx5_ib_remove(dev, profile, i); 6197 6198 return NULL; 6199 } 6200 6201 static const struct mlx5_ib_profile pf_profile = { 6202 STAGE_CREATE(MLX5_IB_STAGE_INIT, 6203 mlx5_ib_stage_init_init, 6204 mlx5_ib_stage_init_cleanup), 6205 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB, 6206 mlx5_ib_stage_flow_db_init, 6207 mlx5_ib_stage_flow_db_cleanup), 6208 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 6209 mlx5_ib_stage_caps_init, 6210 NULL), 6211 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 6212 mlx5_ib_stage_non_default_cb, 6213 NULL), 6214 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 6215 mlx5_ib_stage_roce_init, 6216 mlx5_ib_stage_roce_cleanup), 6217 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 6218 mlx5_ib_stage_dev_res_init, 6219 mlx5_ib_stage_dev_res_cleanup), 6220 STAGE_CREATE(MLX5_IB_STAGE_ODP, 6221 mlx5_ib_stage_odp_init, 6222 NULL), 6223 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 6224 mlx5_ib_stage_counters_init, 6225 mlx5_ib_stage_counters_cleanup), 6226 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 6227 mlx5_ib_stage_cong_debugfs_init, 6228 mlx5_ib_stage_cong_debugfs_cleanup), 6229 STAGE_CREATE(MLX5_IB_STAGE_UAR, 6230 mlx5_ib_stage_uar_init, 6231 mlx5_ib_stage_uar_cleanup), 6232 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 6233 mlx5_ib_stage_bfrag_init, 6234 mlx5_ib_stage_bfrag_cleanup), 6235 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 6236 NULL, 6237 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 6238 STAGE_CREATE(MLX5_IB_STAGE_SPECS, 6239 mlx5_ib_stage_populate_specs, 6240 NULL), 6241 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 6242 mlx5_ib_stage_ib_reg_init, 6243 mlx5_ib_stage_ib_reg_cleanup), 6244 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 6245 mlx5_ib_stage_post_ib_reg_umr_init, 6246 NULL), 6247 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP, 6248 mlx5_ib_stage_delay_drop_init, 6249 mlx5_ib_stage_delay_drop_cleanup), 6250 STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR, 6251 mlx5_ib_stage_class_attr_init, 6252 NULL), 6253 }; 6254 6255 static const struct mlx5_ib_profile nic_rep_profile = { 6256 STAGE_CREATE(MLX5_IB_STAGE_INIT, 6257 mlx5_ib_stage_init_init, 6258 mlx5_ib_stage_init_cleanup), 6259 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB, 6260 mlx5_ib_stage_flow_db_init, 6261 mlx5_ib_stage_flow_db_cleanup), 6262 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 6263 mlx5_ib_stage_caps_init, 6264 NULL), 6265 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 6266 mlx5_ib_stage_rep_non_default_cb, 6267 NULL), 6268 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 6269 mlx5_ib_stage_rep_roce_init, 6270 mlx5_ib_stage_rep_roce_cleanup), 6271 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 6272 mlx5_ib_stage_dev_res_init, 6273 mlx5_ib_stage_dev_res_cleanup), 6274 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 6275 mlx5_ib_stage_counters_init, 6276 mlx5_ib_stage_counters_cleanup), 6277 STAGE_CREATE(MLX5_IB_STAGE_UAR, 6278 mlx5_ib_stage_uar_init, 6279 mlx5_ib_stage_uar_cleanup), 6280 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 6281 mlx5_ib_stage_bfrag_init, 6282 mlx5_ib_stage_bfrag_cleanup), 6283 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 6284 NULL, 6285 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 6286 STAGE_CREATE(MLX5_IB_STAGE_SPECS, 6287 mlx5_ib_stage_populate_specs, 6288 NULL), 6289 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 6290 mlx5_ib_stage_ib_reg_init, 6291 mlx5_ib_stage_ib_reg_cleanup), 6292 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 6293 mlx5_ib_stage_post_ib_reg_umr_init, 6294 NULL), 6295 STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR, 6296 mlx5_ib_stage_class_attr_init, 6297 NULL), 6298 STAGE_CREATE(MLX5_IB_STAGE_REP_REG, 6299 mlx5_ib_stage_rep_reg_init, 6300 mlx5_ib_stage_rep_reg_cleanup), 6301 }; 6302 6303 static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev) 6304 { 6305 struct mlx5_ib_multiport_info *mpi; 6306 struct mlx5_ib_dev *dev; 6307 bool bound = false; 6308 int err; 6309 6310 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 6311 if (!mpi) 6312 return NULL; 6313 6314 mpi->mdev = mdev; 6315 6316 err = mlx5_query_nic_vport_system_image_guid(mdev, 6317 &mpi->sys_image_guid); 6318 if (err) { 6319 kfree(mpi); 6320 return NULL; 6321 } 6322 6323 mutex_lock(&mlx5_ib_multiport_mutex); 6324 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) { 6325 if (dev->sys_image_guid == mpi->sys_image_guid) 6326 bound = mlx5_ib_bind_slave_port(dev, mpi); 6327 6328 if (bound) { 6329 rdma_roce_rescan_device(&dev->ib_dev); 6330 break; 6331 } 6332 } 6333 6334 if (!bound) { 6335 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 6336 dev_dbg(&mdev->pdev->dev, "no suitable IB device found to bind to, added to unaffiliated list.\n"); 6337 } 6338 mutex_unlock(&mlx5_ib_multiport_mutex); 6339 6340 return mpi; 6341 } 6342 6343 static void *mlx5_ib_add(struct mlx5_core_dev *mdev) 6344 { 6345 enum rdma_link_layer ll; 6346 struct mlx5_ib_dev *dev; 6347 int port_type_cap; 6348 6349 printk_once(KERN_INFO "%s", mlx5_version); 6350 6351 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 6352 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 6353 6354 if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET) 6355 return mlx5_ib_add_slave_port(mdev); 6356 6357 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev)); 6358 if (!dev) 6359 return NULL; 6360 6361 dev->mdev = mdev; 6362 dev->num_ports = max(MLX5_CAP_GEN(mdev, num_ports), 6363 MLX5_CAP_GEN(mdev, num_vhca_ports)); 6364 6365 if (MLX5_ESWITCH_MANAGER(mdev) && 6366 mlx5_ib_eswitch_mode(mdev->priv.eswitch) == SRIOV_OFFLOADS) { 6367 dev->rep = mlx5_ib_vport_rep(mdev->priv.eswitch, 0); 6368 6369 return __mlx5_ib_add(dev, &nic_rep_profile); 6370 } 6371 6372 return __mlx5_ib_add(dev, &pf_profile); 6373 } 6374 6375 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context) 6376 { 6377 struct mlx5_ib_multiport_info *mpi; 6378 struct mlx5_ib_dev *dev; 6379 6380 if (mlx5_core_is_mp_slave(mdev)) { 6381 mpi = context; 6382 mutex_lock(&mlx5_ib_multiport_mutex); 6383 if (mpi->ibdev) 6384 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi); 6385 list_del(&mpi->list); 6386 mutex_unlock(&mlx5_ib_multiport_mutex); 6387 return; 6388 } 6389 6390 dev = context; 6391 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX); 6392 } 6393 6394 static struct mlx5_interface mlx5_ib_interface = { 6395 .add = mlx5_ib_add, 6396 .remove = mlx5_ib_remove, 6397 .event = mlx5_ib_event, 6398 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 6399 .pfault = mlx5_ib_pfault, 6400 #endif 6401 .protocol = MLX5_INTERFACE_PROTOCOL_IB, 6402 }; 6403 6404 unsigned long mlx5_ib_get_xlt_emergency_page(void) 6405 { 6406 mutex_lock(&xlt_emergency_page_mutex); 6407 return xlt_emergency_page; 6408 } 6409 6410 void mlx5_ib_put_xlt_emergency_page(void) 6411 { 6412 mutex_unlock(&xlt_emergency_page_mutex); 6413 } 6414 6415 static int __init mlx5_ib_init(void) 6416 { 6417 int err; 6418 6419 xlt_emergency_page = __get_free_page(GFP_KERNEL); 6420 if (!xlt_emergency_page) 6421 return -ENOMEM; 6422 6423 mutex_init(&xlt_emergency_page_mutex); 6424 6425 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0); 6426 if (!mlx5_ib_event_wq) { 6427 free_page(xlt_emergency_page); 6428 return -ENOMEM; 6429 } 6430 6431 mlx5_ib_odp_init(); 6432 6433 err = mlx5_register_interface(&mlx5_ib_interface); 6434 6435 return err; 6436 } 6437 6438 static void __exit mlx5_ib_cleanup(void) 6439 { 6440 mlx5_unregister_interface(&mlx5_ib_interface); 6441 destroy_workqueue(mlx5_ib_event_wq); 6442 mutex_destroy(&xlt_emergency_page_mutex); 6443 free_page(xlt_emergency_page); 6444 } 6445 6446 module_init(mlx5_ib_init); 6447 module_exit(mlx5_ib_cleanup); 6448