1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/debugfs.h> 34 #include <linux/highmem.h> 35 #include <linux/module.h> 36 #include <linux/init.h> 37 #include <linux/errno.h> 38 #include <linux/pci.h> 39 #include <linux/dma-mapping.h> 40 #include <linux/slab.h> 41 #if defined(CONFIG_X86) 42 #include <asm/pat.h> 43 #endif 44 #include <linux/sched.h> 45 #include <linux/sched/mm.h> 46 #include <linux/sched/task.h> 47 #include <linux/delay.h> 48 #include <rdma/ib_user_verbs.h> 49 #include <rdma/ib_addr.h> 50 #include <rdma/ib_cache.h> 51 #include <linux/mlx5/port.h> 52 #include <linux/mlx5/vport.h> 53 #include <linux/list.h> 54 #include <rdma/ib_smi.h> 55 #include <rdma/ib_umem.h> 56 #include <linux/in.h> 57 #include <linux/etherdevice.h> 58 #include <linux/mlx5/fs.h> 59 #include <linux/mlx5/vport.h> 60 #include "mlx5_ib.h" 61 #include "cmd.h" 62 #include <linux/mlx5/vport.h> 63 64 #define DRIVER_NAME "mlx5_ib" 65 #define DRIVER_VERSION "5.0-0" 66 67 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 68 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver"); 69 MODULE_LICENSE("Dual BSD/GPL"); 70 71 static char mlx5_version[] = 72 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v" 73 DRIVER_VERSION "\n"; 74 75 enum { 76 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 77 }; 78 79 static enum rdma_link_layer 80 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 81 { 82 switch (port_type_cap) { 83 case MLX5_CAP_PORT_TYPE_IB: 84 return IB_LINK_LAYER_INFINIBAND; 85 case MLX5_CAP_PORT_TYPE_ETH: 86 return IB_LINK_LAYER_ETHERNET; 87 default: 88 return IB_LINK_LAYER_UNSPECIFIED; 89 } 90 } 91 92 static enum rdma_link_layer 93 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num) 94 { 95 struct mlx5_ib_dev *dev = to_mdev(device); 96 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 97 98 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 99 } 100 101 static int get_port_state(struct ib_device *ibdev, 102 u8 port_num, 103 enum ib_port_state *state) 104 { 105 struct ib_port_attr attr; 106 int ret; 107 108 memset(&attr, 0, sizeof(attr)); 109 ret = mlx5_ib_query_port(ibdev, port_num, &attr); 110 if (!ret) 111 *state = attr.state; 112 return ret; 113 } 114 115 static int mlx5_netdev_event(struct notifier_block *this, 116 unsigned long event, void *ptr) 117 { 118 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 119 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev, 120 roce.nb); 121 122 switch (event) { 123 case NETDEV_REGISTER: 124 case NETDEV_UNREGISTER: 125 write_lock(&ibdev->roce.netdev_lock); 126 if (ndev->dev.parent == &ibdev->mdev->pdev->dev) 127 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ? 128 NULL : ndev; 129 write_unlock(&ibdev->roce.netdev_lock); 130 break; 131 132 case NETDEV_CHANGE: 133 case NETDEV_UP: 134 case NETDEV_DOWN: { 135 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(ibdev->mdev); 136 struct net_device *upper = NULL; 137 138 if (lag_ndev) { 139 upper = netdev_master_upper_dev_get(lag_ndev); 140 dev_put(lag_ndev); 141 } 142 143 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev)) 144 && ibdev->ib_active) { 145 struct ib_event ibev = { }; 146 enum ib_port_state port_state; 147 148 if (get_port_state(&ibdev->ib_dev, 1, &port_state)) 149 return NOTIFY_DONE; 150 151 if (ibdev->roce.last_port_state == port_state) 152 return NOTIFY_DONE; 153 154 ibdev->roce.last_port_state = port_state; 155 ibev.device = &ibdev->ib_dev; 156 if (port_state == IB_PORT_DOWN) 157 ibev.event = IB_EVENT_PORT_ERR; 158 else if (port_state == IB_PORT_ACTIVE) 159 ibev.event = IB_EVENT_PORT_ACTIVE; 160 else 161 return NOTIFY_DONE; 162 163 ibev.element.port_num = 1; 164 ib_dispatch_event(&ibev); 165 } 166 break; 167 } 168 169 default: 170 break; 171 } 172 173 return NOTIFY_DONE; 174 } 175 176 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device, 177 u8 port_num) 178 { 179 struct mlx5_ib_dev *ibdev = to_mdev(device); 180 struct net_device *ndev; 181 182 ndev = mlx5_lag_get_roce_netdev(ibdev->mdev); 183 if (ndev) 184 return ndev; 185 186 /* Ensure ndev does not disappear before we invoke dev_hold() 187 */ 188 read_lock(&ibdev->roce.netdev_lock); 189 ndev = ibdev->roce.netdev; 190 if (ndev) 191 dev_hold(ndev); 192 read_unlock(&ibdev->roce.netdev_lock); 193 194 return ndev; 195 } 196 197 static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed, 198 u8 *active_width) 199 { 200 switch (eth_proto_oper) { 201 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII): 202 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX): 203 case MLX5E_PROT_MASK(MLX5E_100BASE_TX): 204 case MLX5E_PROT_MASK(MLX5E_1000BASE_T): 205 *active_width = IB_WIDTH_1X; 206 *active_speed = IB_SPEED_SDR; 207 break; 208 case MLX5E_PROT_MASK(MLX5E_10GBASE_T): 209 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4): 210 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4): 211 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR): 212 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR): 213 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR): 214 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER): 215 *active_width = IB_WIDTH_1X; 216 *active_speed = IB_SPEED_QDR; 217 break; 218 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR): 219 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR): 220 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR): 221 *active_width = IB_WIDTH_1X; 222 *active_speed = IB_SPEED_EDR; 223 break; 224 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4): 225 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4): 226 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4): 227 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4): 228 *active_width = IB_WIDTH_4X; 229 *active_speed = IB_SPEED_QDR; 230 break; 231 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2): 232 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2): 233 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2): 234 *active_width = IB_WIDTH_1X; 235 *active_speed = IB_SPEED_HDR; 236 break; 237 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4): 238 *active_width = IB_WIDTH_4X; 239 *active_speed = IB_SPEED_FDR; 240 break; 241 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4): 242 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4): 243 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4): 244 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4): 245 *active_width = IB_WIDTH_4X; 246 *active_speed = IB_SPEED_EDR; 247 break; 248 default: 249 return -EINVAL; 250 } 251 252 return 0; 253 } 254 255 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num, 256 struct ib_port_attr *props) 257 { 258 struct mlx5_ib_dev *dev = to_mdev(device); 259 struct mlx5_core_dev *mdev = dev->mdev; 260 struct net_device *ndev, *upper; 261 enum ib_mtu ndev_ib_mtu; 262 u16 qkey_viol_cntr; 263 u32 eth_prot_oper; 264 int err; 265 266 /* Possible bad flows are checked before filling out props so in case 267 * of an error it will still be zeroed out. 268 */ 269 err = mlx5_query_port_eth_proto_oper(mdev, ð_prot_oper, port_num); 270 if (err) 271 return err; 272 273 translate_eth_proto_oper(eth_prot_oper, &props->active_speed, 274 &props->active_width); 275 276 props->port_cap_flags |= IB_PORT_CM_SUP; 277 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS; 278 279 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 280 roce_address_table_size); 281 props->max_mtu = IB_MTU_4096; 282 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 283 props->pkey_tbl_len = 1; 284 props->state = IB_PORT_DOWN; 285 props->phys_state = 3; 286 287 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr); 288 props->qkey_viol_cntr = qkey_viol_cntr; 289 290 ndev = mlx5_ib_get_netdev(device, port_num); 291 if (!ndev) 292 return 0; 293 294 if (mlx5_lag_is_active(dev->mdev)) { 295 rcu_read_lock(); 296 upper = netdev_master_upper_dev_get_rcu(ndev); 297 if (upper) { 298 dev_put(ndev); 299 ndev = upper; 300 dev_hold(ndev); 301 } 302 rcu_read_unlock(); 303 } 304 305 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 306 props->state = IB_PORT_ACTIVE; 307 props->phys_state = 5; 308 } 309 310 ndev_ib_mtu = iboe_get_mtu(ndev->mtu); 311 312 dev_put(ndev); 313 314 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 315 return 0; 316 } 317 318 static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num, 319 unsigned int index, const union ib_gid *gid, 320 const struct ib_gid_attr *attr) 321 { 322 enum ib_gid_type gid_type = IB_GID_TYPE_IB; 323 u8 roce_version = 0; 324 u8 roce_l3_type = 0; 325 bool vlan = false; 326 u8 mac[ETH_ALEN]; 327 u16 vlan_id = 0; 328 329 if (gid) { 330 gid_type = attr->gid_type; 331 ether_addr_copy(mac, attr->ndev->dev_addr); 332 333 if (is_vlan_dev(attr->ndev)) { 334 vlan = true; 335 vlan_id = vlan_dev_vlan_id(attr->ndev); 336 } 337 } 338 339 switch (gid_type) { 340 case IB_GID_TYPE_IB: 341 roce_version = MLX5_ROCE_VERSION_1; 342 break; 343 case IB_GID_TYPE_ROCE_UDP_ENCAP: 344 roce_version = MLX5_ROCE_VERSION_2; 345 if (ipv6_addr_v4mapped((void *)gid)) 346 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4; 347 else 348 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6; 349 break; 350 351 default: 352 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type); 353 } 354 355 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version, 356 roce_l3_type, gid->raw, mac, vlan, 357 vlan_id); 358 } 359 360 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num, 361 unsigned int index, const union ib_gid *gid, 362 const struct ib_gid_attr *attr, 363 __always_unused void **context) 364 { 365 return set_roce_addr(to_mdev(device), port_num, index, gid, attr); 366 } 367 368 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num, 369 unsigned int index, __always_unused void **context) 370 { 371 return set_roce_addr(to_mdev(device), port_num, index, NULL, NULL); 372 } 373 374 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num, 375 int index) 376 { 377 struct ib_gid_attr attr; 378 union ib_gid gid; 379 380 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr)) 381 return 0; 382 383 if (!attr.ndev) 384 return 0; 385 386 dev_put(attr.ndev); 387 388 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 389 return 0; 390 391 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 392 } 393 394 int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num, 395 int index, enum ib_gid_type *gid_type) 396 { 397 struct ib_gid_attr attr; 398 union ib_gid gid; 399 int ret; 400 401 ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr); 402 if (ret) 403 return ret; 404 405 if (!attr.ndev) 406 return -ENODEV; 407 408 dev_put(attr.ndev); 409 410 *gid_type = attr.gid_type; 411 412 return 0; 413 } 414 415 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 416 { 417 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 418 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 419 return 0; 420 } 421 422 enum { 423 MLX5_VPORT_ACCESS_METHOD_MAD, 424 MLX5_VPORT_ACCESS_METHOD_HCA, 425 MLX5_VPORT_ACCESS_METHOD_NIC, 426 }; 427 428 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 429 { 430 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 431 return MLX5_VPORT_ACCESS_METHOD_MAD; 432 433 if (mlx5_ib_port_link_layer(ibdev, 1) == 434 IB_LINK_LAYER_ETHERNET) 435 return MLX5_VPORT_ACCESS_METHOD_NIC; 436 437 return MLX5_VPORT_ACCESS_METHOD_HCA; 438 } 439 440 static void get_atomic_caps(struct mlx5_ib_dev *dev, 441 struct ib_device_attr *props) 442 { 443 u8 tmp; 444 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 445 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 446 u8 atomic_req_8B_endianness_mode = 447 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode); 448 449 /* Check if HW supports 8 bytes standard atomic operations and capable 450 * of host endianness respond 451 */ 452 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 453 if (((atomic_operations & tmp) == tmp) && 454 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 455 (atomic_req_8B_endianness_mode)) { 456 props->atomic_cap = IB_ATOMIC_HCA; 457 } else { 458 props->atomic_cap = IB_ATOMIC_NONE; 459 } 460 } 461 462 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 463 __be64 *sys_image_guid) 464 { 465 struct mlx5_ib_dev *dev = to_mdev(ibdev); 466 struct mlx5_core_dev *mdev = dev->mdev; 467 u64 tmp; 468 int err; 469 470 switch (mlx5_get_vport_access_method(ibdev)) { 471 case MLX5_VPORT_ACCESS_METHOD_MAD: 472 return mlx5_query_mad_ifc_system_image_guid(ibdev, 473 sys_image_guid); 474 475 case MLX5_VPORT_ACCESS_METHOD_HCA: 476 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 477 break; 478 479 case MLX5_VPORT_ACCESS_METHOD_NIC: 480 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 481 break; 482 483 default: 484 return -EINVAL; 485 } 486 487 if (!err) 488 *sys_image_guid = cpu_to_be64(tmp); 489 490 return err; 491 492 } 493 494 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 495 u16 *max_pkeys) 496 { 497 struct mlx5_ib_dev *dev = to_mdev(ibdev); 498 struct mlx5_core_dev *mdev = dev->mdev; 499 500 switch (mlx5_get_vport_access_method(ibdev)) { 501 case MLX5_VPORT_ACCESS_METHOD_MAD: 502 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 503 504 case MLX5_VPORT_ACCESS_METHOD_HCA: 505 case MLX5_VPORT_ACCESS_METHOD_NIC: 506 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 507 pkey_table_size)); 508 return 0; 509 510 default: 511 return -EINVAL; 512 } 513 } 514 515 static int mlx5_query_vendor_id(struct ib_device *ibdev, 516 u32 *vendor_id) 517 { 518 struct mlx5_ib_dev *dev = to_mdev(ibdev); 519 520 switch (mlx5_get_vport_access_method(ibdev)) { 521 case MLX5_VPORT_ACCESS_METHOD_MAD: 522 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 523 524 case MLX5_VPORT_ACCESS_METHOD_HCA: 525 case MLX5_VPORT_ACCESS_METHOD_NIC: 526 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 527 528 default: 529 return -EINVAL; 530 } 531 } 532 533 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 534 __be64 *node_guid) 535 { 536 u64 tmp; 537 int err; 538 539 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 540 case MLX5_VPORT_ACCESS_METHOD_MAD: 541 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 542 543 case MLX5_VPORT_ACCESS_METHOD_HCA: 544 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 545 break; 546 547 case MLX5_VPORT_ACCESS_METHOD_NIC: 548 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 549 break; 550 551 default: 552 return -EINVAL; 553 } 554 555 if (!err) 556 *node_guid = cpu_to_be64(tmp); 557 558 return err; 559 } 560 561 struct mlx5_reg_node_desc { 562 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 563 }; 564 565 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 566 { 567 struct mlx5_reg_node_desc in; 568 569 if (mlx5_use_mad_ifc(dev)) 570 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 571 572 memset(&in, 0, sizeof(in)); 573 574 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 575 sizeof(struct mlx5_reg_node_desc), 576 MLX5_REG_NODE_DESC, 0, 0); 577 } 578 579 static int mlx5_ib_query_device(struct ib_device *ibdev, 580 struct ib_device_attr *props, 581 struct ib_udata *uhw) 582 { 583 struct mlx5_ib_dev *dev = to_mdev(ibdev); 584 struct mlx5_core_dev *mdev = dev->mdev; 585 int err = -ENOMEM; 586 int max_sq_desc; 587 int max_rq_sg; 588 int max_sq_sg; 589 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 590 struct mlx5_ib_query_device_resp resp = {}; 591 size_t resp_len; 592 u64 max_tso; 593 594 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 595 if (uhw->outlen && uhw->outlen < resp_len) 596 return -EINVAL; 597 else 598 resp.response_length = resp_len; 599 600 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) 601 return -EINVAL; 602 603 memset(props, 0, sizeof(*props)); 604 err = mlx5_query_system_image_guid(ibdev, 605 &props->sys_image_guid); 606 if (err) 607 return err; 608 609 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys); 610 if (err) 611 return err; 612 613 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 614 if (err) 615 return err; 616 617 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 618 (fw_rev_min(dev->mdev) << 16) | 619 fw_rev_sub(dev->mdev); 620 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 621 IB_DEVICE_PORT_ACTIVE_EVENT | 622 IB_DEVICE_SYS_IMAGE_GUID | 623 IB_DEVICE_RC_RNR_NAK_GEN; 624 625 if (MLX5_CAP_GEN(mdev, pkv)) 626 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 627 if (MLX5_CAP_GEN(mdev, qkv)) 628 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 629 if (MLX5_CAP_GEN(mdev, apm)) 630 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 631 if (MLX5_CAP_GEN(mdev, xrc)) 632 props->device_cap_flags |= IB_DEVICE_XRC; 633 if (MLX5_CAP_GEN(mdev, imaicl)) { 634 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 635 IB_DEVICE_MEM_WINDOW_TYPE_2B; 636 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 637 /* We support 'Gappy' memory registration too */ 638 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG; 639 } 640 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 641 if (MLX5_CAP_GEN(mdev, sho)) { 642 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER; 643 /* At this stage no support for signature handover */ 644 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 645 IB_PROT_T10DIF_TYPE_2 | 646 IB_PROT_T10DIF_TYPE_3; 647 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 648 IB_GUARD_T10DIF_CSUM; 649 } 650 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 651 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 652 653 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) { 654 if (MLX5_CAP_ETH(mdev, csum_cap)) { 655 /* Legacy bit to support old userspace libraries */ 656 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 657 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM; 658 } 659 660 if (MLX5_CAP_ETH(dev->mdev, vlan_cap)) 661 props->raw_packet_caps |= 662 IB_RAW_PACKET_CAP_CVLAN_STRIPPING; 663 664 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) { 665 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 666 if (max_tso) { 667 resp.tso_caps.max_tso = 1 << max_tso; 668 resp.tso_caps.supported_qpts |= 669 1 << IB_QPT_RAW_PACKET; 670 resp.response_length += sizeof(resp.tso_caps); 671 } 672 } 673 674 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) { 675 resp.rss_caps.rx_hash_function = 676 MLX5_RX_HASH_FUNC_TOEPLITZ; 677 resp.rss_caps.rx_hash_fields_mask = 678 MLX5_RX_HASH_SRC_IPV4 | 679 MLX5_RX_HASH_DST_IPV4 | 680 MLX5_RX_HASH_SRC_IPV6 | 681 MLX5_RX_HASH_DST_IPV6 | 682 MLX5_RX_HASH_SRC_PORT_TCP | 683 MLX5_RX_HASH_DST_PORT_TCP | 684 MLX5_RX_HASH_SRC_PORT_UDP | 685 MLX5_RX_HASH_DST_PORT_UDP; 686 resp.response_length += sizeof(resp.rss_caps); 687 } 688 } else { 689 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) 690 resp.response_length += sizeof(resp.tso_caps); 691 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) 692 resp.response_length += sizeof(resp.rss_caps); 693 } 694 695 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 696 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 697 props->device_cap_flags |= IB_DEVICE_UD_TSO; 698 } 699 700 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) && 701 MLX5_CAP_GEN(dev->mdev, general_notification_event)) 702 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP; 703 704 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 705 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap)) 706 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 707 708 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 709 MLX5_CAP_ETH(dev->mdev, scatter_fcs)) { 710 /* Legacy bit to support old userspace libraries */ 711 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 712 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; 713 } 714 715 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 716 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 717 718 props->vendor_part_id = mdev->pdev->device; 719 props->hw_ver = mdev->pdev->revision; 720 721 props->max_mr_size = ~0ull; 722 props->page_size_cap = ~(min_page_size - 1); 723 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 724 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 725 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 726 sizeof(struct mlx5_wqe_data_seg); 727 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512); 728 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) - 729 sizeof(struct mlx5_wqe_raddr_seg)) / 730 sizeof(struct mlx5_wqe_data_seg); 731 props->max_sge = min(max_rq_sg, max_sq_sg); 732 props->max_sge_rd = MLX5_MAX_SGE_RD; 733 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 734 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 735 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 736 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 737 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 738 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 739 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 740 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 741 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 742 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 743 props->max_srq_sge = max_rq_sg - 1; 744 props->max_fast_reg_page_list_len = 745 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 746 get_atomic_caps(dev, props); 747 props->masked_atomic_cap = IB_ATOMIC_NONE; 748 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 749 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 750 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 751 props->max_mcast_grp; 752 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */ 753 props->max_ah = INT_MAX; 754 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 755 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 756 757 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 758 if (MLX5_CAP_GEN(mdev, pg)) 759 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING; 760 props->odp_caps = dev->odp_caps; 761 #endif 762 763 if (MLX5_CAP_GEN(mdev, cd)) 764 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL; 765 766 if (!mlx5_core_is_pf(mdev)) 767 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION; 768 769 if (mlx5_ib_port_link_layer(ibdev, 1) == 770 IB_LINK_LAYER_ETHERNET) { 771 props->rss_caps.max_rwq_indirection_tables = 772 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 773 props->rss_caps.max_rwq_indirection_table_size = 774 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 775 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 776 props->max_wq_type_rq = 777 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 778 } 779 780 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) { 781 resp.cqe_comp_caps.max_num = 782 MLX5_CAP_GEN(dev->mdev, cqe_compression) ? 783 MLX5_CAP_GEN(dev->mdev, cqe_compression_max_num) : 0; 784 resp.cqe_comp_caps.supported_format = 785 MLX5_IB_CQE_RES_FORMAT_HASH | 786 MLX5_IB_CQE_RES_FORMAT_CSUM; 787 resp.response_length += sizeof(resp.cqe_comp_caps); 788 } 789 790 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen)) { 791 if (MLX5_CAP_QOS(mdev, packet_pacing) && 792 MLX5_CAP_GEN(mdev, qos)) { 793 resp.packet_pacing_caps.qp_rate_limit_max = 794 MLX5_CAP_QOS(mdev, packet_pacing_max_rate); 795 resp.packet_pacing_caps.qp_rate_limit_min = 796 MLX5_CAP_QOS(mdev, packet_pacing_min_rate); 797 resp.packet_pacing_caps.supported_qpts |= 798 1 << IB_QPT_RAW_PACKET; 799 } 800 resp.response_length += sizeof(resp.packet_pacing_caps); 801 } 802 803 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes, 804 uhw->outlen)) { 805 resp.mlx5_ib_support_multi_pkt_send_wqes = 806 MLX5_CAP_ETH(mdev, multi_pkt_send_wqe); 807 resp.response_length += 808 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes); 809 } 810 811 if (field_avail(typeof(resp), reserved, uhw->outlen)) 812 resp.response_length += sizeof(resp.reserved); 813 814 if (field_avail(typeof(resp), sw_parsing_caps, 815 uhw->outlen)) { 816 resp.response_length += sizeof(resp.sw_parsing_caps); 817 if (MLX5_CAP_ETH(mdev, swp)) { 818 resp.sw_parsing_caps.sw_parsing_offloads |= 819 MLX5_IB_SW_PARSING; 820 821 if (MLX5_CAP_ETH(mdev, swp_csum)) 822 resp.sw_parsing_caps.sw_parsing_offloads |= 823 MLX5_IB_SW_PARSING_CSUM; 824 825 if (MLX5_CAP_ETH(mdev, swp_lso)) 826 resp.sw_parsing_caps.sw_parsing_offloads |= 827 MLX5_IB_SW_PARSING_LSO; 828 829 if (resp.sw_parsing_caps.sw_parsing_offloads) 830 resp.sw_parsing_caps.supported_qpts = 831 BIT(IB_QPT_RAW_PACKET); 832 } 833 } 834 835 if (uhw->outlen) { 836 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 837 838 if (err) 839 return err; 840 } 841 842 return 0; 843 } 844 845 enum mlx5_ib_width { 846 MLX5_IB_WIDTH_1X = 1 << 0, 847 MLX5_IB_WIDTH_2X = 1 << 1, 848 MLX5_IB_WIDTH_4X = 1 << 2, 849 MLX5_IB_WIDTH_8X = 1 << 3, 850 MLX5_IB_WIDTH_12X = 1 << 4 851 }; 852 853 static int translate_active_width(struct ib_device *ibdev, u8 active_width, 854 u8 *ib_width) 855 { 856 struct mlx5_ib_dev *dev = to_mdev(ibdev); 857 int err = 0; 858 859 if (active_width & MLX5_IB_WIDTH_1X) { 860 *ib_width = IB_WIDTH_1X; 861 } else if (active_width & MLX5_IB_WIDTH_2X) { 862 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n", 863 (int)active_width); 864 err = -EINVAL; 865 } else if (active_width & MLX5_IB_WIDTH_4X) { 866 *ib_width = IB_WIDTH_4X; 867 } else if (active_width & MLX5_IB_WIDTH_8X) { 868 *ib_width = IB_WIDTH_8X; 869 } else if (active_width & MLX5_IB_WIDTH_12X) { 870 *ib_width = IB_WIDTH_12X; 871 } else { 872 mlx5_ib_dbg(dev, "Invalid active_width %d\n", 873 (int)active_width); 874 err = -EINVAL; 875 } 876 877 return err; 878 } 879 880 static int mlx5_mtu_to_ib_mtu(int mtu) 881 { 882 switch (mtu) { 883 case 256: return 1; 884 case 512: return 2; 885 case 1024: return 3; 886 case 2048: return 4; 887 case 4096: return 5; 888 default: 889 pr_warn("invalid mtu\n"); 890 return -1; 891 } 892 } 893 894 enum ib_max_vl_num { 895 __IB_MAX_VL_0 = 1, 896 __IB_MAX_VL_0_1 = 2, 897 __IB_MAX_VL_0_3 = 3, 898 __IB_MAX_VL_0_7 = 4, 899 __IB_MAX_VL_0_14 = 5, 900 }; 901 902 enum mlx5_vl_hw_cap { 903 MLX5_VL_HW_0 = 1, 904 MLX5_VL_HW_0_1 = 2, 905 MLX5_VL_HW_0_2 = 3, 906 MLX5_VL_HW_0_3 = 4, 907 MLX5_VL_HW_0_4 = 5, 908 MLX5_VL_HW_0_5 = 6, 909 MLX5_VL_HW_0_6 = 7, 910 MLX5_VL_HW_0_7 = 8, 911 MLX5_VL_HW_0_14 = 15 912 }; 913 914 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 915 u8 *max_vl_num) 916 { 917 switch (vl_hw_cap) { 918 case MLX5_VL_HW_0: 919 *max_vl_num = __IB_MAX_VL_0; 920 break; 921 case MLX5_VL_HW_0_1: 922 *max_vl_num = __IB_MAX_VL_0_1; 923 break; 924 case MLX5_VL_HW_0_3: 925 *max_vl_num = __IB_MAX_VL_0_3; 926 break; 927 case MLX5_VL_HW_0_7: 928 *max_vl_num = __IB_MAX_VL_0_7; 929 break; 930 case MLX5_VL_HW_0_14: 931 *max_vl_num = __IB_MAX_VL_0_14; 932 break; 933 934 default: 935 return -EINVAL; 936 } 937 938 return 0; 939 } 940 941 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port, 942 struct ib_port_attr *props) 943 { 944 struct mlx5_ib_dev *dev = to_mdev(ibdev); 945 struct mlx5_core_dev *mdev = dev->mdev; 946 struct mlx5_hca_vport_context *rep; 947 u16 max_mtu; 948 u16 oper_mtu; 949 int err; 950 u8 ib_link_width_oper; 951 u8 vl_hw_cap; 952 953 rep = kzalloc(sizeof(*rep), GFP_KERNEL); 954 if (!rep) { 955 err = -ENOMEM; 956 goto out; 957 } 958 959 /* props being zeroed by the caller, avoid zeroing it here */ 960 961 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); 962 if (err) 963 goto out; 964 965 props->lid = rep->lid; 966 props->lmc = rep->lmc; 967 props->sm_lid = rep->sm_lid; 968 props->sm_sl = rep->sm_sl; 969 props->state = rep->vport_state; 970 props->phys_state = rep->port_physical_state; 971 props->port_cap_flags = rep->cap_mask1; 972 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 973 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 974 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 975 props->bad_pkey_cntr = rep->pkey_violation_counter; 976 props->qkey_viol_cntr = rep->qkey_violation_counter; 977 props->subnet_timeout = rep->subnet_timeout; 978 props->init_type_reply = rep->init_type_reply; 979 props->grh_required = rep->grh_required; 980 981 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port); 982 if (err) 983 goto out; 984 985 err = translate_active_width(ibdev, ib_link_width_oper, 986 &props->active_width); 987 if (err) 988 goto out; 989 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port); 990 if (err) 991 goto out; 992 993 mlx5_query_port_max_mtu(mdev, &max_mtu, port); 994 995 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); 996 997 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); 998 999 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); 1000 1001 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); 1002 if (err) 1003 goto out; 1004 1005 err = translate_max_vl_num(ibdev, vl_hw_cap, 1006 &props->max_vl_num); 1007 out: 1008 kfree(rep); 1009 return err; 1010 } 1011 1012 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 1013 struct ib_port_attr *props) 1014 { 1015 unsigned int count; 1016 int ret; 1017 1018 switch (mlx5_get_vport_access_method(ibdev)) { 1019 case MLX5_VPORT_ACCESS_METHOD_MAD: 1020 ret = mlx5_query_mad_ifc_port(ibdev, port, props); 1021 break; 1022 1023 case MLX5_VPORT_ACCESS_METHOD_HCA: 1024 ret = mlx5_query_hca_port(ibdev, port, props); 1025 break; 1026 1027 case MLX5_VPORT_ACCESS_METHOD_NIC: 1028 ret = mlx5_query_port_roce(ibdev, port, props); 1029 break; 1030 1031 default: 1032 ret = -EINVAL; 1033 } 1034 1035 if (!ret && props) { 1036 count = mlx5_core_reserved_gids_count(to_mdev(ibdev)->mdev); 1037 props->gid_tbl_len -= count; 1038 } 1039 return ret; 1040 } 1041 1042 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 1043 union ib_gid *gid) 1044 { 1045 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1046 struct mlx5_core_dev *mdev = dev->mdev; 1047 1048 switch (mlx5_get_vport_access_method(ibdev)) { 1049 case MLX5_VPORT_ACCESS_METHOD_MAD: 1050 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 1051 1052 case MLX5_VPORT_ACCESS_METHOD_HCA: 1053 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); 1054 1055 default: 1056 return -EINVAL; 1057 } 1058 1059 } 1060 1061 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 1062 u16 *pkey) 1063 { 1064 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1065 struct mlx5_core_dev *mdev = dev->mdev; 1066 1067 switch (mlx5_get_vport_access_method(ibdev)) { 1068 case MLX5_VPORT_ACCESS_METHOD_MAD: 1069 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 1070 1071 case MLX5_VPORT_ACCESS_METHOD_HCA: 1072 case MLX5_VPORT_ACCESS_METHOD_NIC: 1073 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index, 1074 pkey); 1075 default: 1076 return -EINVAL; 1077 } 1078 } 1079 1080 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 1081 struct ib_device_modify *props) 1082 { 1083 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1084 struct mlx5_reg_node_desc in; 1085 struct mlx5_reg_node_desc out; 1086 int err; 1087 1088 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 1089 return -EOPNOTSUPP; 1090 1091 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 1092 return 0; 1093 1094 /* 1095 * If possible, pass node desc to FW, so it can generate 1096 * a 144 trap. If cmd fails, just ignore. 1097 */ 1098 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1099 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 1100 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 1101 if (err) 1102 return err; 1103 1104 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1105 1106 return err; 1107 } 1108 1109 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask, 1110 u32 value) 1111 { 1112 struct mlx5_hca_vport_context ctx = {}; 1113 int err; 1114 1115 err = mlx5_query_hca_vport_context(dev->mdev, 0, 1116 port_num, 0, &ctx); 1117 if (err) 1118 return err; 1119 1120 if (~ctx.cap_mask1_perm & mask) { 1121 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n", 1122 mask, ctx.cap_mask1_perm); 1123 return -EINVAL; 1124 } 1125 1126 ctx.cap_mask1 = value; 1127 ctx.cap_mask1_perm = mask; 1128 err = mlx5_core_modify_hca_vport_context(dev->mdev, 0, 1129 port_num, 0, &ctx); 1130 1131 return err; 1132 } 1133 1134 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, 1135 struct ib_port_modify *props) 1136 { 1137 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1138 struct ib_port_attr attr; 1139 u32 tmp; 1140 int err; 1141 u32 change_mask; 1142 u32 value; 1143 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) == 1144 IB_LINK_LAYER_INFINIBAND); 1145 1146 /* CM layer calls ib_modify_port() regardless of the link layer. For 1147 * Ethernet ports, qkey violation and Port capabilities are meaningless. 1148 */ 1149 if (!is_ib) 1150 return 0; 1151 1152 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) { 1153 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask; 1154 value = ~props->clr_port_cap_mask | props->set_port_cap_mask; 1155 return set_port_caps_atomic(dev, port, change_mask, value); 1156 } 1157 1158 mutex_lock(&dev->cap_mask_mutex); 1159 1160 err = ib_query_port(ibdev, port, &attr); 1161 if (err) 1162 goto out; 1163 1164 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 1165 ~props->clr_port_cap_mask; 1166 1167 err = mlx5_set_port_caps(dev->mdev, port, tmp); 1168 1169 out: 1170 mutex_unlock(&dev->cap_mask_mutex); 1171 return err; 1172 } 1173 1174 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps) 1175 { 1176 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n", 1177 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n"); 1178 } 1179 1180 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k, 1181 struct mlx5_ib_alloc_ucontext_req_v2 *req, 1182 u32 *num_sys_pages) 1183 { 1184 int uars_per_sys_page; 1185 int bfregs_per_sys_page; 1186 int ref_bfregs = req->total_num_bfregs; 1187 1188 if (req->total_num_bfregs == 0) 1189 return -EINVAL; 1190 1191 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE); 1192 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE); 1193 1194 if (req->total_num_bfregs > MLX5_MAX_BFREGS) 1195 return -ENOMEM; 1196 1197 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k); 1198 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR; 1199 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page); 1200 *num_sys_pages = req->total_num_bfregs / bfregs_per_sys_page; 1201 1202 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1) 1203 return -EINVAL; 1204 1205 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, using %d sys pages\n", 1206 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no", 1207 lib_uar_4k ? "yes" : "no", ref_bfregs, 1208 req->total_num_bfregs, *num_sys_pages); 1209 1210 return 0; 1211 } 1212 1213 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1214 { 1215 struct mlx5_bfreg_info *bfregi; 1216 int err; 1217 int i; 1218 1219 bfregi = &context->bfregi; 1220 for (i = 0; i < bfregi->num_sys_pages; i++) { 1221 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]); 1222 if (err) 1223 goto error; 1224 1225 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]); 1226 } 1227 return 0; 1228 1229 error: 1230 for (--i; i >= 0; i--) 1231 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i])) 1232 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1233 1234 return err; 1235 } 1236 1237 static int deallocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1238 { 1239 struct mlx5_bfreg_info *bfregi; 1240 int err; 1241 int i; 1242 1243 bfregi = &context->bfregi; 1244 for (i = 0; i < bfregi->num_sys_pages; i++) { 1245 err = mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]); 1246 if (err) { 1247 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1248 return err; 1249 } 1250 } 1251 return 0; 1252 } 1253 1254 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn) 1255 { 1256 int err; 1257 1258 err = mlx5_core_alloc_transport_domain(dev->mdev, tdn); 1259 if (err) 1260 return err; 1261 1262 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1263 !MLX5_CAP_GEN(dev->mdev, disable_local_lb)) 1264 return err; 1265 1266 mutex_lock(&dev->lb_mutex); 1267 dev->user_td++; 1268 1269 if (dev->user_td == 2) 1270 err = mlx5_nic_vport_update_local_lb(dev->mdev, true); 1271 1272 mutex_unlock(&dev->lb_mutex); 1273 return err; 1274 } 1275 1276 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn) 1277 { 1278 mlx5_core_dealloc_transport_domain(dev->mdev, tdn); 1279 1280 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1281 !MLX5_CAP_GEN(dev->mdev, disable_local_lb)) 1282 return; 1283 1284 mutex_lock(&dev->lb_mutex); 1285 dev->user_td--; 1286 1287 if (dev->user_td < 2) 1288 mlx5_nic_vport_update_local_lb(dev->mdev, false); 1289 1290 mutex_unlock(&dev->lb_mutex); 1291 } 1292 1293 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev, 1294 struct ib_udata *udata) 1295 { 1296 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1297 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 1298 struct mlx5_ib_alloc_ucontext_resp resp = {}; 1299 struct mlx5_ib_ucontext *context; 1300 struct mlx5_bfreg_info *bfregi; 1301 int ver; 1302 int err; 1303 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 1304 max_cqe_version); 1305 bool lib_uar_4k; 1306 1307 if (!dev->ib_active) 1308 return ERR_PTR(-EAGAIN); 1309 1310 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 1311 ver = 0; 1312 else if (udata->inlen >= min_req_v2) 1313 ver = 2; 1314 else 1315 return ERR_PTR(-EINVAL); 1316 1317 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req))); 1318 if (err) 1319 return ERR_PTR(err); 1320 1321 if (req.flags) 1322 return ERR_PTR(-EINVAL); 1323 1324 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 1325 return ERR_PTR(-EOPNOTSUPP); 1326 1327 req.total_num_bfregs = ALIGN(req.total_num_bfregs, 1328 MLX5_NON_FP_BFREGS_PER_UAR); 1329 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1) 1330 return ERR_PTR(-EINVAL); 1331 1332 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 1333 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf)) 1334 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size); 1335 resp.cache_line_size = cache_line_size(); 1336 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 1337 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 1338 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1339 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1340 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 1341 resp.cqe_version = min_t(__u8, 1342 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 1343 req.max_cqe_version); 1344 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1345 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT; 1346 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1347 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1; 1348 resp.response_length = min(offsetof(typeof(resp), response_length) + 1349 sizeof(resp.response_length), udata->outlen); 1350 1351 context = kzalloc(sizeof(*context), GFP_KERNEL); 1352 if (!context) 1353 return ERR_PTR(-ENOMEM); 1354 1355 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR; 1356 bfregi = &context->bfregi; 1357 1358 /* updates req->total_num_bfregs */ 1359 err = calc_total_bfregs(dev, lib_uar_4k, &req, &bfregi->num_sys_pages); 1360 if (err) 1361 goto out_ctx; 1362 1363 mutex_init(&bfregi->lock); 1364 bfregi->lib_uar_4k = lib_uar_4k; 1365 bfregi->count = kcalloc(req.total_num_bfregs, sizeof(*bfregi->count), 1366 GFP_KERNEL); 1367 if (!bfregi->count) { 1368 err = -ENOMEM; 1369 goto out_ctx; 1370 } 1371 1372 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages, 1373 sizeof(*bfregi->sys_pages), 1374 GFP_KERNEL); 1375 if (!bfregi->sys_pages) { 1376 err = -ENOMEM; 1377 goto out_count; 1378 } 1379 1380 err = allocate_uars(dev, context); 1381 if (err) 1382 goto out_sys_pages; 1383 1384 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1385 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range; 1386 #endif 1387 1388 context->upd_xlt_page = __get_free_page(GFP_KERNEL); 1389 if (!context->upd_xlt_page) { 1390 err = -ENOMEM; 1391 goto out_uars; 1392 } 1393 mutex_init(&context->upd_xlt_page_mutex); 1394 1395 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) { 1396 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn); 1397 if (err) 1398 goto out_page; 1399 } 1400 1401 INIT_LIST_HEAD(&context->vma_private_list); 1402 INIT_LIST_HEAD(&context->db_page_list); 1403 mutex_init(&context->db_page_mutex); 1404 1405 resp.tot_bfregs = req.total_num_bfregs; 1406 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports); 1407 1408 if (field_avail(typeof(resp), cqe_version, udata->outlen)) 1409 resp.response_length += sizeof(resp.cqe_version); 1410 1411 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) { 1412 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 1413 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 1414 resp.response_length += sizeof(resp.cmds_supp_uhw); 1415 } 1416 1417 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) { 1418 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) { 1419 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline); 1420 resp.eth_min_inline++; 1421 } 1422 resp.response_length += sizeof(resp.eth_min_inline); 1423 } 1424 1425 /* 1426 * We don't want to expose information from the PCI bar that is located 1427 * after 4096 bytes, so if the arch only supports larger pages, let's 1428 * pretend we don't support reading the HCA's core clock. This is also 1429 * forced by mmap function. 1430 */ 1431 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) { 1432 if (PAGE_SIZE <= 4096) { 1433 resp.comp_mask |= 1434 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 1435 resp.hca_core_clock_offset = 1436 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE; 1437 } 1438 resp.response_length += sizeof(resp.hca_core_clock_offset) + 1439 sizeof(resp.reserved2); 1440 } 1441 1442 if (field_avail(typeof(resp), log_uar_size, udata->outlen)) 1443 resp.response_length += sizeof(resp.log_uar_size); 1444 1445 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen)) 1446 resp.response_length += sizeof(resp.num_uars_per_page); 1447 1448 err = ib_copy_to_udata(udata, &resp, resp.response_length); 1449 if (err) 1450 goto out_td; 1451 1452 bfregi->ver = ver; 1453 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs; 1454 context->cqe_version = resp.cqe_version; 1455 context->lib_caps = req.lib_caps; 1456 print_lib_caps(dev, context->lib_caps); 1457 1458 return &context->ibucontext; 1459 1460 out_td: 1461 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1462 mlx5_ib_dealloc_transport_domain(dev, context->tdn); 1463 1464 out_page: 1465 free_page(context->upd_xlt_page); 1466 1467 out_uars: 1468 deallocate_uars(dev, context); 1469 1470 out_sys_pages: 1471 kfree(bfregi->sys_pages); 1472 1473 out_count: 1474 kfree(bfregi->count); 1475 1476 out_ctx: 1477 kfree(context); 1478 1479 return ERR_PTR(err); 1480 } 1481 1482 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1483 { 1484 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1485 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1486 struct mlx5_bfreg_info *bfregi; 1487 1488 bfregi = &context->bfregi; 1489 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1490 mlx5_ib_dealloc_transport_domain(dev, context->tdn); 1491 1492 free_page(context->upd_xlt_page); 1493 deallocate_uars(dev, context); 1494 kfree(bfregi->sys_pages); 1495 kfree(bfregi->count); 1496 kfree(context); 1497 1498 return 0; 1499 } 1500 1501 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, 1502 struct mlx5_bfreg_info *bfregi, 1503 int idx) 1504 { 1505 int fw_uars_per_page; 1506 1507 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1; 1508 1509 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + 1510 bfregi->sys_pages[idx] / fw_uars_per_page; 1511 } 1512 1513 static int get_command(unsigned long offset) 1514 { 1515 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 1516 } 1517 1518 static int get_arg(unsigned long offset) 1519 { 1520 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 1521 } 1522 1523 static int get_index(unsigned long offset) 1524 { 1525 return get_arg(offset); 1526 } 1527 1528 static void mlx5_ib_vma_open(struct vm_area_struct *area) 1529 { 1530 /* vma_open is called when a new VMA is created on top of our VMA. This 1531 * is done through either mremap flow or split_vma (usually due to 1532 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA, 1533 * as this VMA is strongly hardware related. Therefore we set the 1534 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from 1535 * calling us again and trying to do incorrect actions. We assume that 1536 * the original VMA size is exactly a single page, and therefore all 1537 * "splitting" operation will not happen to it. 1538 */ 1539 area->vm_ops = NULL; 1540 } 1541 1542 static void mlx5_ib_vma_close(struct vm_area_struct *area) 1543 { 1544 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data; 1545 1546 /* It's guaranteed that all VMAs opened on a FD are closed before the 1547 * file itself is closed, therefore no sync is needed with the regular 1548 * closing flow. (e.g. mlx5 ib_dealloc_ucontext) 1549 * However need a sync with accessing the vma as part of 1550 * mlx5_ib_disassociate_ucontext. 1551 * The close operation is usually called under mm->mmap_sem except when 1552 * process is exiting. 1553 * The exiting case is handled explicitly as part of 1554 * mlx5_ib_disassociate_ucontext. 1555 */ 1556 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data; 1557 1558 /* setting the vma context pointer to null in the mlx5_ib driver's 1559 * private data, to protect a race condition in 1560 * mlx5_ib_disassociate_ucontext(). 1561 */ 1562 mlx5_ib_vma_priv_data->vma = NULL; 1563 list_del(&mlx5_ib_vma_priv_data->list); 1564 kfree(mlx5_ib_vma_priv_data); 1565 } 1566 1567 static const struct vm_operations_struct mlx5_ib_vm_ops = { 1568 .open = mlx5_ib_vma_open, 1569 .close = mlx5_ib_vma_close 1570 }; 1571 1572 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma, 1573 struct mlx5_ib_ucontext *ctx) 1574 { 1575 struct mlx5_ib_vma_private_data *vma_prv; 1576 struct list_head *vma_head = &ctx->vma_private_list; 1577 1578 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL); 1579 if (!vma_prv) 1580 return -ENOMEM; 1581 1582 vma_prv->vma = vma; 1583 vma->vm_private_data = vma_prv; 1584 vma->vm_ops = &mlx5_ib_vm_ops; 1585 1586 list_add(&vma_prv->list, vma_head); 1587 1588 return 0; 1589 } 1590 1591 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 1592 { 1593 int ret; 1594 struct vm_area_struct *vma; 1595 struct mlx5_ib_vma_private_data *vma_private, *n; 1596 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1597 struct task_struct *owning_process = NULL; 1598 struct mm_struct *owning_mm = NULL; 1599 1600 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID); 1601 if (!owning_process) 1602 return; 1603 1604 owning_mm = get_task_mm(owning_process); 1605 if (!owning_mm) { 1606 pr_info("no mm, disassociate ucontext is pending task termination\n"); 1607 while (1) { 1608 put_task_struct(owning_process); 1609 usleep_range(1000, 2000); 1610 owning_process = get_pid_task(ibcontext->tgid, 1611 PIDTYPE_PID); 1612 if (!owning_process || 1613 owning_process->state == TASK_DEAD) { 1614 pr_info("disassociate ucontext done, task was terminated\n"); 1615 /* in case task was dead need to release the 1616 * task struct. 1617 */ 1618 if (owning_process) 1619 put_task_struct(owning_process); 1620 return; 1621 } 1622 } 1623 } 1624 1625 /* need to protect from a race on closing the vma as part of 1626 * mlx5_ib_vma_close. 1627 */ 1628 down_write(&owning_mm->mmap_sem); 1629 list_for_each_entry_safe(vma_private, n, &context->vma_private_list, 1630 list) { 1631 vma = vma_private->vma; 1632 ret = zap_vma_ptes(vma, vma->vm_start, 1633 PAGE_SIZE); 1634 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__); 1635 /* context going to be destroyed, should 1636 * not access ops any more. 1637 */ 1638 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE); 1639 vma->vm_ops = NULL; 1640 list_del(&vma_private->list); 1641 kfree(vma_private); 1642 } 1643 up_write(&owning_mm->mmap_sem); 1644 mmput(owning_mm); 1645 put_task_struct(owning_process); 1646 } 1647 1648 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 1649 { 1650 switch (cmd) { 1651 case MLX5_IB_MMAP_WC_PAGE: 1652 return "WC"; 1653 case MLX5_IB_MMAP_REGULAR_PAGE: 1654 return "best effort WC"; 1655 case MLX5_IB_MMAP_NC_PAGE: 1656 return "NC"; 1657 default: 1658 return NULL; 1659 } 1660 } 1661 1662 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 1663 struct vm_area_struct *vma, 1664 struct mlx5_ib_ucontext *context) 1665 { 1666 struct mlx5_bfreg_info *bfregi = &context->bfregi; 1667 int err; 1668 unsigned long idx; 1669 phys_addr_t pfn, pa; 1670 pgprot_t prot; 1671 int uars_per_page; 1672 1673 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1674 return -EINVAL; 1675 1676 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k); 1677 idx = get_index(vma->vm_pgoff); 1678 if (idx % uars_per_page || 1679 idx * uars_per_page >= bfregi->num_sys_pages) { 1680 mlx5_ib_warn(dev, "invalid uar index %lu\n", idx); 1681 return -EINVAL; 1682 } 1683 1684 switch (cmd) { 1685 case MLX5_IB_MMAP_WC_PAGE: 1686 /* Some architectures don't support WC memory */ 1687 #if defined(CONFIG_X86) 1688 if (!pat_enabled()) 1689 return -EPERM; 1690 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU))) 1691 return -EPERM; 1692 #endif 1693 /* fall through */ 1694 case MLX5_IB_MMAP_REGULAR_PAGE: 1695 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 1696 prot = pgprot_writecombine(vma->vm_page_prot); 1697 break; 1698 case MLX5_IB_MMAP_NC_PAGE: 1699 prot = pgprot_noncached(vma->vm_page_prot); 1700 break; 1701 default: 1702 return -EINVAL; 1703 } 1704 1705 pfn = uar_index2pfn(dev, bfregi, idx); 1706 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 1707 1708 vma->vm_page_prot = prot; 1709 err = io_remap_pfn_range(vma, vma->vm_start, pfn, 1710 PAGE_SIZE, vma->vm_page_prot); 1711 if (err) { 1712 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n", 1713 err, vma->vm_start, &pfn, mmap_cmd2str(cmd)); 1714 return -EAGAIN; 1715 } 1716 1717 pa = pfn << PAGE_SHIFT; 1718 mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd), 1719 vma->vm_start, &pa); 1720 1721 return mlx5_ib_set_vma_data(vma, context); 1722 } 1723 1724 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 1725 { 1726 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1727 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1728 unsigned long command; 1729 phys_addr_t pfn; 1730 1731 command = get_command(vma->vm_pgoff); 1732 switch (command) { 1733 case MLX5_IB_MMAP_WC_PAGE: 1734 case MLX5_IB_MMAP_NC_PAGE: 1735 case MLX5_IB_MMAP_REGULAR_PAGE: 1736 return uar_mmap(dev, command, vma, context); 1737 1738 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 1739 return -ENOSYS; 1740 1741 case MLX5_IB_MMAP_CORE_CLOCK: 1742 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1743 return -EINVAL; 1744 1745 if (vma->vm_flags & VM_WRITE) 1746 return -EPERM; 1747 1748 /* Don't expose to user-space information it shouldn't have */ 1749 if (PAGE_SIZE > 4096) 1750 return -EOPNOTSUPP; 1751 1752 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 1753 pfn = (dev->mdev->iseg_base + 1754 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 1755 PAGE_SHIFT; 1756 if (io_remap_pfn_range(vma, vma->vm_start, pfn, 1757 PAGE_SIZE, vma->vm_page_prot)) 1758 return -EAGAIN; 1759 1760 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n", 1761 vma->vm_start, 1762 (unsigned long long)pfn << PAGE_SHIFT); 1763 break; 1764 1765 default: 1766 return -EINVAL; 1767 } 1768 1769 return 0; 1770 } 1771 1772 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev, 1773 struct ib_ucontext *context, 1774 struct ib_udata *udata) 1775 { 1776 struct mlx5_ib_alloc_pd_resp resp; 1777 struct mlx5_ib_pd *pd; 1778 int err; 1779 1780 pd = kmalloc(sizeof(*pd), GFP_KERNEL); 1781 if (!pd) 1782 return ERR_PTR(-ENOMEM); 1783 1784 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn); 1785 if (err) { 1786 kfree(pd); 1787 return ERR_PTR(err); 1788 } 1789 1790 if (context) { 1791 resp.pdn = pd->pdn; 1792 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 1793 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn); 1794 kfree(pd); 1795 return ERR_PTR(-EFAULT); 1796 } 1797 } 1798 1799 return &pd->ibpd; 1800 } 1801 1802 static int mlx5_ib_dealloc_pd(struct ib_pd *pd) 1803 { 1804 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 1805 struct mlx5_ib_pd *mpd = to_mpd(pd); 1806 1807 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn); 1808 kfree(mpd); 1809 1810 return 0; 1811 } 1812 1813 enum { 1814 MATCH_CRITERIA_ENABLE_OUTER_BIT, 1815 MATCH_CRITERIA_ENABLE_MISC_BIT, 1816 MATCH_CRITERIA_ENABLE_INNER_BIT 1817 }; 1818 1819 #define HEADER_IS_ZERO(match_criteria, headers) \ 1820 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \ 1821 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \ 1822 1823 static u8 get_match_criteria_enable(u32 *match_criteria) 1824 { 1825 u8 match_criteria_enable; 1826 1827 match_criteria_enable = 1828 (!HEADER_IS_ZERO(match_criteria, outer_headers)) << 1829 MATCH_CRITERIA_ENABLE_OUTER_BIT; 1830 match_criteria_enable |= 1831 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) << 1832 MATCH_CRITERIA_ENABLE_MISC_BIT; 1833 match_criteria_enable |= 1834 (!HEADER_IS_ZERO(match_criteria, inner_headers)) << 1835 MATCH_CRITERIA_ENABLE_INNER_BIT; 1836 1837 return match_criteria_enable; 1838 } 1839 1840 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val) 1841 { 1842 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask); 1843 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val); 1844 } 1845 1846 static void set_flow_label(void *misc_c, void *misc_v, u8 mask, u8 val, 1847 bool inner) 1848 { 1849 if (inner) { 1850 MLX5_SET(fte_match_set_misc, 1851 misc_c, inner_ipv6_flow_label, mask); 1852 MLX5_SET(fte_match_set_misc, 1853 misc_v, inner_ipv6_flow_label, val); 1854 } else { 1855 MLX5_SET(fte_match_set_misc, 1856 misc_c, outer_ipv6_flow_label, mask); 1857 MLX5_SET(fte_match_set_misc, 1858 misc_v, outer_ipv6_flow_label, val); 1859 } 1860 } 1861 1862 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val) 1863 { 1864 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask); 1865 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val); 1866 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2); 1867 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2); 1868 } 1869 1870 #define LAST_ETH_FIELD vlan_tag 1871 #define LAST_IB_FIELD sl 1872 #define LAST_IPV4_FIELD tos 1873 #define LAST_IPV6_FIELD traffic_class 1874 #define LAST_TCP_UDP_FIELD src_port 1875 #define LAST_TUNNEL_FIELD tunnel_id 1876 #define LAST_FLOW_TAG_FIELD tag_id 1877 #define LAST_DROP_FIELD size 1878 1879 /* Field is the last supported field */ 1880 #define FIELDS_NOT_SUPPORTED(filter, field)\ 1881 memchr_inv((void *)&filter.field +\ 1882 sizeof(filter.field), 0,\ 1883 sizeof(filter) -\ 1884 offsetof(typeof(filter), field) -\ 1885 sizeof(filter.field)) 1886 1887 #define IPV4_VERSION 4 1888 #define IPV6_VERSION 6 1889 static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c, 1890 u32 *match_v, const union ib_flow_spec *ib_spec, 1891 u32 *tag_id, bool *is_drop) 1892 { 1893 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c, 1894 misc_parameters); 1895 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v, 1896 misc_parameters); 1897 void *headers_c; 1898 void *headers_v; 1899 int match_ipv; 1900 1901 if (ib_spec->type & IB_FLOW_SPEC_INNER) { 1902 headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 1903 inner_headers); 1904 headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 1905 inner_headers); 1906 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 1907 ft_field_support.inner_ip_version); 1908 } else { 1909 headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 1910 outer_headers); 1911 headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 1912 outer_headers); 1913 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 1914 ft_field_support.outer_ip_version); 1915 } 1916 1917 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) { 1918 case IB_FLOW_SPEC_ETH: 1919 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD)) 1920 return -EOPNOTSUPP; 1921 1922 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 1923 dmac_47_16), 1924 ib_spec->eth.mask.dst_mac); 1925 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1926 dmac_47_16), 1927 ib_spec->eth.val.dst_mac); 1928 1929 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 1930 smac_47_16), 1931 ib_spec->eth.mask.src_mac); 1932 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1933 smac_47_16), 1934 ib_spec->eth.val.src_mac); 1935 1936 if (ib_spec->eth.mask.vlan_tag) { 1937 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1938 cvlan_tag, 1); 1939 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1940 cvlan_tag, 1); 1941 1942 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1943 first_vid, ntohs(ib_spec->eth.mask.vlan_tag)); 1944 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1945 first_vid, ntohs(ib_spec->eth.val.vlan_tag)); 1946 1947 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1948 first_cfi, 1949 ntohs(ib_spec->eth.mask.vlan_tag) >> 12); 1950 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1951 first_cfi, 1952 ntohs(ib_spec->eth.val.vlan_tag) >> 12); 1953 1954 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1955 first_prio, 1956 ntohs(ib_spec->eth.mask.vlan_tag) >> 13); 1957 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1958 first_prio, 1959 ntohs(ib_spec->eth.val.vlan_tag) >> 13); 1960 } 1961 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1962 ethertype, ntohs(ib_spec->eth.mask.ether_type)); 1963 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1964 ethertype, ntohs(ib_spec->eth.val.ether_type)); 1965 break; 1966 case IB_FLOW_SPEC_IPV4: 1967 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD)) 1968 return -EOPNOTSUPP; 1969 1970 if (match_ipv) { 1971 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1972 ip_version, 0xf); 1973 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1974 ip_version, IPV4_VERSION); 1975 } else { 1976 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1977 ethertype, 0xffff); 1978 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1979 ethertype, ETH_P_IP); 1980 } 1981 1982 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 1983 src_ipv4_src_ipv6.ipv4_layout.ipv4), 1984 &ib_spec->ipv4.mask.src_ip, 1985 sizeof(ib_spec->ipv4.mask.src_ip)); 1986 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1987 src_ipv4_src_ipv6.ipv4_layout.ipv4), 1988 &ib_spec->ipv4.val.src_ip, 1989 sizeof(ib_spec->ipv4.val.src_ip)); 1990 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 1991 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 1992 &ib_spec->ipv4.mask.dst_ip, 1993 sizeof(ib_spec->ipv4.mask.dst_ip)); 1994 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1995 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 1996 &ib_spec->ipv4.val.dst_ip, 1997 sizeof(ib_spec->ipv4.val.dst_ip)); 1998 1999 set_tos(headers_c, headers_v, 2000 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos); 2001 2002 set_proto(headers_c, headers_v, 2003 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto); 2004 break; 2005 case IB_FLOW_SPEC_IPV6: 2006 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD)) 2007 return -EOPNOTSUPP; 2008 2009 if (match_ipv) { 2010 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2011 ip_version, 0xf); 2012 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2013 ip_version, IPV6_VERSION); 2014 } else { 2015 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2016 ethertype, 0xffff); 2017 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2018 ethertype, ETH_P_IPV6); 2019 } 2020 2021 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2022 src_ipv4_src_ipv6.ipv6_layout.ipv6), 2023 &ib_spec->ipv6.mask.src_ip, 2024 sizeof(ib_spec->ipv6.mask.src_ip)); 2025 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2026 src_ipv4_src_ipv6.ipv6_layout.ipv6), 2027 &ib_spec->ipv6.val.src_ip, 2028 sizeof(ib_spec->ipv6.val.src_ip)); 2029 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2030 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 2031 &ib_spec->ipv6.mask.dst_ip, 2032 sizeof(ib_spec->ipv6.mask.dst_ip)); 2033 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2034 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 2035 &ib_spec->ipv6.val.dst_ip, 2036 sizeof(ib_spec->ipv6.val.dst_ip)); 2037 2038 set_tos(headers_c, headers_v, 2039 ib_spec->ipv6.mask.traffic_class, 2040 ib_spec->ipv6.val.traffic_class); 2041 2042 set_proto(headers_c, headers_v, 2043 ib_spec->ipv6.mask.next_hdr, 2044 ib_spec->ipv6.val.next_hdr); 2045 2046 set_flow_label(misc_params_c, misc_params_v, 2047 ntohl(ib_spec->ipv6.mask.flow_label), 2048 ntohl(ib_spec->ipv6.val.flow_label), 2049 ib_spec->type & IB_FLOW_SPEC_INNER); 2050 2051 break; 2052 case IB_FLOW_SPEC_TCP: 2053 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 2054 LAST_TCP_UDP_FIELD)) 2055 return -EOPNOTSUPP; 2056 2057 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol, 2058 0xff); 2059 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, 2060 IPPROTO_TCP); 2061 2062 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport, 2063 ntohs(ib_spec->tcp_udp.mask.src_port)); 2064 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport, 2065 ntohs(ib_spec->tcp_udp.val.src_port)); 2066 2067 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport, 2068 ntohs(ib_spec->tcp_udp.mask.dst_port)); 2069 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport, 2070 ntohs(ib_spec->tcp_udp.val.dst_port)); 2071 break; 2072 case IB_FLOW_SPEC_UDP: 2073 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 2074 LAST_TCP_UDP_FIELD)) 2075 return -EOPNOTSUPP; 2076 2077 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol, 2078 0xff); 2079 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, 2080 IPPROTO_UDP); 2081 2082 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport, 2083 ntohs(ib_spec->tcp_udp.mask.src_port)); 2084 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport, 2085 ntohs(ib_spec->tcp_udp.val.src_port)); 2086 2087 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport, 2088 ntohs(ib_spec->tcp_udp.mask.dst_port)); 2089 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, 2090 ntohs(ib_spec->tcp_udp.val.dst_port)); 2091 break; 2092 case IB_FLOW_SPEC_VXLAN_TUNNEL: 2093 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask, 2094 LAST_TUNNEL_FIELD)) 2095 return -EOPNOTSUPP; 2096 2097 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni, 2098 ntohl(ib_spec->tunnel.mask.tunnel_id)); 2099 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni, 2100 ntohl(ib_spec->tunnel.val.tunnel_id)); 2101 break; 2102 case IB_FLOW_SPEC_ACTION_TAG: 2103 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag, 2104 LAST_FLOW_TAG_FIELD)) 2105 return -EOPNOTSUPP; 2106 if (ib_spec->flow_tag.tag_id >= BIT(24)) 2107 return -EINVAL; 2108 2109 *tag_id = ib_spec->flow_tag.tag_id; 2110 break; 2111 case IB_FLOW_SPEC_ACTION_DROP: 2112 if (FIELDS_NOT_SUPPORTED(ib_spec->drop, 2113 LAST_DROP_FIELD)) 2114 return -EOPNOTSUPP; 2115 *is_drop = true; 2116 break; 2117 default: 2118 return -EINVAL; 2119 } 2120 2121 return 0; 2122 } 2123 2124 /* If a flow could catch both multicast and unicast packets, 2125 * it won't fall into the multicast flow steering table and this rule 2126 * could steal other multicast packets. 2127 */ 2128 static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr) 2129 { 2130 union ib_flow_spec *flow_spec; 2131 2132 if (ib_attr->type != IB_FLOW_ATTR_NORMAL || 2133 ib_attr->num_of_specs < 1) 2134 return false; 2135 2136 flow_spec = (union ib_flow_spec *)(ib_attr + 1); 2137 if (flow_spec->type == IB_FLOW_SPEC_IPV4) { 2138 struct ib_flow_spec_ipv4 *ipv4_spec; 2139 2140 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec; 2141 if (ipv4_is_multicast(ipv4_spec->val.dst_ip)) 2142 return true; 2143 2144 return false; 2145 } 2146 2147 if (flow_spec->type == IB_FLOW_SPEC_ETH) { 2148 struct ib_flow_spec_eth *eth_spec; 2149 2150 eth_spec = (struct ib_flow_spec_eth *)flow_spec; 2151 return is_multicast_ether_addr(eth_spec->mask.dst_mac) && 2152 is_multicast_ether_addr(eth_spec->val.dst_mac); 2153 } 2154 2155 return false; 2156 } 2157 2158 static bool is_valid_ethertype(struct mlx5_core_dev *mdev, 2159 const struct ib_flow_attr *flow_attr, 2160 bool check_inner) 2161 { 2162 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1); 2163 int match_ipv = check_inner ? 2164 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2165 ft_field_support.inner_ip_version) : 2166 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2167 ft_field_support.outer_ip_version); 2168 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0; 2169 bool ipv4_spec_valid, ipv6_spec_valid; 2170 unsigned int ip_spec_type = 0; 2171 bool has_ethertype = false; 2172 unsigned int spec_index; 2173 bool mask_valid = true; 2174 u16 eth_type = 0; 2175 bool type_valid; 2176 2177 /* Validate that ethertype is correct */ 2178 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 2179 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) && 2180 ib_spec->eth.mask.ether_type) { 2181 mask_valid = (ib_spec->eth.mask.ether_type == 2182 htons(0xffff)); 2183 has_ethertype = true; 2184 eth_type = ntohs(ib_spec->eth.val.ether_type); 2185 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) || 2186 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) { 2187 ip_spec_type = ib_spec->type; 2188 } 2189 ib_spec = (void *)ib_spec + ib_spec->size; 2190 } 2191 2192 type_valid = (!has_ethertype) || (!ip_spec_type); 2193 if (!type_valid && mask_valid) { 2194 ipv4_spec_valid = (eth_type == ETH_P_IP) && 2195 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit)); 2196 ipv6_spec_valid = (eth_type == ETH_P_IPV6) && 2197 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit)); 2198 2199 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) || 2200 (((eth_type == ETH_P_MPLS_UC) || 2201 (eth_type == ETH_P_MPLS_MC)) && match_ipv); 2202 } 2203 2204 return type_valid; 2205 } 2206 2207 static bool is_valid_attr(struct mlx5_core_dev *mdev, 2208 const struct ib_flow_attr *flow_attr) 2209 { 2210 return is_valid_ethertype(mdev, flow_attr, false) && 2211 is_valid_ethertype(mdev, flow_attr, true); 2212 } 2213 2214 static void put_flow_table(struct mlx5_ib_dev *dev, 2215 struct mlx5_ib_flow_prio *prio, bool ft_added) 2216 { 2217 prio->refcount -= !!ft_added; 2218 if (!prio->refcount) { 2219 mlx5_destroy_flow_table(prio->flow_table); 2220 prio->flow_table = NULL; 2221 } 2222 } 2223 2224 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id) 2225 { 2226 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device); 2227 struct mlx5_ib_flow_handler *handler = container_of(flow_id, 2228 struct mlx5_ib_flow_handler, 2229 ibflow); 2230 struct mlx5_ib_flow_handler *iter, *tmp; 2231 2232 mutex_lock(&dev->flow_db.lock); 2233 2234 list_for_each_entry_safe(iter, tmp, &handler->list, list) { 2235 mlx5_del_flow_rules(iter->rule); 2236 put_flow_table(dev, iter->prio, true); 2237 list_del(&iter->list); 2238 kfree(iter); 2239 } 2240 2241 mlx5_del_flow_rules(handler->rule); 2242 put_flow_table(dev, handler->prio, true); 2243 mutex_unlock(&dev->flow_db.lock); 2244 2245 kfree(handler); 2246 2247 return 0; 2248 } 2249 2250 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap) 2251 { 2252 priority *= 2; 2253 if (!dont_trap) 2254 priority++; 2255 return priority; 2256 } 2257 2258 enum flow_table_type { 2259 MLX5_IB_FT_RX, 2260 MLX5_IB_FT_TX 2261 }; 2262 2263 #define MLX5_FS_MAX_TYPES 6 2264 #define MLX5_FS_MAX_ENTRIES BIT(16) 2265 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev, 2266 struct ib_flow_attr *flow_attr, 2267 enum flow_table_type ft_type) 2268 { 2269 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP; 2270 struct mlx5_flow_namespace *ns = NULL; 2271 struct mlx5_ib_flow_prio *prio; 2272 struct mlx5_flow_table *ft; 2273 int max_table_size; 2274 int num_entries; 2275 int num_groups; 2276 int priority; 2277 int err = 0; 2278 2279 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 2280 log_max_ft_size)); 2281 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 2282 if (flow_is_multicast_only(flow_attr) && 2283 !dont_trap) 2284 priority = MLX5_IB_FLOW_MCAST_PRIO; 2285 else 2286 priority = ib_prio_to_core_prio(flow_attr->priority, 2287 dont_trap); 2288 ns = mlx5_get_flow_namespace(dev->mdev, 2289 MLX5_FLOW_NAMESPACE_BYPASS); 2290 num_entries = MLX5_FS_MAX_ENTRIES; 2291 num_groups = MLX5_FS_MAX_TYPES; 2292 prio = &dev->flow_db.prios[priority]; 2293 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 2294 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 2295 ns = mlx5_get_flow_namespace(dev->mdev, 2296 MLX5_FLOW_NAMESPACE_LEFTOVERS); 2297 build_leftovers_ft_param(&priority, 2298 &num_entries, 2299 &num_groups); 2300 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO]; 2301 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 2302 if (!MLX5_CAP_FLOWTABLE(dev->mdev, 2303 allow_sniffer_and_nic_rx_shared_tir)) 2304 return ERR_PTR(-ENOTSUPP); 2305 2306 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ? 2307 MLX5_FLOW_NAMESPACE_SNIFFER_RX : 2308 MLX5_FLOW_NAMESPACE_SNIFFER_TX); 2309 2310 prio = &dev->flow_db.sniffer[ft_type]; 2311 priority = 0; 2312 num_entries = 1; 2313 num_groups = 1; 2314 } 2315 2316 if (!ns) 2317 return ERR_PTR(-ENOTSUPP); 2318 2319 if (num_entries > max_table_size) 2320 return ERR_PTR(-ENOMEM); 2321 2322 ft = prio->flow_table; 2323 if (!ft) { 2324 ft = mlx5_create_auto_grouped_flow_table(ns, priority, 2325 num_entries, 2326 num_groups, 2327 0, 0); 2328 2329 if (!IS_ERR(ft)) { 2330 prio->refcount = 0; 2331 prio->flow_table = ft; 2332 } else { 2333 err = PTR_ERR(ft); 2334 } 2335 } 2336 2337 return err ? ERR_PTR(err) : prio; 2338 } 2339 2340 static void set_underlay_qp(struct mlx5_ib_dev *dev, 2341 struct mlx5_flow_spec *spec, 2342 u32 underlay_qpn) 2343 { 2344 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, 2345 spec->match_criteria, 2346 misc_parameters); 2347 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, 2348 misc_parameters); 2349 2350 if (underlay_qpn && 2351 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 2352 ft_field_support.bth_dst_qp)) { 2353 MLX5_SET(fte_match_set_misc, 2354 misc_params_v, bth_dst_qp, underlay_qpn); 2355 MLX5_SET(fte_match_set_misc, 2356 misc_params_c, bth_dst_qp, 0xffffff); 2357 } 2358 } 2359 2360 static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev, 2361 struct mlx5_ib_flow_prio *ft_prio, 2362 const struct ib_flow_attr *flow_attr, 2363 struct mlx5_flow_destination *dst, 2364 u32 underlay_qpn) 2365 { 2366 struct mlx5_flow_table *ft = ft_prio->flow_table; 2367 struct mlx5_ib_flow_handler *handler; 2368 struct mlx5_flow_act flow_act = {0}; 2369 struct mlx5_flow_spec *spec; 2370 struct mlx5_flow_destination *rule_dst = dst; 2371 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr); 2372 unsigned int spec_index; 2373 u32 flow_tag = MLX5_FS_DEFAULT_FLOW_TAG; 2374 bool is_drop = false; 2375 int err = 0; 2376 int dest_num = 1; 2377 2378 if (!is_valid_attr(dev->mdev, flow_attr)) 2379 return ERR_PTR(-EINVAL); 2380 2381 spec = kvzalloc(sizeof(*spec), GFP_KERNEL); 2382 handler = kzalloc(sizeof(*handler), GFP_KERNEL); 2383 if (!handler || !spec) { 2384 err = -ENOMEM; 2385 goto free; 2386 } 2387 2388 INIT_LIST_HEAD(&handler->list); 2389 2390 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 2391 err = parse_flow_attr(dev->mdev, spec->match_criteria, 2392 spec->match_value, 2393 ib_flow, &flow_tag, &is_drop); 2394 if (err < 0) 2395 goto free; 2396 2397 ib_flow += ((union ib_flow_spec *)ib_flow)->size; 2398 } 2399 2400 if (!flow_is_multicast_only(flow_attr)) 2401 set_underlay_qp(dev, spec, underlay_qpn); 2402 2403 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria); 2404 if (is_drop) { 2405 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_DROP; 2406 rule_dst = NULL; 2407 dest_num = 0; 2408 } else { 2409 flow_act.action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST : 2410 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO; 2411 } 2412 2413 if (flow_tag != MLX5_FS_DEFAULT_FLOW_TAG && 2414 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 2415 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) { 2416 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n", 2417 flow_tag, flow_attr->type); 2418 err = -EINVAL; 2419 goto free; 2420 } 2421 flow_act.flow_tag = flow_tag; 2422 handler->rule = mlx5_add_flow_rules(ft, spec, 2423 &flow_act, 2424 rule_dst, dest_num); 2425 2426 if (IS_ERR(handler->rule)) { 2427 err = PTR_ERR(handler->rule); 2428 goto free; 2429 } 2430 2431 ft_prio->refcount++; 2432 handler->prio = ft_prio; 2433 2434 ft_prio->flow_table = ft; 2435 free: 2436 if (err) 2437 kfree(handler); 2438 kvfree(spec); 2439 return err ? ERR_PTR(err) : handler; 2440 } 2441 2442 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev, 2443 struct mlx5_ib_flow_prio *ft_prio, 2444 const struct ib_flow_attr *flow_attr, 2445 struct mlx5_flow_destination *dst) 2446 { 2447 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0); 2448 } 2449 2450 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev, 2451 struct mlx5_ib_flow_prio *ft_prio, 2452 struct ib_flow_attr *flow_attr, 2453 struct mlx5_flow_destination *dst) 2454 { 2455 struct mlx5_ib_flow_handler *handler_dst = NULL; 2456 struct mlx5_ib_flow_handler *handler = NULL; 2457 2458 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL); 2459 if (!IS_ERR(handler)) { 2460 handler_dst = create_flow_rule(dev, ft_prio, 2461 flow_attr, dst); 2462 if (IS_ERR(handler_dst)) { 2463 mlx5_del_flow_rules(handler->rule); 2464 ft_prio->refcount--; 2465 kfree(handler); 2466 handler = handler_dst; 2467 } else { 2468 list_add(&handler_dst->list, &handler->list); 2469 } 2470 } 2471 2472 return handler; 2473 } 2474 enum { 2475 LEFTOVERS_MC, 2476 LEFTOVERS_UC, 2477 }; 2478 2479 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev, 2480 struct mlx5_ib_flow_prio *ft_prio, 2481 struct ib_flow_attr *flow_attr, 2482 struct mlx5_flow_destination *dst) 2483 { 2484 struct mlx5_ib_flow_handler *handler_ucast = NULL; 2485 struct mlx5_ib_flow_handler *handler = NULL; 2486 2487 static struct { 2488 struct ib_flow_attr flow_attr; 2489 struct ib_flow_spec_eth eth_flow; 2490 } leftovers_specs[] = { 2491 [LEFTOVERS_MC] = { 2492 .flow_attr = { 2493 .num_of_specs = 1, 2494 .size = sizeof(leftovers_specs[0]) 2495 }, 2496 .eth_flow = { 2497 .type = IB_FLOW_SPEC_ETH, 2498 .size = sizeof(struct ib_flow_spec_eth), 2499 .mask = {.dst_mac = {0x1} }, 2500 .val = {.dst_mac = {0x1} } 2501 } 2502 }, 2503 [LEFTOVERS_UC] = { 2504 .flow_attr = { 2505 .num_of_specs = 1, 2506 .size = sizeof(leftovers_specs[0]) 2507 }, 2508 .eth_flow = { 2509 .type = IB_FLOW_SPEC_ETH, 2510 .size = sizeof(struct ib_flow_spec_eth), 2511 .mask = {.dst_mac = {0x1} }, 2512 .val = {.dst_mac = {} } 2513 } 2514 } 2515 }; 2516 2517 handler = create_flow_rule(dev, ft_prio, 2518 &leftovers_specs[LEFTOVERS_MC].flow_attr, 2519 dst); 2520 if (!IS_ERR(handler) && 2521 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) { 2522 handler_ucast = create_flow_rule(dev, ft_prio, 2523 &leftovers_specs[LEFTOVERS_UC].flow_attr, 2524 dst); 2525 if (IS_ERR(handler_ucast)) { 2526 mlx5_del_flow_rules(handler->rule); 2527 ft_prio->refcount--; 2528 kfree(handler); 2529 handler = handler_ucast; 2530 } else { 2531 list_add(&handler_ucast->list, &handler->list); 2532 } 2533 } 2534 2535 return handler; 2536 } 2537 2538 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev, 2539 struct mlx5_ib_flow_prio *ft_rx, 2540 struct mlx5_ib_flow_prio *ft_tx, 2541 struct mlx5_flow_destination *dst) 2542 { 2543 struct mlx5_ib_flow_handler *handler_rx; 2544 struct mlx5_ib_flow_handler *handler_tx; 2545 int err; 2546 static const struct ib_flow_attr flow_attr = { 2547 .num_of_specs = 0, 2548 .size = sizeof(flow_attr) 2549 }; 2550 2551 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst); 2552 if (IS_ERR(handler_rx)) { 2553 err = PTR_ERR(handler_rx); 2554 goto err; 2555 } 2556 2557 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst); 2558 if (IS_ERR(handler_tx)) { 2559 err = PTR_ERR(handler_tx); 2560 goto err_tx; 2561 } 2562 2563 list_add(&handler_tx->list, &handler_rx->list); 2564 2565 return handler_rx; 2566 2567 err_tx: 2568 mlx5_del_flow_rules(handler_rx->rule); 2569 ft_rx->refcount--; 2570 kfree(handler_rx); 2571 err: 2572 return ERR_PTR(err); 2573 } 2574 2575 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp, 2576 struct ib_flow_attr *flow_attr, 2577 int domain) 2578 { 2579 struct mlx5_ib_dev *dev = to_mdev(qp->device); 2580 struct mlx5_ib_qp *mqp = to_mqp(qp); 2581 struct mlx5_ib_flow_handler *handler = NULL; 2582 struct mlx5_flow_destination *dst = NULL; 2583 struct mlx5_ib_flow_prio *ft_prio_tx = NULL; 2584 struct mlx5_ib_flow_prio *ft_prio; 2585 int err; 2586 int underlay_qpn; 2587 2588 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) 2589 return ERR_PTR(-ENOMEM); 2590 2591 if (domain != IB_FLOW_DOMAIN_USER || 2592 flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) || 2593 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP)) 2594 return ERR_PTR(-EINVAL); 2595 2596 dst = kzalloc(sizeof(*dst), GFP_KERNEL); 2597 if (!dst) 2598 return ERR_PTR(-ENOMEM); 2599 2600 mutex_lock(&dev->flow_db.lock); 2601 2602 ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX); 2603 if (IS_ERR(ft_prio)) { 2604 err = PTR_ERR(ft_prio); 2605 goto unlock; 2606 } 2607 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 2608 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX); 2609 if (IS_ERR(ft_prio_tx)) { 2610 err = PTR_ERR(ft_prio_tx); 2611 ft_prio_tx = NULL; 2612 goto destroy_ft; 2613 } 2614 } 2615 2616 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR; 2617 if (mqp->flags & MLX5_IB_QP_RSS) 2618 dst->tir_num = mqp->rss_qp.tirn; 2619 else 2620 dst->tir_num = mqp->raw_packet_qp.rq.tirn; 2621 2622 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 2623 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) { 2624 handler = create_dont_trap_rule(dev, ft_prio, 2625 flow_attr, dst); 2626 } else { 2627 underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ? 2628 mqp->underlay_qpn : 0; 2629 handler = _create_flow_rule(dev, ft_prio, flow_attr, 2630 dst, underlay_qpn); 2631 } 2632 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 2633 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 2634 handler = create_leftovers_rule(dev, ft_prio, flow_attr, 2635 dst); 2636 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 2637 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst); 2638 } else { 2639 err = -EINVAL; 2640 goto destroy_ft; 2641 } 2642 2643 if (IS_ERR(handler)) { 2644 err = PTR_ERR(handler); 2645 handler = NULL; 2646 goto destroy_ft; 2647 } 2648 2649 mutex_unlock(&dev->flow_db.lock); 2650 kfree(dst); 2651 2652 return &handler->ibflow; 2653 2654 destroy_ft: 2655 put_flow_table(dev, ft_prio, false); 2656 if (ft_prio_tx) 2657 put_flow_table(dev, ft_prio_tx, false); 2658 unlock: 2659 mutex_unlock(&dev->flow_db.lock); 2660 kfree(dst); 2661 kfree(handler); 2662 return ERR_PTR(err); 2663 } 2664 2665 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2666 { 2667 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2668 struct mlx5_ib_qp *mqp = to_mqp(ibqp); 2669 int err; 2670 2671 if (mqp->flags & MLX5_IB_QP_UNDERLAY) { 2672 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n"); 2673 return -EOPNOTSUPP; 2674 } 2675 2676 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num); 2677 if (err) 2678 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 2679 ibqp->qp_num, gid->raw); 2680 2681 return err; 2682 } 2683 2684 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2685 { 2686 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2687 int err; 2688 2689 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num); 2690 if (err) 2691 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 2692 ibqp->qp_num, gid->raw); 2693 2694 return err; 2695 } 2696 2697 static int init_node_data(struct mlx5_ib_dev *dev) 2698 { 2699 int err; 2700 2701 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 2702 if (err) 2703 return err; 2704 2705 dev->mdev->rev_id = dev->mdev->pdev->revision; 2706 2707 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 2708 } 2709 2710 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr, 2711 char *buf) 2712 { 2713 struct mlx5_ib_dev *dev = 2714 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2715 2716 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages); 2717 } 2718 2719 static ssize_t show_reg_pages(struct device *device, 2720 struct device_attribute *attr, char *buf) 2721 { 2722 struct mlx5_ib_dev *dev = 2723 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2724 2725 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 2726 } 2727 2728 static ssize_t show_hca(struct device *device, struct device_attribute *attr, 2729 char *buf) 2730 { 2731 struct mlx5_ib_dev *dev = 2732 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2733 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device); 2734 } 2735 2736 static ssize_t show_rev(struct device *device, struct device_attribute *attr, 2737 char *buf) 2738 { 2739 struct mlx5_ib_dev *dev = 2740 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2741 return sprintf(buf, "%x\n", dev->mdev->rev_id); 2742 } 2743 2744 static ssize_t show_board(struct device *device, struct device_attribute *attr, 2745 char *buf) 2746 { 2747 struct mlx5_ib_dev *dev = 2748 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2749 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 2750 dev->mdev->board_id); 2751 } 2752 2753 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL); 2754 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL); 2755 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL); 2756 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL); 2757 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL); 2758 2759 static struct device_attribute *mlx5_class_attributes[] = { 2760 &dev_attr_hw_rev, 2761 &dev_attr_hca_type, 2762 &dev_attr_board_id, 2763 &dev_attr_fw_pages, 2764 &dev_attr_reg_pages, 2765 }; 2766 2767 static void pkey_change_handler(struct work_struct *work) 2768 { 2769 struct mlx5_ib_port_resources *ports = 2770 container_of(work, struct mlx5_ib_port_resources, 2771 pkey_change_work); 2772 2773 mutex_lock(&ports->devr->mutex); 2774 mlx5_ib_gsi_pkey_change(ports->gsi); 2775 mutex_unlock(&ports->devr->mutex); 2776 } 2777 2778 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 2779 { 2780 struct mlx5_ib_qp *mqp; 2781 struct mlx5_ib_cq *send_mcq, *recv_mcq; 2782 struct mlx5_core_cq *mcq; 2783 struct list_head cq_armed_list; 2784 unsigned long flags_qp; 2785 unsigned long flags_cq; 2786 unsigned long flags; 2787 2788 INIT_LIST_HEAD(&cq_armed_list); 2789 2790 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 2791 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 2792 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 2793 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 2794 if (mqp->sq.tail != mqp->sq.head) { 2795 send_mcq = to_mcq(mqp->ibqp.send_cq); 2796 spin_lock_irqsave(&send_mcq->lock, flags_cq); 2797 if (send_mcq->mcq.comp && 2798 mqp->ibqp.send_cq->comp_handler) { 2799 if (!send_mcq->mcq.reset_notify_added) { 2800 send_mcq->mcq.reset_notify_added = 1; 2801 list_add_tail(&send_mcq->mcq.reset_notify, 2802 &cq_armed_list); 2803 } 2804 } 2805 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 2806 } 2807 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 2808 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 2809 /* no handling is needed for SRQ */ 2810 if (!mqp->ibqp.srq) { 2811 if (mqp->rq.tail != mqp->rq.head) { 2812 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 2813 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 2814 if (recv_mcq->mcq.comp && 2815 mqp->ibqp.recv_cq->comp_handler) { 2816 if (!recv_mcq->mcq.reset_notify_added) { 2817 recv_mcq->mcq.reset_notify_added = 1; 2818 list_add_tail(&recv_mcq->mcq.reset_notify, 2819 &cq_armed_list); 2820 } 2821 } 2822 spin_unlock_irqrestore(&recv_mcq->lock, 2823 flags_cq); 2824 } 2825 } 2826 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 2827 } 2828 /*At that point all inflight post send were put to be executed as of we 2829 * lock/unlock above locks Now need to arm all involved CQs. 2830 */ 2831 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 2832 mcq->comp(mcq); 2833 } 2834 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 2835 } 2836 2837 static void delay_drop_handler(struct work_struct *work) 2838 { 2839 int err; 2840 struct mlx5_ib_delay_drop *delay_drop = 2841 container_of(work, struct mlx5_ib_delay_drop, 2842 delay_drop_work); 2843 2844 atomic_inc(&delay_drop->events_cnt); 2845 2846 mutex_lock(&delay_drop->lock); 2847 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev, 2848 delay_drop->timeout); 2849 if (err) { 2850 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n", 2851 delay_drop->timeout); 2852 delay_drop->activate = false; 2853 } 2854 mutex_unlock(&delay_drop->lock); 2855 } 2856 2857 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context, 2858 enum mlx5_dev_event event, unsigned long param) 2859 { 2860 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context; 2861 struct ib_event ibev; 2862 bool fatal = false; 2863 u8 port = 0; 2864 2865 switch (event) { 2866 case MLX5_DEV_EVENT_SYS_ERROR: 2867 ibev.event = IB_EVENT_DEVICE_FATAL; 2868 mlx5_ib_handle_internal_error(ibdev); 2869 fatal = true; 2870 break; 2871 2872 case MLX5_DEV_EVENT_PORT_UP: 2873 case MLX5_DEV_EVENT_PORT_DOWN: 2874 case MLX5_DEV_EVENT_PORT_INITIALIZED: 2875 port = (u8)param; 2876 2877 /* In RoCE, port up/down events are handled in 2878 * mlx5_netdev_event(). 2879 */ 2880 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2881 IB_LINK_LAYER_ETHERNET) 2882 return; 2883 2884 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ? 2885 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 2886 break; 2887 2888 case MLX5_DEV_EVENT_LID_CHANGE: 2889 ibev.event = IB_EVENT_LID_CHANGE; 2890 port = (u8)param; 2891 break; 2892 2893 case MLX5_DEV_EVENT_PKEY_CHANGE: 2894 ibev.event = IB_EVENT_PKEY_CHANGE; 2895 port = (u8)param; 2896 2897 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 2898 break; 2899 2900 case MLX5_DEV_EVENT_GUID_CHANGE: 2901 ibev.event = IB_EVENT_GID_CHANGE; 2902 port = (u8)param; 2903 break; 2904 2905 case MLX5_DEV_EVENT_CLIENT_REREG: 2906 ibev.event = IB_EVENT_CLIENT_REREGISTER; 2907 port = (u8)param; 2908 break; 2909 case MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT: 2910 schedule_work(&ibdev->delay_drop.delay_drop_work); 2911 goto out; 2912 default: 2913 goto out; 2914 } 2915 2916 ibev.device = &ibdev->ib_dev; 2917 ibev.element.port_num = port; 2918 2919 if (port < 1 || port > ibdev->num_ports) { 2920 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port); 2921 goto out; 2922 } 2923 2924 if (ibdev->ib_active) 2925 ib_dispatch_event(&ibev); 2926 2927 if (fatal) 2928 ibdev->ib_active = false; 2929 2930 out: 2931 return; 2932 } 2933 2934 static int set_has_smi_cap(struct mlx5_ib_dev *dev) 2935 { 2936 struct mlx5_hca_vport_context vport_ctx; 2937 int err; 2938 int port; 2939 2940 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) { 2941 dev->mdev->port_caps[port - 1].has_smi = false; 2942 if (MLX5_CAP_GEN(dev->mdev, port_type) == 2943 MLX5_CAP_PORT_TYPE_IB) { 2944 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) { 2945 err = mlx5_query_hca_vport_context(dev->mdev, 0, 2946 port, 0, 2947 &vport_ctx); 2948 if (err) { 2949 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n", 2950 port, err); 2951 return err; 2952 } 2953 dev->mdev->port_caps[port - 1].has_smi = 2954 vport_ctx.has_smi; 2955 } else { 2956 dev->mdev->port_caps[port - 1].has_smi = true; 2957 } 2958 } 2959 } 2960 return 0; 2961 } 2962 2963 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 2964 { 2965 int port; 2966 2967 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) 2968 mlx5_query_ext_port_caps(dev, port); 2969 } 2970 2971 static int get_port_caps(struct mlx5_ib_dev *dev) 2972 { 2973 struct ib_device_attr *dprops = NULL; 2974 struct ib_port_attr *pprops = NULL; 2975 int err = -ENOMEM; 2976 int port; 2977 struct ib_udata uhw = {.inlen = 0, .outlen = 0}; 2978 2979 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL); 2980 if (!pprops) 2981 goto out; 2982 2983 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL); 2984 if (!dprops) 2985 goto out; 2986 2987 err = set_has_smi_cap(dev); 2988 if (err) 2989 goto out; 2990 2991 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw); 2992 if (err) { 2993 mlx5_ib_warn(dev, "query_device failed %d\n", err); 2994 goto out; 2995 } 2996 2997 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) { 2998 memset(pprops, 0, sizeof(*pprops)); 2999 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops); 3000 if (err) { 3001 mlx5_ib_warn(dev, "query_port %d failed %d\n", 3002 port, err); 3003 break; 3004 } 3005 dev->mdev->port_caps[port - 1].pkey_table_len = 3006 dprops->max_pkeys; 3007 dev->mdev->port_caps[port - 1].gid_table_len = 3008 pprops->gid_tbl_len; 3009 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n", 3010 dprops->max_pkeys, pprops->gid_tbl_len); 3011 } 3012 3013 out: 3014 kfree(pprops); 3015 kfree(dprops); 3016 3017 return err; 3018 } 3019 3020 static void destroy_umrc_res(struct mlx5_ib_dev *dev) 3021 { 3022 int err; 3023 3024 err = mlx5_mr_cache_cleanup(dev); 3025 if (err) 3026 mlx5_ib_warn(dev, "mr cache cleanup failed\n"); 3027 3028 mlx5_ib_destroy_qp(dev->umrc.qp); 3029 ib_free_cq(dev->umrc.cq); 3030 ib_dealloc_pd(dev->umrc.pd); 3031 } 3032 3033 enum { 3034 MAX_UMR_WR = 128, 3035 }; 3036 3037 static int create_umr_res(struct mlx5_ib_dev *dev) 3038 { 3039 struct ib_qp_init_attr *init_attr = NULL; 3040 struct ib_qp_attr *attr = NULL; 3041 struct ib_pd *pd; 3042 struct ib_cq *cq; 3043 struct ib_qp *qp; 3044 int ret; 3045 3046 attr = kzalloc(sizeof(*attr), GFP_KERNEL); 3047 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL); 3048 if (!attr || !init_attr) { 3049 ret = -ENOMEM; 3050 goto error_0; 3051 } 3052 3053 pd = ib_alloc_pd(&dev->ib_dev, 0); 3054 if (IS_ERR(pd)) { 3055 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n"); 3056 ret = PTR_ERR(pd); 3057 goto error_0; 3058 } 3059 3060 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ); 3061 if (IS_ERR(cq)) { 3062 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n"); 3063 ret = PTR_ERR(cq); 3064 goto error_2; 3065 } 3066 3067 init_attr->send_cq = cq; 3068 init_attr->recv_cq = cq; 3069 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR; 3070 init_attr->cap.max_send_wr = MAX_UMR_WR; 3071 init_attr->cap.max_send_sge = 1; 3072 init_attr->qp_type = MLX5_IB_QPT_REG_UMR; 3073 init_attr->port_num = 1; 3074 qp = mlx5_ib_create_qp(pd, init_attr, NULL); 3075 if (IS_ERR(qp)) { 3076 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n"); 3077 ret = PTR_ERR(qp); 3078 goto error_3; 3079 } 3080 qp->device = &dev->ib_dev; 3081 qp->real_qp = qp; 3082 qp->uobject = NULL; 3083 qp->qp_type = MLX5_IB_QPT_REG_UMR; 3084 3085 attr->qp_state = IB_QPS_INIT; 3086 attr->port_num = 1; 3087 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX | 3088 IB_QP_PORT, NULL); 3089 if (ret) { 3090 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n"); 3091 goto error_4; 3092 } 3093 3094 memset(attr, 0, sizeof(*attr)); 3095 attr->qp_state = IB_QPS_RTR; 3096 attr->path_mtu = IB_MTU_256; 3097 3098 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 3099 if (ret) { 3100 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n"); 3101 goto error_4; 3102 } 3103 3104 memset(attr, 0, sizeof(*attr)); 3105 attr->qp_state = IB_QPS_RTS; 3106 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 3107 if (ret) { 3108 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n"); 3109 goto error_4; 3110 } 3111 3112 dev->umrc.qp = qp; 3113 dev->umrc.cq = cq; 3114 dev->umrc.pd = pd; 3115 3116 sema_init(&dev->umrc.sem, MAX_UMR_WR); 3117 ret = mlx5_mr_cache_init(dev); 3118 if (ret) { 3119 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 3120 goto error_4; 3121 } 3122 3123 kfree(attr); 3124 kfree(init_attr); 3125 3126 return 0; 3127 3128 error_4: 3129 mlx5_ib_destroy_qp(qp); 3130 3131 error_3: 3132 ib_free_cq(cq); 3133 3134 error_2: 3135 ib_dealloc_pd(pd); 3136 3137 error_0: 3138 kfree(attr); 3139 kfree(init_attr); 3140 return ret; 3141 } 3142 3143 static u8 mlx5_get_umr_fence(u8 umr_fence_cap) 3144 { 3145 switch (umr_fence_cap) { 3146 case MLX5_CAP_UMR_FENCE_NONE: 3147 return MLX5_FENCE_MODE_NONE; 3148 case MLX5_CAP_UMR_FENCE_SMALL: 3149 return MLX5_FENCE_MODE_INITIATOR_SMALL; 3150 default: 3151 return MLX5_FENCE_MODE_STRONG_ORDERING; 3152 } 3153 } 3154 3155 static int create_dev_resources(struct mlx5_ib_resources *devr) 3156 { 3157 struct ib_srq_init_attr attr; 3158 struct mlx5_ib_dev *dev; 3159 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 3160 int port; 3161 int ret = 0; 3162 3163 dev = container_of(devr, struct mlx5_ib_dev, devr); 3164 3165 mutex_init(&devr->mutex); 3166 3167 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL); 3168 if (IS_ERR(devr->p0)) { 3169 ret = PTR_ERR(devr->p0); 3170 goto error0; 3171 } 3172 devr->p0->device = &dev->ib_dev; 3173 devr->p0->uobject = NULL; 3174 atomic_set(&devr->p0->usecnt, 0); 3175 3176 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL); 3177 if (IS_ERR(devr->c0)) { 3178 ret = PTR_ERR(devr->c0); 3179 goto error1; 3180 } 3181 devr->c0->device = &dev->ib_dev; 3182 devr->c0->uobject = NULL; 3183 devr->c0->comp_handler = NULL; 3184 devr->c0->event_handler = NULL; 3185 devr->c0->cq_context = NULL; 3186 atomic_set(&devr->c0->usecnt, 0); 3187 3188 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 3189 if (IS_ERR(devr->x0)) { 3190 ret = PTR_ERR(devr->x0); 3191 goto error2; 3192 } 3193 devr->x0->device = &dev->ib_dev; 3194 devr->x0->inode = NULL; 3195 atomic_set(&devr->x0->usecnt, 0); 3196 mutex_init(&devr->x0->tgt_qp_mutex); 3197 INIT_LIST_HEAD(&devr->x0->tgt_qp_list); 3198 3199 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 3200 if (IS_ERR(devr->x1)) { 3201 ret = PTR_ERR(devr->x1); 3202 goto error3; 3203 } 3204 devr->x1->device = &dev->ib_dev; 3205 devr->x1->inode = NULL; 3206 atomic_set(&devr->x1->usecnt, 0); 3207 mutex_init(&devr->x1->tgt_qp_mutex); 3208 INIT_LIST_HEAD(&devr->x1->tgt_qp_list); 3209 3210 memset(&attr, 0, sizeof(attr)); 3211 attr.attr.max_sge = 1; 3212 attr.attr.max_wr = 1; 3213 attr.srq_type = IB_SRQT_XRC; 3214 attr.ext.xrc.cq = devr->c0; 3215 attr.ext.xrc.xrcd = devr->x0; 3216 3217 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 3218 if (IS_ERR(devr->s0)) { 3219 ret = PTR_ERR(devr->s0); 3220 goto error4; 3221 } 3222 devr->s0->device = &dev->ib_dev; 3223 devr->s0->pd = devr->p0; 3224 devr->s0->uobject = NULL; 3225 devr->s0->event_handler = NULL; 3226 devr->s0->srq_context = NULL; 3227 devr->s0->srq_type = IB_SRQT_XRC; 3228 devr->s0->ext.xrc.xrcd = devr->x0; 3229 devr->s0->ext.xrc.cq = devr->c0; 3230 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt); 3231 atomic_inc(&devr->s0->ext.xrc.cq->usecnt); 3232 atomic_inc(&devr->p0->usecnt); 3233 atomic_set(&devr->s0->usecnt, 0); 3234 3235 memset(&attr, 0, sizeof(attr)); 3236 attr.attr.max_sge = 1; 3237 attr.attr.max_wr = 1; 3238 attr.srq_type = IB_SRQT_BASIC; 3239 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 3240 if (IS_ERR(devr->s1)) { 3241 ret = PTR_ERR(devr->s1); 3242 goto error5; 3243 } 3244 devr->s1->device = &dev->ib_dev; 3245 devr->s1->pd = devr->p0; 3246 devr->s1->uobject = NULL; 3247 devr->s1->event_handler = NULL; 3248 devr->s1->srq_context = NULL; 3249 devr->s1->srq_type = IB_SRQT_BASIC; 3250 devr->s1->ext.xrc.cq = devr->c0; 3251 atomic_inc(&devr->p0->usecnt); 3252 atomic_set(&devr->s0->usecnt, 0); 3253 3254 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) { 3255 INIT_WORK(&devr->ports[port].pkey_change_work, 3256 pkey_change_handler); 3257 devr->ports[port].devr = devr; 3258 } 3259 3260 return 0; 3261 3262 error5: 3263 mlx5_ib_destroy_srq(devr->s0); 3264 error4: 3265 mlx5_ib_dealloc_xrcd(devr->x1); 3266 error3: 3267 mlx5_ib_dealloc_xrcd(devr->x0); 3268 error2: 3269 mlx5_ib_destroy_cq(devr->c0); 3270 error1: 3271 mlx5_ib_dealloc_pd(devr->p0); 3272 error0: 3273 return ret; 3274 } 3275 3276 static void destroy_dev_resources(struct mlx5_ib_resources *devr) 3277 { 3278 struct mlx5_ib_dev *dev = 3279 container_of(devr, struct mlx5_ib_dev, devr); 3280 int port; 3281 3282 mlx5_ib_destroy_srq(devr->s1); 3283 mlx5_ib_destroy_srq(devr->s0); 3284 mlx5_ib_dealloc_xrcd(devr->x0); 3285 mlx5_ib_dealloc_xrcd(devr->x1); 3286 mlx5_ib_destroy_cq(devr->c0); 3287 mlx5_ib_dealloc_pd(devr->p0); 3288 3289 /* Make sure no change P_Key work items are still executing */ 3290 for (port = 0; port < dev->num_ports; ++port) 3291 cancel_work_sync(&devr->ports[port].pkey_change_work); 3292 } 3293 3294 static u32 get_core_cap_flags(struct ib_device *ibdev) 3295 { 3296 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3297 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 3298 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 3299 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 3300 u32 ret = 0; 3301 3302 if (ll == IB_LINK_LAYER_INFINIBAND) 3303 return RDMA_CORE_PORT_IBA_IB; 3304 3305 ret = RDMA_CORE_PORT_RAW_PACKET; 3306 3307 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 3308 return ret; 3309 3310 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 3311 return ret; 3312 3313 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 3314 ret |= RDMA_CORE_PORT_IBA_ROCE; 3315 3316 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 3317 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 3318 3319 return ret; 3320 } 3321 3322 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num, 3323 struct ib_port_immutable *immutable) 3324 { 3325 struct ib_port_attr attr; 3326 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3327 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num); 3328 int err; 3329 3330 immutable->core_cap_flags = get_core_cap_flags(ibdev); 3331 3332 err = ib_query_port(ibdev, port_num, &attr); 3333 if (err) 3334 return err; 3335 3336 immutable->pkey_tbl_len = attr.pkey_tbl_len; 3337 immutable->gid_tbl_len = attr.gid_tbl_len; 3338 immutable->core_cap_flags = get_core_cap_flags(ibdev); 3339 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce)) 3340 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 3341 3342 return 0; 3343 } 3344 3345 static void get_dev_fw_str(struct ib_device *ibdev, char *str) 3346 { 3347 struct mlx5_ib_dev *dev = 3348 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 3349 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d", 3350 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev), 3351 fw_rev_sub(dev->mdev)); 3352 } 3353 3354 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev) 3355 { 3356 struct mlx5_core_dev *mdev = dev->mdev; 3357 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev, 3358 MLX5_FLOW_NAMESPACE_LAG); 3359 struct mlx5_flow_table *ft; 3360 int err; 3361 3362 if (!ns || !mlx5_lag_is_active(mdev)) 3363 return 0; 3364 3365 err = mlx5_cmd_create_vport_lag(mdev); 3366 if (err) 3367 return err; 3368 3369 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0); 3370 if (IS_ERR(ft)) { 3371 err = PTR_ERR(ft); 3372 goto err_destroy_vport_lag; 3373 } 3374 3375 dev->flow_db.lag_demux_ft = ft; 3376 return 0; 3377 3378 err_destroy_vport_lag: 3379 mlx5_cmd_destroy_vport_lag(mdev); 3380 return err; 3381 } 3382 3383 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev) 3384 { 3385 struct mlx5_core_dev *mdev = dev->mdev; 3386 3387 if (dev->flow_db.lag_demux_ft) { 3388 mlx5_destroy_flow_table(dev->flow_db.lag_demux_ft); 3389 dev->flow_db.lag_demux_ft = NULL; 3390 3391 mlx5_cmd_destroy_vport_lag(mdev); 3392 } 3393 } 3394 3395 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev) 3396 { 3397 int err; 3398 3399 dev->roce.nb.notifier_call = mlx5_netdev_event; 3400 err = register_netdevice_notifier(&dev->roce.nb); 3401 if (err) { 3402 dev->roce.nb.notifier_call = NULL; 3403 return err; 3404 } 3405 3406 return 0; 3407 } 3408 3409 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev) 3410 { 3411 if (dev->roce.nb.notifier_call) { 3412 unregister_netdevice_notifier(&dev->roce.nb); 3413 dev->roce.nb.notifier_call = NULL; 3414 } 3415 } 3416 3417 static int mlx5_enable_eth(struct mlx5_ib_dev *dev) 3418 { 3419 int err; 3420 3421 err = mlx5_add_netdev_notifier(dev); 3422 if (err) 3423 return err; 3424 3425 if (MLX5_CAP_GEN(dev->mdev, roce)) { 3426 err = mlx5_nic_vport_enable_roce(dev->mdev); 3427 if (err) 3428 goto err_unregister_netdevice_notifier; 3429 } 3430 3431 err = mlx5_eth_lag_init(dev); 3432 if (err) 3433 goto err_disable_roce; 3434 3435 return 0; 3436 3437 err_disable_roce: 3438 if (MLX5_CAP_GEN(dev->mdev, roce)) 3439 mlx5_nic_vport_disable_roce(dev->mdev); 3440 3441 err_unregister_netdevice_notifier: 3442 mlx5_remove_netdev_notifier(dev); 3443 return err; 3444 } 3445 3446 static void mlx5_disable_eth(struct mlx5_ib_dev *dev) 3447 { 3448 mlx5_eth_lag_cleanup(dev); 3449 if (MLX5_CAP_GEN(dev->mdev, roce)) 3450 mlx5_nic_vport_disable_roce(dev->mdev); 3451 } 3452 3453 struct mlx5_ib_counter { 3454 const char *name; 3455 size_t offset; 3456 }; 3457 3458 #define INIT_Q_COUNTER(_name) \ 3459 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)} 3460 3461 static const struct mlx5_ib_counter basic_q_cnts[] = { 3462 INIT_Q_COUNTER(rx_write_requests), 3463 INIT_Q_COUNTER(rx_read_requests), 3464 INIT_Q_COUNTER(rx_atomic_requests), 3465 INIT_Q_COUNTER(out_of_buffer), 3466 }; 3467 3468 static const struct mlx5_ib_counter out_of_seq_q_cnts[] = { 3469 INIT_Q_COUNTER(out_of_sequence), 3470 }; 3471 3472 static const struct mlx5_ib_counter retrans_q_cnts[] = { 3473 INIT_Q_COUNTER(duplicate_request), 3474 INIT_Q_COUNTER(rnr_nak_retry_err), 3475 INIT_Q_COUNTER(packet_seq_err), 3476 INIT_Q_COUNTER(implied_nak_seq_err), 3477 INIT_Q_COUNTER(local_ack_timeout_err), 3478 }; 3479 3480 #define INIT_CONG_COUNTER(_name) \ 3481 { .name = #_name, .offset = \ 3482 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)} 3483 3484 static const struct mlx5_ib_counter cong_cnts[] = { 3485 INIT_CONG_COUNTER(rp_cnp_ignored), 3486 INIT_CONG_COUNTER(rp_cnp_handled), 3487 INIT_CONG_COUNTER(np_ecn_marked_roce_packets), 3488 INIT_CONG_COUNTER(np_cnp_sent), 3489 }; 3490 3491 static const struct mlx5_ib_counter extended_err_cnts[] = { 3492 INIT_Q_COUNTER(resp_local_length_error), 3493 INIT_Q_COUNTER(resp_cqe_error), 3494 INIT_Q_COUNTER(req_cqe_error), 3495 INIT_Q_COUNTER(req_remote_invalid_request), 3496 INIT_Q_COUNTER(req_remote_access_errors), 3497 INIT_Q_COUNTER(resp_remote_access_errors), 3498 INIT_Q_COUNTER(resp_cqe_flush_error), 3499 INIT_Q_COUNTER(req_cqe_flush_error), 3500 }; 3501 3502 static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev) 3503 { 3504 unsigned int i; 3505 3506 for (i = 0; i < dev->num_ports; i++) { 3507 mlx5_core_dealloc_q_counter(dev->mdev, 3508 dev->port[i].cnts.set_id); 3509 kfree(dev->port[i].cnts.names); 3510 kfree(dev->port[i].cnts.offsets); 3511 } 3512 } 3513 3514 static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev, 3515 struct mlx5_ib_counters *cnts) 3516 { 3517 u32 num_counters; 3518 3519 num_counters = ARRAY_SIZE(basic_q_cnts); 3520 3521 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) 3522 num_counters += ARRAY_SIZE(out_of_seq_q_cnts); 3523 3524 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) 3525 num_counters += ARRAY_SIZE(retrans_q_cnts); 3526 3527 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) 3528 num_counters += ARRAY_SIZE(extended_err_cnts); 3529 3530 cnts->num_q_counters = num_counters; 3531 3532 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 3533 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts); 3534 num_counters += ARRAY_SIZE(cong_cnts); 3535 } 3536 3537 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL); 3538 if (!cnts->names) 3539 return -ENOMEM; 3540 3541 cnts->offsets = kcalloc(num_counters, 3542 sizeof(cnts->offsets), GFP_KERNEL); 3543 if (!cnts->offsets) 3544 goto err_names; 3545 3546 return 0; 3547 3548 err_names: 3549 kfree(cnts->names); 3550 return -ENOMEM; 3551 } 3552 3553 static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev, 3554 const char **names, 3555 size_t *offsets) 3556 { 3557 int i; 3558 int j = 0; 3559 3560 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) { 3561 names[j] = basic_q_cnts[i].name; 3562 offsets[j] = basic_q_cnts[i].offset; 3563 } 3564 3565 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) { 3566 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) { 3567 names[j] = out_of_seq_q_cnts[i].name; 3568 offsets[j] = out_of_seq_q_cnts[i].offset; 3569 } 3570 } 3571 3572 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) { 3573 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) { 3574 names[j] = retrans_q_cnts[i].name; 3575 offsets[j] = retrans_q_cnts[i].offset; 3576 } 3577 } 3578 3579 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) { 3580 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) { 3581 names[j] = extended_err_cnts[i].name; 3582 offsets[j] = extended_err_cnts[i].offset; 3583 } 3584 } 3585 3586 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 3587 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) { 3588 names[j] = cong_cnts[i].name; 3589 offsets[j] = cong_cnts[i].offset; 3590 } 3591 } 3592 } 3593 3594 static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev) 3595 { 3596 int i; 3597 int ret; 3598 3599 for (i = 0; i < dev->num_ports; i++) { 3600 struct mlx5_ib_port *port = &dev->port[i]; 3601 3602 ret = mlx5_core_alloc_q_counter(dev->mdev, 3603 &port->cnts.set_id); 3604 if (ret) { 3605 mlx5_ib_warn(dev, 3606 "couldn't allocate queue counter for port %d, err %d\n", 3607 i + 1, ret); 3608 goto dealloc_counters; 3609 } 3610 3611 ret = __mlx5_ib_alloc_counters(dev, &port->cnts); 3612 if (ret) 3613 goto dealloc_counters; 3614 3615 mlx5_ib_fill_counters(dev, port->cnts.names, 3616 port->cnts.offsets); 3617 } 3618 3619 return 0; 3620 3621 dealloc_counters: 3622 while (--i >= 0) 3623 mlx5_core_dealloc_q_counter(dev->mdev, 3624 dev->port[i].cnts.set_id); 3625 3626 return ret; 3627 } 3628 3629 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev, 3630 u8 port_num) 3631 { 3632 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3633 struct mlx5_ib_port *port = &dev->port[port_num - 1]; 3634 3635 /* We support only per port stats */ 3636 if (port_num == 0) 3637 return NULL; 3638 3639 return rdma_alloc_hw_stats_struct(port->cnts.names, 3640 port->cnts.num_q_counters + 3641 port->cnts.num_cong_counters, 3642 RDMA_HW_STATS_DEFAULT_LIFESPAN); 3643 } 3644 3645 static int mlx5_ib_query_q_counters(struct mlx5_ib_dev *dev, 3646 struct mlx5_ib_port *port, 3647 struct rdma_hw_stats *stats) 3648 { 3649 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out); 3650 void *out; 3651 __be32 val; 3652 int ret, i; 3653 3654 out = kvzalloc(outlen, GFP_KERNEL); 3655 if (!out) 3656 return -ENOMEM; 3657 3658 ret = mlx5_core_query_q_counter(dev->mdev, 3659 port->cnts.set_id, 0, 3660 out, outlen); 3661 if (ret) 3662 goto free; 3663 3664 for (i = 0; i < port->cnts.num_q_counters; i++) { 3665 val = *(__be32 *)(out + port->cnts.offsets[i]); 3666 stats->value[i] = (u64)be32_to_cpu(val); 3667 } 3668 3669 free: 3670 kvfree(out); 3671 return ret; 3672 } 3673 3674 static int mlx5_ib_query_cong_counters(struct mlx5_ib_dev *dev, 3675 struct mlx5_ib_port *port, 3676 struct rdma_hw_stats *stats) 3677 { 3678 int outlen = MLX5_ST_SZ_BYTES(query_cong_statistics_out); 3679 void *out; 3680 int ret, i; 3681 int offset = port->cnts.num_q_counters; 3682 3683 out = kvzalloc(outlen, GFP_KERNEL); 3684 if (!out) 3685 return -ENOMEM; 3686 3687 ret = mlx5_cmd_query_cong_counter(dev->mdev, false, out, outlen); 3688 if (ret) 3689 goto free; 3690 3691 for (i = 0; i < port->cnts.num_cong_counters; i++) { 3692 stats->value[i + offset] = 3693 be64_to_cpup((__be64 *)(out + 3694 port->cnts.offsets[i + offset])); 3695 } 3696 3697 free: 3698 kvfree(out); 3699 return ret; 3700 } 3701 3702 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev, 3703 struct rdma_hw_stats *stats, 3704 u8 port_num, int index) 3705 { 3706 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3707 struct mlx5_ib_port *port = &dev->port[port_num - 1]; 3708 int ret, num_counters; 3709 3710 if (!stats) 3711 return -EINVAL; 3712 3713 ret = mlx5_ib_query_q_counters(dev, port, stats); 3714 if (ret) 3715 return ret; 3716 num_counters = port->cnts.num_q_counters; 3717 3718 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 3719 ret = mlx5_ib_query_cong_counters(dev, port, stats); 3720 if (ret) 3721 return ret; 3722 num_counters += port->cnts.num_cong_counters; 3723 } 3724 3725 return num_counters; 3726 } 3727 3728 static void mlx5_ib_free_rdma_netdev(struct net_device *netdev) 3729 { 3730 return mlx5_rdma_netdev_free(netdev); 3731 } 3732 3733 static struct net_device* 3734 mlx5_ib_alloc_rdma_netdev(struct ib_device *hca, 3735 u8 port_num, 3736 enum rdma_netdev_t type, 3737 const char *name, 3738 unsigned char name_assign_type, 3739 void (*setup)(struct net_device *)) 3740 { 3741 struct net_device *netdev; 3742 struct rdma_netdev *rn; 3743 3744 if (type != RDMA_NETDEV_IPOIB) 3745 return ERR_PTR(-EOPNOTSUPP); 3746 3747 netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca, 3748 name, setup); 3749 if (likely(!IS_ERR_OR_NULL(netdev))) { 3750 rn = netdev_priv(netdev); 3751 rn->free_rdma_netdev = mlx5_ib_free_rdma_netdev; 3752 } 3753 return netdev; 3754 } 3755 3756 static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev) 3757 { 3758 if (!dev->delay_drop.dbg) 3759 return; 3760 debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs); 3761 kfree(dev->delay_drop.dbg); 3762 dev->delay_drop.dbg = NULL; 3763 } 3764 3765 static void cancel_delay_drop(struct mlx5_ib_dev *dev) 3766 { 3767 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 3768 return; 3769 3770 cancel_work_sync(&dev->delay_drop.delay_drop_work); 3771 delay_drop_debugfs_cleanup(dev); 3772 } 3773 3774 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf, 3775 size_t count, loff_t *pos) 3776 { 3777 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3778 char lbuf[20]; 3779 int len; 3780 3781 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout); 3782 return simple_read_from_buffer(buf, count, pos, lbuf, len); 3783 } 3784 3785 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf, 3786 size_t count, loff_t *pos) 3787 { 3788 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3789 u32 timeout; 3790 u32 var; 3791 3792 if (kstrtouint_from_user(buf, count, 0, &var)) 3793 return -EFAULT; 3794 3795 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 3796 1000); 3797 if (timeout != var) 3798 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n", 3799 timeout); 3800 3801 delay_drop->timeout = timeout; 3802 3803 return count; 3804 } 3805 3806 static const struct file_operations fops_delay_drop_timeout = { 3807 .owner = THIS_MODULE, 3808 .open = simple_open, 3809 .write = delay_drop_timeout_write, 3810 .read = delay_drop_timeout_read, 3811 }; 3812 3813 static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev) 3814 { 3815 struct mlx5_ib_dbg_delay_drop *dbg; 3816 3817 if (!mlx5_debugfs_root) 3818 return 0; 3819 3820 dbg = kzalloc(sizeof(*dbg), GFP_KERNEL); 3821 if (!dbg) 3822 return -ENOMEM; 3823 3824 dbg->dir_debugfs = 3825 debugfs_create_dir("delay_drop", 3826 dev->mdev->priv.dbg_root); 3827 if (!dbg->dir_debugfs) 3828 return -ENOMEM; 3829 3830 dbg->events_cnt_debugfs = 3831 debugfs_create_atomic_t("num_timeout_events", 0400, 3832 dbg->dir_debugfs, 3833 &dev->delay_drop.events_cnt); 3834 if (!dbg->events_cnt_debugfs) 3835 goto out_debugfs; 3836 3837 dbg->rqs_cnt_debugfs = 3838 debugfs_create_atomic_t("num_rqs", 0400, 3839 dbg->dir_debugfs, 3840 &dev->delay_drop.rqs_cnt); 3841 if (!dbg->rqs_cnt_debugfs) 3842 goto out_debugfs; 3843 3844 dbg->timeout_debugfs = 3845 debugfs_create_file("timeout", 0600, 3846 dbg->dir_debugfs, 3847 &dev->delay_drop, 3848 &fops_delay_drop_timeout); 3849 if (!dbg->timeout_debugfs) 3850 goto out_debugfs; 3851 3852 dev->delay_drop.dbg = dbg; 3853 3854 return 0; 3855 3856 out_debugfs: 3857 delay_drop_debugfs_cleanup(dev); 3858 return -ENOMEM; 3859 } 3860 3861 static void init_delay_drop(struct mlx5_ib_dev *dev) 3862 { 3863 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 3864 return; 3865 3866 mutex_init(&dev->delay_drop.lock); 3867 dev->delay_drop.dev = dev; 3868 dev->delay_drop.activate = false; 3869 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000; 3870 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler); 3871 atomic_set(&dev->delay_drop.rqs_cnt, 0); 3872 atomic_set(&dev->delay_drop.events_cnt, 0); 3873 3874 if (delay_drop_debugfs_init(dev)) 3875 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n"); 3876 } 3877 3878 static const struct cpumask * 3879 mlx5_ib_get_vector_affinity(struct ib_device *ibdev, int comp_vector) 3880 { 3881 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3882 3883 return mlx5_get_vector_affinity(dev->mdev, comp_vector); 3884 } 3885 3886 static void *mlx5_ib_add(struct mlx5_core_dev *mdev) 3887 { 3888 struct mlx5_ib_dev *dev; 3889 enum rdma_link_layer ll; 3890 int port_type_cap; 3891 const char *name; 3892 int err; 3893 int i; 3894 3895 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 3896 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 3897 3898 printk_once(KERN_INFO "%s", mlx5_version); 3899 3900 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev)); 3901 if (!dev) 3902 return NULL; 3903 3904 dev->mdev = mdev; 3905 3906 dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port), 3907 GFP_KERNEL); 3908 if (!dev->port) 3909 goto err_dealloc; 3910 3911 rwlock_init(&dev->roce.netdev_lock); 3912 err = get_port_caps(dev); 3913 if (err) 3914 goto err_free_port; 3915 3916 if (mlx5_use_mad_ifc(dev)) 3917 get_ext_port_caps(dev); 3918 3919 if (!mlx5_lag_is_active(mdev)) 3920 name = "mlx5_%d"; 3921 else 3922 name = "mlx5_bond_%d"; 3923 3924 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX); 3925 dev->ib_dev.owner = THIS_MODULE; 3926 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 3927 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 3928 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports); 3929 dev->ib_dev.phys_port_cnt = dev->num_ports; 3930 dev->ib_dev.num_comp_vectors = 3931 dev->mdev->priv.eq_table.num_comp_vectors; 3932 dev->ib_dev.dev.parent = &mdev->pdev->dev; 3933 3934 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION; 3935 dev->ib_dev.uverbs_cmd_mask = 3936 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | 3937 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | 3938 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | 3939 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | 3940 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | 3941 (1ull << IB_USER_VERBS_CMD_CREATE_AH) | 3942 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) | 3943 (1ull << IB_USER_VERBS_CMD_REG_MR) | 3944 (1ull << IB_USER_VERBS_CMD_REREG_MR) | 3945 (1ull << IB_USER_VERBS_CMD_DEREG_MR) | 3946 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 3947 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | 3948 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) | 3949 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | 3950 (1ull << IB_USER_VERBS_CMD_CREATE_QP) | 3951 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | 3952 (1ull << IB_USER_VERBS_CMD_QUERY_QP) | 3953 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | 3954 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) | 3955 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) | 3956 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | 3957 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | 3958 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | 3959 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | 3960 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) | 3961 (1ull << IB_USER_VERBS_CMD_OPEN_QP); 3962 dev->ib_dev.uverbs_ex_cmd_mask = 3963 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) | 3964 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) | 3965 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) | 3966 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP); 3967 3968 dev->ib_dev.query_device = mlx5_ib_query_device; 3969 dev->ib_dev.query_port = mlx5_ib_query_port; 3970 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer; 3971 if (ll == IB_LINK_LAYER_ETHERNET) 3972 dev->ib_dev.get_netdev = mlx5_ib_get_netdev; 3973 dev->ib_dev.query_gid = mlx5_ib_query_gid; 3974 dev->ib_dev.add_gid = mlx5_ib_add_gid; 3975 dev->ib_dev.del_gid = mlx5_ib_del_gid; 3976 dev->ib_dev.query_pkey = mlx5_ib_query_pkey; 3977 dev->ib_dev.modify_device = mlx5_ib_modify_device; 3978 dev->ib_dev.modify_port = mlx5_ib_modify_port; 3979 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext; 3980 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext; 3981 dev->ib_dev.mmap = mlx5_ib_mmap; 3982 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd; 3983 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd; 3984 dev->ib_dev.create_ah = mlx5_ib_create_ah; 3985 dev->ib_dev.query_ah = mlx5_ib_query_ah; 3986 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah; 3987 dev->ib_dev.create_srq = mlx5_ib_create_srq; 3988 dev->ib_dev.modify_srq = mlx5_ib_modify_srq; 3989 dev->ib_dev.query_srq = mlx5_ib_query_srq; 3990 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq; 3991 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv; 3992 dev->ib_dev.create_qp = mlx5_ib_create_qp; 3993 dev->ib_dev.modify_qp = mlx5_ib_modify_qp; 3994 dev->ib_dev.query_qp = mlx5_ib_query_qp; 3995 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp; 3996 dev->ib_dev.post_send = mlx5_ib_post_send; 3997 dev->ib_dev.post_recv = mlx5_ib_post_recv; 3998 dev->ib_dev.create_cq = mlx5_ib_create_cq; 3999 dev->ib_dev.modify_cq = mlx5_ib_modify_cq; 4000 dev->ib_dev.resize_cq = mlx5_ib_resize_cq; 4001 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq; 4002 dev->ib_dev.poll_cq = mlx5_ib_poll_cq; 4003 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq; 4004 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr; 4005 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr; 4006 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr; 4007 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr; 4008 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach; 4009 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach; 4010 dev->ib_dev.process_mad = mlx5_ib_process_mad; 4011 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr; 4012 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg; 4013 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status; 4014 dev->ib_dev.get_port_immutable = mlx5_port_immutable; 4015 dev->ib_dev.get_dev_fw_str = get_dev_fw_str; 4016 dev->ib_dev.get_vector_affinity = mlx5_ib_get_vector_affinity; 4017 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads)) 4018 dev->ib_dev.alloc_rdma_netdev = mlx5_ib_alloc_rdma_netdev; 4019 4020 if (mlx5_core_is_pf(mdev)) { 4021 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config; 4022 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state; 4023 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats; 4024 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid; 4025 } 4026 4027 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext; 4028 4029 mlx5_ib_internal_fill_odp_caps(dev); 4030 4031 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence)); 4032 4033 if (MLX5_CAP_GEN(mdev, imaicl)) { 4034 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw; 4035 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw; 4036 dev->ib_dev.uverbs_cmd_mask |= 4037 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) | 4038 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW); 4039 } 4040 4041 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) { 4042 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats; 4043 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats; 4044 } 4045 4046 if (MLX5_CAP_GEN(mdev, xrc)) { 4047 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd; 4048 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd; 4049 dev->ib_dev.uverbs_cmd_mask |= 4050 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) | 4051 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD); 4052 } 4053 4054 dev->ib_dev.create_flow = mlx5_ib_create_flow; 4055 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow; 4056 dev->ib_dev.uverbs_ex_cmd_mask |= 4057 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) | 4058 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW); 4059 4060 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) == 4061 IB_LINK_LAYER_ETHERNET) { 4062 dev->ib_dev.create_wq = mlx5_ib_create_wq; 4063 dev->ib_dev.modify_wq = mlx5_ib_modify_wq; 4064 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq; 4065 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table; 4066 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table; 4067 dev->ib_dev.uverbs_ex_cmd_mask |= 4068 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) | 4069 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) | 4070 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) | 4071 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) | 4072 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL); 4073 } 4074 err = init_node_data(dev); 4075 if (err) 4076 goto err_free_port; 4077 4078 mutex_init(&dev->flow_db.lock); 4079 mutex_init(&dev->cap_mask_mutex); 4080 INIT_LIST_HEAD(&dev->qp_list); 4081 spin_lock_init(&dev->reset_flow_resource_lock); 4082 4083 if (ll == IB_LINK_LAYER_ETHERNET) { 4084 err = mlx5_enable_eth(dev); 4085 if (err) 4086 goto err_free_port; 4087 dev->roce.last_port_state = IB_PORT_DOWN; 4088 } 4089 4090 err = create_dev_resources(&dev->devr); 4091 if (err) 4092 goto err_disable_eth; 4093 4094 err = mlx5_ib_odp_init_one(dev); 4095 if (err) 4096 goto err_rsrc; 4097 4098 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) { 4099 err = mlx5_ib_alloc_counters(dev); 4100 if (err) 4101 goto err_odp; 4102 } 4103 4104 err = mlx5_ib_init_cong_debugfs(dev); 4105 if (err) 4106 goto err_cnt; 4107 4108 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev); 4109 if (!dev->mdev->priv.uar) 4110 goto err_cong; 4111 4112 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false); 4113 if (err) 4114 goto err_uar_page; 4115 4116 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true); 4117 if (err) 4118 goto err_bfreg; 4119 4120 err = ib_register_device(&dev->ib_dev, NULL); 4121 if (err) 4122 goto err_fp_bfreg; 4123 4124 err = create_umr_res(dev); 4125 if (err) 4126 goto err_dev; 4127 4128 init_delay_drop(dev); 4129 4130 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) { 4131 err = device_create_file(&dev->ib_dev.dev, 4132 mlx5_class_attributes[i]); 4133 if (err) 4134 goto err_delay_drop; 4135 } 4136 4137 if ((MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && 4138 MLX5_CAP_GEN(mdev, disable_local_lb)) 4139 mutex_init(&dev->lb_mutex); 4140 4141 dev->ib_active = true; 4142 4143 return dev; 4144 4145 err_delay_drop: 4146 cancel_delay_drop(dev); 4147 destroy_umrc_res(dev); 4148 4149 err_dev: 4150 ib_unregister_device(&dev->ib_dev); 4151 4152 err_fp_bfreg: 4153 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 4154 4155 err_bfreg: 4156 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4157 4158 err_uar_page: 4159 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar); 4160 4161 err_cnt: 4162 mlx5_ib_cleanup_cong_debugfs(dev); 4163 err_cong: 4164 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) 4165 mlx5_ib_dealloc_counters(dev); 4166 4167 err_odp: 4168 mlx5_ib_odp_remove_one(dev); 4169 4170 err_rsrc: 4171 destroy_dev_resources(&dev->devr); 4172 4173 err_disable_eth: 4174 if (ll == IB_LINK_LAYER_ETHERNET) { 4175 mlx5_disable_eth(dev); 4176 mlx5_remove_netdev_notifier(dev); 4177 } 4178 4179 err_free_port: 4180 kfree(dev->port); 4181 4182 err_dealloc: 4183 ib_dealloc_device((struct ib_device *)dev); 4184 4185 return NULL; 4186 } 4187 4188 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context) 4189 { 4190 struct mlx5_ib_dev *dev = context; 4191 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1); 4192 4193 cancel_delay_drop(dev); 4194 mlx5_remove_netdev_notifier(dev); 4195 ib_unregister_device(&dev->ib_dev); 4196 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 4197 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4198 mlx5_put_uars_page(dev->mdev, mdev->priv.uar); 4199 mlx5_ib_cleanup_cong_debugfs(dev); 4200 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) 4201 mlx5_ib_dealloc_counters(dev); 4202 destroy_umrc_res(dev); 4203 mlx5_ib_odp_remove_one(dev); 4204 destroy_dev_resources(&dev->devr); 4205 if (ll == IB_LINK_LAYER_ETHERNET) 4206 mlx5_disable_eth(dev); 4207 kfree(dev->port); 4208 ib_dealloc_device(&dev->ib_dev); 4209 } 4210 4211 static struct mlx5_interface mlx5_ib_interface = { 4212 .add = mlx5_ib_add, 4213 .remove = mlx5_ib_remove, 4214 .event = mlx5_ib_event, 4215 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 4216 .pfault = mlx5_ib_pfault, 4217 #endif 4218 .protocol = MLX5_INTERFACE_PROTOCOL_IB, 4219 }; 4220 4221 static int __init mlx5_ib_init(void) 4222 { 4223 int err; 4224 4225 mlx5_ib_odp_init(); 4226 4227 err = mlx5_register_interface(&mlx5_ib_interface); 4228 4229 return err; 4230 } 4231 4232 static void __exit mlx5_ib_cleanup(void) 4233 { 4234 mlx5_unregister_interface(&mlx5_ib_interface); 4235 } 4236 4237 module_init(mlx5_ib_init); 4238 module_exit(mlx5_ib_cleanup); 4239