1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/debugfs.h> 34 #include <linux/highmem.h> 35 #include <linux/module.h> 36 #include <linux/init.h> 37 #include <linux/errno.h> 38 #include <linux/pci.h> 39 #include <linux/dma-mapping.h> 40 #include <linux/slab.h> 41 #if defined(CONFIG_X86) 42 #include <asm/pat.h> 43 #endif 44 #include <linux/sched.h> 45 #include <linux/sched/mm.h> 46 #include <linux/sched/task.h> 47 #include <linux/delay.h> 48 #include <rdma/ib_user_verbs.h> 49 #include <rdma/ib_addr.h> 50 #include <rdma/ib_cache.h> 51 #include <linux/mlx5/port.h> 52 #include <linux/mlx5/vport.h> 53 #include <linux/mlx5/fs.h> 54 #include <linux/list.h> 55 #include <rdma/ib_smi.h> 56 #include <rdma/ib_umem.h> 57 #include <linux/in.h> 58 #include <linux/etherdevice.h> 59 #include "mlx5_ib.h" 60 #include "ib_rep.h" 61 #include "cmd.h" 62 63 #define DRIVER_NAME "mlx5_ib" 64 #define DRIVER_VERSION "5.0-0" 65 66 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 67 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver"); 68 MODULE_LICENSE("Dual BSD/GPL"); 69 70 static char mlx5_version[] = 71 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v" 72 DRIVER_VERSION "\n"; 73 74 struct mlx5_ib_event_work { 75 struct work_struct work; 76 struct mlx5_core_dev *dev; 77 void *context; 78 enum mlx5_dev_event event; 79 unsigned long param; 80 }; 81 82 enum { 83 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 84 }; 85 86 static struct workqueue_struct *mlx5_ib_event_wq; 87 static LIST_HEAD(mlx5_ib_unaffiliated_port_list); 88 static LIST_HEAD(mlx5_ib_dev_list); 89 /* 90 * This mutex should be held when accessing either of the above lists 91 */ 92 static DEFINE_MUTEX(mlx5_ib_multiport_mutex); 93 94 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi) 95 { 96 struct mlx5_ib_dev *dev; 97 98 mutex_lock(&mlx5_ib_multiport_mutex); 99 dev = mpi->ibdev; 100 mutex_unlock(&mlx5_ib_multiport_mutex); 101 return dev; 102 } 103 104 static enum rdma_link_layer 105 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 106 { 107 switch (port_type_cap) { 108 case MLX5_CAP_PORT_TYPE_IB: 109 return IB_LINK_LAYER_INFINIBAND; 110 case MLX5_CAP_PORT_TYPE_ETH: 111 return IB_LINK_LAYER_ETHERNET; 112 default: 113 return IB_LINK_LAYER_UNSPECIFIED; 114 } 115 } 116 117 static enum rdma_link_layer 118 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num) 119 { 120 struct mlx5_ib_dev *dev = to_mdev(device); 121 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 122 123 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 124 } 125 126 static int get_port_state(struct ib_device *ibdev, 127 u8 port_num, 128 enum ib_port_state *state) 129 { 130 struct ib_port_attr attr; 131 int ret; 132 133 memset(&attr, 0, sizeof(attr)); 134 ret = ibdev->query_port(ibdev, port_num, &attr); 135 if (!ret) 136 *state = attr.state; 137 return ret; 138 } 139 140 static int mlx5_netdev_event(struct notifier_block *this, 141 unsigned long event, void *ptr) 142 { 143 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb); 144 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 145 u8 port_num = roce->native_port_num; 146 struct mlx5_core_dev *mdev; 147 struct mlx5_ib_dev *ibdev; 148 149 ibdev = roce->dev; 150 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 151 if (!mdev) 152 return NOTIFY_DONE; 153 154 switch (event) { 155 case NETDEV_REGISTER: 156 case NETDEV_UNREGISTER: 157 write_lock(&roce->netdev_lock); 158 if (ibdev->rep) { 159 struct mlx5_eswitch *esw = ibdev->mdev->priv.eswitch; 160 struct net_device *rep_ndev; 161 162 rep_ndev = mlx5_ib_get_rep_netdev(esw, 163 ibdev->rep->vport); 164 if (rep_ndev == ndev) 165 roce->netdev = (event == NETDEV_UNREGISTER) ? 166 NULL : ndev; 167 } else if (ndev->dev.parent == &ibdev->mdev->pdev->dev) { 168 roce->netdev = (event == NETDEV_UNREGISTER) ? 169 NULL : ndev; 170 } 171 write_unlock(&roce->netdev_lock); 172 break; 173 174 case NETDEV_CHANGE: 175 case NETDEV_UP: 176 case NETDEV_DOWN: { 177 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev); 178 struct net_device *upper = NULL; 179 180 if (lag_ndev) { 181 upper = netdev_master_upper_dev_get(lag_ndev); 182 dev_put(lag_ndev); 183 } 184 185 if ((upper == ndev || (!upper && ndev == roce->netdev)) 186 && ibdev->ib_active) { 187 struct ib_event ibev = { }; 188 enum ib_port_state port_state; 189 190 if (get_port_state(&ibdev->ib_dev, port_num, 191 &port_state)) 192 goto done; 193 194 if (roce->last_port_state == port_state) 195 goto done; 196 197 roce->last_port_state = port_state; 198 ibev.device = &ibdev->ib_dev; 199 if (port_state == IB_PORT_DOWN) 200 ibev.event = IB_EVENT_PORT_ERR; 201 else if (port_state == IB_PORT_ACTIVE) 202 ibev.event = IB_EVENT_PORT_ACTIVE; 203 else 204 goto done; 205 206 ibev.element.port_num = port_num; 207 ib_dispatch_event(&ibev); 208 } 209 break; 210 } 211 212 default: 213 break; 214 } 215 done: 216 mlx5_ib_put_native_port_mdev(ibdev, port_num); 217 return NOTIFY_DONE; 218 } 219 220 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device, 221 u8 port_num) 222 { 223 struct mlx5_ib_dev *ibdev = to_mdev(device); 224 struct net_device *ndev; 225 struct mlx5_core_dev *mdev; 226 227 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 228 if (!mdev) 229 return NULL; 230 231 ndev = mlx5_lag_get_roce_netdev(mdev); 232 if (ndev) 233 goto out; 234 235 /* Ensure ndev does not disappear before we invoke dev_hold() 236 */ 237 read_lock(&ibdev->roce[port_num - 1].netdev_lock); 238 ndev = ibdev->roce[port_num - 1].netdev; 239 if (ndev) 240 dev_hold(ndev); 241 read_unlock(&ibdev->roce[port_num - 1].netdev_lock); 242 243 out: 244 mlx5_ib_put_native_port_mdev(ibdev, port_num); 245 return ndev; 246 } 247 248 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev, 249 u8 ib_port_num, 250 u8 *native_port_num) 251 { 252 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 253 ib_port_num); 254 struct mlx5_core_dev *mdev = NULL; 255 struct mlx5_ib_multiport_info *mpi; 256 struct mlx5_ib_port *port; 257 258 if (native_port_num) 259 *native_port_num = 1; 260 261 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 262 return ibdev->mdev; 263 264 port = &ibdev->port[ib_port_num - 1]; 265 if (!port) 266 return NULL; 267 268 spin_lock(&port->mp.mpi_lock); 269 mpi = ibdev->port[ib_port_num - 1].mp.mpi; 270 if (mpi && !mpi->unaffiliate) { 271 mdev = mpi->mdev; 272 /* If it's the master no need to refcount, it'll exist 273 * as long as the ib_dev exists. 274 */ 275 if (!mpi->is_master) 276 mpi->mdev_refcnt++; 277 } 278 spin_unlock(&port->mp.mpi_lock); 279 280 return mdev; 281 } 282 283 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num) 284 { 285 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 286 port_num); 287 struct mlx5_ib_multiport_info *mpi; 288 struct mlx5_ib_port *port; 289 290 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 291 return; 292 293 port = &ibdev->port[port_num - 1]; 294 295 spin_lock(&port->mp.mpi_lock); 296 mpi = ibdev->port[port_num - 1].mp.mpi; 297 if (mpi->is_master) 298 goto out; 299 300 mpi->mdev_refcnt--; 301 if (mpi->unaffiliate) 302 complete(&mpi->unref_comp); 303 out: 304 spin_unlock(&port->mp.mpi_lock); 305 } 306 307 static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed, 308 u8 *active_width) 309 { 310 switch (eth_proto_oper) { 311 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII): 312 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX): 313 case MLX5E_PROT_MASK(MLX5E_100BASE_TX): 314 case MLX5E_PROT_MASK(MLX5E_1000BASE_T): 315 *active_width = IB_WIDTH_1X; 316 *active_speed = IB_SPEED_SDR; 317 break; 318 case MLX5E_PROT_MASK(MLX5E_10GBASE_T): 319 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4): 320 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4): 321 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR): 322 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR): 323 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR): 324 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER): 325 *active_width = IB_WIDTH_1X; 326 *active_speed = IB_SPEED_QDR; 327 break; 328 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR): 329 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR): 330 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR): 331 *active_width = IB_WIDTH_1X; 332 *active_speed = IB_SPEED_EDR; 333 break; 334 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4): 335 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4): 336 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4): 337 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4): 338 *active_width = IB_WIDTH_4X; 339 *active_speed = IB_SPEED_QDR; 340 break; 341 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2): 342 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2): 343 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2): 344 *active_width = IB_WIDTH_1X; 345 *active_speed = IB_SPEED_HDR; 346 break; 347 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4): 348 *active_width = IB_WIDTH_4X; 349 *active_speed = IB_SPEED_FDR; 350 break; 351 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4): 352 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4): 353 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4): 354 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4): 355 *active_width = IB_WIDTH_4X; 356 *active_speed = IB_SPEED_EDR; 357 break; 358 default: 359 return -EINVAL; 360 } 361 362 return 0; 363 } 364 365 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num, 366 struct ib_port_attr *props) 367 { 368 struct mlx5_ib_dev *dev = to_mdev(device); 369 struct mlx5_core_dev *mdev; 370 struct net_device *ndev, *upper; 371 enum ib_mtu ndev_ib_mtu; 372 bool put_mdev = true; 373 u16 qkey_viol_cntr; 374 u32 eth_prot_oper; 375 u8 mdev_port_num; 376 int err; 377 378 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 379 if (!mdev) { 380 /* This means the port isn't affiliated yet. Get the 381 * info for the master port instead. 382 */ 383 put_mdev = false; 384 mdev = dev->mdev; 385 mdev_port_num = 1; 386 port_num = 1; 387 } 388 389 /* Possible bad flows are checked before filling out props so in case 390 * of an error it will still be zeroed out. 391 */ 392 err = mlx5_query_port_eth_proto_oper(mdev, ð_prot_oper, 393 mdev_port_num); 394 if (err) 395 goto out; 396 397 translate_eth_proto_oper(eth_prot_oper, &props->active_speed, 398 &props->active_width); 399 400 props->port_cap_flags |= IB_PORT_CM_SUP; 401 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS; 402 403 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 404 roce_address_table_size); 405 props->max_mtu = IB_MTU_4096; 406 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 407 props->pkey_tbl_len = 1; 408 props->state = IB_PORT_DOWN; 409 props->phys_state = 3; 410 411 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr); 412 props->qkey_viol_cntr = qkey_viol_cntr; 413 414 /* If this is a stub query for an unaffiliated port stop here */ 415 if (!put_mdev) 416 goto out; 417 418 ndev = mlx5_ib_get_netdev(device, port_num); 419 if (!ndev) 420 goto out; 421 422 if (mlx5_lag_is_active(dev->mdev)) { 423 rcu_read_lock(); 424 upper = netdev_master_upper_dev_get_rcu(ndev); 425 if (upper) { 426 dev_put(ndev); 427 ndev = upper; 428 dev_hold(ndev); 429 } 430 rcu_read_unlock(); 431 } 432 433 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 434 props->state = IB_PORT_ACTIVE; 435 props->phys_state = 5; 436 } 437 438 ndev_ib_mtu = iboe_get_mtu(ndev->mtu); 439 440 dev_put(ndev); 441 442 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 443 out: 444 if (put_mdev) 445 mlx5_ib_put_native_port_mdev(dev, port_num); 446 return err; 447 } 448 449 static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num, 450 unsigned int index, const union ib_gid *gid, 451 const struct ib_gid_attr *attr) 452 { 453 enum ib_gid_type gid_type = IB_GID_TYPE_IB; 454 u8 roce_version = 0; 455 u8 roce_l3_type = 0; 456 bool vlan = false; 457 u8 mac[ETH_ALEN]; 458 u16 vlan_id = 0; 459 460 if (gid) { 461 gid_type = attr->gid_type; 462 ether_addr_copy(mac, attr->ndev->dev_addr); 463 464 if (is_vlan_dev(attr->ndev)) { 465 vlan = true; 466 vlan_id = vlan_dev_vlan_id(attr->ndev); 467 } 468 } 469 470 switch (gid_type) { 471 case IB_GID_TYPE_IB: 472 roce_version = MLX5_ROCE_VERSION_1; 473 break; 474 case IB_GID_TYPE_ROCE_UDP_ENCAP: 475 roce_version = MLX5_ROCE_VERSION_2; 476 if (ipv6_addr_v4mapped((void *)gid)) 477 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4; 478 else 479 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6; 480 break; 481 482 default: 483 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type); 484 } 485 486 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version, 487 roce_l3_type, gid->raw, mac, vlan, 488 vlan_id, port_num); 489 } 490 491 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num, 492 unsigned int index, const union ib_gid *gid, 493 const struct ib_gid_attr *attr, 494 __always_unused void **context) 495 { 496 return set_roce_addr(to_mdev(device), port_num, index, gid, attr); 497 } 498 499 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num, 500 unsigned int index, __always_unused void **context) 501 { 502 return set_roce_addr(to_mdev(device), port_num, index, NULL, NULL); 503 } 504 505 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num, 506 int index) 507 { 508 struct ib_gid_attr attr; 509 union ib_gid gid; 510 511 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr)) 512 return 0; 513 514 if (!attr.ndev) 515 return 0; 516 517 dev_put(attr.ndev); 518 519 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 520 return 0; 521 522 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 523 } 524 525 int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num, 526 int index, enum ib_gid_type *gid_type) 527 { 528 struct ib_gid_attr attr; 529 union ib_gid gid; 530 int ret; 531 532 ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr); 533 if (ret) 534 return ret; 535 536 if (!attr.ndev) 537 return -ENODEV; 538 539 dev_put(attr.ndev); 540 541 *gid_type = attr.gid_type; 542 543 return 0; 544 } 545 546 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 547 { 548 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 549 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 550 return 0; 551 } 552 553 enum { 554 MLX5_VPORT_ACCESS_METHOD_MAD, 555 MLX5_VPORT_ACCESS_METHOD_HCA, 556 MLX5_VPORT_ACCESS_METHOD_NIC, 557 }; 558 559 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 560 { 561 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 562 return MLX5_VPORT_ACCESS_METHOD_MAD; 563 564 if (mlx5_ib_port_link_layer(ibdev, 1) == 565 IB_LINK_LAYER_ETHERNET) 566 return MLX5_VPORT_ACCESS_METHOD_NIC; 567 568 return MLX5_VPORT_ACCESS_METHOD_HCA; 569 } 570 571 static void get_atomic_caps(struct mlx5_ib_dev *dev, 572 u8 atomic_size_qp, 573 struct ib_device_attr *props) 574 { 575 u8 tmp; 576 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 577 u8 atomic_req_8B_endianness_mode = 578 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode); 579 580 /* Check if HW supports 8 bytes standard atomic operations and capable 581 * of host endianness respond 582 */ 583 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 584 if (((atomic_operations & tmp) == tmp) && 585 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 586 (atomic_req_8B_endianness_mode)) { 587 props->atomic_cap = IB_ATOMIC_HCA; 588 } else { 589 props->atomic_cap = IB_ATOMIC_NONE; 590 } 591 } 592 593 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev, 594 struct ib_device_attr *props) 595 { 596 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 597 598 get_atomic_caps(dev, atomic_size_qp, props); 599 } 600 601 static void get_atomic_caps_dc(struct mlx5_ib_dev *dev, 602 struct ib_device_attr *props) 603 { 604 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc); 605 606 get_atomic_caps(dev, atomic_size_qp, props); 607 } 608 609 bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev) 610 { 611 struct ib_device_attr props = {}; 612 613 get_atomic_caps_dc(dev, &props); 614 return (props.atomic_cap == IB_ATOMIC_HCA) ? true : false; 615 } 616 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 617 __be64 *sys_image_guid) 618 { 619 struct mlx5_ib_dev *dev = to_mdev(ibdev); 620 struct mlx5_core_dev *mdev = dev->mdev; 621 u64 tmp; 622 int err; 623 624 switch (mlx5_get_vport_access_method(ibdev)) { 625 case MLX5_VPORT_ACCESS_METHOD_MAD: 626 return mlx5_query_mad_ifc_system_image_guid(ibdev, 627 sys_image_guid); 628 629 case MLX5_VPORT_ACCESS_METHOD_HCA: 630 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 631 break; 632 633 case MLX5_VPORT_ACCESS_METHOD_NIC: 634 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 635 break; 636 637 default: 638 return -EINVAL; 639 } 640 641 if (!err) 642 *sys_image_guid = cpu_to_be64(tmp); 643 644 return err; 645 646 } 647 648 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 649 u16 *max_pkeys) 650 { 651 struct mlx5_ib_dev *dev = to_mdev(ibdev); 652 struct mlx5_core_dev *mdev = dev->mdev; 653 654 switch (mlx5_get_vport_access_method(ibdev)) { 655 case MLX5_VPORT_ACCESS_METHOD_MAD: 656 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 657 658 case MLX5_VPORT_ACCESS_METHOD_HCA: 659 case MLX5_VPORT_ACCESS_METHOD_NIC: 660 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 661 pkey_table_size)); 662 return 0; 663 664 default: 665 return -EINVAL; 666 } 667 } 668 669 static int mlx5_query_vendor_id(struct ib_device *ibdev, 670 u32 *vendor_id) 671 { 672 struct mlx5_ib_dev *dev = to_mdev(ibdev); 673 674 switch (mlx5_get_vport_access_method(ibdev)) { 675 case MLX5_VPORT_ACCESS_METHOD_MAD: 676 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 677 678 case MLX5_VPORT_ACCESS_METHOD_HCA: 679 case MLX5_VPORT_ACCESS_METHOD_NIC: 680 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 681 682 default: 683 return -EINVAL; 684 } 685 } 686 687 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 688 __be64 *node_guid) 689 { 690 u64 tmp; 691 int err; 692 693 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 694 case MLX5_VPORT_ACCESS_METHOD_MAD: 695 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 696 697 case MLX5_VPORT_ACCESS_METHOD_HCA: 698 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 699 break; 700 701 case MLX5_VPORT_ACCESS_METHOD_NIC: 702 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 703 break; 704 705 default: 706 return -EINVAL; 707 } 708 709 if (!err) 710 *node_guid = cpu_to_be64(tmp); 711 712 return err; 713 } 714 715 struct mlx5_reg_node_desc { 716 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 717 }; 718 719 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 720 { 721 struct mlx5_reg_node_desc in; 722 723 if (mlx5_use_mad_ifc(dev)) 724 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 725 726 memset(&in, 0, sizeof(in)); 727 728 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 729 sizeof(struct mlx5_reg_node_desc), 730 MLX5_REG_NODE_DESC, 0, 0); 731 } 732 733 static int mlx5_ib_query_device(struct ib_device *ibdev, 734 struct ib_device_attr *props, 735 struct ib_udata *uhw) 736 { 737 struct mlx5_ib_dev *dev = to_mdev(ibdev); 738 struct mlx5_core_dev *mdev = dev->mdev; 739 int err = -ENOMEM; 740 int max_sq_desc; 741 int max_rq_sg; 742 int max_sq_sg; 743 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 744 bool raw_support = !mlx5_core_mp_enabled(mdev); 745 struct mlx5_ib_query_device_resp resp = {}; 746 size_t resp_len; 747 u64 max_tso; 748 749 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 750 if (uhw->outlen && uhw->outlen < resp_len) 751 return -EINVAL; 752 else 753 resp.response_length = resp_len; 754 755 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) 756 return -EINVAL; 757 758 memset(props, 0, sizeof(*props)); 759 err = mlx5_query_system_image_guid(ibdev, 760 &props->sys_image_guid); 761 if (err) 762 return err; 763 764 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys); 765 if (err) 766 return err; 767 768 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 769 if (err) 770 return err; 771 772 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 773 (fw_rev_min(dev->mdev) << 16) | 774 fw_rev_sub(dev->mdev); 775 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 776 IB_DEVICE_PORT_ACTIVE_EVENT | 777 IB_DEVICE_SYS_IMAGE_GUID | 778 IB_DEVICE_RC_RNR_NAK_GEN; 779 780 if (MLX5_CAP_GEN(mdev, pkv)) 781 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 782 if (MLX5_CAP_GEN(mdev, qkv)) 783 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 784 if (MLX5_CAP_GEN(mdev, apm)) 785 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 786 if (MLX5_CAP_GEN(mdev, xrc)) 787 props->device_cap_flags |= IB_DEVICE_XRC; 788 if (MLX5_CAP_GEN(mdev, imaicl)) { 789 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 790 IB_DEVICE_MEM_WINDOW_TYPE_2B; 791 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 792 /* We support 'Gappy' memory registration too */ 793 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG; 794 } 795 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 796 if (MLX5_CAP_GEN(mdev, sho)) { 797 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER; 798 /* At this stage no support for signature handover */ 799 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 800 IB_PROT_T10DIF_TYPE_2 | 801 IB_PROT_T10DIF_TYPE_3; 802 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 803 IB_GUARD_T10DIF_CSUM; 804 } 805 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 806 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 807 808 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) { 809 if (MLX5_CAP_ETH(mdev, csum_cap)) { 810 /* Legacy bit to support old userspace libraries */ 811 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 812 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM; 813 } 814 815 if (MLX5_CAP_ETH(dev->mdev, vlan_cap)) 816 props->raw_packet_caps |= 817 IB_RAW_PACKET_CAP_CVLAN_STRIPPING; 818 819 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) { 820 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 821 if (max_tso) { 822 resp.tso_caps.max_tso = 1 << max_tso; 823 resp.tso_caps.supported_qpts |= 824 1 << IB_QPT_RAW_PACKET; 825 resp.response_length += sizeof(resp.tso_caps); 826 } 827 } 828 829 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) { 830 resp.rss_caps.rx_hash_function = 831 MLX5_RX_HASH_FUNC_TOEPLITZ; 832 resp.rss_caps.rx_hash_fields_mask = 833 MLX5_RX_HASH_SRC_IPV4 | 834 MLX5_RX_HASH_DST_IPV4 | 835 MLX5_RX_HASH_SRC_IPV6 | 836 MLX5_RX_HASH_DST_IPV6 | 837 MLX5_RX_HASH_SRC_PORT_TCP | 838 MLX5_RX_HASH_DST_PORT_TCP | 839 MLX5_RX_HASH_SRC_PORT_UDP | 840 MLX5_RX_HASH_DST_PORT_UDP | 841 MLX5_RX_HASH_INNER; 842 resp.response_length += sizeof(resp.rss_caps); 843 } 844 } else { 845 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) 846 resp.response_length += sizeof(resp.tso_caps); 847 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) 848 resp.response_length += sizeof(resp.rss_caps); 849 } 850 851 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 852 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 853 props->device_cap_flags |= IB_DEVICE_UD_TSO; 854 } 855 856 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) && 857 MLX5_CAP_GEN(dev->mdev, general_notification_event) && 858 raw_support) 859 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP; 860 861 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 862 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap)) 863 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 864 865 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 866 MLX5_CAP_ETH(dev->mdev, scatter_fcs) && 867 raw_support) { 868 /* Legacy bit to support old userspace libraries */ 869 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 870 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; 871 } 872 873 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 874 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 875 876 if (MLX5_CAP_GEN(mdev, end_pad)) 877 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING; 878 879 props->vendor_part_id = mdev->pdev->device; 880 props->hw_ver = mdev->pdev->revision; 881 882 props->max_mr_size = ~0ull; 883 props->page_size_cap = ~(min_page_size - 1); 884 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 885 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 886 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 887 sizeof(struct mlx5_wqe_data_seg); 888 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512); 889 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) - 890 sizeof(struct mlx5_wqe_raddr_seg)) / 891 sizeof(struct mlx5_wqe_data_seg); 892 props->max_sge = min(max_rq_sg, max_sq_sg); 893 props->max_sge_rd = MLX5_MAX_SGE_RD; 894 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 895 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 896 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 897 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 898 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 899 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 900 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 901 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 902 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 903 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 904 props->max_srq_sge = max_rq_sg - 1; 905 props->max_fast_reg_page_list_len = 906 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 907 get_atomic_caps_qp(dev, props); 908 props->masked_atomic_cap = IB_ATOMIC_NONE; 909 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 910 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 911 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 912 props->max_mcast_grp; 913 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */ 914 props->max_ah = INT_MAX; 915 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 916 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 917 918 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 919 if (MLX5_CAP_GEN(mdev, pg)) 920 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING; 921 props->odp_caps = dev->odp_caps; 922 #endif 923 924 if (MLX5_CAP_GEN(mdev, cd)) 925 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL; 926 927 if (!mlx5_core_is_pf(mdev)) 928 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION; 929 930 if (mlx5_ib_port_link_layer(ibdev, 1) == 931 IB_LINK_LAYER_ETHERNET && raw_support) { 932 props->rss_caps.max_rwq_indirection_tables = 933 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 934 props->rss_caps.max_rwq_indirection_table_size = 935 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 936 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 937 props->max_wq_type_rq = 938 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 939 } 940 941 if (MLX5_CAP_GEN(mdev, tag_matching)) { 942 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE; 943 props->tm_caps.max_num_tags = 944 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1; 945 props->tm_caps.flags = IB_TM_CAP_RC; 946 props->tm_caps.max_ops = 947 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 948 props->tm_caps.max_sge = MLX5_TM_MAX_SGE; 949 } 950 951 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) { 952 props->cq_caps.max_cq_moderation_count = 953 MLX5_MAX_CQ_COUNT; 954 props->cq_caps.max_cq_moderation_period = 955 MLX5_MAX_CQ_PERIOD; 956 } 957 958 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) { 959 resp.cqe_comp_caps.max_num = 960 MLX5_CAP_GEN(dev->mdev, cqe_compression) ? 961 MLX5_CAP_GEN(dev->mdev, cqe_compression_max_num) : 0; 962 resp.cqe_comp_caps.supported_format = 963 MLX5_IB_CQE_RES_FORMAT_HASH | 964 MLX5_IB_CQE_RES_FORMAT_CSUM; 965 resp.response_length += sizeof(resp.cqe_comp_caps); 966 } 967 968 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen) && 969 raw_support) { 970 if (MLX5_CAP_QOS(mdev, packet_pacing) && 971 MLX5_CAP_GEN(mdev, qos)) { 972 resp.packet_pacing_caps.qp_rate_limit_max = 973 MLX5_CAP_QOS(mdev, packet_pacing_max_rate); 974 resp.packet_pacing_caps.qp_rate_limit_min = 975 MLX5_CAP_QOS(mdev, packet_pacing_min_rate); 976 resp.packet_pacing_caps.supported_qpts |= 977 1 << IB_QPT_RAW_PACKET; 978 } 979 resp.response_length += sizeof(resp.packet_pacing_caps); 980 } 981 982 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes, 983 uhw->outlen)) { 984 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe)) 985 resp.mlx5_ib_support_multi_pkt_send_wqes = 986 MLX5_IB_ALLOW_MPW; 987 988 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe)) 989 resp.mlx5_ib_support_multi_pkt_send_wqes |= 990 MLX5_IB_SUPPORT_EMPW; 991 992 resp.response_length += 993 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes); 994 } 995 996 if (field_avail(typeof(resp), flags, uhw->outlen)) { 997 resp.response_length += sizeof(resp.flags); 998 999 if (MLX5_CAP_GEN(mdev, cqe_compression_128)) 1000 resp.flags |= 1001 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP; 1002 1003 if (MLX5_CAP_GEN(mdev, cqe_128_always)) 1004 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD; 1005 } 1006 1007 if (field_avail(typeof(resp), sw_parsing_caps, 1008 uhw->outlen)) { 1009 resp.response_length += sizeof(resp.sw_parsing_caps); 1010 if (MLX5_CAP_ETH(mdev, swp)) { 1011 resp.sw_parsing_caps.sw_parsing_offloads |= 1012 MLX5_IB_SW_PARSING; 1013 1014 if (MLX5_CAP_ETH(mdev, swp_csum)) 1015 resp.sw_parsing_caps.sw_parsing_offloads |= 1016 MLX5_IB_SW_PARSING_CSUM; 1017 1018 if (MLX5_CAP_ETH(mdev, swp_lso)) 1019 resp.sw_parsing_caps.sw_parsing_offloads |= 1020 MLX5_IB_SW_PARSING_LSO; 1021 1022 if (resp.sw_parsing_caps.sw_parsing_offloads) 1023 resp.sw_parsing_caps.supported_qpts = 1024 BIT(IB_QPT_RAW_PACKET); 1025 } 1026 } 1027 1028 if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen) && 1029 raw_support) { 1030 resp.response_length += sizeof(resp.striding_rq_caps); 1031 if (MLX5_CAP_GEN(mdev, striding_rq)) { 1032 resp.striding_rq_caps.min_single_stride_log_num_of_bytes = 1033 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES; 1034 resp.striding_rq_caps.max_single_stride_log_num_of_bytes = 1035 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES; 1036 resp.striding_rq_caps.min_single_wqe_log_num_of_strides = 1037 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1038 resp.striding_rq_caps.max_single_wqe_log_num_of_strides = 1039 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES; 1040 resp.striding_rq_caps.supported_qpts = 1041 BIT(IB_QPT_RAW_PACKET); 1042 } 1043 } 1044 1045 if (field_avail(typeof(resp), tunnel_offloads_caps, 1046 uhw->outlen)) { 1047 resp.response_length += sizeof(resp.tunnel_offloads_caps); 1048 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan)) 1049 resp.tunnel_offloads_caps |= 1050 MLX5_IB_TUNNELED_OFFLOADS_VXLAN; 1051 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx)) 1052 resp.tunnel_offloads_caps |= 1053 MLX5_IB_TUNNELED_OFFLOADS_GENEVE; 1054 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) 1055 resp.tunnel_offloads_caps |= 1056 MLX5_IB_TUNNELED_OFFLOADS_GRE; 1057 } 1058 1059 if (uhw->outlen) { 1060 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 1061 1062 if (err) 1063 return err; 1064 } 1065 1066 return 0; 1067 } 1068 1069 enum mlx5_ib_width { 1070 MLX5_IB_WIDTH_1X = 1 << 0, 1071 MLX5_IB_WIDTH_2X = 1 << 1, 1072 MLX5_IB_WIDTH_4X = 1 << 2, 1073 MLX5_IB_WIDTH_8X = 1 << 3, 1074 MLX5_IB_WIDTH_12X = 1 << 4 1075 }; 1076 1077 static int translate_active_width(struct ib_device *ibdev, u8 active_width, 1078 u8 *ib_width) 1079 { 1080 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1081 int err = 0; 1082 1083 if (active_width & MLX5_IB_WIDTH_1X) { 1084 *ib_width = IB_WIDTH_1X; 1085 } else if (active_width & MLX5_IB_WIDTH_2X) { 1086 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n", 1087 (int)active_width); 1088 err = -EINVAL; 1089 } else if (active_width & MLX5_IB_WIDTH_4X) { 1090 *ib_width = IB_WIDTH_4X; 1091 } else if (active_width & MLX5_IB_WIDTH_8X) { 1092 *ib_width = IB_WIDTH_8X; 1093 } else if (active_width & MLX5_IB_WIDTH_12X) { 1094 *ib_width = IB_WIDTH_12X; 1095 } else { 1096 mlx5_ib_dbg(dev, "Invalid active_width %d\n", 1097 (int)active_width); 1098 err = -EINVAL; 1099 } 1100 1101 return err; 1102 } 1103 1104 static int mlx5_mtu_to_ib_mtu(int mtu) 1105 { 1106 switch (mtu) { 1107 case 256: return 1; 1108 case 512: return 2; 1109 case 1024: return 3; 1110 case 2048: return 4; 1111 case 4096: return 5; 1112 default: 1113 pr_warn("invalid mtu\n"); 1114 return -1; 1115 } 1116 } 1117 1118 enum ib_max_vl_num { 1119 __IB_MAX_VL_0 = 1, 1120 __IB_MAX_VL_0_1 = 2, 1121 __IB_MAX_VL_0_3 = 3, 1122 __IB_MAX_VL_0_7 = 4, 1123 __IB_MAX_VL_0_14 = 5, 1124 }; 1125 1126 enum mlx5_vl_hw_cap { 1127 MLX5_VL_HW_0 = 1, 1128 MLX5_VL_HW_0_1 = 2, 1129 MLX5_VL_HW_0_2 = 3, 1130 MLX5_VL_HW_0_3 = 4, 1131 MLX5_VL_HW_0_4 = 5, 1132 MLX5_VL_HW_0_5 = 6, 1133 MLX5_VL_HW_0_6 = 7, 1134 MLX5_VL_HW_0_7 = 8, 1135 MLX5_VL_HW_0_14 = 15 1136 }; 1137 1138 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 1139 u8 *max_vl_num) 1140 { 1141 switch (vl_hw_cap) { 1142 case MLX5_VL_HW_0: 1143 *max_vl_num = __IB_MAX_VL_0; 1144 break; 1145 case MLX5_VL_HW_0_1: 1146 *max_vl_num = __IB_MAX_VL_0_1; 1147 break; 1148 case MLX5_VL_HW_0_3: 1149 *max_vl_num = __IB_MAX_VL_0_3; 1150 break; 1151 case MLX5_VL_HW_0_7: 1152 *max_vl_num = __IB_MAX_VL_0_7; 1153 break; 1154 case MLX5_VL_HW_0_14: 1155 *max_vl_num = __IB_MAX_VL_0_14; 1156 break; 1157 1158 default: 1159 return -EINVAL; 1160 } 1161 1162 return 0; 1163 } 1164 1165 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port, 1166 struct ib_port_attr *props) 1167 { 1168 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1169 struct mlx5_core_dev *mdev = dev->mdev; 1170 struct mlx5_hca_vport_context *rep; 1171 u16 max_mtu; 1172 u16 oper_mtu; 1173 int err; 1174 u8 ib_link_width_oper; 1175 u8 vl_hw_cap; 1176 1177 rep = kzalloc(sizeof(*rep), GFP_KERNEL); 1178 if (!rep) { 1179 err = -ENOMEM; 1180 goto out; 1181 } 1182 1183 /* props being zeroed by the caller, avoid zeroing it here */ 1184 1185 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); 1186 if (err) 1187 goto out; 1188 1189 props->lid = rep->lid; 1190 props->lmc = rep->lmc; 1191 props->sm_lid = rep->sm_lid; 1192 props->sm_sl = rep->sm_sl; 1193 props->state = rep->vport_state; 1194 props->phys_state = rep->port_physical_state; 1195 props->port_cap_flags = rep->cap_mask1; 1196 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 1197 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 1198 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 1199 props->bad_pkey_cntr = rep->pkey_violation_counter; 1200 props->qkey_viol_cntr = rep->qkey_violation_counter; 1201 props->subnet_timeout = rep->subnet_timeout; 1202 props->init_type_reply = rep->init_type_reply; 1203 props->grh_required = rep->grh_required; 1204 1205 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port); 1206 if (err) 1207 goto out; 1208 1209 err = translate_active_width(ibdev, ib_link_width_oper, 1210 &props->active_width); 1211 if (err) 1212 goto out; 1213 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port); 1214 if (err) 1215 goto out; 1216 1217 mlx5_query_port_max_mtu(mdev, &max_mtu, port); 1218 1219 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); 1220 1221 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); 1222 1223 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); 1224 1225 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); 1226 if (err) 1227 goto out; 1228 1229 err = translate_max_vl_num(ibdev, vl_hw_cap, 1230 &props->max_vl_num); 1231 out: 1232 kfree(rep); 1233 return err; 1234 } 1235 1236 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 1237 struct ib_port_attr *props) 1238 { 1239 unsigned int count; 1240 int ret; 1241 1242 switch (mlx5_get_vport_access_method(ibdev)) { 1243 case MLX5_VPORT_ACCESS_METHOD_MAD: 1244 ret = mlx5_query_mad_ifc_port(ibdev, port, props); 1245 break; 1246 1247 case MLX5_VPORT_ACCESS_METHOD_HCA: 1248 ret = mlx5_query_hca_port(ibdev, port, props); 1249 break; 1250 1251 case MLX5_VPORT_ACCESS_METHOD_NIC: 1252 ret = mlx5_query_port_roce(ibdev, port, props); 1253 break; 1254 1255 default: 1256 ret = -EINVAL; 1257 } 1258 1259 if (!ret && props) { 1260 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1261 struct mlx5_core_dev *mdev; 1262 bool put_mdev = true; 1263 1264 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL); 1265 if (!mdev) { 1266 /* If the port isn't affiliated yet query the master. 1267 * The master and slave will have the same values. 1268 */ 1269 mdev = dev->mdev; 1270 port = 1; 1271 put_mdev = false; 1272 } 1273 count = mlx5_core_reserved_gids_count(mdev); 1274 if (put_mdev) 1275 mlx5_ib_put_native_port_mdev(dev, port); 1276 props->gid_tbl_len -= count; 1277 } 1278 return ret; 1279 } 1280 1281 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port, 1282 struct ib_port_attr *props) 1283 { 1284 int ret; 1285 1286 /* Only link layer == ethernet is valid for representors */ 1287 ret = mlx5_query_port_roce(ibdev, port, props); 1288 if (ret || !props) 1289 return ret; 1290 1291 /* We don't support GIDS */ 1292 props->gid_tbl_len = 0; 1293 1294 return ret; 1295 } 1296 1297 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 1298 union ib_gid *gid) 1299 { 1300 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1301 struct mlx5_core_dev *mdev = dev->mdev; 1302 1303 switch (mlx5_get_vport_access_method(ibdev)) { 1304 case MLX5_VPORT_ACCESS_METHOD_MAD: 1305 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 1306 1307 case MLX5_VPORT_ACCESS_METHOD_HCA: 1308 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); 1309 1310 default: 1311 return -EINVAL; 1312 } 1313 1314 } 1315 1316 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port, 1317 u16 index, u16 *pkey) 1318 { 1319 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1320 struct mlx5_core_dev *mdev; 1321 bool put_mdev = true; 1322 u8 mdev_port_num; 1323 int err; 1324 1325 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num); 1326 if (!mdev) { 1327 /* The port isn't affiliated yet, get the PKey from the master 1328 * port. For RoCE the PKey tables will be the same. 1329 */ 1330 put_mdev = false; 1331 mdev = dev->mdev; 1332 mdev_port_num = 1; 1333 } 1334 1335 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0, 1336 index, pkey); 1337 if (put_mdev) 1338 mlx5_ib_put_native_port_mdev(dev, port); 1339 1340 return err; 1341 } 1342 1343 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 1344 u16 *pkey) 1345 { 1346 switch (mlx5_get_vport_access_method(ibdev)) { 1347 case MLX5_VPORT_ACCESS_METHOD_MAD: 1348 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 1349 1350 case MLX5_VPORT_ACCESS_METHOD_HCA: 1351 case MLX5_VPORT_ACCESS_METHOD_NIC: 1352 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey); 1353 default: 1354 return -EINVAL; 1355 } 1356 } 1357 1358 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 1359 struct ib_device_modify *props) 1360 { 1361 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1362 struct mlx5_reg_node_desc in; 1363 struct mlx5_reg_node_desc out; 1364 int err; 1365 1366 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 1367 return -EOPNOTSUPP; 1368 1369 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 1370 return 0; 1371 1372 /* 1373 * If possible, pass node desc to FW, so it can generate 1374 * a 144 trap. If cmd fails, just ignore. 1375 */ 1376 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1377 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 1378 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 1379 if (err) 1380 return err; 1381 1382 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1383 1384 return err; 1385 } 1386 1387 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask, 1388 u32 value) 1389 { 1390 struct mlx5_hca_vport_context ctx = {}; 1391 struct mlx5_core_dev *mdev; 1392 u8 mdev_port_num; 1393 int err; 1394 1395 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 1396 if (!mdev) 1397 return -ENODEV; 1398 1399 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx); 1400 if (err) 1401 goto out; 1402 1403 if (~ctx.cap_mask1_perm & mask) { 1404 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n", 1405 mask, ctx.cap_mask1_perm); 1406 err = -EINVAL; 1407 goto out; 1408 } 1409 1410 ctx.cap_mask1 = value; 1411 ctx.cap_mask1_perm = mask; 1412 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num, 1413 0, &ctx); 1414 1415 out: 1416 mlx5_ib_put_native_port_mdev(dev, port_num); 1417 1418 return err; 1419 } 1420 1421 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, 1422 struct ib_port_modify *props) 1423 { 1424 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1425 struct ib_port_attr attr; 1426 u32 tmp; 1427 int err; 1428 u32 change_mask; 1429 u32 value; 1430 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) == 1431 IB_LINK_LAYER_INFINIBAND); 1432 1433 /* CM layer calls ib_modify_port() regardless of the link layer. For 1434 * Ethernet ports, qkey violation and Port capabilities are meaningless. 1435 */ 1436 if (!is_ib) 1437 return 0; 1438 1439 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) { 1440 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask; 1441 value = ~props->clr_port_cap_mask | props->set_port_cap_mask; 1442 return set_port_caps_atomic(dev, port, change_mask, value); 1443 } 1444 1445 mutex_lock(&dev->cap_mask_mutex); 1446 1447 err = ib_query_port(ibdev, port, &attr); 1448 if (err) 1449 goto out; 1450 1451 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 1452 ~props->clr_port_cap_mask; 1453 1454 err = mlx5_set_port_caps(dev->mdev, port, tmp); 1455 1456 out: 1457 mutex_unlock(&dev->cap_mask_mutex); 1458 return err; 1459 } 1460 1461 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps) 1462 { 1463 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n", 1464 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n"); 1465 } 1466 1467 static u16 calc_dynamic_bfregs(int uars_per_sys_page) 1468 { 1469 /* Large page with non 4k uar support might limit the dynamic size */ 1470 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096) 1471 return MLX5_MIN_DYN_BFREGS; 1472 1473 return MLX5_MAX_DYN_BFREGS; 1474 } 1475 1476 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k, 1477 struct mlx5_ib_alloc_ucontext_req_v2 *req, 1478 struct mlx5_bfreg_info *bfregi) 1479 { 1480 int uars_per_sys_page; 1481 int bfregs_per_sys_page; 1482 int ref_bfregs = req->total_num_bfregs; 1483 1484 if (req->total_num_bfregs == 0) 1485 return -EINVAL; 1486 1487 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE); 1488 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE); 1489 1490 if (req->total_num_bfregs > MLX5_MAX_BFREGS) 1491 return -ENOMEM; 1492 1493 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k); 1494 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR; 1495 /* This holds the required static allocation asked by the user */ 1496 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page); 1497 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1) 1498 return -EINVAL; 1499 1500 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page; 1501 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page); 1502 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs; 1503 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page; 1504 1505 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n", 1506 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no", 1507 lib_uar_4k ? "yes" : "no", ref_bfregs, 1508 req->total_num_bfregs, bfregi->total_num_bfregs, 1509 bfregi->num_sys_pages); 1510 1511 return 0; 1512 } 1513 1514 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1515 { 1516 struct mlx5_bfreg_info *bfregi; 1517 int err; 1518 int i; 1519 1520 bfregi = &context->bfregi; 1521 for (i = 0; i < bfregi->num_static_sys_pages; i++) { 1522 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]); 1523 if (err) 1524 goto error; 1525 1526 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]); 1527 } 1528 1529 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++) 1530 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX; 1531 1532 return 0; 1533 1534 error: 1535 for (--i; i >= 0; i--) 1536 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i])) 1537 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1538 1539 return err; 1540 } 1541 1542 static int deallocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1543 { 1544 struct mlx5_bfreg_info *bfregi; 1545 int err; 1546 int i; 1547 1548 bfregi = &context->bfregi; 1549 for (i = 0; i < bfregi->num_sys_pages; i++) { 1550 if (i < bfregi->num_static_sys_pages || 1551 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) { 1552 err = mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]); 1553 if (err) { 1554 mlx5_ib_warn(dev, "failed to free uar %d, err=%d\n", i, err); 1555 return err; 1556 } 1557 } 1558 } 1559 1560 return 0; 1561 } 1562 1563 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn) 1564 { 1565 int err; 1566 1567 err = mlx5_core_alloc_transport_domain(dev->mdev, tdn); 1568 if (err) 1569 return err; 1570 1571 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1572 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1573 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1574 return err; 1575 1576 mutex_lock(&dev->lb_mutex); 1577 dev->user_td++; 1578 1579 if (dev->user_td == 2) 1580 err = mlx5_nic_vport_update_local_lb(dev->mdev, true); 1581 1582 mutex_unlock(&dev->lb_mutex); 1583 return err; 1584 } 1585 1586 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn) 1587 { 1588 mlx5_core_dealloc_transport_domain(dev->mdev, tdn); 1589 1590 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1591 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1592 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1593 return; 1594 1595 mutex_lock(&dev->lb_mutex); 1596 dev->user_td--; 1597 1598 if (dev->user_td < 2) 1599 mlx5_nic_vport_update_local_lb(dev->mdev, false); 1600 1601 mutex_unlock(&dev->lb_mutex); 1602 } 1603 1604 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev, 1605 struct ib_udata *udata) 1606 { 1607 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1608 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 1609 struct mlx5_ib_alloc_ucontext_resp resp = {}; 1610 struct mlx5_core_dev *mdev = dev->mdev; 1611 struct mlx5_ib_ucontext *context; 1612 struct mlx5_bfreg_info *bfregi; 1613 int ver; 1614 int err; 1615 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 1616 max_cqe_version); 1617 bool lib_uar_4k; 1618 1619 if (!dev->ib_active) 1620 return ERR_PTR(-EAGAIN); 1621 1622 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 1623 ver = 0; 1624 else if (udata->inlen >= min_req_v2) 1625 ver = 2; 1626 else 1627 return ERR_PTR(-EINVAL); 1628 1629 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req))); 1630 if (err) 1631 return ERR_PTR(err); 1632 1633 if (req.flags) 1634 return ERR_PTR(-EINVAL); 1635 1636 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 1637 return ERR_PTR(-EOPNOTSUPP); 1638 1639 req.total_num_bfregs = ALIGN(req.total_num_bfregs, 1640 MLX5_NON_FP_BFREGS_PER_UAR); 1641 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1) 1642 return ERR_PTR(-EINVAL); 1643 1644 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 1645 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf)) 1646 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size); 1647 resp.cache_line_size = cache_line_size(); 1648 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 1649 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 1650 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1651 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1652 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 1653 resp.cqe_version = min_t(__u8, 1654 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 1655 req.max_cqe_version); 1656 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1657 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT; 1658 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1659 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1; 1660 resp.response_length = min(offsetof(typeof(resp), response_length) + 1661 sizeof(resp.response_length), udata->outlen); 1662 1663 context = kzalloc(sizeof(*context), GFP_KERNEL); 1664 if (!context) 1665 return ERR_PTR(-ENOMEM); 1666 1667 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR; 1668 bfregi = &context->bfregi; 1669 1670 /* updates req->total_num_bfregs */ 1671 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi); 1672 if (err) 1673 goto out_ctx; 1674 1675 mutex_init(&bfregi->lock); 1676 bfregi->lib_uar_4k = lib_uar_4k; 1677 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count), 1678 GFP_KERNEL); 1679 if (!bfregi->count) { 1680 err = -ENOMEM; 1681 goto out_ctx; 1682 } 1683 1684 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages, 1685 sizeof(*bfregi->sys_pages), 1686 GFP_KERNEL); 1687 if (!bfregi->sys_pages) { 1688 err = -ENOMEM; 1689 goto out_count; 1690 } 1691 1692 err = allocate_uars(dev, context); 1693 if (err) 1694 goto out_sys_pages; 1695 1696 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1697 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range; 1698 #endif 1699 1700 context->upd_xlt_page = __get_free_page(GFP_KERNEL); 1701 if (!context->upd_xlt_page) { 1702 err = -ENOMEM; 1703 goto out_uars; 1704 } 1705 mutex_init(&context->upd_xlt_page_mutex); 1706 1707 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) { 1708 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn); 1709 if (err) 1710 goto out_page; 1711 } 1712 1713 INIT_LIST_HEAD(&context->vma_private_list); 1714 mutex_init(&context->vma_private_list_mutex); 1715 INIT_LIST_HEAD(&context->db_page_list); 1716 mutex_init(&context->db_page_mutex); 1717 1718 resp.tot_bfregs = req.total_num_bfregs; 1719 resp.num_ports = dev->num_ports; 1720 1721 if (field_avail(typeof(resp), cqe_version, udata->outlen)) 1722 resp.response_length += sizeof(resp.cqe_version); 1723 1724 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) { 1725 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 1726 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 1727 resp.response_length += sizeof(resp.cmds_supp_uhw); 1728 } 1729 1730 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) { 1731 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) { 1732 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline); 1733 resp.eth_min_inline++; 1734 } 1735 resp.response_length += sizeof(resp.eth_min_inline); 1736 } 1737 1738 if (field_avail(typeof(resp), clock_info_versions, udata->outlen)) { 1739 if (mdev->clock_info) 1740 resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1); 1741 resp.response_length += sizeof(resp.clock_info_versions); 1742 } 1743 1744 /* 1745 * We don't want to expose information from the PCI bar that is located 1746 * after 4096 bytes, so if the arch only supports larger pages, let's 1747 * pretend we don't support reading the HCA's core clock. This is also 1748 * forced by mmap function. 1749 */ 1750 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) { 1751 if (PAGE_SIZE <= 4096) { 1752 resp.comp_mask |= 1753 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 1754 resp.hca_core_clock_offset = 1755 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE; 1756 } 1757 resp.response_length += sizeof(resp.hca_core_clock_offset); 1758 } 1759 1760 if (field_avail(typeof(resp), log_uar_size, udata->outlen)) 1761 resp.response_length += sizeof(resp.log_uar_size); 1762 1763 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen)) 1764 resp.response_length += sizeof(resp.num_uars_per_page); 1765 1766 if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) { 1767 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs; 1768 resp.response_length += sizeof(resp.num_dyn_bfregs); 1769 } 1770 1771 err = ib_copy_to_udata(udata, &resp, resp.response_length); 1772 if (err) 1773 goto out_td; 1774 1775 bfregi->ver = ver; 1776 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs; 1777 context->cqe_version = resp.cqe_version; 1778 context->lib_caps = req.lib_caps; 1779 print_lib_caps(dev, context->lib_caps); 1780 1781 return &context->ibucontext; 1782 1783 out_td: 1784 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1785 mlx5_ib_dealloc_transport_domain(dev, context->tdn); 1786 1787 out_page: 1788 free_page(context->upd_xlt_page); 1789 1790 out_uars: 1791 deallocate_uars(dev, context); 1792 1793 out_sys_pages: 1794 kfree(bfregi->sys_pages); 1795 1796 out_count: 1797 kfree(bfregi->count); 1798 1799 out_ctx: 1800 kfree(context); 1801 1802 return ERR_PTR(err); 1803 } 1804 1805 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1806 { 1807 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1808 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1809 struct mlx5_bfreg_info *bfregi; 1810 1811 bfregi = &context->bfregi; 1812 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1813 mlx5_ib_dealloc_transport_domain(dev, context->tdn); 1814 1815 free_page(context->upd_xlt_page); 1816 deallocate_uars(dev, context); 1817 kfree(bfregi->sys_pages); 1818 kfree(bfregi->count); 1819 kfree(context); 1820 1821 return 0; 1822 } 1823 1824 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, 1825 int uar_idx) 1826 { 1827 int fw_uars_per_page; 1828 1829 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1; 1830 1831 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + uar_idx / fw_uars_per_page; 1832 } 1833 1834 static int get_command(unsigned long offset) 1835 { 1836 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 1837 } 1838 1839 static int get_arg(unsigned long offset) 1840 { 1841 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 1842 } 1843 1844 static int get_index(unsigned long offset) 1845 { 1846 return get_arg(offset); 1847 } 1848 1849 /* Index resides in an extra byte to enable larger values than 255 */ 1850 static int get_extended_index(unsigned long offset) 1851 { 1852 return get_arg(offset) | ((offset >> 16) & 0xff) << 8; 1853 } 1854 1855 static void mlx5_ib_vma_open(struct vm_area_struct *area) 1856 { 1857 /* vma_open is called when a new VMA is created on top of our VMA. This 1858 * is done through either mremap flow or split_vma (usually due to 1859 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA, 1860 * as this VMA is strongly hardware related. Therefore we set the 1861 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from 1862 * calling us again and trying to do incorrect actions. We assume that 1863 * the original VMA size is exactly a single page, and therefore all 1864 * "splitting" operation will not happen to it. 1865 */ 1866 area->vm_ops = NULL; 1867 } 1868 1869 static void mlx5_ib_vma_close(struct vm_area_struct *area) 1870 { 1871 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data; 1872 1873 /* It's guaranteed that all VMAs opened on a FD are closed before the 1874 * file itself is closed, therefore no sync is needed with the regular 1875 * closing flow. (e.g. mlx5 ib_dealloc_ucontext) 1876 * However need a sync with accessing the vma as part of 1877 * mlx5_ib_disassociate_ucontext. 1878 * The close operation is usually called under mm->mmap_sem except when 1879 * process is exiting. 1880 * The exiting case is handled explicitly as part of 1881 * mlx5_ib_disassociate_ucontext. 1882 */ 1883 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data; 1884 1885 /* setting the vma context pointer to null in the mlx5_ib driver's 1886 * private data, to protect a race condition in 1887 * mlx5_ib_disassociate_ucontext(). 1888 */ 1889 mlx5_ib_vma_priv_data->vma = NULL; 1890 mutex_lock(mlx5_ib_vma_priv_data->vma_private_list_mutex); 1891 list_del(&mlx5_ib_vma_priv_data->list); 1892 mutex_unlock(mlx5_ib_vma_priv_data->vma_private_list_mutex); 1893 kfree(mlx5_ib_vma_priv_data); 1894 } 1895 1896 static const struct vm_operations_struct mlx5_ib_vm_ops = { 1897 .open = mlx5_ib_vma_open, 1898 .close = mlx5_ib_vma_close 1899 }; 1900 1901 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma, 1902 struct mlx5_ib_ucontext *ctx) 1903 { 1904 struct mlx5_ib_vma_private_data *vma_prv; 1905 struct list_head *vma_head = &ctx->vma_private_list; 1906 1907 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL); 1908 if (!vma_prv) 1909 return -ENOMEM; 1910 1911 vma_prv->vma = vma; 1912 vma_prv->vma_private_list_mutex = &ctx->vma_private_list_mutex; 1913 vma->vm_private_data = vma_prv; 1914 vma->vm_ops = &mlx5_ib_vm_ops; 1915 1916 mutex_lock(&ctx->vma_private_list_mutex); 1917 list_add(&vma_prv->list, vma_head); 1918 mutex_unlock(&ctx->vma_private_list_mutex); 1919 1920 return 0; 1921 } 1922 1923 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 1924 { 1925 int ret; 1926 struct vm_area_struct *vma; 1927 struct mlx5_ib_vma_private_data *vma_private, *n; 1928 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1929 struct task_struct *owning_process = NULL; 1930 struct mm_struct *owning_mm = NULL; 1931 1932 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID); 1933 if (!owning_process) 1934 return; 1935 1936 owning_mm = get_task_mm(owning_process); 1937 if (!owning_mm) { 1938 pr_info("no mm, disassociate ucontext is pending task termination\n"); 1939 while (1) { 1940 put_task_struct(owning_process); 1941 usleep_range(1000, 2000); 1942 owning_process = get_pid_task(ibcontext->tgid, 1943 PIDTYPE_PID); 1944 if (!owning_process || 1945 owning_process->state == TASK_DEAD) { 1946 pr_info("disassociate ucontext done, task was terminated\n"); 1947 /* in case task was dead need to release the 1948 * task struct. 1949 */ 1950 if (owning_process) 1951 put_task_struct(owning_process); 1952 return; 1953 } 1954 } 1955 } 1956 1957 /* need to protect from a race on closing the vma as part of 1958 * mlx5_ib_vma_close. 1959 */ 1960 down_write(&owning_mm->mmap_sem); 1961 mutex_lock(&context->vma_private_list_mutex); 1962 list_for_each_entry_safe(vma_private, n, &context->vma_private_list, 1963 list) { 1964 vma = vma_private->vma; 1965 ret = zap_vma_ptes(vma, vma->vm_start, 1966 PAGE_SIZE); 1967 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__); 1968 /* context going to be destroyed, should 1969 * not access ops any more. 1970 */ 1971 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE); 1972 vma->vm_ops = NULL; 1973 list_del(&vma_private->list); 1974 kfree(vma_private); 1975 } 1976 mutex_unlock(&context->vma_private_list_mutex); 1977 up_write(&owning_mm->mmap_sem); 1978 mmput(owning_mm); 1979 put_task_struct(owning_process); 1980 } 1981 1982 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 1983 { 1984 switch (cmd) { 1985 case MLX5_IB_MMAP_WC_PAGE: 1986 return "WC"; 1987 case MLX5_IB_MMAP_REGULAR_PAGE: 1988 return "best effort WC"; 1989 case MLX5_IB_MMAP_NC_PAGE: 1990 return "NC"; 1991 default: 1992 return NULL; 1993 } 1994 } 1995 1996 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev, 1997 struct vm_area_struct *vma, 1998 struct mlx5_ib_ucontext *context) 1999 { 2000 phys_addr_t pfn; 2001 int err; 2002 2003 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2004 return -EINVAL; 2005 2006 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1) 2007 return -EOPNOTSUPP; 2008 2009 if (vma->vm_flags & VM_WRITE) 2010 return -EPERM; 2011 2012 if (!dev->mdev->clock_info_page) 2013 return -EOPNOTSUPP; 2014 2015 pfn = page_to_pfn(dev->mdev->clock_info_page); 2016 err = remap_pfn_range(vma, vma->vm_start, pfn, PAGE_SIZE, 2017 vma->vm_page_prot); 2018 if (err) 2019 return err; 2020 2021 mlx5_ib_dbg(dev, "mapped clock info at 0x%lx, PA 0x%llx\n", 2022 vma->vm_start, 2023 (unsigned long long)pfn << PAGE_SHIFT); 2024 2025 return mlx5_ib_set_vma_data(vma, context); 2026 } 2027 2028 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 2029 struct vm_area_struct *vma, 2030 struct mlx5_ib_ucontext *context) 2031 { 2032 struct mlx5_bfreg_info *bfregi = &context->bfregi; 2033 int err; 2034 unsigned long idx; 2035 phys_addr_t pfn, pa; 2036 pgprot_t prot; 2037 u32 bfreg_dyn_idx = 0; 2038 u32 uar_index; 2039 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC); 2040 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages : 2041 bfregi->num_static_sys_pages; 2042 2043 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2044 return -EINVAL; 2045 2046 if (dyn_uar) 2047 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages; 2048 else 2049 idx = get_index(vma->vm_pgoff); 2050 2051 if (idx >= max_valid_idx) { 2052 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n", 2053 idx, max_valid_idx); 2054 return -EINVAL; 2055 } 2056 2057 switch (cmd) { 2058 case MLX5_IB_MMAP_WC_PAGE: 2059 case MLX5_IB_MMAP_ALLOC_WC: 2060 /* Some architectures don't support WC memory */ 2061 #if defined(CONFIG_X86) 2062 if (!pat_enabled()) 2063 return -EPERM; 2064 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU))) 2065 return -EPERM; 2066 #endif 2067 /* fall through */ 2068 case MLX5_IB_MMAP_REGULAR_PAGE: 2069 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 2070 prot = pgprot_writecombine(vma->vm_page_prot); 2071 break; 2072 case MLX5_IB_MMAP_NC_PAGE: 2073 prot = pgprot_noncached(vma->vm_page_prot); 2074 break; 2075 default: 2076 return -EINVAL; 2077 } 2078 2079 if (dyn_uar) { 2080 int uars_per_page; 2081 2082 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k); 2083 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR); 2084 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) { 2085 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n", 2086 bfreg_dyn_idx, bfregi->total_num_bfregs); 2087 return -EINVAL; 2088 } 2089 2090 mutex_lock(&bfregi->lock); 2091 /* Fail if uar already allocated, first bfreg index of each 2092 * page holds its count. 2093 */ 2094 if (bfregi->count[bfreg_dyn_idx]) { 2095 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx); 2096 mutex_unlock(&bfregi->lock); 2097 return -EINVAL; 2098 } 2099 2100 bfregi->count[bfreg_dyn_idx]++; 2101 mutex_unlock(&bfregi->lock); 2102 2103 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index); 2104 if (err) { 2105 mlx5_ib_warn(dev, "UAR alloc failed\n"); 2106 goto free_bfreg; 2107 } 2108 } else { 2109 uar_index = bfregi->sys_pages[idx]; 2110 } 2111 2112 pfn = uar_index2pfn(dev, uar_index); 2113 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 2114 2115 vma->vm_page_prot = prot; 2116 err = io_remap_pfn_range(vma, vma->vm_start, pfn, 2117 PAGE_SIZE, vma->vm_page_prot); 2118 if (err) { 2119 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n", 2120 err, vma->vm_start, &pfn, mmap_cmd2str(cmd)); 2121 err = -EAGAIN; 2122 goto err; 2123 } 2124 2125 pa = pfn << PAGE_SHIFT; 2126 mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd), 2127 vma->vm_start, &pa); 2128 2129 err = mlx5_ib_set_vma_data(vma, context); 2130 if (err) 2131 goto err; 2132 2133 if (dyn_uar) 2134 bfregi->sys_pages[idx] = uar_index; 2135 return 0; 2136 2137 err: 2138 if (!dyn_uar) 2139 return err; 2140 2141 mlx5_cmd_free_uar(dev->mdev, idx); 2142 2143 free_bfreg: 2144 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx); 2145 2146 return err; 2147 } 2148 2149 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 2150 { 2151 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2152 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2153 unsigned long command; 2154 phys_addr_t pfn; 2155 2156 command = get_command(vma->vm_pgoff); 2157 switch (command) { 2158 case MLX5_IB_MMAP_WC_PAGE: 2159 case MLX5_IB_MMAP_NC_PAGE: 2160 case MLX5_IB_MMAP_REGULAR_PAGE: 2161 case MLX5_IB_MMAP_ALLOC_WC: 2162 return uar_mmap(dev, command, vma, context); 2163 2164 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 2165 return -ENOSYS; 2166 2167 case MLX5_IB_MMAP_CORE_CLOCK: 2168 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2169 return -EINVAL; 2170 2171 if (vma->vm_flags & VM_WRITE) 2172 return -EPERM; 2173 2174 /* Don't expose to user-space information it shouldn't have */ 2175 if (PAGE_SIZE > 4096) 2176 return -EOPNOTSUPP; 2177 2178 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 2179 pfn = (dev->mdev->iseg_base + 2180 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 2181 PAGE_SHIFT; 2182 if (io_remap_pfn_range(vma, vma->vm_start, pfn, 2183 PAGE_SIZE, vma->vm_page_prot)) 2184 return -EAGAIN; 2185 2186 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n", 2187 vma->vm_start, 2188 (unsigned long long)pfn << PAGE_SHIFT); 2189 break; 2190 case MLX5_IB_MMAP_CLOCK_INFO: 2191 return mlx5_ib_mmap_clock_info_page(dev, vma, context); 2192 2193 default: 2194 return -EINVAL; 2195 } 2196 2197 return 0; 2198 } 2199 2200 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev, 2201 struct ib_ucontext *context, 2202 struct ib_udata *udata) 2203 { 2204 struct mlx5_ib_alloc_pd_resp resp; 2205 struct mlx5_ib_pd *pd; 2206 int err; 2207 2208 pd = kmalloc(sizeof(*pd), GFP_KERNEL); 2209 if (!pd) 2210 return ERR_PTR(-ENOMEM); 2211 2212 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn); 2213 if (err) { 2214 kfree(pd); 2215 return ERR_PTR(err); 2216 } 2217 2218 if (context) { 2219 resp.pdn = pd->pdn; 2220 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 2221 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn); 2222 kfree(pd); 2223 return ERR_PTR(-EFAULT); 2224 } 2225 } 2226 2227 return &pd->ibpd; 2228 } 2229 2230 static int mlx5_ib_dealloc_pd(struct ib_pd *pd) 2231 { 2232 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 2233 struct mlx5_ib_pd *mpd = to_mpd(pd); 2234 2235 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn); 2236 kfree(mpd); 2237 2238 return 0; 2239 } 2240 2241 enum { 2242 MATCH_CRITERIA_ENABLE_OUTER_BIT, 2243 MATCH_CRITERIA_ENABLE_MISC_BIT, 2244 MATCH_CRITERIA_ENABLE_INNER_BIT 2245 }; 2246 2247 #define HEADER_IS_ZERO(match_criteria, headers) \ 2248 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \ 2249 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \ 2250 2251 static u8 get_match_criteria_enable(u32 *match_criteria) 2252 { 2253 u8 match_criteria_enable; 2254 2255 match_criteria_enable = 2256 (!HEADER_IS_ZERO(match_criteria, outer_headers)) << 2257 MATCH_CRITERIA_ENABLE_OUTER_BIT; 2258 match_criteria_enable |= 2259 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) << 2260 MATCH_CRITERIA_ENABLE_MISC_BIT; 2261 match_criteria_enable |= 2262 (!HEADER_IS_ZERO(match_criteria, inner_headers)) << 2263 MATCH_CRITERIA_ENABLE_INNER_BIT; 2264 2265 return match_criteria_enable; 2266 } 2267 2268 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val) 2269 { 2270 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask); 2271 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val); 2272 } 2273 2274 static void set_flow_label(void *misc_c, void *misc_v, u8 mask, u8 val, 2275 bool inner) 2276 { 2277 if (inner) { 2278 MLX5_SET(fte_match_set_misc, 2279 misc_c, inner_ipv6_flow_label, mask); 2280 MLX5_SET(fte_match_set_misc, 2281 misc_v, inner_ipv6_flow_label, val); 2282 } else { 2283 MLX5_SET(fte_match_set_misc, 2284 misc_c, outer_ipv6_flow_label, mask); 2285 MLX5_SET(fte_match_set_misc, 2286 misc_v, outer_ipv6_flow_label, val); 2287 } 2288 } 2289 2290 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val) 2291 { 2292 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask); 2293 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val); 2294 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2); 2295 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2); 2296 } 2297 2298 #define LAST_ETH_FIELD vlan_tag 2299 #define LAST_IB_FIELD sl 2300 #define LAST_IPV4_FIELD tos 2301 #define LAST_IPV6_FIELD traffic_class 2302 #define LAST_TCP_UDP_FIELD src_port 2303 #define LAST_TUNNEL_FIELD tunnel_id 2304 #define LAST_FLOW_TAG_FIELD tag_id 2305 #define LAST_DROP_FIELD size 2306 2307 /* Field is the last supported field */ 2308 #define FIELDS_NOT_SUPPORTED(filter, field)\ 2309 memchr_inv((void *)&filter.field +\ 2310 sizeof(filter.field), 0,\ 2311 sizeof(filter) -\ 2312 offsetof(typeof(filter), field) -\ 2313 sizeof(filter.field)) 2314 2315 #define IPV4_VERSION 4 2316 #define IPV6_VERSION 6 2317 static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c, 2318 u32 *match_v, const union ib_flow_spec *ib_spec, 2319 u32 *tag_id, bool *is_drop) 2320 { 2321 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c, 2322 misc_parameters); 2323 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v, 2324 misc_parameters); 2325 void *headers_c; 2326 void *headers_v; 2327 int match_ipv; 2328 2329 if (ib_spec->type & IB_FLOW_SPEC_INNER) { 2330 headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 2331 inner_headers); 2332 headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 2333 inner_headers); 2334 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2335 ft_field_support.inner_ip_version); 2336 } else { 2337 headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 2338 outer_headers); 2339 headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 2340 outer_headers); 2341 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2342 ft_field_support.outer_ip_version); 2343 } 2344 2345 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) { 2346 case IB_FLOW_SPEC_ETH: 2347 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD)) 2348 return -EOPNOTSUPP; 2349 2350 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2351 dmac_47_16), 2352 ib_spec->eth.mask.dst_mac); 2353 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2354 dmac_47_16), 2355 ib_spec->eth.val.dst_mac); 2356 2357 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2358 smac_47_16), 2359 ib_spec->eth.mask.src_mac); 2360 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2361 smac_47_16), 2362 ib_spec->eth.val.src_mac); 2363 2364 if (ib_spec->eth.mask.vlan_tag) { 2365 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2366 cvlan_tag, 1); 2367 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2368 cvlan_tag, 1); 2369 2370 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2371 first_vid, ntohs(ib_spec->eth.mask.vlan_tag)); 2372 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2373 first_vid, ntohs(ib_spec->eth.val.vlan_tag)); 2374 2375 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2376 first_cfi, 2377 ntohs(ib_spec->eth.mask.vlan_tag) >> 12); 2378 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2379 first_cfi, 2380 ntohs(ib_spec->eth.val.vlan_tag) >> 12); 2381 2382 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2383 first_prio, 2384 ntohs(ib_spec->eth.mask.vlan_tag) >> 13); 2385 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2386 first_prio, 2387 ntohs(ib_spec->eth.val.vlan_tag) >> 13); 2388 } 2389 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2390 ethertype, ntohs(ib_spec->eth.mask.ether_type)); 2391 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2392 ethertype, ntohs(ib_spec->eth.val.ether_type)); 2393 break; 2394 case IB_FLOW_SPEC_IPV4: 2395 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD)) 2396 return -EOPNOTSUPP; 2397 2398 if (match_ipv) { 2399 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2400 ip_version, 0xf); 2401 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2402 ip_version, IPV4_VERSION); 2403 } else { 2404 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2405 ethertype, 0xffff); 2406 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2407 ethertype, ETH_P_IP); 2408 } 2409 2410 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2411 src_ipv4_src_ipv6.ipv4_layout.ipv4), 2412 &ib_spec->ipv4.mask.src_ip, 2413 sizeof(ib_spec->ipv4.mask.src_ip)); 2414 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2415 src_ipv4_src_ipv6.ipv4_layout.ipv4), 2416 &ib_spec->ipv4.val.src_ip, 2417 sizeof(ib_spec->ipv4.val.src_ip)); 2418 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2419 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 2420 &ib_spec->ipv4.mask.dst_ip, 2421 sizeof(ib_spec->ipv4.mask.dst_ip)); 2422 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2423 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 2424 &ib_spec->ipv4.val.dst_ip, 2425 sizeof(ib_spec->ipv4.val.dst_ip)); 2426 2427 set_tos(headers_c, headers_v, 2428 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos); 2429 2430 set_proto(headers_c, headers_v, 2431 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto); 2432 break; 2433 case IB_FLOW_SPEC_IPV6: 2434 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD)) 2435 return -EOPNOTSUPP; 2436 2437 if (match_ipv) { 2438 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2439 ip_version, 0xf); 2440 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2441 ip_version, IPV6_VERSION); 2442 } else { 2443 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2444 ethertype, 0xffff); 2445 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2446 ethertype, ETH_P_IPV6); 2447 } 2448 2449 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2450 src_ipv4_src_ipv6.ipv6_layout.ipv6), 2451 &ib_spec->ipv6.mask.src_ip, 2452 sizeof(ib_spec->ipv6.mask.src_ip)); 2453 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2454 src_ipv4_src_ipv6.ipv6_layout.ipv6), 2455 &ib_spec->ipv6.val.src_ip, 2456 sizeof(ib_spec->ipv6.val.src_ip)); 2457 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2458 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 2459 &ib_spec->ipv6.mask.dst_ip, 2460 sizeof(ib_spec->ipv6.mask.dst_ip)); 2461 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2462 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 2463 &ib_spec->ipv6.val.dst_ip, 2464 sizeof(ib_spec->ipv6.val.dst_ip)); 2465 2466 set_tos(headers_c, headers_v, 2467 ib_spec->ipv6.mask.traffic_class, 2468 ib_spec->ipv6.val.traffic_class); 2469 2470 set_proto(headers_c, headers_v, 2471 ib_spec->ipv6.mask.next_hdr, 2472 ib_spec->ipv6.val.next_hdr); 2473 2474 set_flow_label(misc_params_c, misc_params_v, 2475 ntohl(ib_spec->ipv6.mask.flow_label), 2476 ntohl(ib_spec->ipv6.val.flow_label), 2477 ib_spec->type & IB_FLOW_SPEC_INNER); 2478 2479 break; 2480 case IB_FLOW_SPEC_TCP: 2481 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 2482 LAST_TCP_UDP_FIELD)) 2483 return -EOPNOTSUPP; 2484 2485 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol, 2486 0xff); 2487 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, 2488 IPPROTO_TCP); 2489 2490 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport, 2491 ntohs(ib_spec->tcp_udp.mask.src_port)); 2492 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport, 2493 ntohs(ib_spec->tcp_udp.val.src_port)); 2494 2495 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport, 2496 ntohs(ib_spec->tcp_udp.mask.dst_port)); 2497 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport, 2498 ntohs(ib_spec->tcp_udp.val.dst_port)); 2499 break; 2500 case IB_FLOW_SPEC_UDP: 2501 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 2502 LAST_TCP_UDP_FIELD)) 2503 return -EOPNOTSUPP; 2504 2505 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol, 2506 0xff); 2507 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, 2508 IPPROTO_UDP); 2509 2510 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport, 2511 ntohs(ib_spec->tcp_udp.mask.src_port)); 2512 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport, 2513 ntohs(ib_spec->tcp_udp.val.src_port)); 2514 2515 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport, 2516 ntohs(ib_spec->tcp_udp.mask.dst_port)); 2517 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, 2518 ntohs(ib_spec->tcp_udp.val.dst_port)); 2519 break; 2520 case IB_FLOW_SPEC_VXLAN_TUNNEL: 2521 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask, 2522 LAST_TUNNEL_FIELD)) 2523 return -EOPNOTSUPP; 2524 2525 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni, 2526 ntohl(ib_spec->tunnel.mask.tunnel_id)); 2527 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni, 2528 ntohl(ib_spec->tunnel.val.tunnel_id)); 2529 break; 2530 case IB_FLOW_SPEC_ACTION_TAG: 2531 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag, 2532 LAST_FLOW_TAG_FIELD)) 2533 return -EOPNOTSUPP; 2534 if (ib_spec->flow_tag.tag_id >= BIT(24)) 2535 return -EINVAL; 2536 2537 *tag_id = ib_spec->flow_tag.tag_id; 2538 break; 2539 case IB_FLOW_SPEC_ACTION_DROP: 2540 if (FIELDS_NOT_SUPPORTED(ib_spec->drop, 2541 LAST_DROP_FIELD)) 2542 return -EOPNOTSUPP; 2543 *is_drop = true; 2544 break; 2545 default: 2546 return -EINVAL; 2547 } 2548 2549 return 0; 2550 } 2551 2552 /* If a flow could catch both multicast and unicast packets, 2553 * it won't fall into the multicast flow steering table and this rule 2554 * could steal other multicast packets. 2555 */ 2556 static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr) 2557 { 2558 union ib_flow_spec *flow_spec; 2559 2560 if (ib_attr->type != IB_FLOW_ATTR_NORMAL || 2561 ib_attr->num_of_specs < 1) 2562 return false; 2563 2564 flow_spec = (union ib_flow_spec *)(ib_attr + 1); 2565 if (flow_spec->type == IB_FLOW_SPEC_IPV4) { 2566 struct ib_flow_spec_ipv4 *ipv4_spec; 2567 2568 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec; 2569 if (ipv4_is_multicast(ipv4_spec->val.dst_ip)) 2570 return true; 2571 2572 return false; 2573 } 2574 2575 if (flow_spec->type == IB_FLOW_SPEC_ETH) { 2576 struct ib_flow_spec_eth *eth_spec; 2577 2578 eth_spec = (struct ib_flow_spec_eth *)flow_spec; 2579 return is_multicast_ether_addr(eth_spec->mask.dst_mac) && 2580 is_multicast_ether_addr(eth_spec->val.dst_mac); 2581 } 2582 2583 return false; 2584 } 2585 2586 static bool is_valid_ethertype(struct mlx5_core_dev *mdev, 2587 const struct ib_flow_attr *flow_attr, 2588 bool check_inner) 2589 { 2590 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1); 2591 int match_ipv = check_inner ? 2592 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2593 ft_field_support.inner_ip_version) : 2594 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2595 ft_field_support.outer_ip_version); 2596 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0; 2597 bool ipv4_spec_valid, ipv6_spec_valid; 2598 unsigned int ip_spec_type = 0; 2599 bool has_ethertype = false; 2600 unsigned int spec_index; 2601 bool mask_valid = true; 2602 u16 eth_type = 0; 2603 bool type_valid; 2604 2605 /* Validate that ethertype is correct */ 2606 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 2607 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) && 2608 ib_spec->eth.mask.ether_type) { 2609 mask_valid = (ib_spec->eth.mask.ether_type == 2610 htons(0xffff)); 2611 has_ethertype = true; 2612 eth_type = ntohs(ib_spec->eth.val.ether_type); 2613 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) || 2614 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) { 2615 ip_spec_type = ib_spec->type; 2616 } 2617 ib_spec = (void *)ib_spec + ib_spec->size; 2618 } 2619 2620 type_valid = (!has_ethertype) || (!ip_spec_type); 2621 if (!type_valid && mask_valid) { 2622 ipv4_spec_valid = (eth_type == ETH_P_IP) && 2623 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit)); 2624 ipv6_spec_valid = (eth_type == ETH_P_IPV6) && 2625 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit)); 2626 2627 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) || 2628 (((eth_type == ETH_P_MPLS_UC) || 2629 (eth_type == ETH_P_MPLS_MC)) && match_ipv); 2630 } 2631 2632 return type_valid; 2633 } 2634 2635 static bool is_valid_attr(struct mlx5_core_dev *mdev, 2636 const struct ib_flow_attr *flow_attr) 2637 { 2638 return is_valid_ethertype(mdev, flow_attr, false) && 2639 is_valid_ethertype(mdev, flow_attr, true); 2640 } 2641 2642 static void put_flow_table(struct mlx5_ib_dev *dev, 2643 struct mlx5_ib_flow_prio *prio, bool ft_added) 2644 { 2645 prio->refcount -= !!ft_added; 2646 if (!prio->refcount) { 2647 mlx5_destroy_flow_table(prio->flow_table); 2648 prio->flow_table = NULL; 2649 } 2650 } 2651 2652 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id) 2653 { 2654 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device); 2655 struct mlx5_ib_flow_handler *handler = container_of(flow_id, 2656 struct mlx5_ib_flow_handler, 2657 ibflow); 2658 struct mlx5_ib_flow_handler *iter, *tmp; 2659 2660 mutex_lock(&dev->flow_db->lock); 2661 2662 list_for_each_entry_safe(iter, tmp, &handler->list, list) { 2663 mlx5_del_flow_rules(iter->rule); 2664 put_flow_table(dev, iter->prio, true); 2665 list_del(&iter->list); 2666 kfree(iter); 2667 } 2668 2669 mlx5_del_flow_rules(handler->rule); 2670 put_flow_table(dev, handler->prio, true); 2671 mutex_unlock(&dev->flow_db->lock); 2672 2673 kfree(handler); 2674 2675 return 0; 2676 } 2677 2678 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap) 2679 { 2680 priority *= 2; 2681 if (!dont_trap) 2682 priority++; 2683 return priority; 2684 } 2685 2686 enum flow_table_type { 2687 MLX5_IB_FT_RX, 2688 MLX5_IB_FT_TX 2689 }; 2690 2691 #define MLX5_FS_MAX_TYPES 6 2692 #define MLX5_FS_MAX_ENTRIES BIT(16) 2693 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev, 2694 struct ib_flow_attr *flow_attr, 2695 enum flow_table_type ft_type) 2696 { 2697 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP; 2698 struct mlx5_flow_namespace *ns = NULL; 2699 struct mlx5_ib_flow_prio *prio; 2700 struct mlx5_flow_table *ft; 2701 int max_table_size; 2702 int num_entries; 2703 int num_groups; 2704 int priority; 2705 int err = 0; 2706 2707 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 2708 log_max_ft_size)); 2709 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 2710 if (flow_is_multicast_only(flow_attr) && 2711 !dont_trap) 2712 priority = MLX5_IB_FLOW_MCAST_PRIO; 2713 else 2714 priority = ib_prio_to_core_prio(flow_attr->priority, 2715 dont_trap); 2716 ns = mlx5_get_flow_namespace(dev->mdev, 2717 MLX5_FLOW_NAMESPACE_BYPASS); 2718 num_entries = MLX5_FS_MAX_ENTRIES; 2719 num_groups = MLX5_FS_MAX_TYPES; 2720 prio = &dev->flow_db->prios[priority]; 2721 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 2722 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 2723 ns = mlx5_get_flow_namespace(dev->mdev, 2724 MLX5_FLOW_NAMESPACE_LEFTOVERS); 2725 build_leftovers_ft_param(&priority, 2726 &num_entries, 2727 &num_groups); 2728 prio = &dev->flow_db->prios[MLX5_IB_FLOW_LEFTOVERS_PRIO]; 2729 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 2730 if (!MLX5_CAP_FLOWTABLE(dev->mdev, 2731 allow_sniffer_and_nic_rx_shared_tir)) 2732 return ERR_PTR(-ENOTSUPP); 2733 2734 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ? 2735 MLX5_FLOW_NAMESPACE_SNIFFER_RX : 2736 MLX5_FLOW_NAMESPACE_SNIFFER_TX); 2737 2738 prio = &dev->flow_db->sniffer[ft_type]; 2739 priority = 0; 2740 num_entries = 1; 2741 num_groups = 1; 2742 } 2743 2744 if (!ns) 2745 return ERR_PTR(-ENOTSUPP); 2746 2747 if (num_entries > max_table_size) 2748 return ERR_PTR(-ENOMEM); 2749 2750 ft = prio->flow_table; 2751 if (!ft) { 2752 ft = mlx5_create_auto_grouped_flow_table(ns, priority, 2753 num_entries, 2754 num_groups, 2755 0, 0); 2756 2757 if (!IS_ERR(ft)) { 2758 prio->refcount = 0; 2759 prio->flow_table = ft; 2760 } else { 2761 err = PTR_ERR(ft); 2762 } 2763 } 2764 2765 return err ? ERR_PTR(err) : prio; 2766 } 2767 2768 static void set_underlay_qp(struct mlx5_ib_dev *dev, 2769 struct mlx5_flow_spec *spec, 2770 u32 underlay_qpn) 2771 { 2772 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, 2773 spec->match_criteria, 2774 misc_parameters); 2775 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, 2776 misc_parameters); 2777 2778 if (underlay_qpn && 2779 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 2780 ft_field_support.bth_dst_qp)) { 2781 MLX5_SET(fte_match_set_misc, 2782 misc_params_v, bth_dst_qp, underlay_qpn); 2783 MLX5_SET(fte_match_set_misc, 2784 misc_params_c, bth_dst_qp, 0xffffff); 2785 } 2786 } 2787 2788 static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev, 2789 struct mlx5_ib_flow_prio *ft_prio, 2790 const struct ib_flow_attr *flow_attr, 2791 struct mlx5_flow_destination *dst, 2792 u32 underlay_qpn) 2793 { 2794 struct mlx5_flow_table *ft = ft_prio->flow_table; 2795 struct mlx5_ib_flow_handler *handler; 2796 struct mlx5_flow_act flow_act = {0}; 2797 struct mlx5_flow_spec *spec; 2798 struct mlx5_flow_destination *rule_dst = dst; 2799 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr); 2800 unsigned int spec_index; 2801 u32 flow_tag = MLX5_FS_DEFAULT_FLOW_TAG; 2802 bool is_drop = false; 2803 int err = 0; 2804 int dest_num = 1; 2805 2806 if (!is_valid_attr(dev->mdev, flow_attr)) 2807 return ERR_PTR(-EINVAL); 2808 2809 spec = kvzalloc(sizeof(*spec), GFP_KERNEL); 2810 handler = kzalloc(sizeof(*handler), GFP_KERNEL); 2811 if (!handler || !spec) { 2812 err = -ENOMEM; 2813 goto free; 2814 } 2815 2816 INIT_LIST_HEAD(&handler->list); 2817 2818 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 2819 err = parse_flow_attr(dev->mdev, spec->match_criteria, 2820 spec->match_value, 2821 ib_flow, &flow_tag, &is_drop); 2822 if (err < 0) 2823 goto free; 2824 2825 ib_flow += ((union ib_flow_spec *)ib_flow)->size; 2826 } 2827 2828 if (!flow_is_multicast_only(flow_attr)) 2829 set_underlay_qp(dev, spec, underlay_qpn); 2830 2831 if (dev->rep) { 2832 void *misc; 2833 2834 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, 2835 misc_parameters); 2836 MLX5_SET(fte_match_set_misc, misc, source_port, 2837 dev->rep->vport); 2838 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, 2839 misc_parameters); 2840 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port); 2841 } 2842 2843 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria); 2844 if (is_drop) { 2845 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_DROP; 2846 rule_dst = NULL; 2847 dest_num = 0; 2848 } else { 2849 flow_act.action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST : 2850 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO; 2851 } 2852 2853 if (flow_tag != MLX5_FS_DEFAULT_FLOW_TAG && 2854 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 2855 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) { 2856 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n", 2857 flow_tag, flow_attr->type); 2858 err = -EINVAL; 2859 goto free; 2860 } 2861 flow_act.flow_tag = flow_tag; 2862 handler->rule = mlx5_add_flow_rules(ft, spec, 2863 &flow_act, 2864 rule_dst, dest_num); 2865 2866 if (IS_ERR(handler->rule)) { 2867 err = PTR_ERR(handler->rule); 2868 goto free; 2869 } 2870 2871 ft_prio->refcount++; 2872 handler->prio = ft_prio; 2873 2874 ft_prio->flow_table = ft; 2875 free: 2876 if (err) 2877 kfree(handler); 2878 kvfree(spec); 2879 return err ? ERR_PTR(err) : handler; 2880 } 2881 2882 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev, 2883 struct mlx5_ib_flow_prio *ft_prio, 2884 const struct ib_flow_attr *flow_attr, 2885 struct mlx5_flow_destination *dst) 2886 { 2887 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0); 2888 } 2889 2890 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev, 2891 struct mlx5_ib_flow_prio *ft_prio, 2892 struct ib_flow_attr *flow_attr, 2893 struct mlx5_flow_destination *dst) 2894 { 2895 struct mlx5_ib_flow_handler *handler_dst = NULL; 2896 struct mlx5_ib_flow_handler *handler = NULL; 2897 2898 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL); 2899 if (!IS_ERR(handler)) { 2900 handler_dst = create_flow_rule(dev, ft_prio, 2901 flow_attr, dst); 2902 if (IS_ERR(handler_dst)) { 2903 mlx5_del_flow_rules(handler->rule); 2904 ft_prio->refcount--; 2905 kfree(handler); 2906 handler = handler_dst; 2907 } else { 2908 list_add(&handler_dst->list, &handler->list); 2909 } 2910 } 2911 2912 return handler; 2913 } 2914 enum { 2915 LEFTOVERS_MC, 2916 LEFTOVERS_UC, 2917 }; 2918 2919 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev, 2920 struct mlx5_ib_flow_prio *ft_prio, 2921 struct ib_flow_attr *flow_attr, 2922 struct mlx5_flow_destination *dst) 2923 { 2924 struct mlx5_ib_flow_handler *handler_ucast = NULL; 2925 struct mlx5_ib_flow_handler *handler = NULL; 2926 2927 static struct { 2928 struct ib_flow_attr flow_attr; 2929 struct ib_flow_spec_eth eth_flow; 2930 } leftovers_specs[] = { 2931 [LEFTOVERS_MC] = { 2932 .flow_attr = { 2933 .num_of_specs = 1, 2934 .size = sizeof(leftovers_specs[0]) 2935 }, 2936 .eth_flow = { 2937 .type = IB_FLOW_SPEC_ETH, 2938 .size = sizeof(struct ib_flow_spec_eth), 2939 .mask = {.dst_mac = {0x1} }, 2940 .val = {.dst_mac = {0x1} } 2941 } 2942 }, 2943 [LEFTOVERS_UC] = { 2944 .flow_attr = { 2945 .num_of_specs = 1, 2946 .size = sizeof(leftovers_specs[0]) 2947 }, 2948 .eth_flow = { 2949 .type = IB_FLOW_SPEC_ETH, 2950 .size = sizeof(struct ib_flow_spec_eth), 2951 .mask = {.dst_mac = {0x1} }, 2952 .val = {.dst_mac = {} } 2953 } 2954 } 2955 }; 2956 2957 handler = create_flow_rule(dev, ft_prio, 2958 &leftovers_specs[LEFTOVERS_MC].flow_attr, 2959 dst); 2960 if (!IS_ERR(handler) && 2961 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) { 2962 handler_ucast = create_flow_rule(dev, ft_prio, 2963 &leftovers_specs[LEFTOVERS_UC].flow_attr, 2964 dst); 2965 if (IS_ERR(handler_ucast)) { 2966 mlx5_del_flow_rules(handler->rule); 2967 ft_prio->refcount--; 2968 kfree(handler); 2969 handler = handler_ucast; 2970 } else { 2971 list_add(&handler_ucast->list, &handler->list); 2972 } 2973 } 2974 2975 return handler; 2976 } 2977 2978 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev, 2979 struct mlx5_ib_flow_prio *ft_rx, 2980 struct mlx5_ib_flow_prio *ft_tx, 2981 struct mlx5_flow_destination *dst) 2982 { 2983 struct mlx5_ib_flow_handler *handler_rx; 2984 struct mlx5_ib_flow_handler *handler_tx; 2985 int err; 2986 static const struct ib_flow_attr flow_attr = { 2987 .num_of_specs = 0, 2988 .size = sizeof(flow_attr) 2989 }; 2990 2991 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst); 2992 if (IS_ERR(handler_rx)) { 2993 err = PTR_ERR(handler_rx); 2994 goto err; 2995 } 2996 2997 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst); 2998 if (IS_ERR(handler_tx)) { 2999 err = PTR_ERR(handler_tx); 3000 goto err_tx; 3001 } 3002 3003 list_add(&handler_tx->list, &handler_rx->list); 3004 3005 return handler_rx; 3006 3007 err_tx: 3008 mlx5_del_flow_rules(handler_rx->rule); 3009 ft_rx->refcount--; 3010 kfree(handler_rx); 3011 err: 3012 return ERR_PTR(err); 3013 } 3014 3015 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp, 3016 struct ib_flow_attr *flow_attr, 3017 int domain) 3018 { 3019 struct mlx5_ib_dev *dev = to_mdev(qp->device); 3020 struct mlx5_ib_qp *mqp = to_mqp(qp); 3021 struct mlx5_ib_flow_handler *handler = NULL; 3022 struct mlx5_flow_destination *dst = NULL; 3023 struct mlx5_ib_flow_prio *ft_prio_tx = NULL; 3024 struct mlx5_ib_flow_prio *ft_prio; 3025 int err; 3026 int underlay_qpn; 3027 3028 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) 3029 return ERR_PTR(-ENOMEM); 3030 3031 if (domain != IB_FLOW_DOMAIN_USER || 3032 flow_attr->port > dev->num_ports || 3033 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP)) 3034 return ERR_PTR(-EINVAL); 3035 3036 dst = kzalloc(sizeof(*dst), GFP_KERNEL); 3037 if (!dst) 3038 return ERR_PTR(-ENOMEM); 3039 3040 mutex_lock(&dev->flow_db->lock); 3041 3042 ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX); 3043 if (IS_ERR(ft_prio)) { 3044 err = PTR_ERR(ft_prio); 3045 goto unlock; 3046 } 3047 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 3048 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX); 3049 if (IS_ERR(ft_prio_tx)) { 3050 err = PTR_ERR(ft_prio_tx); 3051 ft_prio_tx = NULL; 3052 goto destroy_ft; 3053 } 3054 } 3055 3056 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR; 3057 if (mqp->flags & MLX5_IB_QP_RSS) 3058 dst->tir_num = mqp->rss_qp.tirn; 3059 else 3060 dst->tir_num = mqp->raw_packet_qp.rq.tirn; 3061 3062 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 3063 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) { 3064 handler = create_dont_trap_rule(dev, ft_prio, 3065 flow_attr, dst); 3066 } else { 3067 underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ? 3068 mqp->underlay_qpn : 0; 3069 handler = _create_flow_rule(dev, ft_prio, flow_attr, 3070 dst, underlay_qpn); 3071 } 3072 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 3073 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 3074 handler = create_leftovers_rule(dev, ft_prio, flow_attr, 3075 dst); 3076 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 3077 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst); 3078 } else { 3079 err = -EINVAL; 3080 goto destroy_ft; 3081 } 3082 3083 if (IS_ERR(handler)) { 3084 err = PTR_ERR(handler); 3085 handler = NULL; 3086 goto destroy_ft; 3087 } 3088 3089 mutex_unlock(&dev->flow_db->lock); 3090 kfree(dst); 3091 3092 return &handler->ibflow; 3093 3094 destroy_ft: 3095 put_flow_table(dev, ft_prio, false); 3096 if (ft_prio_tx) 3097 put_flow_table(dev, ft_prio_tx, false); 3098 unlock: 3099 mutex_unlock(&dev->flow_db->lock); 3100 kfree(dst); 3101 kfree(handler); 3102 return ERR_PTR(err); 3103 } 3104 3105 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 3106 { 3107 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3108 struct mlx5_ib_qp *mqp = to_mqp(ibqp); 3109 int err; 3110 3111 if (mqp->flags & MLX5_IB_QP_UNDERLAY) { 3112 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n"); 3113 return -EOPNOTSUPP; 3114 } 3115 3116 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num); 3117 if (err) 3118 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 3119 ibqp->qp_num, gid->raw); 3120 3121 return err; 3122 } 3123 3124 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 3125 { 3126 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3127 int err; 3128 3129 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num); 3130 if (err) 3131 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 3132 ibqp->qp_num, gid->raw); 3133 3134 return err; 3135 } 3136 3137 static int init_node_data(struct mlx5_ib_dev *dev) 3138 { 3139 int err; 3140 3141 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 3142 if (err) 3143 return err; 3144 3145 dev->mdev->rev_id = dev->mdev->pdev->revision; 3146 3147 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 3148 } 3149 3150 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr, 3151 char *buf) 3152 { 3153 struct mlx5_ib_dev *dev = 3154 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 3155 3156 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages); 3157 } 3158 3159 static ssize_t show_reg_pages(struct device *device, 3160 struct device_attribute *attr, char *buf) 3161 { 3162 struct mlx5_ib_dev *dev = 3163 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 3164 3165 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 3166 } 3167 3168 static ssize_t show_hca(struct device *device, struct device_attribute *attr, 3169 char *buf) 3170 { 3171 struct mlx5_ib_dev *dev = 3172 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 3173 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device); 3174 } 3175 3176 static ssize_t show_rev(struct device *device, struct device_attribute *attr, 3177 char *buf) 3178 { 3179 struct mlx5_ib_dev *dev = 3180 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 3181 return sprintf(buf, "%x\n", dev->mdev->rev_id); 3182 } 3183 3184 static ssize_t show_board(struct device *device, struct device_attribute *attr, 3185 char *buf) 3186 { 3187 struct mlx5_ib_dev *dev = 3188 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 3189 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 3190 dev->mdev->board_id); 3191 } 3192 3193 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL); 3194 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL); 3195 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL); 3196 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL); 3197 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL); 3198 3199 static struct device_attribute *mlx5_class_attributes[] = { 3200 &dev_attr_hw_rev, 3201 &dev_attr_hca_type, 3202 &dev_attr_board_id, 3203 &dev_attr_fw_pages, 3204 &dev_attr_reg_pages, 3205 }; 3206 3207 static void pkey_change_handler(struct work_struct *work) 3208 { 3209 struct mlx5_ib_port_resources *ports = 3210 container_of(work, struct mlx5_ib_port_resources, 3211 pkey_change_work); 3212 3213 mutex_lock(&ports->devr->mutex); 3214 mlx5_ib_gsi_pkey_change(ports->gsi); 3215 mutex_unlock(&ports->devr->mutex); 3216 } 3217 3218 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 3219 { 3220 struct mlx5_ib_qp *mqp; 3221 struct mlx5_ib_cq *send_mcq, *recv_mcq; 3222 struct mlx5_core_cq *mcq; 3223 struct list_head cq_armed_list; 3224 unsigned long flags_qp; 3225 unsigned long flags_cq; 3226 unsigned long flags; 3227 3228 INIT_LIST_HEAD(&cq_armed_list); 3229 3230 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 3231 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 3232 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 3233 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 3234 if (mqp->sq.tail != mqp->sq.head) { 3235 send_mcq = to_mcq(mqp->ibqp.send_cq); 3236 spin_lock_irqsave(&send_mcq->lock, flags_cq); 3237 if (send_mcq->mcq.comp && 3238 mqp->ibqp.send_cq->comp_handler) { 3239 if (!send_mcq->mcq.reset_notify_added) { 3240 send_mcq->mcq.reset_notify_added = 1; 3241 list_add_tail(&send_mcq->mcq.reset_notify, 3242 &cq_armed_list); 3243 } 3244 } 3245 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 3246 } 3247 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 3248 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 3249 /* no handling is needed for SRQ */ 3250 if (!mqp->ibqp.srq) { 3251 if (mqp->rq.tail != mqp->rq.head) { 3252 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 3253 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 3254 if (recv_mcq->mcq.comp && 3255 mqp->ibqp.recv_cq->comp_handler) { 3256 if (!recv_mcq->mcq.reset_notify_added) { 3257 recv_mcq->mcq.reset_notify_added = 1; 3258 list_add_tail(&recv_mcq->mcq.reset_notify, 3259 &cq_armed_list); 3260 } 3261 } 3262 spin_unlock_irqrestore(&recv_mcq->lock, 3263 flags_cq); 3264 } 3265 } 3266 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 3267 } 3268 /*At that point all inflight post send were put to be executed as of we 3269 * lock/unlock above locks Now need to arm all involved CQs. 3270 */ 3271 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 3272 mcq->comp(mcq); 3273 } 3274 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 3275 } 3276 3277 static void delay_drop_handler(struct work_struct *work) 3278 { 3279 int err; 3280 struct mlx5_ib_delay_drop *delay_drop = 3281 container_of(work, struct mlx5_ib_delay_drop, 3282 delay_drop_work); 3283 3284 atomic_inc(&delay_drop->events_cnt); 3285 3286 mutex_lock(&delay_drop->lock); 3287 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev, 3288 delay_drop->timeout); 3289 if (err) { 3290 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n", 3291 delay_drop->timeout); 3292 delay_drop->activate = false; 3293 } 3294 mutex_unlock(&delay_drop->lock); 3295 } 3296 3297 static void mlx5_ib_handle_event(struct work_struct *_work) 3298 { 3299 struct mlx5_ib_event_work *work = 3300 container_of(_work, struct mlx5_ib_event_work, work); 3301 struct mlx5_ib_dev *ibdev; 3302 struct ib_event ibev; 3303 bool fatal = false; 3304 u8 port = 0; 3305 3306 if (mlx5_core_is_mp_slave(work->dev)) { 3307 ibdev = mlx5_ib_get_ibdev_from_mpi(work->context); 3308 if (!ibdev) 3309 goto out; 3310 } else { 3311 ibdev = work->context; 3312 } 3313 3314 switch (work->event) { 3315 case MLX5_DEV_EVENT_SYS_ERROR: 3316 ibev.event = IB_EVENT_DEVICE_FATAL; 3317 mlx5_ib_handle_internal_error(ibdev); 3318 fatal = true; 3319 break; 3320 3321 case MLX5_DEV_EVENT_PORT_UP: 3322 case MLX5_DEV_EVENT_PORT_DOWN: 3323 case MLX5_DEV_EVENT_PORT_INITIALIZED: 3324 port = (u8)work->param; 3325 3326 /* In RoCE, port up/down events are handled in 3327 * mlx5_netdev_event(). 3328 */ 3329 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 3330 IB_LINK_LAYER_ETHERNET) 3331 goto out; 3332 3333 ibev.event = (work->event == MLX5_DEV_EVENT_PORT_UP) ? 3334 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 3335 break; 3336 3337 case MLX5_DEV_EVENT_LID_CHANGE: 3338 ibev.event = IB_EVENT_LID_CHANGE; 3339 port = (u8)work->param; 3340 break; 3341 3342 case MLX5_DEV_EVENT_PKEY_CHANGE: 3343 ibev.event = IB_EVENT_PKEY_CHANGE; 3344 port = (u8)work->param; 3345 3346 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 3347 break; 3348 3349 case MLX5_DEV_EVENT_GUID_CHANGE: 3350 ibev.event = IB_EVENT_GID_CHANGE; 3351 port = (u8)work->param; 3352 break; 3353 3354 case MLX5_DEV_EVENT_CLIENT_REREG: 3355 ibev.event = IB_EVENT_CLIENT_REREGISTER; 3356 port = (u8)work->param; 3357 break; 3358 case MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT: 3359 schedule_work(&ibdev->delay_drop.delay_drop_work); 3360 goto out; 3361 default: 3362 goto out; 3363 } 3364 3365 ibev.device = &ibdev->ib_dev; 3366 ibev.element.port_num = port; 3367 3368 if (port < 1 || port > ibdev->num_ports) { 3369 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port); 3370 goto out; 3371 } 3372 3373 if (ibdev->ib_active) 3374 ib_dispatch_event(&ibev); 3375 3376 if (fatal) 3377 ibdev->ib_active = false; 3378 out: 3379 kfree(work); 3380 } 3381 3382 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context, 3383 enum mlx5_dev_event event, unsigned long param) 3384 { 3385 struct mlx5_ib_event_work *work; 3386 3387 work = kmalloc(sizeof(*work), GFP_ATOMIC); 3388 if (!work) 3389 return; 3390 3391 INIT_WORK(&work->work, mlx5_ib_handle_event); 3392 work->dev = dev; 3393 work->param = param; 3394 work->context = context; 3395 work->event = event; 3396 3397 queue_work(mlx5_ib_event_wq, &work->work); 3398 } 3399 3400 static int set_has_smi_cap(struct mlx5_ib_dev *dev) 3401 { 3402 struct mlx5_hca_vport_context vport_ctx; 3403 int err; 3404 int port; 3405 3406 for (port = 1; port <= dev->num_ports; port++) { 3407 dev->mdev->port_caps[port - 1].has_smi = false; 3408 if (MLX5_CAP_GEN(dev->mdev, port_type) == 3409 MLX5_CAP_PORT_TYPE_IB) { 3410 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) { 3411 err = mlx5_query_hca_vport_context(dev->mdev, 0, 3412 port, 0, 3413 &vport_ctx); 3414 if (err) { 3415 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n", 3416 port, err); 3417 return err; 3418 } 3419 dev->mdev->port_caps[port - 1].has_smi = 3420 vport_ctx.has_smi; 3421 } else { 3422 dev->mdev->port_caps[port - 1].has_smi = true; 3423 } 3424 } 3425 } 3426 return 0; 3427 } 3428 3429 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 3430 { 3431 int port; 3432 3433 for (port = 1; port <= dev->num_ports; port++) 3434 mlx5_query_ext_port_caps(dev, port); 3435 } 3436 3437 static int get_port_caps(struct mlx5_ib_dev *dev, u8 port) 3438 { 3439 struct ib_device_attr *dprops = NULL; 3440 struct ib_port_attr *pprops = NULL; 3441 int err = -ENOMEM; 3442 struct ib_udata uhw = {.inlen = 0, .outlen = 0}; 3443 3444 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL); 3445 if (!pprops) 3446 goto out; 3447 3448 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL); 3449 if (!dprops) 3450 goto out; 3451 3452 err = set_has_smi_cap(dev); 3453 if (err) 3454 goto out; 3455 3456 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw); 3457 if (err) { 3458 mlx5_ib_warn(dev, "query_device failed %d\n", err); 3459 goto out; 3460 } 3461 3462 memset(pprops, 0, sizeof(*pprops)); 3463 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops); 3464 if (err) { 3465 mlx5_ib_warn(dev, "query_port %d failed %d\n", 3466 port, err); 3467 goto out; 3468 } 3469 3470 dev->mdev->port_caps[port - 1].pkey_table_len = 3471 dprops->max_pkeys; 3472 dev->mdev->port_caps[port - 1].gid_table_len = 3473 pprops->gid_tbl_len; 3474 mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n", 3475 port, dprops->max_pkeys, pprops->gid_tbl_len); 3476 3477 out: 3478 kfree(pprops); 3479 kfree(dprops); 3480 3481 return err; 3482 } 3483 3484 static void destroy_umrc_res(struct mlx5_ib_dev *dev) 3485 { 3486 int err; 3487 3488 err = mlx5_mr_cache_cleanup(dev); 3489 if (err) 3490 mlx5_ib_warn(dev, "mr cache cleanup failed\n"); 3491 3492 mlx5_ib_destroy_qp(dev->umrc.qp); 3493 ib_free_cq(dev->umrc.cq); 3494 ib_dealloc_pd(dev->umrc.pd); 3495 } 3496 3497 enum { 3498 MAX_UMR_WR = 128, 3499 }; 3500 3501 static int create_umr_res(struct mlx5_ib_dev *dev) 3502 { 3503 struct ib_qp_init_attr *init_attr = NULL; 3504 struct ib_qp_attr *attr = NULL; 3505 struct ib_pd *pd; 3506 struct ib_cq *cq; 3507 struct ib_qp *qp; 3508 int ret; 3509 3510 attr = kzalloc(sizeof(*attr), GFP_KERNEL); 3511 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL); 3512 if (!attr || !init_attr) { 3513 ret = -ENOMEM; 3514 goto error_0; 3515 } 3516 3517 pd = ib_alloc_pd(&dev->ib_dev, 0); 3518 if (IS_ERR(pd)) { 3519 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n"); 3520 ret = PTR_ERR(pd); 3521 goto error_0; 3522 } 3523 3524 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ); 3525 if (IS_ERR(cq)) { 3526 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n"); 3527 ret = PTR_ERR(cq); 3528 goto error_2; 3529 } 3530 3531 init_attr->send_cq = cq; 3532 init_attr->recv_cq = cq; 3533 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR; 3534 init_attr->cap.max_send_wr = MAX_UMR_WR; 3535 init_attr->cap.max_send_sge = 1; 3536 init_attr->qp_type = MLX5_IB_QPT_REG_UMR; 3537 init_attr->port_num = 1; 3538 qp = mlx5_ib_create_qp(pd, init_attr, NULL); 3539 if (IS_ERR(qp)) { 3540 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n"); 3541 ret = PTR_ERR(qp); 3542 goto error_3; 3543 } 3544 qp->device = &dev->ib_dev; 3545 qp->real_qp = qp; 3546 qp->uobject = NULL; 3547 qp->qp_type = MLX5_IB_QPT_REG_UMR; 3548 qp->send_cq = init_attr->send_cq; 3549 qp->recv_cq = init_attr->recv_cq; 3550 3551 attr->qp_state = IB_QPS_INIT; 3552 attr->port_num = 1; 3553 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX | 3554 IB_QP_PORT, NULL); 3555 if (ret) { 3556 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n"); 3557 goto error_4; 3558 } 3559 3560 memset(attr, 0, sizeof(*attr)); 3561 attr->qp_state = IB_QPS_RTR; 3562 attr->path_mtu = IB_MTU_256; 3563 3564 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 3565 if (ret) { 3566 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n"); 3567 goto error_4; 3568 } 3569 3570 memset(attr, 0, sizeof(*attr)); 3571 attr->qp_state = IB_QPS_RTS; 3572 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 3573 if (ret) { 3574 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n"); 3575 goto error_4; 3576 } 3577 3578 dev->umrc.qp = qp; 3579 dev->umrc.cq = cq; 3580 dev->umrc.pd = pd; 3581 3582 sema_init(&dev->umrc.sem, MAX_UMR_WR); 3583 ret = mlx5_mr_cache_init(dev); 3584 if (ret) { 3585 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 3586 goto error_4; 3587 } 3588 3589 kfree(attr); 3590 kfree(init_attr); 3591 3592 return 0; 3593 3594 error_4: 3595 mlx5_ib_destroy_qp(qp); 3596 3597 error_3: 3598 ib_free_cq(cq); 3599 3600 error_2: 3601 ib_dealloc_pd(pd); 3602 3603 error_0: 3604 kfree(attr); 3605 kfree(init_attr); 3606 return ret; 3607 } 3608 3609 static u8 mlx5_get_umr_fence(u8 umr_fence_cap) 3610 { 3611 switch (umr_fence_cap) { 3612 case MLX5_CAP_UMR_FENCE_NONE: 3613 return MLX5_FENCE_MODE_NONE; 3614 case MLX5_CAP_UMR_FENCE_SMALL: 3615 return MLX5_FENCE_MODE_INITIATOR_SMALL; 3616 default: 3617 return MLX5_FENCE_MODE_STRONG_ORDERING; 3618 } 3619 } 3620 3621 static int create_dev_resources(struct mlx5_ib_resources *devr) 3622 { 3623 struct ib_srq_init_attr attr; 3624 struct mlx5_ib_dev *dev; 3625 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 3626 int port; 3627 int ret = 0; 3628 3629 dev = container_of(devr, struct mlx5_ib_dev, devr); 3630 3631 mutex_init(&devr->mutex); 3632 3633 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL); 3634 if (IS_ERR(devr->p0)) { 3635 ret = PTR_ERR(devr->p0); 3636 goto error0; 3637 } 3638 devr->p0->device = &dev->ib_dev; 3639 devr->p0->uobject = NULL; 3640 atomic_set(&devr->p0->usecnt, 0); 3641 3642 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL); 3643 if (IS_ERR(devr->c0)) { 3644 ret = PTR_ERR(devr->c0); 3645 goto error1; 3646 } 3647 devr->c0->device = &dev->ib_dev; 3648 devr->c0->uobject = NULL; 3649 devr->c0->comp_handler = NULL; 3650 devr->c0->event_handler = NULL; 3651 devr->c0->cq_context = NULL; 3652 atomic_set(&devr->c0->usecnt, 0); 3653 3654 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 3655 if (IS_ERR(devr->x0)) { 3656 ret = PTR_ERR(devr->x0); 3657 goto error2; 3658 } 3659 devr->x0->device = &dev->ib_dev; 3660 devr->x0->inode = NULL; 3661 atomic_set(&devr->x0->usecnt, 0); 3662 mutex_init(&devr->x0->tgt_qp_mutex); 3663 INIT_LIST_HEAD(&devr->x0->tgt_qp_list); 3664 3665 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 3666 if (IS_ERR(devr->x1)) { 3667 ret = PTR_ERR(devr->x1); 3668 goto error3; 3669 } 3670 devr->x1->device = &dev->ib_dev; 3671 devr->x1->inode = NULL; 3672 atomic_set(&devr->x1->usecnt, 0); 3673 mutex_init(&devr->x1->tgt_qp_mutex); 3674 INIT_LIST_HEAD(&devr->x1->tgt_qp_list); 3675 3676 memset(&attr, 0, sizeof(attr)); 3677 attr.attr.max_sge = 1; 3678 attr.attr.max_wr = 1; 3679 attr.srq_type = IB_SRQT_XRC; 3680 attr.ext.cq = devr->c0; 3681 attr.ext.xrc.xrcd = devr->x0; 3682 3683 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 3684 if (IS_ERR(devr->s0)) { 3685 ret = PTR_ERR(devr->s0); 3686 goto error4; 3687 } 3688 devr->s0->device = &dev->ib_dev; 3689 devr->s0->pd = devr->p0; 3690 devr->s0->uobject = NULL; 3691 devr->s0->event_handler = NULL; 3692 devr->s0->srq_context = NULL; 3693 devr->s0->srq_type = IB_SRQT_XRC; 3694 devr->s0->ext.xrc.xrcd = devr->x0; 3695 devr->s0->ext.cq = devr->c0; 3696 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt); 3697 atomic_inc(&devr->s0->ext.cq->usecnt); 3698 atomic_inc(&devr->p0->usecnt); 3699 atomic_set(&devr->s0->usecnt, 0); 3700 3701 memset(&attr, 0, sizeof(attr)); 3702 attr.attr.max_sge = 1; 3703 attr.attr.max_wr = 1; 3704 attr.srq_type = IB_SRQT_BASIC; 3705 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 3706 if (IS_ERR(devr->s1)) { 3707 ret = PTR_ERR(devr->s1); 3708 goto error5; 3709 } 3710 devr->s1->device = &dev->ib_dev; 3711 devr->s1->pd = devr->p0; 3712 devr->s1->uobject = NULL; 3713 devr->s1->event_handler = NULL; 3714 devr->s1->srq_context = NULL; 3715 devr->s1->srq_type = IB_SRQT_BASIC; 3716 devr->s1->ext.cq = devr->c0; 3717 atomic_inc(&devr->p0->usecnt); 3718 atomic_set(&devr->s1->usecnt, 0); 3719 3720 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) { 3721 INIT_WORK(&devr->ports[port].pkey_change_work, 3722 pkey_change_handler); 3723 devr->ports[port].devr = devr; 3724 } 3725 3726 return 0; 3727 3728 error5: 3729 mlx5_ib_destroy_srq(devr->s0); 3730 error4: 3731 mlx5_ib_dealloc_xrcd(devr->x1); 3732 error3: 3733 mlx5_ib_dealloc_xrcd(devr->x0); 3734 error2: 3735 mlx5_ib_destroy_cq(devr->c0); 3736 error1: 3737 mlx5_ib_dealloc_pd(devr->p0); 3738 error0: 3739 return ret; 3740 } 3741 3742 static void destroy_dev_resources(struct mlx5_ib_resources *devr) 3743 { 3744 struct mlx5_ib_dev *dev = 3745 container_of(devr, struct mlx5_ib_dev, devr); 3746 int port; 3747 3748 mlx5_ib_destroy_srq(devr->s1); 3749 mlx5_ib_destroy_srq(devr->s0); 3750 mlx5_ib_dealloc_xrcd(devr->x0); 3751 mlx5_ib_dealloc_xrcd(devr->x1); 3752 mlx5_ib_destroy_cq(devr->c0); 3753 mlx5_ib_dealloc_pd(devr->p0); 3754 3755 /* Make sure no change P_Key work items are still executing */ 3756 for (port = 0; port < dev->num_ports; ++port) 3757 cancel_work_sync(&devr->ports[port].pkey_change_work); 3758 } 3759 3760 static u32 get_core_cap_flags(struct ib_device *ibdev) 3761 { 3762 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3763 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 3764 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 3765 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 3766 bool raw_support = !mlx5_core_mp_enabled(dev->mdev); 3767 u32 ret = 0; 3768 3769 if (ll == IB_LINK_LAYER_INFINIBAND) 3770 return RDMA_CORE_PORT_IBA_IB; 3771 3772 if (raw_support) 3773 ret = RDMA_CORE_PORT_RAW_PACKET; 3774 3775 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 3776 return ret; 3777 3778 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 3779 return ret; 3780 3781 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 3782 ret |= RDMA_CORE_PORT_IBA_ROCE; 3783 3784 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 3785 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 3786 3787 return ret; 3788 } 3789 3790 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num, 3791 struct ib_port_immutable *immutable) 3792 { 3793 struct ib_port_attr attr; 3794 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3795 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num); 3796 int err; 3797 3798 immutable->core_cap_flags = get_core_cap_flags(ibdev); 3799 3800 err = ib_query_port(ibdev, port_num, &attr); 3801 if (err) 3802 return err; 3803 3804 immutable->pkey_tbl_len = attr.pkey_tbl_len; 3805 immutable->gid_tbl_len = attr.gid_tbl_len; 3806 immutable->core_cap_flags = get_core_cap_flags(ibdev); 3807 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce)) 3808 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 3809 3810 return 0; 3811 } 3812 3813 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num, 3814 struct ib_port_immutable *immutable) 3815 { 3816 struct ib_port_attr attr; 3817 int err; 3818 3819 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 3820 3821 err = ib_query_port(ibdev, port_num, &attr); 3822 if (err) 3823 return err; 3824 3825 immutable->pkey_tbl_len = attr.pkey_tbl_len; 3826 immutable->gid_tbl_len = attr.gid_tbl_len; 3827 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 3828 3829 return 0; 3830 } 3831 3832 static void get_dev_fw_str(struct ib_device *ibdev, char *str) 3833 { 3834 struct mlx5_ib_dev *dev = 3835 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 3836 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d", 3837 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev), 3838 fw_rev_sub(dev->mdev)); 3839 } 3840 3841 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev) 3842 { 3843 struct mlx5_core_dev *mdev = dev->mdev; 3844 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev, 3845 MLX5_FLOW_NAMESPACE_LAG); 3846 struct mlx5_flow_table *ft; 3847 int err; 3848 3849 if (!ns || !mlx5_lag_is_active(mdev)) 3850 return 0; 3851 3852 err = mlx5_cmd_create_vport_lag(mdev); 3853 if (err) 3854 return err; 3855 3856 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0); 3857 if (IS_ERR(ft)) { 3858 err = PTR_ERR(ft); 3859 goto err_destroy_vport_lag; 3860 } 3861 3862 dev->flow_db->lag_demux_ft = ft; 3863 return 0; 3864 3865 err_destroy_vport_lag: 3866 mlx5_cmd_destroy_vport_lag(mdev); 3867 return err; 3868 } 3869 3870 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev) 3871 { 3872 struct mlx5_core_dev *mdev = dev->mdev; 3873 3874 if (dev->flow_db->lag_demux_ft) { 3875 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft); 3876 dev->flow_db->lag_demux_ft = NULL; 3877 3878 mlx5_cmd_destroy_vport_lag(mdev); 3879 } 3880 } 3881 3882 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num) 3883 { 3884 int err; 3885 3886 dev->roce[port_num].nb.notifier_call = mlx5_netdev_event; 3887 err = register_netdevice_notifier(&dev->roce[port_num].nb); 3888 if (err) { 3889 dev->roce[port_num].nb.notifier_call = NULL; 3890 return err; 3891 } 3892 3893 return 0; 3894 } 3895 3896 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num) 3897 { 3898 if (dev->roce[port_num].nb.notifier_call) { 3899 unregister_netdevice_notifier(&dev->roce[port_num].nb); 3900 dev->roce[port_num].nb.notifier_call = NULL; 3901 } 3902 } 3903 3904 static int mlx5_enable_eth(struct mlx5_ib_dev *dev, u8 port_num) 3905 { 3906 int err; 3907 3908 if (MLX5_CAP_GEN(dev->mdev, roce)) { 3909 err = mlx5_nic_vport_enable_roce(dev->mdev); 3910 if (err) 3911 return err; 3912 } 3913 3914 err = mlx5_eth_lag_init(dev); 3915 if (err) 3916 goto err_disable_roce; 3917 3918 return 0; 3919 3920 err_disable_roce: 3921 if (MLX5_CAP_GEN(dev->mdev, roce)) 3922 mlx5_nic_vport_disable_roce(dev->mdev); 3923 3924 return err; 3925 } 3926 3927 static void mlx5_disable_eth(struct mlx5_ib_dev *dev) 3928 { 3929 mlx5_eth_lag_cleanup(dev); 3930 if (MLX5_CAP_GEN(dev->mdev, roce)) 3931 mlx5_nic_vport_disable_roce(dev->mdev); 3932 } 3933 3934 struct mlx5_ib_counter { 3935 const char *name; 3936 size_t offset; 3937 }; 3938 3939 #define INIT_Q_COUNTER(_name) \ 3940 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)} 3941 3942 static const struct mlx5_ib_counter basic_q_cnts[] = { 3943 INIT_Q_COUNTER(rx_write_requests), 3944 INIT_Q_COUNTER(rx_read_requests), 3945 INIT_Q_COUNTER(rx_atomic_requests), 3946 INIT_Q_COUNTER(out_of_buffer), 3947 }; 3948 3949 static const struct mlx5_ib_counter out_of_seq_q_cnts[] = { 3950 INIT_Q_COUNTER(out_of_sequence), 3951 }; 3952 3953 static const struct mlx5_ib_counter retrans_q_cnts[] = { 3954 INIT_Q_COUNTER(duplicate_request), 3955 INIT_Q_COUNTER(rnr_nak_retry_err), 3956 INIT_Q_COUNTER(packet_seq_err), 3957 INIT_Q_COUNTER(implied_nak_seq_err), 3958 INIT_Q_COUNTER(local_ack_timeout_err), 3959 }; 3960 3961 #define INIT_CONG_COUNTER(_name) \ 3962 { .name = #_name, .offset = \ 3963 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)} 3964 3965 static const struct mlx5_ib_counter cong_cnts[] = { 3966 INIT_CONG_COUNTER(rp_cnp_ignored), 3967 INIT_CONG_COUNTER(rp_cnp_handled), 3968 INIT_CONG_COUNTER(np_ecn_marked_roce_packets), 3969 INIT_CONG_COUNTER(np_cnp_sent), 3970 }; 3971 3972 static const struct mlx5_ib_counter extended_err_cnts[] = { 3973 INIT_Q_COUNTER(resp_local_length_error), 3974 INIT_Q_COUNTER(resp_cqe_error), 3975 INIT_Q_COUNTER(req_cqe_error), 3976 INIT_Q_COUNTER(req_remote_invalid_request), 3977 INIT_Q_COUNTER(req_remote_access_errors), 3978 INIT_Q_COUNTER(resp_remote_access_errors), 3979 INIT_Q_COUNTER(resp_cqe_flush_error), 3980 INIT_Q_COUNTER(req_cqe_flush_error), 3981 }; 3982 3983 static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev) 3984 { 3985 int i; 3986 3987 for (i = 0; i < dev->num_ports; i++) { 3988 if (dev->port[i].cnts.set_id) 3989 mlx5_core_dealloc_q_counter(dev->mdev, 3990 dev->port[i].cnts.set_id); 3991 kfree(dev->port[i].cnts.names); 3992 kfree(dev->port[i].cnts.offsets); 3993 } 3994 } 3995 3996 static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev, 3997 struct mlx5_ib_counters *cnts) 3998 { 3999 u32 num_counters; 4000 4001 num_counters = ARRAY_SIZE(basic_q_cnts); 4002 4003 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) 4004 num_counters += ARRAY_SIZE(out_of_seq_q_cnts); 4005 4006 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) 4007 num_counters += ARRAY_SIZE(retrans_q_cnts); 4008 4009 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) 4010 num_counters += ARRAY_SIZE(extended_err_cnts); 4011 4012 cnts->num_q_counters = num_counters; 4013 4014 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 4015 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts); 4016 num_counters += ARRAY_SIZE(cong_cnts); 4017 } 4018 4019 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL); 4020 if (!cnts->names) 4021 return -ENOMEM; 4022 4023 cnts->offsets = kcalloc(num_counters, 4024 sizeof(cnts->offsets), GFP_KERNEL); 4025 if (!cnts->offsets) 4026 goto err_names; 4027 4028 return 0; 4029 4030 err_names: 4031 kfree(cnts->names); 4032 cnts->names = NULL; 4033 return -ENOMEM; 4034 } 4035 4036 static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev, 4037 const char **names, 4038 size_t *offsets) 4039 { 4040 int i; 4041 int j = 0; 4042 4043 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) { 4044 names[j] = basic_q_cnts[i].name; 4045 offsets[j] = basic_q_cnts[i].offset; 4046 } 4047 4048 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) { 4049 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) { 4050 names[j] = out_of_seq_q_cnts[i].name; 4051 offsets[j] = out_of_seq_q_cnts[i].offset; 4052 } 4053 } 4054 4055 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) { 4056 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) { 4057 names[j] = retrans_q_cnts[i].name; 4058 offsets[j] = retrans_q_cnts[i].offset; 4059 } 4060 } 4061 4062 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) { 4063 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) { 4064 names[j] = extended_err_cnts[i].name; 4065 offsets[j] = extended_err_cnts[i].offset; 4066 } 4067 } 4068 4069 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 4070 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) { 4071 names[j] = cong_cnts[i].name; 4072 offsets[j] = cong_cnts[i].offset; 4073 } 4074 } 4075 } 4076 4077 static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev) 4078 { 4079 int err = 0; 4080 int i; 4081 4082 for (i = 0; i < dev->num_ports; i++) { 4083 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts); 4084 if (err) 4085 goto err_alloc; 4086 4087 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names, 4088 dev->port[i].cnts.offsets); 4089 4090 err = mlx5_core_alloc_q_counter(dev->mdev, 4091 &dev->port[i].cnts.set_id); 4092 if (err) { 4093 mlx5_ib_warn(dev, 4094 "couldn't allocate queue counter for port %d, err %d\n", 4095 i + 1, err); 4096 goto err_alloc; 4097 } 4098 dev->port[i].cnts.set_id_valid = true; 4099 } 4100 4101 return 0; 4102 4103 err_alloc: 4104 mlx5_ib_dealloc_counters(dev); 4105 return err; 4106 } 4107 4108 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev, 4109 u8 port_num) 4110 { 4111 struct mlx5_ib_dev *dev = to_mdev(ibdev); 4112 struct mlx5_ib_port *port = &dev->port[port_num - 1]; 4113 4114 /* We support only per port stats */ 4115 if (port_num == 0) 4116 return NULL; 4117 4118 return rdma_alloc_hw_stats_struct(port->cnts.names, 4119 port->cnts.num_q_counters + 4120 port->cnts.num_cong_counters, 4121 RDMA_HW_STATS_DEFAULT_LIFESPAN); 4122 } 4123 4124 static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev, 4125 struct mlx5_ib_port *port, 4126 struct rdma_hw_stats *stats) 4127 { 4128 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out); 4129 void *out; 4130 __be32 val; 4131 int ret, i; 4132 4133 out = kvzalloc(outlen, GFP_KERNEL); 4134 if (!out) 4135 return -ENOMEM; 4136 4137 ret = mlx5_core_query_q_counter(mdev, 4138 port->cnts.set_id, 0, 4139 out, outlen); 4140 if (ret) 4141 goto free; 4142 4143 for (i = 0; i < port->cnts.num_q_counters; i++) { 4144 val = *(__be32 *)(out + port->cnts.offsets[i]); 4145 stats->value[i] = (u64)be32_to_cpu(val); 4146 } 4147 4148 free: 4149 kvfree(out); 4150 return ret; 4151 } 4152 4153 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev, 4154 struct rdma_hw_stats *stats, 4155 u8 port_num, int index) 4156 { 4157 struct mlx5_ib_dev *dev = to_mdev(ibdev); 4158 struct mlx5_ib_port *port = &dev->port[port_num - 1]; 4159 struct mlx5_core_dev *mdev; 4160 int ret, num_counters; 4161 u8 mdev_port_num; 4162 4163 if (!stats) 4164 return -EINVAL; 4165 4166 num_counters = port->cnts.num_q_counters + port->cnts.num_cong_counters; 4167 4168 /* q_counters are per IB device, query the master mdev */ 4169 ret = mlx5_ib_query_q_counters(dev->mdev, port, stats); 4170 if (ret) 4171 return ret; 4172 4173 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 4174 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, 4175 &mdev_port_num); 4176 if (!mdev) { 4177 /* If port is not affiliated yet, its in down state 4178 * which doesn't have any counters yet, so it would be 4179 * zero. So no need to read from the HCA. 4180 */ 4181 goto done; 4182 } 4183 ret = mlx5_lag_query_cong_counters(dev->mdev, 4184 stats->value + 4185 port->cnts.num_q_counters, 4186 port->cnts.num_cong_counters, 4187 port->cnts.offsets + 4188 port->cnts.num_q_counters); 4189 4190 mlx5_ib_put_native_port_mdev(dev, port_num); 4191 if (ret) 4192 return ret; 4193 } 4194 4195 done: 4196 return num_counters; 4197 } 4198 4199 static void mlx5_ib_free_rdma_netdev(struct net_device *netdev) 4200 { 4201 return mlx5_rdma_netdev_free(netdev); 4202 } 4203 4204 static struct net_device* 4205 mlx5_ib_alloc_rdma_netdev(struct ib_device *hca, 4206 u8 port_num, 4207 enum rdma_netdev_t type, 4208 const char *name, 4209 unsigned char name_assign_type, 4210 void (*setup)(struct net_device *)) 4211 { 4212 struct net_device *netdev; 4213 struct rdma_netdev *rn; 4214 4215 if (type != RDMA_NETDEV_IPOIB) 4216 return ERR_PTR(-EOPNOTSUPP); 4217 4218 netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca, 4219 name, setup); 4220 if (likely(!IS_ERR_OR_NULL(netdev))) { 4221 rn = netdev_priv(netdev); 4222 rn->free_rdma_netdev = mlx5_ib_free_rdma_netdev; 4223 } 4224 return netdev; 4225 } 4226 4227 static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev) 4228 { 4229 if (!dev->delay_drop.dbg) 4230 return; 4231 debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs); 4232 kfree(dev->delay_drop.dbg); 4233 dev->delay_drop.dbg = NULL; 4234 } 4235 4236 static void cancel_delay_drop(struct mlx5_ib_dev *dev) 4237 { 4238 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4239 return; 4240 4241 cancel_work_sync(&dev->delay_drop.delay_drop_work); 4242 delay_drop_debugfs_cleanup(dev); 4243 } 4244 4245 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf, 4246 size_t count, loff_t *pos) 4247 { 4248 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 4249 char lbuf[20]; 4250 int len; 4251 4252 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout); 4253 return simple_read_from_buffer(buf, count, pos, lbuf, len); 4254 } 4255 4256 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf, 4257 size_t count, loff_t *pos) 4258 { 4259 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 4260 u32 timeout; 4261 u32 var; 4262 4263 if (kstrtouint_from_user(buf, count, 0, &var)) 4264 return -EFAULT; 4265 4266 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 4267 1000); 4268 if (timeout != var) 4269 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n", 4270 timeout); 4271 4272 delay_drop->timeout = timeout; 4273 4274 return count; 4275 } 4276 4277 static const struct file_operations fops_delay_drop_timeout = { 4278 .owner = THIS_MODULE, 4279 .open = simple_open, 4280 .write = delay_drop_timeout_write, 4281 .read = delay_drop_timeout_read, 4282 }; 4283 4284 static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev) 4285 { 4286 struct mlx5_ib_dbg_delay_drop *dbg; 4287 4288 if (!mlx5_debugfs_root) 4289 return 0; 4290 4291 dbg = kzalloc(sizeof(*dbg), GFP_KERNEL); 4292 if (!dbg) 4293 return -ENOMEM; 4294 4295 dev->delay_drop.dbg = dbg; 4296 4297 dbg->dir_debugfs = 4298 debugfs_create_dir("delay_drop", 4299 dev->mdev->priv.dbg_root); 4300 if (!dbg->dir_debugfs) 4301 goto out_debugfs; 4302 4303 dbg->events_cnt_debugfs = 4304 debugfs_create_atomic_t("num_timeout_events", 0400, 4305 dbg->dir_debugfs, 4306 &dev->delay_drop.events_cnt); 4307 if (!dbg->events_cnt_debugfs) 4308 goto out_debugfs; 4309 4310 dbg->rqs_cnt_debugfs = 4311 debugfs_create_atomic_t("num_rqs", 0400, 4312 dbg->dir_debugfs, 4313 &dev->delay_drop.rqs_cnt); 4314 if (!dbg->rqs_cnt_debugfs) 4315 goto out_debugfs; 4316 4317 dbg->timeout_debugfs = 4318 debugfs_create_file("timeout", 0600, 4319 dbg->dir_debugfs, 4320 &dev->delay_drop, 4321 &fops_delay_drop_timeout); 4322 if (!dbg->timeout_debugfs) 4323 goto out_debugfs; 4324 4325 return 0; 4326 4327 out_debugfs: 4328 delay_drop_debugfs_cleanup(dev); 4329 return -ENOMEM; 4330 } 4331 4332 static void init_delay_drop(struct mlx5_ib_dev *dev) 4333 { 4334 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4335 return; 4336 4337 mutex_init(&dev->delay_drop.lock); 4338 dev->delay_drop.dev = dev; 4339 dev->delay_drop.activate = false; 4340 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000; 4341 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler); 4342 atomic_set(&dev->delay_drop.rqs_cnt, 0); 4343 atomic_set(&dev->delay_drop.events_cnt, 0); 4344 4345 if (delay_drop_debugfs_init(dev)) 4346 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n"); 4347 } 4348 4349 static const struct cpumask * 4350 mlx5_ib_get_vector_affinity(struct ib_device *ibdev, int comp_vector) 4351 { 4352 struct mlx5_ib_dev *dev = to_mdev(ibdev); 4353 4354 return mlx5_get_vector_affinity(dev->mdev, comp_vector); 4355 } 4356 4357 /* The mlx5_ib_multiport_mutex should be held when calling this function */ 4358 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev, 4359 struct mlx5_ib_multiport_info *mpi) 4360 { 4361 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 4362 struct mlx5_ib_port *port = &ibdev->port[port_num]; 4363 int comps; 4364 int err; 4365 int i; 4366 4367 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num); 4368 4369 spin_lock(&port->mp.mpi_lock); 4370 if (!mpi->ibdev) { 4371 spin_unlock(&port->mp.mpi_lock); 4372 return; 4373 } 4374 mpi->ibdev = NULL; 4375 4376 spin_unlock(&port->mp.mpi_lock); 4377 mlx5_remove_netdev_notifier(ibdev, port_num); 4378 spin_lock(&port->mp.mpi_lock); 4379 4380 comps = mpi->mdev_refcnt; 4381 if (comps) { 4382 mpi->unaffiliate = true; 4383 init_completion(&mpi->unref_comp); 4384 spin_unlock(&port->mp.mpi_lock); 4385 4386 for (i = 0; i < comps; i++) 4387 wait_for_completion(&mpi->unref_comp); 4388 4389 spin_lock(&port->mp.mpi_lock); 4390 mpi->unaffiliate = false; 4391 } 4392 4393 port->mp.mpi = NULL; 4394 4395 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 4396 4397 spin_unlock(&port->mp.mpi_lock); 4398 4399 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev); 4400 4401 mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1); 4402 /* Log an error, still needed to cleanup the pointers and add 4403 * it back to the list. 4404 */ 4405 if (err) 4406 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n", 4407 port_num + 1); 4408 4409 ibdev->roce[port_num].last_port_state = IB_PORT_DOWN; 4410 } 4411 4412 /* The mlx5_ib_multiport_mutex should be held when calling this function */ 4413 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev, 4414 struct mlx5_ib_multiport_info *mpi) 4415 { 4416 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 4417 int err; 4418 4419 spin_lock(&ibdev->port[port_num].mp.mpi_lock); 4420 if (ibdev->port[port_num].mp.mpi) { 4421 mlx5_ib_warn(ibdev, "port %d already affiliated.\n", 4422 port_num + 1); 4423 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 4424 return false; 4425 } 4426 4427 ibdev->port[port_num].mp.mpi = mpi; 4428 mpi->ibdev = ibdev; 4429 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 4430 4431 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev); 4432 if (err) 4433 goto unbind; 4434 4435 err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev)); 4436 if (err) 4437 goto unbind; 4438 4439 err = mlx5_add_netdev_notifier(ibdev, port_num); 4440 if (err) { 4441 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n", 4442 port_num + 1); 4443 goto unbind; 4444 } 4445 4446 err = mlx5_ib_init_cong_debugfs(ibdev, port_num); 4447 if (err) 4448 goto unbind; 4449 4450 return true; 4451 4452 unbind: 4453 mlx5_ib_unbind_slave_port(ibdev, mpi); 4454 return false; 4455 } 4456 4457 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev) 4458 { 4459 int port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4460 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 4461 port_num + 1); 4462 struct mlx5_ib_multiport_info *mpi; 4463 int err; 4464 int i; 4465 4466 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 4467 return 0; 4468 4469 err = mlx5_query_nic_vport_system_image_guid(dev->mdev, 4470 &dev->sys_image_guid); 4471 if (err) 4472 return err; 4473 4474 err = mlx5_nic_vport_enable_roce(dev->mdev); 4475 if (err) 4476 return err; 4477 4478 mutex_lock(&mlx5_ib_multiport_mutex); 4479 for (i = 0; i < dev->num_ports; i++) { 4480 bool bound = false; 4481 4482 /* build a stub multiport info struct for the native port. */ 4483 if (i == port_num) { 4484 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 4485 if (!mpi) { 4486 mutex_unlock(&mlx5_ib_multiport_mutex); 4487 mlx5_nic_vport_disable_roce(dev->mdev); 4488 return -ENOMEM; 4489 } 4490 4491 mpi->is_master = true; 4492 mpi->mdev = dev->mdev; 4493 mpi->sys_image_guid = dev->sys_image_guid; 4494 dev->port[i].mp.mpi = mpi; 4495 mpi->ibdev = dev; 4496 mpi = NULL; 4497 continue; 4498 } 4499 4500 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list, 4501 list) { 4502 if (dev->sys_image_guid == mpi->sys_image_guid && 4503 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) { 4504 bound = mlx5_ib_bind_slave_port(dev, mpi); 4505 } 4506 4507 if (bound) { 4508 dev_dbg(&mpi->mdev->pdev->dev, "removing port from unaffiliated list.\n"); 4509 mlx5_ib_dbg(dev, "port %d bound\n", i + 1); 4510 list_del(&mpi->list); 4511 break; 4512 } 4513 } 4514 if (!bound) { 4515 get_port_caps(dev, i + 1); 4516 mlx5_ib_dbg(dev, "no free port found for port %d\n", 4517 i + 1); 4518 } 4519 } 4520 4521 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list); 4522 mutex_unlock(&mlx5_ib_multiport_mutex); 4523 return err; 4524 } 4525 4526 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev) 4527 { 4528 int port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4529 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 4530 port_num + 1); 4531 int i; 4532 4533 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 4534 return; 4535 4536 mutex_lock(&mlx5_ib_multiport_mutex); 4537 for (i = 0; i < dev->num_ports; i++) { 4538 if (dev->port[i].mp.mpi) { 4539 /* Destroy the native port stub */ 4540 if (i == port_num) { 4541 kfree(dev->port[i].mp.mpi); 4542 dev->port[i].mp.mpi = NULL; 4543 } else { 4544 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1); 4545 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi); 4546 } 4547 } 4548 } 4549 4550 mlx5_ib_dbg(dev, "removing from devlist\n"); 4551 list_del(&dev->ib_dev_list); 4552 mutex_unlock(&mlx5_ib_multiport_mutex); 4553 4554 mlx5_nic_vport_disable_roce(dev->mdev); 4555 } 4556 4557 static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev) 4558 { 4559 mlx5_ib_cleanup_multiport_master(dev); 4560 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 4561 cleanup_srcu_struct(&dev->mr_srcu); 4562 #endif 4563 kfree(dev->port); 4564 } 4565 4566 static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev) 4567 { 4568 struct mlx5_core_dev *mdev = dev->mdev; 4569 const char *name; 4570 int err; 4571 int i; 4572 4573 dev->port = kcalloc(dev->num_ports, sizeof(*dev->port), 4574 GFP_KERNEL); 4575 if (!dev->port) 4576 return -ENOMEM; 4577 4578 for (i = 0; i < dev->num_ports; i++) { 4579 spin_lock_init(&dev->port[i].mp.mpi_lock); 4580 rwlock_init(&dev->roce[i].netdev_lock); 4581 } 4582 4583 err = mlx5_ib_init_multiport_master(dev); 4584 if (err) 4585 goto err_free_port; 4586 4587 if (!mlx5_core_mp_enabled(mdev)) { 4588 int i; 4589 4590 for (i = 1; i <= dev->num_ports; i++) { 4591 err = get_port_caps(dev, i); 4592 if (err) 4593 break; 4594 } 4595 } else { 4596 err = get_port_caps(dev, mlx5_core_native_port_num(mdev)); 4597 } 4598 if (err) 4599 goto err_mp; 4600 4601 if (mlx5_use_mad_ifc(dev)) 4602 get_ext_port_caps(dev); 4603 4604 if (!mlx5_lag_is_active(mdev)) 4605 name = "mlx5_%d"; 4606 else 4607 name = "mlx5_bond_%d"; 4608 4609 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX); 4610 dev->ib_dev.owner = THIS_MODULE; 4611 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 4612 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 4613 dev->ib_dev.phys_port_cnt = dev->num_ports; 4614 dev->ib_dev.num_comp_vectors = 4615 dev->mdev->priv.eq_table.num_comp_vectors; 4616 dev->ib_dev.dev.parent = &mdev->pdev->dev; 4617 4618 mutex_init(&dev->cap_mask_mutex); 4619 INIT_LIST_HEAD(&dev->qp_list); 4620 spin_lock_init(&dev->reset_flow_resource_lock); 4621 4622 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 4623 err = init_srcu_struct(&dev->mr_srcu); 4624 if (err) 4625 goto err_free_port; 4626 #endif 4627 4628 return 0; 4629 err_mp: 4630 mlx5_ib_cleanup_multiport_master(dev); 4631 4632 err_free_port: 4633 kfree(dev->port); 4634 4635 return -ENOMEM; 4636 } 4637 4638 static int mlx5_ib_stage_flow_db_init(struct mlx5_ib_dev *dev) 4639 { 4640 dev->flow_db = kzalloc(sizeof(*dev->flow_db), GFP_KERNEL); 4641 4642 if (!dev->flow_db) 4643 return -ENOMEM; 4644 4645 mutex_init(&dev->flow_db->lock); 4646 4647 return 0; 4648 } 4649 4650 static void mlx5_ib_stage_flow_db_cleanup(struct mlx5_ib_dev *dev) 4651 { 4652 kfree(dev->flow_db); 4653 } 4654 4655 static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev) 4656 { 4657 struct mlx5_core_dev *mdev = dev->mdev; 4658 int err; 4659 4660 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION; 4661 dev->ib_dev.uverbs_cmd_mask = 4662 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | 4663 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | 4664 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | 4665 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | 4666 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | 4667 (1ull << IB_USER_VERBS_CMD_CREATE_AH) | 4668 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) | 4669 (1ull << IB_USER_VERBS_CMD_REG_MR) | 4670 (1ull << IB_USER_VERBS_CMD_REREG_MR) | 4671 (1ull << IB_USER_VERBS_CMD_DEREG_MR) | 4672 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 4673 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | 4674 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) | 4675 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | 4676 (1ull << IB_USER_VERBS_CMD_CREATE_QP) | 4677 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | 4678 (1ull << IB_USER_VERBS_CMD_QUERY_QP) | 4679 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | 4680 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) | 4681 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) | 4682 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | 4683 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | 4684 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | 4685 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | 4686 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) | 4687 (1ull << IB_USER_VERBS_CMD_OPEN_QP); 4688 dev->ib_dev.uverbs_ex_cmd_mask = 4689 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) | 4690 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) | 4691 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) | 4692 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP) | 4693 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ); 4694 4695 dev->ib_dev.query_device = mlx5_ib_query_device; 4696 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer; 4697 dev->ib_dev.query_gid = mlx5_ib_query_gid; 4698 dev->ib_dev.add_gid = mlx5_ib_add_gid; 4699 dev->ib_dev.del_gid = mlx5_ib_del_gid; 4700 dev->ib_dev.query_pkey = mlx5_ib_query_pkey; 4701 dev->ib_dev.modify_device = mlx5_ib_modify_device; 4702 dev->ib_dev.modify_port = mlx5_ib_modify_port; 4703 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext; 4704 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext; 4705 dev->ib_dev.mmap = mlx5_ib_mmap; 4706 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd; 4707 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd; 4708 dev->ib_dev.create_ah = mlx5_ib_create_ah; 4709 dev->ib_dev.query_ah = mlx5_ib_query_ah; 4710 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah; 4711 dev->ib_dev.create_srq = mlx5_ib_create_srq; 4712 dev->ib_dev.modify_srq = mlx5_ib_modify_srq; 4713 dev->ib_dev.query_srq = mlx5_ib_query_srq; 4714 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq; 4715 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv; 4716 dev->ib_dev.create_qp = mlx5_ib_create_qp; 4717 dev->ib_dev.modify_qp = mlx5_ib_modify_qp; 4718 dev->ib_dev.query_qp = mlx5_ib_query_qp; 4719 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp; 4720 dev->ib_dev.post_send = mlx5_ib_post_send; 4721 dev->ib_dev.post_recv = mlx5_ib_post_recv; 4722 dev->ib_dev.create_cq = mlx5_ib_create_cq; 4723 dev->ib_dev.modify_cq = mlx5_ib_modify_cq; 4724 dev->ib_dev.resize_cq = mlx5_ib_resize_cq; 4725 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq; 4726 dev->ib_dev.poll_cq = mlx5_ib_poll_cq; 4727 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq; 4728 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr; 4729 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr; 4730 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr; 4731 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr; 4732 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach; 4733 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach; 4734 dev->ib_dev.process_mad = mlx5_ib_process_mad; 4735 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr; 4736 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg; 4737 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status; 4738 dev->ib_dev.get_dev_fw_str = get_dev_fw_str; 4739 dev->ib_dev.get_vector_affinity = mlx5_ib_get_vector_affinity; 4740 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads)) 4741 dev->ib_dev.alloc_rdma_netdev = mlx5_ib_alloc_rdma_netdev; 4742 4743 if (mlx5_core_is_pf(mdev)) { 4744 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config; 4745 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state; 4746 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats; 4747 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid; 4748 } 4749 4750 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext; 4751 4752 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence)); 4753 4754 if (MLX5_CAP_GEN(mdev, imaicl)) { 4755 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw; 4756 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw; 4757 dev->ib_dev.uverbs_cmd_mask |= 4758 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) | 4759 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW); 4760 } 4761 4762 if (MLX5_CAP_GEN(mdev, xrc)) { 4763 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd; 4764 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd; 4765 dev->ib_dev.uverbs_cmd_mask |= 4766 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) | 4767 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD); 4768 } 4769 4770 dev->ib_dev.create_flow = mlx5_ib_create_flow; 4771 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow; 4772 dev->ib_dev.uverbs_ex_cmd_mask |= 4773 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) | 4774 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW); 4775 4776 err = init_node_data(dev); 4777 if (err) 4778 return err; 4779 4780 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && 4781 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) || 4782 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 4783 mutex_init(&dev->lb_mutex); 4784 4785 return 0; 4786 } 4787 4788 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev) 4789 { 4790 dev->ib_dev.get_port_immutable = mlx5_port_immutable; 4791 dev->ib_dev.query_port = mlx5_ib_query_port; 4792 4793 return 0; 4794 } 4795 4796 static int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev) 4797 { 4798 dev->ib_dev.get_port_immutable = mlx5_port_rep_immutable; 4799 dev->ib_dev.query_port = mlx5_ib_rep_query_port; 4800 4801 return 0; 4802 } 4803 4804 static int mlx5_ib_stage_common_roce_init(struct mlx5_ib_dev *dev, 4805 u8 port_num) 4806 { 4807 int i; 4808 4809 for (i = 0; i < dev->num_ports; i++) { 4810 dev->roce[i].dev = dev; 4811 dev->roce[i].native_port_num = i + 1; 4812 dev->roce[i].last_port_state = IB_PORT_DOWN; 4813 } 4814 4815 dev->ib_dev.get_netdev = mlx5_ib_get_netdev; 4816 dev->ib_dev.create_wq = mlx5_ib_create_wq; 4817 dev->ib_dev.modify_wq = mlx5_ib_modify_wq; 4818 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq; 4819 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table; 4820 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table; 4821 4822 dev->ib_dev.uverbs_ex_cmd_mask |= 4823 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) | 4824 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) | 4825 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) | 4826 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) | 4827 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL); 4828 4829 return mlx5_add_netdev_notifier(dev, port_num); 4830 } 4831 4832 static void mlx5_ib_stage_common_roce_cleanup(struct mlx5_ib_dev *dev) 4833 { 4834 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4835 4836 mlx5_remove_netdev_notifier(dev, port_num); 4837 } 4838 4839 int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev) 4840 { 4841 struct mlx5_core_dev *mdev = dev->mdev; 4842 enum rdma_link_layer ll; 4843 int port_type_cap; 4844 int err = 0; 4845 u8 port_num; 4846 4847 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4848 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4849 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4850 4851 if (ll == IB_LINK_LAYER_ETHERNET) 4852 err = mlx5_ib_stage_common_roce_init(dev, port_num); 4853 4854 return err; 4855 } 4856 4857 void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev) 4858 { 4859 mlx5_ib_stage_common_roce_cleanup(dev); 4860 } 4861 4862 static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev) 4863 { 4864 struct mlx5_core_dev *mdev = dev->mdev; 4865 enum rdma_link_layer ll; 4866 int port_type_cap; 4867 u8 port_num; 4868 int err; 4869 4870 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4871 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4872 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4873 4874 if (ll == IB_LINK_LAYER_ETHERNET) { 4875 err = mlx5_ib_stage_common_roce_init(dev, port_num); 4876 if (err) 4877 return err; 4878 4879 err = mlx5_enable_eth(dev, port_num); 4880 if (err) 4881 goto cleanup; 4882 } 4883 4884 return 0; 4885 cleanup: 4886 mlx5_ib_stage_common_roce_cleanup(dev); 4887 4888 return err; 4889 } 4890 4891 static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev) 4892 { 4893 struct mlx5_core_dev *mdev = dev->mdev; 4894 enum rdma_link_layer ll; 4895 int port_type_cap; 4896 u8 port_num; 4897 4898 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4899 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4900 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4901 4902 if (ll == IB_LINK_LAYER_ETHERNET) { 4903 mlx5_disable_eth(dev); 4904 mlx5_ib_stage_common_roce_cleanup(dev); 4905 } 4906 } 4907 4908 static int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev) 4909 { 4910 return create_dev_resources(&dev->devr); 4911 } 4912 4913 static void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev) 4914 { 4915 destroy_dev_resources(&dev->devr); 4916 } 4917 4918 static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev) 4919 { 4920 mlx5_ib_internal_fill_odp_caps(dev); 4921 4922 return mlx5_ib_odp_init_one(dev); 4923 } 4924 4925 static int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev) 4926 { 4927 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) { 4928 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats; 4929 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats; 4930 4931 return mlx5_ib_alloc_counters(dev); 4932 } 4933 4934 return 0; 4935 } 4936 4937 static void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev) 4938 { 4939 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) 4940 mlx5_ib_dealloc_counters(dev); 4941 } 4942 4943 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev) 4944 { 4945 return mlx5_ib_init_cong_debugfs(dev, 4946 mlx5_core_native_port_num(dev->mdev) - 1); 4947 } 4948 4949 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev) 4950 { 4951 mlx5_ib_cleanup_cong_debugfs(dev, 4952 mlx5_core_native_port_num(dev->mdev) - 1); 4953 } 4954 4955 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev) 4956 { 4957 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev); 4958 if (!dev->mdev->priv.uar) 4959 return -ENOMEM; 4960 return 0; 4961 } 4962 4963 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev) 4964 { 4965 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar); 4966 } 4967 4968 static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev) 4969 { 4970 int err; 4971 4972 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false); 4973 if (err) 4974 return err; 4975 4976 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true); 4977 if (err) 4978 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 4979 4980 return err; 4981 } 4982 4983 static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev) 4984 { 4985 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 4986 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4987 } 4988 4989 static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev) 4990 { 4991 return ib_register_device(&dev->ib_dev, NULL); 4992 } 4993 4994 static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev) 4995 { 4996 ib_unregister_device(&dev->ib_dev); 4997 } 4998 4999 static int mlx5_ib_stage_umr_res_init(struct mlx5_ib_dev *dev) 5000 { 5001 return create_umr_res(dev); 5002 } 5003 5004 static void mlx5_ib_stage_umr_res_cleanup(struct mlx5_ib_dev *dev) 5005 { 5006 destroy_umrc_res(dev); 5007 } 5008 5009 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev) 5010 { 5011 init_delay_drop(dev); 5012 5013 return 0; 5014 } 5015 5016 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev) 5017 { 5018 cancel_delay_drop(dev); 5019 } 5020 5021 static int mlx5_ib_stage_class_attr_init(struct mlx5_ib_dev *dev) 5022 { 5023 int err; 5024 int i; 5025 5026 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) { 5027 err = device_create_file(&dev->ib_dev.dev, 5028 mlx5_class_attributes[i]); 5029 if (err) 5030 return err; 5031 } 5032 5033 return 0; 5034 } 5035 5036 static int mlx5_ib_stage_rep_reg_init(struct mlx5_ib_dev *dev) 5037 { 5038 mlx5_ib_register_vport_reps(dev); 5039 5040 return 0; 5041 } 5042 5043 static void mlx5_ib_stage_rep_reg_cleanup(struct mlx5_ib_dev *dev) 5044 { 5045 mlx5_ib_unregister_vport_reps(dev); 5046 } 5047 5048 static void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 5049 const struct mlx5_ib_profile *profile, 5050 int stage) 5051 { 5052 /* Number of stages to cleanup */ 5053 while (stage) { 5054 stage--; 5055 if (profile->stage[stage].cleanup) 5056 profile->stage[stage].cleanup(dev); 5057 } 5058 5059 ib_dealloc_device((struct ib_device *)dev); 5060 } 5061 5062 static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev, u8 port_num); 5063 5064 static void *__mlx5_ib_add(struct mlx5_core_dev *mdev, 5065 const struct mlx5_ib_profile *profile) 5066 { 5067 struct mlx5_ib_dev *dev; 5068 int err; 5069 int i; 5070 5071 printk_once(KERN_INFO "%s", mlx5_version); 5072 5073 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev)); 5074 if (!dev) 5075 return NULL; 5076 5077 dev->mdev = mdev; 5078 dev->num_ports = max(MLX5_CAP_GEN(mdev, num_ports), 5079 MLX5_CAP_GEN(mdev, num_vhca_ports)); 5080 5081 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) { 5082 if (profile->stage[i].init) { 5083 err = profile->stage[i].init(dev); 5084 if (err) 5085 goto err_out; 5086 } 5087 } 5088 5089 dev->profile = profile; 5090 dev->ib_active = true; 5091 5092 return dev; 5093 5094 err_out: 5095 __mlx5_ib_remove(dev, profile, i); 5096 5097 return NULL; 5098 } 5099 5100 static const struct mlx5_ib_profile pf_profile = { 5101 STAGE_CREATE(MLX5_IB_STAGE_INIT, 5102 mlx5_ib_stage_init_init, 5103 mlx5_ib_stage_init_cleanup), 5104 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB, 5105 mlx5_ib_stage_flow_db_init, 5106 mlx5_ib_stage_flow_db_cleanup), 5107 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 5108 mlx5_ib_stage_caps_init, 5109 NULL), 5110 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 5111 mlx5_ib_stage_non_default_cb, 5112 NULL), 5113 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 5114 mlx5_ib_stage_roce_init, 5115 mlx5_ib_stage_roce_cleanup), 5116 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 5117 mlx5_ib_stage_dev_res_init, 5118 mlx5_ib_stage_dev_res_cleanup), 5119 STAGE_CREATE(MLX5_IB_STAGE_ODP, 5120 mlx5_ib_stage_odp_init, 5121 NULL), 5122 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 5123 mlx5_ib_stage_counters_init, 5124 mlx5_ib_stage_counters_cleanup), 5125 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 5126 mlx5_ib_stage_cong_debugfs_init, 5127 mlx5_ib_stage_cong_debugfs_cleanup), 5128 STAGE_CREATE(MLX5_IB_STAGE_UAR, 5129 mlx5_ib_stage_uar_init, 5130 mlx5_ib_stage_uar_cleanup), 5131 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 5132 mlx5_ib_stage_bfrag_init, 5133 mlx5_ib_stage_bfrag_cleanup), 5134 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 5135 mlx5_ib_stage_ib_reg_init, 5136 mlx5_ib_stage_ib_reg_cleanup), 5137 STAGE_CREATE(MLX5_IB_STAGE_UMR_RESOURCES, 5138 mlx5_ib_stage_umr_res_init, 5139 mlx5_ib_stage_umr_res_cleanup), 5140 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP, 5141 mlx5_ib_stage_delay_drop_init, 5142 mlx5_ib_stage_delay_drop_cleanup), 5143 STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR, 5144 mlx5_ib_stage_class_attr_init, 5145 NULL), 5146 }; 5147 5148 static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev, u8 port_num) 5149 { 5150 struct mlx5_ib_multiport_info *mpi; 5151 struct mlx5_ib_dev *dev; 5152 bool bound = false; 5153 int err; 5154 5155 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 5156 if (!mpi) 5157 return NULL; 5158 5159 mpi->mdev = mdev; 5160 5161 err = mlx5_query_nic_vport_system_image_guid(mdev, 5162 &mpi->sys_image_guid); 5163 if (err) { 5164 kfree(mpi); 5165 return NULL; 5166 } 5167 5168 mutex_lock(&mlx5_ib_multiport_mutex); 5169 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) { 5170 if (dev->sys_image_guid == mpi->sys_image_guid) 5171 bound = mlx5_ib_bind_slave_port(dev, mpi); 5172 5173 if (bound) { 5174 rdma_roce_rescan_device(&dev->ib_dev); 5175 break; 5176 } 5177 } 5178 5179 if (!bound) { 5180 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 5181 dev_dbg(&mdev->pdev->dev, "no suitable IB device found to bind to, added to unaffiliated list.\n"); 5182 } else { 5183 mlx5_ib_dbg(dev, "bound port %u\n", port_num + 1); 5184 } 5185 mutex_unlock(&mlx5_ib_multiport_mutex); 5186 5187 return mpi; 5188 } 5189 5190 static void *mlx5_ib_add(struct mlx5_core_dev *mdev) 5191 { 5192 enum rdma_link_layer ll; 5193 int port_type_cap; 5194 5195 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 5196 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 5197 5198 if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET) { 5199 u8 port_num = mlx5_core_native_port_num(mdev) - 1; 5200 5201 return mlx5_ib_add_slave_port(mdev, port_num); 5202 } 5203 5204 return __mlx5_ib_add(mdev, &pf_profile); 5205 } 5206 5207 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context) 5208 { 5209 struct mlx5_ib_multiport_info *mpi; 5210 struct mlx5_ib_dev *dev; 5211 5212 if (mlx5_core_is_mp_slave(mdev)) { 5213 mpi = context; 5214 mutex_lock(&mlx5_ib_multiport_mutex); 5215 if (mpi->ibdev) 5216 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi); 5217 list_del(&mpi->list); 5218 mutex_unlock(&mlx5_ib_multiport_mutex); 5219 return; 5220 } 5221 5222 dev = context; 5223 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX); 5224 } 5225 5226 static struct mlx5_interface mlx5_ib_interface = { 5227 .add = mlx5_ib_add, 5228 .remove = mlx5_ib_remove, 5229 .event = mlx5_ib_event, 5230 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 5231 .pfault = mlx5_ib_pfault, 5232 #endif 5233 .protocol = MLX5_INTERFACE_PROTOCOL_IB, 5234 }; 5235 5236 static int __init mlx5_ib_init(void) 5237 { 5238 int err; 5239 5240 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0); 5241 if (!mlx5_ib_event_wq) 5242 return -ENOMEM; 5243 5244 mlx5_ib_odp_init(); 5245 5246 err = mlx5_register_interface(&mlx5_ib_interface); 5247 5248 return err; 5249 } 5250 5251 static void __exit mlx5_ib_cleanup(void) 5252 { 5253 mlx5_unregister_interface(&mlx5_ib_interface); 5254 destroy_workqueue(mlx5_ib_event_wq); 5255 } 5256 5257 module_init(mlx5_ib_init); 5258 module_exit(mlx5_ib_cleanup); 5259