1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/debugfs.h> 34 #include <linux/highmem.h> 35 #include <linux/module.h> 36 #include <linux/init.h> 37 #include <linux/errno.h> 38 #include <linux/pci.h> 39 #include <linux/dma-mapping.h> 40 #include <linux/slab.h> 41 #include <linux/bitmap.h> 42 #include <linux/sched.h> 43 #include <linux/sched/mm.h> 44 #include <linux/sched/task.h> 45 #include <linux/delay.h> 46 #include <rdma/ib_user_verbs.h> 47 #include <rdma/ib_addr.h> 48 #include <rdma/ib_cache.h> 49 #include <linux/mlx5/port.h> 50 #include <linux/mlx5/vport.h> 51 #include <linux/mlx5/fs.h> 52 #include <linux/mlx5/eswitch.h> 53 #include <linux/list.h> 54 #include <rdma/ib_smi.h> 55 #include <rdma/ib_umem.h> 56 #include <rdma/lag.h> 57 #include <linux/in.h> 58 #include <linux/etherdevice.h> 59 #include "mlx5_ib.h" 60 #include "ib_rep.h" 61 #include "cmd.h" 62 #include "srq.h" 63 #include "qp.h" 64 #include "wr.h" 65 #include <linux/mlx5/fs_helpers.h> 66 #include <linux/mlx5/accel.h> 67 #include <rdma/uverbs_std_types.h> 68 #include <rdma/mlx5_user_ioctl_verbs.h> 69 #include <rdma/mlx5_user_ioctl_cmds.h> 70 #include <rdma/ib_umem_odp.h> 71 72 #define UVERBS_MODULE_NAME mlx5_ib 73 #include <rdma/uverbs_named_ioctl.h> 74 75 #define DRIVER_NAME "mlx5_ib" 76 #define DRIVER_VERSION "5.0-0" 77 78 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 79 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver"); 80 MODULE_LICENSE("Dual BSD/GPL"); 81 82 static char mlx5_version[] = 83 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v" 84 DRIVER_VERSION "\n"; 85 86 struct mlx5_ib_event_work { 87 struct work_struct work; 88 union { 89 struct mlx5_ib_dev *dev; 90 struct mlx5_ib_multiport_info *mpi; 91 }; 92 bool is_slave; 93 unsigned int event; 94 void *param; 95 }; 96 97 enum { 98 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 99 }; 100 101 static struct workqueue_struct *mlx5_ib_event_wq; 102 static LIST_HEAD(mlx5_ib_unaffiliated_port_list); 103 static LIST_HEAD(mlx5_ib_dev_list); 104 /* 105 * This mutex should be held when accessing either of the above lists 106 */ 107 static DEFINE_MUTEX(mlx5_ib_multiport_mutex); 108 109 /* We can't use an array for xlt_emergency_page because dma_map_single 110 * doesn't work on kernel modules memory 111 */ 112 static unsigned long xlt_emergency_page; 113 static struct mutex xlt_emergency_page_mutex; 114 115 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi) 116 { 117 struct mlx5_ib_dev *dev; 118 119 mutex_lock(&mlx5_ib_multiport_mutex); 120 dev = mpi->ibdev; 121 mutex_unlock(&mlx5_ib_multiport_mutex); 122 return dev; 123 } 124 125 static enum rdma_link_layer 126 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 127 { 128 switch (port_type_cap) { 129 case MLX5_CAP_PORT_TYPE_IB: 130 return IB_LINK_LAYER_INFINIBAND; 131 case MLX5_CAP_PORT_TYPE_ETH: 132 return IB_LINK_LAYER_ETHERNET; 133 default: 134 return IB_LINK_LAYER_UNSPECIFIED; 135 } 136 } 137 138 static enum rdma_link_layer 139 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num) 140 { 141 struct mlx5_ib_dev *dev = to_mdev(device); 142 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 143 144 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 145 } 146 147 static int get_port_state(struct ib_device *ibdev, 148 u8 port_num, 149 enum ib_port_state *state) 150 { 151 struct ib_port_attr attr; 152 int ret; 153 154 memset(&attr, 0, sizeof(attr)); 155 ret = ibdev->ops.query_port(ibdev, port_num, &attr); 156 if (!ret) 157 *state = attr.state; 158 return ret; 159 } 160 161 static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev, 162 struct net_device *ndev, 163 u8 *port_num) 164 { 165 struct mlx5_eswitch *esw = dev->mdev->priv.eswitch; 166 struct net_device *rep_ndev; 167 struct mlx5_ib_port *port; 168 int i; 169 170 for (i = 0; i < dev->num_ports; i++) { 171 port = &dev->port[i]; 172 if (!port->rep) 173 continue; 174 175 read_lock(&port->roce.netdev_lock); 176 rep_ndev = mlx5_ib_get_rep_netdev(esw, 177 port->rep->vport); 178 if (rep_ndev == ndev) { 179 read_unlock(&port->roce.netdev_lock); 180 *port_num = i + 1; 181 return &port->roce; 182 } 183 read_unlock(&port->roce.netdev_lock); 184 } 185 186 return NULL; 187 } 188 189 static int mlx5_netdev_event(struct notifier_block *this, 190 unsigned long event, void *ptr) 191 { 192 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb); 193 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 194 u8 port_num = roce->native_port_num; 195 struct mlx5_core_dev *mdev; 196 struct mlx5_ib_dev *ibdev; 197 198 ibdev = roce->dev; 199 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 200 if (!mdev) 201 return NOTIFY_DONE; 202 203 switch (event) { 204 case NETDEV_REGISTER: 205 /* Should already be registered during the load */ 206 if (ibdev->is_rep) 207 break; 208 write_lock(&roce->netdev_lock); 209 if (ndev->dev.parent == mdev->device) 210 roce->netdev = ndev; 211 write_unlock(&roce->netdev_lock); 212 break; 213 214 case NETDEV_UNREGISTER: 215 /* In case of reps, ib device goes away before the netdevs */ 216 write_lock(&roce->netdev_lock); 217 if (roce->netdev == ndev) 218 roce->netdev = NULL; 219 write_unlock(&roce->netdev_lock); 220 break; 221 222 case NETDEV_CHANGE: 223 case NETDEV_UP: 224 case NETDEV_DOWN: { 225 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev); 226 struct net_device *upper = NULL; 227 228 if (lag_ndev) { 229 upper = netdev_master_upper_dev_get(lag_ndev); 230 dev_put(lag_ndev); 231 } 232 233 if (ibdev->is_rep) 234 roce = mlx5_get_rep_roce(ibdev, ndev, &port_num); 235 if (!roce) 236 return NOTIFY_DONE; 237 if ((upper == ndev || (!upper && ndev == roce->netdev)) 238 && ibdev->ib_active) { 239 struct ib_event ibev = { }; 240 enum ib_port_state port_state; 241 242 if (get_port_state(&ibdev->ib_dev, port_num, 243 &port_state)) 244 goto done; 245 246 if (roce->last_port_state == port_state) 247 goto done; 248 249 roce->last_port_state = port_state; 250 ibev.device = &ibdev->ib_dev; 251 if (port_state == IB_PORT_DOWN) 252 ibev.event = IB_EVENT_PORT_ERR; 253 else if (port_state == IB_PORT_ACTIVE) 254 ibev.event = IB_EVENT_PORT_ACTIVE; 255 else 256 goto done; 257 258 ibev.element.port_num = port_num; 259 ib_dispatch_event(&ibev); 260 } 261 break; 262 } 263 264 default: 265 break; 266 } 267 done: 268 mlx5_ib_put_native_port_mdev(ibdev, port_num); 269 return NOTIFY_DONE; 270 } 271 272 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device, 273 u8 port_num) 274 { 275 struct mlx5_ib_dev *ibdev = to_mdev(device); 276 struct net_device *ndev; 277 struct mlx5_core_dev *mdev; 278 279 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 280 if (!mdev) 281 return NULL; 282 283 ndev = mlx5_lag_get_roce_netdev(mdev); 284 if (ndev) 285 goto out; 286 287 /* Ensure ndev does not disappear before we invoke dev_hold() 288 */ 289 read_lock(&ibdev->port[port_num - 1].roce.netdev_lock); 290 ndev = ibdev->port[port_num - 1].roce.netdev; 291 if (ndev) 292 dev_hold(ndev); 293 read_unlock(&ibdev->port[port_num - 1].roce.netdev_lock); 294 295 out: 296 mlx5_ib_put_native_port_mdev(ibdev, port_num); 297 return ndev; 298 } 299 300 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev, 301 u8 ib_port_num, 302 u8 *native_port_num) 303 { 304 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 305 ib_port_num); 306 struct mlx5_core_dev *mdev = NULL; 307 struct mlx5_ib_multiport_info *mpi; 308 struct mlx5_ib_port *port; 309 310 if (!mlx5_core_mp_enabled(ibdev->mdev) || 311 ll != IB_LINK_LAYER_ETHERNET) { 312 if (native_port_num) 313 *native_port_num = ib_port_num; 314 return ibdev->mdev; 315 } 316 317 if (native_port_num) 318 *native_port_num = 1; 319 320 port = &ibdev->port[ib_port_num - 1]; 321 if (!port) 322 return NULL; 323 324 spin_lock(&port->mp.mpi_lock); 325 mpi = ibdev->port[ib_port_num - 1].mp.mpi; 326 if (mpi && !mpi->unaffiliate) { 327 mdev = mpi->mdev; 328 /* If it's the master no need to refcount, it'll exist 329 * as long as the ib_dev exists. 330 */ 331 if (!mpi->is_master) 332 mpi->mdev_refcnt++; 333 } 334 spin_unlock(&port->mp.mpi_lock); 335 336 return mdev; 337 } 338 339 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num) 340 { 341 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 342 port_num); 343 struct mlx5_ib_multiport_info *mpi; 344 struct mlx5_ib_port *port; 345 346 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 347 return; 348 349 port = &ibdev->port[port_num - 1]; 350 351 spin_lock(&port->mp.mpi_lock); 352 mpi = ibdev->port[port_num - 1].mp.mpi; 353 if (mpi->is_master) 354 goto out; 355 356 mpi->mdev_refcnt--; 357 if (mpi->unaffiliate) 358 complete(&mpi->unref_comp); 359 out: 360 spin_unlock(&port->mp.mpi_lock); 361 } 362 363 static int translate_eth_legacy_proto_oper(u32 eth_proto_oper, u8 *active_speed, 364 u8 *active_width) 365 { 366 switch (eth_proto_oper) { 367 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII): 368 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX): 369 case MLX5E_PROT_MASK(MLX5E_100BASE_TX): 370 case MLX5E_PROT_MASK(MLX5E_1000BASE_T): 371 *active_width = IB_WIDTH_1X; 372 *active_speed = IB_SPEED_SDR; 373 break; 374 case MLX5E_PROT_MASK(MLX5E_10GBASE_T): 375 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4): 376 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4): 377 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR): 378 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR): 379 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR): 380 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER): 381 *active_width = IB_WIDTH_1X; 382 *active_speed = IB_SPEED_QDR; 383 break; 384 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR): 385 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR): 386 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR): 387 *active_width = IB_WIDTH_1X; 388 *active_speed = IB_SPEED_EDR; 389 break; 390 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4): 391 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4): 392 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4): 393 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4): 394 *active_width = IB_WIDTH_4X; 395 *active_speed = IB_SPEED_QDR; 396 break; 397 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2): 398 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2): 399 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2): 400 *active_width = IB_WIDTH_1X; 401 *active_speed = IB_SPEED_HDR; 402 break; 403 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4): 404 *active_width = IB_WIDTH_4X; 405 *active_speed = IB_SPEED_FDR; 406 break; 407 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4): 408 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4): 409 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4): 410 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4): 411 *active_width = IB_WIDTH_4X; 412 *active_speed = IB_SPEED_EDR; 413 break; 414 default: 415 return -EINVAL; 416 } 417 418 return 0; 419 } 420 421 static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u8 *active_speed, 422 u8 *active_width) 423 { 424 switch (eth_proto_oper) { 425 case MLX5E_PROT_MASK(MLX5E_SGMII_100M): 426 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII): 427 *active_width = IB_WIDTH_1X; 428 *active_speed = IB_SPEED_SDR; 429 break; 430 case MLX5E_PROT_MASK(MLX5E_5GBASE_R): 431 *active_width = IB_WIDTH_1X; 432 *active_speed = IB_SPEED_DDR; 433 break; 434 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1): 435 *active_width = IB_WIDTH_1X; 436 *active_speed = IB_SPEED_QDR; 437 break; 438 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4): 439 *active_width = IB_WIDTH_4X; 440 *active_speed = IB_SPEED_QDR; 441 break; 442 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR): 443 *active_width = IB_WIDTH_1X; 444 *active_speed = IB_SPEED_EDR; 445 break; 446 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2): 447 *active_width = IB_WIDTH_2X; 448 *active_speed = IB_SPEED_EDR; 449 break; 450 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR): 451 *active_width = IB_WIDTH_1X; 452 *active_speed = IB_SPEED_HDR; 453 break; 454 case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4): 455 *active_width = IB_WIDTH_4X; 456 *active_speed = IB_SPEED_EDR; 457 break; 458 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2): 459 *active_width = IB_WIDTH_2X; 460 *active_speed = IB_SPEED_HDR; 461 break; 462 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4): 463 *active_width = IB_WIDTH_4X; 464 *active_speed = IB_SPEED_HDR; 465 break; 466 default: 467 return -EINVAL; 468 } 469 470 return 0; 471 } 472 473 static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed, 474 u8 *active_width, bool ext) 475 { 476 return ext ? 477 translate_eth_ext_proto_oper(eth_proto_oper, active_speed, 478 active_width) : 479 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed, 480 active_width); 481 } 482 483 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num, 484 struct ib_port_attr *props) 485 { 486 struct mlx5_ib_dev *dev = to_mdev(device); 487 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0}; 488 struct mlx5_core_dev *mdev; 489 struct net_device *ndev, *upper; 490 enum ib_mtu ndev_ib_mtu; 491 bool put_mdev = true; 492 u16 qkey_viol_cntr; 493 u32 eth_prot_oper; 494 u8 mdev_port_num; 495 bool ext; 496 int err; 497 498 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 499 if (!mdev) { 500 /* This means the port isn't affiliated yet. Get the 501 * info for the master port instead. 502 */ 503 put_mdev = false; 504 mdev = dev->mdev; 505 mdev_port_num = 1; 506 port_num = 1; 507 } 508 509 /* Possible bad flows are checked before filling out props so in case 510 * of an error it will still be zeroed out. 511 * Use native port in case of reps 512 */ 513 if (dev->is_rep) 514 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 515 1); 516 else 517 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 518 mdev_port_num); 519 if (err) 520 goto out; 521 ext = MLX5_CAP_PCAM_FEATURE(dev->mdev, ptys_extended_ethernet); 522 eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper); 523 524 props->active_width = IB_WIDTH_4X; 525 props->active_speed = IB_SPEED_QDR; 526 527 translate_eth_proto_oper(eth_prot_oper, &props->active_speed, 528 &props->active_width, ext); 529 530 props->port_cap_flags |= IB_PORT_CM_SUP; 531 props->ip_gids = true; 532 533 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 534 roce_address_table_size); 535 props->max_mtu = IB_MTU_4096; 536 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 537 props->pkey_tbl_len = 1; 538 props->state = IB_PORT_DOWN; 539 props->phys_state = IB_PORT_PHYS_STATE_DISABLED; 540 541 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr); 542 props->qkey_viol_cntr = qkey_viol_cntr; 543 544 /* If this is a stub query for an unaffiliated port stop here */ 545 if (!put_mdev) 546 goto out; 547 548 ndev = mlx5_ib_get_netdev(device, port_num); 549 if (!ndev) 550 goto out; 551 552 if (dev->lag_active) { 553 rcu_read_lock(); 554 upper = netdev_master_upper_dev_get_rcu(ndev); 555 if (upper) { 556 dev_put(ndev); 557 ndev = upper; 558 dev_hold(ndev); 559 } 560 rcu_read_unlock(); 561 } 562 563 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 564 props->state = IB_PORT_ACTIVE; 565 props->phys_state = IB_PORT_PHYS_STATE_LINK_UP; 566 } 567 568 ndev_ib_mtu = iboe_get_mtu(ndev->mtu); 569 570 dev_put(ndev); 571 572 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 573 out: 574 if (put_mdev) 575 mlx5_ib_put_native_port_mdev(dev, port_num); 576 return err; 577 } 578 579 static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num, 580 unsigned int index, const union ib_gid *gid, 581 const struct ib_gid_attr *attr) 582 { 583 enum ib_gid_type gid_type = IB_GID_TYPE_IB; 584 u16 vlan_id = 0xffff; 585 u8 roce_version = 0; 586 u8 roce_l3_type = 0; 587 u8 mac[ETH_ALEN]; 588 int ret; 589 590 if (gid) { 591 gid_type = attr->gid_type; 592 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]); 593 if (ret) 594 return ret; 595 } 596 597 switch (gid_type) { 598 case IB_GID_TYPE_IB: 599 roce_version = MLX5_ROCE_VERSION_1; 600 break; 601 case IB_GID_TYPE_ROCE_UDP_ENCAP: 602 roce_version = MLX5_ROCE_VERSION_2; 603 if (ipv6_addr_v4mapped((void *)gid)) 604 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4; 605 else 606 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6; 607 break; 608 609 default: 610 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type); 611 } 612 613 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version, 614 roce_l3_type, gid->raw, mac, 615 vlan_id < VLAN_CFI_MASK, vlan_id, 616 port_num); 617 } 618 619 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr, 620 __always_unused void **context) 621 { 622 return set_roce_addr(to_mdev(attr->device), attr->port_num, 623 attr->index, &attr->gid, attr); 624 } 625 626 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr, 627 __always_unused void **context) 628 { 629 return set_roce_addr(to_mdev(attr->device), attr->port_num, 630 attr->index, NULL, NULL); 631 } 632 633 __be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev, 634 const struct ib_gid_attr *attr) 635 { 636 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 637 return 0; 638 639 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 640 } 641 642 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 643 { 644 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 645 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 646 return 0; 647 } 648 649 enum { 650 MLX5_VPORT_ACCESS_METHOD_MAD, 651 MLX5_VPORT_ACCESS_METHOD_HCA, 652 MLX5_VPORT_ACCESS_METHOD_NIC, 653 }; 654 655 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 656 { 657 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 658 return MLX5_VPORT_ACCESS_METHOD_MAD; 659 660 if (mlx5_ib_port_link_layer(ibdev, 1) == 661 IB_LINK_LAYER_ETHERNET) 662 return MLX5_VPORT_ACCESS_METHOD_NIC; 663 664 return MLX5_VPORT_ACCESS_METHOD_HCA; 665 } 666 667 static void get_atomic_caps(struct mlx5_ib_dev *dev, 668 u8 atomic_size_qp, 669 struct ib_device_attr *props) 670 { 671 u8 tmp; 672 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 673 u8 atomic_req_8B_endianness_mode = 674 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode); 675 676 /* Check if HW supports 8 bytes standard atomic operations and capable 677 * of host endianness respond 678 */ 679 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 680 if (((atomic_operations & tmp) == tmp) && 681 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 682 (atomic_req_8B_endianness_mode)) { 683 props->atomic_cap = IB_ATOMIC_HCA; 684 } else { 685 props->atomic_cap = IB_ATOMIC_NONE; 686 } 687 } 688 689 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev, 690 struct ib_device_attr *props) 691 { 692 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 693 694 get_atomic_caps(dev, atomic_size_qp, props); 695 } 696 697 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 698 __be64 *sys_image_guid) 699 { 700 struct mlx5_ib_dev *dev = to_mdev(ibdev); 701 struct mlx5_core_dev *mdev = dev->mdev; 702 u64 tmp; 703 int err; 704 705 switch (mlx5_get_vport_access_method(ibdev)) { 706 case MLX5_VPORT_ACCESS_METHOD_MAD: 707 return mlx5_query_mad_ifc_system_image_guid(ibdev, 708 sys_image_guid); 709 710 case MLX5_VPORT_ACCESS_METHOD_HCA: 711 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 712 break; 713 714 case MLX5_VPORT_ACCESS_METHOD_NIC: 715 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 716 break; 717 718 default: 719 return -EINVAL; 720 } 721 722 if (!err) 723 *sys_image_guid = cpu_to_be64(tmp); 724 725 return err; 726 727 } 728 729 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 730 u16 *max_pkeys) 731 { 732 struct mlx5_ib_dev *dev = to_mdev(ibdev); 733 struct mlx5_core_dev *mdev = dev->mdev; 734 735 switch (mlx5_get_vport_access_method(ibdev)) { 736 case MLX5_VPORT_ACCESS_METHOD_MAD: 737 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 738 739 case MLX5_VPORT_ACCESS_METHOD_HCA: 740 case MLX5_VPORT_ACCESS_METHOD_NIC: 741 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 742 pkey_table_size)); 743 return 0; 744 745 default: 746 return -EINVAL; 747 } 748 } 749 750 static int mlx5_query_vendor_id(struct ib_device *ibdev, 751 u32 *vendor_id) 752 { 753 struct mlx5_ib_dev *dev = to_mdev(ibdev); 754 755 switch (mlx5_get_vport_access_method(ibdev)) { 756 case MLX5_VPORT_ACCESS_METHOD_MAD: 757 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 758 759 case MLX5_VPORT_ACCESS_METHOD_HCA: 760 case MLX5_VPORT_ACCESS_METHOD_NIC: 761 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 762 763 default: 764 return -EINVAL; 765 } 766 } 767 768 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 769 __be64 *node_guid) 770 { 771 u64 tmp; 772 int err; 773 774 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 775 case MLX5_VPORT_ACCESS_METHOD_MAD: 776 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 777 778 case MLX5_VPORT_ACCESS_METHOD_HCA: 779 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 780 break; 781 782 case MLX5_VPORT_ACCESS_METHOD_NIC: 783 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 784 break; 785 786 default: 787 return -EINVAL; 788 } 789 790 if (!err) 791 *node_guid = cpu_to_be64(tmp); 792 793 return err; 794 } 795 796 struct mlx5_reg_node_desc { 797 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 798 }; 799 800 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 801 { 802 struct mlx5_reg_node_desc in; 803 804 if (mlx5_use_mad_ifc(dev)) 805 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 806 807 memset(&in, 0, sizeof(in)); 808 809 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 810 sizeof(struct mlx5_reg_node_desc), 811 MLX5_REG_NODE_DESC, 0, 0); 812 } 813 814 static int mlx5_ib_query_device(struct ib_device *ibdev, 815 struct ib_device_attr *props, 816 struct ib_udata *uhw) 817 { 818 size_t uhw_outlen = (uhw) ? uhw->outlen : 0; 819 struct mlx5_ib_dev *dev = to_mdev(ibdev); 820 struct mlx5_core_dev *mdev = dev->mdev; 821 int err = -ENOMEM; 822 int max_sq_desc; 823 int max_rq_sg; 824 int max_sq_sg; 825 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 826 bool raw_support = !mlx5_core_mp_enabled(mdev); 827 struct mlx5_ib_query_device_resp resp = {}; 828 size_t resp_len; 829 u64 max_tso; 830 831 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 832 if (uhw_outlen && uhw_outlen < resp_len) 833 return -EINVAL; 834 835 resp.response_length = resp_len; 836 837 if (uhw && uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) 838 return -EINVAL; 839 840 memset(props, 0, sizeof(*props)); 841 err = mlx5_query_system_image_guid(ibdev, 842 &props->sys_image_guid); 843 if (err) 844 return err; 845 846 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys); 847 if (err) 848 return err; 849 850 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 851 if (err) 852 return err; 853 854 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 855 (fw_rev_min(dev->mdev) << 16) | 856 fw_rev_sub(dev->mdev); 857 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 858 IB_DEVICE_PORT_ACTIVE_EVENT | 859 IB_DEVICE_SYS_IMAGE_GUID | 860 IB_DEVICE_RC_RNR_NAK_GEN; 861 862 if (MLX5_CAP_GEN(mdev, pkv)) 863 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 864 if (MLX5_CAP_GEN(mdev, qkv)) 865 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 866 if (MLX5_CAP_GEN(mdev, apm)) 867 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 868 if (MLX5_CAP_GEN(mdev, xrc)) 869 props->device_cap_flags |= IB_DEVICE_XRC; 870 if (MLX5_CAP_GEN(mdev, imaicl)) { 871 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 872 IB_DEVICE_MEM_WINDOW_TYPE_2B; 873 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 874 /* We support 'Gappy' memory registration too */ 875 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG; 876 } 877 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 878 if (MLX5_CAP_GEN(mdev, sho)) { 879 props->device_cap_flags |= IB_DEVICE_INTEGRITY_HANDOVER; 880 /* At this stage no support for signature handover */ 881 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 882 IB_PROT_T10DIF_TYPE_2 | 883 IB_PROT_T10DIF_TYPE_3; 884 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 885 IB_GUARD_T10DIF_CSUM; 886 } 887 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 888 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 889 890 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) { 891 if (MLX5_CAP_ETH(mdev, csum_cap)) { 892 /* Legacy bit to support old userspace libraries */ 893 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 894 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM; 895 } 896 897 if (MLX5_CAP_ETH(dev->mdev, vlan_cap)) 898 props->raw_packet_caps |= 899 IB_RAW_PACKET_CAP_CVLAN_STRIPPING; 900 901 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) { 902 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 903 if (max_tso) { 904 resp.tso_caps.max_tso = 1 << max_tso; 905 resp.tso_caps.supported_qpts |= 906 1 << IB_QPT_RAW_PACKET; 907 resp.response_length += sizeof(resp.tso_caps); 908 } 909 } 910 911 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) { 912 resp.rss_caps.rx_hash_function = 913 MLX5_RX_HASH_FUNC_TOEPLITZ; 914 resp.rss_caps.rx_hash_fields_mask = 915 MLX5_RX_HASH_SRC_IPV4 | 916 MLX5_RX_HASH_DST_IPV4 | 917 MLX5_RX_HASH_SRC_IPV6 | 918 MLX5_RX_HASH_DST_IPV6 | 919 MLX5_RX_HASH_SRC_PORT_TCP | 920 MLX5_RX_HASH_DST_PORT_TCP | 921 MLX5_RX_HASH_SRC_PORT_UDP | 922 MLX5_RX_HASH_DST_PORT_UDP | 923 MLX5_RX_HASH_INNER; 924 if (mlx5_accel_ipsec_device_caps(dev->mdev) & 925 MLX5_ACCEL_IPSEC_CAP_DEVICE) 926 resp.rss_caps.rx_hash_fields_mask |= 927 MLX5_RX_HASH_IPSEC_SPI; 928 resp.response_length += sizeof(resp.rss_caps); 929 } 930 } else { 931 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) 932 resp.response_length += sizeof(resp.tso_caps); 933 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) 934 resp.response_length += sizeof(resp.rss_caps); 935 } 936 937 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 938 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 939 props->device_cap_flags |= IB_DEVICE_UD_TSO; 940 } 941 942 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) && 943 MLX5_CAP_GEN(dev->mdev, general_notification_event) && 944 raw_support) 945 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP; 946 947 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 948 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap)) 949 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 950 951 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 952 MLX5_CAP_ETH(dev->mdev, scatter_fcs) && 953 raw_support) { 954 /* Legacy bit to support old userspace libraries */ 955 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 956 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; 957 } 958 959 if (MLX5_CAP_DEV_MEM(mdev, memic)) { 960 props->max_dm_size = 961 MLX5_CAP_DEV_MEM(mdev, max_memic_size); 962 } 963 964 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 965 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 966 967 if (MLX5_CAP_GEN(mdev, end_pad)) 968 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING; 969 970 props->vendor_part_id = mdev->pdev->device; 971 props->hw_ver = mdev->pdev->revision; 972 973 props->max_mr_size = ~0ull; 974 props->page_size_cap = ~(min_page_size - 1); 975 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 976 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 977 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 978 sizeof(struct mlx5_wqe_data_seg); 979 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512); 980 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) - 981 sizeof(struct mlx5_wqe_raddr_seg)) / 982 sizeof(struct mlx5_wqe_data_seg); 983 props->max_send_sge = max_sq_sg; 984 props->max_recv_sge = max_rq_sg; 985 props->max_sge_rd = MLX5_MAX_SGE_RD; 986 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 987 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 988 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 989 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 990 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 991 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 992 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 993 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 994 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 995 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 996 props->max_srq_sge = max_rq_sg - 1; 997 props->max_fast_reg_page_list_len = 998 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 999 props->max_pi_fast_reg_page_list_len = 1000 props->max_fast_reg_page_list_len / 2; 1001 props->max_sgl_rd = 1002 MLX5_CAP_GEN(mdev, max_sgl_for_optimized_performance); 1003 get_atomic_caps_qp(dev, props); 1004 props->masked_atomic_cap = IB_ATOMIC_NONE; 1005 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 1006 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 1007 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 1008 props->max_mcast_grp; 1009 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */ 1010 props->max_ah = INT_MAX; 1011 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 1012 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 1013 1014 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) { 1015 if (dev->odp_caps.general_caps & IB_ODP_SUPPORT) 1016 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING; 1017 props->odp_caps = dev->odp_caps; 1018 if (!uhw) { 1019 /* ODP for kernel QPs is not implemented for receive 1020 * WQEs and SRQ WQEs 1021 */ 1022 props->odp_caps.per_transport_caps.rc_odp_caps &= 1023 ~(IB_ODP_SUPPORT_READ | 1024 IB_ODP_SUPPORT_SRQ_RECV); 1025 props->odp_caps.per_transport_caps.uc_odp_caps &= 1026 ~(IB_ODP_SUPPORT_READ | 1027 IB_ODP_SUPPORT_SRQ_RECV); 1028 props->odp_caps.per_transport_caps.ud_odp_caps &= 1029 ~(IB_ODP_SUPPORT_READ | 1030 IB_ODP_SUPPORT_SRQ_RECV); 1031 props->odp_caps.per_transport_caps.xrc_odp_caps &= 1032 ~(IB_ODP_SUPPORT_READ | 1033 IB_ODP_SUPPORT_SRQ_RECV); 1034 } 1035 } 1036 1037 if (MLX5_CAP_GEN(mdev, cd)) 1038 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL; 1039 1040 if (mlx5_core_is_vf(mdev)) 1041 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION; 1042 1043 if (mlx5_ib_port_link_layer(ibdev, 1) == 1044 IB_LINK_LAYER_ETHERNET && raw_support) { 1045 props->rss_caps.max_rwq_indirection_tables = 1046 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 1047 props->rss_caps.max_rwq_indirection_table_size = 1048 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 1049 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 1050 props->max_wq_type_rq = 1051 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 1052 } 1053 1054 if (MLX5_CAP_GEN(mdev, tag_matching)) { 1055 props->tm_caps.max_num_tags = 1056 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1; 1057 props->tm_caps.max_ops = 1058 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 1059 props->tm_caps.max_sge = MLX5_TM_MAX_SGE; 1060 } 1061 1062 if (MLX5_CAP_GEN(mdev, tag_matching) && 1063 MLX5_CAP_GEN(mdev, rndv_offload_rc)) { 1064 props->tm_caps.flags = IB_TM_CAP_RNDV_RC; 1065 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE; 1066 } 1067 1068 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) { 1069 props->cq_caps.max_cq_moderation_count = 1070 MLX5_MAX_CQ_COUNT; 1071 props->cq_caps.max_cq_moderation_period = 1072 MLX5_MAX_CQ_PERIOD; 1073 } 1074 1075 if (offsetofend(typeof(resp), cqe_comp_caps) <= uhw_outlen) { 1076 resp.response_length += sizeof(resp.cqe_comp_caps); 1077 1078 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) { 1079 resp.cqe_comp_caps.max_num = 1080 MLX5_CAP_GEN(dev->mdev, 1081 cqe_compression_max_num); 1082 1083 resp.cqe_comp_caps.supported_format = 1084 MLX5_IB_CQE_RES_FORMAT_HASH | 1085 MLX5_IB_CQE_RES_FORMAT_CSUM; 1086 1087 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index)) 1088 resp.cqe_comp_caps.supported_format |= 1089 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX; 1090 } 1091 } 1092 1093 if (offsetofend(typeof(resp), packet_pacing_caps) <= uhw_outlen && 1094 raw_support) { 1095 if (MLX5_CAP_QOS(mdev, packet_pacing) && 1096 MLX5_CAP_GEN(mdev, qos)) { 1097 resp.packet_pacing_caps.qp_rate_limit_max = 1098 MLX5_CAP_QOS(mdev, packet_pacing_max_rate); 1099 resp.packet_pacing_caps.qp_rate_limit_min = 1100 MLX5_CAP_QOS(mdev, packet_pacing_min_rate); 1101 resp.packet_pacing_caps.supported_qpts |= 1102 1 << IB_QPT_RAW_PACKET; 1103 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) && 1104 MLX5_CAP_QOS(mdev, packet_pacing_typical_size)) 1105 resp.packet_pacing_caps.cap_flags |= 1106 MLX5_IB_PP_SUPPORT_BURST; 1107 } 1108 resp.response_length += sizeof(resp.packet_pacing_caps); 1109 } 1110 1111 if (offsetofend(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes) <= 1112 uhw_outlen) { 1113 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe)) 1114 resp.mlx5_ib_support_multi_pkt_send_wqes = 1115 MLX5_IB_ALLOW_MPW; 1116 1117 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe)) 1118 resp.mlx5_ib_support_multi_pkt_send_wqes |= 1119 MLX5_IB_SUPPORT_EMPW; 1120 1121 resp.response_length += 1122 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes); 1123 } 1124 1125 if (offsetofend(typeof(resp), flags) <= uhw_outlen) { 1126 resp.response_length += sizeof(resp.flags); 1127 1128 if (MLX5_CAP_GEN(mdev, cqe_compression_128)) 1129 resp.flags |= 1130 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP; 1131 1132 if (MLX5_CAP_GEN(mdev, cqe_128_always)) 1133 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD; 1134 if (MLX5_CAP_GEN(mdev, qp_packet_based)) 1135 resp.flags |= 1136 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE; 1137 1138 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT; 1139 } 1140 1141 if (offsetofend(typeof(resp), sw_parsing_caps) <= uhw_outlen) { 1142 resp.response_length += sizeof(resp.sw_parsing_caps); 1143 if (MLX5_CAP_ETH(mdev, swp)) { 1144 resp.sw_parsing_caps.sw_parsing_offloads |= 1145 MLX5_IB_SW_PARSING; 1146 1147 if (MLX5_CAP_ETH(mdev, swp_csum)) 1148 resp.sw_parsing_caps.sw_parsing_offloads |= 1149 MLX5_IB_SW_PARSING_CSUM; 1150 1151 if (MLX5_CAP_ETH(mdev, swp_lso)) 1152 resp.sw_parsing_caps.sw_parsing_offloads |= 1153 MLX5_IB_SW_PARSING_LSO; 1154 1155 if (resp.sw_parsing_caps.sw_parsing_offloads) 1156 resp.sw_parsing_caps.supported_qpts = 1157 BIT(IB_QPT_RAW_PACKET); 1158 } 1159 } 1160 1161 if (offsetofend(typeof(resp), striding_rq_caps) <= uhw_outlen && 1162 raw_support) { 1163 resp.response_length += sizeof(resp.striding_rq_caps); 1164 if (MLX5_CAP_GEN(mdev, striding_rq)) { 1165 resp.striding_rq_caps.min_single_stride_log_num_of_bytes = 1166 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES; 1167 resp.striding_rq_caps.max_single_stride_log_num_of_bytes = 1168 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES; 1169 if (MLX5_CAP_GEN(dev->mdev, ext_stride_num_range)) 1170 resp.striding_rq_caps 1171 .min_single_wqe_log_num_of_strides = 1172 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1173 else 1174 resp.striding_rq_caps 1175 .min_single_wqe_log_num_of_strides = 1176 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1177 resp.striding_rq_caps.max_single_wqe_log_num_of_strides = 1178 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES; 1179 resp.striding_rq_caps.supported_qpts = 1180 BIT(IB_QPT_RAW_PACKET); 1181 } 1182 } 1183 1184 if (offsetofend(typeof(resp), tunnel_offloads_caps) <= uhw_outlen) { 1185 resp.response_length += sizeof(resp.tunnel_offloads_caps); 1186 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan)) 1187 resp.tunnel_offloads_caps |= 1188 MLX5_IB_TUNNELED_OFFLOADS_VXLAN; 1189 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx)) 1190 resp.tunnel_offloads_caps |= 1191 MLX5_IB_TUNNELED_OFFLOADS_GENEVE; 1192 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) 1193 resp.tunnel_offloads_caps |= 1194 MLX5_IB_TUNNELED_OFFLOADS_GRE; 1195 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre)) 1196 resp.tunnel_offloads_caps |= 1197 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE; 1198 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_udp)) 1199 resp.tunnel_offloads_caps |= 1200 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP; 1201 } 1202 1203 if (uhw_outlen) { 1204 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 1205 1206 if (err) 1207 return err; 1208 } 1209 1210 return 0; 1211 } 1212 1213 enum mlx5_ib_width { 1214 MLX5_IB_WIDTH_1X = 1 << 0, 1215 MLX5_IB_WIDTH_2X = 1 << 1, 1216 MLX5_IB_WIDTH_4X = 1 << 2, 1217 MLX5_IB_WIDTH_8X = 1 << 3, 1218 MLX5_IB_WIDTH_12X = 1 << 4 1219 }; 1220 1221 static void translate_active_width(struct ib_device *ibdev, u8 active_width, 1222 u8 *ib_width) 1223 { 1224 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1225 1226 if (active_width & MLX5_IB_WIDTH_1X) 1227 *ib_width = IB_WIDTH_1X; 1228 else if (active_width & MLX5_IB_WIDTH_2X) 1229 *ib_width = IB_WIDTH_2X; 1230 else if (active_width & MLX5_IB_WIDTH_4X) 1231 *ib_width = IB_WIDTH_4X; 1232 else if (active_width & MLX5_IB_WIDTH_8X) 1233 *ib_width = IB_WIDTH_8X; 1234 else if (active_width & MLX5_IB_WIDTH_12X) 1235 *ib_width = IB_WIDTH_12X; 1236 else { 1237 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n", 1238 (int)active_width); 1239 *ib_width = IB_WIDTH_4X; 1240 } 1241 1242 return; 1243 } 1244 1245 static int mlx5_mtu_to_ib_mtu(int mtu) 1246 { 1247 switch (mtu) { 1248 case 256: return 1; 1249 case 512: return 2; 1250 case 1024: return 3; 1251 case 2048: return 4; 1252 case 4096: return 5; 1253 default: 1254 pr_warn("invalid mtu\n"); 1255 return -1; 1256 } 1257 } 1258 1259 enum ib_max_vl_num { 1260 __IB_MAX_VL_0 = 1, 1261 __IB_MAX_VL_0_1 = 2, 1262 __IB_MAX_VL_0_3 = 3, 1263 __IB_MAX_VL_0_7 = 4, 1264 __IB_MAX_VL_0_14 = 5, 1265 }; 1266 1267 enum mlx5_vl_hw_cap { 1268 MLX5_VL_HW_0 = 1, 1269 MLX5_VL_HW_0_1 = 2, 1270 MLX5_VL_HW_0_2 = 3, 1271 MLX5_VL_HW_0_3 = 4, 1272 MLX5_VL_HW_0_4 = 5, 1273 MLX5_VL_HW_0_5 = 6, 1274 MLX5_VL_HW_0_6 = 7, 1275 MLX5_VL_HW_0_7 = 8, 1276 MLX5_VL_HW_0_14 = 15 1277 }; 1278 1279 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 1280 u8 *max_vl_num) 1281 { 1282 switch (vl_hw_cap) { 1283 case MLX5_VL_HW_0: 1284 *max_vl_num = __IB_MAX_VL_0; 1285 break; 1286 case MLX5_VL_HW_0_1: 1287 *max_vl_num = __IB_MAX_VL_0_1; 1288 break; 1289 case MLX5_VL_HW_0_3: 1290 *max_vl_num = __IB_MAX_VL_0_3; 1291 break; 1292 case MLX5_VL_HW_0_7: 1293 *max_vl_num = __IB_MAX_VL_0_7; 1294 break; 1295 case MLX5_VL_HW_0_14: 1296 *max_vl_num = __IB_MAX_VL_0_14; 1297 break; 1298 1299 default: 1300 return -EINVAL; 1301 } 1302 1303 return 0; 1304 } 1305 1306 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port, 1307 struct ib_port_attr *props) 1308 { 1309 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1310 struct mlx5_core_dev *mdev = dev->mdev; 1311 struct mlx5_hca_vport_context *rep; 1312 u16 max_mtu; 1313 u16 oper_mtu; 1314 int err; 1315 u8 ib_link_width_oper; 1316 u8 vl_hw_cap; 1317 1318 rep = kzalloc(sizeof(*rep), GFP_KERNEL); 1319 if (!rep) { 1320 err = -ENOMEM; 1321 goto out; 1322 } 1323 1324 /* props being zeroed by the caller, avoid zeroing it here */ 1325 1326 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); 1327 if (err) 1328 goto out; 1329 1330 props->lid = rep->lid; 1331 props->lmc = rep->lmc; 1332 props->sm_lid = rep->sm_lid; 1333 props->sm_sl = rep->sm_sl; 1334 props->state = rep->vport_state; 1335 props->phys_state = rep->port_physical_state; 1336 props->port_cap_flags = rep->cap_mask1; 1337 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 1338 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 1339 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 1340 props->bad_pkey_cntr = rep->pkey_violation_counter; 1341 props->qkey_viol_cntr = rep->qkey_violation_counter; 1342 props->subnet_timeout = rep->subnet_timeout; 1343 props->init_type_reply = rep->init_type_reply; 1344 1345 if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP) 1346 props->port_cap_flags2 = rep->cap_mask2; 1347 1348 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port); 1349 if (err) 1350 goto out; 1351 1352 translate_active_width(ibdev, ib_link_width_oper, &props->active_width); 1353 1354 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port); 1355 if (err) 1356 goto out; 1357 1358 mlx5_query_port_max_mtu(mdev, &max_mtu, port); 1359 1360 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); 1361 1362 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); 1363 1364 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); 1365 1366 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); 1367 if (err) 1368 goto out; 1369 1370 err = translate_max_vl_num(ibdev, vl_hw_cap, 1371 &props->max_vl_num); 1372 out: 1373 kfree(rep); 1374 return err; 1375 } 1376 1377 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 1378 struct ib_port_attr *props) 1379 { 1380 unsigned int count; 1381 int ret; 1382 1383 switch (mlx5_get_vport_access_method(ibdev)) { 1384 case MLX5_VPORT_ACCESS_METHOD_MAD: 1385 ret = mlx5_query_mad_ifc_port(ibdev, port, props); 1386 break; 1387 1388 case MLX5_VPORT_ACCESS_METHOD_HCA: 1389 ret = mlx5_query_hca_port(ibdev, port, props); 1390 break; 1391 1392 case MLX5_VPORT_ACCESS_METHOD_NIC: 1393 ret = mlx5_query_port_roce(ibdev, port, props); 1394 break; 1395 1396 default: 1397 ret = -EINVAL; 1398 } 1399 1400 if (!ret && props) { 1401 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1402 struct mlx5_core_dev *mdev; 1403 bool put_mdev = true; 1404 1405 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL); 1406 if (!mdev) { 1407 /* If the port isn't affiliated yet query the master. 1408 * The master and slave will have the same values. 1409 */ 1410 mdev = dev->mdev; 1411 port = 1; 1412 put_mdev = false; 1413 } 1414 count = mlx5_core_reserved_gids_count(mdev); 1415 if (put_mdev) 1416 mlx5_ib_put_native_port_mdev(dev, port); 1417 props->gid_tbl_len -= count; 1418 } 1419 return ret; 1420 } 1421 1422 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port, 1423 struct ib_port_attr *props) 1424 { 1425 int ret; 1426 1427 /* Only link layer == ethernet is valid for representors 1428 * and we always use port 1 1429 */ 1430 ret = mlx5_query_port_roce(ibdev, port, props); 1431 if (ret || !props) 1432 return ret; 1433 1434 /* We don't support GIDS */ 1435 props->gid_tbl_len = 0; 1436 1437 return ret; 1438 } 1439 1440 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 1441 union ib_gid *gid) 1442 { 1443 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1444 struct mlx5_core_dev *mdev = dev->mdev; 1445 1446 switch (mlx5_get_vport_access_method(ibdev)) { 1447 case MLX5_VPORT_ACCESS_METHOD_MAD: 1448 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 1449 1450 case MLX5_VPORT_ACCESS_METHOD_HCA: 1451 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); 1452 1453 default: 1454 return -EINVAL; 1455 } 1456 1457 } 1458 1459 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port, 1460 u16 index, u16 *pkey) 1461 { 1462 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1463 struct mlx5_core_dev *mdev; 1464 bool put_mdev = true; 1465 u8 mdev_port_num; 1466 int err; 1467 1468 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num); 1469 if (!mdev) { 1470 /* The port isn't affiliated yet, get the PKey from the master 1471 * port. For RoCE the PKey tables will be the same. 1472 */ 1473 put_mdev = false; 1474 mdev = dev->mdev; 1475 mdev_port_num = 1; 1476 } 1477 1478 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0, 1479 index, pkey); 1480 if (put_mdev) 1481 mlx5_ib_put_native_port_mdev(dev, port); 1482 1483 return err; 1484 } 1485 1486 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 1487 u16 *pkey) 1488 { 1489 switch (mlx5_get_vport_access_method(ibdev)) { 1490 case MLX5_VPORT_ACCESS_METHOD_MAD: 1491 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 1492 1493 case MLX5_VPORT_ACCESS_METHOD_HCA: 1494 case MLX5_VPORT_ACCESS_METHOD_NIC: 1495 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey); 1496 default: 1497 return -EINVAL; 1498 } 1499 } 1500 1501 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 1502 struct ib_device_modify *props) 1503 { 1504 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1505 struct mlx5_reg_node_desc in; 1506 struct mlx5_reg_node_desc out; 1507 int err; 1508 1509 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 1510 return -EOPNOTSUPP; 1511 1512 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 1513 return 0; 1514 1515 /* 1516 * If possible, pass node desc to FW, so it can generate 1517 * a 144 trap. If cmd fails, just ignore. 1518 */ 1519 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1520 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 1521 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 1522 if (err) 1523 return err; 1524 1525 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1526 1527 return err; 1528 } 1529 1530 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask, 1531 u32 value) 1532 { 1533 struct mlx5_hca_vport_context ctx = {}; 1534 struct mlx5_core_dev *mdev; 1535 u8 mdev_port_num; 1536 int err; 1537 1538 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 1539 if (!mdev) 1540 return -ENODEV; 1541 1542 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx); 1543 if (err) 1544 goto out; 1545 1546 if (~ctx.cap_mask1_perm & mask) { 1547 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n", 1548 mask, ctx.cap_mask1_perm); 1549 err = -EINVAL; 1550 goto out; 1551 } 1552 1553 ctx.cap_mask1 = value; 1554 ctx.cap_mask1_perm = mask; 1555 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num, 1556 0, &ctx); 1557 1558 out: 1559 mlx5_ib_put_native_port_mdev(dev, port_num); 1560 1561 return err; 1562 } 1563 1564 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, 1565 struct ib_port_modify *props) 1566 { 1567 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1568 struct ib_port_attr attr; 1569 u32 tmp; 1570 int err; 1571 u32 change_mask; 1572 u32 value; 1573 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) == 1574 IB_LINK_LAYER_INFINIBAND); 1575 1576 /* CM layer calls ib_modify_port() regardless of the link layer. For 1577 * Ethernet ports, qkey violation and Port capabilities are meaningless. 1578 */ 1579 if (!is_ib) 1580 return 0; 1581 1582 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) { 1583 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask; 1584 value = ~props->clr_port_cap_mask | props->set_port_cap_mask; 1585 return set_port_caps_atomic(dev, port, change_mask, value); 1586 } 1587 1588 mutex_lock(&dev->cap_mask_mutex); 1589 1590 err = ib_query_port(ibdev, port, &attr); 1591 if (err) 1592 goto out; 1593 1594 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 1595 ~props->clr_port_cap_mask; 1596 1597 err = mlx5_set_port_caps(dev->mdev, port, tmp); 1598 1599 out: 1600 mutex_unlock(&dev->cap_mask_mutex); 1601 return err; 1602 } 1603 1604 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps) 1605 { 1606 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n", 1607 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n"); 1608 } 1609 1610 static u16 calc_dynamic_bfregs(int uars_per_sys_page) 1611 { 1612 /* Large page with non 4k uar support might limit the dynamic size */ 1613 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096) 1614 return MLX5_MIN_DYN_BFREGS; 1615 1616 return MLX5_MAX_DYN_BFREGS; 1617 } 1618 1619 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k, 1620 struct mlx5_ib_alloc_ucontext_req_v2 *req, 1621 struct mlx5_bfreg_info *bfregi) 1622 { 1623 int uars_per_sys_page; 1624 int bfregs_per_sys_page; 1625 int ref_bfregs = req->total_num_bfregs; 1626 1627 if (req->total_num_bfregs == 0) 1628 return -EINVAL; 1629 1630 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE); 1631 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE); 1632 1633 if (req->total_num_bfregs > MLX5_MAX_BFREGS) 1634 return -ENOMEM; 1635 1636 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k); 1637 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR; 1638 /* This holds the required static allocation asked by the user */ 1639 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page); 1640 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1) 1641 return -EINVAL; 1642 1643 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page; 1644 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page); 1645 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs; 1646 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page; 1647 1648 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n", 1649 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no", 1650 lib_uar_4k ? "yes" : "no", ref_bfregs, 1651 req->total_num_bfregs, bfregi->total_num_bfregs, 1652 bfregi->num_sys_pages); 1653 1654 return 0; 1655 } 1656 1657 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1658 { 1659 struct mlx5_bfreg_info *bfregi; 1660 int err; 1661 int i; 1662 1663 bfregi = &context->bfregi; 1664 for (i = 0; i < bfregi->num_static_sys_pages; i++) { 1665 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]); 1666 if (err) 1667 goto error; 1668 1669 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]); 1670 } 1671 1672 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++) 1673 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX; 1674 1675 return 0; 1676 1677 error: 1678 for (--i; i >= 0; i--) 1679 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i])) 1680 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1681 1682 return err; 1683 } 1684 1685 static void deallocate_uars(struct mlx5_ib_dev *dev, 1686 struct mlx5_ib_ucontext *context) 1687 { 1688 struct mlx5_bfreg_info *bfregi; 1689 int i; 1690 1691 bfregi = &context->bfregi; 1692 for (i = 0; i < bfregi->num_sys_pages; i++) 1693 if (i < bfregi->num_static_sys_pages || 1694 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) 1695 mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]); 1696 } 1697 1698 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 1699 { 1700 int err = 0; 1701 1702 mutex_lock(&dev->lb.mutex); 1703 if (td) 1704 dev->lb.user_td++; 1705 if (qp) 1706 dev->lb.qps++; 1707 1708 if (dev->lb.user_td == 2 || 1709 dev->lb.qps == 1) { 1710 if (!dev->lb.enabled) { 1711 err = mlx5_nic_vport_update_local_lb(dev->mdev, true); 1712 dev->lb.enabled = true; 1713 } 1714 } 1715 1716 mutex_unlock(&dev->lb.mutex); 1717 1718 return err; 1719 } 1720 1721 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 1722 { 1723 mutex_lock(&dev->lb.mutex); 1724 if (td) 1725 dev->lb.user_td--; 1726 if (qp) 1727 dev->lb.qps--; 1728 1729 if (dev->lb.user_td == 1 && 1730 dev->lb.qps == 0) { 1731 if (dev->lb.enabled) { 1732 mlx5_nic_vport_update_local_lb(dev->mdev, false); 1733 dev->lb.enabled = false; 1734 } 1735 } 1736 1737 mutex_unlock(&dev->lb.mutex); 1738 } 1739 1740 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn, 1741 u16 uid) 1742 { 1743 int err; 1744 1745 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1746 return 0; 1747 1748 err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid); 1749 if (err) 1750 return err; 1751 1752 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1753 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1754 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1755 return err; 1756 1757 return mlx5_ib_enable_lb(dev, true, false); 1758 } 1759 1760 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn, 1761 u16 uid) 1762 { 1763 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1764 return; 1765 1766 mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid); 1767 1768 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1769 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1770 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1771 return; 1772 1773 mlx5_ib_disable_lb(dev, true, false); 1774 } 1775 1776 static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx, 1777 struct ib_udata *udata) 1778 { 1779 struct ib_device *ibdev = uctx->device; 1780 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1781 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 1782 struct mlx5_ib_alloc_ucontext_resp resp = {}; 1783 struct mlx5_core_dev *mdev = dev->mdev; 1784 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 1785 struct mlx5_bfreg_info *bfregi; 1786 int ver; 1787 int err; 1788 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 1789 max_cqe_version); 1790 u32 dump_fill_mkey; 1791 bool lib_uar_4k; 1792 bool lib_uar_dyn; 1793 1794 if (!dev->ib_active) 1795 return -EAGAIN; 1796 1797 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 1798 ver = 0; 1799 else if (udata->inlen >= min_req_v2) 1800 ver = 2; 1801 else 1802 return -EINVAL; 1803 1804 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req))); 1805 if (err) 1806 return err; 1807 1808 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX) 1809 return -EOPNOTSUPP; 1810 1811 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 1812 return -EOPNOTSUPP; 1813 1814 req.total_num_bfregs = ALIGN(req.total_num_bfregs, 1815 MLX5_NON_FP_BFREGS_PER_UAR); 1816 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1) 1817 return -EINVAL; 1818 1819 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 1820 if (dev->wc_support) 1821 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size); 1822 resp.cache_line_size = cache_line_size(); 1823 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 1824 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 1825 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1826 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1827 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 1828 resp.cqe_version = min_t(__u8, 1829 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 1830 req.max_cqe_version); 1831 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1832 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT; 1833 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1834 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1; 1835 resp.response_length = min(offsetof(typeof(resp), response_length) + 1836 sizeof(resp.response_length), udata->outlen); 1837 1838 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE) { 1839 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_EGRESS)) 1840 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM; 1841 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA) 1842 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA; 1843 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi)) 1844 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING; 1845 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN) 1846 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN; 1847 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */ 1848 } 1849 1850 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR; 1851 lib_uar_dyn = req.lib_caps & MLX5_LIB_CAP_DYN_UAR; 1852 bfregi = &context->bfregi; 1853 1854 if (lib_uar_dyn) { 1855 bfregi->lib_uar_dyn = lib_uar_dyn; 1856 goto uar_done; 1857 } 1858 1859 /* updates req->total_num_bfregs */ 1860 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi); 1861 if (err) 1862 goto out_ctx; 1863 1864 mutex_init(&bfregi->lock); 1865 bfregi->lib_uar_4k = lib_uar_4k; 1866 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count), 1867 GFP_KERNEL); 1868 if (!bfregi->count) { 1869 err = -ENOMEM; 1870 goto out_ctx; 1871 } 1872 1873 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages, 1874 sizeof(*bfregi->sys_pages), 1875 GFP_KERNEL); 1876 if (!bfregi->sys_pages) { 1877 err = -ENOMEM; 1878 goto out_count; 1879 } 1880 1881 err = allocate_uars(dev, context); 1882 if (err) 1883 goto out_sys_pages; 1884 1885 uar_done: 1886 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) { 1887 err = mlx5_ib_devx_create(dev, true); 1888 if (err < 0) 1889 goto out_uars; 1890 context->devx_uid = err; 1891 } 1892 1893 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn, 1894 context->devx_uid); 1895 if (err) 1896 goto out_devx; 1897 1898 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) { 1899 err = mlx5_cmd_dump_fill_mkey(dev->mdev, &dump_fill_mkey); 1900 if (err) 1901 goto out_mdev; 1902 } 1903 1904 INIT_LIST_HEAD(&context->db_page_list); 1905 mutex_init(&context->db_page_mutex); 1906 1907 resp.tot_bfregs = lib_uar_dyn ? 0 : req.total_num_bfregs; 1908 resp.num_ports = dev->num_ports; 1909 1910 if (offsetofend(typeof(resp), cqe_version) <= udata->outlen) 1911 resp.response_length += sizeof(resp.cqe_version); 1912 1913 if (offsetofend(typeof(resp), cmds_supp_uhw) <= udata->outlen) { 1914 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 1915 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 1916 resp.response_length += sizeof(resp.cmds_supp_uhw); 1917 } 1918 1919 if (offsetofend(typeof(resp), eth_min_inline) <= udata->outlen) { 1920 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) { 1921 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline); 1922 resp.eth_min_inline++; 1923 } 1924 resp.response_length += sizeof(resp.eth_min_inline); 1925 } 1926 1927 if (offsetofend(typeof(resp), clock_info_versions) <= udata->outlen) { 1928 if (mdev->clock_info) 1929 resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1); 1930 resp.response_length += sizeof(resp.clock_info_versions); 1931 } 1932 1933 /* 1934 * We don't want to expose information from the PCI bar that is located 1935 * after 4096 bytes, so if the arch only supports larger pages, let's 1936 * pretend we don't support reading the HCA's core clock. This is also 1937 * forced by mmap function. 1938 */ 1939 if (offsetofend(typeof(resp), hca_core_clock_offset) <= udata->outlen) { 1940 if (PAGE_SIZE <= 4096) { 1941 resp.comp_mask |= 1942 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 1943 resp.hca_core_clock_offset = 1944 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE; 1945 } 1946 resp.response_length += sizeof(resp.hca_core_clock_offset); 1947 } 1948 1949 if (offsetofend(typeof(resp), log_uar_size) <= udata->outlen) 1950 resp.response_length += sizeof(resp.log_uar_size); 1951 1952 if (offsetofend(typeof(resp), num_uars_per_page) <= udata->outlen) 1953 resp.response_length += sizeof(resp.num_uars_per_page); 1954 1955 if (offsetofend(typeof(resp), num_dyn_bfregs) <= udata->outlen) { 1956 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs; 1957 resp.response_length += sizeof(resp.num_dyn_bfregs); 1958 } 1959 1960 if (offsetofend(typeof(resp), dump_fill_mkey) <= udata->outlen) { 1961 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) { 1962 resp.dump_fill_mkey = dump_fill_mkey; 1963 resp.comp_mask |= 1964 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY; 1965 } 1966 resp.response_length += sizeof(resp.dump_fill_mkey); 1967 } 1968 1969 err = ib_copy_to_udata(udata, &resp, resp.response_length); 1970 if (err) 1971 goto out_mdev; 1972 1973 bfregi->ver = ver; 1974 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs; 1975 context->cqe_version = resp.cqe_version; 1976 context->lib_caps = req.lib_caps; 1977 print_lib_caps(dev, context->lib_caps); 1978 1979 if (dev->lag_active) { 1980 u8 port = mlx5_core_native_port_num(dev->mdev) - 1; 1981 1982 atomic_set(&context->tx_port_affinity, 1983 atomic_add_return( 1984 1, &dev->port[port].roce.tx_port_affinity)); 1985 } 1986 1987 return 0; 1988 1989 out_mdev: 1990 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 1991 out_devx: 1992 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) 1993 mlx5_ib_devx_destroy(dev, context->devx_uid); 1994 1995 out_uars: 1996 deallocate_uars(dev, context); 1997 1998 out_sys_pages: 1999 kfree(bfregi->sys_pages); 2000 2001 out_count: 2002 kfree(bfregi->count); 2003 2004 out_ctx: 2005 return err; 2006 } 2007 2008 static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 2009 { 2010 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2011 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2012 struct mlx5_bfreg_info *bfregi; 2013 2014 bfregi = &context->bfregi; 2015 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 2016 2017 if (context->devx_uid) 2018 mlx5_ib_devx_destroy(dev, context->devx_uid); 2019 2020 deallocate_uars(dev, context); 2021 kfree(bfregi->sys_pages); 2022 kfree(bfregi->count); 2023 } 2024 2025 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, 2026 int uar_idx) 2027 { 2028 int fw_uars_per_page; 2029 2030 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1; 2031 2032 return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page; 2033 } 2034 2035 static u64 uar_index2paddress(struct mlx5_ib_dev *dev, 2036 int uar_idx) 2037 { 2038 unsigned int fw_uars_per_page; 2039 2040 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 2041 MLX5_UARS_IN_PAGE : 1; 2042 2043 return (dev->mdev->bar_addr + (uar_idx / fw_uars_per_page) * PAGE_SIZE); 2044 } 2045 2046 static int get_command(unsigned long offset) 2047 { 2048 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 2049 } 2050 2051 static int get_arg(unsigned long offset) 2052 { 2053 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 2054 } 2055 2056 static int get_index(unsigned long offset) 2057 { 2058 return get_arg(offset); 2059 } 2060 2061 /* Index resides in an extra byte to enable larger values than 255 */ 2062 static int get_extended_index(unsigned long offset) 2063 { 2064 return get_arg(offset) | ((offset >> 16) & 0xff) << 8; 2065 } 2066 2067 2068 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 2069 { 2070 } 2071 2072 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 2073 { 2074 switch (cmd) { 2075 case MLX5_IB_MMAP_WC_PAGE: 2076 return "WC"; 2077 case MLX5_IB_MMAP_REGULAR_PAGE: 2078 return "best effort WC"; 2079 case MLX5_IB_MMAP_NC_PAGE: 2080 return "NC"; 2081 case MLX5_IB_MMAP_DEVICE_MEM: 2082 return "Device Memory"; 2083 default: 2084 return NULL; 2085 } 2086 } 2087 2088 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev, 2089 struct vm_area_struct *vma, 2090 struct mlx5_ib_ucontext *context) 2091 { 2092 if ((vma->vm_end - vma->vm_start != PAGE_SIZE) || 2093 !(vma->vm_flags & VM_SHARED)) 2094 return -EINVAL; 2095 2096 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1) 2097 return -EOPNOTSUPP; 2098 2099 if (vma->vm_flags & (VM_WRITE | VM_EXEC)) 2100 return -EPERM; 2101 vma->vm_flags &= ~VM_MAYWRITE; 2102 2103 if (!dev->mdev->clock_info) 2104 return -EOPNOTSUPP; 2105 2106 return vm_insert_page(vma, vma->vm_start, 2107 virt_to_page(dev->mdev->clock_info)); 2108 } 2109 2110 static void mlx5_ib_mmap_free(struct rdma_user_mmap_entry *entry) 2111 { 2112 struct mlx5_user_mmap_entry *mentry = to_mmmap(entry); 2113 struct mlx5_ib_dev *dev = to_mdev(entry->ucontext->device); 2114 struct mlx5_var_table *var_table = &dev->var_table; 2115 struct mlx5_ib_dm *mdm; 2116 2117 switch (mentry->mmap_flag) { 2118 case MLX5_IB_MMAP_TYPE_MEMIC: 2119 mdm = container_of(mentry, struct mlx5_ib_dm, mentry); 2120 mlx5_cmd_dealloc_memic(&dev->dm, mdm->dev_addr, 2121 mdm->size); 2122 kfree(mdm); 2123 break; 2124 case MLX5_IB_MMAP_TYPE_VAR: 2125 mutex_lock(&var_table->bitmap_lock); 2126 clear_bit(mentry->page_idx, var_table->bitmap); 2127 mutex_unlock(&var_table->bitmap_lock); 2128 kfree(mentry); 2129 break; 2130 case MLX5_IB_MMAP_TYPE_UAR_WC: 2131 case MLX5_IB_MMAP_TYPE_UAR_NC: 2132 mlx5_cmd_free_uar(dev->mdev, mentry->page_idx); 2133 kfree(mentry); 2134 break; 2135 default: 2136 WARN_ON(true); 2137 } 2138 } 2139 2140 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 2141 struct vm_area_struct *vma, 2142 struct mlx5_ib_ucontext *context) 2143 { 2144 struct mlx5_bfreg_info *bfregi = &context->bfregi; 2145 int err; 2146 unsigned long idx; 2147 phys_addr_t pfn; 2148 pgprot_t prot; 2149 u32 bfreg_dyn_idx = 0; 2150 u32 uar_index; 2151 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC); 2152 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages : 2153 bfregi->num_static_sys_pages; 2154 2155 if (bfregi->lib_uar_dyn) 2156 return -EINVAL; 2157 2158 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2159 return -EINVAL; 2160 2161 if (dyn_uar) 2162 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages; 2163 else 2164 idx = get_index(vma->vm_pgoff); 2165 2166 if (idx >= max_valid_idx) { 2167 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n", 2168 idx, max_valid_idx); 2169 return -EINVAL; 2170 } 2171 2172 switch (cmd) { 2173 case MLX5_IB_MMAP_WC_PAGE: 2174 case MLX5_IB_MMAP_ALLOC_WC: 2175 case MLX5_IB_MMAP_REGULAR_PAGE: 2176 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 2177 prot = pgprot_writecombine(vma->vm_page_prot); 2178 break; 2179 case MLX5_IB_MMAP_NC_PAGE: 2180 prot = pgprot_noncached(vma->vm_page_prot); 2181 break; 2182 default: 2183 return -EINVAL; 2184 } 2185 2186 if (dyn_uar) { 2187 int uars_per_page; 2188 2189 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k); 2190 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR); 2191 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) { 2192 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n", 2193 bfreg_dyn_idx, bfregi->total_num_bfregs); 2194 return -EINVAL; 2195 } 2196 2197 mutex_lock(&bfregi->lock); 2198 /* Fail if uar already allocated, first bfreg index of each 2199 * page holds its count. 2200 */ 2201 if (bfregi->count[bfreg_dyn_idx]) { 2202 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx); 2203 mutex_unlock(&bfregi->lock); 2204 return -EINVAL; 2205 } 2206 2207 bfregi->count[bfreg_dyn_idx]++; 2208 mutex_unlock(&bfregi->lock); 2209 2210 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index); 2211 if (err) { 2212 mlx5_ib_warn(dev, "UAR alloc failed\n"); 2213 goto free_bfreg; 2214 } 2215 } else { 2216 uar_index = bfregi->sys_pages[idx]; 2217 } 2218 2219 pfn = uar_index2pfn(dev, uar_index); 2220 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 2221 2222 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE, 2223 prot, NULL); 2224 if (err) { 2225 mlx5_ib_err(dev, 2226 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n", 2227 err, mmap_cmd2str(cmd)); 2228 goto err; 2229 } 2230 2231 if (dyn_uar) 2232 bfregi->sys_pages[idx] = uar_index; 2233 return 0; 2234 2235 err: 2236 if (!dyn_uar) 2237 return err; 2238 2239 mlx5_cmd_free_uar(dev->mdev, idx); 2240 2241 free_bfreg: 2242 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx); 2243 2244 return err; 2245 } 2246 2247 static int add_dm_mmap_entry(struct ib_ucontext *context, 2248 struct mlx5_ib_dm *mdm, 2249 u64 address) 2250 { 2251 mdm->mentry.mmap_flag = MLX5_IB_MMAP_TYPE_MEMIC; 2252 mdm->mentry.address = address; 2253 return rdma_user_mmap_entry_insert_range( 2254 context, &mdm->mentry.rdma_entry, 2255 mdm->size, 2256 MLX5_IB_MMAP_DEVICE_MEM << 16, 2257 (MLX5_IB_MMAP_DEVICE_MEM << 16) + (1UL << 16) - 1); 2258 } 2259 2260 static unsigned long mlx5_vma_to_pgoff(struct vm_area_struct *vma) 2261 { 2262 unsigned long idx; 2263 u8 command; 2264 2265 command = get_command(vma->vm_pgoff); 2266 idx = get_extended_index(vma->vm_pgoff); 2267 2268 return (command << 16 | idx); 2269 } 2270 2271 static int mlx5_ib_mmap_offset(struct mlx5_ib_dev *dev, 2272 struct vm_area_struct *vma, 2273 struct ib_ucontext *ucontext) 2274 { 2275 struct mlx5_user_mmap_entry *mentry; 2276 struct rdma_user_mmap_entry *entry; 2277 unsigned long pgoff; 2278 pgprot_t prot; 2279 phys_addr_t pfn; 2280 int ret; 2281 2282 pgoff = mlx5_vma_to_pgoff(vma); 2283 entry = rdma_user_mmap_entry_get_pgoff(ucontext, pgoff); 2284 if (!entry) 2285 return -EINVAL; 2286 2287 mentry = to_mmmap(entry); 2288 pfn = (mentry->address >> PAGE_SHIFT); 2289 if (mentry->mmap_flag == MLX5_IB_MMAP_TYPE_VAR || 2290 mentry->mmap_flag == MLX5_IB_MMAP_TYPE_UAR_NC) 2291 prot = pgprot_noncached(vma->vm_page_prot); 2292 else 2293 prot = pgprot_writecombine(vma->vm_page_prot); 2294 ret = rdma_user_mmap_io(ucontext, vma, pfn, 2295 entry->npages * PAGE_SIZE, 2296 prot, 2297 entry); 2298 rdma_user_mmap_entry_put(&mentry->rdma_entry); 2299 return ret; 2300 } 2301 2302 static u64 mlx5_entry_to_mmap_offset(struct mlx5_user_mmap_entry *entry) 2303 { 2304 u64 cmd = (entry->rdma_entry.start_pgoff >> 16) & 0xFFFF; 2305 u64 index = entry->rdma_entry.start_pgoff & 0xFFFF; 2306 2307 return (((index >> 8) << 16) | (cmd << MLX5_IB_MMAP_CMD_SHIFT) | 2308 (index & 0xFF)) << PAGE_SHIFT; 2309 } 2310 2311 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 2312 { 2313 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2314 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2315 unsigned long command; 2316 phys_addr_t pfn; 2317 2318 command = get_command(vma->vm_pgoff); 2319 switch (command) { 2320 case MLX5_IB_MMAP_WC_PAGE: 2321 case MLX5_IB_MMAP_ALLOC_WC: 2322 if (!dev->wc_support) 2323 return -EPERM; 2324 fallthrough; 2325 case MLX5_IB_MMAP_NC_PAGE: 2326 case MLX5_IB_MMAP_REGULAR_PAGE: 2327 return uar_mmap(dev, command, vma, context); 2328 2329 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 2330 return -ENOSYS; 2331 2332 case MLX5_IB_MMAP_CORE_CLOCK: 2333 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2334 return -EINVAL; 2335 2336 if (vma->vm_flags & VM_WRITE) 2337 return -EPERM; 2338 vma->vm_flags &= ~VM_MAYWRITE; 2339 2340 /* Don't expose to user-space information it shouldn't have */ 2341 if (PAGE_SIZE > 4096) 2342 return -EOPNOTSUPP; 2343 2344 pfn = (dev->mdev->iseg_base + 2345 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 2346 PAGE_SHIFT; 2347 return rdma_user_mmap_io(&context->ibucontext, vma, pfn, 2348 PAGE_SIZE, 2349 pgprot_noncached(vma->vm_page_prot), 2350 NULL); 2351 case MLX5_IB_MMAP_CLOCK_INFO: 2352 return mlx5_ib_mmap_clock_info_page(dev, vma, context); 2353 2354 default: 2355 return mlx5_ib_mmap_offset(dev, vma, ibcontext); 2356 } 2357 2358 return 0; 2359 } 2360 2361 static inline int check_dm_type_support(struct mlx5_ib_dev *dev, 2362 u32 type) 2363 { 2364 switch (type) { 2365 case MLX5_IB_UAPI_DM_TYPE_MEMIC: 2366 if (!MLX5_CAP_DEV_MEM(dev->mdev, memic)) 2367 return -EOPNOTSUPP; 2368 break; 2369 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM: 2370 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM: 2371 if (!capable(CAP_SYS_RAWIO) || 2372 !capable(CAP_NET_RAW)) 2373 return -EPERM; 2374 2375 if (!(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) || 2376 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, sw_owner))) 2377 return -EOPNOTSUPP; 2378 break; 2379 } 2380 2381 return 0; 2382 } 2383 2384 static int handle_alloc_dm_memic(struct ib_ucontext *ctx, 2385 struct mlx5_ib_dm *dm, 2386 struct ib_dm_alloc_attr *attr, 2387 struct uverbs_attr_bundle *attrs) 2388 { 2389 struct mlx5_dm *dm_db = &to_mdev(ctx->device)->dm; 2390 u64 start_offset; 2391 u16 page_idx; 2392 int err; 2393 u64 address; 2394 2395 dm->size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE); 2396 2397 err = mlx5_cmd_alloc_memic(dm_db, &dm->dev_addr, 2398 dm->size, attr->alignment); 2399 if (err) 2400 return err; 2401 2402 address = dm->dev_addr & PAGE_MASK; 2403 err = add_dm_mmap_entry(ctx, dm, address); 2404 if (err) 2405 goto err_dealloc; 2406 2407 page_idx = dm->mentry.rdma_entry.start_pgoff & 0xFFFF; 2408 err = uverbs_copy_to(attrs, 2409 MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX, 2410 &page_idx, 2411 sizeof(page_idx)); 2412 if (err) 2413 goto err_copy; 2414 2415 start_offset = dm->dev_addr & ~PAGE_MASK; 2416 err = uverbs_copy_to(attrs, 2417 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET, 2418 &start_offset, sizeof(start_offset)); 2419 if (err) 2420 goto err_copy; 2421 2422 return 0; 2423 2424 err_copy: 2425 rdma_user_mmap_entry_remove(&dm->mentry.rdma_entry); 2426 err_dealloc: 2427 mlx5_cmd_dealloc_memic(dm_db, dm->dev_addr, dm->size); 2428 2429 return err; 2430 } 2431 2432 static int handle_alloc_dm_sw_icm(struct ib_ucontext *ctx, 2433 struct mlx5_ib_dm *dm, 2434 struct ib_dm_alloc_attr *attr, 2435 struct uverbs_attr_bundle *attrs, 2436 int type) 2437 { 2438 struct mlx5_core_dev *dev = to_mdev(ctx->device)->mdev; 2439 u64 act_size; 2440 int err; 2441 2442 /* Allocation size must a multiple of the basic block size 2443 * and a power of 2. 2444 */ 2445 act_size = round_up(attr->length, MLX5_SW_ICM_BLOCK_SIZE(dev)); 2446 act_size = roundup_pow_of_two(act_size); 2447 2448 dm->size = act_size; 2449 err = mlx5_dm_sw_icm_alloc(dev, type, act_size, attr->alignment, 2450 to_mucontext(ctx)->devx_uid, &dm->dev_addr, 2451 &dm->icm_dm.obj_id); 2452 if (err) 2453 return err; 2454 2455 err = uverbs_copy_to(attrs, 2456 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET, 2457 &dm->dev_addr, sizeof(dm->dev_addr)); 2458 if (err) 2459 mlx5_dm_sw_icm_dealloc(dev, type, dm->size, 2460 to_mucontext(ctx)->devx_uid, dm->dev_addr, 2461 dm->icm_dm.obj_id); 2462 2463 return err; 2464 } 2465 2466 struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev, 2467 struct ib_ucontext *context, 2468 struct ib_dm_alloc_attr *attr, 2469 struct uverbs_attr_bundle *attrs) 2470 { 2471 struct mlx5_ib_dm *dm; 2472 enum mlx5_ib_uapi_dm_type type; 2473 int err; 2474 2475 err = uverbs_get_const_default(&type, attrs, 2476 MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE, 2477 MLX5_IB_UAPI_DM_TYPE_MEMIC); 2478 if (err) 2479 return ERR_PTR(err); 2480 2481 mlx5_ib_dbg(to_mdev(ibdev), "alloc_dm req: dm_type=%d user_length=0x%llx log_alignment=%d\n", 2482 type, attr->length, attr->alignment); 2483 2484 err = check_dm_type_support(to_mdev(ibdev), type); 2485 if (err) 2486 return ERR_PTR(err); 2487 2488 dm = kzalloc(sizeof(*dm), GFP_KERNEL); 2489 if (!dm) 2490 return ERR_PTR(-ENOMEM); 2491 2492 dm->type = type; 2493 2494 switch (type) { 2495 case MLX5_IB_UAPI_DM_TYPE_MEMIC: 2496 err = handle_alloc_dm_memic(context, dm, 2497 attr, 2498 attrs); 2499 break; 2500 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM: 2501 err = handle_alloc_dm_sw_icm(context, dm, 2502 attr, attrs, 2503 MLX5_SW_ICM_TYPE_STEERING); 2504 break; 2505 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM: 2506 err = handle_alloc_dm_sw_icm(context, dm, 2507 attr, attrs, 2508 MLX5_SW_ICM_TYPE_HEADER_MODIFY); 2509 break; 2510 default: 2511 err = -EOPNOTSUPP; 2512 } 2513 2514 if (err) 2515 goto err_free; 2516 2517 return &dm->ibdm; 2518 2519 err_free: 2520 kfree(dm); 2521 return ERR_PTR(err); 2522 } 2523 2524 int mlx5_ib_dealloc_dm(struct ib_dm *ibdm, struct uverbs_attr_bundle *attrs) 2525 { 2526 struct mlx5_ib_ucontext *ctx = rdma_udata_to_drv_context( 2527 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext); 2528 struct mlx5_core_dev *dev = to_mdev(ibdm->device)->mdev; 2529 struct mlx5_ib_dm *dm = to_mdm(ibdm); 2530 int ret; 2531 2532 switch (dm->type) { 2533 case MLX5_IB_UAPI_DM_TYPE_MEMIC: 2534 rdma_user_mmap_entry_remove(&dm->mentry.rdma_entry); 2535 return 0; 2536 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM: 2537 ret = mlx5_dm_sw_icm_dealloc(dev, MLX5_SW_ICM_TYPE_STEERING, 2538 dm->size, ctx->devx_uid, dm->dev_addr, 2539 dm->icm_dm.obj_id); 2540 if (ret) 2541 return ret; 2542 break; 2543 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM: 2544 ret = mlx5_dm_sw_icm_dealloc(dev, MLX5_SW_ICM_TYPE_HEADER_MODIFY, 2545 dm->size, ctx->devx_uid, dm->dev_addr, 2546 dm->icm_dm.obj_id); 2547 if (ret) 2548 return ret; 2549 break; 2550 default: 2551 return -EOPNOTSUPP; 2552 } 2553 2554 kfree(dm); 2555 2556 return 0; 2557 } 2558 2559 static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata) 2560 { 2561 struct mlx5_ib_pd *pd = to_mpd(ibpd); 2562 struct ib_device *ibdev = ibpd->device; 2563 struct mlx5_ib_alloc_pd_resp resp; 2564 int err; 2565 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {}; 2566 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {}; 2567 u16 uid = 0; 2568 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 2569 udata, struct mlx5_ib_ucontext, ibucontext); 2570 2571 uid = context ? context->devx_uid : 0; 2572 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2573 MLX5_SET(alloc_pd_in, in, uid, uid); 2574 err = mlx5_cmd_exec_inout(to_mdev(ibdev)->mdev, alloc_pd, in, out); 2575 if (err) 2576 return err; 2577 2578 pd->pdn = MLX5_GET(alloc_pd_out, out, pd); 2579 pd->uid = uid; 2580 if (udata) { 2581 resp.pdn = pd->pdn; 2582 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 2583 mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid); 2584 return -EFAULT; 2585 } 2586 } 2587 2588 return 0; 2589 } 2590 2591 static void mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata) 2592 { 2593 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 2594 struct mlx5_ib_pd *mpd = to_mpd(pd); 2595 2596 mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid); 2597 } 2598 2599 enum { 2600 MATCH_CRITERIA_ENABLE_OUTER_BIT, 2601 MATCH_CRITERIA_ENABLE_MISC_BIT, 2602 MATCH_CRITERIA_ENABLE_INNER_BIT, 2603 MATCH_CRITERIA_ENABLE_MISC2_BIT 2604 }; 2605 2606 #define HEADER_IS_ZERO(match_criteria, headers) \ 2607 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \ 2608 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \ 2609 2610 static u8 get_match_criteria_enable(u32 *match_criteria) 2611 { 2612 u8 match_criteria_enable; 2613 2614 match_criteria_enable = 2615 (!HEADER_IS_ZERO(match_criteria, outer_headers)) << 2616 MATCH_CRITERIA_ENABLE_OUTER_BIT; 2617 match_criteria_enable |= 2618 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) << 2619 MATCH_CRITERIA_ENABLE_MISC_BIT; 2620 match_criteria_enable |= 2621 (!HEADER_IS_ZERO(match_criteria, inner_headers)) << 2622 MATCH_CRITERIA_ENABLE_INNER_BIT; 2623 match_criteria_enable |= 2624 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) << 2625 MATCH_CRITERIA_ENABLE_MISC2_BIT; 2626 2627 return match_criteria_enable; 2628 } 2629 2630 static int set_proto(void *outer_c, void *outer_v, u8 mask, u8 val) 2631 { 2632 u8 entry_mask; 2633 u8 entry_val; 2634 int err = 0; 2635 2636 if (!mask) 2637 goto out; 2638 2639 entry_mask = MLX5_GET(fte_match_set_lyr_2_4, outer_c, 2640 ip_protocol); 2641 entry_val = MLX5_GET(fte_match_set_lyr_2_4, outer_v, 2642 ip_protocol); 2643 if (!entry_mask) { 2644 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask); 2645 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val); 2646 goto out; 2647 } 2648 /* Don't override existing ip protocol */ 2649 if (mask != entry_mask || val != entry_val) 2650 err = -EINVAL; 2651 out: 2652 return err; 2653 } 2654 2655 static void set_flow_label(void *misc_c, void *misc_v, u32 mask, u32 val, 2656 bool inner) 2657 { 2658 if (inner) { 2659 MLX5_SET(fte_match_set_misc, 2660 misc_c, inner_ipv6_flow_label, mask); 2661 MLX5_SET(fte_match_set_misc, 2662 misc_v, inner_ipv6_flow_label, val); 2663 } else { 2664 MLX5_SET(fte_match_set_misc, 2665 misc_c, outer_ipv6_flow_label, mask); 2666 MLX5_SET(fte_match_set_misc, 2667 misc_v, outer_ipv6_flow_label, val); 2668 } 2669 } 2670 2671 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val) 2672 { 2673 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask); 2674 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val); 2675 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2); 2676 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2); 2677 } 2678 2679 static int check_mpls_supp_fields(u32 field_support, const __be32 *set_mask) 2680 { 2681 if (MLX5_GET(fte_match_mpls, set_mask, mpls_label) && 2682 !(field_support & MLX5_FIELD_SUPPORT_MPLS_LABEL)) 2683 return -EOPNOTSUPP; 2684 2685 if (MLX5_GET(fte_match_mpls, set_mask, mpls_exp) && 2686 !(field_support & MLX5_FIELD_SUPPORT_MPLS_EXP)) 2687 return -EOPNOTSUPP; 2688 2689 if (MLX5_GET(fte_match_mpls, set_mask, mpls_s_bos) && 2690 !(field_support & MLX5_FIELD_SUPPORT_MPLS_S_BOS)) 2691 return -EOPNOTSUPP; 2692 2693 if (MLX5_GET(fte_match_mpls, set_mask, mpls_ttl) && 2694 !(field_support & MLX5_FIELD_SUPPORT_MPLS_TTL)) 2695 return -EOPNOTSUPP; 2696 2697 return 0; 2698 } 2699 2700 #define LAST_ETH_FIELD vlan_tag 2701 #define LAST_IB_FIELD sl 2702 #define LAST_IPV4_FIELD tos 2703 #define LAST_IPV6_FIELD traffic_class 2704 #define LAST_TCP_UDP_FIELD src_port 2705 #define LAST_TUNNEL_FIELD tunnel_id 2706 #define LAST_FLOW_TAG_FIELD tag_id 2707 #define LAST_DROP_FIELD size 2708 #define LAST_COUNTERS_FIELD counters 2709 2710 /* Field is the last supported field */ 2711 #define FIELDS_NOT_SUPPORTED(filter, field)\ 2712 memchr_inv((void *)&filter.field +\ 2713 sizeof(filter.field), 0,\ 2714 sizeof(filter) -\ 2715 offsetof(typeof(filter), field) -\ 2716 sizeof(filter.field)) 2717 2718 int parse_flow_flow_action(struct mlx5_ib_flow_action *maction, 2719 bool is_egress, 2720 struct mlx5_flow_act *action) 2721 { 2722 2723 switch (maction->ib_action.type) { 2724 case IB_FLOW_ACTION_ESP: 2725 if (action->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT | 2726 MLX5_FLOW_CONTEXT_ACTION_DECRYPT)) 2727 return -EINVAL; 2728 /* Currently only AES_GCM keymat is supported by the driver */ 2729 action->esp_id = (uintptr_t)maction->esp_aes_gcm.ctx; 2730 action->action |= is_egress ? 2731 MLX5_FLOW_CONTEXT_ACTION_ENCRYPT : 2732 MLX5_FLOW_CONTEXT_ACTION_DECRYPT; 2733 return 0; 2734 case IB_FLOW_ACTION_UNSPECIFIED: 2735 if (maction->flow_action_raw.sub_type == 2736 MLX5_IB_FLOW_ACTION_MODIFY_HEADER) { 2737 if (action->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) 2738 return -EINVAL; 2739 action->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR; 2740 action->modify_hdr = 2741 maction->flow_action_raw.modify_hdr; 2742 return 0; 2743 } 2744 if (maction->flow_action_raw.sub_type == 2745 MLX5_IB_FLOW_ACTION_DECAP) { 2746 if (action->action & MLX5_FLOW_CONTEXT_ACTION_DECAP) 2747 return -EINVAL; 2748 action->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP; 2749 return 0; 2750 } 2751 if (maction->flow_action_raw.sub_type == 2752 MLX5_IB_FLOW_ACTION_PACKET_REFORMAT) { 2753 if (action->action & 2754 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT) 2755 return -EINVAL; 2756 action->action |= 2757 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT; 2758 action->pkt_reformat = 2759 maction->flow_action_raw.pkt_reformat; 2760 return 0; 2761 } 2762 /* fall through */ 2763 default: 2764 return -EOPNOTSUPP; 2765 } 2766 } 2767 2768 static int parse_flow_attr(struct mlx5_core_dev *mdev, 2769 struct mlx5_flow_spec *spec, 2770 const union ib_flow_spec *ib_spec, 2771 const struct ib_flow_attr *flow_attr, 2772 struct mlx5_flow_act *action, u32 prev_type) 2773 { 2774 struct mlx5_flow_context *flow_context = &spec->flow_context; 2775 u32 *match_c = spec->match_criteria; 2776 u32 *match_v = spec->match_value; 2777 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c, 2778 misc_parameters); 2779 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v, 2780 misc_parameters); 2781 void *misc_params2_c = MLX5_ADDR_OF(fte_match_param, match_c, 2782 misc_parameters_2); 2783 void *misc_params2_v = MLX5_ADDR_OF(fte_match_param, match_v, 2784 misc_parameters_2); 2785 void *headers_c; 2786 void *headers_v; 2787 int match_ipv; 2788 int ret; 2789 2790 if (ib_spec->type & IB_FLOW_SPEC_INNER) { 2791 headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 2792 inner_headers); 2793 headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 2794 inner_headers); 2795 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2796 ft_field_support.inner_ip_version); 2797 } else { 2798 headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 2799 outer_headers); 2800 headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 2801 outer_headers); 2802 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2803 ft_field_support.outer_ip_version); 2804 } 2805 2806 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) { 2807 case IB_FLOW_SPEC_ETH: 2808 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD)) 2809 return -EOPNOTSUPP; 2810 2811 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2812 dmac_47_16), 2813 ib_spec->eth.mask.dst_mac); 2814 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2815 dmac_47_16), 2816 ib_spec->eth.val.dst_mac); 2817 2818 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2819 smac_47_16), 2820 ib_spec->eth.mask.src_mac); 2821 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2822 smac_47_16), 2823 ib_spec->eth.val.src_mac); 2824 2825 if (ib_spec->eth.mask.vlan_tag) { 2826 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2827 cvlan_tag, 1); 2828 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2829 cvlan_tag, 1); 2830 2831 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2832 first_vid, ntohs(ib_spec->eth.mask.vlan_tag)); 2833 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2834 first_vid, ntohs(ib_spec->eth.val.vlan_tag)); 2835 2836 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2837 first_cfi, 2838 ntohs(ib_spec->eth.mask.vlan_tag) >> 12); 2839 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2840 first_cfi, 2841 ntohs(ib_spec->eth.val.vlan_tag) >> 12); 2842 2843 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2844 first_prio, 2845 ntohs(ib_spec->eth.mask.vlan_tag) >> 13); 2846 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2847 first_prio, 2848 ntohs(ib_spec->eth.val.vlan_tag) >> 13); 2849 } 2850 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2851 ethertype, ntohs(ib_spec->eth.mask.ether_type)); 2852 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2853 ethertype, ntohs(ib_spec->eth.val.ether_type)); 2854 break; 2855 case IB_FLOW_SPEC_IPV4: 2856 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD)) 2857 return -EOPNOTSUPP; 2858 2859 if (match_ipv) { 2860 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2861 ip_version, 0xf); 2862 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2863 ip_version, MLX5_FS_IPV4_VERSION); 2864 } else { 2865 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2866 ethertype, 0xffff); 2867 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2868 ethertype, ETH_P_IP); 2869 } 2870 2871 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2872 src_ipv4_src_ipv6.ipv4_layout.ipv4), 2873 &ib_spec->ipv4.mask.src_ip, 2874 sizeof(ib_spec->ipv4.mask.src_ip)); 2875 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2876 src_ipv4_src_ipv6.ipv4_layout.ipv4), 2877 &ib_spec->ipv4.val.src_ip, 2878 sizeof(ib_spec->ipv4.val.src_ip)); 2879 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2880 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 2881 &ib_spec->ipv4.mask.dst_ip, 2882 sizeof(ib_spec->ipv4.mask.dst_ip)); 2883 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2884 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 2885 &ib_spec->ipv4.val.dst_ip, 2886 sizeof(ib_spec->ipv4.val.dst_ip)); 2887 2888 set_tos(headers_c, headers_v, 2889 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos); 2890 2891 if (set_proto(headers_c, headers_v, 2892 ib_spec->ipv4.mask.proto, 2893 ib_spec->ipv4.val.proto)) 2894 return -EINVAL; 2895 break; 2896 case IB_FLOW_SPEC_IPV6: 2897 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD)) 2898 return -EOPNOTSUPP; 2899 2900 if (match_ipv) { 2901 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2902 ip_version, 0xf); 2903 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2904 ip_version, MLX5_FS_IPV6_VERSION); 2905 } else { 2906 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2907 ethertype, 0xffff); 2908 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2909 ethertype, ETH_P_IPV6); 2910 } 2911 2912 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2913 src_ipv4_src_ipv6.ipv6_layout.ipv6), 2914 &ib_spec->ipv6.mask.src_ip, 2915 sizeof(ib_spec->ipv6.mask.src_ip)); 2916 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2917 src_ipv4_src_ipv6.ipv6_layout.ipv6), 2918 &ib_spec->ipv6.val.src_ip, 2919 sizeof(ib_spec->ipv6.val.src_ip)); 2920 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2921 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 2922 &ib_spec->ipv6.mask.dst_ip, 2923 sizeof(ib_spec->ipv6.mask.dst_ip)); 2924 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2925 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 2926 &ib_spec->ipv6.val.dst_ip, 2927 sizeof(ib_spec->ipv6.val.dst_ip)); 2928 2929 set_tos(headers_c, headers_v, 2930 ib_spec->ipv6.mask.traffic_class, 2931 ib_spec->ipv6.val.traffic_class); 2932 2933 if (set_proto(headers_c, headers_v, 2934 ib_spec->ipv6.mask.next_hdr, 2935 ib_spec->ipv6.val.next_hdr)) 2936 return -EINVAL; 2937 2938 set_flow_label(misc_params_c, misc_params_v, 2939 ntohl(ib_spec->ipv6.mask.flow_label), 2940 ntohl(ib_spec->ipv6.val.flow_label), 2941 ib_spec->type & IB_FLOW_SPEC_INNER); 2942 break; 2943 case IB_FLOW_SPEC_ESP: 2944 if (ib_spec->esp.mask.seq) 2945 return -EOPNOTSUPP; 2946 2947 MLX5_SET(fte_match_set_misc, misc_params_c, outer_esp_spi, 2948 ntohl(ib_spec->esp.mask.spi)); 2949 MLX5_SET(fte_match_set_misc, misc_params_v, outer_esp_spi, 2950 ntohl(ib_spec->esp.val.spi)); 2951 break; 2952 case IB_FLOW_SPEC_TCP: 2953 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 2954 LAST_TCP_UDP_FIELD)) 2955 return -EOPNOTSUPP; 2956 2957 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_TCP)) 2958 return -EINVAL; 2959 2960 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport, 2961 ntohs(ib_spec->tcp_udp.mask.src_port)); 2962 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport, 2963 ntohs(ib_spec->tcp_udp.val.src_port)); 2964 2965 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport, 2966 ntohs(ib_spec->tcp_udp.mask.dst_port)); 2967 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport, 2968 ntohs(ib_spec->tcp_udp.val.dst_port)); 2969 break; 2970 case IB_FLOW_SPEC_UDP: 2971 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 2972 LAST_TCP_UDP_FIELD)) 2973 return -EOPNOTSUPP; 2974 2975 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_UDP)) 2976 return -EINVAL; 2977 2978 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport, 2979 ntohs(ib_spec->tcp_udp.mask.src_port)); 2980 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport, 2981 ntohs(ib_spec->tcp_udp.val.src_port)); 2982 2983 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport, 2984 ntohs(ib_spec->tcp_udp.mask.dst_port)); 2985 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, 2986 ntohs(ib_spec->tcp_udp.val.dst_port)); 2987 break; 2988 case IB_FLOW_SPEC_GRE: 2989 if (ib_spec->gre.mask.c_ks_res0_ver) 2990 return -EOPNOTSUPP; 2991 2992 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_GRE)) 2993 return -EINVAL; 2994 2995 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol, 2996 0xff); 2997 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, 2998 IPPROTO_GRE); 2999 3000 MLX5_SET(fte_match_set_misc, misc_params_c, gre_protocol, 3001 ntohs(ib_spec->gre.mask.protocol)); 3002 MLX5_SET(fte_match_set_misc, misc_params_v, gre_protocol, 3003 ntohs(ib_spec->gre.val.protocol)); 3004 3005 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_c, 3006 gre_key.nvgre.hi), 3007 &ib_spec->gre.mask.key, 3008 sizeof(ib_spec->gre.mask.key)); 3009 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_v, 3010 gre_key.nvgre.hi), 3011 &ib_spec->gre.val.key, 3012 sizeof(ib_spec->gre.val.key)); 3013 break; 3014 case IB_FLOW_SPEC_MPLS: 3015 switch (prev_type) { 3016 case IB_FLOW_SPEC_UDP: 3017 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 3018 ft_field_support.outer_first_mpls_over_udp), 3019 &ib_spec->mpls.mask.tag)) 3020 return -EOPNOTSUPP; 3021 3022 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v, 3023 outer_first_mpls_over_udp), 3024 &ib_spec->mpls.val.tag, 3025 sizeof(ib_spec->mpls.val.tag)); 3026 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c, 3027 outer_first_mpls_over_udp), 3028 &ib_spec->mpls.mask.tag, 3029 sizeof(ib_spec->mpls.mask.tag)); 3030 break; 3031 case IB_FLOW_SPEC_GRE: 3032 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 3033 ft_field_support.outer_first_mpls_over_gre), 3034 &ib_spec->mpls.mask.tag)) 3035 return -EOPNOTSUPP; 3036 3037 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v, 3038 outer_first_mpls_over_gre), 3039 &ib_spec->mpls.val.tag, 3040 sizeof(ib_spec->mpls.val.tag)); 3041 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c, 3042 outer_first_mpls_over_gre), 3043 &ib_spec->mpls.mask.tag, 3044 sizeof(ib_spec->mpls.mask.tag)); 3045 break; 3046 default: 3047 if (ib_spec->type & IB_FLOW_SPEC_INNER) { 3048 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 3049 ft_field_support.inner_first_mpls), 3050 &ib_spec->mpls.mask.tag)) 3051 return -EOPNOTSUPP; 3052 3053 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v, 3054 inner_first_mpls), 3055 &ib_spec->mpls.val.tag, 3056 sizeof(ib_spec->mpls.val.tag)); 3057 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c, 3058 inner_first_mpls), 3059 &ib_spec->mpls.mask.tag, 3060 sizeof(ib_spec->mpls.mask.tag)); 3061 } else { 3062 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 3063 ft_field_support.outer_first_mpls), 3064 &ib_spec->mpls.mask.tag)) 3065 return -EOPNOTSUPP; 3066 3067 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v, 3068 outer_first_mpls), 3069 &ib_spec->mpls.val.tag, 3070 sizeof(ib_spec->mpls.val.tag)); 3071 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c, 3072 outer_first_mpls), 3073 &ib_spec->mpls.mask.tag, 3074 sizeof(ib_spec->mpls.mask.tag)); 3075 } 3076 } 3077 break; 3078 case IB_FLOW_SPEC_VXLAN_TUNNEL: 3079 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask, 3080 LAST_TUNNEL_FIELD)) 3081 return -EOPNOTSUPP; 3082 3083 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni, 3084 ntohl(ib_spec->tunnel.mask.tunnel_id)); 3085 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni, 3086 ntohl(ib_spec->tunnel.val.tunnel_id)); 3087 break; 3088 case IB_FLOW_SPEC_ACTION_TAG: 3089 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag, 3090 LAST_FLOW_TAG_FIELD)) 3091 return -EOPNOTSUPP; 3092 if (ib_spec->flow_tag.tag_id >= BIT(24)) 3093 return -EINVAL; 3094 3095 flow_context->flow_tag = ib_spec->flow_tag.tag_id; 3096 flow_context->flags |= FLOW_CONTEXT_HAS_TAG; 3097 break; 3098 case IB_FLOW_SPEC_ACTION_DROP: 3099 if (FIELDS_NOT_SUPPORTED(ib_spec->drop, 3100 LAST_DROP_FIELD)) 3101 return -EOPNOTSUPP; 3102 action->action |= MLX5_FLOW_CONTEXT_ACTION_DROP; 3103 break; 3104 case IB_FLOW_SPEC_ACTION_HANDLE: 3105 ret = parse_flow_flow_action(to_mflow_act(ib_spec->action.act), 3106 flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS, action); 3107 if (ret) 3108 return ret; 3109 break; 3110 case IB_FLOW_SPEC_ACTION_COUNT: 3111 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_count, 3112 LAST_COUNTERS_FIELD)) 3113 return -EOPNOTSUPP; 3114 3115 /* for now support only one counters spec per flow */ 3116 if (action->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) 3117 return -EINVAL; 3118 3119 action->counters = ib_spec->flow_count.counters; 3120 action->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT; 3121 break; 3122 default: 3123 return -EINVAL; 3124 } 3125 3126 return 0; 3127 } 3128 3129 /* If a flow could catch both multicast and unicast packets, 3130 * it won't fall into the multicast flow steering table and this rule 3131 * could steal other multicast packets. 3132 */ 3133 static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr) 3134 { 3135 union ib_flow_spec *flow_spec; 3136 3137 if (ib_attr->type != IB_FLOW_ATTR_NORMAL || 3138 ib_attr->num_of_specs < 1) 3139 return false; 3140 3141 flow_spec = (union ib_flow_spec *)(ib_attr + 1); 3142 if (flow_spec->type == IB_FLOW_SPEC_IPV4) { 3143 struct ib_flow_spec_ipv4 *ipv4_spec; 3144 3145 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec; 3146 if (ipv4_is_multicast(ipv4_spec->val.dst_ip)) 3147 return true; 3148 3149 return false; 3150 } 3151 3152 if (flow_spec->type == IB_FLOW_SPEC_ETH) { 3153 struct ib_flow_spec_eth *eth_spec; 3154 3155 eth_spec = (struct ib_flow_spec_eth *)flow_spec; 3156 return is_multicast_ether_addr(eth_spec->mask.dst_mac) && 3157 is_multicast_ether_addr(eth_spec->val.dst_mac); 3158 } 3159 3160 return false; 3161 } 3162 3163 enum valid_spec { 3164 VALID_SPEC_INVALID, 3165 VALID_SPEC_VALID, 3166 VALID_SPEC_NA, 3167 }; 3168 3169 static enum valid_spec 3170 is_valid_esp_aes_gcm(struct mlx5_core_dev *mdev, 3171 const struct mlx5_flow_spec *spec, 3172 const struct mlx5_flow_act *flow_act, 3173 bool egress) 3174 { 3175 const u32 *match_c = spec->match_criteria; 3176 bool is_crypto = 3177 (flow_act->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT | 3178 MLX5_FLOW_CONTEXT_ACTION_DECRYPT)); 3179 bool is_ipsec = mlx5_fs_is_ipsec_flow(match_c); 3180 bool is_drop = flow_act->action & MLX5_FLOW_CONTEXT_ACTION_DROP; 3181 3182 /* 3183 * Currently only crypto is supported in egress, when regular egress 3184 * rules would be supported, always return VALID_SPEC_NA. 3185 */ 3186 if (!is_crypto) 3187 return VALID_SPEC_NA; 3188 3189 return is_crypto && is_ipsec && 3190 (!egress || (!is_drop && 3191 !(spec->flow_context.flags & FLOW_CONTEXT_HAS_TAG))) ? 3192 VALID_SPEC_VALID : VALID_SPEC_INVALID; 3193 } 3194 3195 static bool is_valid_spec(struct mlx5_core_dev *mdev, 3196 const struct mlx5_flow_spec *spec, 3197 const struct mlx5_flow_act *flow_act, 3198 bool egress) 3199 { 3200 /* We curretly only support ipsec egress flow */ 3201 return is_valid_esp_aes_gcm(mdev, spec, flow_act, egress) != VALID_SPEC_INVALID; 3202 } 3203 3204 static bool is_valid_ethertype(struct mlx5_core_dev *mdev, 3205 const struct ib_flow_attr *flow_attr, 3206 bool check_inner) 3207 { 3208 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1); 3209 int match_ipv = check_inner ? 3210 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 3211 ft_field_support.inner_ip_version) : 3212 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 3213 ft_field_support.outer_ip_version); 3214 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0; 3215 bool ipv4_spec_valid, ipv6_spec_valid; 3216 unsigned int ip_spec_type = 0; 3217 bool has_ethertype = false; 3218 unsigned int spec_index; 3219 bool mask_valid = true; 3220 u16 eth_type = 0; 3221 bool type_valid; 3222 3223 /* Validate that ethertype is correct */ 3224 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 3225 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) && 3226 ib_spec->eth.mask.ether_type) { 3227 mask_valid = (ib_spec->eth.mask.ether_type == 3228 htons(0xffff)); 3229 has_ethertype = true; 3230 eth_type = ntohs(ib_spec->eth.val.ether_type); 3231 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) || 3232 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) { 3233 ip_spec_type = ib_spec->type; 3234 } 3235 ib_spec = (void *)ib_spec + ib_spec->size; 3236 } 3237 3238 type_valid = (!has_ethertype) || (!ip_spec_type); 3239 if (!type_valid && mask_valid) { 3240 ipv4_spec_valid = (eth_type == ETH_P_IP) && 3241 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit)); 3242 ipv6_spec_valid = (eth_type == ETH_P_IPV6) && 3243 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit)); 3244 3245 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) || 3246 (((eth_type == ETH_P_MPLS_UC) || 3247 (eth_type == ETH_P_MPLS_MC)) && match_ipv); 3248 } 3249 3250 return type_valid; 3251 } 3252 3253 static bool is_valid_attr(struct mlx5_core_dev *mdev, 3254 const struct ib_flow_attr *flow_attr) 3255 { 3256 return is_valid_ethertype(mdev, flow_attr, false) && 3257 is_valid_ethertype(mdev, flow_attr, true); 3258 } 3259 3260 static void put_flow_table(struct mlx5_ib_dev *dev, 3261 struct mlx5_ib_flow_prio *prio, bool ft_added) 3262 { 3263 prio->refcount -= !!ft_added; 3264 if (!prio->refcount) { 3265 mlx5_destroy_flow_table(prio->flow_table); 3266 prio->flow_table = NULL; 3267 } 3268 } 3269 3270 static void counters_clear_description(struct ib_counters *counters) 3271 { 3272 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters); 3273 3274 mutex_lock(&mcounters->mcntrs_mutex); 3275 kfree(mcounters->counters_data); 3276 mcounters->counters_data = NULL; 3277 mcounters->cntrs_max_index = 0; 3278 mutex_unlock(&mcounters->mcntrs_mutex); 3279 } 3280 3281 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id) 3282 { 3283 struct mlx5_ib_flow_handler *handler = container_of(flow_id, 3284 struct mlx5_ib_flow_handler, 3285 ibflow); 3286 struct mlx5_ib_flow_handler *iter, *tmp; 3287 struct mlx5_ib_dev *dev = handler->dev; 3288 3289 mutex_lock(&dev->flow_db->lock); 3290 3291 list_for_each_entry_safe(iter, tmp, &handler->list, list) { 3292 mlx5_del_flow_rules(iter->rule); 3293 put_flow_table(dev, iter->prio, true); 3294 list_del(&iter->list); 3295 kfree(iter); 3296 } 3297 3298 mlx5_del_flow_rules(handler->rule); 3299 put_flow_table(dev, handler->prio, true); 3300 if (handler->ibcounters && 3301 atomic_read(&handler->ibcounters->usecnt) == 1) 3302 counters_clear_description(handler->ibcounters); 3303 3304 mutex_unlock(&dev->flow_db->lock); 3305 if (handler->flow_matcher) 3306 atomic_dec(&handler->flow_matcher->usecnt); 3307 kfree(handler); 3308 3309 return 0; 3310 } 3311 3312 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap) 3313 { 3314 priority *= 2; 3315 if (!dont_trap) 3316 priority++; 3317 return priority; 3318 } 3319 3320 enum flow_table_type { 3321 MLX5_IB_FT_RX, 3322 MLX5_IB_FT_TX 3323 }; 3324 3325 #define MLX5_FS_MAX_TYPES 6 3326 #define MLX5_FS_MAX_ENTRIES BIT(16) 3327 3328 static struct mlx5_ib_flow_prio *_get_prio(struct mlx5_flow_namespace *ns, 3329 struct mlx5_ib_flow_prio *prio, 3330 int priority, 3331 int num_entries, int num_groups, 3332 u32 flags) 3333 { 3334 struct mlx5_flow_table_attr ft_attr = {}; 3335 struct mlx5_flow_table *ft; 3336 3337 ft_attr.prio = priority; 3338 ft_attr.max_fte = num_entries; 3339 ft_attr.flags = flags; 3340 ft_attr.autogroup.max_num_groups = num_groups; 3341 ft = mlx5_create_auto_grouped_flow_table(ns, &ft_attr); 3342 if (IS_ERR(ft)) 3343 return ERR_CAST(ft); 3344 3345 prio->flow_table = ft; 3346 prio->refcount = 0; 3347 return prio; 3348 } 3349 3350 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev, 3351 struct ib_flow_attr *flow_attr, 3352 enum flow_table_type ft_type) 3353 { 3354 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP; 3355 struct mlx5_flow_namespace *ns = NULL; 3356 struct mlx5_ib_flow_prio *prio; 3357 struct mlx5_flow_table *ft; 3358 int max_table_size; 3359 int num_entries; 3360 int num_groups; 3361 bool esw_encap; 3362 u32 flags = 0; 3363 int priority; 3364 3365 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 3366 log_max_ft_size)); 3367 esw_encap = mlx5_eswitch_get_encap_mode(dev->mdev) != 3368 DEVLINK_ESWITCH_ENCAP_MODE_NONE; 3369 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 3370 enum mlx5_flow_namespace_type fn_type; 3371 3372 if (flow_is_multicast_only(flow_attr) && 3373 !dont_trap) 3374 priority = MLX5_IB_FLOW_MCAST_PRIO; 3375 else 3376 priority = ib_prio_to_core_prio(flow_attr->priority, 3377 dont_trap); 3378 if (ft_type == MLX5_IB_FT_RX) { 3379 fn_type = MLX5_FLOW_NAMESPACE_BYPASS; 3380 prio = &dev->flow_db->prios[priority]; 3381 if (!dev->is_rep && !esw_encap && 3382 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap)) 3383 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP; 3384 if (!dev->is_rep && !esw_encap && 3385 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 3386 reformat_l3_tunnel_to_l2)) 3387 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT; 3388 } else { 3389 max_table_size = 3390 BIT(MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, 3391 log_max_ft_size)); 3392 fn_type = MLX5_FLOW_NAMESPACE_EGRESS; 3393 prio = &dev->flow_db->egress_prios[priority]; 3394 if (!dev->is_rep && !esw_encap && 3395 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat)) 3396 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT; 3397 } 3398 ns = mlx5_get_flow_namespace(dev->mdev, fn_type); 3399 num_entries = MLX5_FS_MAX_ENTRIES; 3400 num_groups = MLX5_FS_MAX_TYPES; 3401 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 3402 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 3403 ns = mlx5_get_flow_namespace(dev->mdev, 3404 MLX5_FLOW_NAMESPACE_LEFTOVERS); 3405 build_leftovers_ft_param(&priority, 3406 &num_entries, 3407 &num_groups); 3408 prio = &dev->flow_db->prios[MLX5_IB_FLOW_LEFTOVERS_PRIO]; 3409 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 3410 if (!MLX5_CAP_FLOWTABLE(dev->mdev, 3411 allow_sniffer_and_nic_rx_shared_tir)) 3412 return ERR_PTR(-ENOTSUPP); 3413 3414 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ? 3415 MLX5_FLOW_NAMESPACE_SNIFFER_RX : 3416 MLX5_FLOW_NAMESPACE_SNIFFER_TX); 3417 3418 prio = &dev->flow_db->sniffer[ft_type]; 3419 priority = 0; 3420 num_entries = 1; 3421 num_groups = 1; 3422 } 3423 3424 if (!ns) 3425 return ERR_PTR(-ENOTSUPP); 3426 3427 max_table_size = min_t(int, num_entries, max_table_size); 3428 3429 ft = prio->flow_table; 3430 if (!ft) 3431 return _get_prio(ns, prio, priority, max_table_size, num_groups, 3432 flags); 3433 3434 return prio; 3435 } 3436 3437 static void set_underlay_qp(struct mlx5_ib_dev *dev, 3438 struct mlx5_flow_spec *spec, 3439 u32 underlay_qpn) 3440 { 3441 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, 3442 spec->match_criteria, 3443 misc_parameters); 3444 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, 3445 misc_parameters); 3446 3447 if (underlay_qpn && 3448 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 3449 ft_field_support.bth_dst_qp)) { 3450 MLX5_SET(fte_match_set_misc, 3451 misc_params_v, bth_dst_qp, underlay_qpn); 3452 MLX5_SET(fte_match_set_misc, 3453 misc_params_c, bth_dst_qp, 0xffffff); 3454 } 3455 } 3456 3457 static int read_flow_counters(struct ib_device *ibdev, 3458 struct mlx5_read_counters_attr *read_attr) 3459 { 3460 struct mlx5_fc *fc = read_attr->hw_cntrs_hndl; 3461 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3462 3463 return mlx5_fc_query(dev->mdev, fc, 3464 &read_attr->out[IB_COUNTER_PACKETS], 3465 &read_attr->out[IB_COUNTER_BYTES]); 3466 } 3467 3468 /* flow counters currently expose two counters packets and bytes */ 3469 #define FLOW_COUNTERS_NUM 2 3470 static int counters_set_description(struct ib_counters *counters, 3471 enum mlx5_ib_counters_type counters_type, 3472 struct mlx5_ib_flow_counters_desc *desc_data, 3473 u32 ncounters) 3474 { 3475 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters); 3476 u32 cntrs_max_index = 0; 3477 int i; 3478 3479 if (counters_type != MLX5_IB_COUNTERS_FLOW) 3480 return -EINVAL; 3481 3482 /* init the fields for the object */ 3483 mcounters->type = counters_type; 3484 mcounters->read_counters = read_flow_counters; 3485 mcounters->counters_num = FLOW_COUNTERS_NUM; 3486 mcounters->ncounters = ncounters; 3487 /* each counter entry have both description and index pair */ 3488 for (i = 0; i < ncounters; i++) { 3489 if (desc_data[i].description > IB_COUNTER_BYTES) 3490 return -EINVAL; 3491 3492 if (cntrs_max_index <= desc_data[i].index) 3493 cntrs_max_index = desc_data[i].index + 1; 3494 } 3495 3496 mutex_lock(&mcounters->mcntrs_mutex); 3497 mcounters->counters_data = desc_data; 3498 mcounters->cntrs_max_index = cntrs_max_index; 3499 mutex_unlock(&mcounters->mcntrs_mutex); 3500 3501 return 0; 3502 } 3503 3504 #define MAX_COUNTERS_NUM (USHRT_MAX / (sizeof(u32) * 2)) 3505 static int flow_counters_set_data(struct ib_counters *ibcounters, 3506 struct mlx5_ib_create_flow *ucmd) 3507 { 3508 struct mlx5_ib_mcounters *mcounters = to_mcounters(ibcounters); 3509 struct mlx5_ib_flow_counters_data *cntrs_data = NULL; 3510 struct mlx5_ib_flow_counters_desc *desc_data = NULL; 3511 bool hw_hndl = false; 3512 int ret = 0; 3513 3514 if (ucmd && ucmd->ncounters_data != 0) { 3515 cntrs_data = ucmd->data; 3516 if (cntrs_data->ncounters > MAX_COUNTERS_NUM) 3517 return -EINVAL; 3518 3519 desc_data = kcalloc(cntrs_data->ncounters, 3520 sizeof(*desc_data), 3521 GFP_KERNEL); 3522 if (!desc_data) 3523 return -ENOMEM; 3524 3525 if (copy_from_user(desc_data, 3526 u64_to_user_ptr(cntrs_data->counters_data), 3527 sizeof(*desc_data) * cntrs_data->ncounters)) { 3528 ret = -EFAULT; 3529 goto free; 3530 } 3531 } 3532 3533 if (!mcounters->hw_cntrs_hndl) { 3534 mcounters->hw_cntrs_hndl = mlx5_fc_create( 3535 to_mdev(ibcounters->device)->mdev, false); 3536 if (IS_ERR(mcounters->hw_cntrs_hndl)) { 3537 ret = PTR_ERR(mcounters->hw_cntrs_hndl); 3538 goto free; 3539 } 3540 hw_hndl = true; 3541 } 3542 3543 if (desc_data) { 3544 /* counters already bound to at least one flow */ 3545 if (mcounters->cntrs_max_index) { 3546 ret = -EINVAL; 3547 goto free_hndl; 3548 } 3549 3550 ret = counters_set_description(ibcounters, 3551 MLX5_IB_COUNTERS_FLOW, 3552 desc_data, 3553 cntrs_data->ncounters); 3554 if (ret) 3555 goto free_hndl; 3556 3557 } else if (!mcounters->cntrs_max_index) { 3558 /* counters not bound yet, must have udata passed */ 3559 ret = -EINVAL; 3560 goto free_hndl; 3561 } 3562 3563 return 0; 3564 3565 free_hndl: 3566 if (hw_hndl) { 3567 mlx5_fc_destroy(to_mdev(ibcounters->device)->mdev, 3568 mcounters->hw_cntrs_hndl); 3569 mcounters->hw_cntrs_hndl = NULL; 3570 } 3571 free: 3572 kfree(desc_data); 3573 return ret; 3574 } 3575 3576 static void mlx5_ib_set_rule_source_port(struct mlx5_ib_dev *dev, 3577 struct mlx5_flow_spec *spec, 3578 struct mlx5_eswitch_rep *rep) 3579 { 3580 struct mlx5_eswitch *esw = dev->mdev->priv.eswitch; 3581 void *misc; 3582 3583 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) { 3584 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, 3585 misc_parameters_2); 3586 3587 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0, 3588 mlx5_eswitch_get_vport_metadata_for_match(esw, 3589 rep->vport)); 3590 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, 3591 misc_parameters_2); 3592 3593 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0, 3594 mlx5_eswitch_get_vport_metadata_mask()); 3595 } else { 3596 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, 3597 misc_parameters); 3598 3599 MLX5_SET(fte_match_set_misc, misc, source_port, rep->vport); 3600 3601 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, 3602 misc_parameters); 3603 3604 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port); 3605 } 3606 } 3607 3608 static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev, 3609 struct mlx5_ib_flow_prio *ft_prio, 3610 const struct ib_flow_attr *flow_attr, 3611 struct mlx5_flow_destination *dst, 3612 u32 underlay_qpn, 3613 struct mlx5_ib_create_flow *ucmd) 3614 { 3615 struct mlx5_flow_table *ft = ft_prio->flow_table; 3616 struct mlx5_ib_flow_handler *handler; 3617 struct mlx5_flow_act flow_act = {}; 3618 struct mlx5_flow_spec *spec; 3619 struct mlx5_flow_destination dest_arr[2] = {}; 3620 struct mlx5_flow_destination *rule_dst = dest_arr; 3621 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr); 3622 unsigned int spec_index; 3623 u32 prev_type = 0; 3624 int err = 0; 3625 int dest_num = 0; 3626 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS; 3627 3628 if (!is_valid_attr(dev->mdev, flow_attr)) 3629 return ERR_PTR(-EINVAL); 3630 3631 if (dev->is_rep && is_egress) 3632 return ERR_PTR(-EINVAL); 3633 3634 spec = kvzalloc(sizeof(*spec), GFP_KERNEL); 3635 handler = kzalloc(sizeof(*handler), GFP_KERNEL); 3636 if (!handler || !spec) { 3637 err = -ENOMEM; 3638 goto free; 3639 } 3640 3641 INIT_LIST_HEAD(&handler->list); 3642 3643 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 3644 err = parse_flow_attr(dev->mdev, spec, 3645 ib_flow, flow_attr, &flow_act, 3646 prev_type); 3647 if (err < 0) 3648 goto free; 3649 3650 prev_type = ((union ib_flow_spec *)ib_flow)->type; 3651 ib_flow += ((union ib_flow_spec *)ib_flow)->size; 3652 } 3653 3654 if (dst && !(flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP)) { 3655 memcpy(&dest_arr[0], dst, sizeof(*dst)); 3656 dest_num++; 3657 } 3658 3659 if (!flow_is_multicast_only(flow_attr)) 3660 set_underlay_qp(dev, spec, underlay_qpn); 3661 3662 if (dev->is_rep) { 3663 struct mlx5_eswitch_rep *rep; 3664 3665 rep = dev->port[flow_attr->port - 1].rep; 3666 if (!rep) { 3667 err = -EINVAL; 3668 goto free; 3669 } 3670 3671 mlx5_ib_set_rule_source_port(dev, spec, rep); 3672 } 3673 3674 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria); 3675 3676 if (is_egress && 3677 !is_valid_spec(dev->mdev, spec, &flow_act, is_egress)) { 3678 err = -EINVAL; 3679 goto free; 3680 } 3681 3682 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) { 3683 struct mlx5_ib_mcounters *mcounters; 3684 3685 err = flow_counters_set_data(flow_act.counters, ucmd); 3686 if (err) 3687 goto free; 3688 3689 mcounters = to_mcounters(flow_act.counters); 3690 handler->ibcounters = flow_act.counters; 3691 dest_arr[dest_num].type = 3692 MLX5_FLOW_DESTINATION_TYPE_COUNTER; 3693 dest_arr[dest_num].counter_id = 3694 mlx5_fc_id(mcounters->hw_cntrs_hndl); 3695 dest_num++; 3696 } 3697 3698 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP) { 3699 if (!dest_num) 3700 rule_dst = NULL; 3701 } else { 3702 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) 3703 flow_act.action |= 3704 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO; 3705 if (is_egress) 3706 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW; 3707 else if (dest_num) 3708 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; 3709 } 3710 3711 if ((spec->flow_context.flags & FLOW_CONTEXT_HAS_TAG) && 3712 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 3713 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) { 3714 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n", 3715 spec->flow_context.flow_tag, flow_attr->type); 3716 err = -EINVAL; 3717 goto free; 3718 } 3719 handler->rule = mlx5_add_flow_rules(ft, spec, 3720 &flow_act, 3721 rule_dst, dest_num); 3722 3723 if (IS_ERR(handler->rule)) { 3724 err = PTR_ERR(handler->rule); 3725 goto free; 3726 } 3727 3728 ft_prio->refcount++; 3729 handler->prio = ft_prio; 3730 handler->dev = dev; 3731 3732 ft_prio->flow_table = ft; 3733 free: 3734 if (err && handler) { 3735 if (handler->ibcounters && 3736 atomic_read(&handler->ibcounters->usecnt) == 1) 3737 counters_clear_description(handler->ibcounters); 3738 kfree(handler); 3739 } 3740 kvfree(spec); 3741 return err ? ERR_PTR(err) : handler; 3742 } 3743 3744 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev, 3745 struct mlx5_ib_flow_prio *ft_prio, 3746 const struct ib_flow_attr *flow_attr, 3747 struct mlx5_flow_destination *dst) 3748 { 3749 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0, NULL); 3750 } 3751 3752 enum { 3753 LEFTOVERS_MC, 3754 LEFTOVERS_UC, 3755 }; 3756 3757 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev, 3758 struct mlx5_ib_flow_prio *ft_prio, 3759 struct ib_flow_attr *flow_attr, 3760 struct mlx5_flow_destination *dst) 3761 { 3762 struct mlx5_ib_flow_handler *handler_ucast = NULL; 3763 struct mlx5_ib_flow_handler *handler = NULL; 3764 3765 static struct { 3766 struct ib_flow_attr flow_attr; 3767 struct ib_flow_spec_eth eth_flow; 3768 } leftovers_specs[] = { 3769 [LEFTOVERS_MC] = { 3770 .flow_attr = { 3771 .num_of_specs = 1, 3772 .size = sizeof(leftovers_specs[0]) 3773 }, 3774 .eth_flow = { 3775 .type = IB_FLOW_SPEC_ETH, 3776 .size = sizeof(struct ib_flow_spec_eth), 3777 .mask = {.dst_mac = {0x1} }, 3778 .val = {.dst_mac = {0x1} } 3779 } 3780 }, 3781 [LEFTOVERS_UC] = { 3782 .flow_attr = { 3783 .num_of_specs = 1, 3784 .size = sizeof(leftovers_specs[0]) 3785 }, 3786 .eth_flow = { 3787 .type = IB_FLOW_SPEC_ETH, 3788 .size = sizeof(struct ib_flow_spec_eth), 3789 .mask = {.dst_mac = {0x1} }, 3790 .val = {.dst_mac = {} } 3791 } 3792 } 3793 }; 3794 3795 handler = create_flow_rule(dev, ft_prio, 3796 &leftovers_specs[LEFTOVERS_MC].flow_attr, 3797 dst); 3798 if (!IS_ERR(handler) && 3799 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) { 3800 handler_ucast = create_flow_rule(dev, ft_prio, 3801 &leftovers_specs[LEFTOVERS_UC].flow_attr, 3802 dst); 3803 if (IS_ERR(handler_ucast)) { 3804 mlx5_del_flow_rules(handler->rule); 3805 ft_prio->refcount--; 3806 kfree(handler); 3807 handler = handler_ucast; 3808 } else { 3809 list_add(&handler_ucast->list, &handler->list); 3810 } 3811 } 3812 3813 return handler; 3814 } 3815 3816 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev, 3817 struct mlx5_ib_flow_prio *ft_rx, 3818 struct mlx5_ib_flow_prio *ft_tx, 3819 struct mlx5_flow_destination *dst) 3820 { 3821 struct mlx5_ib_flow_handler *handler_rx; 3822 struct mlx5_ib_flow_handler *handler_tx; 3823 int err; 3824 static const struct ib_flow_attr flow_attr = { 3825 .num_of_specs = 0, 3826 .size = sizeof(flow_attr) 3827 }; 3828 3829 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst); 3830 if (IS_ERR(handler_rx)) { 3831 err = PTR_ERR(handler_rx); 3832 goto err; 3833 } 3834 3835 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst); 3836 if (IS_ERR(handler_tx)) { 3837 err = PTR_ERR(handler_tx); 3838 goto err_tx; 3839 } 3840 3841 list_add(&handler_tx->list, &handler_rx->list); 3842 3843 return handler_rx; 3844 3845 err_tx: 3846 mlx5_del_flow_rules(handler_rx->rule); 3847 ft_rx->refcount--; 3848 kfree(handler_rx); 3849 err: 3850 return ERR_PTR(err); 3851 } 3852 3853 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp, 3854 struct ib_flow_attr *flow_attr, 3855 int domain, 3856 struct ib_udata *udata) 3857 { 3858 struct mlx5_ib_dev *dev = to_mdev(qp->device); 3859 struct mlx5_ib_qp *mqp = to_mqp(qp); 3860 struct mlx5_ib_flow_handler *handler = NULL; 3861 struct mlx5_flow_destination *dst = NULL; 3862 struct mlx5_ib_flow_prio *ft_prio_tx = NULL; 3863 struct mlx5_ib_flow_prio *ft_prio; 3864 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS; 3865 struct mlx5_ib_create_flow *ucmd = NULL, ucmd_hdr; 3866 size_t min_ucmd_sz, required_ucmd_sz; 3867 int err; 3868 int underlay_qpn; 3869 3870 if (udata && udata->inlen) { 3871 min_ucmd_sz = offsetof(typeof(ucmd_hdr), reserved) + 3872 sizeof(ucmd_hdr.reserved); 3873 if (udata->inlen < min_ucmd_sz) 3874 return ERR_PTR(-EOPNOTSUPP); 3875 3876 err = ib_copy_from_udata(&ucmd_hdr, udata, min_ucmd_sz); 3877 if (err) 3878 return ERR_PTR(err); 3879 3880 /* currently supports only one counters data */ 3881 if (ucmd_hdr.ncounters_data > 1) 3882 return ERR_PTR(-EINVAL); 3883 3884 required_ucmd_sz = min_ucmd_sz + 3885 sizeof(struct mlx5_ib_flow_counters_data) * 3886 ucmd_hdr.ncounters_data; 3887 if (udata->inlen > required_ucmd_sz && 3888 !ib_is_udata_cleared(udata, required_ucmd_sz, 3889 udata->inlen - required_ucmd_sz)) 3890 return ERR_PTR(-EOPNOTSUPP); 3891 3892 ucmd = kzalloc(required_ucmd_sz, GFP_KERNEL); 3893 if (!ucmd) 3894 return ERR_PTR(-ENOMEM); 3895 3896 err = ib_copy_from_udata(ucmd, udata, required_ucmd_sz); 3897 if (err) 3898 goto free_ucmd; 3899 } 3900 3901 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) { 3902 err = -ENOMEM; 3903 goto free_ucmd; 3904 } 3905 3906 if (domain != IB_FLOW_DOMAIN_USER || 3907 flow_attr->port > dev->num_ports || 3908 (flow_attr->flags & ~(IB_FLOW_ATTR_FLAGS_DONT_TRAP | 3909 IB_FLOW_ATTR_FLAGS_EGRESS))) { 3910 err = -EINVAL; 3911 goto free_ucmd; 3912 } 3913 3914 if (is_egress && 3915 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 3916 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) { 3917 err = -EINVAL; 3918 goto free_ucmd; 3919 } 3920 3921 dst = kzalloc(sizeof(*dst), GFP_KERNEL); 3922 if (!dst) { 3923 err = -ENOMEM; 3924 goto free_ucmd; 3925 } 3926 3927 mutex_lock(&dev->flow_db->lock); 3928 3929 ft_prio = get_flow_table(dev, flow_attr, 3930 is_egress ? MLX5_IB_FT_TX : MLX5_IB_FT_RX); 3931 if (IS_ERR(ft_prio)) { 3932 err = PTR_ERR(ft_prio); 3933 goto unlock; 3934 } 3935 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 3936 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX); 3937 if (IS_ERR(ft_prio_tx)) { 3938 err = PTR_ERR(ft_prio_tx); 3939 ft_prio_tx = NULL; 3940 goto destroy_ft; 3941 } 3942 } 3943 3944 if (is_egress) { 3945 dst->type = MLX5_FLOW_DESTINATION_TYPE_PORT; 3946 } else { 3947 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR; 3948 if (mqp->is_rss) 3949 dst->tir_num = mqp->rss_qp.tirn; 3950 else 3951 dst->tir_num = mqp->raw_packet_qp.rq.tirn; 3952 } 3953 3954 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 3955 underlay_qpn = (mqp->flags & IB_QP_CREATE_SOURCE_QPN) ? 3956 mqp->underlay_qpn : 3957 0; 3958 handler = _create_flow_rule(dev, ft_prio, flow_attr, dst, 3959 underlay_qpn, ucmd); 3960 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 3961 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 3962 handler = create_leftovers_rule(dev, ft_prio, flow_attr, 3963 dst); 3964 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 3965 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst); 3966 } else { 3967 err = -EINVAL; 3968 goto destroy_ft; 3969 } 3970 3971 if (IS_ERR(handler)) { 3972 err = PTR_ERR(handler); 3973 handler = NULL; 3974 goto destroy_ft; 3975 } 3976 3977 mutex_unlock(&dev->flow_db->lock); 3978 kfree(dst); 3979 kfree(ucmd); 3980 3981 return &handler->ibflow; 3982 3983 destroy_ft: 3984 put_flow_table(dev, ft_prio, false); 3985 if (ft_prio_tx) 3986 put_flow_table(dev, ft_prio_tx, false); 3987 unlock: 3988 mutex_unlock(&dev->flow_db->lock); 3989 kfree(dst); 3990 free_ucmd: 3991 kfree(ucmd); 3992 return ERR_PTR(err); 3993 } 3994 3995 static struct mlx5_ib_flow_prio * 3996 _get_flow_table(struct mlx5_ib_dev *dev, 3997 struct mlx5_ib_flow_matcher *fs_matcher, 3998 bool mcast) 3999 { 4000 struct mlx5_flow_namespace *ns = NULL; 4001 struct mlx5_ib_flow_prio *prio = NULL; 4002 int max_table_size = 0; 4003 bool esw_encap; 4004 u32 flags = 0; 4005 int priority; 4006 4007 if (mcast) 4008 priority = MLX5_IB_FLOW_MCAST_PRIO; 4009 else 4010 priority = ib_prio_to_core_prio(fs_matcher->priority, false); 4011 4012 esw_encap = mlx5_eswitch_get_encap_mode(dev->mdev) != 4013 DEVLINK_ESWITCH_ENCAP_MODE_NONE; 4014 if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS) { 4015 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 4016 log_max_ft_size)); 4017 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap) && !esw_encap) 4018 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP; 4019 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 4020 reformat_l3_tunnel_to_l2) && 4021 !esw_encap) 4022 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT; 4023 } else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_EGRESS) { 4024 max_table_size = BIT( 4025 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, log_max_ft_size)); 4026 if (MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat) && !esw_encap) 4027 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT; 4028 } else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_FDB) { 4029 max_table_size = BIT( 4030 MLX5_CAP_ESW_FLOWTABLE_FDB(dev->mdev, log_max_ft_size)); 4031 if (MLX5_CAP_ESW_FLOWTABLE_FDB(dev->mdev, decap) && esw_encap) 4032 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP; 4033 if (MLX5_CAP_ESW_FLOWTABLE_FDB(dev->mdev, reformat_l3_tunnel_to_l2) && 4034 esw_encap) 4035 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT; 4036 priority = FDB_BYPASS_PATH; 4037 } else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_RDMA_RX) { 4038 max_table_size = 4039 BIT(MLX5_CAP_FLOWTABLE_RDMA_RX(dev->mdev, 4040 log_max_ft_size)); 4041 priority = fs_matcher->priority; 4042 } else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_RDMA_TX) { 4043 max_table_size = 4044 BIT(MLX5_CAP_FLOWTABLE_RDMA_TX(dev->mdev, 4045 log_max_ft_size)); 4046 priority = fs_matcher->priority; 4047 } 4048 4049 max_table_size = min_t(int, max_table_size, MLX5_FS_MAX_ENTRIES); 4050 4051 ns = mlx5_get_flow_namespace(dev->mdev, fs_matcher->ns_type); 4052 if (!ns) 4053 return ERR_PTR(-ENOTSUPP); 4054 4055 if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS) 4056 prio = &dev->flow_db->prios[priority]; 4057 else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_EGRESS) 4058 prio = &dev->flow_db->egress_prios[priority]; 4059 else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_FDB) 4060 prio = &dev->flow_db->fdb; 4061 else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_RDMA_RX) 4062 prio = &dev->flow_db->rdma_rx[priority]; 4063 else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_RDMA_TX) 4064 prio = &dev->flow_db->rdma_tx[priority]; 4065 4066 if (!prio) 4067 return ERR_PTR(-EINVAL); 4068 4069 if (prio->flow_table) 4070 return prio; 4071 4072 return _get_prio(ns, prio, priority, max_table_size, 4073 MLX5_FS_MAX_TYPES, flags); 4074 } 4075 4076 static struct mlx5_ib_flow_handler * 4077 _create_raw_flow_rule(struct mlx5_ib_dev *dev, 4078 struct mlx5_ib_flow_prio *ft_prio, 4079 struct mlx5_flow_destination *dst, 4080 struct mlx5_ib_flow_matcher *fs_matcher, 4081 struct mlx5_flow_context *flow_context, 4082 struct mlx5_flow_act *flow_act, 4083 void *cmd_in, int inlen, 4084 int dst_num) 4085 { 4086 struct mlx5_ib_flow_handler *handler; 4087 struct mlx5_flow_spec *spec; 4088 struct mlx5_flow_table *ft = ft_prio->flow_table; 4089 int err = 0; 4090 4091 spec = kvzalloc(sizeof(*spec), GFP_KERNEL); 4092 handler = kzalloc(sizeof(*handler), GFP_KERNEL); 4093 if (!handler || !spec) { 4094 err = -ENOMEM; 4095 goto free; 4096 } 4097 4098 INIT_LIST_HEAD(&handler->list); 4099 4100 memcpy(spec->match_value, cmd_in, inlen); 4101 memcpy(spec->match_criteria, fs_matcher->matcher_mask.match_params, 4102 fs_matcher->mask_len); 4103 spec->match_criteria_enable = fs_matcher->match_criteria_enable; 4104 spec->flow_context = *flow_context; 4105 4106 handler->rule = mlx5_add_flow_rules(ft, spec, 4107 flow_act, dst, dst_num); 4108 4109 if (IS_ERR(handler->rule)) { 4110 err = PTR_ERR(handler->rule); 4111 goto free; 4112 } 4113 4114 ft_prio->refcount++; 4115 handler->prio = ft_prio; 4116 handler->dev = dev; 4117 ft_prio->flow_table = ft; 4118 4119 free: 4120 if (err) 4121 kfree(handler); 4122 kvfree(spec); 4123 return err ? ERR_PTR(err) : handler; 4124 } 4125 4126 static bool raw_fs_is_multicast(struct mlx5_ib_flow_matcher *fs_matcher, 4127 void *match_v) 4128 { 4129 void *match_c; 4130 void *match_v_set_lyr_2_4, *match_c_set_lyr_2_4; 4131 void *dmac, *dmac_mask; 4132 void *ipv4, *ipv4_mask; 4133 4134 if (!(fs_matcher->match_criteria_enable & 4135 (1 << MATCH_CRITERIA_ENABLE_OUTER_BIT))) 4136 return false; 4137 4138 match_c = fs_matcher->matcher_mask.match_params; 4139 match_v_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_v, 4140 outer_headers); 4141 match_c_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_c, 4142 outer_headers); 4143 4144 dmac = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4, 4145 dmac_47_16); 4146 dmac_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4, 4147 dmac_47_16); 4148 4149 if (is_multicast_ether_addr(dmac) && 4150 is_multicast_ether_addr(dmac_mask)) 4151 return true; 4152 4153 ipv4 = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4, 4154 dst_ipv4_dst_ipv6.ipv4_layout.ipv4); 4155 4156 ipv4_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4, 4157 dst_ipv4_dst_ipv6.ipv4_layout.ipv4); 4158 4159 if (ipv4_is_multicast(*(__be32 *)(ipv4)) && 4160 ipv4_is_multicast(*(__be32 *)(ipv4_mask))) 4161 return true; 4162 4163 return false; 4164 } 4165 4166 struct mlx5_ib_flow_handler * 4167 mlx5_ib_raw_fs_rule_add(struct mlx5_ib_dev *dev, 4168 struct mlx5_ib_flow_matcher *fs_matcher, 4169 struct mlx5_flow_context *flow_context, 4170 struct mlx5_flow_act *flow_act, 4171 u32 counter_id, 4172 void *cmd_in, int inlen, int dest_id, 4173 int dest_type) 4174 { 4175 struct mlx5_flow_destination *dst; 4176 struct mlx5_ib_flow_prio *ft_prio; 4177 struct mlx5_ib_flow_handler *handler; 4178 int dst_num = 0; 4179 bool mcast; 4180 int err; 4181 4182 if (fs_matcher->flow_type != MLX5_IB_FLOW_TYPE_NORMAL) 4183 return ERR_PTR(-EOPNOTSUPP); 4184 4185 if (fs_matcher->priority > MLX5_IB_FLOW_LAST_PRIO) 4186 return ERR_PTR(-ENOMEM); 4187 4188 dst = kcalloc(2, sizeof(*dst), GFP_KERNEL); 4189 if (!dst) 4190 return ERR_PTR(-ENOMEM); 4191 4192 mcast = raw_fs_is_multicast(fs_matcher, cmd_in); 4193 mutex_lock(&dev->flow_db->lock); 4194 4195 ft_prio = _get_flow_table(dev, fs_matcher, mcast); 4196 if (IS_ERR(ft_prio)) { 4197 err = PTR_ERR(ft_prio); 4198 goto unlock; 4199 } 4200 4201 if (dest_type == MLX5_FLOW_DESTINATION_TYPE_TIR) { 4202 dst[dst_num].type = dest_type; 4203 dst[dst_num++].tir_num = dest_id; 4204 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; 4205 } else if (dest_type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE) { 4206 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM; 4207 dst[dst_num++].ft_num = dest_id; 4208 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; 4209 } else if (dest_type == MLX5_FLOW_DESTINATION_TYPE_PORT) { 4210 dst[dst_num++].type = MLX5_FLOW_DESTINATION_TYPE_PORT; 4211 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW; 4212 } 4213 4214 4215 if (flow_act->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) { 4216 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER; 4217 dst[dst_num].counter_id = counter_id; 4218 dst_num++; 4219 } 4220 4221 handler = _create_raw_flow_rule(dev, ft_prio, dst, fs_matcher, 4222 flow_context, flow_act, 4223 cmd_in, inlen, dst_num); 4224 4225 if (IS_ERR(handler)) { 4226 err = PTR_ERR(handler); 4227 goto destroy_ft; 4228 } 4229 4230 mutex_unlock(&dev->flow_db->lock); 4231 atomic_inc(&fs_matcher->usecnt); 4232 handler->flow_matcher = fs_matcher; 4233 4234 kfree(dst); 4235 4236 return handler; 4237 4238 destroy_ft: 4239 put_flow_table(dev, ft_prio, false); 4240 unlock: 4241 mutex_unlock(&dev->flow_db->lock); 4242 kfree(dst); 4243 4244 return ERR_PTR(err); 4245 } 4246 4247 static u32 mlx5_ib_flow_action_flags_to_accel_xfrm_flags(u32 mlx5_flags) 4248 { 4249 u32 flags = 0; 4250 4251 if (mlx5_flags & MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA) 4252 flags |= MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA; 4253 4254 return flags; 4255 } 4256 4257 #define MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA 4258 static struct ib_flow_action * 4259 mlx5_ib_create_flow_action_esp(struct ib_device *device, 4260 const struct ib_flow_action_attrs_esp *attr, 4261 struct uverbs_attr_bundle *attrs) 4262 { 4263 struct mlx5_ib_dev *mdev = to_mdev(device); 4264 struct ib_uverbs_flow_action_esp_keymat_aes_gcm *aes_gcm; 4265 struct mlx5_accel_esp_xfrm_attrs accel_attrs = {}; 4266 struct mlx5_ib_flow_action *action; 4267 u64 action_flags; 4268 u64 flags; 4269 int err = 0; 4270 4271 err = uverbs_get_flags64( 4272 &action_flags, attrs, MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS, 4273 ((MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED << 1) - 1)); 4274 if (err) 4275 return ERR_PTR(err); 4276 4277 flags = mlx5_ib_flow_action_flags_to_accel_xfrm_flags(action_flags); 4278 4279 /* We current only support a subset of the standard features. Only a 4280 * keymat of type AES_GCM, with icv_len == 16, iv_algo == SEQ and esn 4281 * (with overlap). Full offload mode isn't supported. 4282 */ 4283 if (!attr->keymat || attr->replay || attr->encap || 4284 attr->spi || attr->seq || attr->tfc_pad || 4285 attr->hard_limit_pkts || 4286 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED | 4287 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT))) 4288 return ERR_PTR(-EOPNOTSUPP); 4289 4290 if (attr->keymat->protocol != 4291 IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM) 4292 return ERR_PTR(-EOPNOTSUPP); 4293 4294 aes_gcm = &attr->keymat->keymat.aes_gcm; 4295 4296 if (aes_gcm->icv_len != 16 || 4297 aes_gcm->iv_algo != IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ) 4298 return ERR_PTR(-EOPNOTSUPP); 4299 4300 action = kmalloc(sizeof(*action), GFP_KERNEL); 4301 if (!action) 4302 return ERR_PTR(-ENOMEM); 4303 4304 action->esp_aes_gcm.ib_flags = attr->flags; 4305 memcpy(&accel_attrs.keymat.aes_gcm.aes_key, &aes_gcm->aes_key, 4306 sizeof(accel_attrs.keymat.aes_gcm.aes_key)); 4307 accel_attrs.keymat.aes_gcm.key_len = aes_gcm->key_len * 8; 4308 memcpy(&accel_attrs.keymat.aes_gcm.salt, &aes_gcm->salt, 4309 sizeof(accel_attrs.keymat.aes_gcm.salt)); 4310 memcpy(&accel_attrs.keymat.aes_gcm.seq_iv, &aes_gcm->iv, 4311 sizeof(accel_attrs.keymat.aes_gcm.seq_iv)); 4312 accel_attrs.keymat.aes_gcm.icv_len = aes_gcm->icv_len * 8; 4313 accel_attrs.keymat.aes_gcm.iv_algo = MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ; 4314 accel_attrs.keymat_type = MLX5_ACCEL_ESP_KEYMAT_AES_GCM; 4315 4316 accel_attrs.esn = attr->esn; 4317 if (attr->flags & IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) 4318 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED; 4319 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW) 4320 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP; 4321 4322 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT) 4323 accel_attrs.action |= MLX5_ACCEL_ESP_ACTION_ENCRYPT; 4324 4325 action->esp_aes_gcm.ctx = 4326 mlx5_accel_esp_create_xfrm(mdev->mdev, &accel_attrs, flags); 4327 if (IS_ERR(action->esp_aes_gcm.ctx)) { 4328 err = PTR_ERR(action->esp_aes_gcm.ctx); 4329 goto err_parse; 4330 } 4331 4332 action->esp_aes_gcm.ib_flags = attr->flags; 4333 4334 return &action->ib_action; 4335 4336 err_parse: 4337 kfree(action); 4338 return ERR_PTR(err); 4339 } 4340 4341 static int 4342 mlx5_ib_modify_flow_action_esp(struct ib_flow_action *action, 4343 const struct ib_flow_action_attrs_esp *attr, 4344 struct uverbs_attr_bundle *attrs) 4345 { 4346 struct mlx5_ib_flow_action *maction = to_mflow_act(action); 4347 struct mlx5_accel_esp_xfrm_attrs accel_attrs; 4348 int err = 0; 4349 4350 if (attr->keymat || attr->replay || attr->encap || 4351 attr->spi || attr->seq || attr->tfc_pad || 4352 attr->hard_limit_pkts || 4353 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED | 4354 IB_FLOW_ACTION_ESP_FLAGS_MOD_ESP_ATTRS | 4355 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW))) 4356 return -EOPNOTSUPP; 4357 4358 /* Only the ESN value or the MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP can 4359 * be modified. 4360 */ 4361 if (!(maction->esp_aes_gcm.ib_flags & 4362 IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) && 4363 attr->flags & (IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED | 4364 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)) 4365 return -EINVAL; 4366 4367 memcpy(&accel_attrs, &maction->esp_aes_gcm.ctx->attrs, 4368 sizeof(accel_attrs)); 4369 4370 accel_attrs.esn = attr->esn; 4371 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW) 4372 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP; 4373 else 4374 accel_attrs.flags &= ~MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP; 4375 4376 err = mlx5_accel_esp_modify_xfrm(maction->esp_aes_gcm.ctx, 4377 &accel_attrs); 4378 if (err) 4379 return err; 4380 4381 maction->esp_aes_gcm.ib_flags &= 4382 ~IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW; 4383 maction->esp_aes_gcm.ib_flags |= 4384 attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW; 4385 4386 return 0; 4387 } 4388 4389 static int mlx5_ib_destroy_flow_action(struct ib_flow_action *action) 4390 { 4391 struct mlx5_ib_flow_action *maction = to_mflow_act(action); 4392 4393 switch (action->type) { 4394 case IB_FLOW_ACTION_ESP: 4395 /* 4396 * We only support aes_gcm by now, so we implicitly know this is 4397 * the underline crypto. 4398 */ 4399 mlx5_accel_esp_destroy_xfrm(maction->esp_aes_gcm.ctx); 4400 break; 4401 case IB_FLOW_ACTION_UNSPECIFIED: 4402 mlx5_ib_destroy_flow_action_raw(maction); 4403 break; 4404 default: 4405 WARN_ON(true); 4406 break; 4407 } 4408 4409 kfree(maction); 4410 return 0; 4411 } 4412 4413 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 4414 { 4415 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4416 struct mlx5_ib_qp *mqp = to_mqp(ibqp); 4417 int err; 4418 u16 uid; 4419 4420 uid = ibqp->pd ? 4421 to_mpd(ibqp->pd)->uid : 0; 4422 4423 if (mqp->flags & IB_QP_CREATE_SOURCE_QPN) { 4424 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n"); 4425 return -EOPNOTSUPP; 4426 } 4427 4428 err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 4429 if (err) 4430 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 4431 ibqp->qp_num, gid->raw); 4432 4433 return err; 4434 } 4435 4436 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 4437 { 4438 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4439 int err; 4440 u16 uid; 4441 4442 uid = ibqp->pd ? 4443 to_mpd(ibqp->pd)->uid : 0; 4444 err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 4445 if (err) 4446 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 4447 ibqp->qp_num, gid->raw); 4448 4449 return err; 4450 } 4451 4452 static int init_node_data(struct mlx5_ib_dev *dev) 4453 { 4454 int err; 4455 4456 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 4457 if (err) 4458 return err; 4459 4460 dev->mdev->rev_id = dev->mdev->pdev->revision; 4461 4462 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 4463 } 4464 4465 static ssize_t fw_pages_show(struct device *device, 4466 struct device_attribute *attr, char *buf) 4467 { 4468 struct mlx5_ib_dev *dev = 4469 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 4470 4471 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages); 4472 } 4473 static DEVICE_ATTR_RO(fw_pages); 4474 4475 static ssize_t reg_pages_show(struct device *device, 4476 struct device_attribute *attr, char *buf) 4477 { 4478 struct mlx5_ib_dev *dev = 4479 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 4480 4481 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 4482 } 4483 static DEVICE_ATTR_RO(reg_pages); 4484 4485 static ssize_t hca_type_show(struct device *device, 4486 struct device_attribute *attr, char *buf) 4487 { 4488 struct mlx5_ib_dev *dev = 4489 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 4490 4491 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device); 4492 } 4493 static DEVICE_ATTR_RO(hca_type); 4494 4495 static ssize_t hw_rev_show(struct device *device, 4496 struct device_attribute *attr, char *buf) 4497 { 4498 struct mlx5_ib_dev *dev = 4499 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 4500 4501 return sprintf(buf, "%x\n", dev->mdev->rev_id); 4502 } 4503 static DEVICE_ATTR_RO(hw_rev); 4504 4505 static ssize_t board_id_show(struct device *device, 4506 struct device_attribute *attr, char *buf) 4507 { 4508 struct mlx5_ib_dev *dev = 4509 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 4510 4511 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 4512 dev->mdev->board_id); 4513 } 4514 static DEVICE_ATTR_RO(board_id); 4515 4516 static struct attribute *mlx5_class_attributes[] = { 4517 &dev_attr_hw_rev.attr, 4518 &dev_attr_hca_type.attr, 4519 &dev_attr_board_id.attr, 4520 &dev_attr_fw_pages.attr, 4521 &dev_attr_reg_pages.attr, 4522 NULL, 4523 }; 4524 4525 static const struct attribute_group mlx5_attr_group = { 4526 .attrs = mlx5_class_attributes, 4527 }; 4528 4529 static void pkey_change_handler(struct work_struct *work) 4530 { 4531 struct mlx5_ib_port_resources *ports = 4532 container_of(work, struct mlx5_ib_port_resources, 4533 pkey_change_work); 4534 4535 mutex_lock(&ports->devr->mutex); 4536 mlx5_ib_gsi_pkey_change(ports->gsi); 4537 mutex_unlock(&ports->devr->mutex); 4538 } 4539 4540 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 4541 { 4542 struct mlx5_ib_qp *mqp; 4543 struct mlx5_ib_cq *send_mcq, *recv_mcq; 4544 struct mlx5_core_cq *mcq; 4545 struct list_head cq_armed_list; 4546 unsigned long flags_qp; 4547 unsigned long flags_cq; 4548 unsigned long flags; 4549 4550 INIT_LIST_HEAD(&cq_armed_list); 4551 4552 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 4553 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 4554 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 4555 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 4556 if (mqp->sq.tail != mqp->sq.head) { 4557 send_mcq = to_mcq(mqp->ibqp.send_cq); 4558 spin_lock_irqsave(&send_mcq->lock, flags_cq); 4559 if (send_mcq->mcq.comp && 4560 mqp->ibqp.send_cq->comp_handler) { 4561 if (!send_mcq->mcq.reset_notify_added) { 4562 send_mcq->mcq.reset_notify_added = 1; 4563 list_add_tail(&send_mcq->mcq.reset_notify, 4564 &cq_armed_list); 4565 } 4566 } 4567 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 4568 } 4569 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 4570 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 4571 /* no handling is needed for SRQ */ 4572 if (!mqp->ibqp.srq) { 4573 if (mqp->rq.tail != mqp->rq.head) { 4574 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 4575 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 4576 if (recv_mcq->mcq.comp && 4577 mqp->ibqp.recv_cq->comp_handler) { 4578 if (!recv_mcq->mcq.reset_notify_added) { 4579 recv_mcq->mcq.reset_notify_added = 1; 4580 list_add_tail(&recv_mcq->mcq.reset_notify, 4581 &cq_armed_list); 4582 } 4583 } 4584 spin_unlock_irqrestore(&recv_mcq->lock, 4585 flags_cq); 4586 } 4587 } 4588 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 4589 } 4590 /*At that point all inflight post send were put to be executed as of we 4591 * lock/unlock above locks Now need to arm all involved CQs. 4592 */ 4593 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 4594 mcq->comp(mcq, NULL); 4595 } 4596 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 4597 } 4598 4599 static void delay_drop_handler(struct work_struct *work) 4600 { 4601 int err; 4602 struct mlx5_ib_delay_drop *delay_drop = 4603 container_of(work, struct mlx5_ib_delay_drop, 4604 delay_drop_work); 4605 4606 atomic_inc(&delay_drop->events_cnt); 4607 4608 mutex_lock(&delay_drop->lock); 4609 err = mlx5_core_set_delay_drop(delay_drop->dev, delay_drop->timeout); 4610 if (err) { 4611 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n", 4612 delay_drop->timeout); 4613 delay_drop->activate = false; 4614 } 4615 mutex_unlock(&delay_drop->lock); 4616 } 4617 4618 static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 4619 struct ib_event *ibev) 4620 { 4621 u8 port = (eqe->data.port.port >> 4) & 0xf; 4622 4623 switch (eqe->sub_type) { 4624 case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT: 4625 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 4626 IB_LINK_LAYER_ETHERNET) 4627 schedule_work(&ibdev->delay_drop.delay_drop_work); 4628 break; 4629 default: /* do nothing */ 4630 return; 4631 } 4632 } 4633 4634 static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 4635 struct ib_event *ibev) 4636 { 4637 u8 port = (eqe->data.port.port >> 4) & 0xf; 4638 4639 ibev->element.port_num = port; 4640 4641 switch (eqe->sub_type) { 4642 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 4643 case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 4644 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED: 4645 /* In RoCE, port up/down events are handled in 4646 * mlx5_netdev_event(). 4647 */ 4648 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 4649 IB_LINK_LAYER_ETHERNET) 4650 return -EINVAL; 4651 4652 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ? 4653 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 4654 break; 4655 4656 case MLX5_PORT_CHANGE_SUBTYPE_LID: 4657 ibev->event = IB_EVENT_LID_CHANGE; 4658 break; 4659 4660 case MLX5_PORT_CHANGE_SUBTYPE_PKEY: 4661 ibev->event = IB_EVENT_PKEY_CHANGE; 4662 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 4663 break; 4664 4665 case MLX5_PORT_CHANGE_SUBTYPE_GUID: 4666 ibev->event = IB_EVENT_GID_CHANGE; 4667 break; 4668 4669 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG: 4670 ibev->event = IB_EVENT_CLIENT_REREGISTER; 4671 break; 4672 default: 4673 return -EINVAL; 4674 } 4675 4676 return 0; 4677 } 4678 4679 static void mlx5_ib_handle_event(struct work_struct *_work) 4680 { 4681 struct mlx5_ib_event_work *work = 4682 container_of(_work, struct mlx5_ib_event_work, work); 4683 struct mlx5_ib_dev *ibdev; 4684 struct ib_event ibev; 4685 bool fatal = false; 4686 4687 if (work->is_slave) { 4688 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi); 4689 if (!ibdev) 4690 goto out; 4691 } else { 4692 ibdev = work->dev; 4693 } 4694 4695 switch (work->event) { 4696 case MLX5_DEV_EVENT_SYS_ERROR: 4697 ibev.event = IB_EVENT_DEVICE_FATAL; 4698 mlx5_ib_handle_internal_error(ibdev); 4699 ibev.element.port_num = (u8)(unsigned long)work->param; 4700 fatal = true; 4701 break; 4702 case MLX5_EVENT_TYPE_PORT_CHANGE: 4703 if (handle_port_change(ibdev, work->param, &ibev)) 4704 goto out; 4705 break; 4706 case MLX5_EVENT_TYPE_GENERAL_EVENT: 4707 handle_general_event(ibdev, work->param, &ibev); 4708 /* fall through */ 4709 default: 4710 goto out; 4711 } 4712 4713 ibev.device = &ibdev->ib_dev; 4714 4715 if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) { 4716 mlx5_ib_warn(ibdev, "warning: event on port %d\n", ibev.element.port_num); 4717 goto out; 4718 } 4719 4720 if (ibdev->ib_active) 4721 ib_dispatch_event(&ibev); 4722 4723 if (fatal) 4724 ibdev->ib_active = false; 4725 out: 4726 kfree(work); 4727 } 4728 4729 static int mlx5_ib_event(struct notifier_block *nb, 4730 unsigned long event, void *param) 4731 { 4732 struct mlx5_ib_event_work *work; 4733 4734 work = kmalloc(sizeof(*work), GFP_ATOMIC); 4735 if (!work) 4736 return NOTIFY_DONE; 4737 4738 INIT_WORK(&work->work, mlx5_ib_handle_event); 4739 work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events); 4740 work->is_slave = false; 4741 work->param = param; 4742 work->event = event; 4743 4744 queue_work(mlx5_ib_event_wq, &work->work); 4745 4746 return NOTIFY_OK; 4747 } 4748 4749 static int mlx5_ib_event_slave_port(struct notifier_block *nb, 4750 unsigned long event, void *param) 4751 { 4752 struct mlx5_ib_event_work *work; 4753 4754 work = kmalloc(sizeof(*work), GFP_ATOMIC); 4755 if (!work) 4756 return NOTIFY_DONE; 4757 4758 INIT_WORK(&work->work, mlx5_ib_handle_event); 4759 work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events); 4760 work->is_slave = true; 4761 work->param = param; 4762 work->event = event; 4763 queue_work(mlx5_ib_event_wq, &work->work); 4764 4765 return NOTIFY_OK; 4766 } 4767 4768 static int set_has_smi_cap(struct mlx5_ib_dev *dev) 4769 { 4770 struct mlx5_hca_vport_context vport_ctx; 4771 int err; 4772 int port; 4773 4774 for (port = 1; port <= ARRAY_SIZE(dev->mdev->port_caps); port++) { 4775 dev->mdev->port_caps[port - 1].has_smi = false; 4776 if (MLX5_CAP_GEN(dev->mdev, port_type) == 4777 MLX5_CAP_PORT_TYPE_IB) { 4778 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) { 4779 err = mlx5_query_hca_vport_context(dev->mdev, 0, 4780 port, 0, 4781 &vport_ctx); 4782 if (err) { 4783 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n", 4784 port, err); 4785 return err; 4786 } 4787 dev->mdev->port_caps[port - 1].has_smi = 4788 vport_ctx.has_smi; 4789 } else { 4790 dev->mdev->port_caps[port - 1].has_smi = true; 4791 } 4792 } 4793 } 4794 return 0; 4795 } 4796 4797 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 4798 { 4799 int port; 4800 4801 for (port = 1; port <= dev->num_ports; port++) 4802 mlx5_query_ext_port_caps(dev, port); 4803 } 4804 4805 static int __get_port_caps(struct mlx5_ib_dev *dev, u8 port) 4806 { 4807 struct ib_device_attr *dprops = NULL; 4808 struct ib_port_attr *pprops = NULL; 4809 int err = -ENOMEM; 4810 4811 pprops = kzalloc(sizeof(*pprops), GFP_KERNEL); 4812 if (!pprops) 4813 goto out; 4814 4815 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL); 4816 if (!dprops) 4817 goto out; 4818 4819 err = mlx5_ib_query_device(&dev->ib_dev, dprops, NULL); 4820 if (err) { 4821 mlx5_ib_warn(dev, "query_device failed %d\n", err); 4822 goto out; 4823 } 4824 4825 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops); 4826 if (err) { 4827 mlx5_ib_warn(dev, "query_port %d failed %d\n", 4828 port, err); 4829 goto out; 4830 } 4831 4832 dev->mdev->port_caps[port - 1].pkey_table_len = 4833 dprops->max_pkeys; 4834 dev->mdev->port_caps[port - 1].gid_table_len = 4835 pprops->gid_tbl_len; 4836 mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n", 4837 port, dprops->max_pkeys, pprops->gid_tbl_len); 4838 4839 out: 4840 kfree(pprops); 4841 kfree(dprops); 4842 4843 return err; 4844 } 4845 4846 static int get_port_caps(struct mlx5_ib_dev *dev, u8 port) 4847 { 4848 /* For representors use port 1, is this is the only native 4849 * port 4850 */ 4851 if (dev->is_rep) 4852 return __get_port_caps(dev, 1); 4853 return __get_port_caps(dev, port); 4854 } 4855 4856 static void destroy_umrc_res(struct mlx5_ib_dev *dev) 4857 { 4858 int err; 4859 4860 err = mlx5_mr_cache_cleanup(dev); 4861 if (err) 4862 mlx5_ib_warn(dev, "mr cache cleanup failed\n"); 4863 4864 if (dev->umrc.qp) 4865 mlx5_ib_destroy_qp(dev->umrc.qp, NULL); 4866 if (dev->umrc.cq) 4867 ib_free_cq(dev->umrc.cq); 4868 if (dev->umrc.pd) 4869 ib_dealloc_pd(dev->umrc.pd); 4870 } 4871 4872 enum { 4873 MAX_UMR_WR = 128, 4874 }; 4875 4876 static int create_umr_res(struct mlx5_ib_dev *dev) 4877 { 4878 struct ib_qp_init_attr *init_attr = NULL; 4879 struct ib_qp_attr *attr = NULL; 4880 struct ib_pd *pd; 4881 struct ib_cq *cq; 4882 struct ib_qp *qp; 4883 int ret; 4884 4885 attr = kzalloc(sizeof(*attr), GFP_KERNEL); 4886 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL); 4887 if (!attr || !init_attr) { 4888 ret = -ENOMEM; 4889 goto error_0; 4890 } 4891 4892 pd = ib_alloc_pd(&dev->ib_dev, 0); 4893 if (IS_ERR(pd)) { 4894 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n"); 4895 ret = PTR_ERR(pd); 4896 goto error_0; 4897 } 4898 4899 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ); 4900 if (IS_ERR(cq)) { 4901 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n"); 4902 ret = PTR_ERR(cq); 4903 goto error_2; 4904 } 4905 4906 init_attr->send_cq = cq; 4907 init_attr->recv_cq = cq; 4908 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR; 4909 init_attr->cap.max_send_wr = MAX_UMR_WR; 4910 init_attr->cap.max_send_sge = 1; 4911 init_attr->qp_type = MLX5_IB_QPT_REG_UMR; 4912 init_attr->port_num = 1; 4913 qp = mlx5_ib_create_qp(pd, init_attr, NULL); 4914 if (IS_ERR(qp)) { 4915 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n"); 4916 ret = PTR_ERR(qp); 4917 goto error_3; 4918 } 4919 qp->device = &dev->ib_dev; 4920 qp->real_qp = qp; 4921 qp->uobject = NULL; 4922 qp->qp_type = MLX5_IB_QPT_REG_UMR; 4923 qp->send_cq = init_attr->send_cq; 4924 qp->recv_cq = init_attr->recv_cq; 4925 4926 attr->qp_state = IB_QPS_INIT; 4927 attr->port_num = 1; 4928 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX | 4929 IB_QP_PORT, NULL); 4930 if (ret) { 4931 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n"); 4932 goto error_4; 4933 } 4934 4935 memset(attr, 0, sizeof(*attr)); 4936 attr->qp_state = IB_QPS_RTR; 4937 attr->path_mtu = IB_MTU_256; 4938 4939 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 4940 if (ret) { 4941 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n"); 4942 goto error_4; 4943 } 4944 4945 memset(attr, 0, sizeof(*attr)); 4946 attr->qp_state = IB_QPS_RTS; 4947 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 4948 if (ret) { 4949 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n"); 4950 goto error_4; 4951 } 4952 4953 dev->umrc.qp = qp; 4954 dev->umrc.cq = cq; 4955 dev->umrc.pd = pd; 4956 4957 sema_init(&dev->umrc.sem, MAX_UMR_WR); 4958 ret = mlx5_mr_cache_init(dev); 4959 if (ret) { 4960 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 4961 goto error_4; 4962 } 4963 4964 kfree(attr); 4965 kfree(init_attr); 4966 4967 return 0; 4968 4969 error_4: 4970 mlx5_ib_destroy_qp(qp, NULL); 4971 dev->umrc.qp = NULL; 4972 4973 error_3: 4974 ib_free_cq(cq); 4975 dev->umrc.cq = NULL; 4976 4977 error_2: 4978 ib_dealloc_pd(pd); 4979 dev->umrc.pd = NULL; 4980 4981 error_0: 4982 kfree(attr); 4983 kfree(init_attr); 4984 return ret; 4985 } 4986 4987 static u8 mlx5_get_umr_fence(u8 umr_fence_cap) 4988 { 4989 switch (umr_fence_cap) { 4990 case MLX5_CAP_UMR_FENCE_NONE: 4991 return MLX5_FENCE_MODE_NONE; 4992 case MLX5_CAP_UMR_FENCE_SMALL: 4993 return MLX5_FENCE_MODE_INITIATOR_SMALL; 4994 default: 4995 return MLX5_FENCE_MODE_STRONG_ORDERING; 4996 } 4997 } 4998 4999 static int create_dev_resources(struct mlx5_ib_resources *devr) 5000 { 5001 struct ib_srq_init_attr attr; 5002 struct mlx5_ib_dev *dev; 5003 struct ib_device *ibdev; 5004 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 5005 int port; 5006 int ret = 0; 5007 5008 dev = container_of(devr, struct mlx5_ib_dev, devr); 5009 ibdev = &dev->ib_dev; 5010 5011 mutex_init(&devr->mutex); 5012 5013 devr->p0 = rdma_zalloc_drv_obj(ibdev, ib_pd); 5014 if (!devr->p0) 5015 return -ENOMEM; 5016 5017 devr->p0->device = ibdev; 5018 devr->p0->uobject = NULL; 5019 atomic_set(&devr->p0->usecnt, 0); 5020 5021 ret = mlx5_ib_alloc_pd(devr->p0, NULL); 5022 if (ret) 5023 goto error0; 5024 5025 devr->c0 = rdma_zalloc_drv_obj(ibdev, ib_cq); 5026 if (!devr->c0) { 5027 ret = -ENOMEM; 5028 goto error1; 5029 } 5030 5031 devr->c0->device = &dev->ib_dev; 5032 atomic_set(&devr->c0->usecnt, 0); 5033 5034 ret = mlx5_ib_create_cq(devr->c0, &cq_attr, NULL); 5035 if (ret) 5036 goto err_create_cq; 5037 5038 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL); 5039 if (IS_ERR(devr->x0)) { 5040 ret = PTR_ERR(devr->x0); 5041 goto error2; 5042 } 5043 devr->x0->device = &dev->ib_dev; 5044 devr->x0->inode = NULL; 5045 atomic_set(&devr->x0->usecnt, 0); 5046 mutex_init(&devr->x0->tgt_qp_mutex); 5047 INIT_LIST_HEAD(&devr->x0->tgt_qp_list); 5048 5049 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL); 5050 if (IS_ERR(devr->x1)) { 5051 ret = PTR_ERR(devr->x1); 5052 goto error3; 5053 } 5054 devr->x1->device = &dev->ib_dev; 5055 devr->x1->inode = NULL; 5056 atomic_set(&devr->x1->usecnt, 0); 5057 mutex_init(&devr->x1->tgt_qp_mutex); 5058 INIT_LIST_HEAD(&devr->x1->tgt_qp_list); 5059 5060 memset(&attr, 0, sizeof(attr)); 5061 attr.attr.max_sge = 1; 5062 attr.attr.max_wr = 1; 5063 attr.srq_type = IB_SRQT_XRC; 5064 attr.ext.cq = devr->c0; 5065 attr.ext.xrc.xrcd = devr->x0; 5066 5067 devr->s0 = rdma_zalloc_drv_obj(ibdev, ib_srq); 5068 if (!devr->s0) { 5069 ret = -ENOMEM; 5070 goto error4; 5071 } 5072 5073 devr->s0->device = &dev->ib_dev; 5074 devr->s0->pd = devr->p0; 5075 devr->s0->srq_type = IB_SRQT_XRC; 5076 devr->s0->ext.xrc.xrcd = devr->x0; 5077 devr->s0->ext.cq = devr->c0; 5078 ret = mlx5_ib_create_srq(devr->s0, &attr, NULL); 5079 if (ret) 5080 goto err_create; 5081 5082 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt); 5083 atomic_inc(&devr->s0->ext.cq->usecnt); 5084 atomic_inc(&devr->p0->usecnt); 5085 atomic_set(&devr->s0->usecnt, 0); 5086 5087 memset(&attr, 0, sizeof(attr)); 5088 attr.attr.max_sge = 1; 5089 attr.attr.max_wr = 1; 5090 attr.srq_type = IB_SRQT_BASIC; 5091 devr->s1 = rdma_zalloc_drv_obj(ibdev, ib_srq); 5092 if (!devr->s1) { 5093 ret = -ENOMEM; 5094 goto error5; 5095 } 5096 5097 devr->s1->device = &dev->ib_dev; 5098 devr->s1->pd = devr->p0; 5099 devr->s1->srq_type = IB_SRQT_BASIC; 5100 devr->s1->ext.cq = devr->c0; 5101 5102 ret = mlx5_ib_create_srq(devr->s1, &attr, NULL); 5103 if (ret) 5104 goto error6; 5105 5106 atomic_inc(&devr->p0->usecnt); 5107 atomic_set(&devr->s1->usecnt, 0); 5108 5109 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) { 5110 INIT_WORK(&devr->ports[port].pkey_change_work, 5111 pkey_change_handler); 5112 devr->ports[port].devr = devr; 5113 } 5114 5115 return 0; 5116 5117 error6: 5118 kfree(devr->s1); 5119 error5: 5120 mlx5_ib_destroy_srq(devr->s0, NULL); 5121 err_create: 5122 kfree(devr->s0); 5123 error4: 5124 mlx5_ib_dealloc_xrcd(devr->x1, NULL); 5125 error3: 5126 mlx5_ib_dealloc_xrcd(devr->x0, NULL); 5127 error2: 5128 mlx5_ib_destroy_cq(devr->c0, NULL); 5129 err_create_cq: 5130 kfree(devr->c0); 5131 error1: 5132 mlx5_ib_dealloc_pd(devr->p0, NULL); 5133 error0: 5134 kfree(devr->p0); 5135 return ret; 5136 } 5137 5138 static void destroy_dev_resources(struct mlx5_ib_resources *devr) 5139 { 5140 int port; 5141 5142 mlx5_ib_destroy_srq(devr->s1, NULL); 5143 kfree(devr->s1); 5144 mlx5_ib_destroy_srq(devr->s0, NULL); 5145 kfree(devr->s0); 5146 mlx5_ib_dealloc_xrcd(devr->x0, NULL); 5147 mlx5_ib_dealloc_xrcd(devr->x1, NULL); 5148 mlx5_ib_destroy_cq(devr->c0, NULL); 5149 kfree(devr->c0); 5150 mlx5_ib_dealloc_pd(devr->p0, NULL); 5151 kfree(devr->p0); 5152 5153 /* Make sure no change P_Key work items are still executing */ 5154 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) 5155 cancel_work_sync(&devr->ports[port].pkey_change_work); 5156 } 5157 5158 static u32 get_core_cap_flags(struct ib_device *ibdev, 5159 struct mlx5_hca_vport_context *rep) 5160 { 5161 struct mlx5_ib_dev *dev = to_mdev(ibdev); 5162 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 5163 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 5164 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 5165 bool raw_support = !mlx5_core_mp_enabled(dev->mdev); 5166 u32 ret = 0; 5167 5168 if (rep->grh_required) 5169 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED; 5170 5171 if (ll == IB_LINK_LAYER_INFINIBAND) 5172 return ret | RDMA_CORE_PORT_IBA_IB; 5173 5174 if (raw_support) 5175 ret |= RDMA_CORE_PORT_RAW_PACKET; 5176 5177 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 5178 return ret; 5179 5180 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 5181 return ret; 5182 5183 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 5184 ret |= RDMA_CORE_PORT_IBA_ROCE; 5185 5186 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 5187 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 5188 5189 return ret; 5190 } 5191 5192 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num, 5193 struct ib_port_immutable *immutable) 5194 { 5195 struct ib_port_attr attr; 5196 struct mlx5_ib_dev *dev = to_mdev(ibdev); 5197 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num); 5198 struct mlx5_hca_vport_context rep = {0}; 5199 int err; 5200 5201 err = ib_query_port(ibdev, port_num, &attr); 5202 if (err) 5203 return err; 5204 5205 if (ll == IB_LINK_LAYER_INFINIBAND) { 5206 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0, 5207 &rep); 5208 if (err) 5209 return err; 5210 } 5211 5212 immutable->pkey_tbl_len = attr.pkey_tbl_len; 5213 immutable->gid_tbl_len = attr.gid_tbl_len; 5214 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep); 5215 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 5216 5217 return 0; 5218 } 5219 5220 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num, 5221 struct ib_port_immutable *immutable) 5222 { 5223 struct ib_port_attr attr; 5224 int err; 5225 5226 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 5227 5228 err = ib_query_port(ibdev, port_num, &attr); 5229 if (err) 5230 return err; 5231 5232 immutable->pkey_tbl_len = attr.pkey_tbl_len; 5233 immutable->gid_tbl_len = attr.gid_tbl_len; 5234 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 5235 5236 return 0; 5237 } 5238 5239 static void get_dev_fw_str(struct ib_device *ibdev, char *str) 5240 { 5241 struct mlx5_ib_dev *dev = 5242 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 5243 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d", 5244 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev), 5245 fw_rev_sub(dev->mdev)); 5246 } 5247 5248 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev) 5249 { 5250 struct mlx5_core_dev *mdev = dev->mdev; 5251 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev, 5252 MLX5_FLOW_NAMESPACE_LAG); 5253 struct mlx5_flow_table *ft; 5254 int err; 5255 5256 if (!ns || !mlx5_lag_is_roce(mdev)) 5257 return 0; 5258 5259 err = mlx5_cmd_create_vport_lag(mdev); 5260 if (err) 5261 return err; 5262 5263 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0); 5264 if (IS_ERR(ft)) { 5265 err = PTR_ERR(ft); 5266 goto err_destroy_vport_lag; 5267 } 5268 5269 dev->flow_db->lag_demux_ft = ft; 5270 dev->lag_active = true; 5271 return 0; 5272 5273 err_destroy_vport_lag: 5274 mlx5_cmd_destroy_vport_lag(mdev); 5275 return err; 5276 } 5277 5278 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev) 5279 { 5280 struct mlx5_core_dev *mdev = dev->mdev; 5281 5282 if (dev->lag_active) { 5283 dev->lag_active = false; 5284 5285 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft); 5286 dev->flow_db->lag_demux_ft = NULL; 5287 5288 mlx5_cmd_destroy_vport_lag(mdev); 5289 } 5290 } 5291 5292 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num) 5293 { 5294 int err; 5295 5296 dev->port[port_num].roce.nb.notifier_call = mlx5_netdev_event; 5297 err = register_netdevice_notifier(&dev->port[port_num].roce.nb); 5298 if (err) { 5299 dev->port[port_num].roce.nb.notifier_call = NULL; 5300 return err; 5301 } 5302 5303 return 0; 5304 } 5305 5306 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num) 5307 { 5308 if (dev->port[port_num].roce.nb.notifier_call) { 5309 unregister_netdevice_notifier(&dev->port[port_num].roce.nb); 5310 dev->port[port_num].roce.nb.notifier_call = NULL; 5311 } 5312 } 5313 5314 static int mlx5_enable_eth(struct mlx5_ib_dev *dev) 5315 { 5316 int err; 5317 5318 err = mlx5_nic_vport_enable_roce(dev->mdev); 5319 if (err) 5320 return err; 5321 5322 err = mlx5_eth_lag_init(dev); 5323 if (err) 5324 goto err_disable_roce; 5325 5326 return 0; 5327 5328 err_disable_roce: 5329 mlx5_nic_vport_disable_roce(dev->mdev); 5330 5331 return err; 5332 } 5333 5334 static void mlx5_disable_eth(struct mlx5_ib_dev *dev) 5335 { 5336 mlx5_eth_lag_cleanup(dev); 5337 mlx5_nic_vport_disable_roce(dev->mdev); 5338 } 5339 5340 struct mlx5_ib_counter { 5341 const char *name; 5342 size_t offset; 5343 }; 5344 5345 #define INIT_Q_COUNTER(_name) \ 5346 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)} 5347 5348 static const struct mlx5_ib_counter basic_q_cnts[] = { 5349 INIT_Q_COUNTER(rx_write_requests), 5350 INIT_Q_COUNTER(rx_read_requests), 5351 INIT_Q_COUNTER(rx_atomic_requests), 5352 INIT_Q_COUNTER(out_of_buffer), 5353 }; 5354 5355 static const struct mlx5_ib_counter out_of_seq_q_cnts[] = { 5356 INIT_Q_COUNTER(out_of_sequence), 5357 }; 5358 5359 static const struct mlx5_ib_counter retrans_q_cnts[] = { 5360 INIT_Q_COUNTER(duplicate_request), 5361 INIT_Q_COUNTER(rnr_nak_retry_err), 5362 INIT_Q_COUNTER(packet_seq_err), 5363 INIT_Q_COUNTER(implied_nak_seq_err), 5364 INIT_Q_COUNTER(local_ack_timeout_err), 5365 }; 5366 5367 #define INIT_CONG_COUNTER(_name) \ 5368 { .name = #_name, .offset = \ 5369 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)} 5370 5371 static const struct mlx5_ib_counter cong_cnts[] = { 5372 INIT_CONG_COUNTER(rp_cnp_ignored), 5373 INIT_CONG_COUNTER(rp_cnp_handled), 5374 INIT_CONG_COUNTER(np_ecn_marked_roce_packets), 5375 INIT_CONG_COUNTER(np_cnp_sent), 5376 }; 5377 5378 static const struct mlx5_ib_counter extended_err_cnts[] = { 5379 INIT_Q_COUNTER(resp_local_length_error), 5380 INIT_Q_COUNTER(resp_cqe_error), 5381 INIT_Q_COUNTER(req_cqe_error), 5382 INIT_Q_COUNTER(req_remote_invalid_request), 5383 INIT_Q_COUNTER(req_remote_access_errors), 5384 INIT_Q_COUNTER(resp_remote_access_errors), 5385 INIT_Q_COUNTER(resp_cqe_flush_error), 5386 INIT_Q_COUNTER(req_cqe_flush_error), 5387 }; 5388 5389 static const struct mlx5_ib_counter roce_accl_cnts[] = { 5390 INIT_Q_COUNTER(roce_adp_retrans), 5391 INIT_Q_COUNTER(roce_adp_retrans_to), 5392 INIT_Q_COUNTER(roce_slow_restart), 5393 INIT_Q_COUNTER(roce_slow_restart_cnps), 5394 INIT_Q_COUNTER(roce_slow_restart_trans), 5395 }; 5396 5397 #define INIT_EXT_PPCNT_COUNTER(_name) \ 5398 { .name = #_name, .offset = \ 5399 MLX5_BYTE_OFF(ppcnt_reg, \ 5400 counter_set.eth_extended_cntrs_grp_data_layout._name##_high)} 5401 5402 static const struct mlx5_ib_counter ext_ppcnt_cnts[] = { 5403 INIT_EXT_PPCNT_COUNTER(rx_icrc_encapsulated), 5404 }; 5405 5406 static bool is_mdev_switchdev_mode(const struct mlx5_core_dev *mdev) 5407 { 5408 return MLX5_ESWITCH_MANAGER(mdev) && 5409 mlx5_ib_eswitch_mode(mdev->priv.eswitch) == 5410 MLX5_ESWITCH_OFFLOADS; 5411 } 5412 5413 static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev) 5414 { 5415 u32 in[MLX5_ST_SZ_DW(dealloc_q_counter_in)] = {}; 5416 int num_cnt_ports; 5417 int i; 5418 5419 num_cnt_ports = is_mdev_switchdev_mode(dev->mdev) ? 1 : dev->num_ports; 5420 5421 MLX5_SET(dealloc_q_counter_in, in, opcode, 5422 MLX5_CMD_OP_DEALLOC_Q_COUNTER); 5423 5424 for (i = 0; i < num_cnt_ports; i++) { 5425 if (dev->port[i].cnts.set_id) { 5426 MLX5_SET(dealloc_q_counter_in, in, counter_set_id, 5427 dev->port[i].cnts.set_id); 5428 mlx5_cmd_exec_in(dev->mdev, dealloc_q_counter, in); 5429 } 5430 kfree(dev->port[i].cnts.names); 5431 kfree(dev->port[i].cnts.offsets); 5432 } 5433 } 5434 5435 static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev, 5436 struct mlx5_ib_counters *cnts) 5437 { 5438 u32 num_counters; 5439 5440 num_counters = ARRAY_SIZE(basic_q_cnts); 5441 5442 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) 5443 num_counters += ARRAY_SIZE(out_of_seq_q_cnts); 5444 5445 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) 5446 num_counters += ARRAY_SIZE(retrans_q_cnts); 5447 5448 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) 5449 num_counters += ARRAY_SIZE(extended_err_cnts); 5450 5451 if (MLX5_CAP_GEN(dev->mdev, roce_accl)) 5452 num_counters += ARRAY_SIZE(roce_accl_cnts); 5453 5454 cnts->num_q_counters = num_counters; 5455 5456 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 5457 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts); 5458 num_counters += ARRAY_SIZE(cong_cnts); 5459 } 5460 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) { 5461 cnts->num_ext_ppcnt_counters = ARRAY_SIZE(ext_ppcnt_cnts); 5462 num_counters += ARRAY_SIZE(ext_ppcnt_cnts); 5463 } 5464 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL); 5465 if (!cnts->names) 5466 return -ENOMEM; 5467 5468 cnts->offsets = kcalloc(num_counters, 5469 sizeof(cnts->offsets), GFP_KERNEL); 5470 if (!cnts->offsets) 5471 goto err_names; 5472 5473 return 0; 5474 5475 err_names: 5476 kfree(cnts->names); 5477 cnts->names = NULL; 5478 return -ENOMEM; 5479 } 5480 5481 static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev, 5482 const char **names, 5483 size_t *offsets) 5484 { 5485 int i; 5486 int j = 0; 5487 5488 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) { 5489 names[j] = basic_q_cnts[i].name; 5490 offsets[j] = basic_q_cnts[i].offset; 5491 } 5492 5493 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) { 5494 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) { 5495 names[j] = out_of_seq_q_cnts[i].name; 5496 offsets[j] = out_of_seq_q_cnts[i].offset; 5497 } 5498 } 5499 5500 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) { 5501 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) { 5502 names[j] = retrans_q_cnts[i].name; 5503 offsets[j] = retrans_q_cnts[i].offset; 5504 } 5505 } 5506 5507 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) { 5508 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) { 5509 names[j] = extended_err_cnts[i].name; 5510 offsets[j] = extended_err_cnts[i].offset; 5511 } 5512 } 5513 5514 if (MLX5_CAP_GEN(dev->mdev, roce_accl)) { 5515 for (i = 0; i < ARRAY_SIZE(roce_accl_cnts); i++, j++) { 5516 names[j] = roce_accl_cnts[i].name; 5517 offsets[j] = roce_accl_cnts[i].offset; 5518 } 5519 } 5520 5521 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 5522 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) { 5523 names[j] = cong_cnts[i].name; 5524 offsets[j] = cong_cnts[i].offset; 5525 } 5526 } 5527 5528 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) { 5529 for (i = 0; i < ARRAY_SIZE(ext_ppcnt_cnts); i++, j++) { 5530 names[j] = ext_ppcnt_cnts[i].name; 5531 offsets[j] = ext_ppcnt_cnts[i].offset; 5532 } 5533 } 5534 } 5535 5536 static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev) 5537 { 5538 u32 out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {}; 5539 u32 in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {}; 5540 int num_cnt_ports; 5541 int err = 0; 5542 int i; 5543 bool is_shared; 5544 5545 MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER); 5546 is_shared = MLX5_CAP_GEN(dev->mdev, log_max_uctx) != 0; 5547 num_cnt_ports = is_mdev_switchdev_mode(dev->mdev) ? 1 : dev->num_ports; 5548 5549 for (i = 0; i < num_cnt_ports; i++) { 5550 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts); 5551 if (err) 5552 goto err_alloc; 5553 5554 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names, 5555 dev->port[i].cnts.offsets); 5556 5557 MLX5_SET(alloc_q_counter_in, in, uid, 5558 is_shared ? MLX5_SHARED_RESOURCE_UID : 0); 5559 5560 err = mlx5_cmd_exec_inout(dev->mdev, alloc_q_counter, in, out); 5561 if (err) { 5562 mlx5_ib_warn(dev, 5563 "couldn't allocate queue counter for port %d, err %d\n", 5564 i + 1, err); 5565 goto err_alloc; 5566 } 5567 5568 dev->port[i].cnts.set_id = 5569 MLX5_GET(alloc_q_counter_out, out, counter_set_id); 5570 } 5571 return 0; 5572 5573 err_alloc: 5574 mlx5_ib_dealloc_counters(dev); 5575 return err; 5576 } 5577 5578 static const struct mlx5_ib_counters *get_counters(struct mlx5_ib_dev *dev, 5579 u8 port_num) 5580 { 5581 return is_mdev_switchdev_mode(dev->mdev) ? &dev->port[0].cnts : 5582 &dev->port[port_num].cnts; 5583 } 5584 5585 /** 5586 * mlx5_ib_get_counters_id - Returns counters id to use for device+port 5587 * @dev: Pointer to mlx5 IB device 5588 * @port_num: Zero based port number 5589 * 5590 * mlx5_ib_get_counters_id() Returns counters set id to use for given 5591 * device port combination in switchdev and non switchdev mode of the 5592 * parent device. 5593 */ 5594 u16 mlx5_ib_get_counters_id(struct mlx5_ib_dev *dev, u8 port_num) 5595 { 5596 const struct mlx5_ib_counters *cnts = get_counters(dev, port_num); 5597 5598 return cnts->set_id; 5599 } 5600 5601 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev, 5602 u8 port_num) 5603 { 5604 struct mlx5_ib_dev *dev = to_mdev(ibdev); 5605 const struct mlx5_ib_counters *cnts; 5606 bool is_switchdev = is_mdev_switchdev_mode(dev->mdev); 5607 5608 if ((is_switchdev && port_num) || (!is_switchdev && !port_num)) 5609 return NULL; 5610 5611 cnts = get_counters(dev, port_num - 1); 5612 5613 return rdma_alloc_hw_stats_struct(cnts->names, 5614 cnts->num_q_counters + 5615 cnts->num_cong_counters + 5616 cnts->num_ext_ppcnt_counters, 5617 RDMA_HW_STATS_DEFAULT_LIFESPAN); 5618 } 5619 5620 static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev, 5621 const struct mlx5_ib_counters *cnts, 5622 struct rdma_hw_stats *stats, 5623 u16 set_id) 5624 { 5625 u32 out[MLX5_ST_SZ_DW(query_q_counter_out)] = {}; 5626 u32 in[MLX5_ST_SZ_DW(query_q_counter_in)] = {}; 5627 __be32 val; 5628 int ret, i; 5629 5630 MLX5_SET(query_q_counter_in, in, opcode, MLX5_CMD_OP_QUERY_Q_COUNTER); 5631 MLX5_SET(query_q_counter_in, in, counter_set_id, set_id); 5632 ret = mlx5_cmd_exec_inout(mdev, query_q_counter, in, out); 5633 if (ret) 5634 return ret; 5635 5636 for (i = 0; i < cnts->num_q_counters; i++) { 5637 val = *(__be32 *)((void *)out + cnts->offsets[i]); 5638 stats->value[i] = (u64)be32_to_cpu(val); 5639 } 5640 5641 return 0; 5642 } 5643 5644 static int mlx5_ib_query_ext_ppcnt_counters(struct mlx5_ib_dev *dev, 5645 const struct mlx5_ib_counters *cnts, 5646 struct rdma_hw_stats *stats) 5647 { 5648 int offset = cnts->num_q_counters + cnts->num_cong_counters; 5649 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg); 5650 int ret, i; 5651 void *out; 5652 5653 out = kvzalloc(sz, GFP_KERNEL); 5654 if (!out) 5655 return -ENOMEM; 5656 5657 ret = mlx5_cmd_query_ext_ppcnt_counters(dev->mdev, out); 5658 if (ret) 5659 goto free; 5660 5661 for (i = 0; i < cnts->num_ext_ppcnt_counters; i++) 5662 stats->value[i + offset] = 5663 be64_to_cpup((__be64 *)(out + 5664 cnts->offsets[i + offset])); 5665 free: 5666 kvfree(out); 5667 return ret; 5668 } 5669 5670 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev, 5671 struct rdma_hw_stats *stats, 5672 u8 port_num, int index) 5673 { 5674 struct mlx5_ib_dev *dev = to_mdev(ibdev); 5675 const struct mlx5_ib_counters *cnts = get_counters(dev, port_num - 1); 5676 struct mlx5_core_dev *mdev; 5677 int ret, num_counters; 5678 u8 mdev_port_num; 5679 5680 if (!stats) 5681 return -EINVAL; 5682 5683 num_counters = cnts->num_q_counters + 5684 cnts->num_cong_counters + 5685 cnts->num_ext_ppcnt_counters; 5686 5687 /* q_counters are per IB device, query the master mdev */ 5688 ret = mlx5_ib_query_q_counters(dev->mdev, cnts, stats, cnts->set_id); 5689 if (ret) 5690 return ret; 5691 5692 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) { 5693 ret = mlx5_ib_query_ext_ppcnt_counters(dev, cnts, stats); 5694 if (ret) 5695 return ret; 5696 } 5697 5698 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 5699 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, 5700 &mdev_port_num); 5701 if (!mdev) { 5702 /* If port is not affiliated yet, its in down state 5703 * which doesn't have any counters yet, so it would be 5704 * zero. So no need to read from the HCA. 5705 */ 5706 goto done; 5707 } 5708 ret = mlx5_lag_query_cong_counters(dev->mdev, 5709 stats->value + 5710 cnts->num_q_counters, 5711 cnts->num_cong_counters, 5712 cnts->offsets + 5713 cnts->num_q_counters); 5714 5715 mlx5_ib_put_native_port_mdev(dev, port_num); 5716 if (ret) 5717 return ret; 5718 } 5719 5720 done: 5721 return num_counters; 5722 } 5723 5724 static struct rdma_hw_stats * 5725 mlx5_ib_counter_alloc_stats(struct rdma_counter *counter) 5726 { 5727 struct mlx5_ib_dev *dev = to_mdev(counter->device); 5728 const struct mlx5_ib_counters *cnts = 5729 get_counters(dev, counter->port - 1); 5730 5731 return rdma_alloc_hw_stats_struct(cnts->names, 5732 cnts->num_q_counters + 5733 cnts->num_cong_counters + 5734 cnts->num_ext_ppcnt_counters, 5735 RDMA_HW_STATS_DEFAULT_LIFESPAN); 5736 } 5737 5738 static int mlx5_ib_counter_update_stats(struct rdma_counter *counter) 5739 { 5740 struct mlx5_ib_dev *dev = to_mdev(counter->device); 5741 const struct mlx5_ib_counters *cnts = 5742 get_counters(dev, counter->port - 1); 5743 5744 return mlx5_ib_query_q_counters(dev->mdev, cnts, 5745 counter->stats, counter->id); 5746 } 5747 5748 static int mlx5_ib_counter_dealloc(struct rdma_counter *counter) 5749 { 5750 struct mlx5_ib_dev *dev = to_mdev(counter->device); 5751 u32 in[MLX5_ST_SZ_DW(dealloc_q_counter_in)] = {}; 5752 5753 if (!counter->id) 5754 return 0; 5755 5756 MLX5_SET(dealloc_q_counter_in, in, opcode, 5757 MLX5_CMD_OP_DEALLOC_Q_COUNTER); 5758 MLX5_SET(dealloc_q_counter_in, in, counter_set_id, counter->id); 5759 return mlx5_cmd_exec_in(dev->mdev, dealloc_q_counter, in); 5760 } 5761 5762 static int mlx5_ib_counter_bind_qp(struct rdma_counter *counter, 5763 struct ib_qp *qp) 5764 { 5765 struct mlx5_ib_dev *dev = to_mdev(qp->device); 5766 int err; 5767 5768 if (!counter->id) { 5769 u32 out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {}; 5770 u32 in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {}; 5771 5772 MLX5_SET(alloc_q_counter_in, in, opcode, 5773 MLX5_CMD_OP_ALLOC_Q_COUNTER); 5774 MLX5_SET(alloc_q_counter_in, in, uid, MLX5_SHARED_RESOURCE_UID); 5775 err = mlx5_cmd_exec_inout(dev->mdev, alloc_q_counter, in, out); 5776 if (err) 5777 return err; 5778 counter->id = 5779 MLX5_GET(alloc_q_counter_out, out, counter_set_id); 5780 } 5781 5782 err = mlx5_ib_qp_set_counter(qp, counter); 5783 if (err) 5784 goto fail_set_counter; 5785 5786 return 0; 5787 5788 fail_set_counter: 5789 mlx5_ib_counter_dealloc(counter); 5790 counter->id = 0; 5791 5792 return err; 5793 } 5794 5795 static int mlx5_ib_counter_unbind_qp(struct ib_qp *qp) 5796 { 5797 return mlx5_ib_qp_set_counter(qp, NULL); 5798 } 5799 5800 static int mlx5_ib_rn_get_params(struct ib_device *device, u8 port_num, 5801 enum rdma_netdev_t type, 5802 struct rdma_netdev_alloc_params *params) 5803 { 5804 if (type != RDMA_NETDEV_IPOIB) 5805 return -EOPNOTSUPP; 5806 5807 return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params); 5808 } 5809 5810 static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev) 5811 { 5812 if (!dev->delay_drop.dir_debugfs) 5813 return; 5814 debugfs_remove_recursive(dev->delay_drop.dir_debugfs); 5815 dev->delay_drop.dir_debugfs = NULL; 5816 } 5817 5818 static void cancel_delay_drop(struct mlx5_ib_dev *dev) 5819 { 5820 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 5821 return; 5822 5823 cancel_work_sync(&dev->delay_drop.delay_drop_work); 5824 delay_drop_debugfs_cleanup(dev); 5825 } 5826 5827 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf, 5828 size_t count, loff_t *pos) 5829 { 5830 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 5831 char lbuf[20]; 5832 int len; 5833 5834 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout); 5835 return simple_read_from_buffer(buf, count, pos, lbuf, len); 5836 } 5837 5838 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf, 5839 size_t count, loff_t *pos) 5840 { 5841 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 5842 u32 timeout; 5843 u32 var; 5844 5845 if (kstrtouint_from_user(buf, count, 0, &var)) 5846 return -EFAULT; 5847 5848 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 5849 1000); 5850 if (timeout != var) 5851 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n", 5852 timeout); 5853 5854 delay_drop->timeout = timeout; 5855 5856 return count; 5857 } 5858 5859 static const struct file_operations fops_delay_drop_timeout = { 5860 .owner = THIS_MODULE, 5861 .open = simple_open, 5862 .write = delay_drop_timeout_write, 5863 .read = delay_drop_timeout_read, 5864 }; 5865 5866 static void delay_drop_debugfs_init(struct mlx5_ib_dev *dev) 5867 { 5868 struct dentry *root; 5869 5870 if (!mlx5_debugfs_root) 5871 return; 5872 5873 root = debugfs_create_dir("delay_drop", dev->mdev->priv.dbg_root); 5874 dev->delay_drop.dir_debugfs = root; 5875 5876 debugfs_create_atomic_t("num_timeout_events", 0400, root, 5877 &dev->delay_drop.events_cnt); 5878 debugfs_create_atomic_t("num_rqs", 0400, root, 5879 &dev->delay_drop.rqs_cnt); 5880 debugfs_create_file("timeout", 0600, root, &dev->delay_drop, 5881 &fops_delay_drop_timeout); 5882 } 5883 5884 static void init_delay_drop(struct mlx5_ib_dev *dev) 5885 { 5886 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 5887 return; 5888 5889 mutex_init(&dev->delay_drop.lock); 5890 dev->delay_drop.dev = dev; 5891 dev->delay_drop.activate = false; 5892 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000; 5893 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler); 5894 atomic_set(&dev->delay_drop.rqs_cnt, 0); 5895 atomic_set(&dev->delay_drop.events_cnt, 0); 5896 5897 delay_drop_debugfs_init(dev); 5898 } 5899 5900 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev, 5901 struct mlx5_ib_multiport_info *mpi) 5902 { 5903 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 5904 struct mlx5_ib_port *port = &ibdev->port[port_num]; 5905 int comps; 5906 int err; 5907 int i; 5908 5909 lockdep_assert_held(&mlx5_ib_multiport_mutex); 5910 5911 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num); 5912 5913 spin_lock(&port->mp.mpi_lock); 5914 if (!mpi->ibdev) { 5915 spin_unlock(&port->mp.mpi_lock); 5916 return; 5917 } 5918 5919 mpi->ibdev = NULL; 5920 5921 spin_unlock(&port->mp.mpi_lock); 5922 if (mpi->mdev_events.notifier_call) 5923 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events); 5924 mpi->mdev_events.notifier_call = NULL; 5925 mlx5_remove_netdev_notifier(ibdev, port_num); 5926 spin_lock(&port->mp.mpi_lock); 5927 5928 comps = mpi->mdev_refcnt; 5929 if (comps) { 5930 mpi->unaffiliate = true; 5931 init_completion(&mpi->unref_comp); 5932 spin_unlock(&port->mp.mpi_lock); 5933 5934 for (i = 0; i < comps; i++) 5935 wait_for_completion(&mpi->unref_comp); 5936 5937 spin_lock(&port->mp.mpi_lock); 5938 mpi->unaffiliate = false; 5939 } 5940 5941 port->mp.mpi = NULL; 5942 5943 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 5944 5945 spin_unlock(&port->mp.mpi_lock); 5946 5947 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev); 5948 5949 mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1); 5950 /* Log an error, still needed to cleanup the pointers and add 5951 * it back to the list. 5952 */ 5953 if (err) 5954 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n", 5955 port_num + 1); 5956 5957 ibdev->port[port_num].roce.last_port_state = IB_PORT_DOWN; 5958 } 5959 5960 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev, 5961 struct mlx5_ib_multiport_info *mpi) 5962 { 5963 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 5964 int err; 5965 5966 lockdep_assert_held(&mlx5_ib_multiport_mutex); 5967 5968 spin_lock(&ibdev->port[port_num].mp.mpi_lock); 5969 if (ibdev->port[port_num].mp.mpi) { 5970 mlx5_ib_dbg(ibdev, "port %d already affiliated.\n", 5971 port_num + 1); 5972 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 5973 return false; 5974 } 5975 5976 ibdev->port[port_num].mp.mpi = mpi; 5977 mpi->ibdev = ibdev; 5978 mpi->mdev_events.notifier_call = NULL; 5979 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 5980 5981 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev); 5982 if (err) 5983 goto unbind; 5984 5985 err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev)); 5986 if (err) 5987 goto unbind; 5988 5989 err = mlx5_add_netdev_notifier(ibdev, port_num); 5990 if (err) { 5991 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n", 5992 port_num + 1); 5993 goto unbind; 5994 } 5995 5996 mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port; 5997 mlx5_notifier_register(mpi->mdev, &mpi->mdev_events); 5998 5999 mlx5_ib_init_cong_debugfs(ibdev, port_num); 6000 6001 return true; 6002 6003 unbind: 6004 mlx5_ib_unbind_slave_port(ibdev, mpi); 6005 return false; 6006 } 6007 6008 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev) 6009 { 6010 int port_num = mlx5_core_native_port_num(dev->mdev) - 1; 6011 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 6012 port_num + 1); 6013 struct mlx5_ib_multiport_info *mpi; 6014 int err; 6015 int i; 6016 6017 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 6018 return 0; 6019 6020 err = mlx5_query_nic_vport_system_image_guid(dev->mdev, 6021 &dev->sys_image_guid); 6022 if (err) 6023 return err; 6024 6025 err = mlx5_nic_vport_enable_roce(dev->mdev); 6026 if (err) 6027 return err; 6028 6029 mutex_lock(&mlx5_ib_multiport_mutex); 6030 for (i = 0; i < dev->num_ports; i++) { 6031 bool bound = false; 6032 6033 /* build a stub multiport info struct for the native port. */ 6034 if (i == port_num) { 6035 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 6036 if (!mpi) { 6037 mutex_unlock(&mlx5_ib_multiport_mutex); 6038 mlx5_nic_vport_disable_roce(dev->mdev); 6039 return -ENOMEM; 6040 } 6041 6042 mpi->is_master = true; 6043 mpi->mdev = dev->mdev; 6044 mpi->sys_image_guid = dev->sys_image_guid; 6045 dev->port[i].mp.mpi = mpi; 6046 mpi->ibdev = dev; 6047 mpi = NULL; 6048 continue; 6049 } 6050 6051 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list, 6052 list) { 6053 if (dev->sys_image_guid == mpi->sys_image_guid && 6054 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) { 6055 bound = mlx5_ib_bind_slave_port(dev, mpi); 6056 } 6057 6058 if (bound) { 6059 dev_dbg(mpi->mdev->device, 6060 "removing port from unaffiliated list.\n"); 6061 mlx5_ib_dbg(dev, "port %d bound\n", i + 1); 6062 list_del(&mpi->list); 6063 break; 6064 } 6065 } 6066 if (!bound) { 6067 get_port_caps(dev, i + 1); 6068 mlx5_ib_dbg(dev, "no free port found for port %d\n", 6069 i + 1); 6070 } 6071 } 6072 6073 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list); 6074 mutex_unlock(&mlx5_ib_multiport_mutex); 6075 return err; 6076 } 6077 6078 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev) 6079 { 6080 int port_num = mlx5_core_native_port_num(dev->mdev) - 1; 6081 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 6082 port_num + 1); 6083 int i; 6084 6085 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 6086 return; 6087 6088 mutex_lock(&mlx5_ib_multiport_mutex); 6089 for (i = 0; i < dev->num_ports; i++) { 6090 if (dev->port[i].mp.mpi) { 6091 /* Destroy the native port stub */ 6092 if (i == port_num) { 6093 kfree(dev->port[i].mp.mpi); 6094 dev->port[i].mp.mpi = NULL; 6095 } else { 6096 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1); 6097 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi); 6098 } 6099 } 6100 } 6101 6102 mlx5_ib_dbg(dev, "removing from devlist\n"); 6103 list_del(&dev->ib_dev_list); 6104 mutex_unlock(&mlx5_ib_multiport_mutex); 6105 6106 mlx5_nic_vport_disable_roce(dev->mdev); 6107 } 6108 6109 static int mmap_obj_cleanup(struct ib_uobject *uobject, 6110 enum rdma_remove_reason why, 6111 struct uverbs_attr_bundle *attrs) 6112 { 6113 struct mlx5_user_mmap_entry *obj = uobject->object; 6114 6115 rdma_user_mmap_entry_remove(&obj->rdma_entry); 6116 return 0; 6117 } 6118 6119 static int mlx5_rdma_user_mmap_entry_insert(struct mlx5_ib_ucontext *c, 6120 struct mlx5_user_mmap_entry *entry, 6121 size_t length) 6122 { 6123 return rdma_user_mmap_entry_insert_range( 6124 &c->ibucontext, &entry->rdma_entry, length, 6125 (MLX5_IB_MMAP_OFFSET_START << 16), 6126 ((MLX5_IB_MMAP_OFFSET_END << 16) + (1UL << 16) - 1)); 6127 } 6128 6129 static struct mlx5_user_mmap_entry * 6130 alloc_var_entry(struct mlx5_ib_ucontext *c) 6131 { 6132 struct mlx5_user_mmap_entry *entry; 6133 struct mlx5_var_table *var_table; 6134 u32 page_idx; 6135 int err; 6136 6137 var_table = &to_mdev(c->ibucontext.device)->var_table; 6138 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 6139 if (!entry) 6140 return ERR_PTR(-ENOMEM); 6141 6142 mutex_lock(&var_table->bitmap_lock); 6143 page_idx = find_first_zero_bit(var_table->bitmap, 6144 var_table->num_var_hw_entries); 6145 if (page_idx >= var_table->num_var_hw_entries) { 6146 err = -ENOSPC; 6147 mutex_unlock(&var_table->bitmap_lock); 6148 goto end; 6149 } 6150 6151 set_bit(page_idx, var_table->bitmap); 6152 mutex_unlock(&var_table->bitmap_lock); 6153 6154 entry->address = var_table->hw_start_addr + 6155 (page_idx * var_table->stride_size); 6156 entry->page_idx = page_idx; 6157 entry->mmap_flag = MLX5_IB_MMAP_TYPE_VAR; 6158 6159 err = mlx5_rdma_user_mmap_entry_insert(c, entry, 6160 var_table->stride_size); 6161 if (err) 6162 goto err_insert; 6163 6164 return entry; 6165 6166 err_insert: 6167 mutex_lock(&var_table->bitmap_lock); 6168 clear_bit(page_idx, var_table->bitmap); 6169 mutex_unlock(&var_table->bitmap_lock); 6170 end: 6171 kfree(entry); 6172 return ERR_PTR(err); 6173 } 6174 6175 static int UVERBS_HANDLER(MLX5_IB_METHOD_VAR_OBJ_ALLOC)( 6176 struct uverbs_attr_bundle *attrs) 6177 { 6178 struct ib_uobject *uobj = uverbs_attr_get_uobject( 6179 attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE); 6180 struct mlx5_ib_ucontext *c; 6181 struct mlx5_user_mmap_entry *entry; 6182 u64 mmap_offset; 6183 u32 length; 6184 int err; 6185 6186 c = to_mucontext(ib_uverbs_get_ucontext(attrs)); 6187 if (IS_ERR(c)) 6188 return PTR_ERR(c); 6189 6190 entry = alloc_var_entry(c); 6191 if (IS_ERR(entry)) 6192 return PTR_ERR(entry); 6193 6194 mmap_offset = mlx5_entry_to_mmap_offset(entry); 6195 length = entry->rdma_entry.npages * PAGE_SIZE; 6196 uobj->object = entry; 6197 6198 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET, 6199 &mmap_offset, sizeof(mmap_offset)); 6200 if (err) 6201 goto err; 6202 6203 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID, 6204 &entry->page_idx, sizeof(entry->page_idx)); 6205 if (err) 6206 goto err; 6207 6208 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH, 6209 &length, sizeof(length)); 6210 if (err) 6211 goto err; 6212 6213 return 0; 6214 6215 err: 6216 rdma_user_mmap_entry_remove(&entry->rdma_entry); 6217 return err; 6218 } 6219 6220 DECLARE_UVERBS_NAMED_METHOD( 6221 MLX5_IB_METHOD_VAR_OBJ_ALLOC, 6222 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE, 6223 MLX5_IB_OBJECT_VAR, 6224 UVERBS_ACCESS_NEW, 6225 UA_MANDATORY), 6226 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID, 6227 UVERBS_ATTR_TYPE(u32), 6228 UA_MANDATORY), 6229 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH, 6230 UVERBS_ATTR_TYPE(u32), 6231 UA_MANDATORY), 6232 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET, 6233 UVERBS_ATTR_TYPE(u64), 6234 UA_MANDATORY)); 6235 6236 DECLARE_UVERBS_NAMED_METHOD_DESTROY( 6237 MLX5_IB_METHOD_VAR_OBJ_DESTROY, 6238 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_DESTROY_HANDLE, 6239 MLX5_IB_OBJECT_VAR, 6240 UVERBS_ACCESS_DESTROY, 6241 UA_MANDATORY)); 6242 6243 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_VAR, 6244 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup), 6245 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_ALLOC), 6246 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_DESTROY)); 6247 6248 static bool var_is_supported(struct ib_device *device) 6249 { 6250 struct mlx5_ib_dev *dev = to_mdev(device); 6251 6252 return (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 6253 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q); 6254 } 6255 6256 static struct mlx5_user_mmap_entry * 6257 alloc_uar_entry(struct mlx5_ib_ucontext *c, 6258 enum mlx5_ib_uapi_uar_alloc_type alloc_type) 6259 { 6260 struct mlx5_user_mmap_entry *entry; 6261 struct mlx5_ib_dev *dev; 6262 u32 uar_index; 6263 int err; 6264 6265 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 6266 if (!entry) 6267 return ERR_PTR(-ENOMEM); 6268 6269 dev = to_mdev(c->ibucontext.device); 6270 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index); 6271 if (err) 6272 goto end; 6273 6274 entry->page_idx = uar_index; 6275 entry->address = uar_index2paddress(dev, uar_index); 6276 if (alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF) 6277 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_WC; 6278 else 6279 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_NC; 6280 6281 err = mlx5_rdma_user_mmap_entry_insert(c, entry, PAGE_SIZE); 6282 if (err) 6283 goto err_insert; 6284 6285 return entry; 6286 6287 err_insert: 6288 mlx5_cmd_free_uar(dev->mdev, uar_index); 6289 end: 6290 kfree(entry); 6291 return ERR_PTR(err); 6292 } 6293 6294 static int UVERBS_HANDLER(MLX5_IB_METHOD_UAR_OBJ_ALLOC)( 6295 struct uverbs_attr_bundle *attrs) 6296 { 6297 struct ib_uobject *uobj = uverbs_attr_get_uobject( 6298 attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE); 6299 enum mlx5_ib_uapi_uar_alloc_type alloc_type; 6300 struct mlx5_ib_ucontext *c; 6301 struct mlx5_user_mmap_entry *entry; 6302 u64 mmap_offset; 6303 u32 length; 6304 int err; 6305 6306 c = to_mucontext(ib_uverbs_get_ucontext(attrs)); 6307 if (IS_ERR(c)) 6308 return PTR_ERR(c); 6309 6310 err = uverbs_get_const(&alloc_type, attrs, 6311 MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE); 6312 if (err) 6313 return err; 6314 6315 if (alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF && 6316 alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_NC) 6317 return -EOPNOTSUPP; 6318 6319 if (!to_mdev(c->ibucontext.device)->wc_support && 6320 alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF) 6321 return -EOPNOTSUPP; 6322 6323 entry = alloc_uar_entry(c, alloc_type); 6324 if (IS_ERR(entry)) 6325 return PTR_ERR(entry); 6326 6327 mmap_offset = mlx5_entry_to_mmap_offset(entry); 6328 length = entry->rdma_entry.npages * PAGE_SIZE; 6329 uobj->object = entry; 6330 6331 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET, 6332 &mmap_offset, sizeof(mmap_offset)); 6333 if (err) 6334 goto err; 6335 6336 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID, 6337 &entry->page_idx, sizeof(entry->page_idx)); 6338 if (err) 6339 goto err; 6340 6341 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH, 6342 &length, sizeof(length)); 6343 if (err) 6344 goto err; 6345 6346 return 0; 6347 6348 err: 6349 rdma_user_mmap_entry_remove(&entry->rdma_entry); 6350 return err; 6351 } 6352 6353 DECLARE_UVERBS_NAMED_METHOD( 6354 MLX5_IB_METHOD_UAR_OBJ_ALLOC, 6355 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE, 6356 MLX5_IB_OBJECT_UAR, 6357 UVERBS_ACCESS_NEW, 6358 UA_MANDATORY), 6359 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE, 6360 enum mlx5_ib_uapi_uar_alloc_type, 6361 UA_MANDATORY), 6362 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID, 6363 UVERBS_ATTR_TYPE(u32), 6364 UA_MANDATORY), 6365 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH, 6366 UVERBS_ATTR_TYPE(u32), 6367 UA_MANDATORY), 6368 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET, 6369 UVERBS_ATTR_TYPE(u64), 6370 UA_MANDATORY)); 6371 6372 DECLARE_UVERBS_NAMED_METHOD_DESTROY( 6373 MLX5_IB_METHOD_UAR_OBJ_DESTROY, 6374 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_DESTROY_HANDLE, 6375 MLX5_IB_OBJECT_UAR, 6376 UVERBS_ACCESS_DESTROY, 6377 UA_MANDATORY)); 6378 6379 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_UAR, 6380 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup), 6381 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_ALLOC), 6382 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_DESTROY)); 6383 6384 ADD_UVERBS_ATTRIBUTES_SIMPLE( 6385 mlx5_ib_dm, 6386 UVERBS_OBJECT_DM, 6387 UVERBS_METHOD_DM_ALLOC, 6388 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET, 6389 UVERBS_ATTR_TYPE(u64), 6390 UA_MANDATORY), 6391 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX, 6392 UVERBS_ATTR_TYPE(u16), 6393 UA_OPTIONAL), 6394 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE, 6395 enum mlx5_ib_uapi_dm_type, 6396 UA_OPTIONAL)); 6397 6398 ADD_UVERBS_ATTRIBUTES_SIMPLE( 6399 mlx5_ib_flow_action, 6400 UVERBS_OBJECT_FLOW_ACTION, 6401 UVERBS_METHOD_FLOW_ACTION_ESP_CREATE, 6402 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS, 6403 enum mlx5_ib_uapi_flow_action_flags)); 6404 6405 static const struct uapi_definition mlx5_ib_defs[] = { 6406 UAPI_DEF_CHAIN(mlx5_ib_devx_defs), 6407 UAPI_DEF_CHAIN(mlx5_ib_flow_defs), 6408 UAPI_DEF_CHAIN(mlx5_ib_qos_defs), 6409 6410 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_FLOW_ACTION, 6411 &mlx5_ib_flow_action), 6412 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DM, &mlx5_ib_dm), 6413 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_VAR, 6414 UAPI_DEF_IS_OBJ_SUPPORTED(var_is_supported)), 6415 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_UAR), 6416 {} 6417 }; 6418 6419 static int mlx5_ib_read_counters(struct ib_counters *counters, 6420 struct ib_counters_read_attr *read_attr, 6421 struct uverbs_attr_bundle *attrs) 6422 { 6423 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters); 6424 struct mlx5_read_counters_attr mread_attr = {}; 6425 struct mlx5_ib_flow_counters_desc *desc; 6426 int ret, i; 6427 6428 mutex_lock(&mcounters->mcntrs_mutex); 6429 if (mcounters->cntrs_max_index > read_attr->ncounters) { 6430 ret = -EINVAL; 6431 goto err_bound; 6432 } 6433 6434 mread_attr.out = kcalloc(mcounters->counters_num, sizeof(u64), 6435 GFP_KERNEL); 6436 if (!mread_attr.out) { 6437 ret = -ENOMEM; 6438 goto err_bound; 6439 } 6440 6441 mread_attr.hw_cntrs_hndl = mcounters->hw_cntrs_hndl; 6442 mread_attr.flags = read_attr->flags; 6443 ret = mcounters->read_counters(counters->device, &mread_attr); 6444 if (ret) 6445 goto err_read; 6446 6447 /* do the pass over the counters data array to assign according to the 6448 * descriptions and indexing pairs 6449 */ 6450 desc = mcounters->counters_data; 6451 for (i = 0; i < mcounters->ncounters; i++) 6452 read_attr->counters_buff[desc[i].index] += mread_attr.out[desc[i].description]; 6453 6454 err_read: 6455 kfree(mread_attr.out); 6456 err_bound: 6457 mutex_unlock(&mcounters->mcntrs_mutex); 6458 return ret; 6459 } 6460 6461 static int mlx5_ib_destroy_counters(struct ib_counters *counters) 6462 { 6463 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters); 6464 6465 counters_clear_description(counters); 6466 if (mcounters->hw_cntrs_hndl) 6467 mlx5_fc_destroy(to_mdev(counters->device)->mdev, 6468 mcounters->hw_cntrs_hndl); 6469 6470 kfree(mcounters); 6471 6472 return 0; 6473 } 6474 6475 static struct ib_counters *mlx5_ib_create_counters(struct ib_device *device, 6476 struct uverbs_attr_bundle *attrs) 6477 { 6478 struct mlx5_ib_mcounters *mcounters; 6479 6480 mcounters = kzalloc(sizeof(*mcounters), GFP_KERNEL); 6481 if (!mcounters) 6482 return ERR_PTR(-ENOMEM); 6483 6484 mutex_init(&mcounters->mcntrs_mutex); 6485 6486 return &mcounters->ibcntrs; 6487 } 6488 6489 static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev) 6490 { 6491 mlx5_ib_cleanup_multiport_master(dev); 6492 WARN_ON(!xa_empty(&dev->odp_mkeys)); 6493 cleanup_srcu_struct(&dev->odp_srcu); 6494 6495 WARN_ON(!xa_empty(&dev->sig_mrs)); 6496 WARN_ON(!bitmap_empty(dev->dm.memic_alloc_pages, MLX5_MAX_MEMIC_PAGES)); 6497 } 6498 6499 static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev) 6500 { 6501 struct mlx5_core_dev *mdev = dev->mdev; 6502 int err; 6503 int i; 6504 6505 for (i = 0; i < dev->num_ports; i++) { 6506 spin_lock_init(&dev->port[i].mp.mpi_lock); 6507 rwlock_init(&dev->port[i].roce.netdev_lock); 6508 dev->port[i].roce.dev = dev; 6509 dev->port[i].roce.native_port_num = i + 1; 6510 dev->port[i].roce.last_port_state = IB_PORT_DOWN; 6511 } 6512 6513 mlx5_ib_internal_fill_odp_caps(dev); 6514 6515 err = mlx5_ib_init_multiport_master(dev); 6516 if (err) 6517 return err; 6518 6519 err = set_has_smi_cap(dev); 6520 if (err) 6521 return err; 6522 6523 if (!mlx5_core_mp_enabled(mdev)) { 6524 for (i = 1; i <= dev->num_ports; i++) { 6525 err = get_port_caps(dev, i); 6526 if (err) 6527 break; 6528 } 6529 } else { 6530 err = get_port_caps(dev, mlx5_core_native_port_num(mdev)); 6531 } 6532 if (err) 6533 goto err_mp; 6534 6535 if (mlx5_use_mad_ifc(dev)) 6536 get_ext_port_caps(dev); 6537 6538 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 6539 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 6540 dev->ib_dev.phys_port_cnt = dev->num_ports; 6541 dev->ib_dev.num_comp_vectors = mlx5_comp_vectors_count(mdev); 6542 dev->ib_dev.dev.parent = mdev->device; 6543 dev->ib_dev.lag_flags = RDMA_LAG_FLAGS_HASH_ALL_SLAVES; 6544 6545 mutex_init(&dev->cap_mask_mutex); 6546 INIT_LIST_HEAD(&dev->qp_list); 6547 spin_lock_init(&dev->reset_flow_resource_lock); 6548 xa_init(&dev->odp_mkeys); 6549 xa_init(&dev->sig_mrs); 6550 atomic_set(&dev->mkey_var, 0); 6551 6552 spin_lock_init(&dev->dm.lock); 6553 dev->dm.dev = mdev; 6554 6555 err = init_srcu_struct(&dev->odp_srcu); 6556 if (err) 6557 goto err_mp; 6558 6559 return 0; 6560 6561 err_mp: 6562 mlx5_ib_cleanup_multiport_master(dev); 6563 6564 return -ENOMEM; 6565 } 6566 6567 static int mlx5_ib_stage_flow_db_init(struct mlx5_ib_dev *dev) 6568 { 6569 dev->flow_db = kzalloc(sizeof(*dev->flow_db), GFP_KERNEL); 6570 6571 if (!dev->flow_db) 6572 return -ENOMEM; 6573 6574 mutex_init(&dev->flow_db->lock); 6575 6576 return 0; 6577 } 6578 6579 static void mlx5_ib_stage_flow_db_cleanup(struct mlx5_ib_dev *dev) 6580 { 6581 kfree(dev->flow_db); 6582 } 6583 6584 static const struct ib_device_ops mlx5_ib_dev_ops = { 6585 .owner = THIS_MODULE, 6586 .driver_id = RDMA_DRIVER_MLX5, 6587 .uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION, 6588 6589 .add_gid = mlx5_ib_add_gid, 6590 .alloc_mr = mlx5_ib_alloc_mr, 6591 .alloc_mr_integrity = mlx5_ib_alloc_mr_integrity, 6592 .alloc_pd = mlx5_ib_alloc_pd, 6593 .alloc_ucontext = mlx5_ib_alloc_ucontext, 6594 .attach_mcast = mlx5_ib_mcg_attach, 6595 .check_mr_status = mlx5_ib_check_mr_status, 6596 .create_ah = mlx5_ib_create_ah, 6597 .create_counters = mlx5_ib_create_counters, 6598 .create_cq = mlx5_ib_create_cq, 6599 .create_flow = mlx5_ib_create_flow, 6600 .create_qp = mlx5_ib_create_qp, 6601 .create_srq = mlx5_ib_create_srq, 6602 .dealloc_pd = mlx5_ib_dealloc_pd, 6603 .dealloc_ucontext = mlx5_ib_dealloc_ucontext, 6604 .del_gid = mlx5_ib_del_gid, 6605 .dereg_mr = mlx5_ib_dereg_mr, 6606 .destroy_ah = mlx5_ib_destroy_ah, 6607 .destroy_counters = mlx5_ib_destroy_counters, 6608 .destroy_cq = mlx5_ib_destroy_cq, 6609 .destroy_flow = mlx5_ib_destroy_flow, 6610 .destroy_flow_action = mlx5_ib_destroy_flow_action, 6611 .destroy_qp = mlx5_ib_destroy_qp, 6612 .destroy_srq = mlx5_ib_destroy_srq, 6613 .detach_mcast = mlx5_ib_mcg_detach, 6614 .disassociate_ucontext = mlx5_ib_disassociate_ucontext, 6615 .drain_rq = mlx5_ib_drain_rq, 6616 .drain_sq = mlx5_ib_drain_sq, 6617 .enable_driver = mlx5_ib_enable_driver, 6618 .fill_res_entry = mlx5_ib_fill_res_entry, 6619 .fill_stat_entry = mlx5_ib_fill_stat_entry, 6620 .get_dev_fw_str = get_dev_fw_str, 6621 .get_dma_mr = mlx5_ib_get_dma_mr, 6622 .get_link_layer = mlx5_ib_port_link_layer, 6623 .map_mr_sg = mlx5_ib_map_mr_sg, 6624 .map_mr_sg_pi = mlx5_ib_map_mr_sg_pi, 6625 .mmap = mlx5_ib_mmap, 6626 .mmap_free = mlx5_ib_mmap_free, 6627 .modify_cq = mlx5_ib_modify_cq, 6628 .modify_device = mlx5_ib_modify_device, 6629 .modify_port = mlx5_ib_modify_port, 6630 .modify_qp = mlx5_ib_modify_qp, 6631 .modify_srq = mlx5_ib_modify_srq, 6632 .poll_cq = mlx5_ib_poll_cq, 6633 .post_recv = mlx5_ib_post_recv_nodrain, 6634 .post_send = mlx5_ib_post_send_nodrain, 6635 .post_srq_recv = mlx5_ib_post_srq_recv, 6636 .process_mad = mlx5_ib_process_mad, 6637 .query_ah = mlx5_ib_query_ah, 6638 .query_device = mlx5_ib_query_device, 6639 .query_gid = mlx5_ib_query_gid, 6640 .query_pkey = mlx5_ib_query_pkey, 6641 .query_qp = mlx5_ib_query_qp, 6642 .query_srq = mlx5_ib_query_srq, 6643 .read_counters = mlx5_ib_read_counters, 6644 .reg_user_mr = mlx5_ib_reg_user_mr, 6645 .req_notify_cq = mlx5_ib_arm_cq, 6646 .rereg_user_mr = mlx5_ib_rereg_user_mr, 6647 .resize_cq = mlx5_ib_resize_cq, 6648 6649 INIT_RDMA_OBJ_SIZE(ib_ah, mlx5_ib_ah, ibah), 6650 INIT_RDMA_OBJ_SIZE(ib_cq, mlx5_ib_cq, ibcq), 6651 INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd), 6652 INIT_RDMA_OBJ_SIZE(ib_srq, mlx5_ib_srq, ibsrq), 6653 INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext), 6654 }; 6655 6656 static const struct ib_device_ops mlx5_ib_dev_flow_ipsec_ops = { 6657 .create_flow_action_esp = mlx5_ib_create_flow_action_esp, 6658 .modify_flow_action_esp = mlx5_ib_modify_flow_action_esp, 6659 }; 6660 6661 static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = { 6662 .rdma_netdev_get_params = mlx5_ib_rn_get_params, 6663 }; 6664 6665 static const struct ib_device_ops mlx5_ib_dev_sriov_ops = { 6666 .get_vf_config = mlx5_ib_get_vf_config, 6667 .get_vf_guid = mlx5_ib_get_vf_guid, 6668 .get_vf_stats = mlx5_ib_get_vf_stats, 6669 .set_vf_guid = mlx5_ib_set_vf_guid, 6670 .set_vf_link_state = mlx5_ib_set_vf_link_state, 6671 }; 6672 6673 static const struct ib_device_ops mlx5_ib_dev_mw_ops = { 6674 .alloc_mw = mlx5_ib_alloc_mw, 6675 .dealloc_mw = mlx5_ib_dealloc_mw, 6676 }; 6677 6678 static const struct ib_device_ops mlx5_ib_dev_xrc_ops = { 6679 .alloc_xrcd = mlx5_ib_alloc_xrcd, 6680 .dealloc_xrcd = mlx5_ib_dealloc_xrcd, 6681 }; 6682 6683 static const struct ib_device_ops mlx5_ib_dev_dm_ops = { 6684 .alloc_dm = mlx5_ib_alloc_dm, 6685 .dealloc_dm = mlx5_ib_dealloc_dm, 6686 .reg_dm_mr = mlx5_ib_reg_dm_mr, 6687 }; 6688 6689 static int mlx5_ib_init_var_table(struct mlx5_ib_dev *dev) 6690 { 6691 struct mlx5_core_dev *mdev = dev->mdev; 6692 struct mlx5_var_table *var_table = &dev->var_table; 6693 u8 log_doorbell_bar_size; 6694 u8 log_doorbell_stride; 6695 u64 bar_size; 6696 6697 log_doorbell_bar_size = MLX5_CAP_DEV_VDPA_EMULATION(mdev, 6698 log_doorbell_bar_size); 6699 log_doorbell_stride = MLX5_CAP_DEV_VDPA_EMULATION(mdev, 6700 log_doorbell_stride); 6701 var_table->hw_start_addr = dev->mdev->bar_addr + 6702 MLX5_CAP64_DEV_VDPA_EMULATION(mdev, 6703 doorbell_bar_offset); 6704 bar_size = (1ULL << log_doorbell_bar_size) * 4096; 6705 var_table->stride_size = 1ULL << log_doorbell_stride; 6706 var_table->num_var_hw_entries = div_u64(bar_size, 6707 var_table->stride_size); 6708 mutex_init(&var_table->bitmap_lock); 6709 var_table->bitmap = bitmap_zalloc(var_table->num_var_hw_entries, 6710 GFP_KERNEL); 6711 return (var_table->bitmap) ? 0 : -ENOMEM; 6712 } 6713 6714 static void mlx5_ib_stage_caps_cleanup(struct mlx5_ib_dev *dev) 6715 { 6716 bitmap_free(dev->var_table.bitmap); 6717 } 6718 6719 static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev) 6720 { 6721 struct mlx5_core_dev *mdev = dev->mdev; 6722 int err; 6723 6724 dev->ib_dev.uverbs_cmd_mask = 6725 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | 6726 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | 6727 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | 6728 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | 6729 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | 6730 (1ull << IB_USER_VERBS_CMD_CREATE_AH) | 6731 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) | 6732 (1ull << IB_USER_VERBS_CMD_REG_MR) | 6733 (1ull << IB_USER_VERBS_CMD_REREG_MR) | 6734 (1ull << IB_USER_VERBS_CMD_DEREG_MR) | 6735 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 6736 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | 6737 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) | 6738 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | 6739 (1ull << IB_USER_VERBS_CMD_CREATE_QP) | 6740 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | 6741 (1ull << IB_USER_VERBS_CMD_QUERY_QP) | 6742 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | 6743 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) | 6744 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) | 6745 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | 6746 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | 6747 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | 6748 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | 6749 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) | 6750 (1ull << IB_USER_VERBS_CMD_OPEN_QP); 6751 dev->ib_dev.uverbs_ex_cmd_mask = 6752 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) | 6753 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) | 6754 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) | 6755 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP) | 6756 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ) | 6757 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) | 6758 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW); 6759 6760 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 6761 IS_ENABLED(CONFIG_MLX5_CORE_IPOIB)) 6762 ib_set_device_ops(&dev->ib_dev, 6763 &mlx5_ib_dev_ipoib_enhanced_ops); 6764 6765 if (mlx5_core_is_pf(mdev)) 6766 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops); 6767 6768 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence)); 6769 6770 if (MLX5_CAP_GEN(mdev, imaicl)) { 6771 dev->ib_dev.uverbs_cmd_mask |= 6772 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) | 6773 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW); 6774 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops); 6775 } 6776 6777 if (MLX5_CAP_GEN(mdev, xrc)) { 6778 dev->ib_dev.uverbs_cmd_mask |= 6779 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) | 6780 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD); 6781 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops); 6782 } 6783 6784 if (MLX5_CAP_DEV_MEM(mdev, memic) || 6785 MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 6786 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM) 6787 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops); 6788 6789 if (mlx5_accel_ipsec_device_caps(dev->mdev) & 6790 MLX5_ACCEL_IPSEC_CAP_DEVICE) 6791 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_flow_ipsec_ops); 6792 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops); 6793 6794 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)) 6795 dev->ib_dev.driver_def = mlx5_ib_defs; 6796 6797 err = init_node_data(dev); 6798 if (err) 6799 return err; 6800 6801 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && 6802 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) || 6803 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 6804 mutex_init(&dev->lb.mutex); 6805 6806 if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 6807 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) { 6808 err = mlx5_ib_init_var_table(dev); 6809 if (err) 6810 return err; 6811 } 6812 6813 dev->ib_dev.use_cq_dim = true; 6814 6815 return 0; 6816 } 6817 6818 static const struct ib_device_ops mlx5_ib_dev_port_ops = { 6819 .get_port_immutable = mlx5_port_immutable, 6820 .query_port = mlx5_ib_query_port, 6821 }; 6822 6823 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev) 6824 { 6825 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops); 6826 return 0; 6827 } 6828 6829 static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = { 6830 .get_port_immutable = mlx5_port_rep_immutable, 6831 .query_port = mlx5_ib_rep_query_port, 6832 }; 6833 6834 static int mlx5_ib_stage_raw_eth_non_default_cb(struct mlx5_ib_dev *dev) 6835 { 6836 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops); 6837 return 0; 6838 } 6839 6840 static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = { 6841 .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table, 6842 .create_wq = mlx5_ib_create_wq, 6843 .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table, 6844 .destroy_wq = mlx5_ib_destroy_wq, 6845 .get_netdev = mlx5_ib_get_netdev, 6846 .modify_wq = mlx5_ib_modify_wq, 6847 }; 6848 6849 static int mlx5_ib_stage_common_roce_init(struct mlx5_ib_dev *dev) 6850 { 6851 u8 port_num; 6852 6853 dev->ib_dev.uverbs_ex_cmd_mask |= 6854 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) | 6855 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) | 6856 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) | 6857 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) | 6858 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL); 6859 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops); 6860 6861 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 6862 6863 /* Register only for native ports */ 6864 return mlx5_add_netdev_notifier(dev, port_num); 6865 } 6866 6867 static void mlx5_ib_stage_common_roce_cleanup(struct mlx5_ib_dev *dev) 6868 { 6869 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 6870 6871 mlx5_remove_netdev_notifier(dev, port_num); 6872 } 6873 6874 static int mlx5_ib_stage_raw_eth_roce_init(struct mlx5_ib_dev *dev) 6875 { 6876 struct mlx5_core_dev *mdev = dev->mdev; 6877 enum rdma_link_layer ll; 6878 int port_type_cap; 6879 int err = 0; 6880 6881 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 6882 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 6883 6884 if (ll == IB_LINK_LAYER_ETHERNET) 6885 err = mlx5_ib_stage_common_roce_init(dev); 6886 6887 return err; 6888 } 6889 6890 static void mlx5_ib_stage_raw_eth_roce_cleanup(struct mlx5_ib_dev *dev) 6891 { 6892 mlx5_ib_stage_common_roce_cleanup(dev); 6893 } 6894 6895 static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev) 6896 { 6897 struct mlx5_core_dev *mdev = dev->mdev; 6898 enum rdma_link_layer ll; 6899 int port_type_cap; 6900 int err; 6901 6902 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 6903 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 6904 6905 if (ll == IB_LINK_LAYER_ETHERNET) { 6906 err = mlx5_ib_stage_common_roce_init(dev); 6907 if (err) 6908 return err; 6909 6910 err = mlx5_enable_eth(dev); 6911 if (err) 6912 goto cleanup; 6913 } 6914 6915 return 0; 6916 cleanup: 6917 mlx5_ib_stage_common_roce_cleanup(dev); 6918 6919 return err; 6920 } 6921 6922 static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev) 6923 { 6924 struct mlx5_core_dev *mdev = dev->mdev; 6925 enum rdma_link_layer ll; 6926 int port_type_cap; 6927 6928 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 6929 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 6930 6931 if (ll == IB_LINK_LAYER_ETHERNET) { 6932 mlx5_disable_eth(dev); 6933 mlx5_ib_stage_common_roce_cleanup(dev); 6934 } 6935 } 6936 6937 static int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev) 6938 { 6939 return create_dev_resources(&dev->devr); 6940 } 6941 6942 static void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev) 6943 { 6944 destroy_dev_resources(&dev->devr); 6945 } 6946 6947 static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev) 6948 { 6949 return mlx5_ib_odp_init_one(dev); 6950 } 6951 6952 static void mlx5_ib_stage_odp_cleanup(struct mlx5_ib_dev *dev) 6953 { 6954 mlx5_ib_odp_cleanup_one(dev); 6955 } 6956 6957 static const struct ib_device_ops mlx5_ib_dev_hw_stats_ops = { 6958 .alloc_hw_stats = mlx5_ib_alloc_hw_stats, 6959 .get_hw_stats = mlx5_ib_get_hw_stats, 6960 .counter_bind_qp = mlx5_ib_counter_bind_qp, 6961 .counter_unbind_qp = mlx5_ib_counter_unbind_qp, 6962 .counter_dealloc = mlx5_ib_counter_dealloc, 6963 .counter_alloc_stats = mlx5_ib_counter_alloc_stats, 6964 .counter_update_stats = mlx5_ib_counter_update_stats, 6965 }; 6966 6967 static int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev) 6968 { 6969 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) { 6970 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_hw_stats_ops); 6971 6972 return mlx5_ib_alloc_counters(dev); 6973 } 6974 6975 return 0; 6976 } 6977 6978 static void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev) 6979 { 6980 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) 6981 mlx5_ib_dealloc_counters(dev); 6982 } 6983 6984 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev) 6985 { 6986 mlx5_ib_init_cong_debugfs(dev, 6987 mlx5_core_native_port_num(dev->mdev) - 1); 6988 return 0; 6989 } 6990 6991 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev) 6992 { 6993 mlx5_ib_cleanup_cong_debugfs(dev, 6994 mlx5_core_native_port_num(dev->mdev) - 1); 6995 } 6996 6997 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev) 6998 { 6999 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev); 7000 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar); 7001 } 7002 7003 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev) 7004 { 7005 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar); 7006 } 7007 7008 static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev) 7009 { 7010 int err; 7011 7012 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false); 7013 if (err) 7014 return err; 7015 7016 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true); 7017 if (err) 7018 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 7019 7020 return err; 7021 } 7022 7023 static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev) 7024 { 7025 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 7026 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 7027 } 7028 7029 static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev) 7030 { 7031 const char *name; 7032 7033 rdma_set_device_sysfs_group(&dev->ib_dev, &mlx5_attr_group); 7034 if (!mlx5_lag_is_roce(dev->mdev)) 7035 name = "mlx5_%d"; 7036 else 7037 name = "mlx5_bond_%d"; 7038 return ib_register_device(&dev->ib_dev, name); 7039 } 7040 7041 static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev) 7042 { 7043 destroy_umrc_res(dev); 7044 } 7045 7046 static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev) 7047 { 7048 ib_unregister_device(&dev->ib_dev); 7049 } 7050 7051 static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev) 7052 { 7053 return create_umr_res(dev); 7054 } 7055 7056 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev) 7057 { 7058 init_delay_drop(dev); 7059 7060 return 0; 7061 } 7062 7063 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev) 7064 { 7065 cancel_delay_drop(dev); 7066 } 7067 7068 static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev) 7069 { 7070 dev->mdev_events.notifier_call = mlx5_ib_event; 7071 mlx5_notifier_register(dev->mdev, &dev->mdev_events); 7072 return 0; 7073 } 7074 7075 static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev) 7076 { 7077 mlx5_notifier_unregister(dev->mdev, &dev->mdev_events); 7078 } 7079 7080 static int mlx5_ib_stage_devx_init(struct mlx5_ib_dev *dev) 7081 { 7082 int uid; 7083 7084 uid = mlx5_ib_devx_create(dev, false); 7085 if (uid > 0) { 7086 dev->devx_whitelist_uid = uid; 7087 mlx5_ib_devx_init_event_table(dev); 7088 } 7089 7090 return 0; 7091 } 7092 static void mlx5_ib_stage_devx_cleanup(struct mlx5_ib_dev *dev) 7093 { 7094 if (dev->devx_whitelist_uid) { 7095 mlx5_ib_devx_cleanup_event_table(dev); 7096 mlx5_ib_devx_destroy(dev, dev->devx_whitelist_uid); 7097 } 7098 } 7099 7100 int mlx5_ib_enable_driver(struct ib_device *dev) 7101 { 7102 struct mlx5_ib_dev *mdev = to_mdev(dev); 7103 int ret; 7104 7105 ret = mlx5_ib_test_wc(mdev); 7106 mlx5_ib_dbg(mdev, "Write-Combining %s", 7107 mdev->wc_support ? "supported" : "not supported"); 7108 7109 return ret; 7110 } 7111 7112 void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 7113 const struct mlx5_ib_profile *profile, 7114 int stage) 7115 { 7116 dev->ib_active = false; 7117 7118 /* Number of stages to cleanup */ 7119 while (stage) { 7120 stage--; 7121 if (profile->stage[stage].cleanup) 7122 profile->stage[stage].cleanup(dev); 7123 } 7124 7125 kfree(dev->port); 7126 ib_dealloc_device(&dev->ib_dev); 7127 } 7128 7129 void *__mlx5_ib_add(struct mlx5_ib_dev *dev, 7130 const struct mlx5_ib_profile *profile) 7131 { 7132 int err; 7133 int i; 7134 7135 dev->profile = profile; 7136 7137 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) { 7138 if (profile->stage[i].init) { 7139 err = profile->stage[i].init(dev); 7140 if (err) 7141 goto err_out; 7142 } 7143 } 7144 7145 dev->ib_active = true; 7146 7147 return dev; 7148 7149 err_out: 7150 __mlx5_ib_remove(dev, profile, i); 7151 7152 return NULL; 7153 } 7154 7155 static const struct mlx5_ib_profile pf_profile = { 7156 STAGE_CREATE(MLX5_IB_STAGE_INIT, 7157 mlx5_ib_stage_init_init, 7158 mlx5_ib_stage_init_cleanup), 7159 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB, 7160 mlx5_ib_stage_flow_db_init, 7161 mlx5_ib_stage_flow_db_cleanup), 7162 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 7163 mlx5_ib_stage_caps_init, 7164 mlx5_ib_stage_caps_cleanup), 7165 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 7166 mlx5_ib_stage_non_default_cb, 7167 NULL), 7168 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 7169 mlx5_ib_stage_roce_init, 7170 mlx5_ib_stage_roce_cleanup), 7171 STAGE_CREATE(MLX5_IB_STAGE_QP, 7172 mlx5_init_qp_table, 7173 mlx5_cleanup_qp_table), 7174 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 7175 mlx5_init_srq_table, 7176 mlx5_cleanup_srq_table), 7177 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 7178 mlx5_ib_stage_dev_res_init, 7179 mlx5_ib_stage_dev_res_cleanup), 7180 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 7181 mlx5_ib_stage_dev_notifier_init, 7182 mlx5_ib_stage_dev_notifier_cleanup), 7183 STAGE_CREATE(MLX5_IB_STAGE_ODP, 7184 mlx5_ib_stage_odp_init, 7185 mlx5_ib_stage_odp_cleanup), 7186 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 7187 mlx5_ib_stage_counters_init, 7188 mlx5_ib_stage_counters_cleanup), 7189 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 7190 mlx5_ib_stage_cong_debugfs_init, 7191 mlx5_ib_stage_cong_debugfs_cleanup), 7192 STAGE_CREATE(MLX5_IB_STAGE_UAR, 7193 mlx5_ib_stage_uar_init, 7194 mlx5_ib_stage_uar_cleanup), 7195 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 7196 mlx5_ib_stage_bfrag_init, 7197 mlx5_ib_stage_bfrag_cleanup), 7198 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 7199 NULL, 7200 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 7201 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 7202 mlx5_ib_stage_devx_init, 7203 mlx5_ib_stage_devx_cleanup), 7204 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 7205 mlx5_ib_stage_ib_reg_init, 7206 mlx5_ib_stage_ib_reg_cleanup), 7207 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 7208 mlx5_ib_stage_post_ib_reg_umr_init, 7209 NULL), 7210 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP, 7211 mlx5_ib_stage_delay_drop_init, 7212 mlx5_ib_stage_delay_drop_cleanup), 7213 }; 7214 7215 const struct mlx5_ib_profile raw_eth_profile = { 7216 STAGE_CREATE(MLX5_IB_STAGE_INIT, 7217 mlx5_ib_stage_init_init, 7218 mlx5_ib_stage_init_cleanup), 7219 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB, 7220 mlx5_ib_stage_flow_db_init, 7221 mlx5_ib_stage_flow_db_cleanup), 7222 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 7223 mlx5_ib_stage_caps_init, 7224 mlx5_ib_stage_caps_cleanup), 7225 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 7226 mlx5_ib_stage_raw_eth_non_default_cb, 7227 NULL), 7228 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 7229 mlx5_ib_stage_raw_eth_roce_init, 7230 mlx5_ib_stage_raw_eth_roce_cleanup), 7231 STAGE_CREATE(MLX5_IB_STAGE_QP, 7232 mlx5_init_qp_table, 7233 mlx5_cleanup_qp_table), 7234 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 7235 mlx5_init_srq_table, 7236 mlx5_cleanup_srq_table), 7237 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 7238 mlx5_ib_stage_dev_res_init, 7239 mlx5_ib_stage_dev_res_cleanup), 7240 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 7241 mlx5_ib_stage_dev_notifier_init, 7242 mlx5_ib_stage_dev_notifier_cleanup), 7243 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 7244 mlx5_ib_stage_counters_init, 7245 mlx5_ib_stage_counters_cleanup), 7246 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 7247 mlx5_ib_stage_cong_debugfs_init, 7248 mlx5_ib_stage_cong_debugfs_cleanup), 7249 STAGE_CREATE(MLX5_IB_STAGE_UAR, 7250 mlx5_ib_stage_uar_init, 7251 mlx5_ib_stage_uar_cleanup), 7252 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 7253 mlx5_ib_stage_bfrag_init, 7254 mlx5_ib_stage_bfrag_cleanup), 7255 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 7256 NULL, 7257 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 7258 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 7259 mlx5_ib_stage_devx_init, 7260 mlx5_ib_stage_devx_cleanup), 7261 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 7262 mlx5_ib_stage_ib_reg_init, 7263 mlx5_ib_stage_ib_reg_cleanup), 7264 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 7265 mlx5_ib_stage_post_ib_reg_umr_init, 7266 NULL), 7267 }; 7268 7269 static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev) 7270 { 7271 struct mlx5_ib_multiport_info *mpi; 7272 struct mlx5_ib_dev *dev; 7273 bool bound = false; 7274 int err; 7275 7276 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 7277 if (!mpi) 7278 return NULL; 7279 7280 mpi->mdev = mdev; 7281 7282 err = mlx5_query_nic_vport_system_image_guid(mdev, 7283 &mpi->sys_image_guid); 7284 if (err) { 7285 kfree(mpi); 7286 return NULL; 7287 } 7288 7289 mutex_lock(&mlx5_ib_multiport_mutex); 7290 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) { 7291 if (dev->sys_image_guid == mpi->sys_image_guid) 7292 bound = mlx5_ib_bind_slave_port(dev, mpi); 7293 7294 if (bound) { 7295 rdma_roce_rescan_device(&dev->ib_dev); 7296 break; 7297 } 7298 } 7299 7300 if (!bound) { 7301 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 7302 dev_dbg(mdev->device, 7303 "no suitable IB device found to bind to, added to unaffiliated list.\n"); 7304 } 7305 mutex_unlock(&mlx5_ib_multiport_mutex); 7306 7307 return mpi; 7308 } 7309 7310 static void *mlx5_ib_add(struct mlx5_core_dev *mdev) 7311 { 7312 const struct mlx5_ib_profile *profile; 7313 enum rdma_link_layer ll; 7314 struct mlx5_ib_dev *dev; 7315 int port_type_cap; 7316 int num_ports; 7317 7318 printk_once(KERN_INFO "%s", mlx5_version); 7319 7320 if (MLX5_ESWITCH_MANAGER(mdev) && 7321 mlx5_ib_eswitch_mode(mdev->priv.eswitch) == MLX5_ESWITCH_OFFLOADS) { 7322 if (!mlx5_core_mp_enabled(mdev)) 7323 mlx5_ib_register_vport_reps(mdev); 7324 return mdev; 7325 } 7326 7327 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 7328 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 7329 7330 if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET) 7331 return mlx5_ib_add_slave_port(mdev); 7332 7333 num_ports = max(MLX5_CAP_GEN(mdev, num_ports), 7334 MLX5_CAP_GEN(mdev, num_vhca_ports)); 7335 dev = ib_alloc_device(mlx5_ib_dev, ib_dev); 7336 if (!dev) 7337 return NULL; 7338 dev->port = kcalloc(num_ports, sizeof(*dev->port), 7339 GFP_KERNEL); 7340 if (!dev->port) { 7341 ib_dealloc_device(&dev->ib_dev); 7342 return NULL; 7343 } 7344 7345 dev->mdev = mdev; 7346 dev->num_ports = num_ports; 7347 7348 if (ll == IB_LINK_LAYER_ETHERNET && !mlx5_is_roce_enabled(mdev)) 7349 profile = &raw_eth_profile; 7350 else 7351 profile = &pf_profile; 7352 7353 return __mlx5_ib_add(dev, profile); 7354 } 7355 7356 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context) 7357 { 7358 struct mlx5_ib_multiport_info *mpi; 7359 struct mlx5_ib_dev *dev; 7360 7361 if (MLX5_ESWITCH_MANAGER(mdev) && context == mdev) { 7362 mlx5_ib_unregister_vport_reps(mdev); 7363 return; 7364 } 7365 7366 if (mlx5_core_is_mp_slave(mdev)) { 7367 mpi = context; 7368 mutex_lock(&mlx5_ib_multiport_mutex); 7369 if (mpi->ibdev) 7370 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi); 7371 list_del(&mpi->list); 7372 mutex_unlock(&mlx5_ib_multiport_mutex); 7373 kfree(mpi); 7374 return; 7375 } 7376 7377 dev = context; 7378 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX); 7379 } 7380 7381 static struct mlx5_interface mlx5_ib_interface = { 7382 .add = mlx5_ib_add, 7383 .remove = mlx5_ib_remove, 7384 .protocol = MLX5_INTERFACE_PROTOCOL_IB, 7385 }; 7386 7387 unsigned long mlx5_ib_get_xlt_emergency_page(void) 7388 { 7389 mutex_lock(&xlt_emergency_page_mutex); 7390 return xlt_emergency_page; 7391 } 7392 7393 void mlx5_ib_put_xlt_emergency_page(void) 7394 { 7395 mutex_unlock(&xlt_emergency_page_mutex); 7396 } 7397 7398 static int __init mlx5_ib_init(void) 7399 { 7400 int err; 7401 7402 xlt_emergency_page = __get_free_page(GFP_KERNEL); 7403 if (!xlt_emergency_page) 7404 return -ENOMEM; 7405 7406 mutex_init(&xlt_emergency_page_mutex); 7407 7408 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0); 7409 if (!mlx5_ib_event_wq) { 7410 free_page(xlt_emergency_page); 7411 return -ENOMEM; 7412 } 7413 7414 mlx5_ib_odp_init(); 7415 7416 err = mlx5_register_interface(&mlx5_ib_interface); 7417 7418 return err; 7419 } 7420 7421 static void __exit mlx5_ib_cleanup(void) 7422 { 7423 mlx5_unregister_interface(&mlx5_ib_interface); 7424 destroy_workqueue(mlx5_ib_event_wq); 7425 mutex_destroy(&xlt_emergency_page_mutex); 7426 free_page(xlt_emergency_page); 7427 } 7428 7429 module_init(mlx5_ib_init); 7430 module_exit(mlx5_ib_cleanup); 7431