1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 /* 3 * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved. 4 * Copyright (c) 2020, Intel Corporation. All rights reserved. 5 */ 6 7 #include <linux/debugfs.h> 8 #include <linux/highmem.h> 9 #include <linux/module.h> 10 #include <linux/init.h> 11 #include <linux/errno.h> 12 #include <linux/pci.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/slab.h> 15 #include <linux/bitmap.h> 16 #include <linux/sched.h> 17 #include <linux/sched/mm.h> 18 #include <linux/sched/task.h> 19 #include <linux/delay.h> 20 #include <rdma/ib_user_verbs.h> 21 #include <rdma/ib_addr.h> 22 #include <rdma/ib_cache.h> 23 #include <linux/mlx5/port.h> 24 #include <linux/mlx5/vport.h> 25 #include <linux/mlx5/fs.h> 26 #include <linux/mlx5/eswitch.h> 27 #include <linux/list.h> 28 #include <rdma/ib_smi.h> 29 #include <rdma/ib_umem.h> 30 #include <rdma/lag.h> 31 #include <linux/in.h> 32 #include <linux/etherdevice.h> 33 #include "mlx5_ib.h" 34 #include "ib_rep.h" 35 #include "cmd.h" 36 #include "devx.h" 37 #include "dm.h" 38 #include "fs.h" 39 #include "srq.h" 40 #include "qp.h" 41 #include "wr.h" 42 #include "restrack.h" 43 #include "counters.h" 44 #include <linux/mlx5/accel.h> 45 #include <rdma/uverbs_std_types.h> 46 #include <rdma/mlx5_user_ioctl_verbs.h> 47 #include <rdma/mlx5_user_ioctl_cmds.h> 48 #include <rdma/ib_umem_odp.h> 49 50 #define UVERBS_MODULE_NAME mlx5_ib 51 #include <rdma/uverbs_named_ioctl.h> 52 53 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 54 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) IB driver"); 55 MODULE_LICENSE("Dual BSD/GPL"); 56 57 struct mlx5_ib_event_work { 58 struct work_struct work; 59 union { 60 struct mlx5_ib_dev *dev; 61 struct mlx5_ib_multiport_info *mpi; 62 }; 63 bool is_slave; 64 unsigned int event; 65 void *param; 66 }; 67 68 enum { 69 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 70 }; 71 72 static struct workqueue_struct *mlx5_ib_event_wq; 73 static LIST_HEAD(mlx5_ib_unaffiliated_port_list); 74 static LIST_HEAD(mlx5_ib_dev_list); 75 /* 76 * This mutex should be held when accessing either of the above lists 77 */ 78 static DEFINE_MUTEX(mlx5_ib_multiport_mutex); 79 80 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi) 81 { 82 struct mlx5_ib_dev *dev; 83 84 mutex_lock(&mlx5_ib_multiport_mutex); 85 dev = mpi->ibdev; 86 mutex_unlock(&mlx5_ib_multiport_mutex); 87 return dev; 88 } 89 90 static enum rdma_link_layer 91 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 92 { 93 switch (port_type_cap) { 94 case MLX5_CAP_PORT_TYPE_IB: 95 return IB_LINK_LAYER_INFINIBAND; 96 case MLX5_CAP_PORT_TYPE_ETH: 97 return IB_LINK_LAYER_ETHERNET; 98 default: 99 return IB_LINK_LAYER_UNSPECIFIED; 100 } 101 } 102 103 static enum rdma_link_layer 104 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num) 105 { 106 struct mlx5_ib_dev *dev = to_mdev(device); 107 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 108 109 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 110 } 111 112 static int get_port_state(struct ib_device *ibdev, 113 u8 port_num, 114 enum ib_port_state *state) 115 { 116 struct ib_port_attr attr; 117 int ret; 118 119 memset(&attr, 0, sizeof(attr)); 120 ret = ibdev->ops.query_port(ibdev, port_num, &attr); 121 if (!ret) 122 *state = attr.state; 123 return ret; 124 } 125 126 static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev, 127 struct net_device *ndev, 128 u8 *port_num) 129 { 130 struct net_device *rep_ndev; 131 struct mlx5_ib_port *port; 132 int i; 133 134 for (i = 0; i < dev->num_ports; i++) { 135 port = &dev->port[i]; 136 if (!port->rep) 137 continue; 138 139 read_lock(&port->roce.netdev_lock); 140 rep_ndev = mlx5_ib_get_rep_netdev(port->rep->esw, 141 port->rep->vport); 142 if (rep_ndev == ndev) { 143 read_unlock(&port->roce.netdev_lock); 144 *port_num = i + 1; 145 return &port->roce; 146 } 147 read_unlock(&port->roce.netdev_lock); 148 } 149 150 return NULL; 151 } 152 153 static int mlx5_netdev_event(struct notifier_block *this, 154 unsigned long event, void *ptr) 155 { 156 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb); 157 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 158 u8 port_num = roce->native_port_num; 159 struct mlx5_core_dev *mdev; 160 struct mlx5_ib_dev *ibdev; 161 162 ibdev = roce->dev; 163 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 164 if (!mdev) 165 return NOTIFY_DONE; 166 167 switch (event) { 168 case NETDEV_REGISTER: 169 /* Should already be registered during the load */ 170 if (ibdev->is_rep) 171 break; 172 write_lock(&roce->netdev_lock); 173 if (ndev->dev.parent == mdev->device) 174 roce->netdev = ndev; 175 write_unlock(&roce->netdev_lock); 176 break; 177 178 case NETDEV_UNREGISTER: 179 /* In case of reps, ib device goes away before the netdevs */ 180 write_lock(&roce->netdev_lock); 181 if (roce->netdev == ndev) 182 roce->netdev = NULL; 183 write_unlock(&roce->netdev_lock); 184 break; 185 186 case NETDEV_CHANGE: 187 case NETDEV_UP: 188 case NETDEV_DOWN: { 189 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev); 190 struct net_device *upper = NULL; 191 192 if (lag_ndev) { 193 upper = netdev_master_upper_dev_get(lag_ndev); 194 dev_put(lag_ndev); 195 } 196 197 if (ibdev->is_rep) 198 roce = mlx5_get_rep_roce(ibdev, ndev, &port_num); 199 if (!roce) 200 return NOTIFY_DONE; 201 if ((upper == ndev || (!upper && ndev == roce->netdev)) 202 && ibdev->ib_active) { 203 struct ib_event ibev = { }; 204 enum ib_port_state port_state; 205 206 if (get_port_state(&ibdev->ib_dev, port_num, 207 &port_state)) 208 goto done; 209 210 if (roce->last_port_state == port_state) 211 goto done; 212 213 roce->last_port_state = port_state; 214 ibev.device = &ibdev->ib_dev; 215 if (port_state == IB_PORT_DOWN) 216 ibev.event = IB_EVENT_PORT_ERR; 217 else if (port_state == IB_PORT_ACTIVE) 218 ibev.event = IB_EVENT_PORT_ACTIVE; 219 else 220 goto done; 221 222 ibev.element.port_num = port_num; 223 ib_dispatch_event(&ibev); 224 } 225 break; 226 } 227 228 default: 229 break; 230 } 231 done: 232 mlx5_ib_put_native_port_mdev(ibdev, port_num); 233 return NOTIFY_DONE; 234 } 235 236 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device, 237 u8 port_num) 238 { 239 struct mlx5_ib_dev *ibdev = to_mdev(device); 240 struct net_device *ndev; 241 struct mlx5_core_dev *mdev; 242 243 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 244 if (!mdev) 245 return NULL; 246 247 ndev = mlx5_lag_get_roce_netdev(mdev); 248 if (ndev) 249 goto out; 250 251 /* Ensure ndev does not disappear before we invoke dev_hold() 252 */ 253 read_lock(&ibdev->port[port_num - 1].roce.netdev_lock); 254 ndev = ibdev->port[port_num - 1].roce.netdev; 255 if (ndev) 256 dev_hold(ndev); 257 read_unlock(&ibdev->port[port_num - 1].roce.netdev_lock); 258 259 out: 260 mlx5_ib_put_native_port_mdev(ibdev, port_num); 261 return ndev; 262 } 263 264 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev, 265 u8 ib_port_num, 266 u8 *native_port_num) 267 { 268 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 269 ib_port_num); 270 struct mlx5_core_dev *mdev = NULL; 271 struct mlx5_ib_multiport_info *mpi; 272 struct mlx5_ib_port *port; 273 274 if (!mlx5_core_mp_enabled(ibdev->mdev) || 275 ll != IB_LINK_LAYER_ETHERNET) { 276 if (native_port_num) 277 *native_port_num = ib_port_num; 278 return ibdev->mdev; 279 } 280 281 if (native_port_num) 282 *native_port_num = 1; 283 284 port = &ibdev->port[ib_port_num - 1]; 285 spin_lock(&port->mp.mpi_lock); 286 mpi = ibdev->port[ib_port_num - 1].mp.mpi; 287 if (mpi && !mpi->unaffiliate) { 288 mdev = mpi->mdev; 289 /* If it's the master no need to refcount, it'll exist 290 * as long as the ib_dev exists. 291 */ 292 if (!mpi->is_master) 293 mpi->mdev_refcnt++; 294 } 295 spin_unlock(&port->mp.mpi_lock); 296 297 return mdev; 298 } 299 300 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num) 301 { 302 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 303 port_num); 304 struct mlx5_ib_multiport_info *mpi; 305 struct mlx5_ib_port *port; 306 307 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 308 return; 309 310 port = &ibdev->port[port_num - 1]; 311 312 spin_lock(&port->mp.mpi_lock); 313 mpi = ibdev->port[port_num - 1].mp.mpi; 314 if (mpi->is_master) 315 goto out; 316 317 mpi->mdev_refcnt--; 318 if (mpi->unaffiliate) 319 complete(&mpi->unref_comp); 320 out: 321 spin_unlock(&port->mp.mpi_lock); 322 } 323 324 static int translate_eth_legacy_proto_oper(u32 eth_proto_oper, 325 u16 *active_speed, u8 *active_width) 326 { 327 switch (eth_proto_oper) { 328 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII): 329 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX): 330 case MLX5E_PROT_MASK(MLX5E_100BASE_TX): 331 case MLX5E_PROT_MASK(MLX5E_1000BASE_T): 332 *active_width = IB_WIDTH_1X; 333 *active_speed = IB_SPEED_SDR; 334 break; 335 case MLX5E_PROT_MASK(MLX5E_10GBASE_T): 336 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4): 337 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4): 338 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR): 339 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR): 340 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR): 341 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER): 342 *active_width = IB_WIDTH_1X; 343 *active_speed = IB_SPEED_QDR; 344 break; 345 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR): 346 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR): 347 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR): 348 *active_width = IB_WIDTH_1X; 349 *active_speed = IB_SPEED_EDR; 350 break; 351 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4): 352 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4): 353 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4): 354 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4): 355 *active_width = IB_WIDTH_4X; 356 *active_speed = IB_SPEED_QDR; 357 break; 358 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2): 359 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2): 360 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2): 361 *active_width = IB_WIDTH_1X; 362 *active_speed = IB_SPEED_HDR; 363 break; 364 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4): 365 *active_width = IB_WIDTH_4X; 366 *active_speed = IB_SPEED_FDR; 367 break; 368 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4): 369 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4): 370 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4): 371 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4): 372 *active_width = IB_WIDTH_4X; 373 *active_speed = IB_SPEED_EDR; 374 break; 375 default: 376 return -EINVAL; 377 } 378 379 return 0; 380 } 381 382 static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u16 *active_speed, 383 u8 *active_width) 384 { 385 switch (eth_proto_oper) { 386 case MLX5E_PROT_MASK(MLX5E_SGMII_100M): 387 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII): 388 *active_width = IB_WIDTH_1X; 389 *active_speed = IB_SPEED_SDR; 390 break; 391 case MLX5E_PROT_MASK(MLX5E_5GBASE_R): 392 *active_width = IB_WIDTH_1X; 393 *active_speed = IB_SPEED_DDR; 394 break; 395 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1): 396 *active_width = IB_WIDTH_1X; 397 *active_speed = IB_SPEED_QDR; 398 break; 399 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4): 400 *active_width = IB_WIDTH_4X; 401 *active_speed = IB_SPEED_QDR; 402 break; 403 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR): 404 *active_width = IB_WIDTH_1X; 405 *active_speed = IB_SPEED_EDR; 406 break; 407 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2): 408 *active_width = IB_WIDTH_2X; 409 *active_speed = IB_SPEED_EDR; 410 break; 411 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR): 412 *active_width = IB_WIDTH_1X; 413 *active_speed = IB_SPEED_HDR; 414 break; 415 case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4): 416 *active_width = IB_WIDTH_4X; 417 *active_speed = IB_SPEED_EDR; 418 break; 419 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2): 420 *active_width = IB_WIDTH_2X; 421 *active_speed = IB_SPEED_HDR; 422 break; 423 case MLX5E_PROT_MASK(MLX5E_100GAUI_1_100GBASE_CR_KR): 424 *active_width = IB_WIDTH_1X; 425 *active_speed = IB_SPEED_NDR; 426 break; 427 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4): 428 *active_width = IB_WIDTH_4X; 429 *active_speed = IB_SPEED_HDR; 430 break; 431 case MLX5E_PROT_MASK(MLX5E_200GAUI_2_200GBASE_CR2_KR2): 432 *active_width = IB_WIDTH_2X; 433 *active_speed = IB_SPEED_NDR; 434 break; 435 case MLX5E_PROT_MASK(MLX5E_400GAUI_4_400GBASE_CR4_KR4): 436 *active_width = IB_WIDTH_4X; 437 *active_speed = IB_SPEED_NDR; 438 break; 439 default: 440 return -EINVAL; 441 } 442 443 return 0; 444 } 445 446 static int translate_eth_proto_oper(u32 eth_proto_oper, u16 *active_speed, 447 u8 *active_width, bool ext) 448 { 449 return ext ? 450 translate_eth_ext_proto_oper(eth_proto_oper, active_speed, 451 active_width) : 452 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed, 453 active_width); 454 } 455 456 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num, 457 struct ib_port_attr *props) 458 { 459 struct mlx5_ib_dev *dev = to_mdev(device); 460 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0}; 461 struct mlx5_core_dev *mdev; 462 struct net_device *ndev, *upper; 463 enum ib_mtu ndev_ib_mtu; 464 bool put_mdev = true; 465 u32 eth_prot_oper; 466 u8 mdev_port_num; 467 bool ext; 468 int err; 469 470 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 471 if (!mdev) { 472 /* This means the port isn't affiliated yet. Get the 473 * info for the master port instead. 474 */ 475 put_mdev = false; 476 mdev = dev->mdev; 477 mdev_port_num = 1; 478 port_num = 1; 479 } 480 481 /* Possible bad flows are checked before filling out props so in case 482 * of an error it will still be zeroed out. 483 * Use native port in case of reps 484 */ 485 if (dev->is_rep) 486 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 487 1); 488 else 489 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 490 mdev_port_num); 491 if (err) 492 goto out; 493 ext = !!MLX5_GET_ETH_PROTO(ptys_reg, out, true, eth_proto_capability); 494 eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper); 495 496 props->active_width = IB_WIDTH_4X; 497 props->active_speed = IB_SPEED_QDR; 498 499 translate_eth_proto_oper(eth_prot_oper, &props->active_speed, 500 &props->active_width, ext); 501 502 if (!dev->is_rep && mlx5_is_roce_enabled(mdev)) { 503 u16 qkey_viol_cntr; 504 505 props->port_cap_flags |= IB_PORT_CM_SUP; 506 props->ip_gids = true; 507 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 508 roce_address_table_size); 509 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr); 510 props->qkey_viol_cntr = qkey_viol_cntr; 511 } 512 props->max_mtu = IB_MTU_4096; 513 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 514 props->pkey_tbl_len = 1; 515 props->state = IB_PORT_DOWN; 516 props->phys_state = IB_PORT_PHYS_STATE_DISABLED; 517 518 /* If this is a stub query for an unaffiliated port stop here */ 519 if (!put_mdev) 520 goto out; 521 522 ndev = mlx5_ib_get_netdev(device, port_num); 523 if (!ndev) 524 goto out; 525 526 if (dev->lag_active) { 527 rcu_read_lock(); 528 upper = netdev_master_upper_dev_get_rcu(ndev); 529 if (upper) { 530 dev_put(ndev); 531 ndev = upper; 532 dev_hold(ndev); 533 } 534 rcu_read_unlock(); 535 } 536 537 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 538 props->state = IB_PORT_ACTIVE; 539 props->phys_state = IB_PORT_PHYS_STATE_LINK_UP; 540 } 541 542 ndev_ib_mtu = iboe_get_mtu(ndev->mtu); 543 544 dev_put(ndev); 545 546 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 547 out: 548 if (put_mdev) 549 mlx5_ib_put_native_port_mdev(dev, port_num); 550 return err; 551 } 552 553 static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num, 554 unsigned int index, const union ib_gid *gid, 555 const struct ib_gid_attr *attr) 556 { 557 enum ib_gid_type gid_type = IB_GID_TYPE_ROCE; 558 u16 vlan_id = 0xffff; 559 u8 roce_version = 0; 560 u8 roce_l3_type = 0; 561 u8 mac[ETH_ALEN]; 562 int ret; 563 564 if (gid) { 565 gid_type = attr->gid_type; 566 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]); 567 if (ret) 568 return ret; 569 } 570 571 switch (gid_type) { 572 case IB_GID_TYPE_ROCE: 573 roce_version = MLX5_ROCE_VERSION_1; 574 break; 575 case IB_GID_TYPE_ROCE_UDP_ENCAP: 576 roce_version = MLX5_ROCE_VERSION_2; 577 if (ipv6_addr_v4mapped((void *)gid)) 578 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4; 579 else 580 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6; 581 break; 582 583 default: 584 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type); 585 } 586 587 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version, 588 roce_l3_type, gid->raw, mac, 589 vlan_id < VLAN_CFI_MASK, vlan_id, 590 port_num); 591 } 592 593 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr, 594 __always_unused void **context) 595 { 596 return set_roce_addr(to_mdev(attr->device), attr->port_num, 597 attr->index, &attr->gid, attr); 598 } 599 600 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr, 601 __always_unused void **context) 602 { 603 return set_roce_addr(to_mdev(attr->device), attr->port_num, 604 attr->index, NULL, NULL); 605 } 606 607 __be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev, 608 const struct ib_gid_attr *attr) 609 { 610 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 611 return 0; 612 613 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 614 } 615 616 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 617 { 618 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 619 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 620 return 0; 621 } 622 623 enum { 624 MLX5_VPORT_ACCESS_METHOD_MAD, 625 MLX5_VPORT_ACCESS_METHOD_HCA, 626 MLX5_VPORT_ACCESS_METHOD_NIC, 627 }; 628 629 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 630 { 631 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 632 return MLX5_VPORT_ACCESS_METHOD_MAD; 633 634 if (mlx5_ib_port_link_layer(ibdev, 1) == 635 IB_LINK_LAYER_ETHERNET) 636 return MLX5_VPORT_ACCESS_METHOD_NIC; 637 638 return MLX5_VPORT_ACCESS_METHOD_HCA; 639 } 640 641 static void get_atomic_caps(struct mlx5_ib_dev *dev, 642 u8 atomic_size_qp, 643 struct ib_device_attr *props) 644 { 645 u8 tmp; 646 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 647 u8 atomic_req_8B_endianness_mode = 648 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode); 649 650 /* Check if HW supports 8 bytes standard atomic operations and capable 651 * of host endianness respond 652 */ 653 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 654 if (((atomic_operations & tmp) == tmp) && 655 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 656 (atomic_req_8B_endianness_mode)) { 657 props->atomic_cap = IB_ATOMIC_HCA; 658 } else { 659 props->atomic_cap = IB_ATOMIC_NONE; 660 } 661 } 662 663 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev, 664 struct ib_device_attr *props) 665 { 666 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 667 668 get_atomic_caps(dev, atomic_size_qp, props); 669 } 670 671 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 672 __be64 *sys_image_guid) 673 { 674 struct mlx5_ib_dev *dev = to_mdev(ibdev); 675 struct mlx5_core_dev *mdev = dev->mdev; 676 u64 tmp; 677 int err; 678 679 switch (mlx5_get_vport_access_method(ibdev)) { 680 case MLX5_VPORT_ACCESS_METHOD_MAD: 681 return mlx5_query_mad_ifc_system_image_guid(ibdev, 682 sys_image_guid); 683 684 case MLX5_VPORT_ACCESS_METHOD_HCA: 685 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 686 break; 687 688 case MLX5_VPORT_ACCESS_METHOD_NIC: 689 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 690 break; 691 692 default: 693 return -EINVAL; 694 } 695 696 if (!err) 697 *sys_image_guid = cpu_to_be64(tmp); 698 699 return err; 700 701 } 702 703 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 704 u16 *max_pkeys) 705 { 706 struct mlx5_ib_dev *dev = to_mdev(ibdev); 707 struct mlx5_core_dev *mdev = dev->mdev; 708 709 switch (mlx5_get_vport_access_method(ibdev)) { 710 case MLX5_VPORT_ACCESS_METHOD_MAD: 711 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 712 713 case MLX5_VPORT_ACCESS_METHOD_HCA: 714 case MLX5_VPORT_ACCESS_METHOD_NIC: 715 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 716 pkey_table_size)); 717 return 0; 718 719 default: 720 return -EINVAL; 721 } 722 } 723 724 static int mlx5_query_vendor_id(struct ib_device *ibdev, 725 u32 *vendor_id) 726 { 727 struct mlx5_ib_dev *dev = to_mdev(ibdev); 728 729 switch (mlx5_get_vport_access_method(ibdev)) { 730 case MLX5_VPORT_ACCESS_METHOD_MAD: 731 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 732 733 case MLX5_VPORT_ACCESS_METHOD_HCA: 734 case MLX5_VPORT_ACCESS_METHOD_NIC: 735 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 736 737 default: 738 return -EINVAL; 739 } 740 } 741 742 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 743 __be64 *node_guid) 744 { 745 u64 tmp; 746 int err; 747 748 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 749 case MLX5_VPORT_ACCESS_METHOD_MAD: 750 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 751 752 case MLX5_VPORT_ACCESS_METHOD_HCA: 753 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 754 break; 755 756 case MLX5_VPORT_ACCESS_METHOD_NIC: 757 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 758 break; 759 760 default: 761 return -EINVAL; 762 } 763 764 if (!err) 765 *node_guid = cpu_to_be64(tmp); 766 767 return err; 768 } 769 770 struct mlx5_reg_node_desc { 771 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 772 }; 773 774 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 775 { 776 struct mlx5_reg_node_desc in; 777 778 if (mlx5_use_mad_ifc(dev)) 779 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 780 781 memset(&in, 0, sizeof(in)); 782 783 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 784 sizeof(struct mlx5_reg_node_desc), 785 MLX5_REG_NODE_DESC, 0, 0); 786 } 787 788 static int mlx5_ib_query_device(struct ib_device *ibdev, 789 struct ib_device_attr *props, 790 struct ib_udata *uhw) 791 { 792 size_t uhw_outlen = (uhw) ? uhw->outlen : 0; 793 struct mlx5_ib_dev *dev = to_mdev(ibdev); 794 struct mlx5_core_dev *mdev = dev->mdev; 795 int err = -ENOMEM; 796 int max_sq_desc; 797 int max_rq_sg; 798 int max_sq_sg; 799 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 800 bool raw_support = !mlx5_core_mp_enabled(mdev); 801 struct mlx5_ib_query_device_resp resp = {}; 802 size_t resp_len; 803 u64 max_tso; 804 805 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 806 if (uhw_outlen && uhw_outlen < resp_len) 807 return -EINVAL; 808 809 resp.response_length = resp_len; 810 811 if (uhw && uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) 812 return -EINVAL; 813 814 memset(props, 0, sizeof(*props)); 815 err = mlx5_query_system_image_guid(ibdev, 816 &props->sys_image_guid); 817 if (err) 818 return err; 819 820 props->max_pkeys = dev->pkey_table_len; 821 822 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 823 if (err) 824 return err; 825 826 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 827 (fw_rev_min(dev->mdev) << 16) | 828 fw_rev_sub(dev->mdev); 829 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 830 IB_DEVICE_PORT_ACTIVE_EVENT | 831 IB_DEVICE_SYS_IMAGE_GUID | 832 IB_DEVICE_RC_RNR_NAK_GEN; 833 834 if (MLX5_CAP_GEN(mdev, pkv)) 835 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 836 if (MLX5_CAP_GEN(mdev, qkv)) 837 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 838 if (MLX5_CAP_GEN(mdev, apm)) 839 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 840 if (MLX5_CAP_GEN(mdev, xrc)) 841 props->device_cap_flags |= IB_DEVICE_XRC; 842 if (MLX5_CAP_GEN(mdev, imaicl)) { 843 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 844 IB_DEVICE_MEM_WINDOW_TYPE_2B; 845 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 846 /* We support 'Gappy' memory registration too */ 847 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG; 848 } 849 /* IB_WR_REG_MR always requires changing the entity size with UMR */ 850 if (!MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) 851 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 852 if (MLX5_CAP_GEN(mdev, sho)) { 853 props->device_cap_flags |= IB_DEVICE_INTEGRITY_HANDOVER; 854 /* At this stage no support for signature handover */ 855 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 856 IB_PROT_T10DIF_TYPE_2 | 857 IB_PROT_T10DIF_TYPE_3; 858 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 859 IB_GUARD_T10DIF_CSUM; 860 } 861 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 862 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 863 864 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) { 865 if (MLX5_CAP_ETH(mdev, csum_cap)) { 866 /* Legacy bit to support old userspace libraries */ 867 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 868 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM; 869 } 870 871 if (MLX5_CAP_ETH(dev->mdev, vlan_cap)) 872 props->raw_packet_caps |= 873 IB_RAW_PACKET_CAP_CVLAN_STRIPPING; 874 875 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) { 876 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 877 if (max_tso) { 878 resp.tso_caps.max_tso = 1 << max_tso; 879 resp.tso_caps.supported_qpts |= 880 1 << IB_QPT_RAW_PACKET; 881 resp.response_length += sizeof(resp.tso_caps); 882 } 883 } 884 885 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) { 886 resp.rss_caps.rx_hash_function = 887 MLX5_RX_HASH_FUNC_TOEPLITZ; 888 resp.rss_caps.rx_hash_fields_mask = 889 MLX5_RX_HASH_SRC_IPV4 | 890 MLX5_RX_HASH_DST_IPV4 | 891 MLX5_RX_HASH_SRC_IPV6 | 892 MLX5_RX_HASH_DST_IPV6 | 893 MLX5_RX_HASH_SRC_PORT_TCP | 894 MLX5_RX_HASH_DST_PORT_TCP | 895 MLX5_RX_HASH_SRC_PORT_UDP | 896 MLX5_RX_HASH_DST_PORT_UDP | 897 MLX5_RX_HASH_INNER; 898 if (mlx5_accel_ipsec_device_caps(dev->mdev) & 899 MLX5_ACCEL_IPSEC_CAP_DEVICE) 900 resp.rss_caps.rx_hash_fields_mask |= 901 MLX5_RX_HASH_IPSEC_SPI; 902 resp.response_length += sizeof(resp.rss_caps); 903 } 904 } else { 905 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) 906 resp.response_length += sizeof(resp.tso_caps); 907 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) 908 resp.response_length += sizeof(resp.rss_caps); 909 } 910 911 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 912 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 913 props->device_cap_flags |= IB_DEVICE_UD_TSO; 914 } 915 916 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) && 917 MLX5_CAP_GEN(dev->mdev, general_notification_event) && 918 raw_support) 919 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP; 920 921 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 922 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap)) 923 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 924 925 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 926 MLX5_CAP_ETH(dev->mdev, scatter_fcs) && 927 raw_support) { 928 /* Legacy bit to support old userspace libraries */ 929 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 930 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; 931 } 932 933 if (MLX5_CAP_DEV_MEM(mdev, memic)) { 934 props->max_dm_size = 935 MLX5_CAP_DEV_MEM(mdev, max_memic_size); 936 } 937 938 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 939 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 940 941 if (MLX5_CAP_GEN(mdev, end_pad)) 942 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING; 943 944 props->vendor_part_id = mdev->pdev->device; 945 props->hw_ver = mdev->pdev->revision; 946 947 props->max_mr_size = ~0ull; 948 props->page_size_cap = ~(min_page_size - 1); 949 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 950 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 951 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 952 sizeof(struct mlx5_wqe_data_seg); 953 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512); 954 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) - 955 sizeof(struct mlx5_wqe_raddr_seg)) / 956 sizeof(struct mlx5_wqe_data_seg); 957 props->max_send_sge = max_sq_sg; 958 props->max_recv_sge = max_rq_sg; 959 props->max_sge_rd = MLX5_MAX_SGE_RD; 960 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 961 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 962 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 963 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 964 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 965 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 966 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 967 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 968 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 969 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 970 props->max_srq_sge = max_rq_sg - 1; 971 props->max_fast_reg_page_list_len = 972 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 973 props->max_pi_fast_reg_page_list_len = 974 props->max_fast_reg_page_list_len / 2; 975 props->max_sgl_rd = 976 MLX5_CAP_GEN(mdev, max_sgl_for_optimized_performance); 977 get_atomic_caps_qp(dev, props); 978 props->masked_atomic_cap = IB_ATOMIC_NONE; 979 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 980 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 981 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 982 props->max_mcast_grp; 983 props->max_ah = INT_MAX; 984 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 985 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 986 987 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) { 988 if (dev->odp_caps.general_caps & IB_ODP_SUPPORT) 989 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING; 990 props->odp_caps = dev->odp_caps; 991 if (!uhw) { 992 /* ODP for kernel QPs is not implemented for receive 993 * WQEs and SRQ WQEs 994 */ 995 props->odp_caps.per_transport_caps.rc_odp_caps &= 996 ~(IB_ODP_SUPPORT_READ | 997 IB_ODP_SUPPORT_SRQ_RECV); 998 props->odp_caps.per_transport_caps.uc_odp_caps &= 999 ~(IB_ODP_SUPPORT_READ | 1000 IB_ODP_SUPPORT_SRQ_RECV); 1001 props->odp_caps.per_transport_caps.ud_odp_caps &= 1002 ~(IB_ODP_SUPPORT_READ | 1003 IB_ODP_SUPPORT_SRQ_RECV); 1004 props->odp_caps.per_transport_caps.xrc_odp_caps &= 1005 ~(IB_ODP_SUPPORT_READ | 1006 IB_ODP_SUPPORT_SRQ_RECV); 1007 } 1008 } 1009 1010 if (MLX5_CAP_GEN(mdev, cd)) 1011 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL; 1012 1013 if (mlx5_core_is_vf(mdev)) 1014 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION; 1015 1016 if (mlx5_ib_port_link_layer(ibdev, 1) == 1017 IB_LINK_LAYER_ETHERNET && raw_support) { 1018 props->rss_caps.max_rwq_indirection_tables = 1019 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 1020 props->rss_caps.max_rwq_indirection_table_size = 1021 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 1022 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 1023 props->max_wq_type_rq = 1024 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 1025 } 1026 1027 if (MLX5_CAP_GEN(mdev, tag_matching)) { 1028 props->tm_caps.max_num_tags = 1029 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1; 1030 props->tm_caps.max_ops = 1031 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 1032 props->tm_caps.max_sge = MLX5_TM_MAX_SGE; 1033 } 1034 1035 if (MLX5_CAP_GEN(mdev, tag_matching) && 1036 MLX5_CAP_GEN(mdev, rndv_offload_rc)) { 1037 props->tm_caps.flags = IB_TM_CAP_RNDV_RC; 1038 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE; 1039 } 1040 1041 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) { 1042 props->cq_caps.max_cq_moderation_count = 1043 MLX5_MAX_CQ_COUNT; 1044 props->cq_caps.max_cq_moderation_period = 1045 MLX5_MAX_CQ_PERIOD; 1046 } 1047 1048 if (offsetofend(typeof(resp), cqe_comp_caps) <= uhw_outlen) { 1049 resp.response_length += sizeof(resp.cqe_comp_caps); 1050 1051 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) { 1052 resp.cqe_comp_caps.max_num = 1053 MLX5_CAP_GEN(dev->mdev, 1054 cqe_compression_max_num); 1055 1056 resp.cqe_comp_caps.supported_format = 1057 MLX5_IB_CQE_RES_FORMAT_HASH | 1058 MLX5_IB_CQE_RES_FORMAT_CSUM; 1059 1060 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index)) 1061 resp.cqe_comp_caps.supported_format |= 1062 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX; 1063 } 1064 } 1065 1066 if (offsetofend(typeof(resp), packet_pacing_caps) <= uhw_outlen && 1067 raw_support) { 1068 if (MLX5_CAP_QOS(mdev, packet_pacing) && 1069 MLX5_CAP_GEN(mdev, qos)) { 1070 resp.packet_pacing_caps.qp_rate_limit_max = 1071 MLX5_CAP_QOS(mdev, packet_pacing_max_rate); 1072 resp.packet_pacing_caps.qp_rate_limit_min = 1073 MLX5_CAP_QOS(mdev, packet_pacing_min_rate); 1074 resp.packet_pacing_caps.supported_qpts |= 1075 1 << IB_QPT_RAW_PACKET; 1076 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) && 1077 MLX5_CAP_QOS(mdev, packet_pacing_typical_size)) 1078 resp.packet_pacing_caps.cap_flags |= 1079 MLX5_IB_PP_SUPPORT_BURST; 1080 } 1081 resp.response_length += sizeof(resp.packet_pacing_caps); 1082 } 1083 1084 if (offsetofend(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes) <= 1085 uhw_outlen) { 1086 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe)) 1087 resp.mlx5_ib_support_multi_pkt_send_wqes = 1088 MLX5_IB_ALLOW_MPW; 1089 1090 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe)) 1091 resp.mlx5_ib_support_multi_pkt_send_wqes |= 1092 MLX5_IB_SUPPORT_EMPW; 1093 1094 resp.response_length += 1095 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes); 1096 } 1097 1098 if (offsetofend(typeof(resp), flags) <= uhw_outlen) { 1099 resp.response_length += sizeof(resp.flags); 1100 1101 if (MLX5_CAP_GEN(mdev, cqe_compression_128)) 1102 resp.flags |= 1103 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP; 1104 1105 if (MLX5_CAP_GEN(mdev, cqe_128_always)) 1106 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD; 1107 if (MLX5_CAP_GEN(mdev, qp_packet_based)) 1108 resp.flags |= 1109 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE; 1110 1111 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT; 1112 } 1113 1114 if (offsetofend(typeof(resp), sw_parsing_caps) <= uhw_outlen) { 1115 resp.response_length += sizeof(resp.sw_parsing_caps); 1116 if (MLX5_CAP_ETH(mdev, swp)) { 1117 resp.sw_parsing_caps.sw_parsing_offloads |= 1118 MLX5_IB_SW_PARSING; 1119 1120 if (MLX5_CAP_ETH(mdev, swp_csum)) 1121 resp.sw_parsing_caps.sw_parsing_offloads |= 1122 MLX5_IB_SW_PARSING_CSUM; 1123 1124 if (MLX5_CAP_ETH(mdev, swp_lso)) 1125 resp.sw_parsing_caps.sw_parsing_offloads |= 1126 MLX5_IB_SW_PARSING_LSO; 1127 1128 if (resp.sw_parsing_caps.sw_parsing_offloads) 1129 resp.sw_parsing_caps.supported_qpts = 1130 BIT(IB_QPT_RAW_PACKET); 1131 } 1132 } 1133 1134 if (offsetofend(typeof(resp), striding_rq_caps) <= uhw_outlen && 1135 raw_support) { 1136 resp.response_length += sizeof(resp.striding_rq_caps); 1137 if (MLX5_CAP_GEN(mdev, striding_rq)) { 1138 resp.striding_rq_caps.min_single_stride_log_num_of_bytes = 1139 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES; 1140 resp.striding_rq_caps.max_single_stride_log_num_of_bytes = 1141 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES; 1142 if (MLX5_CAP_GEN(dev->mdev, ext_stride_num_range)) 1143 resp.striding_rq_caps 1144 .min_single_wqe_log_num_of_strides = 1145 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1146 else 1147 resp.striding_rq_caps 1148 .min_single_wqe_log_num_of_strides = 1149 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1150 resp.striding_rq_caps.max_single_wqe_log_num_of_strides = 1151 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES; 1152 resp.striding_rq_caps.supported_qpts = 1153 BIT(IB_QPT_RAW_PACKET); 1154 } 1155 } 1156 1157 if (offsetofend(typeof(resp), tunnel_offloads_caps) <= uhw_outlen) { 1158 resp.response_length += sizeof(resp.tunnel_offloads_caps); 1159 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan)) 1160 resp.tunnel_offloads_caps |= 1161 MLX5_IB_TUNNELED_OFFLOADS_VXLAN; 1162 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx)) 1163 resp.tunnel_offloads_caps |= 1164 MLX5_IB_TUNNELED_OFFLOADS_GENEVE; 1165 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) 1166 resp.tunnel_offloads_caps |= 1167 MLX5_IB_TUNNELED_OFFLOADS_GRE; 1168 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre)) 1169 resp.tunnel_offloads_caps |= 1170 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE; 1171 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_udp)) 1172 resp.tunnel_offloads_caps |= 1173 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP; 1174 } 1175 1176 if (uhw_outlen) { 1177 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 1178 1179 if (err) 1180 return err; 1181 } 1182 1183 return 0; 1184 } 1185 1186 static void translate_active_width(struct ib_device *ibdev, u16 active_width, 1187 u8 *ib_width) 1188 { 1189 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1190 1191 if (active_width & MLX5_PTYS_WIDTH_1X) 1192 *ib_width = IB_WIDTH_1X; 1193 else if (active_width & MLX5_PTYS_WIDTH_2X) 1194 *ib_width = IB_WIDTH_2X; 1195 else if (active_width & MLX5_PTYS_WIDTH_4X) 1196 *ib_width = IB_WIDTH_4X; 1197 else if (active_width & MLX5_PTYS_WIDTH_8X) 1198 *ib_width = IB_WIDTH_8X; 1199 else if (active_width & MLX5_PTYS_WIDTH_12X) 1200 *ib_width = IB_WIDTH_12X; 1201 else { 1202 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n", 1203 active_width); 1204 *ib_width = IB_WIDTH_4X; 1205 } 1206 1207 return; 1208 } 1209 1210 static int mlx5_mtu_to_ib_mtu(int mtu) 1211 { 1212 switch (mtu) { 1213 case 256: return 1; 1214 case 512: return 2; 1215 case 1024: return 3; 1216 case 2048: return 4; 1217 case 4096: return 5; 1218 default: 1219 pr_warn("invalid mtu\n"); 1220 return -1; 1221 } 1222 } 1223 1224 enum ib_max_vl_num { 1225 __IB_MAX_VL_0 = 1, 1226 __IB_MAX_VL_0_1 = 2, 1227 __IB_MAX_VL_0_3 = 3, 1228 __IB_MAX_VL_0_7 = 4, 1229 __IB_MAX_VL_0_14 = 5, 1230 }; 1231 1232 enum mlx5_vl_hw_cap { 1233 MLX5_VL_HW_0 = 1, 1234 MLX5_VL_HW_0_1 = 2, 1235 MLX5_VL_HW_0_2 = 3, 1236 MLX5_VL_HW_0_3 = 4, 1237 MLX5_VL_HW_0_4 = 5, 1238 MLX5_VL_HW_0_5 = 6, 1239 MLX5_VL_HW_0_6 = 7, 1240 MLX5_VL_HW_0_7 = 8, 1241 MLX5_VL_HW_0_14 = 15 1242 }; 1243 1244 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 1245 u8 *max_vl_num) 1246 { 1247 switch (vl_hw_cap) { 1248 case MLX5_VL_HW_0: 1249 *max_vl_num = __IB_MAX_VL_0; 1250 break; 1251 case MLX5_VL_HW_0_1: 1252 *max_vl_num = __IB_MAX_VL_0_1; 1253 break; 1254 case MLX5_VL_HW_0_3: 1255 *max_vl_num = __IB_MAX_VL_0_3; 1256 break; 1257 case MLX5_VL_HW_0_7: 1258 *max_vl_num = __IB_MAX_VL_0_7; 1259 break; 1260 case MLX5_VL_HW_0_14: 1261 *max_vl_num = __IB_MAX_VL_0_14; 1262 break; 1263 1264 default: 1265 return -EINVAL; 1266 } 1267 1268 return 0; 1269 } 1270 1271 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port, 1272 struct ib_port_attr *props) 1273 { 1274 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1275 struct mlx5_core_dev *mdev = dev->mdev; 1276 struct mlx5_hca_vport_context *rep; 1277 u16 max_mtu; 1278 u16 oper_mtu; 1279 int err; 1280 u16 ib_link_width_oper; 1281 u8 vl_hw_cap; 1282 1283 rep = kzalloc(sizeof(*rep), GFP_KERNEL); 1284 if (!rep) { 1285 err = -ENOMEM; 1286 goto out; 1287 } 1288 1289 /* props being zeroed by the caller, avoid zeroing it here */ 1290 1291 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); 1292 if (err) 1293 goto out; 1294 1295 props->lid = rep->lid; 1296 props->lmc = rep->lmc; 1297 props->sm_lid = rep->sm_lid; 1298 props->sm_sl = rep->sm_sl; 1299 props->state = rep->vport_state; 1300 props->phys_state = rep->port_physical_state; 1301 props->port_cap_flags = rep->cap_mask1; 1302 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 1303 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 1304 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 1305 props->bad_pkey_cntr = rep->pkey_violation_counter; 1306 props->qkey_viol_cntr = rep->qkey_violation_counter; 1307 props->subnet_timeout = rep->subnet_timeout; 1308 props->init_type_reply = rep->init_type_reply; 1309 1310 if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP) 1311 props->port_cap_flags2 = rep->cap_mask2; 1312 1313 err = mlx5_query_ib_port_oper(mdev, &ib_link_width_oper, 1314 &props->active_speed, port); 1315 if (err) 1316 goto out; 1317 1318 translate_active_width(ibdev, ib_link_width_oper, &props->active_width); 1319 1320 mlx5_query_port_max_mtu(mdev, &max_mtu, port); 1321 1322 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); 1323 1324 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); 1325 1326 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); 1327 1328 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); 1329 if (err) 1330 goto out; 1331 1332 err = translate_max_vl_num(ibdev, vl_hw_cap, 1333 &props->max_vl_num); 1334 out: 1335 kfree(rep); 1336 return err; 1337 } 1338 1339 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 1340 struct ib_port_attr *props) 1341 { 1342 unsigned int count; 1343 int ret; 1344 1345 switch (mlx5_get_vport_access_method(ibdev)) { 1346 case MLX5_VPORT_ACCESS_METHOD_MAD: 1347 ret = mlx5_query_mad_ifc_port(ibdev, port, props); 1348 break; 1349 1350 case MLX5_VPORT_ACCESS_METHOD_HCA: 1351 ret = mlx5_query_hca_port(ibdev, port, props); 1352 break; 1353 1354 case MLX5_VPORT_ACCESS_METHOD_NIC: 1355 ret = mlx5_query_port_roce(ibdev, port, props); 1356 break; 1357 1358 default: 1359 ret = -EINVAL; 1360 } 1361 1362 if (!ret && props) { 1363 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1364 struct mlx5_core_dev *mdev; 1365 bool put_mdev = true; 1366 1367 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL); 1368 if (!mdev) { 1369 /* If the port isn't affiliated yet query the master. 1370 * The master and slave will have the same values. 1371 */ 1372 mdev = dev->mdev; 1373 port = 1; 1374 put_mdev = false; 1375 } 1376 count = mlx5_core_reserved_gids_count(mdev); 1377 if (put_mdev) 1378 mlx5_ib_put_native_port_mdev(dev, port); 1379 props->gid_tbl_len -= count; 1380 } 1381 return ret; 1382 } 1383 1384 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port, 1385 struct ib_port_attr *props) 1386 { 1387 return mlx5_query_port_roce(ibdev, port, props); 1388 } 1389 1390 static int mlx5_ib_rep_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 1391 u16 *pkey) 1392 { 1393 /* Default special Pkey for representor device port as per the 1394 * IB specification 1.3 section 10.9.1.2. 1395 */ 1396 *pkey = 0xffff; 1397 return 0; 1398 } 1399 1400 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 1401 union ib_gid *gid) 1402 { 1403 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1404 struct mlx5_core_dev *mdev = dev->mdev; 1405 1406 switch (mlx5_get_vport_access_method(ibdev)) { 1407 case MLX5_VPORT_ACCESS_METHOD_MAD: 1408 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 1409 1410 case MLX5_VPORT_ACCESS_METHOD_HCA: 1411 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); 1412 1413 default: 1414 return -EINVAL; 1415 } 1416 1417 } 1418 1419 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port, 1420 u16 index, u16 *pkey) 1421 { 1422 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1423 struct mlx5_core_dev *mdev; 1424 bool put_mdev = true; 1425 u8 mdev_port_num; 1426 int err; 1427 1428 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num); 1429 if (!mdev) { 1430 /* The port isn't affiliated yet, get the PKey from the master 1431 * port. For RoCE the PKey tables will be the same. 1432 */ 1433 put_mdev = false; 1434 mdev = dev->mdev; 1435 mdev_port_num = 1; 1436 } 1437 1438 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0, 1439 index, pkey); 1440 if (put_mdev) 1441 mlx5_ib_put_native_port_mdev(dev, port); 1442 1443 return err; 1444 } 1445 1446 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 1447 u16 *pkey) 1448 { 1449 switch (mlx5_get_vport_access_method(ibdev)) { 1450 case MLX5_VPORT_ACCESS_METHOD_MAD: 1451 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 1452 1453 case MLX5_VPORT_ACCESS_METHOD_HCA: 1454 case MLX5_VPORT_ACCESS_METHOD_NIC: 1455 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey); 1456 default: 1457 return -EINVAL; 1458 } 1459 } 1460 1461 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 1462 struct ib_device_modify *props) 1463 { 1464 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1465 struct mlx5_reg_node_desc in; 1466 struct mlx5_reg_node_desc out; 1467 int err; 1468 1469 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 1470 return -EOPNOTSUPP; 1471 1472 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 1473 return 0; 1474 1475 /* 1476 * If possible, pass node desc to FW, so it can generate 1477 * a 144 trap. If cmd fails, just ignore. 1478 */ 1479 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1480 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 1481 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 1482 if (err) 1483 return err; 1484 1485 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1486 1487 return err; 1488 } 1489 1490 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask, 1491 u32 value) 1492 { 1493 struct mlx5_hca_vport_context ctx = {}; 1494 struct mlx5_core_dev *mdev; 1495 u8 mdev_port_num; 1496 int err; 1497 1498 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 1499 if (!mdev) 1500 return -ENODEV; 1501 1502 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx); 1503 if (err) 1504 goto out; 1505 1506 if (~ctx.cap_mask1_perm & mask) { 1507 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n", 1508 mask, ctx.cap_mask1_perm); 1509 err = -EINVAL; 1510 goto out; 1511 } 1512 1513 ctx.cap_mask1 = value; 1514 ctx.cap_mask1_perm = mask; 1515 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num, 1516 0, &ctx); 1517 1518 out: 1519 mlx5_ib_put_native_port_mdev(dev, port_num); 1520 1521 return err; 1522 } 1523 1524 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, 1525 struct ib_port_modify *props) 1526 { 1527 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1528 struct ib_port_attr attr; 1529 u32 tmp; 1530 int err; 1531 u32 change_mask; 1532 u32 value; 1533 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) == 1534 IB_LINK_LAYER_INFINIBAND); 1535 1536 /* CM layer calls ib_modify_port() regardless of the link layer. For 1537 * Ethernet ports, qkey violation and Port capabilities are meaningless. 1538 */ 1539 if (!is_ib) 1540 return 0; 1541 1542 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) { 1543 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask; 1544 value = ~props->clr_port_cap_mask | props->set_port_cap_mask; 1545 return set_port_caps_atomic(dev, port, change_mask, value); 1546 } 1547 1548 mutex_lock(&dev->cap_mask_mutex); 1549 1550 err = ib_query_port(ibdev, port, &attr); 1551 if (err) 1552 goto out; 1553 1554 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 1555 ~props->clr_port_cap_mask; 1556 1557 err = mlx5_set_port_caps(dev->mdev, port, tmp); 1558 1559 out: 1560 mutex_unlock(&dev->cap_mask_mutex); 1561 return err; 1562 } 1563 1564 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps) 1565 { 1566 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n", 1567 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n"); 1568 } 1569 1570 static u16 calc_dynamic_bfregs(int uars_per_sys_page) 1571 { 1572 /* Large page with non 4k uar support might limit the dynamic size */ 1573 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096) 1574 return MLX5_MIN_DYN_BFREGS; 1575 1576 return MLX5_MAX_DYN_BFREGS; 1577 } 1578 1579 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k, 1580 struct mlx5_ib_alloc_ucontext_req_v2 *req, 1581 struct mlx5_bfreg_info *bfregi) 1582 { 1583 int uars_per_sys_page; 1584 int bfregs_per_sys_page; 1585 int ref_bfregs = req->total_num_bfregs; 1586 1587 if (req->total_num_bfregs == 0) 1588 return -EINVAL; 1589 1590 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE); 1591 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE); 1592 1593 if (req->total_num_bfregs > MLX5_MAX_BFREGS) 1594 return -ENOMEM; 1595 1596 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k); 1597 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR; 1598 /* This holds the required static allocation asked by the user */ 1599 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page); 1600 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1) 1601 return -EINVAL; 1602 1603 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page; 1604 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page); 1605 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs; 1606 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page; 1607 1608 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n", 1609 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no", 1610 lib_uar_4k ? "yes" : "no", ref_bfregs, 1611 req->total_num_bfregs, bfregi->total_num_bfregs, 1612 bfregi->num_sys_pages); 1613 1614 return 0; 1615 } 1616 1617 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1618 { 1619 struct mlx5_bfreg_info *bfregi; 1620 int err; 1621 int i; 1622 1623 bfregi = &context->bfregi; 1624 for (i = 0; i < bfregi->num_static_sys_pages; i++) { 1625 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]); 1626 if (err) 1627 goto error; 1628 1629 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]); 1630 } 1631 1632 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++) 1633 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX; 1634 1635 return 0; 1636 1637 error: 1638 for (--i; i >= 0; i--) 1639 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i])) 1640 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1641 1642 return err; 1643 } 1644 1645 static void deallocate_uars(struct mlx5_ib_dev *dev, 1646 struct mlx5_ib_ucontext *context) 1647 { 1648 struct mlx5_bfreg_info *bfregi; 1649 int i; 1650 1651 bfregi = &context->bfregi; 1652 for (i = 0; i < bfregi->num_sys_pages; i++) 1653 if (i < bfregi->num_static_sys_pages || 1654 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) 1655 mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]); 1656 } 1657 1658 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 1659 { 1660 int err = 0; 1661 1662 mutex_lock(&dev->lb.mutex); 1663 if (td) 1664 dev->lb.user_td++; 1665 if (qp) 1666 dev->lb.qps++; 1667 1668 if (dev->lb.user_td == 2 || 1669 dev->lb.qps == 1) { 1670 if (!dev->lb.enabled) { 1671 err = mlx5_nic_vport_update_local_lb(dev->mdev, true); 1672 dev->lb.enabled = true; 1673 } 1674 } 1675 1676 mutex_unlock(&dev->lb.mutex); 1677 1678 return err; 1679 } 1680 1681 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 1682 { 1683 mutex_lock(&dev->lb.mutex); 1684 if (td) 1685 dev->lb.user_td--; 1686 if (qp) 1687 dev->lb.qps--; 1688 1689 if (dev->lb.user_td == 1 && 1690 dev->lb.qps == 0) { 1691 if (dev->lb.enabled) { 1692 mlx5_nic_vport_update_local_lb(dev->mdev, false); 1693 dev->lb.enabled = false; 1694 } 1695 } 1696 1697 mutex_unlock(&dev->lb.mutex); 1698 } 1699 1700 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn, 1701 u16 uid) 1702 { 1703 int err; 1704 1705 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1706 return 0; 1707 1708 err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid); 1709 if (err) 1710 return err; 1711 1712 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1713 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1714 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1715 return err; 1716 1717 return mlx5_ib_enable_lb(dev, true, false); 1718 } 1719 1720 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn, 1721 u16 uid) 1722 { 1723 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1724 return; 1725 1726 mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid); 1727 1728 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1729 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1730 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1731 return; 1732 1733 mlx5_ib_disable_lb(dev, true, false); 1734 } 1735 1736 static int set_ucontext_resp(struct ib_ucontext *uctx, 1737 struct mlx5_ib_alloc_ucontext_resp *resp) 1738 { 1739 struct ib_device *ibdev = uctx->device; 1740 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1741 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 1742 struct mlx5_bfreg_info *bfregi = &context->bfregi; 1743 int err; 1744 1745 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) { 1746 err = mlx5_cmd_dump_fill_mkey(dev->mdev, 1747 &resp->dump_fill_mkey); 1748 if (err) 1749 return err; 1750 resp->comp_mask |= 1751 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY; 1752 } 1753 1754 resp->qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 1755 if (dev->wc_support) 1756 resp->bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, 1757 log_bf_reg_size); 1758 resp->cache_line_size = cache_line_size(); 1759 resp->max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 1760 resp->max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 1761 resp->max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1762 resp->max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1763 resp->max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 1764 resp->cqe_version = context->cqe_version; 1765 resp->log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1766 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT; 1767 resp->num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1768 MLX5_CAP_GEN(dev->mdev, 1769 num_of_uars_per_page) : 1; 1770 1771 if (mlx5_accel_ipsec_device_caps(dev->mdev) & 1772 MLX5_ACCEL_IPSEC_CAP_DEVICE) { 1773 if (mlx5_get_flow_namespace(dev->mdev, 1774 MLX5_FLOW_NAMESPACE_EGRESS)) 1775 resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM; 1776 if (mlx5_accel_ipsec_device_caps(dev->mdev) & 1777 MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA) 1778 resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA; 1779 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi)) 1780 resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING; 1781 if (mlx5_accel_ipsec_device_caps(dev->mdev) & 1782 MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN) 1783 resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN; 1784 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */ 1785 } 1786 1787 resp->tot_bfregs = bfregi->lib_uar_dyn ? 0 : 1788 bfregi->total_num_bfregs - bfregi->num_dyn_bfregs; 1789 resp->num_ports = dev->num_ports; 1790 resp->cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 1791 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 1792 1793 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) { 1794 mlx5_query_min_inline(dev->mdev, &resp->eth_min_inline); 1795 resp->eth_min_inline++; 1796 } 1797 1798 if (dev->mdev->clock_info) 1799 resp->clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1); 1800 1801 /* 1802 * We don't want to expose information from the PCI bar that is located 1803 * after 4096 bytes, so if the arch only supports larger pages, let's 1804 * pretend we don't support reading the HCA's core clock. This is also 1805 * forced by mmap function. 1806 */ 1807 if (PAGE_SIZE <= 4096) { 1808 resp->comp_mask |= 1809 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 1810 resp->hca_core_clock_offset = 1811 offsetof(struct mlx5_init_seg, 1812 internal_timer_h) % PAGE_SIZE; 1813 } 1814 1815 if (MLX5_CAP_GEN(dev->mdev, ece_support)) 1816 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE; 1817 1818 resp->num_dyn_bfregs = bfregi->num_dyn_bfregs; 1819 return 0; 1820 } 1821 1822 static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx, 1823 struct ib_udata *udata) 1824 { 1825 struct ib_device *ibdev = uctx->device; 1826 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1827 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 1828 struct mlx5_ib_alloc_ucontext_resp resp = {}; 1829 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 1830 struct mlx5_bfreg_info *bfregi; 1831 int ver; 1832 int err; 1833 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 1834 max_cqe_version); 1835 bool lib_uar_4k; 1836 bool lib_uar_dyn; 1837 1838 if (!dev->ib_active) 1839 return -EAGAIN; 1840 1841 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 1842 ver = 0; 1843 else if (udata->inlen >= min_req_v2) 1844 ver = 2; 1845 else 1846 return -EINVAL; 1847 1848 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req))); 1849 if (err) 1850 return err; 1851 1852 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX) 1853 return -EOPNOTSUPP; 1854 1855 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 1856 return -EOPNOTSUPP; 1857 1858 req.total_num_bfregs = ALIGN(req.total_num_bfregs, 1859 MLX5_NON_FP_BFREGS_PER_UAR); 1860 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1) 1861 return -EINVAL; 1862 1863 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR; 1864 lib_uar_dyn = req.lib_caps & MLX5_LIB_CAP_DYN_UAR; 1865 bfregi = &context->bfregi; 1866 1867 if (lib_uar_dyn) { 1868 bfregi->lib_uar_dyn = lib_uar_dyn; 1869 goto uar_done; 1870 } 1871 1872 /* updates req->total_num_bfregs */ 1873 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi); 1874 if (err) 1875 goto out_ctx; 1876 1877 mutex_init(&bfregi->lock); 1878 bfregi->lib_uar_4k = lib_uar_4k; 1879 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count), 1880 GFP_KERNEL); 1881 if (!bfregi->count) { 1882 err = -ENOMEM; 1883 goto out_ctx; 1884 } 1885 1886 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages, 1887 sizeof(*bfregi->sys_pages), 1888 GFP_KERNEL); 1889 if (!bfregi->sys_pages) { 1890 err = -ENOMEM; 1891 goto out_count; 1892 } 1893 1894 err = allocate_uars(dev, context); 1895 if (err) 1896 goto out_sys_pages; 1897 1898 uar_done: 1899 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) { 1900 err = mlx5_ib_devx_create(dev, true); 1901 if (err < 0) 1902 goto out_uars; 1903 context->devx_uid = err; 1904 } 1905 1906 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn, 1907 context->devx_uid); 1908 if (err) 1909 goto out_devx; 1910 1911 INIT_LIST_HEAD(&context->db_page_list); 1912 mutex_init(&context->db_page_mutex); 1913 1914 context->cqe_version = min_t(__u8, 1915 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 1916 req.max_cqe_version); 1917 1918 err = set_ucontext_resp(uctx, &resp); 1919 if (err) 1920 goto out_mdev; 1921 1922 resp.response_length = min(udata->outlen, sizeof(resp)); 1923 err = ib_copy_to_udata(udata, &resp, resp.response_length); 1924 if (err) 1925 goto out_mdev; 1926 1927 bfregi->ver = ver; 1928 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs; 1929 context->lib_caps = req.lib_caps; 1930 print_lib_caps(dev, context->lib_caps); 1931 1932 if (mlx5_ib_lag_should_assign_affinity(dev)) { 1933 u8 port = mlx5_core_native_port_num(dev->mdev) - 1; 1934 1935 atomic_set(&context->tx_port_affinity, 1936 atomic_add_return( 1937 1, &dev->port[port].roce.tx_port_affinity)); 1938 } 1939 1940 return 0; 1941 1942 out_mdev: 1943 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 1944 out_devx: 1945 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) 1946 mlx5_ib_devx_destroy(dev, context->devx_uid); 1947 1948 out_uars: 1949 deallocate_uars(dev, context); 1950 1951 out_sys_pages: 1952 kfree(bfregi->sys_pages); 1953 1954 out_count: 1955 kfree(bfregi->count); 1956 1957 out_ctx: 1958 return err; 1959 } 1960 1961 static int mlx5_ib_query_ucontext(struct ib_ucontext *ibcontext, 1962 struct uverbs_attr_bundle *attrs) 1963 { 1964 struct mlx5_ib_alloc_ucontext_resp uctx_resp = {}; 1965 int ret; 1966 1967 ret = set_ucontext_resp(ibcontext, &uctx_resp); 1968 if (ret) 1969 return ret; 1970 1971 uctx_resp.response_length = 1972 min_t(size_t, 1973 uverbs_attr_get_len(attrs, 1974 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX), 1975 sizeof(uctx_resp)); 1976 1977 ret = uverbs_copy_to_struct_or_zero(attrs, 1978 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX, 1979 &uctx_resp, 1980 sizeof(uctx_resp)); 1981 return ret; 1982 } 1983 1984 static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1985 { 1986 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1987 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1988 struct mlx5_bfreg_info *bfregi; 1989 1990 bfregi = &context->bfregi; 1991 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 1992 1993 if (context->devx_uid) 1994 mlx5_ib_devx_destroy(dev, context->devx_uid); 1995 1996 deallocate_uars(dev, context); 1997 kfree(bfregi->sys_pages); 1998 kfree(bfregi->count); 1999 } 2000 2001 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, 2002 int uar_idx) 2003 { 2004 int fw_uars_per_page; 2005 2006 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1; 2007 2008 return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page; 2009 } 2010 2011 static u64 uar_index2paddress(struct mlx5_ib_dev *dev, 2012 int uar_idx) 2013 { 2014 unsigned int fw_uars_per_page; 2015 2016 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 2017 MLX5_UARS_IN_PAGE : 1; 2018 2019 return (dev->mdev->bar_addr + (uar_idx / fw_uars_per_page) * PAGE_SIZE); 2020 } 2021 2022 static int get_command(unsigned long offset) 2023 { 2024 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 2025 } 2026 2027 static int get_arg(unsigned long offset) 2028 { 2029 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 2030 } 2031 2032 static int get_index(unsigned long offset) 2033 { 2034 return get_arg(offset); 2035 } 2036 2037 /* Index resides in an extra byte to enable larger values than 255 */ 2038 static int get_extended_index(unsigned long offset) 2039 { 2040 return get_arg(offset) | ((offset >> 16) & 0xff) << 8; 2041 } 2042 2043 2044 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 2045 { 2046 } 2047 2048 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 2049 { 2050 switch (cmd) { 2051 case MLX5_IB_MMAP_WC_PAGE: 2052 return "WC"; 2053 case MLX5_IB_MMAP_REGULAR_PAGE: 2054 return "best effort WC"; 2055 case MLX5_IB_MMAP_NC_PAGE: 2056 return "NC"; 2057 case MLX5_IB_MMAP_DEVICE_MEM: 2058 return "Device Memory"; 2059 default: 2060 return NULL; 2061 } 2062 } 2063 2064 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev, 2065 struct vm_area_struct *vma, 2066 struct mlx5_ib_ucontext *context) 2067 { 2068 if ((vma->vm_end - vma->vm_start != PAGE_SIZE) || 2069 !(vma->vm_flags & VM_SHARED)) 2070 return -EINVAL; 2071 2072 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1) 2073 return -EOPNOTSUPP; 2074 2075 if (vma->vm_flags & (VM_WRITE | VM_EXEC)) 2076 return -EPERM; 2077 vma->vm_flags &= ~VM_MAYWRITE; 2078 2079 if (!dev->mdev->clock_info) 2080 return -EOPNOTSUPP; 2081 2082 return vm_insert_page(vma, vma->vm_start, 2083 virt_to_page(dev->mdev->clock_info)); 2084 } 2085 2086 static void mlx5_ib_mmap_free(struct rdma_user_mmap_entry *entry) 2087 { 2088 struct mlx5_user_mmap_entry *mentry = to_mmmap(entry); 2089 struct mlx5_ib_dev *dev = to_mdev(entry->ucontext->device); 2090 struct mlx5_var_table *var_table = &dev->var_table; 2091 struct mlx5_ib_dm *mdm; 2092 2093 switch (mentry->mmap_flag) { 2094 case MLX5_IB_MMAP_TYPE_MEMIC: 2095 mdm = container_of(mentry, struct mlx5_ib_dm, mentry); 2096 mlx5_cmd_dealloc_memic(&dev->dm, mdm->dev_addr, 2097 mdm->size); 2098 kfree(mdm); 2099 break; 2100 case MLX5_IB_MMAP_TYPE_VAR: 2101 mutex_lock(&var_table->bitmap_lock); 2102 clear_bit(mentry->page_idx, var_table->bitmap); 2103 mutex_unlock(&var_table->bitmap_lock); 2104 kfree(mentry); 2105 break; 2106 case MLX5_IB_MMAP_TYPE_UAR_WC: 2107 case MLX5_IB_MMAP_TYPE_UAR_NC: 2108 mlx5_cmd_free_uar(dev->mdev, mentry->page_idx); 2109 kfree(mentry); 2110 break; 2111 default: 2112 WARN_ON(true); 2113 } 2114 } 2115 2116 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 2117 struct vm_area_struct *vma, 2118 struct mlx5_ib_ucontext *context) 2119 { 2120 struct mlx5_bfreg_info *bfregi = &context->bfregi; 2121 int err; 2122 unsigned long idx; 2123 phys_addr_t pfn; 2124 pgprot_t prot; 2125 u32 bfreg_dyn_idx = 0; 2126 u32 uar_index; 2127 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC); 2128 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages : 2129 bfregi->num_static_sys_pages; 2130 2131 if (bfregi->lib_uar_dyn) 2132 return -EINVAL; 2133 2134 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2135 return -EINVAL; 2136 2137 if (dyn_uar) 2138 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages; 2139 else 2140 idx = get_index(vma->vm_pgoff); 2141 2142 if (idx >= max_valid_idx) { 2143 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n", 2144 idx, max_valid_idx); 2145 return -EINVAL; 2146 } 2147 2148 switch (cmd) { 2149 case MLX5_IB_MMAP_WC_PAGE: 2150 case MLX5_IB_MMAP_ALLOC_WC: 2151 case MLX5_IB_MMAP_REGULAR_PAGE: 2152 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 2153 prot = pgprot_writecombine(vma->vm_page_prot); 2154 break; 2155 case MLX5_IB_MMAP_NC_PAGE: 2156 prot = pgprot_noncached(vma->vm_page_prot); 2157 break; 2158 default: 2159 return -EINVAL; 2160 } 2161 2162 if (dyn_uar) { 2163 int uars_per_page; 2164 2165 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k); 2166 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR); 2167 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) { 2168 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n", 2169 bfreg_dyn_idx, bfregi->total_num_bfregs); 2170 return -EINVAL; 2171 } 2172 2173 mutex_lock(&bfregi->lock); 2174 /* Fail if uar already allocated, first bfreg index of each 2175 * page holds its count. 2176 */ 2177 if (bfregi->count[bfreg_dyn_idx]) { 2178 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx); 2179 mutex_unlock(&bfregi->lock); 2180 return -EINVAL; 2181 } 2182 2183 bfregi->count[bfreg_dyn_idx]++; 2184 mutex_unlock(&bfregi->lock); 2185 2186 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index); 2187 if (err) { 2188 mlx5_ib_warn(dev, "UAR alloc failed\n"); 2189 goto free_bfreg; 2190 } 2191 } else { 2192 uar_index = bfregi->sys_pages[idx]; 2193 } 2194 2195 pfn = uar_index2pfn(dev, uar_index); 2196 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 2197 2198 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE, 2199 prot, NULL); 2200 if (err) { 2201 mlx5_ib_err(dev, 2202 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n", 2203 err, mmap_cmd2str(cmd)); 2204 goto err; 2205 } 2206 2207 if (dyn_uar) 2208 bfregi->sys_pages[idx] = uar_index; 2209 return 0; 2210 2211 err: 2212 if (!dyn_uar) 2213 return err; 2214 2215 mlx5_cmd_free_uar(dev->mdev, idx); 2216 2217 free_bfreg: 2218 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx); 2219 2220 return err; 2221 } 2222 2223 static unsigned long mlx5_vma_to_pgoff(struct vm_area_struct *vma) 2224 { 2225 unsigned long idx; 2226 u8 command; 2227 2228 command = get_command(vma->vm_pgoff); 2229 idx = get_extended_index(vma->vm_pgoff); 2230 2231 return (command << 16 | idx); 2232 } 2233 2234 static int mlx5_ib_mmap_offset(struct mlx5_ib_dev *dev, 2235 struct vm_area_struct *vma, 2236 struct ib_ucontext *ucontext) 2237 { 2238 struct mlx5_user_mmap_entry *mentry; 2239 struct rdma_user_mmap_entry *entry; 2240 unsigned long pgoff; 2241 pgprot_t prot; 2242 phys_addr_t pfn; 2243 int ret; 2244 2245 pgoff = mlx5_vma_to_pgoff(vma); 2246 entry = rdma_user_mmap_entry_get_pgoff(ucontext, pgoff); 2247 if (!entry) 2248 return -EINVAL; 2249 2250 mentry = to_mmmap(entry); 2251 pfn = (mentry->address >> PAGE_SHIFT); 2252 if (mentry->mmap_flag == MLX5_IB_MMAP_TYPE_VAR || 2253 mentry->mmap_flag == MLX5_IB_MMAP_TYPE_UAR_NC) 2254 prot = pgprot_noncached(vma->vm_page_prot); 2255 else 2256 prot = pgprot_writecombine(vma->vm_page_prot); 2257 ret = rdma_user_mmap_io(ucontext, vma, pfn, 2258 entry->npages * PAGE_SIZE, 2259 prot, 2260 entry); 2261 rdma_user_mmap_entry_put(&mentry->rdma_entry); 2262 return ret; 2263 } 2264 2265 static u64 mlx5_entry_to_mmap_offset(struct mlx5_user_mmap_entry *entry) 2266 { 2267 u64 cmd = (entry->rdma_entry.start_pgoff >> 16) & 0xFFFF; 2268 u64 index = entry->rdma_entry.start_pgoff & 0xFFFF; 2269 2270 return (((index >> 8) << 16) | (cmd << MLX5_IB_MMAP_CMD_SHIFT) | 2271 (index & 0xFF)) << PAGE_SHIFT; 2272 } 2273 2274 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 2275 { 2276 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2277 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2278 unsigned long command; 2279 phys_addr_t pfn; 2280 2281 command = get_command(vma->vm_pgoff); 2282 switch (command) { 2283 case MLX5_IB_MMAP_WC_PAGE: 2284 case MLX5_IB_MMAP_ALLOC_WC: 2285 if (!dev->wc_support) 2286 return -EPERM; 2287 fallthrough; 2288 case MLX5_IB_MMAP_NC_PAGE: 2289 case MLX5_IB_MMAP_REGULAR_PAGE: 2290 return uar_mmap(dev, command, vma, context); 2291 2292 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 2293 return -ENOSYS; 2294 2295 case MLX5_IB_MMAP_CORE_CLOCK: 2296 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2297 return -EINVAL; 2298 2299 if (vma->vm_flags & VM_WRITE) 2300 return -EPERM; 2301 vma->vm_flags &= ~VM_MAYWRITE; 2302 2303 /* Don't expose to user-space information it shouldn't have */ 2304 if (PAGE_SIZE > 4096) 2305 return -EOPNOTSUPP; 2306 2307 pfn = (dev->mdev->iseg_base + 2308 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 2309 PAGE_SHIFT; 2310 return rdma_user_mmap_io(&context->ibucontext, vma, pfn, 2311 PAGE_SIZE, 2312 pgprot_noncached(vma->vm_page_prot), 2313 NULL); 2314 case MLX5_IB_MMAP_CLOCK_INFO: 2315 return mlx5_ib_mmap_clock_info_page(dev, vma, context); 2316 2317 default: 2318 return mlx5_ib_mmap_offset(dev, vma, ibcontext); 2319 } 2320 2321 return 0; 2322 } 2323 2324 static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata) 2325 { 2326 struct mlx5_ib_pd *pd = to_mpd(ibpd); 2327 struct ib_device *ibdev = ibpd->device; 2328 struct mlx5_ib_alloc_pd_resp resp; 2329 int err; 2330 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {}; 2331 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {}; 2332 u16 uid = 0; 2333 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 2334 udata, struct mlx5_ib_ucontext, ibucontext); 2335 2336 uid = context ? context->devx_uid : 0; 2337 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2338 MLX5_SET(alloc_pd_in, in, uid, uid); 2339 err = mlx5_cmd_exec_inout(to_mdev(ibdev)->mdev, alloc_pd, in, out); 2340 if (err) 2341 return err; 2342 2343 pd->pdn = MLX5_GET(alloc_pd_out, out, pd); 2344 pd->uid = uid; 2345 if (udata) { 2346 resp.pdn = pd->pdn; 2347 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 2348 mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid); 2349 return -EFAULT; 2350 } 2351 } 2352 2353 return 0; 2354 } 2355 2356 static int mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata) 2357 { 2358 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 2359 struct mlx5_ib_pd *mpd = to_mpd(pd); 2360 2361 return mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid); 2362 } 2363 2364 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2365 { 2366 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2367 struct mlx5_ib_qp *mqp = to_mqp(ibqp); 2368 int err; 2369 u16 uid; 2370 2371 uid = ibqp->pd ? 2372 to_mpd(ibqp->pd)->uid : 0; 2373 2374 if (mqp->flags & IB_QP_CREATE_SOURCE_QPN) { 2375 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n"); 2376 return -EOPNOTSUPP; 2377 } 2378 2379 err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 2380 if (err) 2381 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 2382 ibqp->qp_num, gid->raw); 2383 2384 return err; 2385 } 2386 2387 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2388 { 2389 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2390 int err; 2391 u16 uid; 2392 2393 uid = ibqp->pd ? 2394 to_mpd(ibqp->pd)->uid : 0; 2395 err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 2396 if (err) 2397 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 2398 ibqp->qp_num, gid->raw); 2399 2400 return err; 2401 } 2402 2403 static int init_node_data(struct mlx5_ib_dev *dev) 2404 { 2405 int err; 2406 2407 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 2408 if (err) 2409 return err; 2410 2411 dev->mdev->rev_id = dev->mdev->pdev->revision; 2412 2413 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 2414 } 2415 2416 static ssize_t fw_pages_show(struct device *device, 2417 struct device_attribute *attr, char *buf) 2418 { 2419 struct mlx5_ib_dev *dev = 2420 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2421 2422 return sysfs_emit(buf, "%d\n", dev->mdev->priv.fw_pages); 2423 } 2424 static DEVICE_ATTR_RO(fw_pages); 2425 2426 static ssize_t reg_pages_show(struct device *device, 2427 struct device_attribute *attr, char *buf) 2428 { 2429 struct mlx5_ib_dev *dev = 2430 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2431 2432 return sysfs_emit(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 2433 } 2434 static DEVICE_ATTR_RO(reg_pages); 2435 2436 static ssize_t hca_type_show(struct device *device, 2437 struct device_attribute *attr, char *buf) 2438 { 2439 struct mlx5_ib_dev *dev = 2440 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2441 2442 return sysfs_emit(buf, "MT%d\n", dev->mdev->pdev->device); 2443 } 2444 static DEVICE_ATTR_RO(hca_type); 2445 2446 static ssize_t hw_rev_show(struct device *device, 2447 struct device_attribute *attr, char *buf) 2448 { 2449 struct mlx5_ib_dev *dev = 2450 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2451 2452 return sysfs_emit(buf, "%x\n", dev->mdev->rev_id); 2453 } 2454 static DEVICE_ATTR_RO(hw_rev); 2455 2456 static ssize_t board_id_show(struct device *device, 2457 struct device_attribute *attr, char *buf) 2458 { 2459 struct mlx5_ib_dev *dev = 2460 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2461 2462 return sysfs_emit(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 2463 dev->mdev->board_id); 2464 } 2465 static DEVICE_ATTR_RO(board_id); 2466 2467 static struct attribute *mlx5_class_attributes[] = { 2468 &dev_attr_hw_rev.attr, 2469 &dev_attr_hca_type.attr, 2470 &dev_attr_board_id.attr, 2471 &dev_attr_fw_pages.attr, 2472 &dev_attr_reg_pages.attr, 2473 NULL, 2474 }; 2475 2476 static const struct attribute_group mlx5_attr_group = { 2477 .attrs = mlx5_class_attributes, 2478 }; 2479 2480 static void pkey_change_handler(struct work_struct *work) 2481 { 2482 struct mlx5_ib_port_resources *ports = 2483 container_of(work, struct mlx5_ib_port_resources, 2484 pkey_change_work); 2485 2486 mlx5_ib_gsi_pkey_change(ports->gsi); 2487 } 2488 2489 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 2490 { 2491 struct mlx5_ib_qp *mqp; 2492 struct mlx5_ib_cq *send_mcq, *recv_mcq; 2493 struct mlx5_core_cq *mcq; 2494 struct list_head cq_armed_list; 2495 unsigned long flags_qp; 2496 unsigned long flags_cq; 2497 unsigned long flags; 2498 2499 INIT_LIST_HEAD(&cq_armed_list); 2500 2501 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 2502 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 2503 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 2504 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 2505 if (mqp->sq.tail != mqp->sq.head) { 2506 send_mcq = to_mcq(mqp->ibqp.send_cq); 2507 spin_lock_irqsave(&send_mcq->lock, flags_cq); 2508 if (send_mcq->mcq.comp && 2509 mqp->ibqp.send_cq->comp_handler) { 2510 if (!send_mcq->mcq.reset_notify_added) { 2511 send_mcq->mcq.reset_notify_added = 1; 2512 list_add_tail(&send_mcq->mcq.reset_notify, 2513 &cq_armed_list); 2514 } 2515 } 2516 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 2517 } 2518 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 2519 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 2520 /* no handling is needed for SRQ */ 2521 if (!mqp->ibqp.srq) { 2522 if (mqp->rq.tail != mqp->rq.head) { 2523 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 2524 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 2525 if (recv_mcq->mcq.comp && 2526 mqp->ibqp.recv_cq->comp_handler) { 2527 if (!recv_mcq->mcq.reset_notify_added) { 2528 recv_mcq->mcq.reset_notify_added = 1; 2529 list_add_tail(&recv_mcq->mcq.reset_notify, 2530 &cq_armed_list); 2531 } 2532 } 2533 spin_unlock_irqrestore(&recv_mcq->lock, 2534 flags_cq); 2535 } 2536 } 2537 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 2538 } 2539 /*At that point all inflight post send were put to be executed as of we 2540 * lock/unlock above locks Now need to arm all involved CQs. 2541 */ 2542 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 2543 mcq->comp(mcq, NULL); 2544 } 2545 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 2546 } 2547 2548 static void delay_drop_handler(struct work_struct *work) 2549 { 2550 int err; 2551 struct mlx5_ib_delay_drop *delay_drop = 2552 container_of(work, struct mlx5_ib_delay_drop, 2553 delay_drop_work); 2554 2555 atomic_inc(&delay_drop->events_cnt); 2556 2557 mutex_lock(&delay_drop->lock); 2558 err = mlx5_core_set_delay_drop(delay_drop->dev, delay_drop->timeout); 2559 if (err) { 2560 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n", 2561 delay_drop->timeout); 2562 delay_drop->activate = false; 2563 } 2564 mutex_unlock(&delay_drop->lock); 2565 } 2566 2567 static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 2568 struct ib_event *ibev) 2569 { 2570 u8 port = (eqe->data.port.port >> 4) & 0xf; 2571 2572 switch (eqe->sub_type) { 2573 case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT: 2574 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2575 IB_LINK_LAYER_ETHERNET) 2576 schedule_work(&ibdev->delay_drop.delay_drop_work); 2577 break; 2578 default: /* do nothing */ 2579 return; 2580 } 2581 } 2582 2583 static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 2584 struct ib_event *ibev) 2585 { 2586 u8 port = (eqe->data.port.port >> 4) & 0xf; 2587 2588 ibev->element.port_num = port; 2589 2590 switch (eqe->sub_type) { 2591 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 2592 case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 2593 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED: 2594 /* In RoCE, port up/down events are handled in 2595 * mlx5_netdev_event(). 2596 */ 2597 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2598 IB_LINK_LAYER_ETHERNET) 2599 return -EINVAL; 2600 2601 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ? 2602 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 2603 break; 2604 2605 case MLX5_PORT_CHANGE_SUBTYPE_LID: 2606 ibev->event = IB_EVENT_LID_CHANGE; 2607 break; 2608 2609 case MLX5_PORT_CHANGE_SUBTYPE_PKEY: 2610 ibev->event = IB_EVENT_PKEY_CHANGE; 2611 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 2612 break; 2613 2614 case MLX5_PORT_CHANGE_SUBTYPE_GUID: 2615 ibev->event = IB_EVENT_GID_CHANGE; 2616 break; 2617 2618 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG: 2619 ibev->event = IB_EVENT_CLIENT_REREGISTER; 2620 break; 2621 default: 2622 return -EINVAL; 2623 } 2624 2625 return 0; 2626 } 2627 2628 static void mlx5_ib_handle_event(struct work_struct *_work) 2629 { 2630 struct mlx5_ib_event_work *work = 2631 container_of(_work, struct mlx5_ib_event_work, work); 2632 struct mlx5_ib_dev *ibdev; 2633 struct ib_event ibev; 2634 bool fatal = false; 2635 2636 if (work->is_slave) { 2637 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi); 2638 if (!ibdev) 2639 goto out; 2640 } else { 2641 ibdev = work->dev; 2642 } 2643 2644 switch (work->event) { 2645 case MLX5_DEV_EVENT_SYS_ERROR: 2646 ibev.event = IB_EVENT_DEVICE_FATAL; 2647 mlx5_ib_handle_internal_error(ibdev); 2648 ibev.element.port_num = (u8)(unsigned long)work->param; 2649 fatal = true; 2650 break; 2651 case MLX5_EVENT_TYPE_PORT_CHANGE: 2652 if (handle_port_change(ibdev, work->param, &ibev)) 2653 goto out; 2654 break; 2655 case MLX5_EVENT_TYPE_GENERAL_EVENT: 2656 handle_general_event(ibdev, work->param, &ibev); 2657 fallthrough; 2658 default: 2659 goto out; 2660 } 2661 2662 ibev.device = &ibdev->ib_dev; 2663 2664 if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) { 2665 mlx5_ib_warn(ibdev, "warning: event on port %d\n", ibev.element.port_num); 2666 goto out; 2667 } 2668 2669 if (ibdev->ib_active) 2670 ib_dispatch_event(&ibev); 2671 2672 if (fatal) 2673 ibdev->ib_active = false; 2674 out: 2675 kfree(work); 2676 } 2677 2678 static int mlx5_ib_event(struct notifier_block *nb, 2679 unsigned long event, void *param) 2680 { 2681 struct mlx5_ib_event_work *work; 2682 2683 work = kmalloc(sizeof(*work), GFP_ATOMIC); 2684 if (!work) 2685 return NOTIFY_DONE; 2686 2687 INIT_WORK(&work->work, mlx5_ib_handle_event); 2688 work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events); 2689 work->is_slave = false; 2690 work->param = param; 2691 work->event = event; 2692 2693 queue_work(mlx5_ib_event_wq, &work->work); 2694 2695 return NOTIFY_OK; 2696 } 2697 2698 static int mlx5_ib_event_slave_port(struct notifier_block *nb, 2699 unsigned long event, void *param) 2700 { 2701 struct mlx5_ib_event_work *work; 2702 2703 work = kmalloc(sizeof(*work), GFP_ATOMIC); 2704 if (!work) 2705 return NOTIFY_DONE; 2706 2707 INIT_WORK(&work->work, mlx5_ib_handle_event); 2708 work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events); 2709 work->is_slave = true; 2710 work->param = param; 2711 work->event = event; 2712 queue_work(mlx5_ib_event_wq, &work->work); 2713 2714 return NOTIFY_OK; 2715 } 2716 2717 static int set_has_smi_cap(struct mlx5_ib_dev *dev) 2718 { 2719 struct mlx5_hca_vport_context vport_ctx; 2720 int err; 2721 int port; 2722 2723 for (port = 1; port <= ARRAY_SIZE(dev->port_caps); port++) { 2724 dev->port_caps[port - 1].has_smi = false; 2725 if (MLX5_CAP_GEN(dev->mdev, port_type) == 2726 MLX5_CAP_PORT_TYPE_IB) { 2727 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) { 2728 err = mlx5_query_hca_vport_context(dev->mdev, 0, 2729 port, 0, 2730 &vport_ctx); 2731 if (err) { 2732 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n", 2733 port, err); 2734 return err; 2735 } 2736 dev->port_caps[port - 1].has_smi = 2737 vport_ctx.has_smi; 2738 } else { 2739 dev->port_caps[port - 1].has_smi = true; 2740 } 2741 } 2742 } 2743 return 0; 2744 } 2745 2746 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 2747 { 2748 unsigned int port; 2749 2750 rdma_for_each_port (&dev->ib_dev, port) 2751 mlx5_query_ext_port_caps(dev, port); 2752 } 2753 2754 static u8 mlx5_get_umr_fence(u8 umr_fence_cap) 2755 { 2756 switch (umr_fence_cap) { 2757 case MLX5_CAP_UMR_FENCE_NONE: 2758 return MLX5_FENCE_MODE_NONE; 2759 case MLX5_CAP_UMR_FENCE_SMALL: 2760 return MLX5_FENCE_MODE_INITIATOR_SMALL; 2761 default: 2762 return MLX5_FENCE_MODE_STRONG_ORDERING; 2763 } 2764 } 2765 2766 static int mlx5_ib_dev_res_init(struct mlx5_ib_dev *dev) 2767 { 2768 struct mlx5_ib_resources *devr = &dev->devr; 2769 struct ib_srq_init_attr attr; 2770 struct ib_device *ibdev; 2771 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 2772 int port; 2773 int ret = 0; 2774 2775 ibdev = &dev->ib_dev; 2776 2777 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 2778 return -EOPNOTSUPP; 2779 2780 mutex_init(&devr->mutex); 2781 2782 devr->p0 = rdma_zalloc_drv_obj(ibdev, ib_pd); 2783 if (!devr->p0) 2784 return -ENOMEM; 2785 2786 devr->p0->device = ibdev; 2787 devr->p0->uobject = NULL; 2788 atomic_set(&devr->p0->usecnt, 0); 2789 2790 ret = mlx5_ib_alloc_pd(devr->p0, NULL); 2791 if (ret) 2792 goto error0; 2793 2794 devr->c0 = rdma_zalloc_drv_obj(ibdev, ib_cq); 2795 if (!devr->c0) { 2796 ret = -ENOMEM; 2797 goto error1; 2798 } 2799 2800 devr->c0->device = &dev->ib_dev; 2801 atomic_set(&devr->c0->usecnt, 0); 2802 2803 ret = mlx5_ib_create_cq(devr->c0, &cq_attr, NULL); 2804 if (ret) 2805 goto err_create_cq; 2806 2807 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn0, 0); 2808 if (ret) 2809 goto error2; 2810 2811 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn1, 0); 2812 if (ret) 2813 goto error3; 2814 2815 memset(&attr, 0, sizeof(attr)); 2816 attr.attr.max_sge = 1; 2817 attr.attr.max_wr = 1; 2818 attr.srq_type = IB_SRQT_XRC; 2819 attr.ext.cq = devr->c0; 2820 2821 devr->s0 = rdma_zalloc_drv_obj(ibdev, ib_srq); 2822 if (!devr->s0) { 2823 ret = -ENOMEM; 2824 goto error4; 2825 } 2826 2827 devr->s0->device = &dev->ib_dev; 2828 devr->s0->pd = devr->p0; 2829 devr->s0->srq_type = IB_SRQT_XRC; 2830 devr->s0->ext.cq = devr->c0; 2831 ret = mlx5_ib_create_srq(devr->s0, &attr, NULL); 2832 if (ret) 2833 goto err_create; 2834 2835 atomic_inc(&devr->s0->ext.cq->usecnt); 2836 atomic_inc(&devr->p0->usecnt); 2837 atomic_set(&devr->s0->usecnt, 0); 2838 2839 memset(&attr, 0, sizeof(attr)); 2840 attr.attr.max_sge = 1; 2841 attr.attr.max_wr = 1; 2842 attr.srq_type = IB_SRQT_BASIC; 2843 devr->s1 = rdma_zalloc_drv_obj(ibdev, ib_srq); 2844 if (!devr->s1) { 2845 ret = -ENOMEM; 2846 goto error5; 2847 } 2848 2849 devr->s1->device = &dev->ib_dev; 2850 devr->s1->pd = devr->p0; 2851 devr->s1->srq_type = IB_SRQT_BASIC; 2852 devr->s1->ext.cq = devr->c0; 2853 2854 ret = mlx5_ib_create_srq(devr->s1, &attr, NULL); 2855 if (ret) 2856 goto error6; 2857 2858 atomic_inc(&devr->p0->usecnt); 2859 atomic_set(&devr->s1->usecnt, 0); 2860 2861 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) 2862 INIT_WORK(&devr->ports[port].pkey_change_work, 2863 pkey_change_handler); 2864 2865 return 0; 2866 2867 error6: 2868 kfree(devr->s1); 2869 error5: 2870 mlx5_ib_destroy_srq(devr->s0, NULL); 2871 err_create: 2872 kfree(devr->s0); 2873 error4: 2874 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0); 2875 error3: 2876 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0); 2877 error2: 2878 mlx5_ib_destroy_cq(devr->c0, NULL); 2879 err_create_cq: 2880 kfree(devr->c0); 2881 error1: 2882 mlx5_ib_dealloc_pd(devr->p0, NULL); 2883 error0: 2884 kfree(devr->p0); 2885 return ret; 2886 } 2887 2888 static void mlx5_ib_dev_res_cleanup(struct mlx5_ib_dev *dev) 2889 { 2890 struct mlx5_ib_resources *devr = &dev->devr; 2891 int port; 2892 2893 mlx5_ib_destroy_srq(devr->s1, NULL); 2894 kfree(devr->s1); 2895 mlx5_ib_destroy_srq(devr->s0, NULL); 2896 kfree(devr->s0); 2897 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0); 2898 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0); 2899 mlx5_ib_destroy_cq(devr->c0, NULL); 2900 kfree(devr->c0); 2901 mlx5_ib_dealloc_pd(devr->p0, NULL); 2902 kfree(devr->p0); 2903 2904 /* Make sure no change P_Key work items are still executing */ 2905 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) 2906 cancel_work_sync(&devr->ports[port].pkey_change_work); 2907 } 2908 2909 static u32 get_core_cap_flags(struct ib_device *ibdev, 2910 struct mlx5_hca_vport_context *rep) 2911 { 2912 struct mlx5_ib_dev *dev = to_mdev(ibdev); 2913 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 2914 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 2915 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 2916 bool raw_support = !mlx5_core_mp_enabled(dev->mdev); 2917 u32 ret = 0; 2918 2919 if (rep->grh_required) 2920 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED; 2921 2922 if (ll == IB_LINK_LAYER_INFINIBAND) 2923 return ret | RDMA_CORE_PORT_IBA_IB; 2924 2925 if (raw_support) 2926 ret |= RDMA_CORE_PORT_RAW_PACKET; 2927 2928 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 2929 return ret; 2930 2931 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 2932 return ret; 2933 2934 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 2935 ret |= RDMA_CORE_PORT_IBA_ROCE; 2936 2937 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 2938 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 2939 2940 return ret; 2941 } 2942 2943 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num, 2944 struct ib_port_immutable *immutable) 2945 { 2946 struct ib_port_attr attr; 2947 struct mlx5_ib_dev *dev = to_mdev(ibdev); 2948 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num); 2949 struct mlx5_hca_vport_context rep = {0}; 2950 int err; 2951 2952 err = ib_query_port(ibdev, port_num, &attr); 2953 if (err) 2954 return err; 2955 2956 if (ll == IB_LINK_LAYER_INFINIBAND) { 2957 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0, 2958 &rep); 2959 if (err) 2960 return err; 2961 } 2962 2963 immutable->pkey_tbl_len = attr.pkey_tbl_len; 2964 immutable->gid_tbl_len = attr.gid_tbl_len; 2965 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep); 2966 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 2967 2968 return 0; 2969 } 2970 2971 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num, 2972 struct ib_port_immutable *immutable) 2973 { 2974 struct ib_port_attr attr; 2975 int err; 2976 2977 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 2978 2979 err = ib_query_port(ibdev, port_num, &attr); 2980 if (err) 2981 return err; 2982 2983 immutable->pkey_tbl_len = attr.pkey_tbl_len; 2984 immutable->gid_tbl_len = attr.gid_tbl_len; 2985 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 2986 2987 return 0; 2988 } 2989 2990 static void get_dev_fw_str(struct ib_device *ibdev, char *str) 2991 { 2992 struct mlx5_ib_dev *dev = 2993 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 2994 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d", 2995 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev), 2996 fw_rev_sub(dev->mdev)); 2997 } 2998 2999 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev) 3000 { 3001 struct mlx5_core_dev *mdev = dev->mdev; 3002 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev, 3003 MLX5_FLOW_NAMESPACE_LAG); 3004 struct mlx5_flow_table *ft; 3005 int err; 3006 3007 if (!ns || !mlx5_lag_is_roce(mdev)) 3008 return 0; 3009 3010 err = mlx5_cmd_create_vport_lag(mdev); 3011 if (err) 3012 return err; 3013 3014 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0); 3015 if (IS_ERR(ft)) { 3016 err = PTR_ERR(ft); 3017 goto err_destroy_vport_lag; 3018 } 3019 3020 dev->flow_db->lag_demux_ft = ft; 3021 dev->lag_active = true; 3022 return 0; 3023 3024 err_destroy_vport_lag: 3025 mlx5_cmd_destroy_vport_lag(mdev); 3026 return err; 3027 } 3028 3029 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev) 3030 { 3031 struct mlx5_core_dev *mdev = dev->mdev; 3032 3033 if (dev->lag_active) { 3034 dev->lag_active = false; 3035 3036 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft); 3037 dev->flow_db->lag_demux_ft = NULL; 3038 3039 mlx5_cmd_destroy_vport_lag(mdev); 3040 } 3041 } 3042 3043 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num) 3044 { 3045 int err; 3046 3047 dev->port[port_num].roce.nb.notifier_call = mlx5_netdev_event; 3048 err = register_netdevice_notifier(&dev->port[port_num].roce.nb); 3049 if (err) { 3050 dev->port[port_num].roce.nb.notifier_call = NULL; 3051 return err; 3052 } 3053 3054 return 0; 3055 } 3056 3057 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num) 3058 { 3059 if (dev->port[port_num].roce.nb.notifier_call) { 3060 unregister_netdevice_notifier(&dev->port[port_num].roce.nb); 3061 dev->port[port_num].roce.nb.notifier_call = NULL; 3062 } 3063 } 3064 3065 static int mlx5_enable_eth(struct mlx5_ib_dev *dev) 3066 { 3067 int err; 3068 3069 err = mlx5_nic_vport_enable_roce(dev->mdev); 3070 if (err) 3071 return err; 3072 3073 err = mlx5_eth_lag_init(dev); 3074 if (err) 3075 goto err_disable_roce; 3076 3077 return 0; 3078 3079 err_disable_roce: 3080 mlx5_nic_vport_disable_roce(dev->mdev); 3081 3082 return err; 3083 } 3084 3085 static void mlx5_disable_eth(struct mlx5_ib_dev *dev) 3086 { 3087 mlx5_eth_lag_cleanup(dev); 3088 mlx5_nic_vport_disable_roce(dev->mdev); 3089 } 3090 3091 static int mlx5_ib_rn_get_params(struct ib_device *device, u8 port_num, 3092 enum rdma_netdev_t type, 3093 struct rdma_netdev_alloc_params *params) 3094 { 3095 if (type != RDMA_NETDEV_IPOIB) 3096 return -EOPNOTSUPP; 3097 3098 return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params); 3099 } 3100 3101 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf, 3102 size_t count, loff_t *pos) 3103 { 3104 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3105 char lbuf[20]; 3106 int len; 3107 3108 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout); 3109 return simple_read_from_buffer(buf, count, pos, lbuf, len); 3110 } 3111 3112 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf, 3113 size_t count, loff_t *pos) 3114 { 3115 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3116 u32 timeout; 3117 u32 var; 3118 3119 if (kstrtouint_from_user(buf, count, 0, &var)) 3120 return -EFAULT; 3121 3122 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 3123 1000); 3124 if (timeout != var) 3125 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n", 3126 timeout); 3127 3128 delay_drop->timeout = timeout; 3129 3130 return count; 3131 } 3132 3133 static const struct file_operations fops_delay_drop_timeout = { 3134 .owner = THIS_MODULE, 3135 .open = simple_open, 3136 .write = delay_drop_timeout_write, 3137 .read = delay_drop_timeout_read, 3138 }; 3139 3140 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev, 3141 struct mlx5_ib_multiport_info *mpi) 3142 { 3143 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 3144 struct mlx5_ib_port *port = &ibdev->port[port_num]; 3145 int comps; 3146 int err; 3147 int i; 3148 3149 lockdep_assert_held(&mlx5_ib_multiport_mutex); 3150 3151 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num); 3152 3153 spin_lock(&port->mp.mpi_lock); 3154 if (!mpi->ibdev) { 3155 spin_unlock(&port->mp.mpi_lock); 3156 return; 3157 } 3158 3159 mpi->ibdev = NULL; 3160 3161 spin_unlock(&port->mp.mpi_lock); 3162 if (mpi->mdev_events.notifier_call) 3163 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events); 3164 mpi->mdev_events.notifier_call = NULL; 3165 mlx5_remove_netdev_notifier(ibdev, port_num); 3166 spin_lock(&port->mp.mpi_lock); 3167 3168 comps = mpi->mdev_refcnt; 3169 if (comps) { 3170 mpi->unaffiliate = true; 3171 init_completion(&mpi->unref_comp); 3172 spin_unlock(&port->mp.mpi_lock); 3173 3174 for (i = 0; i < comps; i++) 3175 wait_for_completion(&mpi->unref_comp); 3176 3177 spin_lock(&port->mp.mpi_lock); 3178 mpi->unaffiliate = false; 3179 } 3180 3181 port->mp.mpi = NULL; 3182 3183 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 3184 3185 spin_unlock(&port->mp.mpi_lock); 3186 3187 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev); 3188 3189 mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1); 3190 /* Log an error, still needed to cleanup the pointers and add 3191 * it back to the list. 3192 */ 3193 if (err) 3194 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n", 3195 port_num + 1); 3196 3197 ibdev->port[port_num].roce.last_port_state = IB_PORT_DOWN; 3198 } 3199 3200 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev, 3201 struct mlx5_ib_multiport_info *mpi) 3202 { 3203 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 3204 int err; 3205 3206 lockdep_assert_held(&mlx5_ib_multiport_mutex); 3207 3208 spin_lock(&ibdev->port[port_num].mp.mpi_lock); 3209 if (ibdev->port[port_num].mp.mpi) { 3210 mlx5_ib_dbg(ibdev, "port %d already affiliated.\n", 3211 port_num + 1); 3212 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 3213 return false; 3214 } 3215 3216 ibdev->port[port_num].mp.mpi = mpi; 3217 mpi->ibdev = ibdev; 3218 mpi->mdev_events.notifier_call = NULL; 3219 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 3220 3221 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev); 3222 if (err) 3223 goto unbind; 3224 3225 err = mlx5_add_netdev_notifier(ibdev, port_num); 3226 if (err) { 3227 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n", 3228 port_num + 1); 3229 goto unbind; 3230 } 3231 3232 mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port; 3233 mlx5_notifier_register(mpi->mdev, &mpi->mdev_events); 3234 3235 mlx5_ib_init_cong_debugfs(ibdev, port_num); 3236 3237 return true; 3238 3239 unbind: 3240 mlx5_ib_unbind_slave_port(ibdev, mpi); 3241 return false; 3242 } 3243 3244 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev) 3245 { 3246 int port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3247 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 3248 port_num + 1); 3249 struct mlx5_ib_multiport_info *mpi; 3250 int err; 3251 int i; 3252 3253 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 3254 return 0; 3255 3256 err = mlx5_query_nic_vport_system_image_guid(dev->mdev, 3257 &dev->sys_image_guid); 3258 if (err) 3259 return err; 3260 3261 err = mlx5_nic_vport_enable_roce(dev->mdev); 3262 if (err) 3263 return err; 3264 3265 mutex_lock(&mlx5_ib_multiport_mutex); 3266 for (i = 0; i < dev->num_ports; i++) { 3267 bool bound = false; 3268 3269 /* build a stub multiport info struct for the native port. */ 3270 if (i == port_num) { 3271 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 3272 if (!mpi) { 3273 mutex_unlock(&mlx5_ib_multiport_mutex); 3274 mlx5_nic_vport_disable_roce(dev->mdev); 3275 return -ENOMEM; 3276 } 3277 3278 mpi->is_master = true; 3279 mpi->mdev = dev->mdev; 3280 mpi->sys_image_guid = dev->sys_image_guid; 3281 dev->port[i].mp.mpi = mpi; 3282 mpi->ibdev = dev; 3283 mpi = NULL; 3284 continue; 3285 } 3286 3287 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list, 3288 list) { 3289 if (dev->sys_image_guid == mpi->sys_image_guid && 3290 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) { 3291 bound = mlx5_ib_bind_slave_port(dev, mpi); 3292 } 3293 3294 if (bound) { 3295 dev_dbg(mpi->mdev->device, 3296 "removing port from unaffiliated list.\n"); 3297 mlx5_ib_dbg(dev, "port %d bound\n", i + 1); 3298 list_del(&mpi->list); 3299 break; 3300 } 3301 } 3302 if (!bound) 3303 mlx5_ib_dbg(dev, "no free port found for port %d\n", 3304 i + 1); 3305 } 3306 3307 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list); 3308 mutex_unlock(&mlx5_ib_multiport_mutex); 3309 return err; 3310 } 3311 3312 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev) 3313 { 3314 int port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3315 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 3316 port_num + 1); 3317 int i; 3318 3319 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 3320 return; 3321 3322 mutex_lock(&mlx5_ib_multiport_mutex); 3323 for (i = 0; i < dev->num_ports; i++) { 3324 if (dev->port[i].mp.mpi) { 3325 /* Destroy the native port stub */ 3326 if (i == port_num) { 3327 kfree(dev->port[i].mp.mpi); 3328 dev->port[i].mp.mpi = NULL; 3329 } else { 3330 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1); 3331 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi); 3332 } 3333 } 3334 } 3335 3336 mlx5_ib_dbg(dev, "removing from devlist\n"); 3337 list_del(&dev->ib_dev_list); 3338 mutex_unlock(&mlx5_ib_multiport_mutex); 3339 3340 mlx5_nic_vport_disable_roce(dev->mdev); 3341 } 3342 3343 static int mmap_obj_cleanup(struct ib_uobject *uobject, 3344 enum rdma_remove_reason why, 3345 struct uverbs_attr_bundle *attrs) 3346 { 3347 struct mlx5_user_mmap_entry *obj = uobject->object; 3348 3349 rdma_user_mmap_entry_remove(&obj->rdma_entry); 3350 return 0; 3351 } 3352 3353 static int mlx5_rdma_user_mmap_entry_insert(struct mlx5_ib_ucontext *c, 3354 struct mlx5_user_mmap_entry *entry, 3355 size_t length) 3356 { 3357 return rdma_user_mmap_entry_insert_range( 3358 &c->ibucontext, &entry->rdma_entry, length, 3359 (MLX5_IB_MMAP_OFFSET_START << 16), 3360 ((MLX5_IB_MMAP_OFFSET_END << 16) + (1UL << 16) - 1)); 3361 } 3362 3363 static struct mlx5_user_mmap_entry * 3364 alloc_var_entry(struct mlx5_ib_ucontext *c) 3365 { 3366 struct mlx5_user_mmap_entry *entry; 3367 struct mlx5_var_table *var_table; 3368 u32 page_idx; 3369 int err; 3370 3371 var_table = &to_mdev(c->ibucontext.device)->var_table; 3372 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 3373 if (!entry) 3374 return ERR_PTR(-ENOMEM); 3375 3376 mutex_lock(&var_table->bitmap_lock); 3377 page_idx = find_first_zero_bit(var_table->bitmap, 3378 var_table->num_var_hw_entries); 3379 if (page_idx >= var_table->num_var_hw_entries) { 3380 err = -ENOSPC; 3381 mutex_unlock(&var_table->bitmap_lock); 3382 goto end; 3383 } 3384 3385 set_bit(page_idx, var_table->bitmap); 3386 mutex_unlock(&var_table->bitmap_lock); 3387 3388 entry->address = var_table->hw_start_addr + 3389 (page_idx * var_table->stride_size); 3390 entry->page_idx = page_idx; 3391 entry->mmap_flag = MLX5_IB_MMAP_TYPE_VAR; 3392 3393 err = mlx5_rdma_user_mmap_entry_insert(c, entry, 3394 var_table->stride_size); 3395 if (err) 3396 goto err_insert; 3397 3398 return entry; 3399 3400 err_insert: 3401 mutex_lock(&var_table->bitmap_lock); 3402 clear_bit(page_idx, var_table->bitmap); 3403 mutex_unlock(&var_table->bitmap_lock); 3404 end: 3405 kfree(entry); 3406 return ERR_PTR(err); 3407 } 3408 3409 static int UVERBS_HANDLER(MLX5_IB_METHOD_VAR_OBJ_ALLOC)( 3410 struct uverbs_attr_bundle *attrs) 3411 { 3412 struct ib_uobject *uobj = uverbs_attr_get_uobject( 3413 attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE); 3414 struct mlx5_ib_ucontext *c; 3415 struct mlx5_user_mmap_entry *entry; 3416 u64 mmap_offset; 3417 u32 length; 3418 int err; 3419 3420 c = to_mucontext(ib_uverbs_get_ucontext(attrs)); 3421 if (IS_ERR(c)) 3422 return PTR_ERR(c); 3423 3424 entry = alloc_var_entry(c); 3425 if (IS_ERR(entry)) 3426 return PTR_ERR(entry); 3427 3428 mmap_offset = mlx5_entry_to_mmap_offset(entry); 3429 length = entry->rdma_entry.npages * PAGE_SIZE; 3430 uobj->object = entry; 3431 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE); 3432 3433 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET, 3434 &mmap_offset, sizeof(mmap_offset)); 3435 if (err) 3436 return err; 3437 3438 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID, 3439 &entry->page_idx, sizeof(entry->page_idx)); 3440 if (err) 3441 return err; 3442 3443 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH, 3444 &length, sizeof(length)); 3445 return err; 3446 } 3447 3448 DECLARE_UVERBS_NAMED_METHOD( 3449 MLX5_IB_METHOD_VAR_OBJ_ALLOC, 3450 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE, 3451 MLX5_IB_OBJECT_VAR, 3452 UVERBS_ACCESS_NEW, 3453 UA_MANDATORY), 3454 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID, 3455 UVERBS_ATTR_TYPE(u32), 3456 UA_MANDATORY), 3457 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH, 3458 UVERBS_ATTR_TYPE(u32), 3459 UA_MANDATORY), 3460 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET, 3461 UVERBS_ATTR_TYPE(u64), 3462 UA_MANDATORY)); 3463 3464 DECLARE_UVERBS_NAMED_METHOD_DESTROY( 3465 MLX5_IB_METHOD_VAR_OBJ_DESTROY, 3466 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_DESTROY_HANDLE, 3467 MLX5_IB_OBJECT_VAR, 3468 UVERBS_ACCESS_DESTROY, 3469 UA_MANDATORY)); 3470 3471 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_VAR, 3472 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup), 3473 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_ALLOC), 3474 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_DESTROY)); 3475 3476 static bool var_is_supported(struct ib_device *device) 3477 { 3478 struct mlx5_ib_dev *dev = to_mdev(device); 3479 3480 return (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 3481 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q); 3482 } 3483 3484 static struct mlx5_user_mmap_entry * 3485 alloc_uar_entry(struct mlx5_ib_ucontext *c, 3486 enum mlx5_ib_uapi_uar_alloc_type alloc_type) 3487 { 3488 struct mlx5_user_mmap_entry *entry; 3489 struct mlx5_ib_dev *dev; 3490 u32 uar_index; 3491 int err; 3492 3493 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 3494 if (!entry) 3495 return ERR_PTR(-ENOMEM); 3496 3497 dev = to_mdev(c->ibucontext.device); 3498 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index); 3499 if (err) 3500 goto end; 3501 3502 entry->page_idx = uar_index; 3503 entry->address = uar_index2paddress(dev, uar_index); 3504 if (alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF) 3505 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_WC; 3506 else 3507 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_NC; 3508 3509 err = mlx5_rdma_user_mmap_entry_insert(c, entry, PAGE_SIZE); 3510 if (err) 3511 goto err_insert; 3512 3513 return entry; 3514 3515 err_insert: 3516 mlx5_cmd_free_uar(dev->mdev, uar_index); 3517 end: 3518 kfree(entry); 3519 return ERR_PTR(err); 3520 } 3521 3522 static int UVERBS_HANDLER(MLX5_IB_METHOD_UAR_OBJ_ALLOC)( 3523 struct uverbs_attr_bundle *attrs) 3524 { 3525 struct ib_uobject *uobj = uverbs_attr_get_uobject( 3526 attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE); 3527 enum mlx5_ib_uapi_uar_alloc_type alloc_type; 3528 struct mlx5_ib_ucontext *c; 3529 struct mlx5_user_mmap_entry *entry; 3530 u64 mmap_offset; 3531 u32 length; 3532 int err; 3533 3534 c = to_mucontext(ib_uverbs_get_ucontext(attrs)); 3535 if (IS_ERR(c)) 3536 return PTR_ERR(c); 3537 3538 err = uverbs_get_const(&alloc_type, attrs, 3539 MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE); 3540 if (err) 3541 return err; 3542 3543 if (alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF && 3544 alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_NC) 3545 return -EOPNOTSUPP; 3546 3547 if (!to_mdev(c->ibucontext.device)->wc_support && 3548 alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF) 3549 return -EOPNOTSUPP; 3550 3551 entry = alloc_uar_entry(c, alloc_type); 3552 if (IS_ERR(entry)) 3553 return PTR_ERR(entry); 3554 3555 mmap_offset = mlx5_entry_to_mmap_offset(entry); 3556 length = entry->rdma_entry.npages * PAGE_SIZE; 3557 uobj->object = entry; 3558 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE); 3559 3560 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET, 3561 &mmap_offset, sizeof(mmap_offset)); 3562 if (err) 3563 return err; 3564 3565 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID, 3566 &entry->page_idx, sizeof(entry->page_idx)); 3567 if (err) 3568 return err; 3569 3570 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH, 3571 &length, sizeof(length)); 3572 return err; 3573 } 3574 3575 DECLARE_UVERBS_NAMED_METHOD( 3576 MLX5_IB_METHOD_UAR_OBJ_ALLOC, 3577 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE, 3578 MLX5_IB_OBJECT_UAR, 3579 UVERBS_ACCESS_NEW, 3580 UA_MANDATORY), 3581 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE, 3582 enum mlx5_ib_uapi_uar_alloc_type, 3583 UA_MANDATORY), 3584 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID, 3585 UVERBS_ATTR_TYPE(u32), 3586 UA_MANDATORY), 3587 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH, 3588 UVERBS_ATTR_TYPE(u32), 3589 UA_MANDATORY), 3590 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET, 3591 UVERBS_ATTR_TYPE(u64), 3592 UA_MANDATORY)); 3593 3594 DECLARE_UVERBS_NAMED_METHOD_DESTROY( 3595 MLX5_IB_METHOD_UAR_OBJ_DESTROY, 3596 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_DESTROY_HANDLE, 3597 MLX5_IB_OBJECT_UAR, 3598 UVERBS_ACCESS_DESTROY, 3599 UA_MANDATORY)); 3600 3601 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_UAR, 3602 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup), 3603 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_ALLOC), 3604 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_DESTROY)); 3605 3606 ADD_UVERBS_ATTRIBUTES_SIMPLE( 3607 mlx5_ib_flow_action, 3608 UVERBS_OBJECT_FLOW_ACTION, 3609 UVERBS_METHOD_FLOW_ACTION_ESP_CREATE, 3610 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS, 3611 enum mlx5_ib_uapi_flow_action_flags)); 3612 3613 ADD_UVERBS_ATTRIBUTES_SIMPLE( 3614 mlx5_ib_query_context, 3615 UVERBS_OBJECT_DEVICE, 3616 UVERBS_METHOD_QUERY_CONTEXT, 3617 UVERBS_ATTR_PTR_OUT( 3618 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX, 3619 UVERBS_ATTR_STRUCT(struct mlx5_ib_alloc_ucontext_resp, 3620 dump_fill_mkey), 3621 UA_MANDATORY)); 3622 3623 static const struct uapi_definition mlx5_ib_defs[] = { 3624 UAPI_DEF_CHAIN(mlx5_ib_devx_defs), 3625 UAPI_DEF_CHAIN(mlx5_ib_flow_defs), 3626 UAPI_DEF_CHAIN(mlx5_ib_qos_defs), 3627 UAPI_DEF_CHAIN(mlx5_ib_std_types_defs), 3628 UAPI_DEF_CHAIN(mlx5_ib_dm_defs), 3629 3630 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_FLOW_ACTION, 3631 &mlx5_ib_flow_action), 3632 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DEVICE, &mlx5_ib_query_context), 3633 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_VAR, 3634 UAPI_DEF_IS_OBJ_SUPPORTED(var_is_supported)), 3635 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_UAR), 3636 {} 3637 }; 3638 3639 static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev) 3640 { 3641 mlx5_ib_cleanup_multiport_master(dev); 3642 WARN_ON(!xa_empty(&dev->odp_mkeys)); 3643 mutex_destroy(&dev->cap_mask_mutex); 3644 WARN_ON(!xa_empty(&dev->sig_mrs)); 3645 WARN_ON(!bitmap_empty(dev->dm.memic_alloc_pages, MLX5_MAX_MEMIC_PAGES)); 3646 } 3647 3648 static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev) 3649 { 3650 struct mlx5_core_dev *mdev = dev->mdev; 3651 int err; 3652 int i; 3653 3654 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 3655 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 3656 dev->ib_dev.phys_port_cnt = dev->num_ports; 3657 dev->ib_dev.dev.parent = mdev->device; 3658 dev->ib_dev.lag_flags = RDMA_LAG_FLAGS_HASH_ALL_SLAVES; 3659 3660 for (i = 0; i < dev->num_ports; i++) { 3661 spin_lock_init(&dev->port[i].mp.mpi_lock); 3662 rwlock_init(&dev->port[i].roce.netdev_lock); 3663 dev->port[i].roce.dev = dev; 3664 dev->port[i].roce.native_port_num = i + 1; 3665 dev->port[i].roce.last_port_state = IB_PORT_DOWN; 3666 } 3667 3668 mlx5_ib_internal_fill_odp_caps(dev); 3669 3670 err = mlx5_ib_init_multiport_master(dev); 3671 if (err) 3672 return err; 3673 3674 err = set_has_smi_cap(dev); 3675 if (err) 3676 goto err_mp; 3677 3678 err = mlx5_query_max_pkeys(&dev->ib_dev, &dev->pkey_table_len); 3679 if (err) 3680 goto err_mp; 3681 3682 if (mlx5_use_mad_ifc(dev)) 3683 get_ext_port_caps(dev); 3684 3685 dev->ib_dev.num_comp_vectors = mlx5_comp_vectors_count(mdev); 3686 3687 mutex_init(&dev->cap_mask_mutex); 3688 INIT_LIST_HEAD(&dev->qp_list); 3689 spin_lock_init(&dev->reset_flow_resource_lock); 3690 xa_init(&dev->odp_mkeys); 3691 xa_init(&dev->sig_mrs); 3692 atomic_set(&dev->mkey_var, 0); 3693 3694 spin_lock_init(&dev->dm.lock); 3695 dev->dm.dev = mdev; 3696 return 0; 3697 3698 err_mp: 3699 mlx5_ib_cleanup_multiport_master(dev); 3700 return err; 3701 } 3702 3703 static int mlx5_ib_enable_driver(struct ib_device *dev) 3704 { 3705 struct mlx5_ib_dev *mdev = to_mdev(dev); 3706 int ret; 3707 3708 ret = mlx5_ib_test_wc(mdev); 3709 mlx5_ib_dbg(mdev, "Write-Combining %s", 3710 mdev->wc_support ? "supported" : "not supported"); 3711 3712 return ret; 3713 } 3714 3715 static const struct ib_device_ops mlx5_ib_dev_ops = { 3716 .owner = THIS_MODULE, 3717 .driver_id = RDMA_DRIVER_MLX5, 3718 .uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION, 3719 3720 .add_gid = mlx5_ib_add_gid, 3721 .alloc_mr = mlx5_ib_alloc_mr, 3722 .alloc_mr_integrity = mlx5_ib_alloc_mr_integrity, 3723 .alloc_pd = mlx5_ib_alloc_pd, 3724 .alloc_ucontext = mlx5_ib_alloc_ucontext, 3725 .attach_mcast = mlx5_ib_mcg_attach, 3726 .check_mr_status = mlx5_ib_check_mr_status, 3727 .create_ah = mlx5_ib_create_ah, 3728 .create_cq = mlx5_ib_create_cq, 3729 .create_qp = mlx5_ib_create_qp, 3730 .create_srq = mlx5_ib_create_srq, 3731 .create_user_ah = mlx5_ib_create_ah, 3732 .dealloc_pd = mlx5_ib_dealloc_pd, 3733 .dealloc_ucontext = mlx5_ib_dealloc_ucontext, 3734 .del_gid = mlx5_ib_del_gid, 3735 .dereg_mr = mlx5_ib_dereg_mr, 3736 .destroy_ah = mlx5_ib_destroy_ah, 3737 .destroy_cq = mlx5_ib_destroy_cq, 3738 .destroy_qp = mlx5_ib_destroy_qp, 3739 .destroy_srq = mlx5_ib_destroy_srq, 3740 .detach_mcast = mlx5_ib_mcg_detach, 3741 .disassociate_ucontext = mlx5_ib_disassociate_ucontext, 3742 .drain_rq = mlx5_ib_drain_rq, 3743 .drain_sq = mlx5_ib_drain_sq, 3744 .enable_driver = mlx5_ib_enable_driver, 3745 .get_dev_fw_str = get_dev_fw_str, 3746 .get_dma_mr = mlx5_ib_get_dma_mr, 3747 .get_link_layer = mlx5_ib_port_link_layer, 3748 .map_mr_sg = mlx5_ib_map_mr_sg, 3749 .map_mr_sg_pi = mlx5_ib_map_mr_sg_pi, 3750 .mmap = mlx5_ib_mmap, 3751 .mmap_free = mlx5_ib_mmap_free, 3752 .modify_cq = mlx5_ib_modify_cq, 3753 .modify_device = mlx5_ib_modify_device, 3754 .modify_port = mlx5_ib_modify_port, 3755 .modify_qp = mlx5_ib_modify_qp, 3756 .modify_srq = mlx5_ib_modify_srq, 3757 .poll_cq = mlx5_ib_poll_cq, 3758 .post_recv = mlx5_ib_post_recv_nodrain, 3759 .post_send = mlx5_ib_post_send_nodrain, 3760 .post_srq_recv = mlx5_ib_post_srq_recv, 3761 .process_mad = mlx5_ib_process_mad, 3762 .query_ah = mlx5_ib_query_ah, 3763 .query_device = mlx5_ib_query_device, 3764 .query_gid = mlx5_ib_query_gid, 3765 .query_pkey = mlx5_ib_query_pkey, 3766 .query_qp = mlx5_ib_query_qp, 3767 .query_srq = mlx5_ib_query_srq, 3768 .query_ucontext = mlx5_ib_query_ucontext, 3769 .reg_user_mr = mlx5_ib_reg_user_mr, 3770 .reg_user_mr_dmabuf = mlx5_ib_reg_user_mr_dmabuf, 3771 .req_notify_cq = mlx5_ib_arm_cq, 3772 .rereg_user_mr = mlx5_ib_rereg_user_mr, 3773 .resize_cq = mlx5_ib_resize_cq, 3774 3775 INIT_RDMA_OBJ_SIZE(ib_ah, mlx5_ib_ah, ibah), 3776 INIT_RDMA_OBJ_SIZE(ib_counters, mlx5_ib_mcounters, ibcntrs), 3777 INIT_RDMA_OBJ_SIZE(ib_cq, mlx5_ib_cq, ibcq), 3778 INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd), 3779 INIT_RDMA_OBJ_SIZE(ib_srq, mlx5_ib_srq, ibsrq), 3780 INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext), 3781 }; 3782 3783 static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = { 3784 .rdma_netdev_get_params = mlx5_ib_rn_get_params, 3785 }; 3786 3787 static const struct ib_device_ops mlx5_ib_dev_sriov_ops = { 3788 .get_vf_config = mlx5_ib_get_vf_config, 3789 .get_vf_guid = mlx5_ib_get_vf_guid, 3790 .get_vf_stats = mlx5_ib_get_vf_stats, 3791 .set_vf_guid = mlx5_ib_set_vf_guid, 3792 .set_vf_link_state = mlx5_ib_set_vf_link_state, 3793 }; 3794 3795 static const struct ib_device_ops mlx5_ib_dev_mw_ops = { 3796 .alloc_mw = mlx5_ib_alloc_mw, 3797 .dealloc_mw = mlx5_ib_dealloc_mw, 3798 3799 INIT_RDMA_OBJ_SIZE(ib_mw, mlx5_ib_mw, ibmw), 3800 }; 3801 3802 static const struct ib_device_ops mlx5_ib_dev_xrc_ops = { 3803 .alloc_xrcd = mlx5_ib_alloc_xrcd, 3804 .dealloc_xrcd = mlx5_ib_dealloc_xrcd, 3805 3806 INIT_RDMA_OBJ_SIZE(ib_xrcd, mlx5_ib_xrcd, ibxrcd), 3807 }; 3808 3809 static int mlx5_ib_init_var_table(struct mlx5_ib_dev *dev) 3810 { 3811 struct mlx5_core_dev *mdev = dev->mdev; 3812 struct mlx5_var_table *var_table = &dev->var_table; 3813 u8 log_doorbell_bar_size; 3814 u8 log_doorbell_stride; 3815 u64 bar_size; 3816 3817 log_doorbell_bar_size = MLX5_CAP_DEV_VDPA_EMULATION(mdev, 3818 log_doorbell_bar_size); 3819 log_doorbell_stride = MLX5_CAP_DEV_VDPA_EMULATION(mdev, 3820 log_doorbell_stride); 3821 var_table->hw_start_addr = dev->mdev->bar_addr + 3822 MLX5_CAP64_DEV_VDPA_EMULATION(mdev, 3823 doorbell_bar_offset); 3824 bar_size = (1ULL << log_doorbell_bar_size) * 4096; 3825 var_table->stride_size = 1ULL << log_doorbell_stride; 3826 var_table->num_var_hw_entries = div_u64(bar_size, 3827 var_table->stride_size); 3828 mutex_init(&var_table->bitmap_lock); 3829 var_table->bitmap = bitmap_zalloc(var_table->num_var_hw_entries, 3830 GFP_KERNEL); 3831 return (var_table->bitmap) ? 0 : -ENOMEM; 3832 } 3833 3834 static void mlx5_ib_stage_caps_cleanup(struct mlx5_ib_dev *dev) 3835 { 3836 bitmap_free(dev->var_table.bitmap); 3837 } 3838 3839 static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev) 3840 { 3841 struct mlx5_core_dev *mdev = dev->mdev; 3842 int err; 3843 3844 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 3845 IS_ENABLED(CONFIG_MLX5_CORE_IPOIB)) 3846 ib_set_device_ops(&dev->ib_dev, 3847 &mlx5_ib_dev_ipoib_enhanced_ops); 3848 3849 if (mlx5_core_is_pf(mdev)) 3850 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops); 3851 3852 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence)); 3853 3854 if (MLX5_CAP_GEN(mdev, imaicl)) 3855 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops); 3856 3857 if (MLX5_CAP_GEN(mdev, xrc)) 3858 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops); 3859 3860 if (MLX5_CAP_DEV_MEM(mdev, memic) || 3861 MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 3862 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM) 3863 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops); 3864 3865 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops); 3866 3867 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)) 3868 dev->ib_dev.driver_def = mlx5_ib_defs; 3869 3870 err = init_node_data(dev); 3871 if (err) 3872 return err; 3873 3874 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && 3875 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) || 3876 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 3877 mutex_init(&dev->lb.mutex); 3878 3879 if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 3880 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) { 3881 err = mlx5_ib_init_var_table(dev); 3882 if (err) 3883 return err; 3884 } 3885 3886 dev->ib_dev.use_cq_dim = true; 3887 3888 return 0; 3889 } 3890 3891 static const struct ib_device_ops mlx5_ib_dev_port_ops = { 3892 .get_port_immutable = mlx5_port_immutable, 3893 .query_port = mlx5_ib_query_port, 3894 }; 3895 3896 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev) 3897 { 3898 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops); 3899 return 0; 3900 } 3901 3902 static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = { 3903 .get_port_immutable = mlx5_port_rep_immutable, 3904 .query_port = mlx5_ib_rep_query_port, 3905 .query_pkey = mlx5_ib_rep_query_pkey, 3906 }; 3907 3908 static int mlx5_ib_stage_raw_eth_non_default_cb(struct mlx5_ib_dev *dev) 3909 { 3910 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops); 3911 return 0; 3912 } 3913 3914 static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = { 3915 .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table, 3916 .create_wq = mlx5_ib_create_wq, 3917 .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table, 3918 .destroy_wq = mlx5_ib_destroy_wq, 3919 .get_netdev = mlx5_ib_get_netdev, 3920 .modify_wq = mlx5_ib_modify_wq, 3921 3922 INIT_RDMA_OBJ_SIZE(ib_rwq_ind_table, mlx5_ib_rwq_ind_table, 3923 ib_rwq_ind_tbl), 3924 }; 3925 3926 static int mlx5_ib_roce_init(struct mlx5_ib_dev *dev) 3927 { 3928 struct mlx5_core_dev *mdev = dev->mdev; 3929 enum rdma_link_layer ll; 3930 int port_type_cap; 3931 u8 port_num = 0; 3932 int err; 3933 3934 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 3935 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 3936 3937 if (ll == IB_LINK_LAYER_ETHERNET) { 3938 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops); 3939 3940 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3941 3942 /* Register only for native ports */ 3943 err = mlx5_add_netdev_notifier(dev, port_num); 3944 if (err || dev->is_rep || !mlx5_is_roce_enabled(mdev)) 3945 /* 3946 * We don't enable ETH interface for 3947 * 1. IB representors 3948 * 2. User disabled ROCE through devlink interface 3949 */ 3950 return err; 3951 3952 err = mlx5_enable_eth(dev); 3953 if (err) 3954 goto cleanup; 3955 } 3956 3957 return 0; 3958 cleanup: 3959 mlx5_remove_netdev_notifier(dev, port_num); 3960 return err; 3961 } 3962 3963 static void mlx5_ib_roce_cleanup(struct mlx5_ib_dev *dev) 3964 { 3965 struct mlx5_core_dev *mdev = dev->mdev; 3966 enum rdma_link_layer ll; 3967 int port_type_cap; 3968 u8 port_num; 3969 3970 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 3971 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 3972 3973 if (ll == IB_LINK_LAYER_ETHERNET) { 3974 if (!dev->is_rep) 3975 mlx5_disable_eth(dev); 3976 3977 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3978 mlx5_remove_netdev_notifier(dev, port_num); 3979 } 3980 } 3981 3982 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev) 3983 { 3984 mlx5_ib_init_cong_debugfs(dev, 3985 mlx5_core_native_port_num(dev->mdev) - 1); 3986 return 0; 3987 } 3988 3989 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev) 3990 { 3991 mlx5_ib_cleanup_cong_debugfs(dev, 3992 mlx5_core_native_port_num(dev->mdev) - 1); 3993 } 3994 3995 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev) 3996 { 3997 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev); 3998 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar); 3999 } 4000 4001 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev) 4002 { 4003 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar); 4004 } 4005 4006 static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev) 4007 { 4008 int err; 4009 4010 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false); 4011 if (err) 4012 return err; 4013 4014 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true); 4015 if (err) 4016 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4017 4018 return err; 4019 } 4020 4021 static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev) 4022 { 4023 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 4024 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4025 } 4026 4027 static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev) 4028 { 4029 const char *name; 4030 4031 rdma_set_device_sysfs_group(&dev->ib_dev, &mlx5_attr_group); 4032 if (!mlx5_lag_is_roce(dev->mdev)) 4033 name = "mlx5_%d"; 4034 else 4035 name = "mlx5_bond_%d"; 4036 return ib_register_device(&dev->ib_dev, name, &dev->mdev->pdev->dev); 4037 } 4038 4039 static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev) 4040 { 4041 int err; 4042 4043 err = mlx5_mr_cache_cleanup(dev); 4044 if (err) 4045 mlx5_ib_warn(dev, "mr cache cleanup failed\n"); 4046 4047 if (dev->umrc.qp) 4048 mlx5_ib_destroy_qp(dev->umrc.qp, NULL); 4049 if (dev->umrc.cq) 4050 ib_free_cq(dev->umrc.cq); 4051 if (dev->umrc.pd) 4052 ib_dealloc_pd(dev->umrc.pd); 4053 } 4054 4055 static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev) 4056 { 4057 ib_unregister_device(&dev->ib_dev); 4058 } 4059 4060 enum { 4061 MAX_UMR_WR = 128, 4062 }; 4063 4064 static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev) 4065 { 4066 struct ib_qp_init_attr *init_attr = NULL; 4067 struct ib_qp_attr *attr = NULL; 4068 struct ib_pd *pd; 4069 struct ib_cq *cq; 4070 struct ib_qp *qp; 4071 int ret; 4072 4073 attr = kzalloc(sizeof(*attr), GFP_KERNEL); 4074 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL); 4075 if (!attr || !init_attr) { 4076 ret = -ENOMEM; 4077 goto error_0; 4078 } 4079 4080 pd = ib_alloc_pd(&dev->ib_dev, 0); 4081 if (IS_ERR(pd)) { 4082 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n"); 4083 ret = PTR_ERR(pd); 4084 goto error_0; 4085 } 4086 4087 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ); 4088 if (IS_ERR(cq)) { 4089 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n"); 4090 ret = PTR_ERR(cq); 4091 goto error_2; 4092 } 4093 4094 init_attr->send_cq = cq; 4095 init_attr->recv_cq = cq; 4096 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR; 4097 init_attr->cap.max_send_wr = MAX_UMR_WR; 4098 init_attr->cap.max_send_sge = 1; 4099 init_attr->qp_type = MLX5_IB_QPT_REG_UMR; 4100 init_attr->port_num = 1; 4101 qp = mlx5_ib_create_qp(pd, init_attr, NULL); 4102 if (IS_ERR(qp)) { 4103 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n"); 4104 ret = PTR_ERR(qp); 4105 goto error_3; 4106 } 4107 qp->device = &dev->ib_dev; 4108 qp->real_qp = qp; 4109 qp->uobject = NULL; 4110 qp->qp_type = MLX5_IB_QPT_REG_UMR; 4111 qp->send_cq = init_attr->send_cq; 4112 qp->recv_cq = init_attr->recv_cq; 4113 4114 attr->qp_state = IB_QPS_INIT; 4115 attr->port_num = 1; 4116 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX | 4117 IB_QP_PORT, NULL); 4118 if (ret) { 4119 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n"); 4120 goto error_4; 4121 } 4122 4123 memset(attr, 0, sizeof(*attr)); 4124 attr->qp_state = IB_QPS_RTR; 4125 attr->path_mtu = IB_MTU_256; 4126 4127 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 4128 if (ret) { 4129 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n"); 4130 goto error_4; 4131 } 4132 4133 memset(attr, 0, sizeof(*attr)); 4134 attr->qp_state = IB_QPS_RTS; 4135 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 4136 if (ret) { 4137 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n"); 4138 goto error_4; 4139 } 4140 4141 dev->umrc.qp = qp; 4142 dev->umrc.cq = cq; 4143 dev->umrc.pd = pd; 4144 4145 sema_init(&dev->umrc.sem, MAX_UMR_WR); 4146 ret = mlx5_mr_cache_init(dev); 4147 if (ret) { 4148 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 4149 goto error_4; 4150 } 4151 4152 kfree(attr); 4153 kfree(init_attr); 4154 4155 return 0; 4156 4157 error_4: 4158 mlx5_ib_destroy_qp(qp, NULL); 4159 dev->umrc.qp = NULL; 4160 4161 error_3: 4162 ib_free_cq(cq); 4163 dev->umrc.cq = NULL; 4164 4165 error_2: 4166 ib_dealloc_pd(pd); 4167 dev->umrc.pd = NULL; 4168 4169 error_0: 4170 kfree(attr); 4171 kfree(init_attr); 4172 return ret; 4173 } 4174 4175 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev) 4176 { 4177 struct dentry *root; 4178 4179 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4180 return 0; 4181 4182 mutex_init(&dev->delay_drop.lock); 4183 dev->delay_drop.dev = dev; 4184 dev->delay_drop.activate = false; 4185 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000; 4186 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler); 4187 atomic_set(&dev->delay_drop.rqs_cnt, 0); 4188 atomic_set(&dev->delay_drop.events_cnt, 0); 4189 4190 if (!mlx5_debugfs_root) 4191 return 0; 4192 4193 root = debugfs_create_dir("delay_drop", dev->mdev->priv.dbg_root); 4194 dev->delay_drop.dir_debugfs = root; 4195 4196 debugfs_create_atomic_t("num_timeout_events", 0400, root, 4197 &dev->delay_drop.events_cnt); 4198 debugfs_create_atomic_t("num_rqs", 0400, root, 4199 &dev->delay_drop.rqs_cnt); 4200 debugfs_create_file("timeout", 0600, root, &dev->delay_drop, 4201 &fops_delay_drop_timeout); 4202 return 0; 4203 } 4204 4205 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev) 4206 { 4207 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4208 return; 4209 4210 cancel_work_sync(&dev->delay_drop.delay_drop_work); 4211 if (!dev->delay_drop.dir_debugfs) 4212 return; 4213 4214 debugfs_remove_recursive(dev->delay_drop.dir_debugfs); 4215 dev->delay_drop.dir_debugfs = NULL; 4216 } 4217 4218 static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev) 4219 { 4220 dev->mdev_events.notifier_call = mlx5_ib_event; 4221 mlx5_notifier_register(dev->mdev, &dev->mdev_events); 4222 return 0; 4223 } 4224 4225 static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev) 4226 { 4227 mlx5_notifier_unregister(dev->mdev, &dev->mdev_events); 4228 } 4229 4230 void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 4231 const struct mlx5_ib_profile *profile, 4232 int stage) 4233 { 4234 dev->ib_active = false; 4235 4236 /* Number of stages to cleanup */ 4237 while (stage) { 4238 stage--; 4239 if (profile->stage[stage].cleanup) 4240 profile->stage[stage].cleanup(dev); 4241 } 4242 4243 kfree(dev->port); 4244 ib_dealloc_device(&dev->ib_dev); 4245 } 4246 4247 int __mlx5_ib_add(struct mlx5_ib_dev *dev, 4248 const struct mlx5_ib_profile *profile) 4249 { 4250 int err; 4251 int i; 4252 4253 dev->profile = profile; 4254 4255 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) { 4256 if (profile->stage[i].init) { 4257 err = profile->stage[i].init(dev); 4258 if (err) 4259 goto err_out; 4260 } 4261 } 4262 4263 dev->ib_active = true; 4264 return 0; 4265 4266 err_out: 4267 /* Clean up stages which were initialized */ 4268 while (i) { 4269 i--; 4270 if (profile->stage[i].cleanup) 4271 profile->stage[i].cleanup(dev); 4272 } 4273 return -ENOMEM; 4274 } 4275 4276 static const struct mlx5_ib_profile pf_profile = { 4277 STAGE_CREATE(MLX5_IB_STAGE_INIT, 4278 mlx5_ib_stage_init_init, 4279 mlx5_ib_stage_init_cleanup), 4280 STAGE_CREATE(MLX5_IB_STAGE_FS, 4281 mlx5_ib_fs_init, 4282 mlx5_ib_fs_cleanup), 4283 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 4284 mlx5_ib_stage_caps_init, 4285 mlx5_ib_stage_caps_cleanup), 4286 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 4287 mlx5_ib_stage_non_default_cb, 4288 NULL), 4289 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 4290 mlx5_ib_roce_init, 4291 mlx5_ib_roce_cleanup), 4292 STAGE_CREATE(MLX5_IB_STAGE_QP, 4293 mlx5_init_qp_table, 4294 mlx5_cleanup_qp_table), 4295 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 4296 mlx5_init_srq_table, 4297 mlx5_cleanup_srq_table), 4298 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 4299 mlx5_ib_dev_res_init, 4300 mlx5_ib_dev_res_cleanup), 4301 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 4302 mlx5_ib_stage_dev_notifier_init, 4303 mlx5_ib_stage_dev_notifier_cleanup), 4304 STAGE_CREATE(MLX5_IB_STAGE_ODP, 4305 mlx5_ib_odp_init_one, 4306 mlx5_ib_odp_cleanup_one), 4307 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 4308 mlx5_ib_counters_init, 4309 mlx5_ib_counters_cleanup), 4310 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 4311 mlx5_ib_stage_cong_debugfs_init, 4312 mlx5_ib_stage_cong_debugfs_cleanup), 4313 STAGE_CREATE(MLX5_IB_STAGE_UAR, 4314 mlx5_ib_stage_uar_init, 4315 mlx5_ib_stage_uar_cleanup), 4316 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 4317 mlx5_ib_stage_bfrag_init, 4318 mlx5_ib_stage_bfrag_cleanup), 4319 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 4320 NULL, 4321 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 4322 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 4323 mlx5_ib_devx_init, 4324 mlx5_ib_devx_cleanup), 4325 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 4326 mlx5_ib_stage_ib_reg_init, 4327 mlx5_ib_stage_ib_reg_cleanup), 4328 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 4329 mlx5_ib_stage_post_ib_reg_umr_init, 4330 NULL), 4331 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP, 4332 mlx5_ib_stage_delay_drop_init, 4333 mlx5_ib_stage_delay_drop_cleanup), 4334 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK, 4335 mlx5_ib_restrack_init, 4336 NULL), 4337 }; 4338 4339 const struct mlx5_ib_profile raw_eth_profile = { 4340 STAGE_CREATE(MLX5_IB_STAGE_INIT, 4341 mlx5_ib_stage_init_init, 4342 mlx5_ib_stage_init_cleanup), 4343 STAGE_CREATE(MLX5_IB_STAGE_FS, 4344 mlx5_ib_fs_init, 4345 mlx5_ib_fs_cleanup), 4346 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 4347 mlx5_ib_stage_caps_init, 4348 mlx5_ib_stage_caps_cleanup), 4349 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 4350 mlx5_ib_stage_raw_eth_non_default_cb, 4351 NULL), 4352 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 4353 mlx5_ib_roce_init, 4354 mlx5_ib_roce_cleanup), 4355 STAGE_CREATE(MLX5_IB_STAGE_QP, 4356 mlx5_init_qp_table, 4357 mlx5_cleanup_qp_table), 4358 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 4359 mlx5_init_srq_table, 4360 mlx5_cleanup_srq_table), 4361 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 4362 mlx5_ib_dev_res_init, 4363 mlx5_ib_dev_res_cleanup), 4364 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 4365 mlx5_ib_stage_dev_notifier_init, 4366 mlx5_ib_stage_dev_notifier_cleanup), 4367 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 4368 mlx5_ib_counters_init, 4369 mlx5_ib_counters_cleanup), 4370 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 4371 mlx5_ib_stage_cong_debugfs_init, 4372 mlx5_ib_stage_cong_debugfs_cleanup), 4373 STAGE_CREATE(MLX5_IB_STAGE_UAR, 4374 mlx5_ib_stage_uar_init, 4375 mlx5_ib_stage_uar_cleanup), 4376 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 4377 mlx5_ib_stage_bfrag_init, 4378 mlx5_ib_stage_bfrag_cleanup), 4379 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 4380 NULL, 4381 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 4382 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 4383 mlx5_ib_devx_init, 4384 mlx5_ib_devx_cleanup), 4385 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 4386 mlx5_ib_stage_ib_reg_init, 4387 mlx5_ib_stage_ib_reg_cleanup), 4388 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 4389 mlx5_ib_stage_post_ib_reg_umr_init, 4390 NULL), 4391 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK, 4392 mlx5_ib_restrack_init, 4393 NULL), 4394 }; 4395 4396 static int mlx5r_mp_probe(struct auxiliary_device *adev, 4397 const struct auxiliary_device_id *id) 4398 { 4399 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev); 4400 struct mlx5_core_dev *mdev = idev->mdev; 4401 struct mlx5_ib_multiport_info *mpi; 4402 struct mlx5_ib_dev *dev; 4403 bool bound = false; 4404 int err; 4405 4406 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 4407 if (!mpi) 4408 return -ENOMEM; 4409 4410 mpi->mdev = mdev; 4411 err = mlx5_query_nic_vport_system_image_guid(mdev, 4412 &mpi->sys_image_guid); 4413 if (err) { 4414 kfree(mpi); 4415 return err; 4416 } 4417 4418 mutex_lock(&mlx5_ib_multiport_mutex); 4419 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) { 4420 if (dev->sys_image_guid == mpi->sys_image_guid) 4421 bound = mlx5_ib_bind_slave_port(dev, mpi); 4422 4423 if (bound) { 4424 rdma_roce_rescan_device(&dev->ib_dev); 4425 break; 4426 } 4427 } 4428 4429 if (!bound) { 4430 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 4431 dev_dbg(mdev->device, 4432 "no suitable IB device found to bind to, added to unaffiliated list.\n"); 4433 } 4434 mutex_unlock(&mlx5_ib_multiport_mutex); 4435 4436 dev_set_drvdata(&adev->dev, mpi); 4437 return 0; 4438 } 4439 4440 static void mlx5r_mp_remove(struct auxiliary_device *adev) 4441 { 4442 struct mlx5_ib_multiport_info *mpi; 4443 4444 mpi = dev_get_drvdata(&adev->dev); 4445 mutex_lock(&mlx5_ib_multiport_mutex); 4446 if (mpi->ibdev) 4447 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi); 4448 list_del(&mpi->list); 4449 mutex_unlock(&mlx5_ib_multiport_mutex); 4450 kfree(mpi); 4451 } 4452 4453 static int mlx5r_probe(struct auxiliary_device *adev, 4454 const struct auxiliary_device_id *id) 4455 { 4456 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev); 4457 struct mlx5_core_dev *mdev = idev->mdev; 4458 const struct mlx5_ib_profile *profile; 4459 int port_type_cap, num_ports, ret; 4460 enum rdma_link_layer ll; 4461 struct mlx5_ib_dev *dev; 4462 4463 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4464 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4465 4466 num_ports = max(MLX5_CAP_GEN(mdev, num_ports), 4467 MLX5_CAP_GEN(mdev, num_vhca_ports)); 4468 dev = ib_alloc_device(mlx5_ib_dev, ib_dev); 4469 if (!dev) 4470 return -ENOMEM; 4471 dev->port = kcalloc(num_ports, sizeof(*dev->port), 4472 GFP_KERNEL); 4473 if (!dev->port) { 4474 ib_dealloc_device(&dev->ib_dev); 4475 return -ENOMEM; 4476 } 4477 4478 dev->mdev = mdev; 4479 dev->num_ports = num_ports; 4480 4481 if (ll == IB_LINK_LAYER_ETHERNET && !mlx5_is_roce_enabled(mdev)) 4482 profile = &raw_eth_profile; 4483 else 4484 profile = &pf_profile; 4485 4486 ret = __mlx5_ib_add(dev, profile); 4487 if (ret) { 4488 kfree(dev->port); 4489 ib_dealloc_device(&dev->ib_dev); 4490 return ret; 4491 } 4492 4493 dev_set_drvdata(&adev->dev, dev); 4494 return 0; 4495 } 4496 4497 static void mlx5r_remove(struct auxiliary_device *adev) 4498 { 4499 struct mlx5_ib_dev *dev; 4500 4501 dev = dev_get_drvdata(&adev->dev); 4502 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX); 4503 } 4504 4505 static const struct auxiliary_device_id mlx5r_mp_id_table[] = { 4506 { .name = MLX5_ADEV_NAME ".multiport", }, 4507 {}, 4508 }; 4509 4510 static const struct auxiliary_device_id mlx5r_id_table[] = { 4511 { .name = MLX5_ADEV_NAME ".rdma", }, 4512 {}, 4513 }; 4514 4515 MODULE_DEVICE_TABLE(auxiliary, mlx5r_mp_id_table); 4516 MODULE_DEVICE_TABLE(auxiliary, mlx5r_id_table); 4517 4518 static struct auxiliary_driver mlx5r_mp_driver = { 4519 .name = "multiport", 4520 .probe = mlx5r_mp_probe, 4521 .remove = mlx5r_mp_remove, 4522 .id_table = mlx5r_mp_id_table, 4523 }; 4524 4525 static struct auxiliary_driver mlx5r_driver = { 4526 .name = "rdma", 4527 .probe = mlx5r_probe, 4528 .remove = mlx5r_remove, 4529 .id_table = mlx5r_id_table, 4530 }; 4531 4532 static int __init mlx5_ib_init(void) 4533 { 4534 int ret; 4535 4536 xlt_emergency_page = (void *)__get_free_page(GFP_KERNEL); 4537 if (!xlt_emergency_page) 4538 return -ENOMEM; 4539 4540 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0); 4541 if (!mlx5_ib_event_wq) { 4542 free_page((unsigned long)xlt_emergency_page); 4543 return -ENOMEM; 4544 } 4545 4546 mlx5_ib_odp_init(); 4547 ret = mlx5r_rep_init(); 4548 if (ret) 4549 goto rep_err; 4550 ret = auxiliary_driver_register(&mlx5r_mp_driver); 4551 if (ret) 4552 goto mp_err; 4553 ret = auxiliary_driver_register(&mlx5r_driver); 4554 if (ret) 4555 goto drv_err; 4556 return 0; 4557 4558 drv_err: 4559 auxiliary_driver_unregister(&mlx5r_mp_driver); 4560 mp_err: 4561 mlx5r_rep_cleanup(); 4562 rep_err: 4563 destroy_workqueue(mlx5_ib_event_wq); 4564 free_page((unsigned long)xlt_emergency_page); 4565 return ret; 4566 } 4567 4568 static void __exit mlx5_ib_cleanup(void) 4569 { 4570 auxiliary_driver_unregister(&mlx5r_driver); 4571 auxiliary_driver_unregister(&mlx5r_mp_driver); 4572 mlx5r_rep_cleanup(); 4573 4574 destroy_workqueue(mlx5_ib_event_wq); 4575 free_page((unsigned long)xlt_emergency_page); 4576 } 4577 4578 module_init(mlx5_ib_init); 4579 module_exit(mlx5_ib_cleanup); 4580