1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/debugfs.h> 34 #include <linux/highmem.h> 35 #include <linux/module.h> 36 #include <linux/init.h> 37 #include <linux/errno.h> 38 #include <linux/pci.h> 39 #include <linux/dma-mapping.h> 40 #include <linux/slab.h> 41 #if defined(CONFIG_X86) 42 #include <asm/pat.h> 43 #endif 44 #include <linux/sched.h> 45 #include <linux/sched/mm.h> 46 #include <linux/sched/task.h> 47 #include <linux/delay.h> 48 #include <rdma/ib_user_verbs.h> 49 #include <rdma/ib_addr.h> 50 #include <rdma/ib_cache.h> 51 #include <linux/mlx5/port.h> 52 #include <linux/mlx5/vport.h> 53 #include <linux/list.h> 54 #include <rdma/ib_smi.h> 55 #include <rdma/ib_umem.h> 56 #include <linux/in.h> 57 #include <linux/etherdevice.h> 58 #include <linux/mlx5/fs.h> 59 #include <linux/mlx5/vport.h> 60 #include "mlx5_ib.h" 61 #include "cmd.h" 62 #include <linux/mlx5/vport.h> 63 64 #define DRIVER_NAME "mlx5_ib" 65 #define DRIVER_VERSION "5.0-0" 66 67 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 68 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver"); 69 MODULE_LICENSE("Dual BSD/GPL"); 70 71 static char mlx5_version[] = 72 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v" 73 DRIVER_VERSION "\n"; 74 75 enum { 76 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 77 }; 78 79 static enum rdma_link_layer 80 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 81 { 82 switch (port_type_cap) { 83 case MLX5_CAP_PORT_TYPE_IB: 84 return IB_LINK_LAYER_INFINIBAND; 85 case MLX5_CAP_PORT_TYPE_ETH: 86 return IB_LINK_LAYER_ETHERNET; 87 default: 88 return IB_LINK_LAYER_UNSPECIFIED; 89 } 90 } 91 92 static enum rdma_link_layer 93 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num) 94 { 95 struct mlx5_ib_dev *dev = to_mdev(device); 96 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 97 98 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 99 } 100 101 static int get_port_state(struct ib_device *ibdev, 102 u8 port_num, 103 enum ib_port_state *state) 104 { 105 struct ib_port_attr attr; 106 int ret; 107 108 memset(&attr, 0, sizeof(attr)); 109 ret = mlx5_ib_query_port(ibdev, port_num, &attr); 110 if (!ret) 111 *state = attr.state; 112 return ret; 113 } 114 115 static int mlx5_netdev_event(struct notifier_block *this, 116 unsigned long event, void *ptr) 117 { 118 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 119 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev, 120 roce.nb); 121 122 switch (event) { 123 case NETDEV_REGISTER: 124 case NETDEV_UNREGISTER: 125 write_lock(&ibdev->roce.netdev_lock); 126 if (ndev->dev.parent == &ibdev->mdev->pdev->dev) 127 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ? 128 NULL : ndev; 129 write_unlock(&ibdev->roce.netdev_lock); 130 break; 131 132 case NETDEV_CHANGE: 133 case NETDEV_UP: 134 case NETDEV_DOWN: { 135 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(ibdev->mdev); 136 struct net_device *upper = NULL; 137 138 if (lag_ndev) { 139 upper = netdev_master_upper_dev_get(lag_ndev); 140 dev_put(lag_ndev); 141 } 142 143 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev)) 144 && ibdev->ib_active) { 145 struct ib_event ibev = { }; 146 enum ib_port_state port_state; 147 148 if (get_port_state(&ibdev->ib_dev, 1, &port_state)) 149 return NOTIFY_DONE; 150 151 if (ibdev->roce.last_port_state == port_state) 152 return NOTIFY_DONE; 153 154 ibdev->roce.last_port_state = port_state; 155 ibev.device = &ibdev->ib_dev; 156 if (port_state == IB_PORT_DOWN) 157 ibev.event = IB_EVENT_PORT_ERR; 158 else if (port_state == IB_PORT_ACTIVE) 159 ibev.event = IB_EVENT_PORT_ACTIVE; 160 else 161 return NOTIFY_DONE; 162 163 ibev.element.port_num = 1; 164 ib_dispatch_event(&ibev); 165 } 166 break; 167 } 168 169 default: 170 break; 171 } 172 173 return NOTIFY_DONE; 174 } 175 176 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device, 177 u8 port_num) 178 { 179 struct mlx5_ib_dev *ibdev = to_mdev(device); 180 struct net_device *ndev; 181 182 ndev = mlx5_lag_get_roce_netdev(ibdev->mdev); 183 if (ndev) 184 return ndev; 185 186 /* Ensure ndev does not disappear before we invoke dev_hold() 187 */ 188 read_lock(&ibdev->roce.netdev_lock); 189 ndev = ibdev->roce.netdev; 190 if (ndev) 191 dev_hold(ndev); 192 read_unlock(&ibdev->roce.netdev_lock); 193 194 return ndev; 195 } 196 197 static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed, 198 u8 *active_width) 199 { 200 switch (eth_proto_oper) { 201 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII): 202 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX): 203 case MLX5E_PROT_MASK(MLX5E_100BASE_TX): 204 case MLX5E_PROT_MASK(MLX5E_1000BASE_T): 205 *active_width = IB_WIDTH_1X; 206 *active_speed = IB_SPEED_SDR; 207 break; 208 case MLX5E_PROT_MASK(MLX5E_10GBASE_T): 209 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4): 210 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4): 211 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR): 212 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR): 213 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR): 214 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER): 215 *active_width = IB_WIDTH_1X; 216 *active_speed = IB_SPEED_QDR; 217 break; 218 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR): 219 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR): 220 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR): 221 *active_width = IB_WIDTH_1X; 222 *active_speed = IB_SPEED_EDR; 223 break; 224 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4): 225 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4): 226 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4): 227 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4): 228 *active_width = IB_WIDTH_4X; 229 *active_speed = IB_SPEED_QDR; 230 break; 231 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2): 232 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2): 233 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2): 234 *active_width = IB_WIDTH_1X; 235 *active_speed = IB_SPEED_HDR; 236 break; 237 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4): 238 *active_width = IB_WIDTH_4X; 239 *active_speed = IB_SPEED_FDR; 240 break; 241 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4): 242 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4): 243 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4): 244 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4): 245 *active_width = IB_WIDTH_4X; 246 *active_speed = IB_SPEED_EDR; 247 break; 248 default: 249 return -EINVAL; 250 } 251 252 return 0; 253 } 254 255 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num, 256 struct ib_port_attr *props) 257 { 258 struct mlx5_ib_dev *dev = to_mdev(device); 259 struct mlx5_core_dev *mdev = dev->mdev; 260 struct net_device *ndev, *upper; 261 enum ib_mtu ndev_ib_mtu; 262 u16 qkey_viol_cntr; 263 u32 eth_prot_oper; 264 int err; 265 266 /* Possible bad flows are checked before filling out props so in case 267 * of an error it will still be zeroed out. 268 */ 269 err = mlx5_query_port_eth_proto_oper(mdev, ð_prot_oper, port_num); 270 if (err) 271 return err; 272 273 translate_eth_proto_oper(eth_prot_oper, &props->active_speed, 274 &props->active_width); 275 276 props->port_cap_flags |= IB_PORT_CM_SUP; 277 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS; 278 279 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 280 roce_address_table_size); 281 props->max_mtu = IB_MTU_4096; 282 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 283 props->pkey_tbl_len = 1; 284 props->state = IB_PORT_DOWN; 285 props->phys_state = 3; 286 287 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr); 288 props->qkey_viol_cntr = qkey_viol_cntr; 289 290 ndev = mlx5_ib_get_netdev(device, port_num); 291 if (!ndev) 292 return 0; 293 294 if (mlx5_lag_is_active(dev->mdev)) { 295 rcu_read_lock(); 296 upper = netdev_master_upper_dev_get_rcu(ndev); 297 if (upper) { 298 dev_put(ndev); 299 ndev = upper; 300 dev_hold(ndev); 301 } 302 rcu_read_unlock(); 303 } 304 305 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 306 props->state = IB_PORT_ACTIVE; 307 props->phys_state = 5; 308 } 309 310 ndev_ib_mtu = iboe_get_mtu(ndev->mtu); 311 312 dev_put(ndev); 313 314 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 315 return 0; 316 } 317 318 static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num, 319 unsigned int index, const union ib_gid *gid, 320 const struct ib_gid_attr *attr) 321 { 322 enum ib_gid_type gid_type = IB_GID_TYPE_IB; 323 u8 roce_version = 0; 324 u8 roce_l3_type = 0; 325 bool vlan = false; 326 u8 mac[ETH_ALEN]; 327 u16 vlan_id = 0; 328 329 if (gid) { 330 gid_type = attr->gid_type; 331 ether_addr_copy(mac, attr->ndev->dev_addr); 332 333 if (is_vlan_dev(attr->ndev)) { 334 vlan = true; 335 vlan_id = vlan_dev_vlan_id(attr->ndev); 336 } 337 } 338 339 switch (gid_type) { 340 case IB_GID_TYPE_IB: 341 roce_version = MLX5_ROCE_VERSION_1; 342 break; 343 case IB_GID_TYPE_ROCE_UDP_ENCAP: 344 roce_version = MLX5_ROCE_VERSION_2; 345 if (ipv6_addr_v4mapped((void *)gid)) 346 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4; 347 else 348 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6; 349 break; 350 351 default: 352 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type); 353 } 354 355 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version, 356 roce_l3_type, gid->raw, mac, vlan, 357 vlan_id); 358 } 359 360 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num, 361 unsigned int index, const union ib_gid *gid, 362 const struct ib_gid_attr *attr, 363 __always_unused void **context) 364 { 365 return set_roce_addr(to_mdev(device), port_num, index, gid, attr); 366 } 367 368 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num, 369 unsigned int index, __always_unused void **context) 370 { 371 return set_roce_addr(to_mdev(device), port_num, index, NULL, NULL); 372 } 373 374 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num, 375 int index) 376 { 377 struct ib_gid_attr attr; 378 union ib_gid gid; 379 380 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr)) 381 return 0; 382 383 if (!attr.ndev) 384 return 0; 385 386 dev_put(attr.ndev); 387 388 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 389 return 0; 390 391 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 392 } 393 394 int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num, 395 int index, enum ib_gid_type *gid_type) 396 { 397 struct ib_gid_attr attr; 398 union ib_gid gid; 399 int ret; 400 401 ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr); 402 if (ret) 403 return ret; 404 405 if (!attr.ndev) 406 return -ENODEV; 407 408 dev_put(attr.ndev); 409 410 *gid_type = attr.gid_type; 411 412 return 0; 413 } 414 415 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 416 { 417 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 418 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 419 return 0; 420 } 421 422 enum { 423 MLX5_VPORT_ACCESS_METHOD_MAD, 424 MLX5_VPORT_ACCESS_METHOD_HCA, 425 MLX5_VPORT_ACCESS_METHOD_NIC, 426 }; 427 428 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 429 { 430 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 431 return MLX5_VPORT_ACCESS_METHOD_MAD; 432 433 if (mlx5_ib_port_link_layer(ibdev, 1) == 434 IB_LINK_LAYER_ETHERNET) 435 return MLX5_VPORT_ACCESS_METHOD_NIC; 436 437 return MLX5_VPORT_ACCESS_METHOD_HCA; 438 } 439 440 static void get_atomic_caps(struct mlx5_ib_dev *dev, 441 struct ib_device_attr *props) 442 { 443 u8 tmp; 444 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 445 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 446 u8 atomic_req_8B_endianness_mode = 447 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode); 448 449 /* Check if HW supports 8 bytes standard atomic operations and capable 450 * of host endianness respond 451 */ 452 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 453 if (((atomic_operations & tmp) == tmp) && 454 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 455 (atomic_req_8B_endianness_mode)) { 456 props->atomic_cap = IB_ATOMIC_HCA; 457 } else { 458 props->atomic_cap = IB_ATOMIC_NONE; 459 } 460 } 461 462 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 463 __be64 *sys_image_guid) 464 { 465 struct mlx5_ib_dev *dev = to_mdev(ibdev); 466 struct mlx5_core_dev *mdev = dev->mdev; 467 u64 tmp; 468 int err; 469 470 switch (mlx5_get_vport_access_method(ibdev)) { 471 case MLX5_VPORT_ACCESS_METHOD_MAD: 472 return mlx5_query_mad_ifc_system_image_guid(ibdev, 473 sys_image_guid); 474 475 case MLX5_VPORT_ACCESS_METHOD_HCA: 476 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 477 break; 478 479 case MLX5_VPORT_ACCESS_METHOD_NIC: 480 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 481 break; 482 483 default: 484 return -EINVAL; 485 } 486 487 if (!err) 488 *sys_image_guid = cpu_to_be64(tmp); 489 490 return err; 491 492 } 493 494 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 495 u16 *max_pkeys) 496 { 497 struct mlx5_ib_dev *dev = to_mdev(ibdev); 498 struct mlx5_core_dev *mdev = dev->mdev; 499 500 switch (mlx5_get_vport_access_method(ibdev)) { 501 case MLX5_VPORT_ACCESS_METHOD_MAD: 502 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 503 504 case MLX5_VPORT_ACCESS_METHOD_HCA: 505 case MLX5_VPORT_ACCESS_METHOD_NIC: 506 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 507 pkey_table_size)); 508 return 0; 509 510 default: 511 return -EINVAL; 512 } 513 } 514 515 static int mlx5_query_vendor_id(struct ib_device *ibdev, 516 u32 *vendor_id) 517 { 518 struct mlx5_ib_dev *dev = to_mdev(ibdev); 519 520 switch (mlx5_get_vport_access_method(ibdev)) { 521 case MLX5_VPORT_ACCESS_METHOD_MAD: 522 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 523 524 case MLX5_VPORT_ACCESS_METHOD_HCA: 525 case MLX5_VPORT_ACCESS_METHOD_NIC: 526 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 527 528 default: 529 return -EINVAL; 530 } 531 } 532 533 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 534 __be64 *node_guid) 535 { 536 u64 tmp; 537 int err; 538 539 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 540 case MLX5_VPORT_ACCESS_METHOD_MAD: 541 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 542 543 case MLX5_VPORT_ACCESS_METHOD_HCA: 544 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 545 break; 546 547 case MLX5_VPORT_ACCESS_METHOD_NIC: 548 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 549 break; 550 551 default: 552 return -EINVAL; 553 } 554 555 if (!err) 556 *node_guid = cpu_to_be64(tmp); 557 558 return err; 559 } 560 561 struct mlx5_reg_node_desc { 562 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 563 }; 564 565 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 566 { 567 struct mlx5_reg_node_desc in; 568 569 if (mlx5_use_mad_ifc(dev)) 570 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 571 572 memset(&in, 0, sizeof(in)); 573 574 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 575 sizeof(struct mlx5_reg_node_desc), 576 MLX5_REG_NODE_DESC, 0, 0); 577 } 578 579 static int mlx5_ib_query_device(struct ib_device *ibdev, 580 struct ib_device_attr *props, 581 struct ib_udata *uhw) 582 { 583 struct mlx5_ib_dev *dev = to_mdev(ibdev); 584 struct mlx5_core_dev *mdev = dev->mdev; 585 int err = -ENOMEM; 586 int max_sq_desc; 587 int max_rq_sg; 588 int max_sq_sg; 589 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 590 struct mlx5_ib_query_device_resp resp = {}; 591 size_t resp_len; 592 u64 max_tso; 593 594 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 595 if (uhw->outlen && uhw->outlen < resp_len) 596 return -EINVAL; 597 else 598 resp.response_length = resp_len; 599 600 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) 601 return -EINVAL; 602 603 memset(props, 0, sizeof(*props)); 604 err = mlx5_query_system_image_guid(ibdev, 605 &props->sys_image_guid); 606 if (err) 607 return err; 608 609 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys); 610 if (err) 611 return err; 612 613 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 614 if (err) 615 return err; 616 617 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 618 (fw_rev_min(dev->mdev) << 16) | 619 fw_rev_sub(dev->mdev); 620 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 621 IB_DEVICE_PORT_ACTIVE_EVENT | 622 IB_DEVICE_SYS_IMAGE_GUID | 623 IB_DEVICE_RC_RNR_NAK_GEN; 624 625 if (MLX5_CAP_GEN(mdev, pkv)) 626 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 627 if (MLX5_CAP_GEN(mdev, qkv)) 628 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 629 if (MLX5_CAP_GEN(mdev, apm)) 630 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 631 if (MLX5_CAP_GEN(mdev, xrc)) 632 props->device_cap_flags |= IB_DEVICE_XRC; 633 if (MLX5_CAP_GEN(mdev, imaicl)) { 634 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 635 IB_DEVICE_MEM_WINDOW_TYPE_2B; 636 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 637 /* We support 'Gappy' memory registration too */ 638 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG; 639 } 640 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 641 if (MLX5_CAP_GEN(mdev, sho)) { 642 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER; 643 /* At this stage no support for signature handover */ 644 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 645 IB_PROT_T10DIF_TYPE_2 | 646 IB_PROT_T10DIF_TYPE_3; 647 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 648 IB_GUARD_T10DIF_CSUM; 649 } 650 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 651 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 652 653 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) { 654 if (MLX5_CAP_ETH(mdev, csum_cap)) { 655 /* Legacy bit to support old userspace libraries */ 656 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 657 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM; 658 } 659 660 if (MLX5_CAP_ETH(dev->mdev, vlan_cap)) 661 props->raw_packet_caps |= 662 IB_RAW_PACKET_CAP_CVLAN_STRIPPING; 663 664 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) { 665 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 666 if (max_tso) { 667 resp.tso_caps.max_tso = 1 << max_tso; 668 resp.tso_caps.supported_qpts |= 669 1 << IB_QPT_RAW_PACKET; 670 resp.response_length += sizeof(resp.tso_caps); 671 } 672 } 673 674 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) { 675 resp.rss_caps.rx_hash_function = 676 MLX5_RX_HASH_FUNC_TOEPLITZ; 677 resp.rss_caps.rx_hash_fields_mask = 678 MLX5_RX_HASH_SRC_IPV4 | 679 MLX5_RX_HASH_DST_IPV4 | 680 MLX5_RX_HASH_SRC_IPV6 | 681 MLX5_RX_HASH_DST_IPV6 | 682 MLX5_RX_HASH_SRC_PORT_TCP | 683 MLX5_RX_HASH_DST_PORT_TCP | 684 MLX5_RX_HASH_SRC_PORT_UDP | 685 MLX5_RX_HASH_DST_PORT_UDP; 686 resp.response_length += sizeof(resp.rss_caps); 687 } 688 } else { 689 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) 690 resp.response_length += sizeof(resp.tso_caps); 691 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) 692 resp.response_length += sizeof(resp.rss_caps); 693 } 694 695 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 696 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 697 props->device_cap_flags |= IB_DEVICE_UD_TSO; 698 } 699 700 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) && 701 MLX5_CAP_GEN(dev->mdev, general_notification_event)) 702 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP; 703 704 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 705 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap)) 706 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 707 708 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 709 MLX5_CAP_ETH(dev->mdev, scatter_fcs)) { 710 /* Legacy bit to support old userspace libraries */ 711 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 712 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; 713 } 714 715 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 716 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 717 718 props->vendor_part_id = mdev->pdev->device; 719 props->hw_ver = mdev->pdev->revision; 720 721 props->max_mr_size = ~0ull; 722 props->page_size_cap = ~(min_page_size - 1); 723 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 724 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 725 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 726 sizeof(struct mlx5_wqe_data_seg); 727 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512); 728 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) - 729 sizeof(struct mlx5_wqe_raddr_seg)) / 730 sizeof(struct mlx5_wqe_data_seg); 731 props->max_sge = min(max_rq_sg, max_sq_sg); 732 props->max_sge_rd = MLX5_MAX_SGE_RD; 733 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 734 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 735 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 736 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 737 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 738 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 739 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 740 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 741 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 742 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 743 props->max_srq_sge = max_rq_sg - 1; 744 props->max_fast_reg_page_list_len = 745 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 746 get_atomic_caps(dev, props); 747 props->masked_atomic_cap = IB_ATOMIC_NONE; 748 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 749 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 750 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 751 props->max_mcast_grp; 752 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */ 753 props->max_ah = INT_MAX; 754 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 755 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 756 757 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 758 if (MLX5_CAP_GEN(mdev, pg)) 759 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING; 760 props->odp_caps = dev->odp_caps; 761 #endif 762 763 if (MLX5_CAP_GEN(mdev, cd)) 764 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL; 765 766 if (!mlx5_core_is_pf(mdev)) 767 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION; 768 769 if (mlx5_ib_port_link_layer(ibdev, 1) == 770 IB_LINK_LAYER_ETHERNET) { 771 props->rss_caps.max_rwq_indirection_tables = 772 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 773 props->rss_caps.max_rwq_indirection_table_size = 774 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 775 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 776 props->max_wq_type_rq = 777 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 778 } 779 780 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) { 781 resp.cqe_comp_caps.max_num = 782 MLX5_CAP_GEN(dev->mdev, cqe_compression) ? 783 MLX5_CAP_GEN(dev->mdev, cqe_compression_max_num) : 0; 784 resp.cqe_comp_caps.supported_format = 785 MLX5_IB_CQE_RES_FORMAT_HASH | 786 MLX5_IB_CQE_RES_FORMAT_CSUM; 787 resp.response_length += sizeof(resp.cqe_comp_caps); 788 } 789 790 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen)) { 791 if (MLX5_CAP_QOS(mdev, packet_pacing) && 792 MLX5_CAP_GEN(mdev, qos)) { 793 resp.packet_pacing_caps.qp_rate_limit_max = 794 MLX5_CAP_QOS(mdev, packet_pacing_max_rate); 795 resp.packet_pacing_caps.qp_rate_limit_min = 796 MLX5_CAP_QOS(mdev, packet_pacing_min_rate); 797 resp.packet_pacing_caps.supported_qpts |= 798 1 << IB_QPT_RAW_PACKET; 799 } 800 resp.response_length += sizeof(resp.packet_pacing_caps); 801 } 802 803 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes, 804 uhw->outlen)) { 805 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe)) 806 resp.mlx5_ib_support_multi_pkt_send_wqes = 807 MLX5_IB_ALLOW_MPW; 808 resp.response_length += 809 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes); 810 } 811 812 if (field_avail(typeof(resp), reserved, uhw->outlen)) 813 resp.response_length += sizeof(resp.reserved); 814 815 if (field_avail(typeof(resp), sw_parsing_caps, 816 uhw->outlen)) { 817 resp.response_length += sizeof(resp.sw_parsing_caps); 818 if (MLX5_CAP_ETH(mdev, swp)) { 819 resp.sw_parsing_caps.sw_parsing_offloads |= 820 MLX5_IB_SW_PARSING; 821 822 if (MLX5_CAP_ETH(mdev, swp_csum)) 823 resp.sw_parsing_caps.sw_parsing_offloads |= 824 MLX5_IB_SW_PARSING_CSUM; 825 826 if (MLX5_CAP_ETH(mdev, swp_lso)) 827 resp.sw_parsing_caps.sw_parsing_offloads |= 828 MLX5_IB_SW_PARSING_LSO; 829 830 if (resp.sw_parsing_caps.sw_parsing_offloads) 831 resp.sw_parsing_caps.supported_qpts = 832 BIT(IB_QPT_RAW_PACKET); 833 } 834 } 835 836 if (uhw->outlen) { 837 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 838 839 if (err) 840 return err; 841 } 842 843 return 0; 844 } 845 846 enum mlx5_ib_width { 847 MLX5_IB_WIDTH_1X = 1 << 0, 848 MLX5_IB_WIDTH_2X = 1 << 1, 849 MLX5_IB_WIDTH_4X = 1 << 2, 850 MLX5_IB_WIDTH_8X = 1 << 3, 851 MLX5_IB_WIDTH_12X = 1 << 4 852 }; 853 854 static int translate_active_width(struct ib_device *ibdev, u8 active_width, 855 u8 *ib_width) 856 { 857 struct mlx5_ib_dev *dev = to_mdev(ibdev); 858 int err = 0; 859 860 if (active_width & MLX5_IB_WIDTH_1X) { 861 *ib_width = IB_WIDTH_1X; 862 } else if (active_width & MLX5_IB_WIDTH_2X) { 863 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n", 864 (int)active_width); 865 err = -EINVAL; 866 } else if (active_width & MLX5_IB_WIDTH_4X) { 867 *ib_width = IB_WIDTH_4X; 868 } else if (active_width & MLX5_IB_WIDTH_8X) { 869 *ib_width = IB_WIDTH_8X; 870 } else if (active_width & MLX5_IB_WIDTH_12X) { 871 *ib_width = IB_WIDTH_12X; 872 } else { 873 mlx5_ib_dbg(dev, "Invalid active_width %d\n", 874 (int)active_width); 875 err = -EINVAL; 876 } 877 878 return err; 879 } 880 881 static int mlx5_mtu_to_ib_mtu(int mtu) 882 { 883 switch (mtu) { 884 case 256: return 1; 885 case 512: return 2; 886 case 1024: return 3; 887 case 2048: return 4; 888 case 4096: return 5; 889 default: 890 pr_warn("invalid mtu\n"); 891 return -1; 892 } 893 } 894 895 enum ib_max_vl_num { 896 __IB_MAX_VL_0 = 1, 897 __IB_MAX_VL_0_1 = 2, 898 __IB_MAX_VL_0_3 = 3, 899 __IB_MAX_VL_0_7 = 4, 900 __IB_MAX_VL_0_14 = 5, 901 }; 902 903 enum mlx5_vl_hw_cap { 904 MLX5_VL_HW_0 = 1, 905 MLX5_VL_HW_0_1 = 2, 906 MLX5_VL_HW_0_2 = 3, 907 MLX5_VL_HW_0_3 = 4, 908 MLX5_VL_HW_0_4 = 5, 909 MLX5_VL_HW_0_5 = 6, 910 MLX5_VL_HW_0_6 = 7, 911 MLX5_VL_HW_0_7 = 8, 912 MLX5_VL_HW_0_14 = 15 913 }; 914 915 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 916 u8 *max_vl_num) 917 { 918 switch (vl_hw_cap) { 919 case MLX5_VL_HW_0: 920 *max_vl_num = __IB_MAX_VL_0; 921 break; 922 case MLX5_VL_HW_0_1: 923 *max_vl_num = __IB_MAX_VL_0_1; 924 break; 925 case MLX5_VL_HW_0_3: 926 *max_vl_num = __IB_MAX_VL_0_3; 927 break; 928 case MLX5_VL_HW_0_7: 929 *max_vl_num = __IB_MAX_VL_0_7; 930 break; 931 case MLX5_VL_HW_0_14: 932 *max_vl_num = __IB_MAX_VL_0_14; 933 break; 934 935 default: 936 return -EINVAL; 937 } 938 939 return 0; 940 } 941 942 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port, 943 struct ib_port_attr *props) 944 { 945 struct mlx5_ib_dev *dev = to_mdev(ibdev); 946 struct mlx5_core_dev *mdev = dev->mdev; 947 struct mlx5_hca_vport_context *rep; 948 u16 max_mtu; 949 u16 oper_mtu; 950 int err; 951 u8 ib_link_width_oper; 952 u8 vl_hw_cap; 953 954 rep = kzalloc(sizeof(*rep), GFP_KERNEL); 955 if (!rep) { 956 err = -ENOMEM; 957 goto out; 958 } 959 960 /* props being zeroed by the caller, avoid zeroing it here */ 961 962 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); 963 if (err) 964 goto out; 965 966 props->lid = rep->lid; 967 props->lmc = rep->lmc; 968 props->sm_lid = rep->sm_lid; 969 props->sm_sl = rep->sm_sl; 970 props->state = rep->vport_state; 971 props->phys_state = rep->port_physical_state; 972 props->port_cap_flags = rep->cap_mask1; 973 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 974 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 975 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 976 props->bad_pkey_cntr = rep->pkey_violation_counter; 977 props->qkey_viol_cntr = rep->qkey_violation_counter; 978 props->subnet_timeout = rep->subnet_timeout; 979 props->init_type_reply = rep->init_type_reply; 980 props->grh_required = rep->grh_required; 981 982 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port); 983 if (err) 984 goto out; 985 986 err = translate_active_width(ibdev, ib_link_width_oper, 987 &props->active_width); 988 if (err) 989 goto out; 990 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port); 991 if (err) 992 goto out; 993 994 mlx5_query_port_max_mtu(mdev, &max_mtu, port); 995 996 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); 997 998 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); 999 1000 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); 1001 1002 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); 1003 if (err) 1004 goto out; 1005 1006 err = translate_max_vl_num(ibdev, vl_hw_cap, 1007 &props->max_vl_num); 1008 out: 1009 kfree(rep); 1010 return err; 1011 } 1012 1013 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 1014 struct ib_port_attr *props) 1015 { 1016 unsigned int count; 1017 int ret; 1018 1019 switch (mlx5_get_vport_access_method(ibdev)) { 1020 case MLX5_VPORT_ACCESS_METHOD_MAD: 1021 ret = mlx5_query_mad_ifc_port(ibdev, port, props); 1022 break; 1023 1024 case MLX5_VPORT_ACCESS_METHOD_HCA: 1025 ret = mlx5_query_hca_port(ibdev, port, props); 1026 break; 1027 1028 case MLX5_VPORT_ACCESS_METHOD_NIC: 1029 ret = mlx5_query_port_roce(ibdev, port, props); 1030 break; 1031 1032 default: 1033 ret = -EINVAL; 1034 } 1035 1036 if (!ret && props) { 1037 count = mlx5_core_reserved_gids_count(to_mdev(ibdev)->mdev); 1038 props->gid_tbl_len -= count; 1039 } 1040 return ret; 1041 } 1042 1043 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 1044 union ib_gid *gid) 1045 { 1046 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1047 struct mlx5_core_dev *mdev = dev->mdev; 1048 1049 switch (mlx5_get_vport_access_method(ibdev)) { 1050 case MLX5_VPORT_ACCESS_METHOD_MAD: 1051 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 1052 1053 case MLX5_VPORT_ACCESS_METHOD_HCA: 1054 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); 1055 1056 default: 1057 return -EINVAL; 1058 } 1059 1060 } 1061 1062 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 1063 u16 *pkey) 1064 { 1065 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1066 struct mlx5_core_dev *mdev = dev->mdev; 1067 1068 switch (mlx5_get_vport_access_method(ibdev)) { 1069 case MLX5_VPORT_ACCESS_METHOD_MAD: 1070 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 1071 1072 case MLX5_VPORT_ACCESS_METHOD_HCA: 1073 case MLX5_VPORT_ACCESS_METHOD_NIC: 1074 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index, 1075 pkey); 1076 default: 1077 return -EINVAL; 1078 } 1079 } 1080 1081 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 1082 struct ib_device_modify *props) 1083 { 1084 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1085 struct mlx5_reg_node_desc in; 1086 struct mlx5_reg_node_desc out; 1087 int err; 1088 1089 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 1090 return -EOPNOTSUPP; 1091 1092 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 1093 return 0; 1094 1095 /* 1096 * If possible, pass node desc to FW, so it can generate 1097 * a 144 trap. If cmd fails, just ignore. 1098 */ 1099 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1100 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 1101 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 1102 if (err) 1103 return err; 1104 1105 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1106 1107 return err; 1108 } 1109 1110 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask, 1111 u32 value) 1112 { 1113 struct mlx5_hca_vport_context ctx = {}; 1114 int err; 1115 1116 err = mlx5_query_hca_vport_context(dev->mdev, 0, 1117 port_num, 0, &ctx); 1118 if (err) 1119 return err; 1120 1121 if (~ctx.cap_mask1_perm & mask) { 1122 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n", 1123 mask, ctx.cap_mask1_perm); 1124 return -EINVAL; 1125 } 1126 1127 ctx.cap_mask1 = value; 1128 ctx.cap_mask1_perm = mask; 1129 err = mlx5_core_modify_hca_vport_context(dev->mdev, 0, 1130 port_num, 0, &ctx); 1131 1132 return err; 1133 } 1134 1135 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, 1136 struct ib_port_modify *props) 1137 { 1138 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1139 struct ib_port_attr attr; 1140 u32 tmp; 1141 int err; 1142 u32 change_mask; 1143 u32 value; 1144 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) == 1145 IB_LINK_LAYER_INFINIBAND); 1146 1147 /* CM layer calls ib_modify_port() regardless of the link layer. For 1148 * Ethernet ports, qkey violation and Port capabilities are meaningless. 1149 */ 1150 if (!is_ib) 1151 return 0; 1152 1153 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) { 1154 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask; 1155 value = ~props->clr_port_cap_mask | props->set_port_cap_mask; 1156 return set_port_caps_atomic(dev, port, change_mask, value); 1157 } 1158 1159 mutex_lock(&dev->cap_mask_mutex); 1160 1161 err = ib_query_port(ibdev, port, &attr); 1162 if (err) 1163 goto out; 1164 1165 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 1166 ~props->clr_port_cap_mask; 1167 1168 err = mlx5_set_port_caps(dev->mdev, port, tmp); 1169 1170 out: 1171 mutex_unlock(&dev->cap_mask_mutex); 1172 return err; 1173 } 1174 1175 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps) 1176 { 1177 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n", 1178 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n"); 1179 } 1180 1181 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k, 1182 struct mlx5_ib_alloc_ucontext_req_v2 *req, 1183 u32 *num_sys_pages) 1184 { 1185 int uars_per_sys_page; 1186 int bfregs_per_sys_page; 1187 int ref_bfregs = req->total_num_bfregs; 1188 1189 if (req->total_num_bfregs == 0) 1190 return -EINVAL; 1191 1192 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE); 1193 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE); 1194 1195 if (req->total_num_bfregs > MLX5_MAX_BFREGS) 1196 return -ENOMEM; 1197 1198 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k); 1199 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR; 1200 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page); 1201 *num_sys_pages = req->total_num_bfregs / bfregs_per_sys_page; 1202 1203 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1) 1204 return -EINVAL; 1205 1206 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, using %d sys pages\n", 1207 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no", 1208 lib_uar_4k ? "yes" : "no", ref_bfregs, 1209 req->total_num_bfregs, *num_sys_pages); 1210 1211 return 0; 1212 } 1213 1214 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1215 { 1216 struct mlx5_bfreg_info *bfregi; 1217 int err; 1218 int i; 1219 1220 bfregi = &context->bfregi; 1221 for (i = 0; i < bfregi->num_sys_pages; i++) { 1222 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]); 1223 if (err) 1224 goto error; 1225 1226 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]); 1227 } 1228 return 0; 1229 1230 error: 1231 for (--i; i >= 0; i--) 1232 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i])) 1233 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1234 1235 return err; 1236 } 1237 1238 static int deallocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1239 { 1240 struct mlx5_bfreg_info *bfregi; 1241 int err; 1242 int i; 1243 1244 bfregi = &context->bfregi; 1245 for (i = 0; i < bfregi->num_sys_pages; i++) { 1246 err = mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]); 1247 if (err) { 1248 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1249 return err; 1250 } 1251 } 1252 return 0; 1253 } 1254 1255 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn) 1256 { 1257 int err; 1258 1259 err = mlx5_core_alloc_transport_domain(dev->mdev, tdn); 1260 if (err) 1261 return err; 1262 1263 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1264 !MLX5_CAP_GEN(dev->mdev, disable_local_lb)) 1265 return err; 1266 1267 mutex_lock(&dev->lb_mutex); 1268 dev->user_td++; 1269 1270 if (dev->user_td == 2) 1271 err = mlx5_nic_vport_update_local_lb(dev->mdev, true); 1272 1273 mutex_unlock(&dev->lb_mutex); 1274 return err; 1275 } 1276 1277 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn) 1278 { 1279 mlx5_core_dealloc_transport_domain(dev->mdev, tdn); 1280 1281 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1282 !MLX5_CAP_GEN(dev->mdev, disable_local_lb)) 1283 return; 1284 1285 mutex_lock(&dev->lb_mutex); 1286 dev->user_td--; 1287 1288 if (dev->user_td < 2) 1289 mlx5_nic_vport_update_local_lb(dev->mdev, false); 1290 1291 mutex_unlock(&dev->lb_mutex); 1292 } 1293 1294 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev, 1295 struct ib_udata *udata) 1296 { 1297 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1298 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 1299 struct mlx5_ib_alloc_ucontext_resp resp = {}; 1300 struct mlx5_ib_ucontext *context; 1301 struct mlx5_bfreg_info *bfregi; 1302 int ver; 1303 int err; 1304 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 1305 max_cqe_version); 1306 bool lib_uar_4k; 1307 1308 if (!dev->ib_active) 1309 return ERR_PTR(-EAGAIN); 1310 1311 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 1312 ver = 0; 1313 else if (udata->inlen >= min_req_v2) 1314 ver = 2; 1315 else 1316 return ERR_PTR(-EINVAL); 1317 1318 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req))); 1319 if (err) 1320 return ERR_PTR(err); 1321 1322 if (req.flags) 1323 return ERR_PTR(-EINVAL); 1324 1325 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 1326 return ERR_PTR(-EOPNOTSUPP); 1327 1328 req.total_num_bfregs = ALIGN(req.total_num_bfregs, 1329 MLX5_NON_FP_BFREGS_PER_UAR); 1330 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1) 1331 return ERR_PTR(-EINVAL); 1332 1333 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 1334 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf)) 1335 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size); 1336 resp.cache_line_size = cache_line_size(); 1337 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 1338 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 1339 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1340 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1341 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 1342 resp.cqe_version = min_t(__u8, 1343 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 1344 req.max_cqe_version); 1345 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1346 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT; 1347 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1348 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1; 1349 resp.response_length = min(offsetof(typeof(resp), response_length) + 1350 sizeof(resp.response_length), udata->outlen); 1351 1352 context = kzalloc(sizeof(*context), GFP_KERNEL); 1353 if (!context) 1354 return ERR_PTR(-ENOMEM); 1355 1356 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR; 1357 bfregi = &context->bfregi; 1358 1359 /* updates req->total_num_bfregs */ 1360 err = calc_total_bfregs(dev, lib_uar_4k, &req, &bfregi->num_sys_pages); 1361 if (err) 1362 goto out_ctx; 1363 1364 mutex_init(&bfregi->lock); 1365 bfregi->lib_uar_4k = lib_uar_4k; 1366 bfregi->count = kcalloc(req.total_num_bfregs, sizeof(*bfregi->count), 1367 GFP_KERNEL); 1368 if (!bfregi->count) { 1369 err = -ENOMEM; 1370 goto out_ctx; 1371 } 1372 1373 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages, 1374 sizeof(*bfregi->sys_pages), 1375 GFP_KERNEL); 1376 if (!bfregi->sys_pages) { 1377 err = -ENOMEM; 1378 goto out_count; 1379 } 1380 1381 err = allocate_uars(dev, context); 1382 if (err) 1383 goto out_sys_pages; 1384 1385 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1386 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range; 1387 #endif 1388 1389 context->upd_xlt_page = __get_free_page(GFP_KERNEL); 1390 if (!context->upd_xlt_page) { 1391 err = -ENOMEM; 1392 goto out_uars; 1393 } 1394 mutex_init(&context->upd_xlt_page_mutex); 1395 1396 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) { 1397 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn); 1398 if (err) 1399 goto out_page; 1400 } 1401 1402 INIT_LIST_HEAD(&context->vma_private_list); 1403 INIT_LIST_HEAD(&context->db_page_list); 1404 mutex_init(&context->db_page_mutex); 1405 1406 resp.tot_bfregs = req.total_num_bfregs; 1407 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports); 1408 1409 if (field_avail(typeof(resp), cqe_version, udata->outlen)) 1410 resp.response_length += sizeof(resp.cqe_version); 1411 1412 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) { 1413 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 1414 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 1415 resp.response_length += sizeof(resp.cmds_supp_uhw); 1416 } 1417 1418 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) { 1419 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) { 1420 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline); 1421 resp.eth_min_inline++; 1422 } 1423 resp.response_length += sizeof(resp.eth_min_inline); 1424 } 1425 1426 /* 1427 * We don't want to expose information from the PCI bar that is located 1428 * after 4096 bytes, so if the arch only supports larger pages, let's 1429 * pretend we don't support reading the HCA's core clock. This is also 1430 * forced by mmap function. 1431 */ 1432 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) { 1433 if (PAGE_SIZE <= 4096) { 1434 resp.comp_mask |= 1435 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 1436 resp.hca_core_clock_offset = 1437 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE; 1438 } 1439 resp.response_length += sizeof(resp.hca_core_clock_offset) + 1440 sizeof(resp.reserved2); 1441 } 1442 1443 if (field_avail(typeof(resp), log_uar_size, udata->outlen)) 1444 resp.response_length += sizeof(resp.log_uar_size); 1445 1446 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen)) 1447 resp.response_length += sizeof(resp.num_uars_per_page); 1448 1449 err = ib_copy_to_udata(udata, &resp, resp.response_length); 1450 if (err) 1451 goto out_td; 1452 1453 bfregi->ver = ver; 1454 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs; 1455 context->cqe_version = resp.cqe_version; 1456 context->lib_caps = req.lib_caps; 1457 print_lib_caps(dev, context->lib_caps); 1458 1459 return &context->ibucontext; 1460 1461 out_td: 1462 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1463 mlx5_ib_dealloc_transport_domain(dev, context->tdn); 1464 1465 out_page: 1466 free_page(context->upd_xlt_page); 1467 1468 out_uars: 1469 deallocate_uars(dev, context); 1470 1471 out_sys_pages: 1472 kfree(bfregi->sys_pages); 1473 1474 out_count: 1475 kfree(bfregi->count); 1476 1477 out_ctx: 1478 kfree(context); 1479 1480 return ERR_PTR(err); 1481 } 1482 1483 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1484 { 1485 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1486 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1487 struct mlx5_bfreg_info *bfregi; 1488 1489 bfregi = &context->bfregi; 1490 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1491 mlx5_ib_dealloc_transport_domain(dev, context->tdn); 1492 1493 free_page(context->upd_xlt_page); 1494 deallocate_uars(dev, context); 1495 kfree(bfregi->sys_pages); 1496 kfree(bfregi->count); 1497 kfree(context); 1498 1499 return 0; 1500 } 1501 1502 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, 1503 struct mlx5_bfreg_info *bfregi, 1504 int idx) 1505 { 1506 int fw_uars_per_page; 1507 1508 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1; 1509 1510 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + 1511 bfregi->sys_pages[idx] / fw_uars_per_page; 1512 } 1513 1514 static int get_command(unsigned long offset) 1515 { 1516 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 1517 } 1518 1519 static int get_arg(unsigned long offset) 1520 { 1521 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 1522 } 1523 1524 static int get_index(unsigned long offset) 1525 { 1526 return get_arg(offset); 1527 } 1528 1529 static void mlx5_ib_vma_open(struct vm_area_struct *area) 1530 { 1531 /* vma_open is called when a new VMA is created on top of our VMA. This 1532 * is done through either mremap flow or split_vma (usually due to 1533 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA, 1534 * as this VMA is strongly hardware related. Therefore we set the 1535 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from 1536 * calling us again and trying to do incorrect actions. We assume that 1537 * the original VMA size is exactly a single page, and therefore all 1538 * "splitting" operation will not happen to it. 1539 */ 1540 area->vm_ops = NULL; 1541 } 1542 1543 static void mlx5_ib_vma_close(struct vm_area_struct *area) 1544 { 1545 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data; 1546 1547 /* It's guaranteed that all VMAs opened on a FD are closed before the 1548 * file itself is closed, therefore no sync is needed with the regular 1549 * closing flow. (e.g. mlx5 ib_dealloc_ucontext) 1550 * However need a sync with accessing the vma as part of 1551 * mlx5_ib_disassociate_ucontext. 1552 * The close operation is usually called under mm->mmap_sem except when 1553 * process is exiting. 1554 * The exiting case is handled explicitly as part of 1555 * mlx5_ib_disassociate_ucontext. 1556 */ 1557 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data; 1558 1559 /* setting the vma context pointer to null in the mlx5_ib driver's 1560 * private data, to protect a race condition in 1561 * mlx5_ib_disassociate_ucontext(). 1562 */ 1563 mlx5_ib_vma_priv_data->vma = NULL; 1564 list_del(&mlx5_ib_vma_priv_data->list); 1565 kfree(mlx5_ib_vma_priv_data); 1566 } 1567 1568 static const struct vm_operations_struct mlx5_ib_vm_ops = { 1569 .open = mlx5_ib_vma_open, 1570 .close = mlx5_ib_vma_close 1571 }; 1572 1573 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma, 1574 struct mlx5_ib_ucontext *ctx) 1575 { 1576 struct mlx5_ib_vma_private_data *vma_prv; 1577 struct list_head *vma_head = &ctx->vma_private_list; 1578 1579 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL); 1580 if (!vma_prv) 1581 return -ENOMEM; 1582 1583 vma_prv->vma = vma; 1584 vma->vm_private_data = vma_prv; 1585 vma->vm_ops = &mlx5_ib_vm_ops; 1586 1587 list_add(&vma_prv->list, vma_head); 1588 1589 return 0; 1590 } 1591 1592 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 1593 { 1594 int ret; 1595 struct vm_area_struct *vma; 1596 struct mlx5_ib_vma_private_data *vma_private, *n; 1597 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1598 struct task_struct *owning_process = NULL; 1599 struct mm_struct *owning_mm = NULL; 1600 1601 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID); 1602 if (!owning_process) 1603 return; 1604 1605 owning_mm = get_task_mm(owning_process); 1606 if (!owning_mm) { 1607 pr_info("no mm, disassociate ucontext is pending task termination\n"); 1608 while (1) { 1609 put_task_struct(owning_process); 1610 usleep_range(1000, 2000); 1611 owning_process = get_pid_task(ibcontext->tgid, 1612 PIDTYPE_PID); 1613 if (!owning_process || 1614 owning_process->state == TASK_DEAD) { 1615 pr_info("disassociate ucontext done, task was terminated\n"); 1616 /* in case task was dead need to release the 1617 * task struct. 1618 */ 1619 if (owning_process) 1620 put_task_struct(owning_process); 1621 return; 1622 } 1623 } 1624 } 1625 1626 /* need to protect from a race on closing the vma as part of 1627 * mlx5_ib_vma_close. 1628 */ 1629 down_write(&owning_mm->mmap_sem); 1630 list_for_each_entry_safe(vma_private, n, &context->vma_private_list, 1631 list) { 1632 vma = vma_private->vma; 1633 ret = zap_vma_ptes(vma, vma->vm_start, 1634 PAGE_SIZE); 1635 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__); 1636 /* context going to be destroyed, should 1637 * not access ops any more. 1638 */ 1639 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE); 1640 vma->vm_ops = NULL; 1641 list_del(&vma_private->list); 1642 kfree(vma_private); 1643 } 1644 up_write(&owning_mm->mmap_sem); 1645 mmput(owning_mm); 1646 put_task_struct(owning_process); 1647 } 1648 1649 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 1650 { 1651 switch (cmd) { 1652 case MLX5_IB_MMAP_WC_PAGE: 1653 return "WC"; 1654 case MLX5_IB_MMAP_REGULAR_PAGE: 1655 return "best effort WC"; 1656 case MLX5_IB_MMAP_NC_PAGE: 1657 return "NC"; 1658 default: 1659 return NULL; 1660 } 1661 } 1662 1663 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 1664 struct vm_area_struct *vma, 1665 struct mlx5_ib_ucontext *context) 1666 { 1667 struct mlx5_bfreg_info *bfregi = &context->bfregi; 1668 int err; 1669 unsigned long idx; 1670 phys_addr_t pfn, pa; 1671 pgprot_t prot; 1672 int uars_per_page; 1673 1674 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1675 return -EINVAL; 1676 1677 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k); 1678 idx = get_index(vma->vm_pgoff); 1679 if (idx % uars_per_page || 1680 idx * uars_per_page >= bfregi->num_sys_pages) { 1681 mlx5_ib_warn(dev, "invalid uar index %lu\n", idx); 1682 return -EINVAL; 1683 } 1684 1685 switch (cmd) { 1686 case MLX5_IB_MMAP_WC_PAGE: 1687 /* Some architectures don't support WC memory */ 1688 #if defined(CONFIG_X86) 1689 if (!pat_enabled()) 1690 return -EPERM; 1691 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU))) 1692 return -EPERM; 1693 #endif 1694 /* fall through */ 1695 case MLX5_IB_MMAP_REGULAR_PAGE: 1696 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 1697 prot = pgprot_writecombine(vma->vm_page_prot); 1698 break; 1699 case MLX5_IB_MMAP_NC_PAGE: 1700 prot = pgprot_noncached(vma->vm_page_prot); 1701 break; 1702 default: 1703 return -EINVAL; 1704 } 1705 1706 pfn = uar_index2pfn(dev, bfregi, idx); 1707 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 1708 1709 vma->vm_page_prot = prot; 1710 err = io_remap_pfn_range(vma, vma->vm_start, pfn, 1711 PAGE_SIZE, vma->vm_page_prot); 1712 if (err) { 1713 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n", 1714 err, vma->vm_start, &pfn, mmap_cmd2str(cmd)); 1715 return -EAGAIN; 1716 } 1717 1718 pa = pfn << PAGE_SHIFT; 1719 mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd), 1720 vma->vm_start, &pa); 1721 1722 return mlx5_ib_set_vma_data(vma, context); 1723 } 1724 1725 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 1726 { 1727 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1728 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1729 unsigned long command; 1730 phys_addr_t pfn; 1731 1732 command = get_command(vma->vm_pgoff); 1733 switch (command) { 1734 case MLX5_IB_MMAP_WC_PAGE: 1735 case MLX5_IB_MMAP_NC_PAGE: 1736 case MLX5_IB_MMAP_REGULAR_PAGE: 1737 return uar_mmap(dev, command, vma, context); 1738 1739 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 1740 return -ENOSYS; 1741 1742 case MLX5_IB_MMAP_CORE_CLOCK: 1743 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1744 return -EINVAL; 1745 1746 if (vma->vm_flags & VM_WRITE) 1747 return -EPERM; 1748 1749 /* Don't expose to user-space information it shouldn't have */ 1750 if (PAGE_SIZE > 4096) 1751 return -EOPNOTSUPP; 1752 1753 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 1754 pfn = (dev->mdev->iseg_base + 1755 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 1756 PAGE_SHIFT; 1757 if (io_remap_pfn_range(vma, vma->vm_start, pfn, 1758 PAGE_SIZE, vma->vm_page_prot)) 1759 return -EAGAIN; 1760 1761 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n", 1762 vma->vm_start, 1763 (unsigned long long)pfn << PAGE_SHIFT); 1764 break; 1765 1766 default: 1767 return -EINVAL; 1768 } 1769 1770 return 0; 1771 } 1772 1773 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev, 1774 struct ib_ucontext *context, 1775 struct ib_udata *udata) 1776 { 1777 struct mlx5_ib_alloc_pd_resp resp; 1778 struct mlx5_ib_pd *pd; 1779 int err; 1780 1781 pd = kmalloc(sizeof(*pd), GFP_KERNEL); 1782 if (!pd) 1783 return ERR_PTR(-ENOMEM); 1784 1785 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn); 1786 if (err) { 1787 kfree(pd); 1788 return ERR_PTR(err); 1789 } 1790 1791 if (context) { 1792 resp.pdn = pd->pdn; 1793 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 1794 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn); 1795 kfree(pd); 1796 return ERR_PTR(-EFAULT); 1797 } 1798 } 1799 1800 return &pd->ibpd; 1801 } 1802 1803 static int mlx5_ib_dealloc_pd(struct ib_pd *pd) 1804 { 1805 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 1806 struct mlx5_ib_pd *mpd = to_mpd(pd); 1807 1808 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn); 1809 kfree(mpd); 1810 1811 return 0; 1812 } 1813 1814 enum { 1815 MATCH_CRITERIA_ENABLE_OUTER_BIT, 1816 MATCH_CRITERIA_ENABLE_MISC_BIT, 1817 MATCH_CRITERIA_ENABLE_INNER_BIT 1818 }; 1819 1820 #define HEADER_IS_ZERO(match_criteria, headers) \ 1821 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \ 1822 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \ 1823 1824 static u8 get_match_criteria_enable(u32 *match_criteria) 1825 { 1826 u8 match_criteria_enable; 1827 1828 match_criteria_enable = 1829 (!HEADER_IS_ZERO(match_criteria, outer_headers)) << 1830 MATCH_CRITERIA_ENABLE_OUTER_BIT; 1831 match_criteria_enable |= 1832 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) << 1833 MATCH_CRITERIA_ENABLE_MISC_BIT; 1834 match_criteria_enable |= 1835 (!HEADER_IS_ZERO(match_criteria, inner_headers)) << 1836 MATCH_CRITERIA_ENABLE_INNER_BIT; 1837 1838 return match_criteria_enable; 1839 } 1840 1841 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val) 1842 { 1843 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask); 1844 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val); 1845 } 1846 1847 static void set_flow_label(void *misc_c, void *misc_v, u8 mask, u8 val, 1848 bool inner) 1849 { 1850 if (inner) { 1851 MLX5_SET(fte_match_set_misc, 1852 misc_c, inner_ipv6_flow_label, mask); 1853 MLX5_SET(fte_match_set_misc, 1854 misc_v, inner_ipv6_flow_label, val); 1855 } else { 1856 MLX5_SET(fte_match_set_misc, 1857 misc_c, outer_ipv6_flow_label, mask); 1858 MLX5_SET(fte_match_set_misc, 1859 misc_v, outer_ipv6_flow_label, val); 1860 } 1861 } 1862 1863 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val) 1864 { 1865 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask); 1866 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val); 1867 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2); 1868 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2); 1869 } 1870 1871 #define LAST_ETH_FIELD vlan_tag 1872 #define LAST_IB_FIELD sl 1873 #define LAST_IPV4_FIELD tos 1874 #define LAST_IPV6_FIELD traffic_class 1875 #define LAST_TCP_UDP_FIELD src_port 1876 #define LAST_TUNNEL_FIELD tunnel_id 1877 #define LAST_FLOW_TAG_FIELD tag_id 1878 #define LAST_DROP_FIELD size 1879 1880 /* Field is the last supported field */ 1881 #define FIELDS_NOT_SUPPORTED(filter, field)\ 1882 memchr_inv((void *)&filter.field +\ 1883 sizeof(filter.field), 0,\ 1884 sizeof(filter) -\ 1885 offsetof(typeof(filter), field) -\ 1886 sizeof(filter.field)) 1887 1888 #define IPV4_VERSION 4 1889 #define IPV6_VERSION 6 1890 static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c, 1891 u32 *match_v, const union ib_flow_spec *ib_spec, 1892 u32 *tag_id, bool *is_drop) 1893 { 1894 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c, 1895 misc_parameters); 1896 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v, 1897 misc_parameters); 1898 void *headers_c; 1899 void *headers_v; 1900 int match_ipv; 1901 1902 if (ib_spec->type & IB_FLOW_SPEC_INNER) { 1903 headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 1904 inner_headers); 1905 headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 1906 inner_headers); 1907 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 1908 ft_field_support.inner_ip_version); 1909 } else { 1910 headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 1911 outer_headers); 1912 headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 1913 outer_headers); 1914 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 1915 ft_field_support.outer_ip_version); 1916 } 1917 1918 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) { 1919 case IB_FLOW_SPEC_ETH: 1920 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD)) 1921 return -EOPNOTSUPP; 1922 1923 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 1924 dmac_47_16), 1925 ib_spec->eth.mask.dst_mac); 1926 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1927 dmac_47_16), 1928 ib_spec->eth.val.dst_mac); 1929 1930 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 1931 smac_47_16), 1932 ib_spec->eth.mask.src_mac); 1933 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1934 smac_47_16), 1935 ib_spec->eth.val.src_mac); 1936 1937 if (ib_spec->eth.mask.vlan_tag) { 1938 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1939 cvlan_tag, 1); 1940 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1941 cvlan_tag, 1); 1942 1943 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1944 first_vid, ntohs(ib_spec->eth.mask.vlan_tag)); 1945 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1946 first_vid, ntohs(ib_spec->eth.val.vlan_tag)); 1947 1948 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1949 first_cfi, 1950 ntohs(ib_spec->eth.mask.vlan_tag) >> 12); 1951 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1952 first_cfi, 1953 ntohs(ib_spec->eth.val.vlan_tag) >> 12); 1954 1955 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1956 first_prio, 1957 ntohs(ib_spec->eth.mask.vlan_tag) >> 13); 1958 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1959 first_prio, 1960 ntohs(ib_spec->eth.val.vlan_tag) >> 13); 1961 } 1962 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1963 ethertype, ntohs(ib_spec->eth.mask.ether_type)); 1964 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1965 ethertype, ntohs(ib_spec->eth.val.ether_type)); 1966 break; 1967 case IB_FLOW_SPEC_IPV4: 1968 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD)) 1969 return -EOPNOTSUPP; 1970 1971 if (match_ipv) { 1972 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1973 ip_version, 0xf); 1974 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1975 ip_version, IPV4_VERSION); 1976 } else { 1977 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 1978 ethertype, 0xffff); 1979 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 1980 ethertype, ETH_P_IP); 1981 } 1982 1983 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 1984 src_ipv4_src_ipv6.ipv4_layout.ipv4), 1985 &ib_spec->ipv4.mask.src_ip, 1986 sizeof(ib_spec->ipv4.mask.src_ip)); 1987 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1988 src_ipv4_src_ipv6.ipv4_layout.ipv4), 1989 &ib_spec->ipv4.val.src_ip, 1990 sizeof(ib_spec->ipv4.val.src_ip)); 1991 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 1992 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 1993 &ib_spec->ipv4.mask.dst_ip, 1994 sizeof(ib_spec->ipv4.mask.dst_ip)); 1995 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 1996 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 1997 &ib_spec->ipv4.val.dst_ip, 1998 sizeof(ib_spec->ipv4.val.dst_ip)); 1999 2000 set_tos(headers_c, headers_v, 2001 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos); 2002 2003 set_proto(headers_c, headers_v, 2004 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto); 2005 break; 2006 case IB_FLOW_SPEC_IPV6: 2007 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD)) 2008 return -EOPNOTSUPP; 2009 2010 if (match_ipv) { 2011 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2012 ip_version, 0xf); 2013 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2014 ip_version, IPV6_VERSION); 2015 } else { 2016 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2017 ethertype, 0xffff); 2018 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2019 ethertype, ETH_P_IPV6); 2020 } 2021 2022 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2023 src_ipv4_src_ipv6.ipv6_layout.ipv6), 2024 &ib_spec->ipv6.mask.src_ip, 2025 sizeof(ib_spec->ipv6.mask.src_ip)); 2026 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2027 src_ipv4_src_ipv6.ipv6_layout.ipv6), 2028 &ib_spec->ipv6.val.src_ip, 2029 sizeof(ib_spec->ipv6.val.src_ip)); 2030 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2031 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 2032 &ib_spec->ipv6.mask.dst_ip, 2033 sizeof(ib_spec->ipv6.mask.dst_ip)); 2034 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2035 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 2036 &ib_spec->ipv6.val.dst_ip, 2037 sizeof(ib_spec->ipv6.val.dst_ip)); 2038 2039 set_tos(headers_c, headers_v, 2040 ib_spec->ipv6.mask.traffic_class, 2041 ib_spec->ipv6.val.traffic_class); 2042 2043 set_proto(headers_c, headers_v, 2044 ib_spec->ipv6.mask.next_hdr, 2045 ib_spec->ipv6.val.next_hdr); 2046 2047 set_flow_label(misc_params_c, misc_params_v, 2048 ntohl(ib_spec->ipv6.mask.flow_label), 2049 ntohl(ib_spec->ipv6.val.flow_label), 2050 ib_spec->type & IB_FLOW_SPEC_INNER); 2051 2052 break; 2053 case IB_FLOW_SPEC_TCP: 2054 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 2055 LAST_TCP_UDP_FIELD)) 2056 return -EOPNOTSUPP; 2057 2058 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol, 2059 0xff); 2060 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, 2061 IPPROTO_TCP); 2062 2063 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport, 2064 ntohs(ib_spec->tcp_udp.mask.src_port)); 2065 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport, 2066 ntohs(ib_spec->tcp_udp.val.src_port)); 2067 2068 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport, 2069 ntohs(ib_spec->tcp_udp.mask.dst_port)); 2070 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport, 2071 ntohs(ib_spec->tcp_udp.val.dst_port)); 2072 break; 2073 case IB_FLOW_SPEC_UDP: 2074 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 2075 LAST_TCP_UDP_FIELD)) 2076 return -EOPNOTSUPP; 2077 2078 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol, 2079 0xff); 2080 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, 2081 IPPROTO_UDP); 2082 2083 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport, 2084 ntohs(ib_spec->tcp_udp.mask.src_port)); 2085 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport, 2086 ntohs(ib_spec->tcp_udp.val.src_port)); 2087 2088 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport, 2089 ntohs(ib_spec->tcp_udp.mask.dst_port)); 2090 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, 2091 ntohs(ib_spec->tcp_udp.val.dst_port)); 2092 break; 2093 case IB_FLOW_SPEC_VXLAN_TUNNEL: 2094 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask, 2095 LAST_TUNNEL_FIELD)) 2096 return -EOPNOTSUPP; 2097 2098 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni, 2099 ntohl(ib_spec->tunnel.mask.tunnel_id)); 2100 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni, 2101 ntohl(ib_spec->tunnel.val.tunnel_id)); 2102 break; 2103 case IB_FLOW_SPEC_ACTION_TAG: 2104 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag, 2105 LAST_FLOW_TAG_FIELD)) 2106 return -EOPNOTSUPP; 2107 if (ib_spec->flow_tag.tag_id >= BIT(24)) 2108 return -EINVAL; 2109 2110 *tag_id = ib_spec->flow_tag.tag_id; 2111 break; 2112 case IB_FLOW_SPEC_ACTION_DROP: 2113 if (FIELDS_NOT_SUPPORTED(ib_spec->drop, 2114 LAST_DROP_FIELD)) 2115 return -EOPNOTSUPP; 2116 *is_drop = true; 2117 break; 2118 default: 2119 return -EINVAL; 2120 } 2121 2122 return 0; 2123 } 2124 2125 /* If a flow could catch both multicast and unicast packets, 2126 * it won't fall into the multicast flow steering table and this rule 2127 * could steal other multicast packets. 2128 */ 2129 static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr) 2130 { 2131 union ib_flow_spec *flow_spec; 2132 2133 if (ib_attr->type != IB_FLOW_ATTR_NORMAL || 2134 ib_attr->num_of_specs < 1) 2135 return false; 2136 2137 flow_spec = (union ib_flow_spec *)(ib_attr + 1); 2138 if (flow_spec->type == IB_FLOW_SPEC_IPV4) { 2139 struct ib_flow_spec_ipv4 *ipv4_spec; 2140 2141 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec; 2142 if (ipv4_is_multicast(ipv4_spec->val.dst_ip)) 2143 return true; 2144 2145 return false; 2146 } 2147 2148 if (flow_spec->type == IB_FLOW_SPEC_ETH) { 2149 struct ib_flow_spec_eth *eth_spec; 2150 2151 eth_spec = (struct ib_flow_spec_eth *)flow_spec; 2152 return is_multicast_ether_addr(eth_spec->mask.dst_mac) && 2153 is_multicast_ether_addr(eth_spec->val.dst_mac); 2154 } 2155 2156 return false; 2157 } 2158 2159 static bool is_valid_ethertype(struct mlx5_core_dev *mdev, 2160 const struct ib_flow_attr *flow_attr, 2161 bool check_inner) 2162 { 2163 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1); 2164 int match_ipv = check_inner ? 2165 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2166 ft_field_support.inner_ip_version) : 2167 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2168 ft_field_support.outer_ip_version); 2169 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0; 2170 bool ipv4_spec_valid, ipv6_spec_valid; 2171 unsigned int ip_spec_type = 0; 2172 bool has_ethertype = false; 2173 unsigned int spec_index; 2174 bool mask_valid = true; 2175 u16 eth_type = 0; 2176 bool type_valid; 2177 2178 /* Validate that ethertype is correct */ 2179 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 2180 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) && 2181 ib_spec->eth.mask.ether_type) { 2182 mask_valid = (ib_spec->eth.mask.ether_type == 2183 htons(0xffff)); 2184 has_ethertype = true; 2185 eth_type = ntohs(ib_spec->eth.val.ether_type); 2186 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) || 2187 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) { 2188 ip_spec_type = ib_spec->type; 2189 } 2190 ib_spec = (void *)ib_spec + ib_spec->size; 2191 } 2192 2193 type_valid = (!has_ethertype) || (!ip_spec_type); 2194 if (!type_valid && mask_valid) { 2195 ipv4_spec_valid = (eth_type == ETH_P_IP) && 2196 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit)); 2197 ipv6_spec_valid = (eth_type == ETH_P_IPV6) && 2198 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit)); 2199 2200 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) || 2201 (((eth_type == ETH_P_MPLS_UC) || 2202 (eth_type == ETH_P_MPLS_MC)) && match_ipv); 2203 } 2204 2205 return type_valid; 2206 } 2207 2208 static bool is_valid_attr(struct mlx5_core_dev *mdev, 2209 const struct ib_flow_attr *flow_attr) 2210 { 2211 return is_valid_ethertype(mdev, flow_attr, false) && 2212 is_valid_ethertype(mdev, flow_attr, true); 2213 } 2214 2215 static void put_flow_table(struct mlx5_ib_dev *dev, 2216 struct mlx5_ib_flow_prio *prio, bool ft_added) 2217 { 2218 prio->refcount -= !!ft_added; 2219 if (!prio->refcount) { 2220 mlx5_destroy_flow_table(prio->flow_table); 2221 prio->flow_table = NULL; 2222 } 2223 } 2224 2225 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id) 2226 { 2227 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device); 2228 struct mlx5_ib_flow_handler *handler = container_of(flow_id, 2229 struct mlx5_ib_flow_handler, 2230 ibflow); 2231 struct mlx5_ib_flow_handler *iter, *tmp; 2232 2233 mutex_lock(&dev->flow_db.lock); 2234 2235 list_for_each_entry_safe(iter, tmp, &handler->list, list) { 2236 mlx5_del_flow_rules(iter->rule); 2237 put_flow_table(dev, iter->prio, true); 2238 list_del(&iter->list); 2239 kfree(iter); 2240 } 2241 2242 mlx5_del_flow_rules(handler->rule); 2243 put_flow_table(dev, handler->prio, true); 2244 mutex_unlock(&dev->flow_db.lock); 2245 2246 kfree(handler); 2247 2248 return 0; 2249 } 2250 2251 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap) 2252 { 2253 priority *= 2; 2254 if (!dont_trap) 2255 priority++; 2256 return priority; 2257 } 2258 2259 enum flow_table_type { 2260 MLX5_IB_FT_RX, 2261 MLX5_IB_FT_TX 2262 }; 2263 2264 #define MLX5_FS_MAX_TYPES 6 2265 #define MLX5_FS_MAX_ENTRIES BIT(16) 2266 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev, 2267 struct ib_flow_attr *flow_attr, 2268 enum flow_table_type ft_type) 2269 { 2270 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP; 2271 struct mlx5_flow_namespace *ns = NULL; 2272 struct mlx5_ib_flow_prio *prio; 2273 struct mlx5_flow_table *ft; 2274 int max_table_size; 2275 int num_entries; 2276 int num_groups; 2277 int priority; 2278 int err = 0; 2279 2280 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 2281 log_max_ft_size)); 2282 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 2283 if (flow_is_multicast_only(flow_attr) && 2284 !dont_trap) 2285 priority = MLX5_IB_FLOW_MCAST_PRIO; 2286 else 2287 priority = ib_prio_to_core_prio(flow_attr->priority, 2288 dont_trap); 2289 ns = mlx5_get_flow_namespace(dev->mdev, 2290 MLX5_FLOW_NAMESPACE_BYPASS); 2291 num_entries = MLX5_FS_MAX_ENTRIES; 2292 num_groups = MLX5_FS_MAX_TYPES; 2293 prio = &dev->flow_db.prios[priority]; 2294 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 2295 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 2296 ns = mlx5_get_flow_namespace(dev->mdev, 2297 MLX5_FLOW_NAMESPACE_LEFTOVERS); 2298 build_leftovers_ft_param(&priority, 2299 &num_entries, 2300 &num_groups); 2301 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO]; 2302 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 2303 if (!MLX5_CAP_FLOWTABLE(dev->mdev, 2304 allow_sniffer_and_nic_rx_shared_tir)) 2305 return ERR_PTR(-ENOTSUPP); 2306 2307 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ? 2308 MLX5_FLOW_NAMESPACE_SNIFFER_RX : 2309 MLX5_FLOW_NAMESPACE_SNIFFER_TX); 2310 2311 prio = &dev->flow_db.sniffer[ft_type]; 2312 priority = 0; 2313 num_entries = 1; 2314 num_groups = 1; 2315 } 2316 2317 if (!ns) 2318 return ERR_PTR(-ENOTSUPP); 2319 2320 if (num_entries > max_table_size) 2321 return ERR_PTR(-ENOMEM); 2322 2323 ft = prio->flow_table; 2324 if (!ft) { 2325 ft = mlx5_create_auto_grouped_flow_table(ns, priority, 2326 num_entries, 2327 num_groups, 2328 0, 0); 2329 2330 if (!IS_ERR(ft)) { 2331 prio->refcount = 0; 2332 prio->flow_table = ft; 2333 } else { 2334 err = PTR_ERR(ft); 2335 } 2336 } 2337 2338 return err ? ERR_PTR(err) : prio; 2339 } 2340 2341 static void set_underlay_qp(struct mlx5_ib_dev *dev, 2342 struct mlx5_flow_spec *spec, 2343 u32 underlay_qpn) 2344 { 2345 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, 2346 spec->match_criteria, 2347 misc_parameters); 2348 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, 2349 misc_parameters); 2350 2351 if (underlay_qpn && 2352 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 2353 ft_field_support.bth_dst_qp)) { 2354 MLX5_SET(fte_match_set_misc, 2355 misc_params_v, bth_dst_qp, underlay_qpn); 2356 MLX5_SET(fte_match_set_misc, 2357 misc_params_c, bth_dst_qp, 0xffffff); 2358 } 2359 } 2360 2361 static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev, 2362 struct mlx5_ib_flow_prio *ft_prio, 2363 const struct ib_flow_attr *flow_attr, 2364 struct mlx5_flow_destination *dst, 2365 u32 underlay_qpn) 2366 { 2367 struct mlx5_flow_table *ft = ft_prio->flow_table; 2368 struct mlx5_ib_flow_handler *handler; 2369 struct mlx5_flow_act flow_act = {0}; 2370 struct mlx5_flow_spec *spec; 2371 struct mlx5_flow_destination *rule_dst = dst; 2372 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr); 2373 unsigned int spec_index; 2374 u32 flow_tag = MLX5_FS_DEFAULT_FLOW_TAG; 2375 bool is_drop = false; 2376 int err = 0; 2377 int dest_num = 1; 2378 2379 if (!is_valid_attr(dev->mdev, flow_attr)) 2380 return ERR_PTR(-EINVAL); 2381 2382 spec = kvzalloc(sizeof(*spec), GFP_KERNEL); 2383 handler = kzalloc(sizeof(*handler), GFP_KERNEL); 2384 if (!handler || !spec) { 2385 err = -ENOMEM; 2386 goto free; 2387 } 2388 2389 INIT_LIST_HEAD(&handler->list); 2390 2391 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 2392 err = parse_flow_attr(dev->mdev, spec->match_criteria, 2393 spec->match_value, 2394 ib_flow, &flow_tag, &is_drop); 2395 if (err < 0) 2396 goto free; 2397 2398 ib_flow += ((union ib_flow_spec *)ib_flow)->size; 2399 } 2400 2401 if (!flow_is_multicast_only(flow_attr)) 2402 set_underlay_qp(dev, spec, underlay_qpn); 2403 2404 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria); 2405 if (is_drop) { 2406 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_DROP; 2407 rule_dst = NULL; 2408 dest_num = 0; 2409 } else { 2410 flow_act.action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST : 2411 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO; 2412 } 2413 2414 if (flow_tag != MLX5_FS_DEFAULT_FLOW_TAG && 2415 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 2416 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) { 2417 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n", 2418 flow_tag, flow_attr->type); 2419 err = -EINVAL; 2420 goto free; 2421 } 2422 flow_act.flow_tag = flow_tag; 2423 handler->rule = mlx5_add_flow_rules(ft, spec, 2424 &flow_act, 2425 rule_dst, dest_num); 2426 2427 if (IS_ERR(handler->rule)) { 2428 err = PTR_ERR(handler->rule); 2429 goto free; 2430 } 2431 2432 ft_prio->refcount++; 2433 handler->prio = ft_prio; 2434 2435 ft_prio->flow_table = ft; 2436 free: 2437 if (err) 2438 kfree(handler); 2439 kvfree(spec); 2440 return err ? ERR_PTR(err) : handler; 2441 } 2442 2443 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev, 2444 struct mlx5_ib_flow_prio *ft_prio, 2445 const struct ib_flow_attr *flow_attr, 2446 struct mlx5_flow_destination *dst) 2447 { 2448 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0); 2449 } 2450 2451 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev, 2452 struct mlx5_ib_flow_prio *ft_prio, 2453 struct ib_flow_attr *flow_attr, 2454 struct mlx5_flow_destination *dst) 2455 { 2456 struct mlx5_ib_flow_handler *handler_dst = NULL; 2457 struct mlx5_ib_flow_handler *handler = NULL; 2458 2459 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL); 2460 if (!IS_ERR(handler)) { 2461 handler_dst = create_flow_rule(dev, ft_prio, 2462 flow_attr, dst); 2463 if (IS_ERR(handler_dst)) { 2464 mlx5_del_flow_rules(handler->rule); 2465 ft_prio->refcount--; 2466 kfree(handler); 2467 handler = handler_dst; 2468 } else { 2469 list_add(&handler_dst->list, &handler->list); 2470 } 2471 } 2472 2473 return handler; 2474 } 2475 enum { 2476 LEFTOVERS_MC, 2477 LEFTOVERS_UC, 2478 }; 2479 2480 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev, 2481 struct mlx5_ib_flow_prio *ft_prio, 2482 struct ib_flow_attr *flow_attr, 2483 struct mlx5_flow_destination *dst) 2484 { 2485 struct mlx5_ib_flow_handler *handler_ucast = NULL; 2486 struct mlx5_ib_flow_handler *handler = NULL; 2487 2488 static struct { 2489 struct ib_flow_attr flow_attr; 2490 struct ib_flow_spec_eth eth_flow; 2491 } leftovers_specs[] = { 2492 [LEFTOVERS_MC] = { 2493 .flow_attr = { 2494 .num_of_specs = 1, 2495 .size = sizeof(leftovers_specs[0]) 2496 }, 2497 .eth_flow = { 2498 .type = IB_FLOW_SPEC_ETH, 2499 .size = sizeof(struct ib_flow_spec_eth), 2500 .mask = {.dst_mac = {0x1} }, 2501 .val = {.dst_mac = {0x1} } 2502 } 2503 }, 2504 [LEFTOVERS_UC] = { 2505 .flow_attr = { 2506 .num_of_specs = 1, 2507 .size = sizeof(leftovers_specs[0]) 2508 }, 2509 .eth_flow = { 2510 .type = IB_FLOW_SPEC_ETH, 2511 .size = sizeof(struct ib_flow_spec_eth), 2512 .mask = {.dst_mac = {0x1} }, 2513 .val = {.dst_mac = {} } 2514 } 2515 } 2516 }; 2517 2518 handler = create_flow_rule(dev, ft_prio, 2519 &leftovers_specs[LEFTOVERS_MC].flow_attr, 2520 dst); 2521 if (!IS_ERR(handler) && 2522 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) { 2523 handler_ucast = create_flow_rule(dev, ft_prio, 2524 &leftovers_specs[LEFTOVERS_UC].flow_attr, 2525 dst); 2526 if (IS_ERR(handler_ucast)) { 2527 mlx5_del_flow_rules(handler->rule); 2528 ft_prio->refcount--; 2529 kfree(handler); 2530 handler = handler_ucast; 2531 } else { 2532 list_add(&handler_ucast->list, &handler->list); 2533 } 2534 } 2535 2536 return handler; 2537 } 2538 2539 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev, 2540 struct mlx5_ib_flow_prio *ft_rx, 2541 struct mlx5_ib_flow_prio *ft_tx, 2542 struct mlx5_flow_destination *dst) 2543 { 2544 struct mlx5_ib_flow_handler *handler_rx; 2545 struct mlx5_ib_flow_handler *handler_tx; 2546 int err; 2547 static const struct ib_flow_attr flow_attr = { 2548 .num_of_specs = 0, 2549 .size = sizeof(flow_attr) 2550 }; 2551 2552 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst); 2553 if (IS_ERR(handler_rx)) { 2554 err = PTR_ERR(handler_rx); 2555 goto err; 2556 } 2557 2558 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst); 2559 if (IS_ERR(handler_tx)) { 2560 err = PTR_ERR(handler_tx); 2561 goto err_tx; 2562 } 2563 2564 list_add(&handler_tx->list, &handler_rx->list); 2565 2566 return handler_rx; 2567 2568 err_tx: 2569 mlx5_del_flow_rules(handler_rx->rule); 2570 ft_rx->refcount--; 2571 kfree(handler_rx); 2572 err: 2573 return ERR_PTR(err); 2574 } 2575 2576 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp, 2577 struct ib_flow_attr *flow_attr, 2578 int domain) 2579 { 2580 struct mlx5_ib_dev *dev = to_mdev(qp->device); 2581 struct mlx5_ib_qp *mqp = to_mqp(qp); 2582 struct mlx5_ib_flow_handler *handler = NULL; 2583 struct mlx5_flow_destination *dst = NULL; 2584 struct mlx5_ib_flow_prio *ft_prio_tx = NULL; 2585 struct mlx5_ib_flow_prio *ft_prio; 2586 int err; 2587 int underlay_qpn; 2588 2589 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) 2590 return ERR_PTR(-ENOMEM); 2591 2592 if (domain != IB_FLOW_DOMAIN_USER || 2593 flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) || 2594 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP)) 2595 return ERR_PTR(-EINVAL); 2596 2597 dst = kzalloc(sizeof(*dst), GFP_KERNEL); 2598 if (!dst) 2599 return ERR_PTR(-ENOMEM); 2600 2601 mutex_lock(&dev->flow_db.lock); 2602 2603 ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX); 2604 if (IS_ERR(ft_prio)) { 2605 err = PTR_ERR(ft_prio); 2606 goto unlock; 2607 } 2608 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 2609 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX); 2610 if (IS_ERR(ft_prio_tx)) { 2611 err = PTR_ERR(ft_prio_tx); 2612 ft_prio_tx = NULL; 2613 goto destroy_ft; 2614 } 2615 } 2616 2617 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR; 2618 if (mqp->flags & MLX5_IB_QP_RSS) 2619 dst->tir_num = mqp->rss_qp.tirn; 2620 else 2621 dst->tir_num = mqp->raw_packet_qp.rq.tirn; 2622 2623 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 2624 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) { 2625 handler = create_dont_trap_rule(dev, ft_prio, 2626 flow_attr, dst); 2627 } else { 2628 underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ? 2629 mqp->underlay_qpn : 0; 2630 handler = _create_flow_rule(dev, ft_prio, flow_attr, 2631 dst, underlay_qpn); 2632 } 2633 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 2634 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 2635 handler = create_leftovers_rule(dev, ft_prio, flow_attr, 2636 dst); 2637 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 2638 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst); 2639 } else { 2640 err = -EINVAL; 2641 goto destroy_ft; 2642 } 2643 2644 if (IS_ERR(handler)) { 2645 err = PTR_ERR(handler); 2646 handler = NULL; 2647 goto destroy_ft; 2648 } 2649 2650 mutex_unlock(&dev->flow_db.lock); 2651 kfree(dst); 2652 2653 return &handler->ibflow; 2654 2655 destroy_ft: 2656 put_flow_table(dev, ft_prio, false); 2657 if (ft_prio_tx) 2658 put_flow_table(dev, ft_prio_tx, false); 2659 unlock: 2660 mutex_unlock(&dev->flow_db.lock); 2661 kfree(dst); 2662 kfree(handler); 2663 return ERR_PTR(err); 2664 } 2665 2666 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2667 { 2668 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2669 struct mlx5_ib_qp *mqp = to_mqp(ibqp); 2670 int err; 2671 2672 if (mqp->flags & MLX5_IB_QP_UNDERLAY) { 2673 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n"); 2674 return -EOPNOTSUPP; 2675 } 2676 2677 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num); 2678 if (err) 2679 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 2680 ibqp->qp_num, gid->raw); 2681 2682 return err; 2683 } 2684 2685 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2686 { 2687 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2688 int err; 2689 2690 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num); 2691 if (err) 2692 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 2693 ibqp->qp_num, gid->raw); 2694 2695 return err; 2696 } 2697 2698 static int init_node_data(struct mlx5_ib_dev *dev) 2699 { 2700 int err; 2701 2702 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 2703 if (err) 2704 return err; 2705 2706 dev->mdev->rev_id = dev->mdev->pdev->revision; 2707 2708 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 2709 } 2710 2711 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr, 2712 char *buf) 2713 { 2714 struct mlx5_ib_dev *dev = 2715 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2716 2717 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages); 2718 } 2719 2720 static ssize_t show_reg_pages(struct device *device, 2721 struct device_attribute *attr, char *buf) 2722 { 2723 struct mlx5_ib_dev *dev = 2724 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2725 2726 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 2727 } 2728 2729 static ssize_t show_hca(struct device *device, struct device_attribute *attr, 2730 char *buf) 2731 { 2732 struct mlx5_ib_dev *dev = 2733 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2734 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device); 2735 } 2736 2737 static ssize_t show_rev(struct device *device, struct device_attribute *attr, 2738 char *buf) 2739 { 2740 struct mlx5_ib_dev *dev = 2741 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2742 return sprintf(buf, "%x\n", dev->mdev->rev_id); 2743 } 2744 2745 static ssize_t show_board(struct device *device, struct device_attribute *attr, 2746 char *buf) 2747 { 2748 struct mlx5_ib_dev *dev = 2749 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2750 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 2751 dev->mdev->board_id); 2752 } 2753 2754 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL); 2755 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL); 2756 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL); 2757 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL); 2758 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL); 2759 2760 static struct device_attribute *mlx5_class_attributes[] = { 2761 &dev_attr_hw_rev, 2762 &dev_attr_hca_type, 2763 &dev_attr_board_id, 2764 &dev_attr_fw_pages, 2765 &dev_attr_reg_pages, 2766 }; 2767 2768 static void pkey_change_handler(struct work_struct *work) 2769 { 2770 struct mlx5_ib_port_resources *ports = 2771 container_of(work, struct mlx5_ib_port_resources, 2772 pkey_change_work); 2773 2774 mutex_lock(&ports->devr->mutex); 2775 mlx5_ib_gsi_pkey_change(ports->gsi); 2776 mutex_unlock(&ports->devr->mutex); 2777 } 2778 2779 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 2780 { 2781 struct mlx5_ib_qp *mqp; 2782 struct mlx5_ib_cq *send_mcq, *recv_mcq; 2783 struct mlx5_core_cq *mcq; 2784 struct list_head cq_armed_list; 2785 unsigned long flags_qp; 2786 unsigned long flags_cq; 2787 unsigned long flags; 2788 2789 INIT_LIST_HEAD(&cq_armed_list); 2790 2791 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 2792 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 2793 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 2794 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 2795 if (mqp->sq.tail != mqp->sq.head) { 2796 send_mcq = to_mcq(mqp->ibqp.send_cq); 2797 spin_lock_irqsave(&send_mcq->lock, flags_cq); 2798 if (send_mcq->mcq.comp && 2799 mqp->ibqp.send_cq->comp_handler) { 2800 if (!send_mcq->mcq.reset_notify_added) { 2801 send_mcq->mcq.reset_notify_added = 1; 2802 list_add_tail(&send_mcq->mcq.reset_notify, 2803 &cq_armed_list); 2804 } 2805 } 2806 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 2807 } 2808 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 2809 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 2810 /* no handling is needed for SRQ */ 2811 if (!mqp->ibqp.srq) { 2812 if (mqp->rq.tail != mqp->rq.head) { 2813 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 2814 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 2815 if (recv_mcq->mcq.comp && 2816 mqp->ibqp.recv_cq->comp_handler) { 2817 if (!recv_mcq->mcq.reset_notify_added) { 2818 recv_mcq->mcq.reset_notify_added = 1; 2819 list_add_tail(&recv_mcq->mcq.reset_notify, 2820 &cq_armed_list); 2821 } 2822 } 2823 spin_unlock_irqrestore(&recv_mcq->lock, 2824 flags_cq); 2825 } 2826 } 2827 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 2828 } 2829 /*At that point all inflight post send were put to be executed as of we 2830 * lock/unlock above locks Now need to arm all involved CQs. 2831 */ 2832 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 2833 mcq->comp(mcq); 2834 } 2835 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 2836 } 2837 2838 static void delay_drop_handler(struct work_struct *work) 2839 { 2840 int err; 2841 struct mlx5_ib_delay_drop *delay_drop = 2842 container_of(work, struct mlx5_ib_delay_drop, 2843 delay_drop_work); 2844 2845 atomic_inc(&delay_drop->events_cnt); 2846 2847 mutex_lock(&delay_drop->lock); 2848 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev, 2849 delay_drop->timeout); 2850 if (err) { 2851 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n", 2852 delay_drop->timeout); 2853 delay_drop->activate = false; 2854 } 2855 mutex_unlock(&delay_drop->lock); 2856 } 2857 2858 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context, 2859 enum mlx5_dev_event event, unsigned long param) 2860 { 2861 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context; 2862 struct ib_event ibev; 2863 bool fatal = false; 2864 u8 port = 0; 2865 2866 switch (event) { 2867 case MLX5_DEV_EVENT_SYS_ERROR: 2868 ibev.event = IB_EVENT_DEVICE_FATAL; 2869 mlx5_ib_handle_internal_error(ibdev); 2870 fatal = true; 2871 break; 2872 2873 case MLX5_DEV_EVENT_PORT_UP: 2874 case MLX5_DEV_EVENT_PORT_DOWN: 2875 case MLX5_DEV_EVENT_PORT_INITIALIZED: 2876 port = (u8)param; 2877 2878 /* In RoCE, port up/down events are handled in 2879 * mlx5_netdev_event(). 2880 */ 2881 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2882 IB_LINK_LAYER_ETHERNET) 2883 return; 2884 2885 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ? 2886 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 2887 break; 2888 2889 case MLX5_DEV_EVENT_LID_CHANGE: 2890 ibev.event = IB_EVENT_LID_CHANGE; 2891 port = (u8)param; 2892 break; 2893 2894 case MLX5_DEV_EVENT_PKEY_CHANGE: 2895 ibev.event = IB_EVENT_PKEY_CHANGE; 2896 port = (u8)param; 2897 2898 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 2899 break; 2900 2901 case MLX5_DEV_EVENT_GUID_CHANGE: 2902 ibev.event = IB_EVENT_GID_CHANGE; 2903 port = (u8)param; 2904 break; 2905 2906 case MLX5_DEV_EVENT_CLIENT_REREG: 2907 ibev.event = IB_EVENT_CLIENT_REREGISTER; 2908 port = (u8)param; 2909 break; 2910 case MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT: 2911 schedule_work(&ibdev->delay_drop.delay_drop_work); 2912 goto out; 2913 default: 2914 goto out; 2915 } 2916 2917 ibev.device = &ibdev->ib_dev; 2918 ibev.element.port_num = port; 2919 2920 if (port < 1 || port > ibdev->num_ports) { 2921 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port); 2922 goto out; 2923 } 2924 2925 if (ibdev->ib_active) 2926 ib_dispatch_event(&ibev); 2927 2928 if (fatal) 2929 ibdev->ib_active = false; 2930 2931 out: 2932 return; 2933 } 2934 2935 static int set_has_smi_cap(struct mlx5_ib_dev *dev) 2936 { 2937 struct mlx5_hca_vport_context vport_ctx; 2938 int err; 2939 int port; 2940 2941 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) { 2942 dev->mdev->port_caps[port - 1].has_smi = false; 2943 if (MLX5_CAP_GEN(dev->mdev, port_type) == 2944 MLX5_CAP_PORT_TYPE_IB) { 2945 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) { 2946 err = mlx5_query_hca_vport_context(dev->mdev, 0, 2947 port, 0, 2948 &vport_ctx); 2949 if (err) { 2950 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n", 2951 port, err); 2952 return err; 2953 } 2954 dev->mdev->port_caps[port - 1].has_smi = 2955 vport_ctx.has_smi; 2956 } else { 2957 dev->mdev->port_caps[port - 1].has_smi = true; 2958 } 2959 } 2960 } 2961 return 0; 2962 } 2963 2964 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 2965 { 2966 int port; 2967 2968 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) 2969 mlx5_query_ext_port_caps(dev, port); 2970 } 2971 2972 static int get_port_caps(struct mlx5_ib_dev *dev) 2973 { 2974 struct ib_device_attr *dprops = NULL; 2975 struct ib_port_attr *pprops = NULL; 2976 int err = -ENOMEM; 2977 int port; 2978 struct ib_udata uhw = {.inlen = 0, .outlen = 0}; 2979 2980 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL); 2981 if (!pprops) 2982 goto out; 2983 2984 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL); 2985 if (!dprops) 2986 goto out; 2987 2988 err = set_has_smi_cap(dev); 2989 if (err) 2990 goto out; 2991 2992 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw); 2993 if (err) { 2994 mlx5_ib_warn(dev, "query_device failed %d\n", err); 2995 goto out; 2996 } 2997 2998 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) { 2999 memset(pprops, 0, sizeof(*pprops)); 3000 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops); 3001 if (err) { 3002 mlx5_ib_warn(dev, "query_port %d failed %d\n", 3003 port, err); 3004 break; 3005 } 3006 dev->mdev->port_caps[port - 1].pkey_table_len = 3007 dprops->max_pkeys; 3008 dev->mdev->port_caps[port - 1].gid_table_len = 3009 pprops->gid_tbl_len; 3010 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n", 3011 dprops->max_pkeys, pprops->gid_tbl_len); 3012 } 3013 3014 out: 3015 kfree(pprops); 3016 kfree(dprops); 3017 3018 return err; 3019 } 3020 3021 static void destroy_umrc_res(struct mlx5_ib_dev *dev) 3022 { 3023 int err; 3024 3025 err = mlx5_mr_cache_cleanup(dev); 3026 if (err) 3027 mlx5_ib_warn(dev, "mr cache cleanup failed\n"); 3028 3029 mlx5_ib_destroy_qp(dev->umrc.qp); 3030 ib_free_cq(dev->umrc.cq); 3031 ib_dealloc_pd(dev->umrc.pd); 3032 } 3033 3034 enum { 3035 MAX_UMR_WR = 128, 3036 }; 3037 3038 static int create_umr_res(struct mlx5_ib_dev *dev) 3039 { 3040 struct ib_qp_init_attr *init_attr = NULL; 3041 struct ib_qp_attr *attr = NULL; 3042 struct ib_pd *pd; 3043 struct ib_cq *cq; 3044 struct ib_qp *qp; 3045 int ret; 3046 3047 attr = kzalloc(sizeof(*attr), GFP_KERNEL); 3048 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL); 3049 if (!attr || !init_attr) { 3050 ret = -ENOMEM; 3051 goto error_0; 3052 } 3053 3054 pd = ib_alloc_pd(&dev->ib_dev, 0); 3055 if (IS_ERR(pd)) { 3056 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n"); 3057 ret = PTR_ERR(pd); 3058 goto error_0; 3059 } 3060 3061 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ); 3062 if (IS_ERR(cq)) { 3063 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n"); 3064 ret = PTR_ERR(cq); 3065 goto error_2; 3066 } 3067 3068 init_attr->send_cq = cq; 3069 init_attr->recv_cq = cq; 3070 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR; 3071 init_attr->cap.max_send_wr = MAX_UMR_WR; 3072 init_attr->cap.max_send_sge = 1; 3073 init_attr->qp_type = MLX5_IB_QPT_REG_UMR; 3074 init_attr->port_num = 1; 3075 qp = mlx5_ib_create_qp(pd, init_attr, NULL); 3076 if (IS_ERR(qp)) { 3077 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n"); 3078 ret = PTR_ERR(qp); 3079 goto error_3; 3080 } 3081 qp->device = &dev->ib_dev; 3082 qp->real_qp = qp; 3083 qp->uobject = NULL; 3084 qp->qp_type = MLX5_IB_QPT_REG_UMR; 3085 3086 attr->qp_state = IB_QPS_INIT; 3087 attr->port_num = 1; 3088 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX | 3089 IB_QP_PORT, NULL); 3090 if (ret) { 3091 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n"); 3092 goto error_4; 3093 } 3094 3095 memset(attr, 0, sizeof(*attr)); 3096 attr->qp_state = IB_QPS_RTR; 3097 attr->path_mtu = IB_MTU_256; 3098 3099 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 3100 if (ret) { 3101 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n"); 3102 goto error_4; 3103 } 3104 3105 memset(attr, 0, sizeof(*attr)); 3106 attr->qp_state = IB_QPS_RTS; 3107 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 3108 if (ret) { 3109 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n"); 3110 goto error_4; 3111 } 3112 3113 dev->umrc.qp = qp; 3114 dev->umrc.cq = cq; 3115 dev->umrc.pd = pd; 3116 3117 sema_init(&dev->umrc.sem, MAX_UMR_WR); 3118 ret = mlx5_mr_cache_init(dev); 3119 if (ret) { 3120 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 3121 goto error_4; 3122 } 3123 3124 kfree(attr); 3125 kfree(init_attr); 3126 3127 return 0; 3128 3129 error_4: 3130 mlx5_ib_destroy_qp(qp); 3131 3132 error_3: 3133 ib_free_cq(cq); 3134 3135 error_2: 3136 ib_dealloc_pd(pd); 3137 3138 error_0: 3139 kfree(attr); 3140 kfree(init_attr); 3141 return ret; 3142 } 3143 3144 static u8 mlx5_get_umr_fence(u8 umr_fence_cap) 3145 { 3146 switch (umr_fence_cap) { 3147 case MLX5_CAP_UMR_FENCE_NONE: 3148 return MLX5_FENCE_MODE_NONE; 3149 case MLX5_CAP_UMR_FENCE_SMALL: 3150 return MLX5_FENCE_MODE_INITIATOR_SMALL; 3151 default: 3152 return MLX5_FENCE_MODE_STRONG_ORDERING; 3153 } 3154 } 3155 3156 static int create_dev_resources(struct mlx5_ib_resources *devr) 3157 { 3158 struct ib_srq_init_attr attr; 3159 struct mlx5_ib_dev *dev; 3160 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 3161 int port; 3162 int ret = 0; 3163 3164 dev = container_of(devr, struct mlx5_ib_dev, devr); 3165 3166 mutex_init(&devr->mutex); 3167 3168 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL); 3169 if (IS_ERR(devr->p0)) { 3170 ret = PTR_ERR(devr->p0); 3171 goto error0; 3172 } 3173 devr->p0->device = &dev->ib_dev; 3174 devr->p0->uobject = NULL; 3175 atomic_set(&devr->p0->usecnt, 0); 3176 3177 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL); 3178 if (IS_ERR(devr->c0)) { 3179 ret = PTR_ERR(devr->c0); 3180 goto error1; 3181 } 3182 devr->c0->device = &dev->ib_dev; 3183 devr->c0->uobject = NULL; 3184 devr->c0->comp_handler = NULL; 3185 devr->c0->event_handler = NULL; 3186 devr->c0->cq_context = NULL; 3187 atomic_set(&devr->c0->usecnt, 0); 3188 3189 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 3190 if (IS_ERR(devr->x0)) { 3191 ret = PTR_ERR(devr->x0); 3192 goto error2; 3193 } 3194 devr->x0->device = &dev->ib_dev; 3195 devr->x0->inode = NULL; 3196 atomic_set(&devr->x0->usecnt, 0); 3197 mutex_init(&devr->x0->tgt_qp_mutex); 3198 INIT_LIST_HEAD(&devr->x0->tgt_qp_list); 3199 3200 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 3201 if (IS_ERR(devr->x1)) { 3202 ret = PTR_ERR(devr->x1); 3203 goto error3; 3204 } 3205 devr->x1->device = &dev->ib_dev; 3206 devr->x1->inode = NULL; 3207 atomic_set(&devr->x1->usecnt, 0); 3208 mutex_init(&devr->x1->tgt_qp_mutex); 3209 INIT_LIST_HEAD(&devr->x1->tgt_qp_list); 3210 3211 memset(&attr, 0, sizeof(attr)); 3212 attr.attr.max_sge = 1; 3213 attr.attr.max_wr = 1; 3214 attr.srq_type = IB_SRQT_XRC; 3215 attr.ext.xrc.cq = devr->c0; 3216 attr.ext.xrc.xrcd = devr->x0; 3217 3218 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 3219 if (IS_ERR(devr->s0)) { 3220 ret = PTR_ERR(devr->s0); 3221 goto error4; 3222 } 3223 devr->s0->device = &dev->ib_dev; 3224 devr->s0->pd = devr->p0; 3225 devr->s0->uobject = NULL; 3226 devr->s0->event_handler = NULL; 3227 devr->s0->srq_context = NULL; 3228 devr->s0->srq_type = IB_SRQT_XRC; 3229 devr->s0->ext.xrc.xrcd = devr->x0; 3230 devr->s0->ext.xrc.cq = devr->c0; 3231 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt); 3232 atomic_inc(&devr->s0->ext.xrc.cq->usecnt); 3233 atomic_inc(&devr->p0->usecnt); 3234 atomic_set(&devr->s0->usecnt, 0); 3235 3236 memset(&attr, 0, sizeof(attr)); 3237 attr.attr.max_sge = 1; 3238 attr.attr.max_wr = 1; 3239 attr.srq_type = IB_SRQT_BASIC; 3240 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 3241 if (IS_ERR(devr->s1)) { 3242 ret = PTR_ERR(devr->s1); 3243 goto error5; 3244 } 3245 devr->s1->device = &dev->ib_dev; 3246 devr->s1->pd = devr->p0; 3247 devr->s1->uobject = NULL; 3248 devr->s1->event_handler = NULL; 3249 devr->s1->srq_context = NULL; 3250 devr->s1->srq_type = IB_SRQT_BASIC; 3251 devr->s1->ext.xrc.cq = devr->c0; 3252 atomic_inc(&devr->p0->usecnt); 3253 atomic_set(&devr->s0->usecnt, 0); 3254 3255 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) { 3256 INIT_WORK(&devr->ports[port].pkey_change_work, 3257 pkey_change_handler); 3258 devr->ports[port].devr = devr; 3259 } 3260 3261 return 0; 3262 3263 error5: 3264 mlx5_ib_destroy_srq(devr->s0); 3265 error4: 3266 mlx5_ib_dealloc_xrcd(devr->x1); 3267 error3: 3268 mlx5_ib_dealloc_xrcd(devr->x0); 3269 error2: 3270 mlx5_ib_destroy_cq(devr->c0); 3271 error1: 3272 mlx5_ib_dealloc_pd(devr->p0); 3273 error0: 3274 return ret; 3275 } 3276 3277 static void destroy_dev_resources(struct mlx5_ib_resources *devr) 3278 { 3279 struct mlx5_ib_dev *dev = 3280 container_of(devr, struct mlx5_ib_dev, devr); 3281 int port; 3282 3283 mlx5_ib_destroy_srq(devr->s1); 3284 mlx5_ib_destroy_srq(devr->s0); 3285 mlx5_ib_dealloc_xrcd(devr->x0); 3286 mlx5_ib_dealloc_xrcd(devr->x1); 3287 mlx5_ib_destroy_cq(devr->c0); 3288 mlx5_ib_dealloc_pd(devr->p0); 3289 3290 /* Make sure no change P_Key work items are still executing */ 3291 for (port = 0; port < dev->num_ports; ++port) 3292 cancel_work_sync(&devr->ports[port].pkey_change_work); 3293 } 3294 3295 static u32 get_core_cap_flags(struct ib_device *ibdev) 3296 { 3297 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3298 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 3299 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 3300 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 3301 u32 ret = 0; 3302 3303 if (ll == IB_LINK_LAYER_INFINIBAND) 3304 return RDMA_CORE_PORT_IBA_IB; 3305 3306 ret = RDMA_CORE_PORT_RAW_PACKET; 3307 3308 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 3309 return ret; 3310 3311 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 3312 return ret; 3313 3314 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 3315 ret |= RDMA_CORE_PORT_IBA_ROCE; 3316 3317 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 3318 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 3319 3320 return ret; 3321 } 3322 3323 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num, 3324 struct ib_port_immutable *immutable) 3325 { 3326 struct ib_port_attr attr; 3327 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3328 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num); 3329 int err; 3330 3331 immutable->core_cap_flags = get_core_cap_flags(ibdev); 3332 3333 err = ib_query_port(ibdev, port_num, &attr); 3334 if (err) 3335 return err; 3336 3337 immutable->pkey_tbl_len = attr.pkey_tbl_len; 3338 immutable->gid_tbl_len = attr.gid_tbl_len; 3339 immutable->core_cap_flags = get_core_cap_flags(ibdev); 3340 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce)) 3341 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 3342 3343 return 0; 3344 } 3345 3346 static void get_dev_fw_str(struct ib_device *ibdev, char *str) 3347 { 3348 struct mlx5_ib_dev *dev = 3349 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 3350 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d", 3351 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev), 3352 fw_rev_sub(dev->mdev)); 3353 } 3354 3355 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev) 3356 { 3357 struct mlx5_core_dev *mdev = dev->mdev; 3358 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev, 3359 MLX5_FLOW_NAMESPACE_LAG); 3360 struct mlx5_flow_table *ft; 3361 int err; 3362 3363 if (!ns || !mlx5_lag_is_active(mdev)) 3364 return 0; 3365 3366 err = mlx5_cmd_create_vport_lag(mdev); 3367 if (err) 3368 return err; 3369 3370 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0); 3371 if (IS_ERR(ft)) { 3372 err = PTR_ERR(ft); 3373 goto err_destroy_vport_lag; 3374 } 3375 3376 dev->flow_db.lag_demux_ft = ft; 3377 return 0; 3378 3379 err_destroy_vport_lag: 3380 mlx5_cmd_destroy_vport_lag(mdev); 3381 return err; 3382 } 3383 3384 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev) 3385 { 3386 struct mlx5_core_dev *mdev = dev->mdev; 3387 3388 if (dev->flow_db.lag_demux_ft) { 3389 mlx5_destroy_flow_table(dev->flow_db.lag_demux_ft); 3390 dev->flow_db.lag_demux_ft = NULL; 3391 3392 mlx5_cmd_destroy_vport_lag(mdev); 3393 } 3394 } 3395 3396 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev) 3397 { 3398 int err; 3399 3400 dev->roce.nb.notifier_call = mlx5_netdev_event; 3401 err = register_netdevice_notifier(&dev->roce.nb); 3402 if (err) { 3403 dev->roce.nb.notifier_call = NULL; 3404 return err; 3405 } 3406 3407 return 0; 3408 } 3409 3410 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev) 3411 { 3412 if (dev->roce.nb.notifier_call) { 3413 unregister_netdevice_notifier(&dev->roce.nb); 3414 dev->roce.nb.notifier_call = NULL; 3415 } 3416 } 3417 3418 static int mlx5_enable_eth(struct mlx5_ib_dev *dev) 3419 { 3420 int err; 3421 3422 err = mlx5_add_netdev_notifier(dev); 3423 if (err) 3424 return err; 3425 3426 if (MLX5_CAP_GEN(dev->mdev, roce)) { 3427 err = mlx5_nic_vport_enable_roce(dev->mdev); 3428 if (err) 3429 goto err_unregister_netdevice_notifier; 3430 } 3431 3432 err = mlx5_eth_lag_init(dev); 3433 if (err) 3434 goto err_disable_roce; 3435 3436 return 0; 3437 3438 err_disable_roce: 3439 if (MLX5_CAP_GEN(dev->mdev, roce)) 3440 mlx5_nic_vport_disable_roce(dev->mdev); 3441 3442 err_unregister_netdevice_notifier: 3443 mlx5_remove_netdev_notifier(dev); 3444 return err; 3445 } 3446 3447 static void mlx5_disable_eth(struct mlx5_ib_dev *dev) 3448 { 3449 mlx5_eth_lag_cleanup(dev); 3450 if (MLX5_CAP_GEN(dev->mdev, roce)) 3451 mlx5_nic_vport_disable_roce(dev->mdev); 3452 } 3453 3454 struct mlx5_ib_counter { 3455 const char *name; 3456 size_t offset; 3457 }; 3458 3459 #define INIT_Q_COUNTER(_name) \ 3460 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)} 3461 3462 static const struct mlx5_ib_counter basic_q_cnts[] = { 3463 INIT_Q_COUNTER(rx_write_requests), 3464 INIT_Q_COUNTER(rx_read_requests), 3465 INIT_Q_COUNTER(rx_atomic_requests), 3466 INIT_Q_COUNTER(out_of_buffer), 3467 }; 3468 3469 static const struct mlx5_ib_counter out_of_seq_q_cnts[] = { 3470 INIT_Q_COUNTER(out_of_sequence), 3471 }; 3472 3473 static const struct mlx5_ib_counter retrans_q_cnts[] = { 3474 INIT_Q_COUNTER(duplicate_request), 3475 INIT_Q_COUNTER(rnr_nak_retry_err), 3476 INIT_Q_COUNTER(packet_seq_err), 3477 INIT_Q_COUNTER(implied_nak_seq_err), 3478 INIT_Q_COUNTER(local_ack_timeout_err), 3479 }; 3480 3481 #define INIT_CONG_COUNTER(_name) \ 3482 { .name = #_name, .offset = \ 3483 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)} 3484 3485 static const struct mlx5_ib_counter cong_cnts[] = { 3486 INIT_CONG_COUNTER(rp_cnp_ignored), 3487 INIT_CONG_COUNTER(rp_cnp_handled), 3488 INIT_CONG_COUNTER(np_ecn_marked_roce_packets), 3489 INIT_CONG_COUNTER(np_cnp_sent), 3490 }; 3491 3492 static const struct mlx5_ib_counter extended_err_cnts[] = { 3493 INIT_Q_COUNTER(resp_local_length_error), 3494 INIT_Q_COUNTER(resp_cqe_error), 3495 INIT_Q_COUNTER(req_cqe_error), 3496 INIT_Q_COUNTER(req_remote_invalid_request), 3497 INIT_Q_COUNTER(req_remote_access_errors), 3498 INIT_Q_COUNTER(resp_remote_access_errors), 3499 INIT_Q_COUNTER(resp_cqe_flush_error), 3500 INIT_Q_COUNTER(req_cqe_flush_error), 3501 }; 3502 3503 static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev) 3504 { 3505 unsigned int i; 3506 3507 for (i = 0; i < dev->num_ports; i++) { 3508 mlx5_core_dealloc_q_counter(dev->mdev, 3509 dev->port[i].cnts.set_id); 3510 kfree(dev->port[i].cnts.names); 3511 kfree(dev->port[i].cnts.offsets); 3512 } 3513 } 3514 3515 static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev, 3516 struct mlx5_ib_counters *cnts) 3517 { 3518 u32 num_counters; 3519 3520 num_counters = ARRAY_SIZE(basic_q_cnts); 3521 3522 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) 3523 num_counters += ARRAY_SIZE(out_of_seq_q_cnts); 3524 3525 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) 3526 num_counters += ARRAY_SIZE(retrans_q_cnts); 3527 3528 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) 3529 num_counters += ARRAY_SIZE(extended_err_cnts); 3530 3531 cnts->num_q_counters = num_counters; 3532 3533 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 3534 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts); 3535 num_counters += ARRAY_SIZE(cong_cnts); 3536 } 3537 3538 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL); 3539 if (!cnts->names) 3540 return -ENOMEM; 3541 3542 cnts->offsets = kcalloc(num_counters, 3543 sizeof(cnts->offsets), GFP_KERNEL); 3544 if (!cnts->offsets) 3545 goto err_names; 3546 3547 return 0; 3548 3549 err_names: 3550 kfree(cnts->names); 3551 return -ENOMEM; 3552 } 3553 3554 static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev, 3555 const char **names, 3556 size_t *offsets) 3557 { 3558 int i; 3559 int j = 0; 3560 3561 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) { 3562 names[j] = basic_q_cnts[i].name; 3563 offsets[j] = basic_q_cnts[i].offset; 3564 } 3565 3566 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) { 3567 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) { 3568 names[j] = out_of_seq_q_cnts[i].name; 3569 offsets[j] = out_of_seq_q_cnts[i].offset; 3570 } 3571 } 3572 3573 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) { 3574 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) { 3575 names[j] = retrans_q_cnts[i].name; 3576 offsets[j] = retrans_q_cnts[i].offset; 3577 } 3578 } 3579 3580 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) { 3581 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) { 3582 names[j] = extended_err_cnts[i].name; 3583 offsets[j] = extended_err_cnts[i].offset; 3584 } 3585 } 3586 3587 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 3588 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) { 3589 names[j] = cong_cnts[i].name; 3590 offsets[j] = cong_cnts[i].offset; 3591 } 3592 } 3593 } 3594 3595 static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev) 3596 { 3597 int i; 3598 int ret; 3599 3600 for (i = 0; i < dev->num_ports; i++) { 3601 struct mlx5_ib_port *port = &dev->port[i]; 3602 3603 ret = mlx5_core_alloc_q_counter(dev->mdev, 3604 &port->cnts.set_id); 3605 if (ret) { 3606 mlx5_ib_warn(dev, 3607 "couldn't allocate queue counter for port %d, err %d\n", 3608 i + 1, ret); 3609 goto dealloc_counters; 3610 } 3611 3612 ret = __mlx5_ib_alloc_counters(dev, &port->cnts); 3613 if (ret) 3614 goto dealloc_counters; 3615 3616 mlx5_ib_fill_counters(dev, port->cnts.names, 3617 port->cnts.offsets); 3618 } 3619 3620 return 0; 3621 3622 dealloc_counters: 3623 while (--i >= 0) 3624 mlx5_core_dealloc_q_counter(dev->mdev, 3625 dev->port[i].cnts.set_id); 3626 3627 return ret; 3628 } 3629 3630 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev, 3631 u8 port_num) 3632 { 3633 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3634 struct mlx5_ib_port *port = &dev->port[port_num - 1]; 3635 3636 /* We support only per port stats */ 3637 if (port_num == 0) 3638 return NULL; 3639 3640 return rdma_alloc_hw_stats_struct(port->cnts.names, 3641 port->cnts.num_q_counters + 3642 port->cnts.num_cong_counters, 3643 RDMA_HW_STATS_DEFAULT_LIFESPAN); 3644 } 3645 3646 static int mlx5_ib_query_q_counters(struct mlx5_ib_dev *dev, 3647 struct mlx5_ib_port *port, 3648 struct rdma_hw_stats *stats) 3649 { 3650 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out); 3651 void *out; 3652 __be32 val; 3653 int ret, i; 3654 3655 out = kvzalloc(outlen, GFP_KERNEL); 3656 if (!out) 3657 return -ENOMEM; 3658 3659 ret = mlx5_core_query_q_counter(dev->mdev, 3660 port->cnts.set_id, 0, 3661 out, outlen); 3662 if (ret) 3663 goto free; 3664 3665 for (i = 0; i < port->cnts.num_q_counters; i++) { 3666 val = *(__be32 *)(out + port->cnts.offsets[i]); 3667 stats->value[i] = (u64)be32_to_cpu(val); 3668 } 3669 3670 free: 3671 kvfree(out); 3672 return ret; 3673 } 3674 3675 static int mlx5_ib_query_cong_counters(struct mlx5_ib_dev *dev, 3676 struct mlx5_ib_port *port, 3677 struct rdma_hw_stats *stats) 3678 { 3679 int outlen = MLX5_ST_SZ_BYTES(query_cong_statistics_out); 3680 void *out; 3681 int ret, i; 3682 int offset = port->cnts.num_q_counters; 3683 3684 out = kvzalloc(outlen, GFP_KERNEL); 3685 if (!out) 3686 return -ENOMEM; 3687 3688 ret = mlx5_cmd_query_cong_counter(dev->mdev, false, out, outlen); 3689 if (ret) 3690 goto free; 3691 3692 for (i = 0; i < port->cnts.num_cong_counters; i++) { 3693 stats->value[i + offset] = 3694 be64_to_cpup((__be64 *)(out + 3695 port->cnts.offsets[i + offset])); 3696 } 3697 3698 free: 3699 kvfree(out); 3700 return ret; 3701 } 3702 3703 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev, 3704 struct rdma_hw_stats *stats, 3705 u8 port_num, int index) 3706 { 3707 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3708 struct mlx5_ib_port *port = &dev->port[port_num - 1]; 3709 int ret, num_counters; 3710 3711 if (!stats) 3712 return -EINVAL; 3713 3714 ret = mlx5_ib_query_q_counters(dev, port, stats); 3715 if (ret) 3716 return ret; 3717 num_counters = port->cnts.num_q_counters; 3718 3719 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 3720 ret = mlx5_ib_query_cong_counters(dev, port, stats); 3721 if (ret) 3722 return ret; 3723 num_counters += port->cnts.num_cong_counters; 3724 } 3725 3726 return num_counters; 3727 } 3728 3729 static void mlx5_ib_free_rdma_netdev(struct net_device *netdev) 3730 { 3731 return mlx5_rdma_netdev_free(netdev); 3732 } 3733 3734 static struct net_device* 3735 mlx5_ib_alloc_rdma_netdev(struct ib_device *hca, 3736 u8 port_num, 3737 enum rdma_netdev_t type, 3738 const char *name, 3739 unsigned char name_assign_type, 3740 void (*setup)(struct net_device *)) 3741 { 3742 struct net_device *netdev; 3743 struct rdma_netdev *rn; 3744 3745 if (type != RDMA_NETDEV_IPOIB) 3746 return ERR_PTR(-EOPNOTSUPP); 3747 3748 netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca, 3749 name, setup); 3750 if (likely(!IS_ERR_OR_NULL(netdev))) { 3751 rn = netdev_priv(netdev); 3752 rn->free_rdma_netdev = mlx5_ib_free_rdma_netdev; 3753 } 3754 return netdev; 3755 } 3756 3757 static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev) 3758 { 3759 if (!dev->delay_drop.dbg) 3760 return; 3761 debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs); 3762 kfree(dev->delay_drop.dbg); 3763 dev->delay_drop.dbg = NULL; 3764 } 3765 3766 static void cancel_delay_drop(struct mlx5_ib_dev *dev) 3767 { 3768 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 3769 return; 3770 3771 cancel_work_sync(&dev->delay_drop.delay_drop_work); 3772 delay_drop_debugfs_cleanup(dev); 3773 } 3774 3775 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf, 3776 size_t count, loff_t *pos) 3777 { 3778 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3779 char lbuf[20]; 3780 int len; 3781 3782 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout); 3783 return simple_read_from_buffer(buf, count, pos, lbuf, len); 3784 } 3785 3786 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf, 3787 size_t count, loff_t *pos) 3788 { 3789 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3790 u32 timeout; 3791 u32 var; 3792 3793 if (kstrtouint_from_user(buf, count, 0, &var)) 3794 return -EFAULT; 3795 3796 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 3797 1000); 3798 if (timeout != var) 3799 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n", 3800 timeout); 3801 3802 delay_drop->timeout = timeout; 3803 3804 return count; 3805 } 3806 3807 static const struct file_operations fops_delay_drop_timeout = { 3808 .owner = THIS_MODULE, 3809 .open = simple_open, 3810 .write = delay_drop_timeout_write, 3811 .read = delay_drop_timeout_read, 3812 }; 3813 3814 static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev) 3815 { 3816 struct mlx5_ib_dbg_delay_drop *dbg; 3817 3818 if (!mlx5_debugfs_root) 3819 return 0; 3820 3821 dbg = kzalloc(sizeof(*dbg), GFP_KERNEL); 3822 if (!dbg) 3823 return -ENOMEM; 3824 3825 dbg->dir_debugfs = 3826 debugfs_create_dir("delay_drop", 3827 dev->mdev->priv.dbg_root); 3828 if (!dbg->dir_debugfs) 3829 return -ENOMEM; 3830 3831 dbg->events_cnt_debugfs = 3832 debugfs_create_atomic_t("num_timeout_events", 0400, 3833 dbg->dir_debugfs, 3834 &dev->delay_drop.events_cnt); 3835 if (!dbg->events_cnt_debugfs) 3836 goto out_debugfs; 3837 3838 dbg->rqs_cnt_debugfs = 3839 debugfs_create_atomic_t("num_rqs", 0400, 3840 dbg->dir_debugfs, 3841 &dev->delay_drop.rqs_cnt); 3842 if (!dbg->rqs_cnt_debugfs) 3843 goto out_debugfs; 3844 3845 dbg->timeout_debugfs = 3846 debugfs_create_file("timeout", 0600, 3847 dbg->dir_debugfs, 3848 &dev->delay_drop, 3849 &fops_delay_drop_timeout); 3850 if (!dbg->timeout_debugfs) 3851 goto out_debugfs; 3852 3853 dev->delay_drop.dbg = dbg; 3854 3855 return 0; 3856 3857 out_debugfs: 3858 delay_drop_debugfs_cleanup(dev); 3859 return -ENOMEM; 3860 } 3861 3862 static void init_delay_drop(struct mlx5_ib_dev *dev) 3863 { 3864 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 3865 return; 3866 3867 mutex_init(&dev->delay_drop.lock); 3868 dev->delay_drop.dev = dev; 3869 dev->delay_drop.activate = false; 3870 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000; 3871 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler); 3872 atomic_set(&dev->delay_drop.rqs_cnt, 0); 3873 atomic_set(&dev->delay_drop.events_cnt, 0); 3874 3875 if (delay_drop_debugfs_init(dev)) 3876 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n"); 3877 } 3878 3879 static const struct cpumask * 3880 mlx5_ib_get_vector_affinity(struct ib_device *ibdev, int comp_vector) 3881 { 3882 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3883 3884 return mlx5_get_vector_affinity(dev->mdev, comp_vector); 3885 } 3886 3887 static void *mlx5_ib_add(struct mlx5_core_dev *mdev) 3888 { 3889 struct mlx5_ib_dev *dev; 3890 enum rdma_link_layer ll; 3891 int port_type_cap; 3892 const char *name; 3893 int err; 3894 int i; 3895 3896 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 3897 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 3898 3899 printk_once(KERN_INFO "%s", mlx5_version); 3900 3901 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev)); 3902 if (!dev) 3903 return NULL; 3904 3905 dev->mdev = mdev; 3906 3907 dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port), 3908 GFP_KERNEL); 3909 if (!dev->port) 3910 goto err_dealloc; 3911 3912 rwlock_init(&dev->roce.netdev_lock); 3913 err = get_port_caps(dev); 3914 if (err) 3915 goto err_free_port; 3916 3917 if (mlx5_use_mad_ifc(dev)) 3918 get_ext_port_caps(dev); 3919 3920 if (!mlx5_lag_is_active(mdev)) 3921 name = "mlx5_%d"; 3922 else 3923 name = "mlx5_bond_%d"; 3924 3925 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX); 3926 dev->ib_dev.owner = THIS_MODULE; 3927 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 3928 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 3929 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports); 3930 dev->ib_dev.phys_port_cnt = dev->num_ports; 3931 dev->ib_dev.num_comp_vectors = 3932 dev->mdev->priv.eq_table.num_comp_vectors; 3933 dev->ib_dev.dev.parent = &mdev->pdev->dev; 3934 3935 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION; 3936 dev->ib_dev.uverbs_cmd_mask = 3937 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | 3938 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | 3939 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | 3940 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | 3941 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | 3942 (1ull << IB_USER_VERBS_CMD_CREATE_AH) | 3943 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) | 3944 (1ull << IB_USER_VERBS_CMD_REG_MR) | 3945 (1ull << IB_USER_VERBS_CMD_REREG_MR) | 3946 (1ull << IB_USER_VERBS_CMD_DEREG_MR) | 3947 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 3948 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | 3949 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) | 3950 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | 3951 (1ull << IB_USER_VERBS_CMD_CREATE_QP) | 3952 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | 3953 (1ull << IB_USER_VERBS_CMD_QUERY_QP) | 3954 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | 3955 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) | 3956 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) | 3957 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | 3958 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | 3959 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | 3960 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | 3961 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) | 3962 (1ull << IB_USER_VERBS_CMD_OPEN_QP); 3963 dev->ib_dev.uverbs_ex_cmd_mask = 3964 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) | 3965 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) | 3966 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) | 3967 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP); 3968 3969 dev->ib_dev.query_device = mlx5_ib_query_device; 3970 dev->ib_dev.query_port = mlx5_ib_query_port; 3971 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer; 3972 if (ll == IB_LINK_LAYER_ETHERNET) 3973 dev->ib_dev.get_netdev = mlx5_ib_get_netdev; 3974 dev->ib_dev.query_gid = mlx5_ib_query_gid; 3975 dev->ib_dev.add_gid = mlx5_ib_add_gid; 3976 dev->ib_dev.del_gid = mlx5_ib_del_gid; 3977 dev->ib_dev.query_pkey = mlx5_ib_query_pkey; 3978 dev->ib_dev.modify_device = mlx5_ib_modify_device; 3979 dev->ib_dev.modify_port = mlx5_ib_modify_port; 3980 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext; 3981 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext; 3982 dev->ib_dev.mmap = mlx5_ib_mmap; 3983 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd; 3984 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd; 3985 dev->ib_dev.create_ah = mlx5_ib_create_ah; 3986 dev->ib_dev.query_ah = mlx5_ib_query_ah; 3987 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah; 3988 dev->ib_dev.create_srq = mlx5_ib_create_srq; 3989 dev->ib_dev.modify_srq = mlx5_ib_modify_srq; 3990 dev->ib_dev.query_srq = mlx5_ib_query_srq; 3991 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq; 3992 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv; 3993 dev->ib_dev.create_qp = mlx5_ib_create_qp; 3994 dev->ib_dev.modify_qp = mlx5_ib_modify_qp; 3995 dev->ib_dev.query_qp = mlx5_ib_query_qp; 3996 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp; 3997 dev->ib_dev.post_send = mlx5_ib_post_send; 3998 dev->ib_dev.post_recv = mlx5_ib_post_recv; 3999 dev->ib_dev.create_cq = mlx5_ib_create_cq; 4000 dev->ib_dev.modify_cq = mlx5_ib_modify_cq; 4001 dev->ib_dev.resize_cq = mlx5_ib_resize_cq; 4002 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq; 4003 dev->ib_dev.poll_cq = mlx5_ib_poll_cq; 4004 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq; 4005 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr; 4006 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr; 4007 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr; 4008 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr; 4009 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach; 4010 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach; 4011 dev->ib_dev.process_mad = mlx5_ib_process_mad; 4012 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr; 4013 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg; 4014 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status; 4015 dev->ib_dev.get_port_immutable = mlx5_port_immutable; 4016 dev->ib_dev.get_dev_fw_str = get_dev_fw_str; 4017 dev->ib_dev.get_vector_affinity = mlx5_ib_get_vector_affinity; 4018 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads)) 4019 dev->ib_dev.alloc_rdma_netdev = mlx5_ib_alloc_rdma_netdev; 4020 4021 if (mlx5_core_is_pf(mdev)) { 4022 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config; 4023 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state; 4024 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats; 4025 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid; 4026 } 4027 4028 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext; 4029 4030 mlx5_ib_internal_fill_odp_caps(dev); 4031 4032 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence)); 4033 4034 if (MLX5_CAP_GEN(mdev, imaicl)) { 4035 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw; 4036 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw; 4037 dev->ib_dev.uverbs_cmd_mask |= 4038 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) | 4039 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW); 4040 } 4041 4042 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) { 4043 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats; 4044 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats; 4045 } 4046 4047 if (MLX5_CAP_GEN(mdev, xrc)) { 4048 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd; 4049 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd; 4050 dev->ib_dev.uverbs_cmd_mask |= 4051 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) | 4052 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD); 4053 } 4054 4055 dev->ib_dev.create_flow = mlx5_ib_create_flow; 4056 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow; 4057 dev->ib_dev.uverbs_ex_cmd_mask |= 4058 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) | 4059 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW); 4060 4061 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) == 4062 IB_LINK_LAYER_ETHERNET) { 4063 dev->ib_dev.create_wq = mlx5_ib_create_wq; 4064 dev->ib_dev.modify_wq = mlx5_ib_modify_wq; 4065 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq; 4066 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table; 4067 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table; 4068 dev->ib_dev.uverbs_ex_cmd_mask |= 4069 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) | 4070 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) | 4071 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) | 4072 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) | 4073 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL); 4074 } 4075 err = init_node_data(dev); 4076 if (err) 4077 goto err_free_port; 4078 4079 mutex_init(&dev->flow_db.lock); 4080 mutex_init(&dev->cap_mask_mutex); 4081 INIT_LIST_HEAD(&dev->qp_list); 4082 spin_lock_init(&dev->reset_flow_resource_lock); 4083 4084 if (ll == IB_LINK_LAYER_ETHERNET) { 4085 err = mlx5_enable_eth(dev); 4086 if (err) 4087 goto err_free_port; 4088 dev->roce.last_port_state = IB_PORT_DOWN; 4089 } 4090 4091 err = create_dev_resources(&dev->devr); 4092 if (err) 4093 goto err_disable_eth; 4094 4095 err = mlx5_ib_odp_init_one(dev); 4096 if (err) 4097 goto err_rsrc; 4098 4099 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) { 4100 err = mlx5_ib_alloc_counters(dev); 4101 if (err) 4102 goto err_odp; 4103 } 4104 4105 err = mlx5_ib_init_cong_debugfs(dev); 4106 if (err) 4107 goto err_cnt; 4108 4109 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev); 4110 if (!dev->mdev->priv.uar) 4111 goto err_cong; 4112 4113 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false); 4114 if (err) 4115 goto err_uar_page; 4116 4117 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true); 4118 if (err) 4119 goto err_bfreg; 4120 4121 err = ib_register_device(&dev->ib_dev, NULL); 4122 if (err) 4123 goto err_fp_bfreg; 4124 4125 err = create_umr_res(dev); 4126 if (err) 4127 goto err_dev; 4128 4129 init_delay_drop(dev); 4130 4131 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) { 4132 err = device_create_file(&dev->ib_dev.dev, 4133 mlx5_class_attributes[i]); 4134 if (err) 4135 goto err_delay_drop; 4136 } 4137 4138 if ((MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && 4139 MLX5_CAP_GEN(mdev, disable_local_lb)) 4140 mutex_init(&dev->lb_mutex); 4141 4142 dev->ib_active = true; 4143 4144 return dev; 4145 4146 err_delay_drop: 4147 cancel_delay_drop(dev); 4148 destroy_umrc_res(dev); 4149 4150 err_dev: 4151 ib_unregister_device(&dev->ib_dev); 4152 4153 err_fp_bfreg: 4154 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 4155 4156 err_bfreg: 4157 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4158 4159 err_uar_page: 4160 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar); 4161 4162 err_cnt: 4163 mlx5_ib_cleanup_cong_debugfs(dev); 4164 err_cong: 4165 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) 4166 mlx5_ib_dealloc_counters(dev); 4167 4168 err_odp: 4169 mlx5_ib_odp_remove_one(dev); 4170 4171 err_rsrc: 4172 destroy_dev_resources(&dev->devr); 4173 4174 err_disable_eth: 4175 if (ll == IB_LINK_LAYER_ETHERNET) { 4176 mlx5_disable_eth(dev); 4177 mlx5_remove_netdev_notifier(dev); 4178 } 4179 4180 err_free_port: 4181 kfree(dev->port); 4182 4183 err_dealloc: 4184 ib_dealloc_device((struct ib_device *)dev); 4185 4186 return NULL; 4187 } 4188 4189 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context) 4190 { 4191 struct mlx5_ib_dev *dev = context; 4192 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1); 4193 4194 cancel_delay_drop(dev); 4195 mlx5_remove_netdev_notifier(dev); 4196 ib_unregister_device(&dev->ib_dev); 4197 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 4198 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4199 mlx5_put_uars_page(dev->mdev, mdev->priv.uar); 4200 mlx5_ib_cleanup_cong_debugfs(dev); 4201 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) 4202 mlx5_ib_dealloc_counters(dev); 4203 destroy_umrc_res(dev); 4204 mlx5_ib_odp_remove_one(dev); 4205 destroy_dev_resources(&dev->devr); 4206 if (ll == IB_LINK_LAYER_ETHERNET) 4207 mlx5_disable_eth(dev); 4208 kfree(dev->port); 4209 ib_dealloc_device(&dev->ib_dev); 4210 } 4211 4212 static struct mlx5_interface mlx5_ib_interface = { 4213 .add = mlx5_ib_add, 4214 .remove = mlx5_ib_remove, 4215 .event = mlx5_ib_event, 4216 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 4217 .pfault = mlx5_ib_pfault, 4218 #endif 4219 .protocol = MLX5_INTERFACE_PROTOCOL_IB, 4220 }; 4221 4222 static int __init mlx5_ib_init(void) 4223 { 4224 int err; 4225 4226 mlx5_ib_odp_init(); 4227 4228 err = mlx5_register_interface(&mlx5_ib_interface); 4229 4230 return err; 4231 } 4232 4233 static void __exit mlx5_ib_cleanup(void) 4234 { 4235 mlx5_unregister_interface(&mlx5_ib_interface); 4236 } 4237 4238 module_init(mlx5_ib_init); 4239 module_exit(mlx5_ib_cleanup); 4240