1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/debugfs.h> 34 #include <linux/highmem.h> 35 #include <linux/module.h> 36 #include <linux/init.h> 37 #include <linux/errno.h> 38 #include <linux/pci.h> 39 #include <linux/dma-mapping.h> 40 #include <linux/slab.h> 41 #if defined(CONFIG_X86) 42 #include <asm/pat.h> 43 #endif 44 #include <linux/sched.h> 45 #include <linux/sched/mm.h> 46 #include <linux/sched/task.h> 47 #include <linux/delay.h> 48 #include <rdma/ib_user_verbs.h> 49 #include <rdma/ib_addr.h> 50 #include <rdma/ib_cache.h> 51 #include <linux/mlx5/port.h> 52 #include <linux/mlx5/vport.h> 53 #include <linux/mlx5/fs.h> 54 #include <linux/list.h> 55 #include <rdma/ib_smi.h> 56 #include <rdma/ib_umem.h> 57 #include <linux/in.h> 58 #include <linux/etherdevice.h> 59 #include "mlx5_ib.h" 60 #include "cmd.h" 61 62 #define DRIVER_NAME "mlx5_ib" 63 #define DRIVER_VERSION "5.0-0" 64 65 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 66 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver"); 67 MODULE_LICENSE("Dual BSD/GPL"); 68 69 static char mlx5_version[] = 70 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v" 71 DRIVER_VERSION "\n"; 72 73 struct mlx5_ib_event_work { 74 struct work_struct work; 75 struct mlx5_core_dev *dev; 76 void *context; 77 enum mlx5_dev_event event; 78 unsigned long param; 79 }; 80 81 enum { 82 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 83 }; 84 85 static struct workqueue_struct *mlx5_ib_event_wq; 86 static LIST_HEAD(mlx5_ib_unaffiliated_port_list); 87 static LIST_HEAD(mlx5_ib_dev_list); 88 /* 89 * This mutex should be held when accessing either of the above lists 90 */ 91 static DEFINE_MUTEX(mlx5_ib_multiport_mutex); 92 93 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi) 94 { 95 struct mlx5_ib_dev *dev; 96 97 mutex_lock(&mlx5_ib_multiport_mutex); 98 dev = mpi->ibdev; 99 mutex_unlock(&mlx5_ib_multiport_mutex); 100 return dev; 101 } 102 103 static enum rdma_link_layer 104 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 105 { 106 switch (port_type_cap) { 107 case MLX5_CAP_PORT_TYPE_IB: 108 return IB_LINK_LAYER_INFINIBAND; 109 case MLX5_CAP_PORT_TYPE_ETH: 110 return IB_LINK_LAYER_ETHERNET; 111 default: 112 return IB_LINK_LAYER_UNSPECIFIED; 113 } 114 } 115 116 static enum rdma_link_layer 117 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num) 118 { 119 struct mlx5_ib_dev *dev = to_mdev(device); 120 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 121 122 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 123 } 124 125 static int get_port_state(struct ib_device *ibdev, 126 u8 port_num, 127 enum ib_port_state *state) 128 { 129 struct ib_port_attr attr; 130 int ret; 131 132 memset(&attr, 0, sizeof(attr)); 133 ret = mlx5_ib_query_port(ibdev, port_num, &attr); 134 if (!ret) 135 *state = attr.state; 136 return ret; 137 } 138 139 static int mlx5_netdev_event(struct notifier_block *this, 140 unsigned long event, void *ptr) 141 { 142 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb); 143 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 144 u8 port_num = roce->native_port_num; 145 struct mlx5_core_dev *mdev; 146 struct mlx5_ib_dev *ibdev; 147 148 ibdev = roce->dev; 149 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 150 if (!mdev) 151 return NOTIFY_DONE; 152 153 switch (event) { 154 case NETDEV_REGISTER: 155 case NETDEV_UNREGISTER: 156 write_lock(&roce->netdev_lock); 157 158 if (ndev->dev.parent == &mdev->pdev->dev) 159 roce->netdev = (event == NETDEV_UNREGISTER) ? 160 NULL : ndev; 161 write_unlock(&roce->netdev_lock); 162 break; 163 164 case NETDEV_CHANGE: 165 case NETDEV_UP: 166 case NETDEV_DOWN: { 167 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev); 168 struct net_device *upper = NULL; 169 170 if (lag_ndev) { 171 upper = netdev_master_upper_dev_get(lag_ndev); 172 dev_put(lag_ndev); 173 } 174 175 if ((upper == ndev || (!upper && ndev == roce->netdev)) 176 && ibdev->ib_active) { 177 struct ib_event ibev = { }; 178 enum ib_port_state port_state; 179 180 if (get_port_state(&ibdev->ib_dev, port_num, 181 &port_state)) 182 goto done; 183 184 if (roce->last_port_state == port_state) 185 goto done; 186 187 roce->last_port_state = port_state; 188 ibev.device = &ibdev->ib_dev; 189 if (port_state == IB_PORT_DOWN) 190 ibev.event = IB_EVENT_PORT_ERR; 191 else if (port_state == IB_PORT_ACTIVE) 192 ibev.event = IB_EVENT_PORT_ACTIVE; 193 else 194 goto done; 195 196 ibev.element.port_num = port_num; 197 ib_dispatch_event(&ibev); 198 } 199 break; 200 } 201 202 default: 203 break; 204 } 205 done: 206 mlx5_ib_put_native_port_mdev(ibdev, port_num); 207 return NOTIFY_DONE; 208 } 209 210 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device, 211 u8 port_num) 212 { 213 struct mlx5_ib_dev *ibdev = to_mdev(device); 214 struct net_device *ndev; 215 struct mlx5_core_dev *mdev; 216 217 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 218 if (!mdev) 219 return NULL; 220 221 ndev = mlx5_lag_get_roce_netdev(mdev); 222 if (ndev) 223 goto out; 224 225 /* Ensure ndev does not disappear before we invoke dev_hold() 226 */ 227 read_lock(&ibdev->roce[port_num - 1].netdev_lock); 228 ndev = ibdev->roce[port_num - 1].netdev; 229 if (ndev) 230 dev_hold(ndev); 231 read_unlock(&ibdev->roce[port_num - 1].netdev_lock); 232 233 out: 234 mlx5_ib_put_native_port_mdev(ibdev, port_num); 235 return ndev; 236 } 237 238 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev, 239 u8 ib_port_num, 240 u8 *native_port_num) 241 { 242 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 243 ib_port_num); 244 struct mlx5_core_dev *mdev = NULL; 245 struct mlx5_ib_multiport_info *mpi; 246 struct mlx5_ib_port *port; 247 248 if (native_port_num) 249 *native_port_num = 1; 250 251 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 252 return ibdev->mdev; 253 254 port = &ibdev->port[ib_port_num - 1]; 255 if (!port) 256 return NULL; 257 258 spin_lock(&port->mp.mpi_lock); 259 mpi = ibdev->port[ib_port_num - 1].mp.mpi; 260 if (mpi && !mpi->unaffiliate) { 261 mdev = mpi->mdev; 262 /* If it's the master no need to refcount, it'll exist 263 * as long as the ib_dev exists. 264 */ 265 if (!mpi->is_master) 266 mpi->mdev_refcnt++; 267 } 268 spin_unlock(&port->mp.mpi_lock); 269 270 return mdev; 271 } 272 273 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num) 274 { 275 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 276 port_num); 277 struct mlx5_ib_multiport_info *mpi; 278 struct mlx5_ib_port *port; 279 280 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 281 return; 282 283 port = &ibdev->port[port_num - 1]; 284 285 spin_lock(&port->mp.mpi_lock); 286 mpi = ibdev->port[port_num - 1].mp.mpi; 287 if (mpi->is_master) 288 goto out; 289 290 mpi->mdev_refcnt--; 291 if (mpi->unaffiliate) 292 complete(&mpi->unref_comp); 293 out: 294 spin_unlock(&port->mp.mpi_lock); 295 } 296 297 static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed, 298 u8 *active_width) 299 { 300 switch (eth_proto_oper) { 301 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII): 302 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX): 303 case MLX5E_PROT_MASK(MLX5E_100BASE_TX): 304 case MLX5E_PROT_MASK(MLX5E_1000BASE_T): 305 *active_width = IB_WIDTH_1X; 306 *active_speed = IB_SPEED_SDR; 307 break; 308 case MLX5E_PROT_MASK(MLX5E_10GBASE_T): 309 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4): 310 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4): 311 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR): 312 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR): 313 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR): 314 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER): 315 *active_width = IB_WIDTH_1X; 316 *active_speed = IB_SPEED_QDR; 317 break; 318 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR): 319 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR): 320 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR): 321 *active_width = IB_WIDTH_1X; 322 *active_speed = IB_SPEED_EDR; 323 break; 324 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4): 325 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4): 326 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4): 327 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4): 328 *active_width = IB_WIDTH_4X; 329 *active_speed = IB_SPEED_QDR; 330 break; 331 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2): 332 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2): 333 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2): 334 *active_width = IB_WIDTH_1X; 335 *active_speed = IB_SPEED_HDR; 336 break; 337 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4): 338 *active_width = IB_WIDTH_4X; 339 *active_speed = IB_SPEED_FDR; 340 break; 341 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4): 342 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4): 343 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4): 344 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4): 345 *active_width = IB_WIDTH_4X; 346 *active_speed = IB_SPEED_EDR; 347 break; 348 default: 349 return -EINVAL; 350 } 351 352 return 0; 353 } 354 355 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num, 356 struct ib_port_attr *props) 357 { 358 struct mlx5_ib_dev *dev = to_mdev(device); 359 struct mlx5_core_dev *mdev; 360 struct net_device *ndev, *upper; 361 enum ib_mtu ndev_ib_mtu; 362 bool put_mdev = true; 363 u16 qkey_viol_cntr; 364 u32 eth_prot_oper; 365 u8 mdev_port_num; 366 int err; 367 368 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 369 if (!mdev) { 370 /* This means the port isn't affiliated yet. Get the 371 * info for the master port instead. 372 */ 373 put_mdev = false; 374 mdev = dev->mdev; 375 mdev_port_num = 1; 376 port_num = 1; 377 } 378 379 /* Possible bad flows are checked before filling out props so in case 380 * of an error it will still be zeroed out. 381 */ 382 err = mlx5_query_port_eth_proto_oper(mdev, ð_prot_oper, 383 mdev_port_num); 384 if (err) 385 goto out; 386 387 translate_eth_proto_oper(eth_prot_oper, &props->active_speed, 388 &props->active_width); 389 390 props->port_cap_flags |= IB_PORT_CM_SUP; 391 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS; 392 393 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 394 roce_address_table_size); 395 props->max_mtu = IB_MTU_4096; 396 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 397 props->pkey_tbl_len = 1; 398 props->state = IB_PORT_DOWN; 399 props->phys_state = 3; 400 401 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr); 402 props->qkey_viol_cntr = qkey_viol_cntr; 403 404 /* If this is a stub query for an unaffiliated port stop here */ 405 if (!put_mdev) 406 goto out; 407 408 ndev = mlx5_ib_get_netdev(device, port_num); 409 if (!ndev) 410 goto out; 411 412 if (mlx5_lag_is_active(dev->mdev)) { 413 rcu_read_lock(); 414 upper = netdev_master_upper_dev_get_rcu(ndev); 415 if (upper) { 416 dev_put(ndev); 417 ndev = upper; 418 dev_hold(ndev); 419 } 420 rcu_read_unlock(); 421 } 422 423 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 424 props->state = IB_PORT_ACTIVE; 425 props->phys_state = 5; 426 } 427 428 ndev_ib_mtu = iboe_get_mtu(ndev->mtu); 429 430 dev_put(ndev); 431 432 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 433 out: 434 if (put_mdev) 435 mlx5_ib_put_native_port_mdev(dev, port_num); 436 return err; 437 } 438 439 static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num, 440 unsigned int index, const union ib_gid *gid, 441 const struct ib_gid_attr *attr) 442 { 443 enum ib_gid_type gid_type = IB_GID_TYPE_IB; 444 u8 roce_version = 0; 445 u8 roce_l3_type = 0; 446 bool vlan = false; 447 u8 mac[ETH_ALEN]; 448 u16 vlan_id = 0; 449 450 if (gid) { 451 gid_type = attr->gid_type; 452 ether_addr_copy(mac, attr->ndev->dev_addr); 453 454 if (is_vlan_dev(attr->ndev)) { 455 vlan = true; 456 vlan_id = vlan_dev_vlan_id(attr->ndev); 457 } 458 } 459 460 switch (gid_type) { 461 case IB_GID_TYPE_IB: 462 roce_version = MLX5_ROCE_VERSION_1; 463 break; 464 case IB_GID_TYPE_ROCE_UDP_ENCAP: 465 roce_version = MLX5_ROCE_VERSION_2; 466 if (ipv6_addr_v4mapped((void *)gid)) 467 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4; 468 else 469 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6; 470 break; 471 472 default: 473 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type); 474 } 475 476 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version, 477 roce_l3_type, gid->raw, mac, vlan, 478 vlan_id, port_num); 479 } 480 481 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num, 482 unsigned int index, const union ib_gid *gid, 483 const struct ib_gid_attr *attr, 484 __always_unused void **context) 485 { 486 return set_roce_addr(to_mdev(device), port_num, index, gid, attr); 487 } 488 489 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num, 490 unsigned int index, __always_unused void **context) 491 { 492 return set_roce_addr(to_mdev(device), port_num, index, NULL, NULL); 493 } 494 495 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num, 496 int index) 497 { 498 struct ib_gid_attr attr; 499 union ib_gid gid; 500 501 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr)) 502 return 0; 503 504 if (!attr.ndev) 505 return 0; 506 507 dev_put(attr.ndev); 508 509 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 510 return 0; 511 512 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 513 } 514 515 int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num, 516 int index, enum ib_gid_type *gid_type) 517 { 518 struct ib_gid_attr attr; 519 union ib_gid gid; 520 int ret; 521 522 ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr); 523 if (ret) 524 return ret; 525 526 if (!attr.ndev) 527 return -ENODEV; 528 529 dev_put(attr.ndev); 530 531 *gid_type = attr.gid_type; 532 533 return 0; 534 } 535 536 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 537 { 538 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 539 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 540 return 0; 541 } 542 543 enum { 544 MLX5_VPORT_ACCESS_METHOD_MAD, 545 MLX5_VPORT_ACCESS_METHOD_HCA, 546 MLX5_VPORT_ACCESS_METHOD_NIC, 547 }; 548 549 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 550 { 551 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 552 return MLX5_VPORT_ACCESS_METHOD_MAD; 553 554 if (mlx5_ib_port_link_layer(ibdev, 1) == 555 IB_LINK_LAYER_ETHERNET) 556 return MLX5_VPORT_ACCESS_METHOD_NIC; 557 558 return MLX5_VPORT_ACCESS_METHOD_HCA; 559 } 560 561 static void get_atomic_caps(struct mlx5_ib_dev *dev, 562 u8 atomic_size_qp, 563 struct ib_device_attr *props) 564 { 565 u8 tmp; 566 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 567 u8 atomic_req_8B_endianness_mode = 568 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode); 569 570 /* Check if HW supports 8 bytes standard atomic operations and capable 571 * of host endianness respond 572 */ 573 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 574 if (((atomic_operations & tmp) == tmp) && 575 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 576 (atomic_req_8B_endianness_mode)) { 577 props->atomic_cap = IB_ATOMIC_HCA; 578 } else { 579 props->atomic_cap = IB_ATOMIC_NONE; 580 } 581 } 582 583 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev, 584 struct ib_device_attr *props) 585 { 586 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 587 588 get_atomic_caps(dev, atomic_size_qp, props); 589 } 590 591 static void get_atomic_caps_dc(struct mlx5_ib_dev *dev, 592 struct ib_device_attr *props) 593 { 594 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc); 595 596 get_atomic_caps(dev, atomic_size_qp, props); 597 } 598 599 bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev) 600 { 601 struct ib_device_attr props = {}; 602 603 get_atomic_caps_dc(dev, &props); 604 return (props.atomic_cap == IB_ATOMIC_HCA) ? true : false; 605 } 606 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 607 __be64 *sys_image_guid) 608 { 609 struct mlx5_ib_dev *dev = to_mdev(ibdev); 610 struct mlx5_core_dev *mdev = dev->mdev; 611 u64 tmp; 612 int err; 613 614 switch (mlx5_get_vport_access_method(ibdev)) { 615 case MLX5_VPORT_ACCESS_METHOD_MAD: 616 return mlx5_query_mad_ifc_system_image_guid(ibdev, 617 sys_image_guid); 618 619 case MLX5_VPORT_ACCESS_METHOD_HCA: 620 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 621 break; 622 623 case MLX5_VPORT_ACCESS_METHOD_NIC: 624 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 625 break; 626 627 default: 628 return -EINVAL; 629 } 630 631 if (!err) 632 *sys_image_guid = cpu_to_be64(tmp); 633 634 return err; 635 636 } 637 638 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 639 u16 *max_pkeys) 640 { 641 struct mlx5_ib_dev *dev = to_mdev(ibdev); 642 struct mlx5_core_dev *mdev = dev->mdev; 643 644 switch (mlx5_get_vport_access_method(ibdev)) { 645 case MLX5_VPORT_ACCESS_METHOD_MAD: 646 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 647 648 case MLX5_VPORT_ACCESS_METHOD_HCA: 649 case MLX5_VPORT_ACCESS_METHOD_NIC: 650 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 651 pkey_table_size)); 652 return 0; 653 654 default: 655 return -EINVAL; 656 } 657 } 658 659 static int mlx5_query_vendor_id(struct ib_device *ibdev, 660 u32 *vendor_id) 661 { 662 struct mlx5_ib_dev *dev = to_mdev(ibdev); 663 664 switch (mlx5_get_vport_access_method(ibdev)) { 665 case MLX5_VPORT_ACCESS_METHOD_MAD: 666 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 667 668 case MLX5_VPORT_ACCESS_METHOD_HCA: 669 case MLX5_VPORT_ACCESS_METHOD_NIC: 670 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 671 672 default: 673 return -EINVAL; 674 } 675 } 676 677 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 678 __be64 *node_guid) 679 { 680 u64 tmp; 681 int err; 682 683 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 684 case MLX5_VPORT_ACCESS_METHOD_MAD: 685 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 686 687 case MLX5_VPORT_ACCESS_METHOD_HCA: 688 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 689 break; 690 691 case MLX5_VPORT_ACCESS_METHOD_NIC: 692 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 693 break; 694 695 default: 696 return -EINVAL; 697 } 698 699 if (!err) 700 *node_guid = cpu_to_be64(tmp); 701 702 return err; 703 } 704 705 struct mlx5_reg_node_desc { 706 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 707 }; 708 709 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 710 { 711 struct mlx5_reg_node_desc in; 712 713 if (mlx5_use_mad_ifc(dev)) 714 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 715 716 memset(&in, 0, sizeof(in)); 717 718 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 719 sizeof(struct mlx5_reg_node_desc), 720 MLX5_REG_NODE_DESC, 0, 0); 721 } 722 723 static int mlx5_ib_query_device(struct ib_device *ibdev, 724 struct ib_device_attr *props, 725 struct ib_udata *uhw) 726 { 727 struct mlx5_ib_dev *dev = to_mdev(ibdev); 728 struct mlx5_core_dev *mdev = dev->mdev; 729 int err = -ENOMEM; 730 int max_sq_desc; 731 int max_rq_sg; 732 int max_sq_sg; 733 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 734 bool raw_support = !mlx5_core_mp_enabled(mdev); 735 struct mlx5_ib_query_device_resp resp = {}; 736 size_t resp_len; 737 u64 max_tso; 738 739 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 740 if (uhw->outlen && uhw->outlen < resp_len) 741 return -EINVAL; 742 else 743 resp.response_length = resp_len; 744 745 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) 746 return -EINVAL; 747 748 memset(props, 0, sizeof(*props)); 749 err = mlx5_query_system_image_guid(ibdev, 750 &props->sys_image_guid); 751 if (err) 752 return err; 753 754 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys); 755 if (err) 756 return err; 757 758 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 759 if (err) 760 return err; 761 762 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 763 (fw_rev_min(dev->mdev) << 16) | 764 fw_rev_sub(dev->mdev); 765 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 766 IB_DEVICE_PORT_ACTIVE_EVENT | 767 IB_DEVICE_SYS_IMAGE_GUID | 768 IB_DEVICE_RC_RNR_NAK_GEN; 769 770 if (MLX5_CAP_GEN(mdev, pkv)) 771 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 772 if (MLX5_CAP_GEN(mdev, qkv)) 773 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 774 if (MLX5_CAP_GEN(mdev, apm)) 775 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 776 if (MLX5_CAP_GEN(mdev, xrc)) 777 props->device_cap_flags |= IB_DEVICE_XRC; 778 if (MLX5_CAP_GEN(mdev, imaicl)) { 779 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 780 IB_DEVICE_MEM_WINDOW_TYPE_2B; 781 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 782 /* We support 'Gappy' memory registration too */ 783 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG; 784 } 785 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 786 if (MLX5_CAP_GEN(mdev, sho)) { 787 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER; 788 /* At this stage no support for signature handover */ 789 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 790 IB_PROT_T10DIF_TYPE_2 | 791 IB_PROT_T10DIF_TYPE_3; 792 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 793 IB_GUARD_T10DIF_CSUM; 794 } 795 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 796 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 797 798 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) { 799 if (MLX5_CAP_ETH(mdev, csum_cap)) { 800 /* Legacy bit to support old userspace libraries */ 801 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 802 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM; 803 } 804 805 if (MLX5_CAP_ETH(dev->mdev, vlan_cap)) 806 props->raw_packet_caps |= 807 IB_RAW_PACKET_CAP_CVLAN_STRIPPING; 808 809 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) { 810 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 811 if (max_tso) { 812 resp.tso_caps.max_tso = 1 << max_tso; 813 resp.tso_caps.supported_qpts |= 814 1 << IB_QPT_RAW_PACKET; 815 resp.response_length += sizeof(resp.tso_caps); 816 } 817 } 818 819 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) { 820 resp.rss_caps.rx_hash_function = 821 MLX5_RX_HASH_FUNC_TOEPLITZ; 822 resp.rss_caps.rx_hash_fields_mask = 823 MLX5_RX_HASH_SRC_IPV4 | 824 MLX5_RX_HASH_DST_IPV4 | 825 MLX5_RX_HASH_SRC_IPV6 | 826 MLX5_RX_HASH_DST_IPV6 | 827 MLX5_RX_HASH_SRC_PORT_TCP | 828 MLX5_RX_HASH_DST_PORT_TCP | 829 MLX5_RX_HASH_SRC_PORT_UDP | 830 MLX5_RX_HASH_DST_PORT_UDP | 831 MLX5_RX_HASH_INNER; 832 resp.response_length += sizeof(resp.rss_caps); 833 } 834 } else { 835 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) 836 resp.response_length += sizeof(resp.tso_caps); 837 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) 838 resp.response_length += sizeof(resp.rss_caps); 839 } 840 841 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 842 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 843 props->device_cap_flags |= IB_DEVICE_UD_TSO; 844 } 845 846 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) && 847 MLX5_CAP_GEN(dev->mdev, general_notification_event) && 848 raw_support) 849 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP; 850 851 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 852 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap)) 853 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 854 855 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 856 MLX5_CAP_ETH(dev->mdev, scatter_fcs) && 857 raw_support) { 858 /* Legacy bit to support old userspace libraries */ 859 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 860 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; 861 } 862 863 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 864 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 865 866 if (MLX5_CAP_GEN(mdev, end_pad)) 867 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING; 868 869 props->vendor_part_id = mdev->pdev->device; 870 props->hw_ver = mdev->pdev->revision; 871 872 props->max_mr_size = ~0ull; 873 props->page_size_cap = ~(min_page_size - 1); 874 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 875 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 876 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 877 sizeof(struct mlx5_wqe_data_seg); 878 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512); 879 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) - 880 sizeof(struct mlx5_wqe_raddr_seg)) / 881 sizeof(struct mlx5_wqe_data_seg); 882 props->max_sge = min(max_rq_sg, max_sq_sg); 883 props->max_sge_rd = MLX5_MAX_SGE_RD; 884 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 885 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 886 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 887 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 888 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 889 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 890 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 891 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 892 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 893 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 894 props->max_srq_sge = max_rq_sg - 1; 895 props->max_fast_reg_page_list_len = 896 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 897 get_atomic_caps_qp(dev, props); 898 props->masked_atomic_cap = IB_ATOMIC_NONE; 899 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 900 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 901 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 902 props->max_mcast_grp; 903 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */ 904 props->max_ah = INT_MAX; 905 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 906 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 907 908 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 909 if (MLX5_CAP_GEN(mdev, pg)) 910 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING; 911 props->odp_caps = dev->odp_caps; 912 #endif 913 914 if (MLX5_CAP_GEN(mdev, cd)) 915 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL; 916 917 if (!mlx5_core_is_pf(mdev)) 918 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION; 919 920 if (mlx5_ib_port_link_layer(ibdev, 1) == 921 IB_LINK_LAYER_ETHERNET && raw_support) { 922 props->rss_caps.max_rwq_indirection_tables = 923 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 924 props->rss_caps.max_rwq_indirection_table_size = 925 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 926 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 927 props->max_wq_type_rq = 928 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 929 } 930 931 if (MLX5_CAP_GEN(mdev, tag_matching)) { 932 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE; 933 props->tm_caps.max_num_tags = 934 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1; 935 props->tm_caps.flags = IB_TM_CAP_RC; 936 props->tm_caps.max_ops = 937 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 938 props->tm_caps.max_sge = MLX5_TM_MAX_SGE; 939 } 940 941 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) { 942 props->cq_caps.max_cq_moderation_count = 943 MLX5_MAX_CQ_COUNT; 944 props->cq_caps.max_cq_moderation_period = 945 MLX5_MAX_CQ_PERIOD; 946 } 947 948 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) { 949 resp.cqe_comp_caps.max_num = 950 MLX5_CAP_GEN(dev->mdev, cqe_compression) ? 951 MLX5_CAP_GEN(dev->mdev, cqe_compression_max_num) : 0; 952 resp.cqe_comp_caps.supported_format = 953 MLX5_IB_CQE_RES_FORMAT_HASH | 954 MLX5_IB_CQE_RES_FORMAT_CSUM; 955 resp.response_length += sizeof(resp.cqe_comp_caps); 956 } 957 958 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen) && 959 raw_support) { 960 if (MLX5_CAP_QOS(mdev, packet_pacing) && 961 MLX5_CAP_GEN(mdev, qos)) { 962 resp.packet_pacing_caps.qp_rate_limit_max = 963 MLX5_CAP_QOS(mdev, packet_pacing_max_rate); 964 resp.packet_pacing_caps.qp_rate_limit_min = 965 MLX5_CAP_QOS(mdev, packet_pacing_min_rate); 966 resp.packet_pacing_caps.supported_qpts |= 967 1 << IB_QPT_RAW_PACKET; 968 } 969 resp.response_length += sizeof(resp.packet_pacing_caps); 970 } 971 972 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes, 973 uhw->outlen)) { 974 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe)) 975 resp.mlx5_ib_support_multi_pkt_send_wqes = 976 MLX5_IB_ALLOW_MPW; 977 978 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe)) 979 resp.mlx5_ib_support_multi_pkt_send_wqes |= 980 MLX5_IB_SUPPORT_EMPW; 981 982 resp.response_length += 983 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes); 984 } 985 986 if (field_avail(typeof(resp), flags, uhw->outlen)) { 987 resp.response_length += sizeof(resp.flags); 988 989 if (MLX5_CAP_GEN(mdev, cqe_compression_128)) 990 resp.flags |= 991 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP; 992 993 if (MLX5_CAP_GEN(mdev, cqe_128_always)) 994 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD; 995 } 996 997 if (field_avail(typeof(resp), sw_parsing_caps, 998 uhw->outlen)) { 999 resp.response_length += sizeof(resp.sw_parsing_caps); 1000 if (MLX5_CAP_ETH(mdev, swp)) { 1001 resp.sw_parsing_caps.sw_parsing_offloads |= 1002 MLX5_IB_SW_PARSING; 1003 1004 if (MLX5_CAP_ETH(mdev, swp_csum)) 1005 resp.sw_parsing_caps.sw_parsing_offloads |= 1006 MLX5_IB_SW_PARSING_CSUM; 1007 1008 if (MLX5_CAP_ETH(mdev, swp_lso)) 1009 resp.sw_parsing_caps.sw_parsing_offloads |= 1010 MLX5_IB_SW_PARSING_LSO; 1011 1012 if (resp.sw_parsing_caps.sw_parsing_offloads) 1013 resp.sw_parsing_caps.supported_qpts = 1014 BIT(IB_QPT_RAW_PACKET); 1015 } 1016 } 1017 1018 if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen) && 1019 raw_support) { 1020 resp.response_length += sizeof(resp.striding_rq_caps); 1021 if (MLX5_CAP_GEN(mdev, striding_rq)) { 1022 resp.striding_rq_caps.min_single_stride_log_num_of_bytes = 1023 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES; 1024 resp.striding_rq_caps.max_single_stride_log_num_of_bytes = 1025 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES; 1026 resp.striding_rq_caps.min_single_wqe_log_num_of_strides = 1027 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1028 resp.striding_rq_caps.max_single_wqe_log_num_of_strides = 1029 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES; 1030 resp.striding_rq_caps.supported_qpts = 1031 BIT(IB_QPT_RAW_PACKET); 1032 } 1033 } 1034 1035 if (field_avail(typeof(resp), tunnel_offloads_caps, 1036 uhw->outlen)) { 1037 resp.response_length += sizeof(resp.tunnel_offloads_caps); 1038 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan)) 1039 resp.tunnel_offloads_caps |= 1040 MLX5_IB_TUNNELED_OFFLOADS_VXLAN; 1041 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx)) 1042 resp.tunnel_offloads_caps |= 1043 MLX5_IB_TUNNELED_OFFLOADS_GENEVE; 1044 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) 1045 resp.tunnel_offloads_caps |= 1046 MLX5_IB_TUNNELED_OFFLOADS_GRE; 1047 } 1048 1049 if (uhw->outlen) { 1050 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 1051 1052 if (err) 1053 return err; 1054 } 1055 1056 return 0; 1057 } 1058 1059 enum mlx5_ib_width { 1060 MLX5_IB_WIDTH_1X = 1 << 0, 1061 MLX5_IB_WIDTH_2X = 1 << 1, 1062 MLX5_IB_WIDTH_4X = 1 << 2, 1063 MLX5_IB_WIDTH_8X = 1 << 3, 1064 MLX5_IB_WIDTH_12X = 1 << 4 1065 }; 1066 1067 static int translate_active_width(struct ib_device *ibdev, u8 active_width, 1068 u8 *ib_width) 1069 { 1070 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1071 int err = 0; 1072 1073 if (active_width & MLX5_IB_WIDTH_1X) { 1074 *ib_width = IB_WIDTH_1X; 1075 } else if (active_width & MLX5_IB_WIDTH_2X) { 1076 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n", 1077 (int)active_width); 1078 err = -EINVAL; 1079 } else if (active_width & MLX5_IB_WIDTH_4X) { 1080 *ib_width = IB_WIDTH_4X; 1081 } else if (active_width & MLX5_IB_WIDTH_8X) { 1082 *ib_width = IB_WIDTH_8X; 1083 } else if (active_width & MLX5_IB_WIDTH_12X) { 1084 *ib_width = IB_WIDTH_12X; 1085 } else { 1086 mlx5_ib_dbg(dev, "Invalid active_width %d\n", 1087 (int)active_width); 1088 err = -EINVAL; 1089 } 1090 1091 return err; 1092 } 1093 1094 static int mlx5_mtu_to_ib_mtu(int mtu) 1095 { 1096 switch (mtu) { 1097 case 256: return 1; 1098 case 512: return 2; 1099 case 1024: return 3; 1100 case 2048: return 4; 1101 case 4096: return 5; 1102 default: 1103 pr_warn("invalid mtu\n"); 1104 return -1; 1105 } 1106 } 1107 1108 enum ib_max_vl_num { 1109 __IB_MAX_VL_0 = 1, 1110 __IB_MAX_VL_0_1 = 2, 1111 __IB_MAX_VL_0_3 = 3, 1112 __IB_MAX_VL_0_7 = 4, 1113 __IB_MAX_VL_0_14 = 5, 1114 }; 1115 1116 enum mlx5_vl_hw_cap { 1117 MLX5_VL_HW_0 = 1, 1118 MLX5_VL_HW_0_1 = 2, 1119 MLX5_VL_HW_0_2 = 3, 1120 MLX5_VL_HW_0_3 = 4, 1121 MLX5_VL_HW_0_4 = 5, 1122 MLX5_VL_HW_0_5 = 6, 1123 MLX5_VL_HW_0_6 = 7, 1124 MLX5_VL_HW_0_7 = 8, 1125 MLX5_VL_HW_0_14 = 15 1126 }; 1127 1128 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 1129 u8 *max_vl_num) 1130 { 1131 switch (vl_hw_cap) { 1132 case MLX5_VL_HW_0: 1133 *max_vl_num = __IB_MAX_VL_0; 1134 break; 1135 case MLX5_VL_HW_0_1: 1136 *max_vl_num = __IB_MAX_VL_0_1; 1137 break; 1138 case MLX5_VL_HW_0_3: 1139 *max_vl_num = __IB_MAX_VL_0_3; 1140 break; 1141 case MLX5_VL_HW_0_7: 1142 *max_vl_num = __IB_MAX_VL_0_7; 1143 break; 1144 case MLX5_VL_HW_0_14: 1145 *max_vl_num = __IB_MAX_VL_0_14; 1146 break; 1147 1148 default: 1149 return -EINVAL; 1150 } 1151 1152 return 0; 1153 } 1154 1155 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port, 1156 struct ib_port_attr *props) 1157 { 1158 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1159 struct mlx5_core_dev *mdev = dev->mdev; 1160 struct mlx5_hca_vport_context *rep; 1161 u16 max_mtu; 1162 u16 oper_mtu; 1163 int err; 1164 u8 ib_link_width_oper; 1165 u8 vl_hw_cap; 1166 1167 rep = kzalloc(sizeof(*rep), GFP_KERNEL); 1168 if (!rep) { 1169 err = -ENOMEM; 1170 goto out; 1171 } 1172 1173 /* props being zeroed by the caller, avoid zeroing it here */ 1174 1175 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); 1176 if (err) 1177 goto out; 1178 1179 props->lid = rep->lid; 1180 props->lmc = rep->lmc; 1181 props->sm_lid = rep->sm_lid; 1182 props->sm_sl = rep->sm_sl; 1183 props->state = rep->vport_state; 1184 props->phys_state = rep->port_physical_state; 1185 props->port_cap_flags = rep->cap_mask1; 1186 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 1187 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 1188 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 1189 props->bad_pkey_cntr = rep->pkey_violation_counter; 1190 props->qkey_viol_cntr = rep->qkey_violation_counter; 1191 props->subnet_timeout = rep->subnet_timeout; 1192 props->init_type_reply = rep->init_type_reply; 1193 props->grh_required = rep->grh_required; 1194 1195 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port); 1196 if (err) 1197 goto out; 1198 1199 err = translate_active_width(ibdev, ib_link_width_oper, 1200 &props->active_width); 1201 if (err) 1202 goto out; 1203 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port); 1204 if (err) 1205 goto out; 1206 1207 mlx5_query_port_max_mtu(mdev, &max_mtu, port); 1208 1209 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); 1210 1211 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); 1212 1213 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); 1214 1215 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); 1216 if (err) 1217 goto out; 1218 1219 err = translate_max_vl_num(ibdev, vl_hw_cap, 1220 &props->max_vl_num); 1221 out: 1222 kfree(rep); 1223 return err; 1224 } 1225 1226 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 1227 struct ib_port_attr *props) 1228 { 1229 unsigned int count; 1230 int ret; 1231 1232 switch (mlx5_get_vport_access_method(ibdev)) { 1233 case MLX5_VPORT_ACCESS_METHOD_MAD: 1234 ret = mlx5_query_mad_ifc_port(ibdev, port, props); 1235 break; 1236 1237 case MLX5_VPORT_ACCESS_METHOD_HCA: 1238 ret = mlx5_query_hca_port(ibdev, port, props); 1239 break; 1240 1241 case MLX5_VPORT_ACCESS_METHOD_NIC: 1242 ret = mlx5_query_port_roce(ibdev, port, props); 1243 break; 1244 1245 default: 1246 ret = -EINVAL; 1247 } 1248 1249 if (!ret && props) { 1250 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1251 struct mlx5_core_dev *mdev; 1252 bool put_mdev = true; 1253 1254 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL); 1255 if (!mdev) { 1256 /* If the port isn't affiliated yet query the master. 1257 * The master and slave will have the same values. 1258 */ 1259 mdev = dev->mdev; 1260 port = 1; 1261 put_mdev = false; 1262 } 1263 count = mlx5_core_reserved_gids_count(mdev); 1264 if (put_mdev) 1265 mlx5_ib_put_native_port_mdev(dev, port); 1266 props->gid_tbl_len -= count; 1267 } 1268 return ret; 1269 } 1270 1271 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 1272 union ib_gid *gid) 1273 { 1274 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1275 struct mlx5_core_dev *mdev = dev->mdev; 1276 1277 switch (mlx5_get_vport_access_method(ibdev)) { 1278 case MLX5_VPORT_ACCESS_METHOD_MAD: 1279 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 1280 1281 case MLX5_VPORT_ACCESS_METHOD_HCA: 1282 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); 1283 1284 default: 1285 return -EINVAL; 1286 } 1287 1288 } 1289 1290 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port, 1291 u16 index, u16 *pkey) 1292 { 1293 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1294 struct mlx5_core_dev *mdev; 1295 bool put_mdev = true; 1296 u8 mdev_port_num; 1297 int err; 1298 1299 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num); 1300 if (!mdev) { 1301 /* The port isn't affiliated yet, get the PKey from the master 1302 * port. For RoCE the PKey tables will be the same. 1303 */ 1304 put_mdev = false; 1305 mdev = dev->mdev; 1306 mdev_port_num = 1; 1307 } 1308 1309 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0, 1310 index, pkey); 1311 if (put_mdev) 1312 mlx5_ib_put_native_port_mdev(dev, port); 1313 1314 return err; 1315 } 1316 1317 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 1318 u16 *pkey) 1319 { 1320 switch (mlx5_get_vport_access_method(ibdev)) { 1321 case MLX5_VPORT_ACCESS_METHOD_MAD: 1322 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 1323 1324 case MLX5_VPORT_ACCESS_METHOD_HCA: 1325 case MLX5_VPORT_ACCESS_METHOD_NIC: 1326 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey); 1327 default: 1328 return -EINVAL; 1329 } 1330 } 1331 1332 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 1333 struct ib_device_modify *props) 1334 { 1335 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1336 struct mlx5_reg_node_desc in; 1337 struct mlx5_reg_node_desc out; 1338 int err; 1339 1340 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 1341 return -EOPNOTSUPP; 1342 1343 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 1344 return 0; 1345 1346 /* 1347 * If possible, pass node desc to FW, so it can generate 1348 * a 144 trap. If cmd fails, just ignore. 1349 */ 1350 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1351 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 1352 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 1353 if (err) 1354 return err; 1355 1356 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1357 1358 return err; 1359 } 1360 1361 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask, 1362 u32 value) 1363 { 1364 struct mlx5_hca_vport_context ctx = {}; 1365 struct mlx5_core_dev *mdev; 1366 u8 mdev_port_num; 1367 int err; 1368 1369 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 1370 if (!mdev) 1371 return -ENODEV; 1372 1373 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx); 1374 if (err) 1375 goto out; 1376 1377 if (~ctx.cap_mask1_perm & mask) { 1378 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n", 1379 mask, ctx.cap_mask1_perm); 1380 err = -EINVAL; 1381 goto out; 1382 } 1383 1384 ctx.cap_mask1 = value; 1385 ctx.cap_mask1_perm = mask; 1386 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num, 1387 0, &ctx); 1388 1389 out: 1390 mlx5_ib_put_native_port_mdev(dev, port_num); 1391 1392 return err; 1393 } 1394 1395 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, 1396 struct ib_port_modify *props) 1397 { 1398 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1399 struct ib_port_attr attr; 1400 u32 tmp; 1401 int err; 1402 u32 change_mask; 1403 u32 value; 1404 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) == 1405 IB_LINK_LAYER_INFINIBAND); 1406 1407 /* CM layer calls ib_modify_port() regardless of the link layer. For 1408 * Ethernet ports, qkey violation and Port capabilities are meaningless. 1409 */ 1410 if (!is_ib) 1411 return 0; 1412 1413 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) { 1414 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask; 1415 value = ~props->clr_port_cap_mask | props->set_port_cap_mask; 1416 return set_port_caps_atomic(dev, port, change_mask, value); 1417 } 1418 1419 mutex_lock(&dev->cap_mask_mutex); 1420 1421 err = ib_query_port(ibdev, port, &attr); 1422 if (err) 1423 goto out; 1424 1425 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 1426 ~props->clr_port_cap_mask; 1427 1428 err = mlx5_set_port_caps(dev->mdev, port, tmp); 1429 1430 out: 1431 mutex_unlock(&dev->cap_mask_mutex); 1432 return err; 1433 } 1434 1435 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps) 1436 { 1437 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n", 1438 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n"); 1439 } 1440 1441 static u16 calc_dynamic_bfregs(int uars_per_sys_page) 1442 { 1443 /* Large page with non 4k uar support might limit the dynamic size */ 1444 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096) 1445 return MLX5_MIN_DYN_BFREGS; 1446 1447 return MLX5_MAX_DYN_BFREGS; 1448 } 1449 1450 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k, 1451 struct mlx5_ib_alloc_ucontext_req_v2 *req, 1452 struct mlx5_bfreg_info *bfregi) 1453 { 1454 int uars_per_sys_page; 1455 int bfregs_per_sys_page; 1456 int ref_bfregs = req->total_num_bfregs; 1457 1458 if (req->total_num_bfregs == 0) 1459 return -EINVAL; 1460 1461 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE); 1462 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE); 1463 1464 if (req->total_num_bfregs > MLX5_MAX_BFREGS) 1465 return -ENOMEM; 1466 1467 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k); 1468 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR; 1469 /* This holds the required static allocation asked by the user */ 1470 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page); 1471 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1) 1472 return -EINVAL; 1473 1474 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page; 1475 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page); 1476 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs; 1477 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page; 1478 1479 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n", 1480 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no", 1481 lib_uar_4k ? "yes" : "no", ref_bfregs, 1482 req->total_num_bfregs, bfregi->total_num_bfregs, 1483 bfregi->num_sys_pages); 1484 1485 return 0; 1486 } 1487 1488 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1489 { 1490 struct mlx5_bfreg_info *bfregi; 1491 int err; 1492 int i; 1493 1494 bfregi = &context->bfregi; 1495 for (i = 0; i < bfregi->num_static_sys_pages; i++) { 1496 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]); 1497 if (err) 1498 goto error; 1499 1500 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]); 1501 } 1502 1503 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++) 1504 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX; 1505 1506 return 0; 1507 1508 error: 1509 for (--i; i >= 0; i--) 1510 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i])) 1511 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1512 1513 return err; 1514 } 1515 1516 static int deallocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1517 { 1518 struct mlx5_bfreg_info *bfregi; 1519 int err; 1520 int i; 1521 1522 bfregi = &context->bfregi; 1523 for (i = 0; i < bfregi->num_sys_pages; i++) { 1524 if (i < bfregi->num_static_sys_pages || 1525 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) { 1526 err = mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]); 1527 if (err) { 1528 mlx5_ib_warn(dev, "failed to free uar %d, err=%d\n", i, err); 1529 return err; 1530 } 1531 } 1532 } 1533 1534 return 0; 1535 } 1536 1537 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn) 1538 { 1539 int err; 1540 1541 err = mlx5_core_alloc_transport_domain(dev->mdev, tdn); 1542 if (err) 1543 return err; 1544 1545 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1546 !MLX5_CAP_GEN(dev->mdev, disable_local_lb)) 1547 return err; 1548 1549 mutex_lock(&dev->lb_mutex); 1550 dev->user_td++; 1551 1552 if (dev->user_td == 2) 1553 err = mlx5_nic_vport_update_local_lb(dev->mdev, true); 1554 1555 mutex_unlock(&dev->lb_mutex); 1556 return err; 1557 } 1558 1559 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn) 1560 { 1561 mlx5_core_dealloc_transport_domain(dev->mdev, tdn); 1562 1563 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1564 !MLX5_CAP_GEN(dev->mdev, disable_local_lb)) 1565 return; 1566 1567 mutex_lock(&dev->lb_mutex); 1568 dev->user_td--; 1569 1570 if (dev->user_td < 2) 1571 mlx5_nic_vport_update_local_lb(dev->mdev, false); 1572 1573 mutex_unlock(&dev->lb_mutex); 1574 } 1575 1576 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev, 1577 struct ib_udata *udata) 1578 { 1579 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1580 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 1581 struct mlx5_ib_alloc_ucontext_resp resp = {}; 1582 struct mlx5_core_dev *mdev = dev->mdev; 1583 struct mlx5_ib_ucontext *context; 1584 struct mlx5_bfreg_info *bfregi; 1585 int ver; 1586 int err; 1587 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 1588 max_cqe_version); 1589 bool lib_uar_4k; 1590 1591 if (!dev->ib_active) 1592 return ERR_PTR(-EAGAIN); 1593 1594 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 1595 ver = 0; 1596 else if (udata->inlen >= min_req_v2) 1597 ver = 2; 1598 else 1599 return ERR_PTR(-EINVAL); 1600 1601 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req))); 1602 if (err) 1603 return ERR_PTR(err); 1604 1605 if (req.flags) 1606 return ERR_PTR(-EINVAL); 1607 1608 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 1609 return ERR_PTR(-EOPNOTSUPP); 1610 1611 req.total_num_bfregs = ALIGN(req.total_num_bfregs, 1612 MLX5_NON_FP_BFREGS_PER_UAR); 1613 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1) 1614 return ERR_PTR(-EINVAL); 1615 1616 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 1617 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf)) 1618 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size); 1619 resp.cache_line_size = cache_line_size(); 1620 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 1621 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 1622 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1623 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1624 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 1625 resp.cqe_version = min_t(__u8, 1626 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 1627 req.max_cqe_version); 1628 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1629 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT; 1630 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1631 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1; 1632 resp.response_length = min(offsetof(typeof(resp), response_length) + 1633 sizeof(resp.response_length), udata->outlen); 1634 1635 context = kzalloc(sizeof(*context), GFP_KERNEL); 1636 if (!context) 1637 return ERR_PTR(-ENOMEM); 1638 1639 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR; 1640 bfregi = &context->bfregi; 1641 1642 /* updates req->total_num_bfregs */ 1643 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi); 1644 if (err) 1645 goto out_ctx; 1646 1647 mutex_init(&bfregi->lock); 1648 bfregi->lib_uar_4k = lib_uar_4k; 1649 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count), 1650 GFP_KERNEL); 1651 if (!bfregi->count) { 1652 err = -ENOMEM; 1653 goto out_ctx; 1654 } 1655 1656 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages, 1657 sizeof(*bfregi->sys_pages), 1658 GFP_KERNEL); 1659 if (!bfregi->sys_pages) { 1660 err = -ENOMEM; 1661 goto out_count; 1662 } 1663 1664 err = allocate_uars(dev, context); 1665 if (err) 1666 goto out_sys_pages; 1667 1668 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1669 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range; 1670 #endif 1671 1672 context->upd_xlt_page = __get_free_page(GFP_KERNEL); 1673 if (!context->upd_xlt_page) { 1674 err = -ENOMEM; 1675 goto out_uars; 1676 } 1677 mutex_init(&context->upd_xlt_page_mutex); 1678 1679 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) { 1680 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn); 1681 if (err) 1682 goto out_page; 1683 } 1684 1685 INIT_LIST_HEAD(&context->vma_private_list); 1686 mutex_init(&context->vma_private_list_mutex); 1687 INIT_LIST_HEAD(&context->db_page_list); 1688 mutex_init(&context->db_page_mutex); 1689 1690 resp.tot_bfregs = req.total_num_bfregs; 1691 resp.num_ports = dev->num_ports; 1692 1693 if (field_avail(typeof(resp), cqe_version, udata->outlen)) 1694 resp.response_length += sizeof(resp.cqe_version); 1695 1696 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) { 1697 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 1698 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 1699 resp.response_length += sizeof(resp.cmds_supp_uhw); 1700 } 1701 1702 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) { 1703 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) { 1704 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline); 1705 resp.eth_min_inline++; 1706 } 1707 resp.response_length += sizeof(resp.eth_min_inline); 1708 } 1709 1710 if (field_avail(typeof(resp), clock_info_versions, udata->outlen)) { 1711 if (mdev->clock_info) 1712 resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1); 1713 resp.response_length += sizeof(resp.clock_info_versions); 1714 } 1715 1716 /* 1717 * We don't want to expose information from the PCI bar that is located 1718 * after 4096 bytes, so if the arch only supports larger pages, let's 1719 * pretend we don't support reading the HCA's core clock. This is also 1720 * forced by mmap function. 1721 */ 1722 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) { 1723 if (PAGE_SIZE <= 4096) { 1724 resp.comp_mask |= 1725 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 1726 resp.hca_core_clock_offset = 1727 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE; 1728 } 1729 resp.response_length += sizeof(resp.hca_core_clock_offset); 1730 } 1731 1732 if (field_avail(typeof(resp), log_uar_size, udata->outlen)) 1733 resp.response_length += sizeof(resp.log_uar_size); 1734 1735 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen)) 1736 resp.response_length += sizeof(resp.num_uars_per_page); 1737 1738 if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) { 1739 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs; 1740 resp.response_length += sizeof(resp.num_dyn_bfregs); 1741 } 1742 1743 err = ib_copy_to_udata(udata, &resp, resp.response_length); 1744 if (err) 1745 goto out_td; 1746 1747 bfregi->ver = ver; 1748 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs; 1749 context->cqe_version = resp.cqe_version; 1750 context->lib_caps = req.lib_caps; 1751 print_lib_caps(dev, context->lib_caps); 1752 1753 return &context->ibucontext; 1754 1755 out_td: 1756 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1757 mlx5_ib_dealloc_transport_domain(dev, context->tdn); 1758 1759 out_page: 1760 free_page(context->upd_xlt_page); 1761 1762 out_uars: 1763 deallocate_uars(dev, context); 1764 1765 out_sys_pages: 1766 kfree(bfregi->sys_pages); 1767 1768 out_count: 1769 kfree(bfregi->count); 1770 1771 out_ctx: 1772 kfree(context); 1773 1774 return ERR_PTR(err); 1775 } 1776 1777 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1778 { 1779 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1780 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1781 struct mlx5_bfreg_info *bfregi; 1782 1783 bfregi = &context->bfregi; 1784 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1785 mlx5_ib_dealloc_transport_domain(dev, context->tdn); 1786 1787 free_page(context->upd_xlt_page); 1788 deallocate_uars(dev, context); 1789 kfree(bfregi->sys_pages); 1790 kfree(bfregi->count); 1791 kfree(context); 1792 1793 return 0; 1794 } 1795 1796 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, 1797 int uar_idx) 1798 { 1799 int fw_uars_per_page; 1800 1801 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1; 1802 1803 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + uar_idx / fw_uars_per_page; 1804 } 1805 1806 static int get_command(unsigned long offset) 1807 { 1808 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 1809 } 1810 1811 static int get_arg(unsigned long offset) 1812 { 1813 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 1814 } 1815 1816 static int get_index(unsigned long offset) 1817 { 1818 return get_arg(offset); 1819 } 1820 1821 /* Index resides in an extra byte to enable larger values than 255 */ 1822 static int get_extended_index(unsigned long offset) 1823 { 1824 return get_arg(offset) | ((offset >> 16) & 0xff) << 8; 1825 } 1826 1827 static void mlx5_ib_vma_open(struct vm_area_struct *area) 1828 { 1829 /* vma_open is called when a new VMA is created on top of our VMA. This 1830 * is done through either mremap flow or split_vma (usually due to 1831 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA, 1832 * as this VMA is strongly hardware related. Therefore we set the 1833 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from 1834 * calling us again and trying to do incorrect actions. We assume that 1835 * the original VMA size is exactly a single page, and therefore all 1836 * "splitting" operation will not happen to it. 1837 */ 1838 area->vm_ops = NULL; 1839 } 1840 1841 static void mlx5_ib_vma_close(struct vm_area_struct *area) 1842 { 1843 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data; 1844 1845 /* It's guaranteed that all VMAs opened on a FD are closed before the 1846 * file itself is closed, therefore no sync is needed with the regular 1847 * closing flow. (e.g. mlx5 ib_dealloc_ucontext) 1848 * However need a sync with accessing the vma as part of 1849 * mlx5_ib_disassociate_ucontext. 1850 * The close operation is usually called under mm->mmap_sem except when 1851 * process is exiting. 1852 * The exiting case is handled explicitly as part of 1853 * mlx5_ib_disassociate_ucontext. 1854 */ 1855 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data; 1856 1857 /* setting the vma context pointer to null in the mlx5_ib driver's 1858 * private data, to protect a race condition in 1859 * mlx5_ib_disassociate_ucontext(). 1860 */ 1861 mlx5_ib_vma_priv_data->vma = NULL; 1862 mutex_lock(mlx5_ib_vma_priv_data->vma_private_list_mutex); 1863 list_del(&mlx5_ib_vma_priv_data->list); 1864 mutex_unlock(mlx5_ib_vma_priv_data->vma_private_list_mutex); 1865 kfree(mlx5_ib_vma_priv_data); 1866 } 1867 1868 static const struct vm_operations_struct mlx5_ib_vm_ops = { 1869 .open = mlx5_ib_vma_open, 1870 .close = mlx5_ib_vma_close 1871 }; 1872 1873 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma, 1874 struct mlx5_ib_ucontext *ctx) 1875 { 1876 struct mlx5_ib_vma_private_data *vma_prv; 1877 struct list_head *vma_head = &ctx->vma_private_list; 1878 1879 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL); 1880 if (!vma_prv) 1881 return -ENOMEM; 1882 1883 vma_prv->vma = vma; 1884 vma_prv->vma_private_list_mutex = &ctx->vma_private_list_mutex; 1885 vma->vm_private_data = vma_prv; 1886 vma->vm_ops = &mlx5_ib_vm_ops; 1887 1888 mutex_lock(&ctx->vma_private_list_mutex); 1889 list_add(&vma_prv->list, vma_head); 1890 mutex_unlock(&ctx->vma_private_list_mutex); 1891 1892 return 0; 1893 } 1894 1895 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 1896 { 1897 int ret; 1898 struct vm_area_struct *vma; 1899 struct mlx5_ib_vma_private_data *vma_private, *n; 1900 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1901 struct task_struct *owning_process = NULL; 1902 struct mm_struct *owning_mm = NULL; 1903 1904 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID); 1905 if (!owning_process) 1906 return; 1907 1908 owning_mm = get_task_mm(owning_process); 1909 if (!owning_mm) { 1910 pr_info("no mm, disassociate ucontext is pending task termination\n"); 1911 while (1) { 1912 put_task_struct(owning_process); 1913 usleep_range(1000, 2000); 1914 owning_process = get_pid_task(ibcontext->tgid, 1915 PIDTYPE_PID); 1916 if (!owning_process || 1917 owning_process->state == TASK_DEAD) { 1918 pr_info("disassociate ucontext done, task was terminated\n"); 1919 /* in case task was dead need to release the 1920 * task struct. 1921 */ 1922 if (owning_process) 1923 put_task_struct(owning_process); 1924 return; 1925 } 1926 } 1927 } 1928 1929 /* need to protect from a race on closing the vma as part of 1930 * mlx5_ib_vma_close. 1931 */ 1932 down_write(&owning_mm->mmap_sem); 1933 mutex_lock(&context->vma_private_list_mutex); 1934 list_for_each_entry_safe(vma_private, n, &context->vma_private_list, 1935 list) { 1936 vma = vma_private->vma; 1937 ret = zap_vma_ptes(vma, vma->vm_start, 1938 PAGE_SIZE); 1939 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__); 1940 /* context going to be destroyed, should 1941 * not access ops any more. 1942 */ 1943 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE); 1944 vma->vm_ops = NULL; 1945 list_del(&vma_private->list); 1946 kfree(vma_private); 1947 } 1948 mutex_unlock(&context->vma_private_list_mutex); 1949 up_write(&owning_mm->mmap_sem); 1950 mmput(owning_mm); 1951 put_task_struct(owning_process); 1952 } 1953 1954 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 1955 { 1956 switch (cmd) { 1957 case MLX5_IB_MMAP_WC_PAGE: 1958 return "WC"; 1959 case MLX5_IB_MMAP_REGULAR_PAGE: 1960 return "best effort WC"; 1961 case MLX5_IB_MMAP_NC_PAGE: 1962 return "NC"; 1963 default: 1964 return NULL; 1965 } 1966 } 1967 1968 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev, 1969 struct vm_area_struct *vma, 1970 struct mlx5_ib_ucontext *context) 1971 { 1972 phys_addr_t pfn; 1973 int err; 1974 1975 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1976 return -EINVAL; 1977 1978 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1) 1979 return -EOPNOTSUPP; 1980 1981 if (vma->vm_flags & VM_WRITE) 1982 return -EPERM; 1983 1984 if (!dev->mdev->clock_info_page) 1985 return -EOPNOTSUPP; 1986 1987 pfn = page_to_pfn(dev->mdev->clock_info_page); 1988 err = remap_pfn_range(vma, vma->vm_start, pfn, PAGE_SIZE, 1989 vma->vm_page_prot); 1990 if (err) 1991 return err; 1992 1993 mlx5_ib_dbg(dev, "mapped clock info at 0x%lx, PA 0x%llx\n", 1994 vma->vm_start, 1995 (unsigned long long)pfn << PAGE_SHIFT); 1996 1997 return mlx5_ib_set_vma_data(vma, context); 1998 } 1999 2000 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 2001 struct vm_area_struct *vma, 2002 struct mlx5_ib_ucontext *context) 2003 { 2004 struct mlx5_bfreg_info *bfregi = &context->bfregi; 2005 int err; 2006 unsigned long idx; 2007 phys_addr_t pfn, pa; 2008 pgprot_t prot; 2009 u32 bfreg_dyn_idx = 0; 2010 u32 uar_index; 2011 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC); 2012 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages : 2013 bfregi->num_static_sys_pages; 2014 2015 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2016 return -EINVAL; 2017 2018 if (dyn_uar) 2019 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages; 2020 else 2021 idx = get_index(vma->vm_pgoff); 2022 2023 if (idx >= max_valid_idx) { 2024 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n", 2025 idx, max_valid_idx); 2026 return -EINVAL; 2027 } 2028 2029 switch (cmd) { 2030 case MLX5_IB_MMAP_WC_PAGE: 2031 case MLX5_IB_MMAP_ALLOC_WC: 2032 /* Some architectures don't support WC memory */ 2033 #if defined(CONFIG_X86) 2034 if (!pat_enabled()) 2035 return -EPERM; 2036 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU))) 2037 return -EPERM; 2038 #endif 2039 /* fall through */ 2040 case MLX5_IB_MMAP_REGULAR_PAGE: 2041 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 2042 prot = pgprot_writecombine(vma->vm_page_prot); 2043 break; 2044 case MLX5_IB_MMAP_NC_PAGE: 2045 prot = pgprot_noncached(vma->vm_page_prot); 2046 break; 2047 default: 2048 return -EINVAL; 2049 } 2050 2051 if (dyn_uar) { 2052 int uars_per_page; 2053 2054 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k); 2055 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR); 2056 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) { 2057 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n", 2058 bfreg_dyn_idx, bfregi->total_num_bfregs); 2059 return -EINVAL; 2060 } 2061 2062 mutex_lock(&bfregi->lock); 2063 /* Fail if uar already allocated, first bfreg index of each 2064 * page holds its count. 2065 */ 2066 if (bfregi->count[bfreg_dyn_idx]) { 2067 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx); 2068 mutex_unlock(&bfregi->lock); 2069 return -EINVAL; 2070 } 2071 2072 bfregi->count[bfreg_dyn_idx]++; 2073 mutex_unlock(&bfregi->lock); 2074 2075 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index); 2076 if (err) { 2077 mlx5_ib_warn(dev, "UAR alloc failed\n"); 2078 goto free_bfreg; 2079 } 2080 } else { 2081 uar_index = bfregi->sys_pages[idx]; 2082 } 2083 2084 pfn = uar_index2pfn(dev, uar_index); 2085 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 2086 2087 vma->vm_page_prot = prot; 2088 err = io_remap_pfn_range(vma, vma->vm_start, pfn, 2089 PAGE_SIZE, vma->vm_page_prot); 2090 if (err) { 2091 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n", 2092 err, vma->vm_start, &pfn, mmap_cmd2str(cmd)); 2093 err = -EAGAIN; 2094 goto err; 2095 } 2096 2097 pa = pfn << PAGE_SHIFT; 2098 mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd), 2099 vma->vm_start, &pa); 2100 2101 err = mlx5_ib_set_vma_data(vma, context); 2102 if (err) 2103 goto err; 2104 2105 if (dyn_uar) 2106 bfregi->sys_pages[idx] = uar_index; 2107 return 0; 2108 2109 err: 2110 if (!dyn_uar) 2111 return err; 2112 2113 mlx5_cmd_free_uar(dev->mdev, idx); 2114 2115 free_bfreg: 2116 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx); 2117 2118 return err; 2119 } 2120 2121 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 2122 { 2123 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2124 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2125 unsigned long command; 2126 phys_addr_t pfn; 2127 2128 command = get_command(vma->vm_pgoff); 2129 switch (command) { 2130 case MLX5_IB_MMAP_WC_PAGE: 2131 case MLX5_IB_MMAP_NC_PAGE: 2132 case MLX5_IB_MMAP_REGULAR_PAGE: 2133 case MLX5_IB_MMAP_ALLOC_WC: 2134 return uar_mmap(dev, command, vma, context); 2135 2136 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 2137 return -ENOSYS; 2138 2139 case MLX5_IB_MMAP_CORE_CLOCK: 2140 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2141 return -EINVAL; 2142 2143 if (vma->vm_flags & VM_WRITE) 2144 return -EPERM; 2145 2146 /* Don't expose to user-space information it shouldn't have */ 2147 if (PAGE_SIZE > 4096) 2148 return -EOPNOTSUPP; 2149 2150 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 2151 pfn = (dev->mdev->iseg_base + 2152 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 2153 PAGE_SHIFT; 2154 if (io_remap_pfn_range(vma, vma->vm_start, pfn, 2155 PAGE_SIZE, vma->vm_page_prot)) 2156 return -EAGAIN; 2157 2158 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n", 2159 vma->vm_start, 2160 (unsigned long long)pfn << PAGE_SHIFT); 2161 break; 2162 case MLX5_IB_MMAP_CLOCK_INFO: 2163 return mlx5_ib_mmap_clock_info_page(dev, vma, context); 2164 2165 default: 2166 return -EINVAL; 2167 } 2168 2169 return 0; 2170 } 2171 2172 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev, 2173 struct ib_ucontext *context, 2174 struct ib_udata *udata) 2175 { 2176 struct mlx5_ib_alloc_pd_resp resp; 2177 struct mlx5_ib_pd *pd; 2178 int err; 2179 2180 pd = kmalloc(sizeof(*pd), GFP_KERNEL); 2181 if (!pd) 2182 return ERR_PTR(-ENOMEM); 2183 2184 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn); 2185 if (err) { 2186 kfree(pd); 2187 return ERR_PTR(err); 2188 } 2189 2190 if (context) { 2191 resp.pdn = pd->pdn; 2192 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 2193 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn); 2194 kfree(pd); 2195 return ERR_PTR(-EFAULT); 2196 } 2197 } 2198 2199 return &pd->ibpd; 2200 } 2201 2202 static int mlx5_ib_dealloc_pd(struct ib_pd *pd) 2203 { 2204 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 2205 struct mlx5_ib_pd *mpd = to_mpd(pd); 2206 2207 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn); 2208 kfree(mpd); 2209 2210 return 0; 2211 } 2212 2213 enum { 2214 MATCH_CRITERIA_ENABLE_OUTER_BIT, 2215 MATCH_CRITERIA_ENABLE_MISC_BIT, 2216 MATCH_CRITERIA_ENABLE_INNER_BIT 2217 }; 2218 2219 #define HEADER_IS_ZERO(match_criteria, headers) \ 2220 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \ 2221 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \ 2222 2223 static u8 get_match_criteria_enable(u32 *match_criteria) 2224 { 2225 u8 match_criteria_enable; 2226 2227 match_criteria_enable = 2228 (!HEADER_IS_ZERO(match_criteria, outer_headers)) << 2229 MATCH_CRITERIA_ENABLE_OUTER_BIT; 2230 match_criteria_enable |= 2231 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) << 2232 MATCH_CRITERIA_ENABLE_MISC_BIT; 2233 match_criteria_enable |= 2234 (!HEADER_IS_ZERO(match_criteria, inner_headers)) << 2235 MATCH_CRITERIA_ENABLE_INNER_BIT; 2236 2237 return match_criteria_enable; 2238 } 2239 2240 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val) 2241 { 2242 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask); 2243 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val); 2244 } 2245 2246 static void set_flow_label(void *misc_c, void *misc_v, u8 mask, u8 val, 2247 bool inner) 2248 { 2249 if (inner) { 2250 MLX5_SET(fte_match_set_misc, 2251 misc_c, inner_ipv6_flow_label, mask); 2252 MLX5_SET(fte_match_set_misc, 2253 misc_v, inner_ipv6_flow_label, val); 2254 } else { 2255 MLX5_SET(fte_match_set_misc, 2256 misc_c, outer_ipv6_flow_label, mask); 2257 MLX5_SET(fte_match_set_misc, 2258 misc_v, outer_ipv6_flow_label, val); 2259 } 2260 } 2261 2262 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val) 2263 { 2264 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask); 2265 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val); 2266 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2); 2267 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2); 2268 } 2269 2270 #define LAST_ETH_FIELD vlan_tag 2271 #define LAST_IB_FIELD sl 2272 #define LAST_IPV4_FIELD tos 2273 #define LAST_IPV6_FIELD traffic_class 2274 #define LAST_TCP_UDP_FIELD src_port 2275 #define LAST_TUNNEL_FIELD tunnel_id 2276 #define LAST_FLOW_TAG_FIELD tag_id 2277 #define LAST_DROP_FIELD size 2278 2279 /* Field is the last supported field */ 2280 #define FIELDS_NOT_SUPPORTED(filter, field)\ 2281 memchr_inv((void *)&filter.field +\ 2282 sizeof(filter.field), 0,\ 2283 sizeof(filter) -\ 2284 offsetof(typeof(filter), field) -\ 2285 sizeof(filter.field)) 2286 2287 #define IPV4_VERSION 4 2288 #define IPV6_VERSION 6 2289 static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c, 2290 u32 *match_v, const union ib_flow_spec *ib_spec, 2291 u32 *tag_id, bool *is_drop) 2292 { 2293 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c, 2294 misc_parameters); 2295 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v, 2296 misc_parameters); 2297 void *headers_c; 2298 void *headers_v; 2299 int match_ipv; 2300 2301 if (ib_spec->type & IB_FLOW_SPEC_INNER) { 2302 headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 2303 inner_headers); 2304 headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 2305 inner_headers); 2306 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2307 ft_field_support.inner_ip_version); 2308 } else { 2309 headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 2310 outer_headers); 2311 headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 2312 outer_headers); 2313 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2314 ft_field_support.outer_ip_version); 2315 } 2316 2317 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) { 2318 case IB_FLOW_SPEC_ETH: 2319 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD)) 2320 return -EOPNOTSUPP; 2321 2322 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2323 dmac_47_16), 2324 ib_spec->eth.mask.dst_mac); 2325 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2326 dmac_47_16), 2327 ib_spec->eth.val.dst_mac); 2328 2329 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2330 smac_47_16), 2331 ib_spec->eth.mask.src_mac); 2332 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2333 smac_47_16), 2334 ib_spec->eth.val.src_mac); 2335 2336 if (ib_spec->eth.mask.vlan_tag) { 2337 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2338 cvlan_tag, 1); 2339 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2340 cvlan_tag, 1); 2341 2342 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2343 first_vid, ntohs(ib_spec->eth.mask.vlan_tag)); 2344 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2345 first_vid, ntohs(ib_spec->eth.val.vlan_tag)); 2346 2347 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2348 first_cfi, 2349 ntohs(ib_spec->eth.mask.vlan_tag) >> 12); 2350 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2351 first_cfi, 2352 ntohs(ib_spec->eth.val.vlan_tag) >> 12); 2353 2354 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2355 first_prio, 2356 ntohs(ib_spec->eth.mask.vlan_tag) >> 13); 2357 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2358 first_prio, 2359 ntohs(ib_spec->eth.val.vlan_tag) >> 13); 2360 } 2361 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2362 ethertype, ntohs(ib_spec->eth.mask.ether_type)); 2363 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2364 ethertype, ntohs(ib_spec->eth.val.ether_type)); 2365 break; 2366 case IB_FLOW_SPEC_IPV4: 2367 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD)) 2368 return -EOPNOTSUPP; 2369 2370 if (match_ipv) { 2371 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2372 ip_version, 0xf); 2373 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2374 ip_version, IPV4_VERSION); 2375 } else { 2376 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2377 ethertype, 0xffff); 2378 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2379 ethertype, ETH_P_IP); 2380 } 2381 2382 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2383 src_ipv4_src_ipv6.ipv4_layout.ipv4), 2384 &ib_spec->ipv4.mask.src_ip, 2385 sizeof(ib_spec->ipv4.mask.src_ip)); 2386 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2387 src_ipv4_src_ipv6.ipv4_layout.ipv4), 2388 &ib_spec->ipv4.val.src_ip, 2389 sizeof(ib_spec->ipv4.val.src_ip)); 2390 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2391 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 2392 &ib_spec->ipv4.mask.dst_ip, 2393 sizeof(ib_spec->ipv4.mask.dst_ip)); 2394 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2395 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 2396 &ib_spec->ipv4.val.dst_ip, 2397 sizeof(ib_spec->ipv4.val.dst_ip)); 2398 2399 set_tos(headers_c, headers_v, 2400 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos); 2401 2402 set_proto(headers_c, headers_v, 2403 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto); 2404 break; 2405 case IB_FLOW_SPEC_IPV6: 2406 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD)) 2407 return -EOPNOTSUPP; 2408 2409 if (match_ipv) { 2410 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2411 ip_version, 0xf); 2412 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2413 ip_version, IPV6_VERSION); 2414 } else { 2415 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2416 ethertype, 0xffff); 2417 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2418 ethertype, ETH_P_IPV6); 2419 } 2420 2421 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2422 src_ipv4_src_ipv6.ipv6_layout.ipv6), 2423 &ib_spec->ipv6.mask.src_ip, 2424 sizeof(ib_spec->ipv6.mask.src_ip)); 2425 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2426 src_ipv4_src_ipv6.ipv6_layout.ipv6), 2427 &ib_spec->ipv6.val.src_ip, 2428 sizeof(ib_spec->ipv6.val.src_ip)); 2429 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2430 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 2431 &ib_spec->ipv6.mask.dst_ip, 2432 sizeof(ib_spec->ipv6.mask.dst_ip)); 2433 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2434 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 2435 &ib_spec->ipv6.val.dst_ip, 2436 sizeof(ib_spec->ipv6.val.dst_ip)); 2437 2438 set_tos(headers_c, headers_v, 2439 ib_spec->ipv6.mask.traffic_class, 2440 ib_spec->ipv6.val.traffic_class); 2441 2442 set_proto(headers_c, headers_v, 2443 ib_spec->ipv6.mask.next_hdr, 2444 ib_spec->ipv6.val.next_hdr); 2445 2446 set_flow_label(misc_params_c, misc_params_v, 2447 ntohl(ib_spec->ipv6.mask.flow_label), 2448 ntohl(ib_spec->ipv6.val.flow_label), 2449 ib_spec->type & IB_FLOW_SPEC_INNER); 2450 2451 break; 2452 case IB_FLOW_SPEC_TCP: 2453 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 2454 LAST_TCP_UDP_FIELD)) 2455 return -EOPNOTSUPP; 2456 2457 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol, 2458 0xff); 2459 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, 2460 IPPROTO_TCP); 2461 2462 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport, 2463 ntohs(ib_spec->tcp_udp.mask.src_port)); 2464 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport, 2465 ntohs(ib_spec->tcp_udp.val.src_port)); 2466 2467 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport, 2468 ntohs(ib_spec->tcp_udp.mask.dst_port)); 2469 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport, 2470 ntohs(ib_spec->tcp_udp.val.dst_port)); 2471 break; 2472 case IB_FLOW_SPEC_UDP: 2473 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 2474 LAST_TCP_UDP_FIELD)) 2475 return -EOPNOTSUPP; 2476 2477 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol, 2478 0xff); 2479 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, 2480 IPPROTO_UDP); 2481 2482 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport, 2483 ntohs(ib_spec->tcp_udp.mask.src_port)); 2484 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport, 2485 ntohs(ib_spec->tcp_udp.val.src_port)); 2486 2487 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport, 2488 ntohs(ib_spec->tcp_udp.mask.dst_port)); 2489 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, 2490 ntohs(ib_spec->tcp_udp.val.dst_port)); 2491 break; 2492 case IB_FLOW_SPEC_VXLAN_TUNNEL: 2493 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask, 2494 LAST_TUNNEL_FIELD)) 2495 return -EOPNOTSUPP; 2496 2497 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni, 2498 ntohl(ib_spec->tunnel.mask.tunnel_id)); 2499 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni, 2500 ntohl(ib_spec->tunnel.val.tunnel_id)); 2501 break; 2502 case IB_FLOW_SPEC_ACTION_TAG: 2503 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag, 2504 LAST_FLOW_TAG_FIELD)) 2505 return -EOPNOTSUPP; 2506 if (ib_spec->flow_tag.tag_id >= BIT(24)) 2507 return -EINVAL; 2508 2509 *tag_id = ib_spec->flow_tag.tag_id; 2510 break; 2511 case IB_FLOW_SPEC_ACTION_DROP: 2512 if (FIELDS_NOT_SUPPORTED(ib_spec->drop, 2513 LAST_DROP_FIELD)) 2514 return -EOPNOTSUPP; 2515 *is_drop = true; 2516 break; 2517 default: 2518 return -EINVAL; 2519 } 2520 2521 return 0; 2522 } 2523 2524 /* If a flow could catch both multicast and unicast packets, 2525 * it won't fall into the multicast flow steering table and this rule 2526 * could steal other multicast packets. 2527 */ 2528 static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr) 2529 { 2530 union ib_flow_spec *flow_spec; 2531 2532 if (ib_attr->type != IB_FLOW_ATTR_NORMAL || 2533 ib_attr->num_of_specs < 1) 2534 return false; 2535 2536 flow_spec = (union ib_flow_spec *)(ib_attr + 1); 2537 if (flow_spec->type == IB_FLOW_SPEC_IPV4) { 2538 struct ib_flow_spec_ipv4 *ipv4_spec; 2539 2540 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec; 2541 if (ipv4_is_multicast(ipv4_spec->val.dst_ip)) 2542 return true; 2543 2544 return false; 2545 } 2546 2547 if (flow_spec->type == IB_FLOW_SPEC_ETH) { 2548 struct ib_flow_spec_eth *eth_spec; 2549 2550 eth_spec = (struct ib_flow_spec_eth *)flow_spec; 2551 return is_multicast_ether_addr(eth_spec->mask.dst_mac) && 2552 is_multicast_ether_addr(eth_spec->val.dst_mac); 2553 } 2554 2555 return false; 2556 } 2557 2558 static bool is_valid_ethertype(struct mlx5_core_dev *mdev, 2559 const struct ib_flow_attr *flow_attr, 2560 bool check_inner) 2561 { 2562 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1); 2563 int match_ipv = check_inner ? 2564 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2565 ft_field_support.inner_ip_version) : 2566 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2567 ft_field_support.outer_ip_version); 2568 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0; 2569 bool ipv4_spec_valid, ipv6_spec_valid; 2570 unsigned int ip_spec_type = 0; 2571 bool has_ethertype = false; 2572 unsigned int spec_index; 2573 bool mask_valid = true; 2574 u16 eth_type = 0; 2575 bool type_valid; 2576 2577 /* Validate that ethertype is correct */ 2578 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 2579 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) && 2580 ib_spec->eth.mask.ether_type) { 2581 mask_valid = (ib_spec->eth.mask.ether_type == 2582 htons(0xffff)); 2583 has_ethertype = true; 2584 eth_type = ntohs(ib_spec->eth.val.ether_type); 2585 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) || 2586 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) { 2587 ip_spec_type = ib_spec->type; 2588 } 2589 ib_spec = (void *)ib_spec + ib_spec->size; 2590 } 2591 2592 type_valid = (!has_ethertype) || (!ip_spec_type); 2593 if (!type_valid && mask_valid) { 2594 ipv4_spec_valid = (eth_type == ETH_P_IP) && 2595 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit)); 2596 ipv6_spec_valid = (eth_type == ETH_P_IPV6) && 2597 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit)); 2598 2599 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) || 2600 (((eth_type == ETH_P_MPLS_UC) || 2601 (eth_type == ETH_P_MPLS_MC)) && match_ipv); 2602 } 2603 2604 return type_valid; 2605 } 2606 2607 static bool is_valid_attr(struct mlx5_core_dev *mdev, 2608 const struct ib_flow_attr *flow_attr) 2609 { 2610 return is_valid_ethertype(mdev, flow_attr, false) && 2611 is_valid_ethertype(mdev, flow_attr, true); 2612 } 2613 2614 static void put_flow_table(struct mlx5_ib_dev *dev, 2615 struct mlx5_ib_flow_prio *prio, bool ft_added) 2616 { 2617 prio->refcount -= !!ft_added; 2618 if (!prio->refcount) { 2619 mlx5_destroy_flow_table(prio->flow_table); 2620 prio->flow_table = NULL; 2621 } 2622 } 2623 2624 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id) 2625 { 2626 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device); 2627 struct mlx5_ib_flow_handler *handler = container_of(flow_id, 2628 struct mlx5_ib_flow_handler, 2629 ibflow); 2630 struct mlx5_ib_flow_handler *iter, *tmp; 2631 2632 mutex_lock(&dev->flow_db.lock); 2633 2634 list_for_each_entry_safe(iter, tmp, &handler->list, list) { 2635 mlx5_del_flow_rules(iter->rule); 2636 put_flow_table(dev, iter->prio, true); 2637 list_del(&iter->list); 2638 kfree(iter); 2639 } 2640 2641 mlx5_del_flow_rules(handler->rule); 2642 put_flow_table(dev, handler->prio, true); 2643 mutex_unlock(&dev->flow_db.lock); 2644 2645 kfree(handler); 2646 2647 return 0; 2648 } 2649 2650 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap) 2651 { 2652 priority *= 2; 2653 if (!dont_trap) 2654 priority++; 2655 return priority; 2656 } 2657 2658 enum flow_table_type { 2659 MLX5_IB_FT_RX, 2660 MLX5_IB_FT_TX 2661 }; 2662 2663 #define MLX5_FS_MAX_TYPES 6 2664 #define MLX5_FS_MAX_ENTRIES BIT(16) 2665 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev, 2666 struct ib_flow_attr *flow_attr, 2667 enum flow_table_type ft_type) 2668 { 2669 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP; 2670 struct mlx5_flow_namespace *ns = NULL; 2671 struct mlx5_ib_flow_prio *prio; 2672 struct mlx5_flow_table *ft; 2673 int max_table_size; 2674 int num_entries; 2675 int num_groups; 2676 int priority; 2677 int err = 0; 2678 2679 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 2680 log_max_ft_size)); 2681 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 2682 if (flow_is_multicast_only(flow_attr) && 2683 !dont_trap) 2684 priority = MLX5_IB_FLOW_MCAST_PRIO; 2685 else 2686 priority = ib_prio_to_core_prio(flow_attr->priority, 2687 dont_trap); 2688 ns = mlx5_get_flow_namespace(dev->mdev, 2689 MLX5_FLOW_NAMESPACE_BYPASS); 2690 num_entries = MLX5_FS_MAX_ENTRIES; 2691 num_groups = MLX5_FS_MAX_TYPES; 2692 prio = &dev->flow_db.prios[priority]; 2693 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 2694 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 2695 ns = mlx5_get_flow_namespace(dev->mdev, 2696 MLX5_FLOW_NAMESPACE_LEFTOVERS); 2697 build_leftovers_ft_param(&priority, 2698 &num_entries, 2699 &num_groups); 2700 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO]; 2701 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 2702 if (!MLX5_CAP_FLOWTABLE(dev->mdev, 2703 allow_sniffer_and_nic_rx_shared_tir)) 2704 return ERR_PTR(-ENOTSUPP); 2705 2706 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ? 2707 MLX5_FLOW_NAMESPACE_SNIFFER_RX : 2708 MLX5_FLOW_NAMESPACE_SNIFFER_TX); 2709 2710 prio = &dev->flow_db.sniffer[ft_type]; 2711 priority = 0; 2712 num_entries = 1; 2713 num_groups = 1; 2714 } 2715 2716 if (!ns) 2717 return ERR_PTR(-ENOTSUPP); 2718 2719 if (num_entries > max_table_size) 2720 return ERR_PTR(-ENOMEM); 2721 2722 ft = prio->flow_table; 2723 if (!ft) { 2724 ft = mlx5_create_auto_grouped_flow_table(ns, priority, 2725 num_entries, 2726 num_groups, 2727 0, 0); 2728 2729 if (!IS_ERR(ft)) { 2730 prio->refcount = 0; 2731 prio->flow_table = ft; 2732 } else { 2733 err = PTR_ERR(ft); 2734 } 2735 } 2736 2737 return err ? ERR_PTR(err) : prio; 2738 } 2739 2740 static void set_underlay_qp(struct mlx5_ib_dev *dev, 2741 struct mlx5_flow_spec *spec, 2742 u32 underlay_qpn) 2743 { 2744 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, 2745 spec->match_criteria, 2746 misc_parameters); 2747 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, 2748 misc_parameters); 2749 2750 if (underlay_qpn && 2751 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 2752 ft_field_support.bth_dst_qp)) { 2753 MLX5_SET(fte_match_set_misc, 2754 misc_params_v, bth_dst_qp, underlay_qpn); 2755 MLX5_SET(fte_match_set_misc, 2756 misc_params_c, bth_dst_qp, 0xffffff); 2757 } 2758 } 2759 2760 static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev, 2761 struct mlx5_ib_flow_prio *ft_prio, 2762 const struct ib_flow_attr *flow_attr, 2763 struct mlx5_flow_destination *dst, 2764 u32 underlay_qpn) 2765 { 2766 struct mlx5_flow_table *ft = ft_prio->flow_table; 2767 struct mlx5_ib_flow_handler *handler; 2768 struct mlx5_flow_act flow_act = {0}; 2769 struct mlx5_flow_spec *spec; 2770 struct mlx5_flow_destination *rule_dst = dst; 2771 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr); 2772 unsigned int spec_index; 2773 u32 flow_tag = MLX5_FS_DEFAULT_FLOW_TAG; 2774 bool is_drop = false; 2775 int err = 0; 2776 int dest_num = 1; 2777 2778 if (!is_valid_attr(dev->mdev, flow_attr)) 2779 return ERR_PTR(-EINVAL); 2780 2781 spec = kvzalloc(sizeof(*spec), GFP_KERNEL); 2782 handler = kzalloc(sizeof(*handler), GFP_KERNEL); 2783 if (!handler || !spec) { 2784 err = -ENOMEM; 2785 goto free; 2786 } 2787 2788 INIT_LIST_HEAD(&handler->list); 2789 2790 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 2791 err = parse_flow_attr(dev->mdev, spec->match_criteria, 2792 spec->match_value, 2793 ib_flow, &flow_tag, &is_drop); 2794 if (err < 0) 2795 goto free; 2796 2797 ib_flow += ((union ib_flow_spec *)ib_flow)->size; 2798 } 2799 2800 if (!flow_is_multicast_only(flow_attr)) 2801 set_underlay_qp(dev, spec, underlay_qpn); 2802 2803 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria); 2804 if (is_drop) { 2805 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_DROP; 2806 rule_dst = NULL; 2807 dest_num = 0; 2808 } else { 2809 flow_act.action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST : 2810 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO; 2811 } 2812 2813 if (flow_tag != MLX5_FS_DEFAULT_FLOW_TAG && 2814 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 2815 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) { 2816 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n", 2817 flow_tag, flow_attr->type); 2818 err = -EINVAL; 2819 goto free; 2820 } 2821 flow_act.flow_tag = flow_tag; 2822 handler->rule = mlx5_add_flow_rules(ft, spec, 2823 &flow_act, 2824 rule_dst, dest_num); 2825 2826 if (IS_ERR(handler->rule)) { 2827 err = PTR_ERR(handler->rule); 2828 goto free; 2829 } 2830 2831 ft_prio->refcount++; 2832 handler->prio = ft_prio; 2833 2834 ft_prio->flow_table = ft; 2835 free: 2836 if (err) 2837 kfree(handler); 2838 kvfree(spec); 2839 return err ? ERR_PTR(err) : handler; 2840 } 2841 2842 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev, 2843 struct mlx5_ib_flow_prio *ft_prio, 2844 const struct ib_flow_attr *flow_attr, 2845 struct mlx5_flow_destination *dst) 2846 { 2847 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0); 2848 } 2849 2850 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev, 2851 struct mlx5_ib_flow_prio *ft_prio, 2852 struct ib_flow_attr *flow_attr, 2853 struct mlx5_flow_destination *dst) 2854 { 2855 struct mlx5_ib_flow_handler *handler_dst = NULL; 2856 struct mlx5_ib_flow_handler *handler = NULL; 2857 2858 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL); 2859 if (!IS_ERR(handler)) { 2860 handler_dst = create_flow_rule(dev, ft_prio, 2861 flow_attr, dst); 2862 if (IS_ERR(handler_dst)) { 2863 mlx5_del_flow_rules(handler->rule); 2864 ft_prio->refcount--; 2865 kfree(handler); 2866 handler = handler_dst; 2867 } else { 2868 list_add(&handler_dst->list, &handler->list); 2869 } 2870 } 2871 2872 return handler; 2873 } 2874 enum { 2875 LEFTOVERS_MC, 2876 LEFTOVERS_UC, 2877 }; 2878 2879 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev, 2880 struct mlx5_ib_flow_prio *ft_prio, 2881 struct ib_flow_attr *flow_attr, 2882 struct mlx5_flow_destination *dst) 2883 { 2884 struct mlx5_ib_flow_handler *handler_ucast = NULL; 2885 struct mlx5_ib_flow_handler *handler = NULL; 2886 2887 static struct { 2888 struct ib_flow_attr flow_attr; 2889 struct ib_flow_spec_eth eth_flow; 2890 } leftovers_specs[] = { 2891 [LEFTOVERS_MC] = { 2892 .flow_attr = { 2893 .num_of_specs = 1, 2894 .size = sizeof(leftovers_specs[0]) 2895 }, 2896 .eth_flow = { 2897 .type = IB_FLOW_SPEC_ETH, 2898 .size = sizeof(struct ib_flow_spec_eth), 2899 .mask = {.dst_mac = {0x1} }, 2900 .val = {.dst_mac = {0x1} } 2901 } 2902 }, 2903 [LEFTOVERS_UC] = { 2904 .flow_attr = { 2905 .num_of_specs = 1, 2906 .size = sizeof(leftovers_specs[0]) 2907 }, 2908 .eth_flow = { 2909 .type = IB_FLOW_SPEC_ETH, 2910 .size = sizeof(struct ib_flow_spec_eth), 2911 .mask = {.dst_mac = {0x1} }, 2912 .val = {.dst_mac = {} } 2913 } 2914 } 2915 }; 2916 2917 handler = create_flow_rule(dev, ft_prio, 2918 &leftovers_specs[LEFTOVERS_MC].flow_attr, 2919 dst); 2920 if (!IS_ERR(handler) && 2921 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) { 2922 handler_ucast = create_flow_rule(dev, ft_prio, 2923 &leftovers_specs[LEFTOVERS_UC].flow_attr, 2924 dst); 2925 if (IS_ERR(handler_ucast)) { 2926 mlx5_del_flow_rules(handler->rule); 2927 ft_prio->refcount--; 2928 kfree(handler); 2929 handler = handler_ucast; 2930 } else { 2931 list_add(&handler_ucast->list, &handler->list); 2932 } 2933 } 2934 2935 return handler; 2936 } 2937 2938 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev, 2939 struct mlx5_ib_flow_prio *ft_rx, 2940 struct mlx5_ib_flow_prio *ft_tx, 2941 struct mlx5_flow_destination *dst) 2942 { 2943 struct mlx5_ib_flow_handler *handler_rx; 2944 struct mlx5_ib_flow_handler *handler_tx; 2945 int err; 2946 static const struct ib_flow_attr flow_attr = { 2947 .num_of_specs = 0, 2948 .size = sizeof(flow_attr) 2949 }; 2950 2951 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst); 2952 if (IS_ERR(handler_rx)) { 2953 err = PTR_ERR(handler_rx); 2954 goto err; 2955 } 2956 2957 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst); 2958 if (IS_ERR(handler_tx)) { 2959 err = PTR_ERR(handler_tx); 2960 goto err_tx; 2961 } 2962 2963 list_add(&handler_tx->list, &handler_rx->list); 2964 2965 return handler_rx; 2966 2967 err_tx: 2968 mlx5_del_flow_rules(handler_rx->rule); 2969 ft_rx->refcount--; 2970 kfree(handler_rx); 2971 err: 2972 return ERR_PTR(err); 2973 } 2974 2975 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp, 2976 struct ib_flow_attr *flow_attr, 2977 int domain) 2978 { 2979 struct mlx5_ib_dev *dev = to_mdev(qp->device); 2980 struct mlx5_ib_qp *mqp = to_mqp(qp); 2981 struct mlx5_ib_flow_handler *handler = NULL; 2982 struct mlx5_flow_destination *dst = NULL; 2983 struct mlx5_ib_flow_prio *ft_prio_tx = NULL; 2984 struct mlx5_ib_flow_prio *ft_prio; 2985 int err; 2986 int underlay_qpn; 2987 2988 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) 2989 return ERR_PTR(-ENOMEM); 2990 2991 if (domain != IB_FLOW_DOMAIN_USER || 2992 flow_attr->port > dev->num_ports || 2993 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP)) 2994 return ERR_PTR(-EINVAL); 2995 2996 dst = kzalloc(sizeof(*dst), GFP_KERNEL); 2997 if (!dst) 2998 return ERR_PTR(-ENOMEM); 2999 3000 mutex_lock(&dev->flow_db.lock); 3001 3002 ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX); 3003 if (IS_ERR(ft_prio)) { 3004 err = PTR_ERR(ft_prio); 3005 goto unlock; 3006 } 3007 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 3008 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX); 3009 if (IS_ERR(ft_prio_tx)) { 3010 err = PTR_ERR(ft_prio_tx); 3011 ft_prio_tx = NULL; 3012 goto destroy_ft; 3013 } 3014 } 3015 3016 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR; 3017 if (mqp->flags & MLX5_IB_QP_RSS) 3018 dst->tir_num = mqp->rss_qp.tirn; 3019 else 3020 dst->tir_num = mqp->raw_packet_qp.rq.tirn; 3021 3022 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 3023 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) { 3024 handler = create_dont_trap_rule(dev, ft_prio, 3025 flow_attr, dst); 3026 } else { 3027 underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ? 3028 mqp->underlay_qpn : 0; 3029 handler = _create_flow_rule(dev, ft_prio, flow_attr, 3030 dst, underlay_qpn); 3031 } 3032 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 3033 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 3034 handler = create_leftovers_rule(dev, ft_prio, flow_attr, 3035 dst); 3036 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 3037 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst); 3038 } else { 3039 err = -EINVAL; 3040 goto destroy_ft; 3041 } 3042 3043 if (IS_ERR(handler)) { 3044 err = PTR_ERR(handler); 3045 handler = NULL; 3046 goto destroy_ft; 3047 } 3048 3049 mutex_unlock(&dev->flow_db.lock); 3050 kfree(dst); 3051 3052 return &handler->ibflow; 3053 3054 destroy_ft: 3055 put_flow_table(dev, ft_prio, false); 3056 if (ft_prio_tx) 3057 put_flow_table(dev, ft_prio_tx, false); 3058 unlock: 3059 mutex_unlock(&dev->flow_db.lock); 3060 kfree(dst); 3061 kfree(handler); 3062 return ERR_PTR(err); 3063 } 3064 3065 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 3066 { 3067 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3068 struct mlx5_ib_qp *mqp = to_mqp(ibqp); 3069 int err; 3070 3071 if (mqp->flags & MLX5_IB_QP_UNDERLAY) { 3072 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n"); 3073 return -EOPNOTSUPP; 3074 } 3075 3076 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num); 3077 if (err) 3078 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 3079 ibqp->qp_num, gid->raw); 3080 3081 return err; 3082 } 3083 3084 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 3085 { 3086 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3087 int err; 3088 3089 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num); 3090 if (err) 3091 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 3092 ibqp->qp_num, gid->raw); 3093 3094 return err; 3095 } 3096 3097 static int init_node_data(struct mlx5_ib_dev *dev) 3098 { 3099 int err; 3100 3101 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 3102 if (err) 3103 return err; 3104 3105 dev->mdev->rev_id = dev->mdev->pdev->revision; 3106 3107 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 3108 } 3109 3110 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr, 3111 char *buf) 3112 { 3113 struct mlx5_ib_dev *dev = 3114 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 3115 3116 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages); 3117 } 3118 3119 static ssize_t show_reg_pages(struct device *device, 3120 struct device_attribute *attr, char *buf) 3121 { 3122 struct mlx5_ib_dev *dev = 3123 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 3124 3125 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 3126 } 3127 3128 static ssize_t show_hca(struct device *device, struct device_attribute *attr, 3129 char *buf) 3130 { 3131 struct mlx5_ib_dev *dev = 3132 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 3133 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device); 3134 } 3135 3136 static ssize_t show_rev(struct device *device, struct device_attribute *attr, 3137 char *buf) 3138 { 3139 struct mlx5_ib_dev *dev = 3140 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 3141 return sprintf(buf, "%x\n", dev->mdev->rev_id); 3142 } 3143 3144 static ssize_t show_board(struct device *device, struct device_attribute *attr, 3145 char *buf) 3146 { 3147 struct mlx5_ib_dev *dev = 3148 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 3149 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 3150 dev->mdev->board_id); 3151 } 3152 3153 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL); 3154 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL); 3155 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL); 3156 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL); 3157 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL); 3158 3159 static struct device_attribute *mlx5_class_attributes[] = { 3160 &dev_attr_hw_rev, 3161 &dev_attr_hca_type, 3162 &dev_attr_board_id, 3163 &dev_attr_fw_pages, 3164 &dev_attr_reg_pages, 3165 }; 3166 3167 static void pkey_change_handler(struct work_struct *work) 3168 { 3169 struct mlx5_ib_port_resources *ports = 3170 container_of(work, struct mlx5_ib_port_resources, 3171 pkey_change_work); 3172 3173 mutex_lock(&ports->devr->mutex); 3174 mlx5_ib_gsi_pkey_change(ports->gsi); 3175 mutex_unlock(&ports->devr->mutex); 3176 } 3177 3178 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 3179 { 3180 struct mlx5_ib_qp *mqp; 3181 struct mlx5_ib_cq *send_mcq, *recv_mcq; 3182 struct mlx5_core_cq *mcq; 3183 struct list_head cq_armed_list; 3184 unsigned long flags_qp; 3185 unsigned long flags_cq; 3186 unsigned long flags; 3187 3188 INIT_LIST_HEAD(&cq_armed_list); 3189 3190 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 3191 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 3192 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 3193 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 3194 if (mqp->sq.tail != mqp->sq.head) { 3195 send_mcq = to_mcq(mqp->ibqp.send_cq); 3196 spin_lock_irqsave(&send_mcq->lock, flags_cq); 3197 if (send_mcq->mcq.comp && 3198 mqp->ibqp.send_cq->comp_handler) { 3199 if (!send_mcq->mcq.reset_notify_added) { 3200 send_mcq->mcq.reset_notify_added = 1; 3201 list_add_tail(&send_mcq->mcq.reset_notify, 3202 &cq_armed_list); 3203 } 3204 } 3205 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 3206 } 3207 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 3208 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 3209 /* no handling is needed for SRQ */ 3210 if (!mqp->ibqp.srq) { 3211 if (mqp->rq.tail != mqp->rq.head) { 3212 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 3213 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 3214 if (recv_mcq->mcq.comp && 3215 mqp->ibqp.recv_cq->comp_handler) { 3216 if (!recv_mcq->mcq.reset_notify_added) { 3217 recv_mcq->mcq.reset_notify_added = 1; 3218 list_add_tail(&recv_mcq->mcq.reset_notify, 3219 &cq_armed_list); 3220 } 3221 } 3222 spin_unlock_irqrestore(&recv_mcq->lock, 3223 flags_cq); 3224 } 3225 } 3226 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 3227 } 3228 /*At that point all inflight post send were put to be executed as of we 3229 * lock/unlock above locks Now need to arm all involved CQs. 3230 */ 3231 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 3232 mcq->comp(mcq); 3233 } 3234 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 3235 } 3236 3237 static void delay_drop_handler(struct work_struct *work) 3238 { 3239 int err; 3240 struct mlx5_ib_delay_drop *delay_drop = 3241 container_of(work, struct mlx5_ib_delay_drop, 3242 delay_drop_work); 3243 3244 atomic_inc(&delay_drop->events_cnt); 3245 3246 mutex_lock(&delay_drop->lock); 3247 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev, 3248 delay_drop->timeout); 3249 if (err) { 3250 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n", 3251 delay_drop->timeout); 3252 delay_drop->activate = false; 3253 } 3254 mutex_unlock(&delay_drop->lock); 3255 } 3256 3257 static void mlx5_ib_handle_event(struct work_struct *_work) 3258 { 3259 struct mlx5_ib_event_work *work = 3260 container_of(_work, struct mlx5_ib_event_work, work); 3261 struct mlx5_ib_dev *ibdev; 3262 struct ib_event ibev; 3263 bool fatal = false; 3264 u8 port = 0; 3265 3266 if (mlx5_core_is_mp_slave(work->dev)) { 3267 ibdev = mlx5_ib_get_ibdev_from_mpi(work->context); 3268 if (!ibdev) 3269 goto out; 3270 } else { 3271 ibdev = work->context; 3272 } 3273 3274 switch (work->event) { 3275 case MLX5_DEV_EVENT_SYS_ERROR: 3276 ibev.event = IB_EVENT_DEVICE_FATAL; 3277 mlx5_ib_handle_internal_error(ibdev); 3278 fatal = true; 3279 break; 3280 3281 case MLX5_DEV_EVENT_PORT_UP: 3282 case MLX5_DEV_EVENT_PORT_DOWN: 3283 case MLX5_DEV_EVENT_PORT_INITIALIZED: 3284 port = (u8)work->param; 3285 3286 /* In RoCE, port up/down events are handled in 3287 * mlx5_netdev_event(). 3288 */ 3289 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 3290 IB_LINK_LAYER_ETHERNET) 3291 goto out; 3292 3293 ibev.event = (work->event == MLX5_DEV_EVENT_PORT_UP) ? 3294 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 3295 break; 3296 3297 case MLX5_DEV_EVENT_LID_CHANGE: 3298 ibev.event = IB_EVENT_LID_CHANGE; 3299 port = (u8)work->param; 3300 break; 3301 3302 case MLX5_DEV_EVENT_PKEY_CHANGE: 3303 ibev.event = IB_EVENT_PKEY_CHANGE; 3304 port = (u8)work->param; 3305 3306 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 3307 break; 3308 3309 case MLX5_DEV_EVENT_GUID_CHANGE: 3310 ibev.event = IB_EVENT_GID_CHANGE; 3311 port = (u8)work->param; 3312 break; 3313 3314 case MLX5_DEV_EVENT_CLIENT_REREG: 3315 ibev.event = IB_EVENT_CLIENT_REREGISTER; 3316 port = (u8)work->param; 3317 break; 3318 case MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT: 3319 schedule_work(&ibdev->delay_drop.delay_drop_work); 3320 goto out; 3321 default: 3322 goto out; 3323 } 3324 3325 ibev.device = &ibdev->ib_dev; 3326 ibev.element.port_num = port; 3327 3328 if (port < 1 || port > ibdev->num_ports) { 3329 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port); 3330 goto out; 3331 } 3332 3333 if (ibdev->ib_active) 3334 ib_dispatch_event(&ibev); 3335 3336 if (fatal) 3337 ibdev->ib_active = false; 3338 out: 3339 kfree(work); 3340 } 3341 3342 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context, 3343 enum mlx5_dev_event event, unsigned long param) 3344 { 3345 struct mlx5_ib_event_work *work; 3346 3347 work = kmalloc(sizeof(*work), GFP_ATOMIC); 3348 if (work) { 3349 INIT_WORK(&work->work, mlx5_ib_handle_event); 3350 work->dev = dev; 3351 work->param = param; 3352 work->context = context; 3353 work->event = event; 3354 3355 queue_work(mlx5_ib_event_wq, &work->work); 3356 return; 3357 } 3358 3359 dev_warn(&dev->pdev->dev, "%s: mlx5_dev_event: %d, with param: %lu dropped, couldn't allocate memory.\n", 3360 __func__, event, param); 3361 } 3362 3363 static int set_has_smi_cap(struct mlx5_ib_dev *dev) 3364 { 3365 struct mlx5_hca_vport_context vport_ctx; 3366 int err; 3367 int port; 3368 3369 for (port = 1; port <= dev->num_ports; port++) { 3370 dev->mdev->port_caps[port - 1].has_smi = false; 3371 if (MLX5_CAP_GEN(dev->mdev, port_type) == 3372 MLX5_CAP_PORT_TYPE_IB) { 3373 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) { 3374 err = mlx5_query_hca_vport_context(dev->mdev, 0, 3375 port, 0, 3376 &vport_ctx); 3377 if (err) { 3378 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n", 3379 port, err); 3380 return err; 3381 } 3382 dev->mdev->port_caps[port - 1].has_smi = 3383 vport_ctx.has_smi; 3384 } else { 3385 dev->mdev->port_caps[port - 1].has_smi = true; 3386 } 3387 } 3388 } 3389 return 0; 3390 } 3391 3392 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 3393 { 3394 int port; 3395 3396 for (port = 1; port <= dev->num_ports; port++) 3397 mlx5_query_ext_port_caps(dev, port); 3398 } 3399 3400 static int get_port_caps(struct mlx5_ib_dev *dev, u8 port) 3401 { 3402 struct ib_device_attr *dprops = NULL; 3403 struct ib_port_attr *pprops = NULL; 3404 int err = -ENOMEM; 3405 struct ib_udata uhw = {.inlen = 0, .outlen = 0}; 3406 3407 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL); 3408 if (!pprops) 3409 goto out; 3410 3411 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL); 3412 if (!dprops) 3413 goto out; 3414 3415 err = set_has_smi_cap(dev); 3416 if (err) 3417 goto out; 3418 3419 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw); 3420 if (err) { 3421 mlx5_ib_warn(dev, "query_device failed %d\n", err); 3422 goto out; 3423 } 3424 3425 memset(pprops, 0, sizeof(*pprops)); 3426 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops); 3427 if (err) { 3428 mlx5_ib_warn(dev, "query_port %d failed %d\n", 3429 port, err); 3430 goto out; 3431 } 3432 3433 dev->mdev->port_caps[port - 1].pkey_table_len = 3434 dprops->max_pkeys; 3435 dev->mdev->port_caps[port - 1].gid_table_len = 3436 pprops->gid_tbl_len; 3437 mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n", 3438 port, dprops->max_pkeys, pprops->gid_tbl_len); 3439 3440 out: 3441 kfree(pprops); 3442 kfree(dprops); 3443 3444 return err; 3445 } 3446 3447 static void destroy_umrc_res(struct mlx5_ib_dev *dev) 3448 { 3449 int err; 3450 3451 err = mlx5_mr_cache_cleanup(dev); 3452 if (err) 3453 mlx5_ib_warn(dev, "mr cache cleanup failed\n"); 3454 3455 mlx5_ib_destroy_qp(dev->umrc.qp); 3456 ib_free_cq(dev->umrc.cq); 3457 ib_dealloc_pd(dev->umrc.pd); 3458 } 3459 3460 enum { 3461 MAX_UMR_WR = 128, 3462 }; 3463 3464 static int create_umr_res(struct mlx5_ib_dev *dev) 3465 { 3466 struct ib_qp_init_attr *init_attr = NULL; 3467 struct ib_qp_attr *attr = NULL; 3468 struct ib_pd *pd; 3469 struct ib_cq *cq; 3470 struct ib_qp *qp; 3471 int ret; 3472 3473 attr = kzalloc(sizeof(*attr), GFP_KERNEL); 3474 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL); 3475 if (!attr || !init_attr) { 3476 ret = -ENOMEM; 3477 goto error_0; 3478 } 3479 3480 pd = ib_alloc_pd(&dev->ib_dev, 0); 3481 if (IS_ERR(pd)) { 3482 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n"); 3483 ret = PTR_ERR(pd); 3484 goto error_0; 3485 } 3486 3487 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ); 3488 if (IS_ERR(cq)) { 3489 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n"); 3490 ret = PTR_ERR(cq); 3491 goto error_2; 3492 } 3493 3494 init_attr->send_cq = cq; 3495 init_attr->recv_cq = cq; 3496 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR; 3497 init_attr->cap.max_send_wr = MAX_UMR_WR; 3498 init_attr->cap.max_send_sge = 1; 3499 init_attr->qp_type = MLX5_IB_QPT_REG_UMR; 3500 init_attr->port_num = 1; 3501 qp = mlx5_ib_create_qp(pd, init_attr, NULL); 3502 if (IS_ERR(qp)) { 3503 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n"); 3504 ret = PTR_ERR(qp); 3505 goto error_3; 3506 } 3507 qp->device = &dev->ib_dev; 3508 qp->real_qp = qp; 3509 qp->uobject = NULL; 3510 qp->qp_type = MLX5_IB_QPT_REG_UMR; 3511 qp->send_cq = init_attr->send_cq; 3512 qp->recv_cq = init_attr->recv_cq; 3513 3514 attr->qp_state = IB_QPS_INIT; 3515 attr->port_num = 1; 3516 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX | 3517 IB_QP_PORT, NULL); 3518 if (ret) { 3519 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n"); 3520 goto error_4; 3521 } 3522 3523 memset(attr, 0, sizeof(*attr)); 3524 attr->qp_state = IB_QPS_RTR; 3525 attr->path_mtu = IB_MTU_256; 3526 3527 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 3528 if (ret) { 3529 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n"); 3530 goto error_4; 3531 } 3532 3533 memset(attr, 0, sizeof(*attr)); 3534 attr->qp_state = IB_QPS_RTS; 3535 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 3536 if (ret) { 3537 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n"); 3538 goto error_4; 3539 } 3540 3541 dev->umrc.qp = qp; 3542 dev->umrc.cq = cq; 3543 dev->umrc.pd = pd; 3544 3545 sema_init(&dev->umrc.sem, MAX_UMR_WR); 3546 ret = mlx5_mr_cache_init(dev); 3547 if (ret) { 3548 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 3549 goto error_4; 3550 } 3551 3552 kfree(attr); 3553 kfree(init_attr); 3554 3555 return 0; 3556 3557 error_4: 3558 mlx5_ib_destroy_qp(qp); 3559 3560 error_3: 3561 ib_free_cq(cq); 3562 3563 error_2: 3564 ib_dealloc_pd(pd); 3565 3566 error_0: 3567 kfree(attr); 3568 kfree(init_attr); 3569 return ret; 3570 } 3571 3572 static u8 mlx5_get_umr_fence(u8 umr_fence_cap) 3573 { 3574 switch (umr_fence_cap) { 3575 case MLX5_CAP_UMR_FENCE_NONE: 3576 return MLX5_FENCE_MODE_NONE; 3577 case MLX5_CAP_UMR_FENCE_SMALL: 3578 return MLX5_FENCE_MODE_INITIATOR_SMALL; 3579 default: 3580 return MLX5_FENCE_MODE_STRONG_ORDERING; 3581 } 3582 } 3583 3584 static int create_dev_resources(struct mlx5_ib_resources *devr) 3585 { 3586 struct ib_srq_init_attr attr; 3587 struct mlx5_ib_dev *dev; 3588 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 3589 int port; 3590 int ret = 0; 3591 3592 dev = container_of(devr, struct mlx5_ib_dev, devr); 3593 3594 mutex_init(&devr->mutex); 3595 3596 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL); 3597 if (IS_ERR(devr->p0)) { 3598 ret = PTR_ERR(devr->p0); 3599 goto error0; 3600 } 3601 devr->p0->device = &dev->ib_dev; 3602 devr->p0->uobject = NULL; 3603 atomic_set(&devr->p0->usecnt, 0); 3604 3605 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL); 3606 if (IS_ERR(devr->c0)) { 3607 ret = PTR_ERR(devr->c0); 3608 goto error1; 3609 } 3610 devr->c0->device = &dev->ib_dev; 3611 devr->c0->uobject = NULL; 3612 devr->c0->comp_handler = NULL; 3613 devr->c0->event_handler = NULL; 3614 devr->c0->cq_context = NULL; 3615 atomic_set(&devr->c0->usecnt, 0); 3616 3617 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 3618 if (IS_ERR(devr->x0)) { 3619 ret = PTR_ERR(devr->x0); 3620 goto error2; 3621 } 3622 devr->x0->device = &dev->ib_dev; 3623 devr->x0->inode = NULL; 3624 atomic_set(&devr->x0->usecnt, 0); 3625 mutex_init(&devr->x0->tgt_qp_mutex); 3626 INIT_LIST_HEAD(&devr->x0->tgt_qp_list); 3627 3628 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 3629 if (IS_ERR(devr->x1)) { 3630 ret = PTR_ERR(devr->x1); 3631 goto error3; 3632 } 3633 devr->x1->device = &dev->ib_dev; 3634 devr->x1->inode = NULL; 3635 atomic_set(&devr->x1->usecnt, 0); 3636 mutex_init(&devr->x1->tgt_qp_mutex); 3637 INIT_LIST_HEAD(&devr->x1->tgt_qp_list); 3638 3639 memset(&attr, 0, sizeof(attr)); 3640 attr.attr.max_sge = 1; 3641 attr.attr.max_wr = 1; 3642 attr.srq_type = IB_SRQT_XRC; 3643 attr.ext.cq = devr->c0; 3644 attr.ext.xrc.xrcd = devr->x0; 3645 3646 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 3647 if (IS_ERR(devr->s0)) { 3648 ret = PTR_ERR(devr->s0); 3649 goto error4; 3650 } 3651 devr->s0->device = &dev->ib_dev; 3652 devr->s0->pd = devr->p0; 3653 devr->s0->uobject = NULL; 3654 devr->s0->event_handler = NULL; 3655 devr->s0->srq_context = NULL; 3656 devr->s0->srq_type = IB_SRQT_XRC; 3657 devr->s0->ext.xrc.xrcd = devr->x0; 3658 devr->s0->ext.cq = devr->c0; 3659 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt); 3660 atomic_inc(&devr->s0->ext.cq->usecnt); 3661 atomic_inc(&devr->p0->usecnt); 3662 atomic_set(&devr->s0->usecnt, 0); 3663 3664 memset(&attr, 0, sizeof(attr)); 3665 attr.attr.max_sge = 1; 3666 attr.attr.max_wr = 1; 3667 attr.srq_type = IB_SRQT_BASIC; 3668 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 3669 if (IS_ERR(devr->s1)) { 3670 ret = PTR_ERR(devr->s1); 3671 goto error5; 3672 } 3673 devr->s1->device = &dev->ib_dev; 3674 devr->s1->pd = devr->p0; 3675 devr->s1->uobject = NULL; 3676 devr->s1->event_handler = NULL; 3677 devr->s1->srq_context = NULL; 3678 devr->s1->srq_type = IB_SRQT_BASIC; 3679 devr->s1->ext.cq = devr->c0; 3680 atomic_inc(&devr->p0->usecnt); 3681 atomic_set(&devr->s1->usecnt, 0); 3682 3683 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) { 3684 INIT_WORK(&devr->ports[port].pkey_change_work, 3685 pkey_change_handler); 3686 devr->ports[port].devr = devr; 3687 } 3688 3689 return 0; 3690 3691 error5: 3692 mlx5_ib_destroy_srq(devr->s0); 3693 error4: 3694 mlx5_ib_dealloc_xrcd(devr->x1); 3695 error3: 3696 mlx5_ib_dealloc_xrcd(devr->x0); 3697 error2: 3698 mlx5_ib_destroy_cq(devr->c0); 3699 error1: 3700 mlx5_ib_dealloc_pd(devr->p0); 3701 error0: 3702 return ret; 3703 } 3704 3705 static void destroy_dev_resources(struct mlx5_ib_resources *devr) 3706 { 3707 struct mlx5_ib_dev *dev = 3708 container_of(devr, struct mlx5_ib_dev, devr); 3709 int port; 3710 3711 mlx5_ib_destroy_srq(devr->s1); 3712 mlx5_ib_destroy_srq(devr->s0); 3713 mlx5_ib_dealloc_xrcd(devr->x0); 3714 mlx5_ib_dealloc_xrcd(devr->x1); 3715 mlx5_ib_destroy_cq(devr->c0); 3716 mlx5_ib_dealloc_pd(devr->p0); 3717 3718 /* Make sure no change P_Key work items are still executing */ 3719 for (port = 0; port < dev->num_ports; ++port) 3720 cancel_work_sync(&devr->ports[port].pkey_change_work); 3721 } 3722 3723 static u32 get_core_cap_flags(struct ib_device *ibdev) 3724 { 3725 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3726 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 3727 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 3728 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 3729 bool raw_support = !mlx5_core_mp_enabled(dev->mdev); 3730 u32 ret = 0; 3731 3732 if (ll == IB_LINK_LAYER_INFINIBAND) 3733 return RDMA_CORE_PORT_IBA_IB; 3734 3735 if (raw_support) 3736 ret = RDMA_CORE_PORT_RAW_PACKET; 3737 3738 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 3739 return ret; 3740 3741 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 3742 return ret; 3743 3744 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 3745 ret |= RDMA_CORE_PORT_IBA_ROCE; 3746 3747 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 3748 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 3749 3750 return ret; 3751 } 3752 3753 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num, 3754 struct ib_port_immutable *immutable) 3755 { 3756 struct ib_port_attr attr; 3757 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3758 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num); 3759 int err; 3760 3761 immutable->core_cap_flags = get_core_cap_flags(ibdev); 3762 3763 err = ib_query_port(ibdev, port_num, &attr); 3764 if (err) 3765 return err; 3766 3767 immutable->pkey_tbl_len = attr.pkey_tbl_len; 3768 immutable->gid_tbl_len = attr.gid_tbl_len; 3769 immutable->core_cap_flags = get_core_cap_flags(ibdev); 3770 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce)) 3771 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 3772 3773 return 0; 3774 } 3775 3776 static void get_dev_fw_str(struct ib_device *ibdev, char *str) 3777 { 3778 struct mlx5_ib_dev *dev = 3779 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 3780 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d", 3781 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev), 3782 fw_rev_sub(dev->mdev)); 3783 } 3784 3785 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev) 3786 { 3787 struct mlx5_core_dev *mdev = dev->mdev; 3788 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev, 3789 MLX5_FLOW_NAMESPACE_LAG); 3790 struct mlx5_flow_table *ft; 3791 int err; 3792 3793 if (!ns || !mlx5_lag_is_active(mdev)) 3794 return 0; 3795 3796 err = mlx5_cmd_create_vport_lag(mdev); 3797 if (err) 3798 return err; 3799 3800 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0); 3801 if (IS_ERR(ft)) { 3802 err = PTR_ERR(ft); 3803 goto err_destroy_vport_lag; 3804 } 3805 3806 dev->flow_db.lag_demux_ft = ft; 3807 return 0; 3808 3809 err_destroy_vport_lag: 3810 mlx5_cmd_destroy_vport_lag(mdev); 3811 return err; 3812 } 3813 3814 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev) 3815 { 3816 struct mlx5_core_dev *mdev = dev->mdev; 3817 3818 if (dev->flow_db.lag_demux_ft) { 3819 mlx5_destroy_flow_table(dev->flow_db.lag_demux_ft); 3820 dev->flow_db.lag_demux_ft = NULL; 3821 3822 mlx5_cmd_destroy_vport_lag(mdev); 3823 } 3824 } 3825 3826 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num) 3827 { 3828 int err; 3829 3830 dev->roce[port_num].nb.notifier_call = mlx5_netdev_event; 3831 err = register_netdevice_notifier(&dev->roce[port_num].nb); 3832 if (err) { 3833 dev->roce[port_num].nb.notifier_call = NULL; 3834 return err; 3835 } 3836 3837 return 0; 3838 } 3839 3840 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num) 3841 { 3842 if (dev->roce[port_num].nb.notifier_call) { 3843 unregister_netdevice_notifier(&dev->roce[port_num].nb); 3844 dev->roce[port_num].nb.notifier_call = NULL; 3845 } 3846 } 3847 3848 static int mlx5_enable_eth(struct mlx5_ib_dev *dev, u8 port_num) 3849 { 3850 int err; 3851 3852 err = mlx5_add_netdev_notifier(dev, port_num); 3853 if (err) 3854 return err; 3855 3856 if (MLX5_CAP_GEN(dev->mdev, roce)) { 3857 err = mlx5_nic_vport_enable_roce(dev->mdev); 3858 if (err) 3859 goto err_unregister_netdevice_notifier; 3860 } 3861 3862 err = mlx5_eth_lag_init(dev); 3863 if (err) 3864 goto err_disable_roce; 3865 3866 return 0; 3867 3868 err_disable_roce: 3869 if (MLX5_CAP_GEN(dev->mdev, roce)) 3870 mlx5_nic_vport_disable_roce(dev->mdev); 3871 3872 err_unregister_netdevice_notifier: 3873 mlx5_remove_netdev_notifier(dev, port_num); 3874 return err; 3875 } 3876 3877 static void mlx5_disable_eth(struct mlx5_ib_dev *dev) 3878 { 3879 mlx5_eth_lag_cleanup(dev); 3880 if (MLX5_CAP_GEN(dev->mdev, roce)) 3881 mlx5_nic_vport_disable_roce(dev->mdev); 3882 } 3883 3884 struct mlx5_ib_counter { 3885 const char *name; 3886 size_t offset; 3887 }; 3888 3889 #define INIT_Q_COUNTER(_name) \ 3890 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)} 3891 3892 static const struct mlx5_ib_counter basic_q_cnts[] = { 3893 INIT_Q_COUNTER(rx_write_requests), 3894 INIT_Q_COUNTER(rx_read_requests), 3895 INIT_Q_COUNTER(rx_atomic_requests), 3896 INIT_Q_COUNTER(out_of_buffer), 3897 }; 3898 3899 static const struct mlx5_ib_counter out_of_seq_q_cnts[] = { 3900 INIT_Q_COUNTER(out_of_sequence), 3901 }; 3902 3903 static const struct mlx5_ib_counter retrans_q_cnts[] = { 3904 INIT_Q_COUNTER(duplicate_request), 3905 INIT_Q_COUNTER(rnr_nak_retry_err), 3906 INIT_Q_COUNTER(packet_seq_err), 3907 INIT_Q_COUNTER(implied_nak_seq_err), 3908 INIT_Q_COUNTER(local_ack_timeout_err), 3909 }; 3910 3911 #define INIT_CONG_COUNTER(_name) \ 3912 { .name = #_name, .offset = \ 3913 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)} 3914 3915 static const struct mlx5_ib_counter cong_cnts[] = { 3916 INIT_CONG_COUNTER(rp_cnp_ignored), 3917 INIT_CONG_COUNTER(rp_cnp_handled), 3918 INIT_CONG_COUNTER(np_ecn_marked_roce_packets), 3919 INIT_CONG_COUNTER(np_cnp_sent), 3920 }; 3921 3922 static const struct mlx5_ib_counter extended_err_cnts[] = { 3923 INIT_Q_COUNTER(resp_local_length_error), 3924 INIT_Q_COUNTER(resp_cqe_error), 3925 INIT_Q_COUNTER(req_cqe_error), 3926 INIT_Q_COUNTER(req_remote_invalid_request), 3927 INIT_Q_COUNTER(req_remote_access_errors), 3928 INIT_Q_COUNTER(resp_remote_access_errors), 3929 INIT_Q_COUNTER(resp_cqe_flush_error), 3930 INIT_Q_COUNTER(req_cqe_flush_error), 3931 }; 3932 3933 static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev) 3934 { 3935 int i; 3936 3937 for (i = 0; i < dev->num_ports; i++) { 3938 if (dev->port[i].cnts.set_id) 3939 mlx5_core_dealloc_q_counter(dev->mdev, 3940 dev->port[i].cnts.set_id); 3941 kfree(dev->port[i].cnts.names); 3942 kfree(dev->port[i].cnts.offsets); 3943 } 3944 } 3945 3946 static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev, 3947 struct mlx5_ib_counters *cnts) 3948 { 3949 u32 num_counters; 3950 3951 num_counters = ARRAY_SIZE(basic_q_cnts); 3952 3953 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) 3954 num_counters += ARRAY_SIZE(out_of_seq_q_cnts); 3955 3956 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) 3957 num_counters += ARRAY_SIZE(retrans_q_cnts); 3958 3959 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) 3960 num_counters += ARRAY_SIZE(extended_err_cnts); 3961 3962 cnts->num_q_counters = num_counters; 3963 3964 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 3965 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts); 3966 num_counters += ARRAY_SIZE(cong_cnts); 3967 } 3968 3969 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL); 3970 if (!cnts->names) 3971 return -ENOMEM; 3972 3973 cnts->offsets = kcalloc(num_counters, 3974 sizeof(cnts->offsets), GFP_KERNEL); 3975 if (!cnts->offsets) 3976 goto err_names; 3977 3978 return 0; 3979 3980 err_names: 3981 kfree(cnts->names); 3982 cnts->names = NULL; 3983 return -ENOMEM; 3984 } 3985 3986 static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev, 3987 const char **names, 3988 size_t *offsets) 3989 { 3990 int i; 3991 int j = 0; 3992 3993 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) { 3994 names[j] = basic_q_cnts[i].name; 3995 offsets[j] = basic_q_cnts[i].offset; 3996 } 3997 3998 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) { 3999 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) { 4000 names[j] = out_of_seq_q_cnts[i].name; 4001 offsets[j] = out_of_seq_q_cnts[i].offset; 4002 } 4003 } 4004 4005 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) { 4006 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) { 4007 names[j] = retrans_q_cnts[i].name; 4008 offsets[j] = retrans_q_cnts[i].offset; 4009 } 4010 } 4011 4012 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) { 4013 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) { 4014 names[j] = extended_err_cnts[i].name; 4015 offsets[j] = extended_err_cnts[i].offset; 4016 } 4017 } 4018 4019 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 4020 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) { 4021 names[j] = cong_cnts[i].name; 4022 offsets[j] = cong_cnts[i].offset; 4023 } 4024 } 4025 } 4026 4027 static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev) 4028 { 4029 int err = 0; 4030 int i; 4031 4032 for (i = 0; i < dev->num_ports; i++) { 4033 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts); 4034 if (err) 4035 goto err_alloc; 4036 4037 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names, 4038 dev->port[i].cnts.offsets); 4039 4040 err = mlx5_core_alloc_q_counter(dev->mdev, 4041 &dev->port[i].cnts.set_id); 4042 if (err) { 4043 mlx5_ib_warn(dev, 4044 "couldn't allocate queue counter for port %d, err %d\n", 4045 i + 1, err); 4046 goto err_alloc; 4047 } 4048 dev->port[i].cnts.set_id_valid = true; 4049 } 4050 4051 return 0; 4052 4053 err_alloc: 4054 mlx5_ib_dealloc_counters(dev); 4055 return err; 4056 } 4057 4058 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev, 4059 u8 port_num) 4060 { 4061 struct mlx5_ib_dev *dev = to_mdev(ibdev); 4062 struct mlx5_ib_port *port = &dev->port[port_num - 1]; 4063 4064 /* We support only per port stats */ 4065 if (port_num == 0) 4066 return NULL; 4067 4068 return rdma_alloc_hw_stats_struct(port->cnts.names, 4069 port->cnts.num_q_counters + 4070 port->cnts.num_cong_counters, 4071 RDMA_HW_STATS_DEFAULT_LIFESPAN); 4072 } 4073 4074 static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev, 4075 struct mlx5_ib_port *port, 4076 struct rdma_hw_stats *stats) 4077 { 4078 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out); 4079 void *out; 4080 __be32 val; 4081 int ret, i; 4082 4083 out = kvzalloc(outlen, GFP_KERNEL); 4084 if (!out) 4085 return -ENOMEM; 4086 4087 ret = mlx5_core_query_q_counter(mdev, 4088 port->cnts.set_id, 0, 4089 out, outlen); 4090 if (ret) 4091 goto free; 4092 4093 for (i = 0; i < port->cnts.num_q_counters; i++) { 4094 val = *(__be32 *)(out + port->cnts.offsets[i]); 4095 stats->value[i] = (u64)be32_to_cpu(val); 4096 } 4097 4098 free: 4099 kvfree(out); 4100 return ret; 4101 } 4102 4103 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev, 4104 struct rdma_hw_stats *stats, 4105 u8 port_num, int index) 4106 { 4107 struct mlx5_ib_dev *dev = to_mdev(ibdev); 4108 struct mlx5_ib_port *port = &dev->port[port_num - 1]; 4109 struct mlx5_core_dev *mdev; 4110 int ret, num_counters; 4111 u8 mdev_port_num; 4112 4113 if (!stats) 4114 return -EINVAL; 4115 4116 num_counters = port->cnts.num_q_counters + port->cnts.num_cong_counters; 4117 4118 /* q_counters are per IB device, query the master mdev */ 4119 ret = mlx5_ib_query_q_counters(dev->mdev, port, stats); 4120 if (ret) 4121 return ret; 4122 4123 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 4124 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, 4125 &mdev_port_num); 4126 if (!mdev) { 4127 /* If port is not affiliated yet, its in down state 4128 * which doesn't have any counters yet, so it would be 4129 * zero. So no need to read from the HCA. 4130 */ 4131 goto done; 4132 } 4133 ret = mlx5_lag_query_cong_counters(dev->mdev, 4134 stats->value + 4135 port->cnts.num_q_counters, 4136 port->cnts.num_cong_counters, 4137 port->cnts.offsets + 4138 port->cnts.num_q_counters); 4139 4140 mlx5_ib_put_native_port_mdev(dev, port_num); 4141 if (ret) 4142 return ret; 4143 } 4144 4145 done: 4146 return num_counters; 4147 } 4148 4149 static void mlx5_ib_free_rdma_netdev(struct net_device *netdev) 4150 { 4151 return mlx5_rdma_netdev_free(netdev); 4152 } 4153 4154 static struct net_device* 4155 mlx5_ib_alloc_rdma_netdev(struct ib_device *hca, 4156 u8 port_num, 4157 enum rdma_netdev_t type, 4158 const char *name, 4159 unsigned char name_assign_type, 4160 void (*setup)(struct net_device *)) 4161 { 4162 struct net_device *netdev; 4163 struct rdma_netdev *rn; 4164 4165 if (type != RDMA_NETDEV_IPOIB) 4166 return ERR_PTR(-EOPNOTSUPP); 4167 4168 netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca, 4169 name, setup); 4170 if (likely(!IS_ERR_OR_NULL(netdev))) { 4171 rn = netdev_priv(netdev); 4172 rn->free_rdma_netdev = mlx5_ib_free_rdma_netdev; 4173 } 4174 return netdev; 4175 } 4176 4177 static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev) 4178 { 4179 if (!dev->delay_drop.dbg) 4180 return; 4181 debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs); 4182 kfree(dev->delay_drop.dbg); 4183 dev->delay_drop.dbg = NULL; 4184 } 4185 4186 static void cancel_delay_drop(struct mlx5_ib_dev *dev) 4187 { 4188 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4189 return; 4190 4191 cancel_work_sync(&dev->delay_drop.delay_drop_work); 4192 delay_drop_debugfs_cleanup(dev); 4193 } 4194 4195 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf, 4196 size_t count, loff_t *pos) 4197 { 4198 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 4199 char lbuf[20]; 4200 int len; 4201 4202 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout); 4203 return simple_read_from_buffer(buf, count, pos, lbuf, len); 4204 } 4205 4206 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf, 4207 size_t count, loff_t *pos) 4208 { 4209 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 4210 u32 timeout; 4211 u32 var; 4212 4213 if (kstrtouint_from_user(buf, count, 0, &var)) 4214 return -EFAULT; 4215 4216 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 4217 1000); 4218 if (timeout != var) 4219 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n", 4220 timeout); 4221 4222 delay_drop->timeout = timeout; 4223 4224 return count; 4225 } 4226 4227 static const struct file_operations fops_delay_drop_timeout = { 4228 .owner = THIS_MODULE, 4229 .open = simple_open, 4230 .write = delay_drop_timeout_write, 4231 .read = delay_drop_timeout_read, 4232 }; 4233 4234 static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev) 4235 { 4236 struct mlx5_ib_dbg_delay_drop *dbg; 4237 4238 if (!mlx5_debugfs_root) 4239 return 0; 4240 4241 dbg = kzalloc(sizeof(*dbg), GFP_KERNEL); 4242 if (!dbg) 4243 return -ENOMEM; 4244 4245 dev->delay_drop.dbg = dbg; 4246 4247 dbg->dir_debugfs = 4248 debugfs_create_dir("delay_drop", 4249 dev->mdev->priv.dbg_root); 4250 if (!dbg->dir_debugfs) 4251 goto out_debugfs; 4252 4253 dbg->events_cnt_debugfs = 4254 debugfs_create_atomic_t("num_timeout_events", 0400, 4255 dbg->dir_debugfs, 4256 &dev->delay_drop.events_cnt); 4257 if (!dbg->events_cnt_debugfs) 4258 goto out_debugfs; 4259 4260 dbg->rqs_cnt_debugfs = 4261 debugfs_create_atomic_t("num_rqs", 0400, 4262 dbg->dir_debugfs, 4263 &dev->delay_drop.rqs_cnt); 4264 if (!dbg->rqs_cnt_debugfs) 4265 goto out_debugfs; 4266 4267 dbg->timeout_debugfs = 4268 debugfs_create_file("timeout", 0600, 4269 dbg->dir_debugfs, 4270 &dev->delay_drop, 4271 &fops_delay_drop_timeout); 4272 if (!dbg->timeout_debugfs) 4273 goto out_debugfs; 4274 4275 return 0; 4276 4277 out_debugfs: 4278 delay_drop_debugfs_cleanup(dev); 4279 return -ENOMEM; 4280 } 4281 4282 static void init_delay_drop(struct mlx5_ib_dev *dev) 4283 { 4284 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4285 return; 4286 4287 mutex_init(&dev->delay_drop.lock); 4288 dev->delay_drop.dev = dev; 4289 dev->delay_drop.activate = false; 4290 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000; 4291 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler); 4292 atomic_set(&dev->delay_drop.rqs_cnt, 0); 4293 atomic_set(&dev->delay_drop.events_cnt, 0); 4294 4295 if (delay_drop_debugfs_init(dev)) 4296 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n"); 4297 } 4298 4299 static const struct cpumask * 4300 mlx5_ib_get_vector_affinity(struct ib_device *ibdev, int comp_vector) 4301 { 4302 struct mlx5_ib_dev *dev = to_mdev(ibdev); 4303 4304 return mlx5_get_vector_affinity(dev->mdev, comp_vector); 4305 } 4306 4307 /* The mlx5_ib_multiport_mutex should be held when calling this function */ 4308 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev, 4309 struct mlx5_ib_multiport_info *mpi) 4310 { 4311 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 4312 struct mlx5_ib_port *port = &ibdev->port[port_num]; 4313 int comps; 4314 int err; 4315 int i; 4316 4317 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num); 4318 4319 spin_lock(&port->mp.mpi_lock); 4320 if (!mpi->ibdev) { 4321 spin_unlock(&port->mp.mpi_lock); 4322 return; 4323 } 4324 mpi->ibdev = NULL; 4325 4326 spin_unlock(&port->mp.mpi_lock); 4327 mlx5_remove_netdev_notifier(ibdev, port_num); 4328 spin_lock(&port->mp.mpi_lock); 4329 4330 comps = mpi->mdev_refcnt; 4331 if (comps) { 4332 mpi->unaffiliate = true; 4333 init_completion(&mpi->unref_comp); 4334 spin_unlock(&port->mp.mpi_lock); 4335 4336 for (i = 0; i < comps; i++) 4337 wait_for_completion(&mpi->unref_comp); 4338 4339 spin_lock(&port->mp.mpi_lock); 4340 mpi->unaffiliate = false; 4341 } 4342 4343 port->mp.mpi = NULL; 4344 4345 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 4346 4347 spin_unlock(&port->mp.mpi_lock); 4348 4349 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev); 4350 4351 mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1); 4352 /* Log an error, still needed to cleanup the pointers and add 4353 * it back to the list. 4354 */ 4355 if (err) 4356 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n", 4357 port_num + 1); 4358 4359 ibdev->roce[port_num].last_port_state = IB_PORT_DOWN; 4360 } 4361 4362 /* The mlx5_ib_multiport_mutex should be held when calling this function */ 4363 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev, 4364 struct mlx5_ib_multiport_info *mpi) 4365 { 4366 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 4367 int err; 4368 4369 spin_lock(&ibdev->port[port_num].mp.mpi_lock); 4370 if (ibdev->port[port_num].mp.mpi) { 4371 mlx5_ib_warn(ibdev, "port %d already affiliated.\n", 4372 port_num + 1); 4373 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 4374 return false; 4375 } 4376 4377 ibdev->port[port_num].mp.mpi = mpi; 4378 mpi->ibdev = ibdev; 4379 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 4380 4381 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev); 4382 if (err) 4383 goto unbind; 4384 4385 err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev)); 4386 if (err) 4387 goto unbind; 4388 4389 err = mlx5_add_netdev_notifier(ibdev, port_num); 4390 if (err) { 4391 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n", 4392 port_num + 1); 4393 goto unbind; 4394 } 4395 4396 err = mlx5_ib_init_cong_debugfs(ibdev, port_num); 4397 if (err) 4398 goto unbind; 4399 4400 return true; 4401 4402 unbind: 4403 mlx5_ib_unbind_slave_port(ibdev, mpi); 4404 return false; 4405 } 4406 4407 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev) 4408 { 4409 int port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4410 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 4411 port_num + 1); 4412 struct mlx5_ib_multiport_info *mpi; 4413 int err; 4414 int i; 4415 4416 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 4417 return 0; 4418 4419 err = mlx5_query_nic_vport_system_image_guid(dev->mdev, 4420 &dev->sys_image_guid); 4421 if (err) 4422 return err; 4423 4424 err = mlx5_nic_vport_enable_roce(dev->mdev); 4425 if (err) 4426 return err; 4427 4428 mutex_lock(&mlx5_ib_multiport_mutex); 4429 for (i = 0; i < dev->num_ports; i++) { 4430 bool bound = false; 4431 4432 /* build a stub multiport info struct for the native port. */ 4433 if (i == port_num) { 4434 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 4435 if (!mpi) { 4436 mutex_unlock(&mlx5_ib_multiport_mutex); 4437 mlx5_nic_vport_disable_roce(dev->mdev); 4438 return -ENOMEM; 4439 } 4440 4441 mpi->is_master = true; 4442 mpi->mdev = dev->mdev; 4443 mpi->sys_image_guid = dev->sys_image_guid; 4444 dev->port[i].mp.mpi = mpi; 4445 mpi->ibdev = dev; 4446 mpi = NULL; 4447 continue; 4448 } 4449 4450 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list, 4451 list) { 4452 if (dev->sys_image_guid == mpi->sys_image_guid && 4453 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) { 4454 bound = mlx5_ib_bind_slave_port(dev, mpi); 4455 } 4456 4457 if (bound) { 4458 dev_dbg(&mpi->mdev->pdev->dev, "removing port from unaffiliated list.\n"); 4459 mlx5_ib_dbg(dev, "port %d bound\n", i + 1); 4460 list_del(&mpi->list); 4461 break; 4462 } 4463 } 4464 if (!bound) { 4465 get_port_caps(dev, i + 1); 4466 mlx5_ib_dbg(dev, "no free port found for port %d\n", 4467 i + 1); 4468 } 4469 } 4470 4471 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list); 4472 mutex_unlock(&mlx5_ib_multiport_mutex); 4473 return err; 4474 } 4475 4476 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev) 4477 { 4478 int port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4479 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 4480 port_num + 1); 4481 int i; 4482 4483 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 4484 return; 4485 4486 mutex_lock(&mlx5_ib_multiport_mutex); 4487 for (i = 0; i < dev->num_ports; i++) { 4488 if (dev->port[i].mp.mpi) { 4489 /* Destroy the native port stub */ 4490 if (i == port_num) { 4491 kfree(dev->port[i].mp.mpi); 4492 dev->port[i].mp.mpi = NULL; 4493 } else { 4494 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1); 4495 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi); 4496 } 4497 } 4498 } 4499 4500 mlx5_ib_dbg(dev, "removing from devlist\n"); 4501 list_del(&dev->ib_dev_list); 4502 mutex_unlock(&mlx5_ib_multiport_mutex); 4503 4504 mlx5_nic_vport_disable_roce(dev->mdev); 4505 } 4506 4507 static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev) 4508 { 4509 mlx5_ib_cleanup_multiport_master(dev); 4510 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 4511 cleanup_srcu_struct(&dev->mr_srcu); 4512 #endif 4513 kfree(dev->port); 4514 } 4515 4516 static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev) 4517 { 4518 struct mlx5_core_dev *mdev = dev->mdev; 4519 const char *name; 4520 int err; 4521 int i; 4522 4523 dev->port = kcalloc(dev->num_ports, sizeof(*dev->port), 4524 GFP_KERNEL); 4525 if (!dev->port) 4526 return -ENOMEM; 4527 4528 for (i = 0; i < dev->num_ports; i++) { 4529 spin_lock_init(&dev->port[i].mp.mpi_lock); 4530 rwlock_init(&dev->roce[i].netdev_lock); 4531 } 4532 4533 err = mlx5_ib_init_multiport_master(dev); 4534 if (err) 4535 goto err_free_port; 4536 4537 if (!mlx5_core_mp_enabled(mdev)) { 4538 int i; 4539 4540 for (i = 1; i <= dev->num_ports; i++) { 4541 err = get_port_caps(dev, i); 4542 if (err) 4543 break; 4544 } 4545 } else { 4546 err = get_port_caps(dev, mlx5_core_native_port_num(mdev)); 4547 } 4548 if (err) 4549 goto err_mp; 4550 4551 if (mlx5_use_mad_ifc(dev)) 4552 get_ext_port_caps(dev); 4553 4554 if (!mlx5_lag_is_active(mdev)) 4555 name = "mlx5_%d"; 4556 else 4557 name = "mlx5_bond_%d"; 4558 4559 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX); 4560 dev->ib_dev.owner = THIS_MODULE; 4561 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 4562 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 4563 dev->ib_dev.phys_port_cnt = dev->num_ports; 4564 dev->ib_dev.num_comp_vectors = 4565 dev->mdev->priv.eq_table.num_comp_vectors; 4566 dev->ib_dev.dev.parent = &mdev->pdev->dev; 4567 4568 mutex_init(&dev->flow_db.lock); 4569 mutex_init(&dev->cap_mask_mutex); 4570 INIT_LIST_HEAD(&dev->qp_list); 4571 spin_lock_init(&dev->reset_flow_resource_lock); 4572 4573 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 4574 err = init_srcu_struct(&dev->mr_srcu); 4575 if (err) 4576 goto err_free_port; 4577 #endif 4578 4579 return 0; 4580 err_mp: 4581 mlx5_ib_cleanup_multiport_master(dev); 4582 4583 err_free_port: 4584 kfree(dev->port); 4585 4586 return -ENOMEM; 4587 } 4588 4589 static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev) 4590 { 4591 struct mlx5_core_dev *mdev = dev->mdev; 4592 int err; 4593 4594 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION; 4595 dev->ib_dev.uverbs_cmd_mask = 4596 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | 4597 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | 4598 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | 4599 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | 4600 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | 4601 (1ull << IB_USER_VERBS_CMD_CREATE_AH) | 4602 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) | 4603 (1ull << IB_USER_VERBS_CMD_REG_MR) | 4604 (1ull << IB_USER_VERBS_CMD_REREG_MR) | 4605 (1ull << IB_USER_VERBS_CMD_DEREG_MR) | 4606 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 4607 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | 4608 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) | 4609 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | 4610 (1ull << IB_USER_VERBS_CMD_CREATE_QP) | 4611 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | 4612 (1ull << IB_USER_VERBS_CMD_QUERY_QP) | 4613 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | 4614 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) | 4615 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) | 4616 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | 4617 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | 4618 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | 4619 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | 4620 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) | 4621 (1ull << IB_USER_VERBS_CMD_OPEN_QP); 4622 dev->ib_dev.uverbs_ex_cmd_mask = 4623 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) | 4624 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) | 4625 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) | 4626 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP) | 4627 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ); 4628 4629 dev->ib_dev.query_device = mlx5_ib_query_device; 4630 dev->ib_dev.query_port = mlx5_ib_query_port; 4631 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer; 4632 dev->ib_dev.query_gid = mlx5_ib_query_gid; 4633 dev->ib_dev.add_gid = mlx5_ib_add_gid; 4634 dev->ib_dev.del_gid = mlx5_ib_del_gid; 4635 dev->ib_dev.query_pkey = mlx5_ib_query_pkey; 4636 dev->ib_dev.modify_device = mlx5_ib_modify_device; 4637 dev->ib_dev.modify_port = mlx5_ib_modify_port; 4638 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext; 4639 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext; 4640 dev->ib_dev.mmap = mlx5_ib_mmap; 4641 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd; 4642 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd; 4643 dev->ib_dev.create_ah = mlx5_ib_create_ah; 4644 dev->ib_dev.query_ah = mlx5_ib_query_ah; 4645 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah; 4646 dev->ib_dev.create_srq = mlx5_ib_create_srq; 4647 dev->ib_dev.modify_srq = mlx5_ib_modify_srq; 4648 dev->ib_dev.query_srq = mlx5_ib_query_srq; 4649 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq; 4650 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv; 4651 dev->ib_dev.create_qp = mlx5_ib_create_qp; 4652 dev->ib_dev.modify_qp = mlx5_ib_modify_qp; 4653 dev->ib_dev.query_qp = mlx5_ib_query_qp; 4654 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp; 4655 dev->ib_dev.post_send = mlx5_ib_post_send; 4656 dev->ib_dev.post_recv = mlx5_ib_post_recv; 4657 dev->ib_dev.create_cq = mlx5_ib_create_cq; 4658 dev->ib_dev.modify_cq = mlx5_ib_modify_cq; 4659 dev->ib_dev.resize_cq = mlx5_ib_resize_cq; 4660 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq; 4661 dev->ib_dev.poll_cq = mlx5_ib_poll_cq; 4662 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq; 4663 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr; 4664 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr; 4665 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr; 4666 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr; 4667 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach; 4668 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach; 4669 dev->ib_dev.process_mad = mlx5_ib_process_mad; 4670 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr; 4671 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg; 4672 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status; 4673 dev->ib_dev.get_port_immutable = mlx5_port_immutable; 4674 dev->ib_dev.get_dev_fw_str = get_dev_fw_str; 4675 dev->ib_dev.get_vector_affinity = mlx5_ib_get_vector_affinity; 4676 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads)) 4677 dev->ib_dev.alloc_rdma_netdev = mlx5_ib_alloc_rdma_netdev; 4678 4679 if (mlx5_core_is_pf(mdev)) { 4680 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config; 4681 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state; 4682 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats; 4683 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid; 4684 } 4685 4686 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext; 4687 4688 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence)); 4689 4690 if (MLX5_CAP_GEN(mdev, imaicl)) { 4691 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw; 4692 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw; 4693 dev->ib_dev.uverbs_cmd_mask |= 4694 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) | 4695 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW); 4696 } 4697 4698 if (MLX5_CAP_GEN(mdev, xrc)) { 4699 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd; 4700 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd; 4701 dev->ib_dev.uverbs_cmd_mask |= 4702 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) | 4703 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD); 4704 } 4705 4706 dev->ib_dev.create_flow = mlx5_ib_create_flow; 4707 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow; 4708 dev->ib_dev.uverbs_ex_cmd_mask |= 4709 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) | 4710 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW); 4711 4712 err = init_node_data(dev); 4713 if (err) 4714 return err; 4715 4716 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && 4717 MLX5_CAP_GEN(dev->mdev, disable_local_lb)) 4718 mutex_init(&dev->lb_mutex); 4719 4720 return 0; 4721 } 4722 4723 static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev) 4724 { 4725 struct mlx5_core_dev *mdev = dev->mdev; 4726 enum rdma_link_layer ll; 4727 int port_type_cap; 4728 u8 port_num; 4729 int err; 4730 int i; 4731 4732 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4733 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4734 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4735 4736 if (ll == IB_LINK_LAYER_ETHERNET) { 4737 for (i = 0; i < dev->num_ports; i++) { 4738 dev->roce[i].dev = dev; 4739 dev->roce[i].native_port_num = i + 1; 4740 dev->roce[i].last_port_state = IB_PORT_DOWN; 4741 } 4742 4743 dev->ib_dev.get_netdev = mlx5_ib_get_netdev; 4744 dev->ib_dev.create_wq = mlx5_ib_create_wq; 4745 dev->ib_dev.modify_wq = mlx5_ib_modify_wq; 4746 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq; 4747 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table; 4748 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table; 4749 dev->ib_dev.uverbs_ex_cmd_mask |= 4750 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) | 4751 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) | 4752 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) | 4753 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) | 4754 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL); 4755 err = mlx5_enable_eth(dev, port_num); 4756 if (err) 4757 return err; 4758 } 4759 4760 return 0; 4761 } 4762 4763 static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev) 4764 { 4765 struct mlx5_core_dev *mdev = dev->mdev; 4766 enum rdma_link_layer ll; 4767 int port_type_cap; 4768 u8 port_num; 4769 4770 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4771 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4772 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4773 4774 if (ll == IB_LINK_LAYER_ETHERNET) { 4775 mlx5_disable_eth(dev); 4776 mlx5_remove_netdev_notifier(dev, port_num); 4777 } 4778 } 4779 4780 static int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev) 4781 { 4782 return create_dev_resources(&dev->devr); 4783 } 4784 4785 static void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev) 4786 { 4787 destroy_dev_resources(&dev->devr); 4788 } 4789 4790 static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev) 4791 { 4792 mlx5_ib_internal_fill_odp_caps(dev); 4793 4794 return mlx5_ib_odp_init_one(dev); 4795 } 4796 4797 static int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev) 4798 { 4799 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) { 4800 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats; 4801 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats; 4802 4803 return mlx5_ib_alloc_counters(dev); 4804 } 4805 4806 return 0; 4807 } 4808 4809 static void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev) 4810 { 4811 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) 4812 mlx5_ib_dealloc_counters(dev); 4813 } 4814 4815 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev) 4816 { 4817 return mlx5_ib_init_cong_debugfs(dev, 4818 mlx5_core_native_port_num(dev->mdev) - 1); 4819 } 4820 4821 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev) 4822 { 4823 mlx5_ib_cleanup_cong_debugfs(dev, 4824 mlx5_core_native_port_num(dev->mdev) - 1); 4825 } 4826 4827 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev) 4828 { 4829 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev); 4830 if (!dev->mdev->priv.uar) 4831 return -ENOMEM; 4832 return 0; 4833 } 4834 4835 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev) 4836 { 4837 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar); 4838 } 4839 4840 static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev) 4841 { 4842 int err; 4843 4844 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false); 4845 if (err) 4846 return err; 4847 4848 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true); 4849 if (err) 4850 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 4851 4852 return err; 4853 } 4854 4855 static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev) 4856 { 4857 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 4858 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4859 } 4860 4861 static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev) 4862 { 4863 return ib_register_device(&dev->ib_dev, NULL); 4864 } 4865 4866 static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev) 4867 { 4868 ib_unregister_device(&dev->ib_dev); 4869 } 4870 4871 static int mlx5_ib_stage_umr_res_init(struct mlx5_ib_dev *dev) 4872 { 4873 return create_umr_res(dev); 4874 } 4875 4876 static void mlx5_ib_stage_umr_res_cleanup(struct mlx5_ib_dev *dev) 4877 { 4878 destroy_umrc_res(dev); 4879 } 4880 4881 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev) 4882 { 4883 init_delay_drop(dev); 4884 4885 return 0; 4886 } 4887 4888 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev) 4889 { 4890 cancel_delay_drop(dev); 4891 } 4892 4893 static int mlx5_ib_stage_class_attr_init(struct mlx5_ib_dev *dev) 4894 { 4895 int err; 4896 int i; 4897 4898 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) { 4899 err = device_create_file(&dev->ib_dev.dev, 4900 mlx5_class_attributes[i]); 4901 if (err) 4902 return err; 4903 } 4904 4905 return 0; 4906 } 4907 4908 static void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 4909 const struct mlx5_ib_profile *profile, 4910 int stage) 4911 { 4912 /* Number of stages to cleanup */ 4913 while (stage) { 4914 stage--; 4915 if (profile->stage[stage].cleanup) 4916 profile->stage[stage].cleanup(dev); 4917 } 4918 4919 ib_dealloc_device((struct ib_device *)dev); 4920 } 4921 4922 static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev, u8 port_num); 4923 4924 static void *__mlx5_ib_add(struct mlx5_core_dev *mdev, 4925 const struct mlx5_ib_profile *profile) 4926 { 4927 struct mlx5_ib_dev *dev; 4928 int err; 4929 int i; 4930 4931 printk_once(KERN_INFO "%s", mlx5_version); 4932 4933 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev)); 4934 if (!dev) 4935 return NULL; 4936 4937 dev->mdev = mdev; 4938 dev->num_ports = max(MLX5_CAP_GEN(mdev, num_ports), 4939 MLX5_CAP_GEN(mdev, num_vhca_ports)); 4940 4941 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) { 4942 if (profile->stage[i].init) { 4943 err = profile->stage[i].init(dev); 4944 if (err) 4945 goto err_out; 4946 } 4947 } 4948 4949 dev->profile = profile; 4950 dev->ib_active = true; 4951 4952 return dev; 4953 4954 err_out: 4955 __mlx5_ib_remove(dev, profile, i); 4956 4957 return NULL; 4958 } 4959 4960 static const struct mlx5_ib_profile pf_profile = { 4961 STAGE_CREATE(MLX5_IB_STAGE_INIT, 4962 mlx5_ib_stage_init_init, 4963 mlx5_ib_stage_init_cleanup), 4964 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 4965 mlx5_ib_stage_caps_init, 4966 NULL), 4967 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 4968 mlx5_ib_stage_roce_init, 4969 mlx5_ib_stage_roce_cleanup), 4970 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 4971 mlx5_ib_stage_dev_res_init, 4972 mlx5_ib_stage_dev_res_cleanup), 4973 STAGE_CREATE(MLX5_IB_STAGE_ODP, 4974 mlx5_ib_stage_odp_init, 4975 NULL), 4976 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 4977 mlx5_ib_stage_counters_init, 4978 mlx5_ib_stage_counters_cleanup), 4979 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 4980 mlx5_ib_stage_cong_debugfs_init, 4981 mlx5_ib_stage_cong_debugfs_cleanup), 4982 STAGE_CREATE(MLX5_IB_STAGE_UAR, 4983 mlx5_ib_stage_uar_init, 4984 mlx5_ib_stage_uar_cleanup), 4985 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 4986 mlx5_ib_stage_bfrag_init, 4987 mlx5_ib_stage_bfrag_cleanup), 4988 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 4989 mlx5_ib_stage_ib_reg_init, 4990 mlx5_ib_stage_ib_reg_cleanup), 4991 STAGE_CREATE(MLX5_IB_STAGE_UMR_RESOURCES, 4992 mlx5_ib_stage_umr_res_init, 4993 mlx5_ib_stage_umr_res_cleanup), 4994 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP, 4995 mlx5_ib_stage_delay_drop_init, 4996 mlx5_ib_stage_delay_drop_cleanup), 4997 STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR, 4998 mlx5_ib_stage_class_attr_init, 4999 NULL), 5000 }; 5001 5002 static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev, u8 port_num) 5003 { 5004 struct mlx5_ib_multiport_info *mpi; 5005 struct mlx5_ib_dev *dev; 5006 bool bound = false; 5007 int err; 5008 5009 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 5010 if (!mpi) 5011 return NULL; 5012 5013 mpi->mdev = mdev; 5014 5015 err = mlx5_query_nic_vport_system_image_guid(mdev, 5016 &mpi->sys_image_guid); 5017 if (err) { 5018 kfree(mpi); 5019 return NULL; 5020 } 5021 5022 mutex_lock(&mlx5_ib_multiport_mutex); 5023 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) { 5024 if (dev->sys_image_guid == mpi->sys_image_guid) 5025 bound = mlx5_ib_bind_slave_port(dev, mpi); 5026 5027 if (bound) { 5028 rdma_roce_rescan_device(&dev->ib_dev); 5029 break; 5030 } 5031 } 5032 5033 if (!bound) { 5034 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 5035 dev_dbg(&mdev->pdev->dev, "no suitable IB device found to bind to, added to unaffiliated list.\n"); 5036 } else { 5037 mlx5_ib_dbg(dev, "bound port %u\n", port_num + 1); 5038 } 5039 mutex_unlock(&mlx5_ib_multiport_mutex); 5040 5041 return mpi; 5042 } 5043 5044 static void *mlx5_ib_add(struct mlx5_core_dev *mdev) 5045 { 5046 enum rdma_link_layer ll; 5047 int port_type_cap; 5048 5049 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 5050 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 5051 5052 if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET) { 5053 u8 port_num = mlx5_core_native_port_num(mdev) - 1; 5054 5055 return mlx5_ib_add_slave_port(mdev, port_num); 5056 } 5057 5058 return __mlx5_ib_add(mdev, &pf_profile); 5059 } 5060 5061 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context) 5062 { 5063 struct mlx5_ib_multiport_info *mpi; 5064 struct mlx5_ib_dev *dev; 5065 5066 if (mlx5_core_is_mp_slave(mdev)) { 5067 mpi = context; 5068 mutex_lock(&mlx5_ib_multiport_mutex); 5069 if (mpi->ibdev) 5070 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi); 5071 list_del(&mpi->list); 5072 mutex_unlock(&mlx5_ib_multiport_mutex); 5073 return; 5074 } 5075 5076 dev = context; 5077 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX); 5078 } 5079 5080 static struct mlx5_interface mlx5_ib_interface = { 5081 .add = mlx5_ib_add, 5082 .remove = mlx5_ib_remove, 5083 .event = mlx5_ib_event, 5084 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 5085 .pfault = mlx5_ib_pfault, 5086 #endif 5087 .protocol = MLX5_INTERFACE_PROTOCOL_IB, 5088 }; 5089 5090 static int __init mlx5_ib_init(void) 5091 { 5092 int err; 5093 5094 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0); 5095 if (!mlx5_ib_event_wq) 5096 return -ENOMEM; 5097 5098 mlx5_ib_odp_init(); 5099 5100 err = mlx5_register_interface(&mlx5_ib_interface); 5101 5102 return err; 5103 } 5104 5105 static void __exit mlx5_ib_cleanup(void) 5106 { 5107 mlx5_unregister_interface(&mlx5_ib_interface); 5108 destroy_workqueue(mlx5_ib_event_wq); 5109 } 5110 5111 module_init(mlx5_ib_init); 5112 module_exit(mlx5_ib_cleanup); 5113