1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 /* 3 * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved. 4 * Copyright (c) 2020, Intel Corporation. All rights reserved. 5 */ 6 7 #include <linux/debugfs.h> 8 #include <linux/highmem.h> 9 #include <linux/module.h> 10 #include <linux/init.h> 11 #include <linux/errno.h> 12 #include <linux/pci.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/slab.h> 15 #include <linux/bitmap.h> 16 #include <linux/sched.h> 17 #include <linux/sched/mm.h> 18 #include <linux/sched/task.h> 19 #include <linux/delay.h> 20 #include <rdma/ib_user_verbs.h> 21 #include <rdma/ib_addr.h> 22 #include <rdma/ib_cache.h> 23 #include <linux/mlx5/port.h> 24 #include <linux/mlx5/vport.h> 25 #include <linux/mlx5/fs.h> 26 #include <linux/mlx5/eswitch.h> 27 #include <linux/list.h> 28 #include <rdma/ib_smi.h> 29 #include <rdma/ib_umem.h> 30 #include <rdma/lag.h> 31 #include <linux/in.h> 32 #include <linux/etherdevice.h> 33 #include "mlx5_ib.h" 34 #include "ib_rep.h" 35 #include "cmd.h" 36 #include "devx.h" 37 #include "fs.h" 38 #include "srq.h" 39 #include "qp.h" 40 #include "wr.h" 41 #include "restrack.h" 42 #include "counters.h" 43 #include <linux/mlx5/accel.h> 44 #include <rdma/uverbs_std_types.h> 45 #include <rdma/mlx5_user_ioctl_verbs.h> 46 #include <rdma/mlx5_user_ioctl_cmds.h> 47 #include <rdma/ib_umem_odp.h> 48 49 #define UVERBS_MODULE_NAME mlx5_ib 50 #include <rdma/uverbs_named_ioctl.h> 51 52 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 53 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) IB driver"); 54 MODULE_LICENSE("Dual BSD/GPL"); 55 56 struct mlx5_ib_event_work { 57 struct work_struct work; 58 union { 59 struct mlx5_ib_dev *dev; 60 struct mlx5_ib_multiport_info *mpi; 61 }; 62 bool is_slave; 63 unsigned int event; 64 void *param; 65 }; 66 67 enum { 68 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 69 }; 70 71 static struct workqueue_struct *mlx5_ib_event_wq; 72 static LIST_HEAD(mlx5_ib_unaffiliated_port_list); 73 static LIST_HEAD(mlx5_ib_dev_list); 74 /* 75 * This mutex should be held when accessing either of the above lists 76 */ 77 static DEFINE_MUTEX(mlx5_ib_multiport_mutex); 78 79 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi) 80 { 81 struct mlx5_ib_dev *dev; 82 83 mutex_lock(&mlx5_ib_multiport_mutex); 84 dev = mpi->ibdev; 85 mutex_unlock(&mlx5_ib_multiport_mutex); 86 return dev; 87 } 88 89 static enum rdma_link_layer 90 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 91 { 92 switch (port_type_cap) { 93 case MLX5_CAP_PORT_TYPE_IB: 94 return IB_LINK_LAYER_INFINIBAND; 95 case MLX5_CAP_PORT_TYPE_ETH: 96 return IB_LINK_LAYER_ETHERNET; 97 default: 98 return IB_LINK_LAYER_UNSPECIFIED; 99 } 100 } 101 102 static enum rdma_link_layer 103 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num) 104 { 105 struct mlx5_ib_dev *dev = to_mdev(device); 106 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 107 108 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 109 } 110 111 static int get_port_state(struct ib_device *ibdev, 112 u8 port_num, 113 enum ib_port_state *state) 114 { 115 struct ib_port_attr attr; 116 int ret; 117 118 memset(&attr, 0, sizeof(attr)); 119 ret = ibdev->ops.query_port(ibdev, port_num, &attr); 120 if (!ret) 121 *state = attr.state; 122 return ret; 123 } 124 125 static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev, 126 struct net_device *ndev, 127 u8 *port_num) 128 { 129 struct mlx5_eswitch *esw = dev->mdev->priv.eswitch; 130 struct net_device *rep_ndev; 131 struct mlx5_ib_port *port; 132 int i; 133 134 for (i = 0; i < dev->num_ports; i++) { 135 port = &dev->port[i]; 136 if (!port->rep) 137 continue; 138 139 read_lock(&port->roce.netdev_lock); 140 rep_ndev = mlx5_ib_get_rep_netdev(esw, 141 port->rep->vport); 142 if (rep_ndev == ndev) { 143 read_unlock(&port->roce.netdev_lock); 144 *port_num = i + 1; 145 return &port->roce; 146 } 147 read_unlock(&port->roce.netdev_lock); 148 } 149 150 return NULL; 151 } 152 153 static int mlx5_netdev_event(struct notifier_block *this, 154 unsigned long event, void *ptr) 155 { 156 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb); 157 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 158 u8 port_num = roce->native_port_num; 159 struct mlx5_core_dev *mdev; 160 struct mlx5_ib_dev *ibdev; 161 162 ibdev = roce->dev; 163 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 164 if (!mdev) 165 return NOTIFY_DONE; 166 167 switch (event) { 168 case NETDEV_REGISTER: 169 /* Should already be registered during the load */ 170 if (ibdev->is_rep) 171 break; 172 write_lock(&roce->netdev_lock); 173 if (ndev->dev.parent == mdev->device) 174 roce->netdev = ndev; 175 write_unlock(&roce->netdev_lock); 176 break; 177 178 case NETDEV_UNREGISTER: 179 /* In case of reps, ib device goes away before the netdevs */ 180 write_lock(&roce->netdev_lock); 181 if (roce->netdev == ndev) 182 roce->netdev = NULL; 183 write_unlock(&roce->netdev_lock); 184 break; 185 186 case NETDEV_CHANGE: 187 case NETDEV_UP: 188 case NETDEV_DOWN: { 189 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev); 190 struct net_device *upper = NULL; 191 192 if (lag_ndev) { 193 upper = netdev_master_upper_dev_get(lag_ndev); 194 dev_put(lag_ndev); 195 } 196 197 if (ibdev->is_rep) 198 roce = mlx5_get_rep_roce(ibdev, ndev, &port_num); 199 if (!roce) 200 return NOTIFY_DONE; 201 if ((upper == ndev || (!upper && ndev == roce->netdev)) 202 && ibdev->ib_active) { 203 struct ib_event ibev = { }; 204 enum ib_port_state port_state; 205 206 if (get_port_state(&ibdev->ib_dev, port_num, 207 &port_state)) 208 goto done; 209 210 if (roce->last_port_state == port_state) 211 goto done; 212 213 roce->last_port_state = port_state; 214 ibev.device = &ibdev->ib_dev; 215 if (port_state == IB_PORT_DOWN) 216 ibev.event = IB_EVENT_PORT_ERR; 217 else if (port_state == IB_PORT_ACTIVE) 218 ibev.event = IB_EVENT_PORT_ACTIVE; 219 else 220 goto done; 221 222 ibev.element.port_num = port_num; 223 ib_dispatch_event(&ibev); 224 } 225 break; 226 } 227 228 default: 229 break; 230 } 231 done: 232 mlx5_ib_put_native_port_mdev(ibdev, port_num); 233 return NOTIFY_DONE; 234 } 235 236 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device, 237 u8 port_num) 238 { 239 struct mlx5_ib_dev *ibdev = to_mdev(device); 240 struct net_device *ndev; 241 struct mlx5_core_dev *mdev; 242 243 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 244 if (!mdev) 245 return NULL; 246 247 ndev = mlx5_lag_get_roce_netdev(mdev); 248 if (ndev) 249 goto out; 250 251 /* Ensure ndev does not disappear before we invoke dev_hold() 252 */ 253 read_lock(&ibdev->port[port_num - 1].roce.netdev_lock); 254 ndev = ibdev->port[port_num - 1].roce.netdev; 255 if (ndev) 256 dev_hold(ndev); 257 read_unlock(&ibdev->port[port_num - 1].roce.netdev_lock); 258 259 out: 260 mlx5_ib_put_native_port_mdev(ibdev, port_num); 261 return ndev; 262 } 263 264 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev, 265 u8 ib_port_num, 266 u8 *native_port_num) 267 { 268 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 269 ib_port_num); 270 struct mlx5_core_dev *mdev = NULL; 271 struct mlx5_ib_multiport_info *mpi; 272 struct mlx5_ib_port *port; 273 274 if (!mlx5_core_mp_enabled(ibdev->mdev) || 275 ll != IB_LINK_LAYER_ETHERNET) { 276 if (native_port_num) 277 *native_port_num = ib_port_num; 278 return ibdev->mdev; 279 } 280 281 if (native_port_num) 282 *native_port_num = 1; 283 284 port = &ibdev->port[ib_port_num - 1]; 285 spin_lock(&port->mp.mpi_lock); 286 mpi = ibdev->port[ib_port_num - 1].mp.mpi; 287 if (mpi && !mpi->unaffiliate) { 288 mdev = mpi->mdev; 289 /* If it's the master no need to refcount, it'll exist 290 * as long as the ib_dev exists. 291 */ 292 if (!mpi->is_master) 293 mpi->mdev_refcnt++; 294 } 295 spin_unlock(&port->mp.mpi_lock); 296 297 return mdev; 298 } 299 300 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num) 301 { 302 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 303 port_num); 304 struct mlx5_ib_multiport_info *mpi; 305 struct mlx5_ib_port *port; 306 307 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 308 return; 309 310 port = &ibdev->port[port_num - 1]; 311 312 spin_lock(&port->mp.mpi_lock); 313 mpi = ibdev->port[port_num - 1].mp.mpi; 314 if (mpi->is_master) 315 goto out; 316 317 mpi->mdev_refcnt--; 318 if (mpi->unaffiliate) 319 complete(&mpi->unref_comp); 320 out: 321 spin_unlock(&port->mp.mpi_lock); 322 } 323 324 static int translate_eth_legacy_proto_oper(u32 eth_proto_oper, 325 u16 *active_speed, u8 *active_width) 326 { 327 switch (eth_proto_oper) { 328 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII): 329 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX): 330 case MLX5E_PROT_MASK(MLX5E_100BASE_TX): 331 case MLX5E_PROT_MASK(MLX5E_1000BASE_T): 332 *active_width = IB_WIDTH_1X; 333 *active_speed = IB_SPEED_SDR; 334 break; 335 case MLX5E_PROT_MASK(MLX5E_10GBASE_T): 336 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4): 337 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4): 338 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR): 339 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR): 340 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR): 341 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER): 342 *active_width = IB_WIDTH_1X; 343 *active_speed = IB_SPEED_QDR; 344 break; 345 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR): 346 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR): 347 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR): 348 *active_width = IB_WIDTH_1X; 349 *active_speed = IB_SPEED_EDR; 350 break; 351 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4): 352 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4): 353 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4): 354 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4): 355 *active_width = IB_WIDTH_4X; 356 *active_speed = IB_SPEED_QDR; 357 break; 358 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2): 359 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2): 360 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2): 361 *active_width = IB_WIDTH_1X; 362 *active_speed = IB_SPEED_HDR; 363 break; 364 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4): 365 *active_width = IB_WIDTH_4X; 366 *active_speed = IB_SPEED_FDR; 367 break; 368 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4): 369 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4): 370 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4): 371 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4): 372 *active_width = IB_WIDTH_4X; 373 *active_speed = IB_SPEED_EDR; 374 break; 375 default: 376 return -EINVAL; 377 } 378 379 return 0; 380 } 381 382 static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u16 *active_speed, 383 u8 *active_width) 384 { 385 switch (eth_proto_oper) { 386 case MLX5E_PROT_MASK(MLX5E_SGMII_100M): 387 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII): 388 *active_width = IB_WIDTH_1X; 389 *active_speed = IB_SPEED_SDR; 390 break; 391 case MLX5E_PROT_MASK(MLX5E_5GBASE_R): 392 *active_width = IB_WIDTH_1X; 393 *active_speed = IB_SPEED_DDR; 394 break; 395 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1): 396 *active_width = IB_WIDTH_1X; 397 *active_speed = IB_SPEED_QDR; 398 break; 399 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4): 400 *active_width = IB_WIDTH_4X; 401 *active_speed = IB_SPEED_QDR; 402 break; 403 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR): 404 *active_width = IB_WIDTH_1X; 405 *active_speed = IB_SPEED_EDR; 406 break; 407 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2): 408 *active_width = IB_WIDTH_2X; 409 *active_speed = IB_SPEED_EDR; 410 break; 411 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR): 412 *active_width = IB_WIDTH_1X; 413 *active_speed = IB_SPEED_HDR; 414 break; 415 case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4): 416 *active_width = IB_WIDTH_4X; 417 *active_speed = IB_SPEED_EDR; 418 break; 419 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2): 420 *active_width = IB_WIDTH_2X; 421 *active_speed = IB_SPEED_HDR; 422 break; 423 case MLX5E_PROT_MASK(MLX5E_100GAUI_1_100GBASE_CR_KR): 424 *active_width = IB_WIDTH_1X; 425 *active_speed = IB_SPEED_NDR; 426 break; 427 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4): 428 *active_width = IB_WIDTH_4X; 429 *active_speed = IB_SPEED_HDR; 430 break; 431 case MLX5E_PROT_MASK(MLX5E_200GAUI_2_200GBASE_CR2_KR2): 432 *active_width = IB_WIDTH_2X; 433 *active_speed = IB_SPEED_NDR; 434 break; 435 case MLX5E_PROT_MASK(MLX5E_400GAUI_4_400GBASE_CR4_KR4): 436 *active_width = IB_WIDTH_4X; 437 *active_speed = IB_SPEED_NDR; 438 break; 439 default: 440 return -EINVAL; 441 } 442 443 return 0; 444 } 445 446 static int translate_eth_proto_oper(u32 eth_proto_oper, u16 *active_speed, 447 u8 *active_width, bool ext) 448 { 449 return ext ? 450 translate_eth_ext_proto_oper(eth_proto_oper, active_speed, 451 active_width) : 452 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed, 453 active_width); 454 } 455 456 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num, 457 struct ib_port_attr *props) 458 { 459 struct mlx5_ib_dev *dev = to_mdev(device); 460 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0}; 461 struct mlx5_core_dev *mdev; 462 struct net_device *ndev, *upper; 463 enum ib_mtu ndev_ib_mtu; 464 bool put_mdev = true; 465 u16 qkey_viol_cntr; 466 u32 eth_prot_oper; 467 u8 mdev_port_num; 468 bool ext; 469 int err; 470 471 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 472 if (!mdev) { 473 /* This means the port isn't affiliated yet. Get the 474 * info for the master port instead. 475 */ 476 put_mdev = false; 477 mdev = dev->mdev; 478 mdev_port_num = 1; 479 port_num = 1; 480 } 481 482 /* Possible bad flows are checked before filling out props so in case 483 * of an error it will still be zeroed out. 484 * Use native port in case of reps 485 */ 486 if (dev->is_rep) 487 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 488 1); 489 else 490 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 491 mdev_port_num); 492 if (err) 493 goto out; 494 ext = !!MLX5_GET_ETH_PROTO(ptys_reg, out, true, eth_proto_capability); 495 eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper); 496 497 props->active_width = IB_WIDTH_4X; 498 props->active_speed = IB_SPEED_QDR; 499 500 translate_eth_proto_oper(eth_prot_oper, &props->active_speed, 501 &props->active_width, ext); 502 503 props->port_cap_flags |= IB_PORT_CM_SUP; 504 props->ip_gids = true; 505 506 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 507 roce_address_table_size); 508 props->max_mtu = IB_MTU_4096; 509 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 510 props->pkey_tbl_len = 1; 511 props->state = IB_PORT_DOWN; 512 props->phys_state = IB_PORT_PHYS_STATE_DISABLED; 513 514 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr); 515 props->qkey_viol_cntr = qkey_viol_cntr; 516 517 /* If this is a stub query for an unaffiliated port stop here */ 518 if (!put_mdev) 519 goto out; 520 521 ndev = mlx5_ib_get_netdev(device, port_num); 522 if (!ndev) 523 goto out; 524 525 if (dev->lag_active) { 526 rcu_read_lock(); 527 upper = netdev_master_upper_dev_get_rcu(ndev); 528 if (upper) { 529 dev_put(ndev); 530 ndev = upper; 531 dev_hold(ndev); 532 } 533 rcu_read_unlock(); 534 } 535 536 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 537 props->state = IB_PORT_ACTIVE; 538 props->phys_state = IB_PORT_PHYS_STATE_LINK_UP; 539 } 540 541 ndev_ib_mtu = iboe_get_mtu(ndev->mtu); 542 543 dev_put(ndev); 544 545 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 546 out: 547 if (put_mdev) 548 mlx5_ib_put_native_port_mdev(dev, port_num); 549 return err; 550 } 551 552 static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num, 553 unsigned int index, const union ib_gid *gid, 554 const struct ib_gid_attr *attr) 555 { 556 enum ib_gid_type gid_type = IB_GID_TYPE_ROCE; 557 u16 vlan_id = 0xffff; 558 u8 roce_version = 0; 559 u8 roce_l3_type = 0; 560 u8 mac[ETH_ALEN]; 561 int ret; 562 563 if (gid) { 564 gid_type = attr->gid_type; 565 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]); 566 if (ret) 567 return ret; 568 } 569 570 switch (gid_type) { 571 case IB_GID_TYPE_ROCE: 572 roce_version = MLX5_ROCE_VERSION_1; 573 break; 574 case IB_GID_TYPE_ROCE_UDP_ENCAP: 575 roce_version = MLX5_ROCE_VERSION_2; 576 if (ipv6_addr_v4mapped((void *)gid)) 577 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4; 578 else 579 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6; 580 break; 581 582 default: 583 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type); 584 } 585 586 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version, 587 roce_l3_type, gid->raw, mac, 588 vlan_id < VLAN_CFI_MASK, vlan_id, 589 port_num); 590 } 591 592 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr, 593 __always_unused void **context) 594 { 595 return set_roce_addr(to_mdev(attr->device), attr->port_num, 596 attr->index, &attr->gid, attr); 597 } 598 599 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr, 600 __always_unused void **context) 601 { 602 return set_roce_addr(to_mdev(attr->device), attr->port_num, 603 attr->index, NULL, NULL); 604 } 605 606 __be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev, 607 const struct ib_gid_attr *attr) 608 { 609 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 610 return 0; 611 612 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 613 } 614 615 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 616 { 617 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 618 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 619 return 0; 620 } 621 622 enum { 623 MLX5_VPORT_ACCESS_METHOD_MAD, 624 MLX5_VPORT_ACCESS_METHOD_HCA, 625 MLX5_VPORT_ACCESS_METHOD_NIC, 626 }; 627 628 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 629 { 630 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 631 return MLX5_VPORT_ACCESS_METHOD_MAD; 632 633 if (mlx5_ib_port_link_layer(ibdev, 1) == 634 IB_LINK_LAYER_ETHERNET) 635 return MLX5_VPORT_ACCESS_METHOD_NIC; 636 637 return MLX5_VPORT_ACCESS_METHOD_HCA; 638 } 639 640 static void get_atomic_caps(struct mlx5_ib_dev *dev, 641 u8 atomic_size_qp, 642 struct ib_device_attr *props) 643 { 644 u8 tmp; 645 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 646 u8 atomic_req_8B_endianness_mode = 647 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode); 648 649 /* Check if HW supports 8 bytes standard atomic operations and capable 650 * of host endianness respond 651 */ 652 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 653 if (((atomic_operations & tmp) == tmp) && 654 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 655 (atomic_req_8B_endianness_mode)) { 656 props->atomic_cap = IB_ATOMIC_HCA; 657 } else { 658 props->atomic_cap = IB_ATOMIC_NONE; 659 } 660 } 661 662 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev, 663 struct ib_device_attr *props) 664 { 665 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 666 667 get_atomic_caps(dev, atomic_size_qp, props); 668 } 669 670 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 671 __be64 *sys_image_guid) 672 { 673 struct mlx5_ib_dev *dev = to_mdev(ibdev); 674 struct mlx5_core_dev *mdev = dev->mdev; 675 u64 tmp; 676 int err; 677 678 switch (mlx5_get_vport_access_method(ibdev)) { 679 case MLX5_VPORT_ACCESS_METHOD_MAD: 680 return mlx5_query_mad_ifc_system_image_guid(ibdev, 681 sys_image_guid); 682 683 case MLX5_VPORT_ACCESS_METHOD_HCA: 684 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 685 break; 686 687 case MLX5_VPORT_ACCESS_METHOD_NIC: 688 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 689 break; 690 691 default: 692 return -EINVAL; 693 } 694 695 if (!err) 696 *sys_image_guid = cpu_to_be64(tmp); 697 698 return err; 699 700 } 701 702 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 703 u16 *max_pkeys) 704 { 705 struct mlx5_ib_dev *dev = to_mdev(ibdev); 706 struct mlx5_core_dev *mdev = dev->mdev; 707 708 switch (mlx5_get_vport_access_method(ibdev)) { 709 case MLX5_VPORT_ACCESS_METHOD_MAD: 710 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 711 712 case MLX5_VPORT_ACCESS_METHOD_HCA: 713 case MLX5_VPORT_ACCESS_METHOD_NIC: 714 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 715 pkey_table_size)); 716 return 0; 717 718 default: 719 return -EINVAL; 720 } 721 } 722 723 static int mlx5_query_vendor_id(struct ib_device *ibdev, 724 u32 *vendor_id) 725 { 726 struct mlx5_ib_dev *dev = to_mdev(ibdev); 727 728 switch (mlx5_get_vport_access_method(ibdev)) { 729 case MLX5_VPORT_ACCESS_METHOD_MAD: 730 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 731 732 case MLX5_VPORT_ACCESS_METHOD_HCA: 733 case MLX5_VPORT_ACCESS_METHOD_NIC: 734 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 735 736 default: 737 return -EINVAL; 738 } 739 } 740 741 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 742 __be64 *node_guid) 743 { 744 u64 tmp; 745 int err; 746 747 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 748 case MLX5_VPORT_ACCESS_METHOD_MAD: 749 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 750 751 case MLX5_VPORT_ACCESS_METHOD_HCA: 752 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 753 break; 754 755 case MLX5_VPORT_ACCESS_METHOD_NIC: 756 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 757 break; 758 759 default: 760 return -EINVAL; 761 } 762 763 if (!err) 764 *node_guid = cpu_to_be64(tmp); 765 766 return err; 767 } 768 769 struct mlx5_reg_node_desc { 770 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 771 }; 772 773 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 774 { 775 struct mlx5_reg_node_desc in; 776 777 if (mlx5_use_mad_ifc(dev)) 778 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 779 780 memset(&in, 0, sizeof(in)); 781 782 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 783 sizeof(struct mlx5_reg_node_desc), 784 MLX5_REG_NODE_DESC, 0, 0); 785 } 786 787 static int mlx5_ib_query_device(struct ib_device *ibdev, 788 struct ib_device_attr *props, 789 struct ib_udata *uhw) 790 { 791 size_t uhw_outlen = (uhw) ? uhw->outlen : 0; 792 struct mlx5_ib_dev *dev = to_mdev(ibdev); 793 struct mlx5_core_dev *mdev = dev->mdev; 794 int err = -ENOMEM; 795 int max_sq_desc; 796 int max_rq_sg; 797 int max_sq_sg; 798 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 799 bool raw_support = !mlx5_core_mp_enabled(mdev); 800 struct mlx5_ib_query_device_resp resp = {}; 801 size_t resp_len; 802 u64 max_tso; 803 804 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 805 if (uhw_outlen && uhw_outlen < resp_len) 806 return -EINVAL; 807 808 resp.response_length = resp_len; 809 810 if (uhw && uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) 811 return -EINVAL; 812 813 memset(props, 0, sizeof(*props)); 814 err = mlx5_query_system_image_guid(ibdev, 815 &props->sys_image_guid); 816 if (err) 817 return err; 818 819 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys); 820 if (err) 821 return err; 822 823 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 824 if (err) 825 return err; 826 827 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 828 (fw_rev_min(dev->mdev) << 16) | 829 fw_rev_sub(dev->mdev); 830 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 831 IB_DEVICE_PORT_ACTIVE_EVENT | 832 IB_DEVICE_SYS_IMAGE_GUID | 833 IB_DEVICE_RC_RNR_NAK_GEN; 834 835 if (MLX5_CAP_GEN(mdev, pkv)) 836 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 837 if (MLX5_CAP_GEN(mdev, qkv)) 838 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 839 if (MLX5_CAP_GEN(mdev, apm)) 840 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 841 if (MLX5_CAP_GEN(mdev, xrc)) 842 props->device_cap_flags |= IB_DEVICE_XRC; 843 if (MLX5_CAP_GEN(mdev, imaicl)) { 844 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 845 IB_DEVICE_MEM_WINDOW_TYPE_2B; 846 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 847 /* We support 'Gappy' memory registration too */ 848 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG; 849 } 850 /* IB_WR_REG_MR always requires changing the entity size with UMR */ 851 if (!MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) 852 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 853 if (MLX5_CAP_GEN(mdev, sho)) { 854 props->device_cap_flags |= IB_DEVICE_INTEGRITY_HANDOVER; 855 /* At this stage no support for signature handover */ 856 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 857 IB_PROT_T10DIF_TYPE_2 | 858 IB_PROT_T10DIF_TYPE_3; 859 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 860 IB_GUARD_T10DIF_CSUM; 861 } 862 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 863 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 864 865 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) { 866 if (MLX5_CAP_ETH(mdev, csum_cap)) { 867 /* Legacy bit to support old userspace libraries */ 868 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 869 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM; 870 } 871 872 if (MLX5_CAP_ETH(dev->mdev, vlan_cap)) 873 props->raw_packet_caps |= 874 IB_RAW_PACKET_CAP_CVLAN_STRIPPING; 875 876 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) { 877 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 878 if (max_tso) { 879 resp.tso_caps.max_tso = 1 << max_tso; 880 resp.tso_caps.supported_qpts |= 881 1 << IB_QPT_RAW_PACKET; 882 resp.response_length += sizeof(resp.tso_caps); 883 } 884 } 885 886 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) { 887 resp.rss_caps.rx_hash_function = 888 MLX5_RX_HASH_FUNC_TOEPLITZ; 889 resp.rss_caps.rx_hash_fields_mask = 890 MLX5_RX_HASH_SRC_IPV4 | 891 MLX5_RX_HASH_DST_IPV4 | 892 MLX5_RX_HASH_SRC_IPV6 | 893 MLX5_RX_HASH_DST_IPV6 | 894 MLX5_RX_HASH_SRC_PORT_TCP | 895 MLX5_RX_HASH_DST_PORT_TCP | 896 MLX5_RX_HASH_SRC_PORT_UDP | 897 MLX5_RX_HASH_DST_PORT_UDP | 898 MLX5_RX_HASH_INNER; 899 if (mlx5_accel_ipsec_device_caps(dev->mdev) & 900 MLX5_ACCEL_IPSEC_CAP_DEVICE) 901 resp.rss_caps.rx_hash_fields_mask |= 902 MLX5_RX_HASH_IPSEC_SPI; 903 resp.response_length += sizeof(resp.rss_caps); 904 } 905 } else { 906 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) 907 resp.response_length += sizeof(resp.tso_caps); 908 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) 909 resp.response_length += sizeof(resp.rss_caps); 910 } 911 912 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 913 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 914 props->device_cap_flags |= IB_DEVICE_UD_TSO; 915 } 916 917 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) && 918 MLX5_CAP_GEN(dev->mdev, general_notification_event) && 919 raw_support) 920 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP; 921 922 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 923 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap)) 924 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 925 926 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 927 MLX5_CAP_ETH(dev->mdev, scatter_fcs) && 928 raw_support) { 929 /* Legacy bit to support old userspace libraries */ 930 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 931 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; 932 } 933 934 if (MLX5_CAP_DEV_MEM(mdev, memic)) { 935 props->max_dm_size = 936 MLX5_CAP_DEV_MEM(mdev, max_memic_size); 937 } 938 939 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 940 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 941 942 if (MLX5_CAP_GEN(mdev, end_pad)) 943 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING; 944 945 props->vendor_part_id = mdev->pdev->device; 946 props->hw_ver = mdev->pdev->revision; 947 948 props->max_mr_size = ~0ull; 949 props->page_size_cap = ~(min_page_size - 1); 950 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 951 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 952 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 953 sizeof(struct mlx5_wqe_data_seg); 954 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512); 955 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) - 956 sizeof(struct mlx5_wqe_raddr_seg)) / 957 sizeof(struct mlx5_wqe_data_seg); 958 props->max_send_sge = max_sq_sg; 959 props->max_recv_sge = max_rq_sg; 960 props->max_sge_rd = MLX5_MAX_SGE_RD; 961 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 962 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 963 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 964 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 965 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 966 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 967 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 968 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 969 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 970 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 971 props->max_srq_sge = max_rq_sg - 1; 972 props->max_fast_reg_page_list_len = 973 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 974 props->max_pi_fast_reg_page_list_len = 975 props->max_fast_reg_page_list_len / 2; 976 props->max_sgl_rd = 977 MLX5_CAP_GEN(mdev, max_sgl_for_optimized_performance); 978 get_atomic_caps_qp(dev, props); 979 props->masked_atomic_cap = IB_ATOMIC_NONE; 980 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 981 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 982 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 983 props->max_mcast_grp; 984 props->max_ah = INT_MAX; 985 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 986 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 987 988 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) { 989 if (dev->odp_caps.general_caps & IB_ODP_SUPPORT) 990 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING; 991 props->odp_caps = dev->odp_caps; 992 if (!uhw) { 993 /* ODP for kernel QPs is not implemented for receive 994 * WQEs and SRQ WQEs 995 */ 996 props->odp_caps.per_transport_caps.rc_odp_caps &= 997 ~(IB_ODP_SUPPORT_READ | 998 IB_ODP_SUPPORT_SRQ_RECV); 999 props->odp_caps.per_transport_caps.uc_odp_caps &= 1000 ~(IB_ODP_SUPPORT_READ | 1001 IB_ODP_SUPPORT_SRQ_RECV); 1002 props->odp_caps.per_transport_caps.ud_odp_caps &= 1003 ~(IB_ODP_SUPPORT_READ | 1004 IB_ODP_SUPPORT_SRQ_RECV); 1005 props->odp_caps.per_transport_caps.xrc_odp_caps &= 1006 ~(IB_ODP_SUPPORT_READ | 1007 IB_ODP_SUPPORT_SRQ_RECV); 1008 } 1009 } 1010 1011 if (MLX5_CAP_GEN(mdev, cd)) 1012 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL; 1013 1014 if (mlx5_core_is_vf(mdev)) 1015 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION; 1016 1017 if (mlx5_ib_port_link_layer(ibdev, 1) == 1018 IB_LINK_LAYER_ETHERNET && raw_support) { 1019 props->rss_caps.max_rwq_indirection_tables = 1020 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 1021 props->rss_caps.max_rwq_indirection_table_size = 1022 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 1023 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 1024 props->max_wq_type_rq = 1025 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 1026 } 1027 1028 if (MLX5_CAP_GEN(mdev, tag_matching)) { 1029 props->tm_caps.max_num_tags = 1030 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1; 1031 props->tm_caps.max_ops = 1032 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 1033 props->tm_caps.max_sge = MLX5_TM_MAX_SGE; 1034 } 1035 1036 if (MLX5_CAP_GEN(mdev, tag_matching) && 1037 MLX5_CAP_GEN(mdev, rndv_offload_rc)) { 1038 props->tm_caps.flags = IB_TM_CAP_RNDV_RC; 1039 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE; 1040 } 1041 1042 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) { 1043 props->cq_caps.max_cq_moderation_count = 1044 MLX5_MAX_CQ_COUNT; 1045 props->cq_caps.max_cq_moderation_period = 1046 MLX5_MAX_CQ_PERIOD; 1047 } 1048 1049 if (offsetofend(typeof(resp), cqe_comp_caps) <= uhw_outlen) { 1050 resp.response_length += sizeof(resp.cqe_comp_caps); 1051 1052 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) { 1053 resp.cqe_comp_caps.max_num = 1054 MLX5_CAP_GEN(dev->mdev, 1055 cqe_compression_max_num); 1056 1057 resp.cqe_comp_caps.supported_format = 1058 MLX5_IB_CQE_RES_FORMAT_HASH | 1059 MLX5_IB_CQE_RES_FORMAT_CSUM; 1060 1061 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index)) 1062 resp.cqe_comp_caps.supported_format |= 1063 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX; 1064 } 1065 } 1066 1067 if (offsetofend(typeof(resp), packet_pacing_caps) <= uhw_outlen && 1068 raw_support) { 1069 if (MLX5_CAP_QOS(mdev, packet_pacing) && 1070 MLX5_CAP_GEN(mdev, qos)) { 1071 resp.packet_pacing_caps.qp_rate_limit_max = 1072 MLX5_CAP_QOS(mdev, packet_pacing_max_rate); 1073 resp.packet_pacing_caps.qp_rate_limit_min = 1074 MLX5_CAP_QOS(mdev, packet_pacing_min_rate); 1075 resp.packet_pacing_caps.supported_qpts |= 1076 1 << IB_QPT_RAW_PACKET; 1077 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) && 1078 MLX5_CAP_QOS(mdev, packet_pacing_typical_size)) 1079 resp.packet_pacing_caps.cap_flags |= 1080 MLX5_IB_PP_SUPPORT_BURST; 1081 } 1082 resp.response_length += sizeof(resp.packet_pacing_caps); 1083 } 1084 1085 if (offsetofend(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes) <= 1086 uhw_outlen) { 1087 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe)) 1088 resp.mlx5_ib_support_multi_pkt_send_wqes = 1089 MLX5_IB_ALLOW_MPW; 1090 1091 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe)) 1092 resp.mlx5_ib_support_multi_pkt_send_wqes |= 1093 MLX5_IB_SUPPORT_EMPW; 1094 1095 resp.response_length += 1096 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes); 1097 } 1098 1099 if (offsetofend(typeof(resp), flags) <= uhw_outlen) { 1100 resp.response_length += sizeof(resp.flags); 1101 1102 if (MLX5_CAP_GEN(mdev, cqe_compression_128)) 1103 resp.flags |= 1104 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP; 1105 1106 if (MLX5_CAP_GEN(mdev, cqe_128_always)) 1107 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD; 1108 if (MLX5_CAP_GEN(mdev, qp_packet_based)) 1109 resp.flags |= 1110 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE; 1111 1112 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT; 1113 } 1114 1115 if (offsetofend(typeof(resp), sw_parsing_caps) <= uhw_outlen) { 1116 resp.response_length += sizeof(resp.sw_parsing_caps); 1117 if (MLX5_CAP_ETH(mdev, swp)) { 1118 resp.sw_parsing_caps.sw_parsing_offloads |= 1119 MLX5_IB_SW_PARSING; 1120 1121 if (MLX5_CAP_ETH(mdev, swp_csum)) 1122 resp.sw_parsing_caps.sw_parsing_offloads |= 1123 MLX5_IB_SW_PARSING_CSUM; 1124 1125 if (MLX5_CAP_ETH(mdev, swp_lso)) 1126 resp.sw_parsing_caps.sw_parsing_offloads |= 1127 MLX5_IB_SW_PARSING_LSO; 1128 1129 if (resp.sw_parsing_caps.sw_parsing_offloads) 1130 resp.sw_parsing_caps.supported_qpts = 1131 BIT(IB_QPT_RAW_PACKET); 1132 } 1133 } 1134 1135 if (offsetofend(typeof(resp), striding_rq_caps) <= uhw_outlen && 1136 raw_support) { 1137 resp.response_length += sizeof(resp.striding_rq_caps); 1138 if (MLX5_CAP_GEN(mdev, striding_rq)) { 1139 resp.striding_rq_caps.min_single_stride_log_num_of_bytes = 1140 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES; 1141 resp.striding_rq_caps.max_single_stride_log_num_of_bytes = 1142 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES; 1143 if (MLX5_CAP_GEN(dev->mdev, ext_stride_num_range)) 1144 resp.striding_rq_caps 1145 .min_single_wqe_log_num_of_strides = 1146 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1147 else 1148 resp.striding_rq_caps 1149 .min_single_wqe_log_num_of_strides = 1150 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1151 resp.striding_rq_caps.max_single_wqe_log_num_of_strides = 1152 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES; 1153 resp.striding_rq_caps.supported_qpts = 1154 BIT(IB_QPT_RAW_PACKET); 1155 } 1156 } 1157 1158 if (offsetofend(typeof(resp), tunnel_offloads_caps) <= uhw_outlen) { 1159 resp.response_length += sizeof(resp.tunnel_offloads_caps); 1160 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan)) 1161 resp.tunnel_offloads_caps |= 1162 MLX5_IB_TUNNELED_OFFLOADS_VXLAN; 1163 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx)) 1164 resp.tunnel_offloads_caps |= 1165 MLX5_IB_TUNNELED_OFFLOADS_GENEVE; 1166 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) 1167 resp.tunnel_offloads_caps |= 1168 MLX5_IB_TUNNELED_OFFLOADS_GRE; 1169 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre)) 1170 resp.tunnel_offloads_caps |= 1171 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE; 1172 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_udp)) 1173 resp.tunnel_offloads_caps |= 1174 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP; 1175 } 1176 1177 if (uhw_outlen) { 1178 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 1179 1180 if (err) 1181 return err; 1182 } 1183 1184 return 0; 1185 } 1186 1187 static void translate_active_width(struct ib_device *ibdev, u16 active_width, 1188 u8 *ib_width) 1189 { 1190 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1191 1192 if (active_width & MLX5_PTYS_WIDTH_1X) 1193 *ib_width = IB_WIDTH_1X; 1194 else if (active_width & MLX5_PTYS_WIDTH_2X) 1195 *ib_width = IB_WIDTH_2X; 1196 else if (active_width & MLX5_PTYS_WIDTH_4X) 1197 *ib_width = IB_WIDTH_4X; 1198 else if (active_width & MLX5_PTYS_WIDTH_8X) 1199 *ib_width = IB_WIDTH_8X; 1200 else if (active_width & MLX5_PTYS_WIDTH_12X) 1201 *ib_width = IB_WIDTH_12X; 1202 else { 1203 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n", 1204 active_width); 1205 *ib_width = IB_WIDTH_4X; 1206 } 1207 1208 return; 1209 } 1210 1211 static int mlx5_mtu_to_ib_mtu(int mtu) 1212 { 1213 switch (mtu) { 1214 case 256: return 1; 1215 case 512: return 2; 1216 case 1024: return 3; 1217 case 2048: return 4; 1218 case 4096: return 5; 1219 default: 1220 pr_warn("invalid mtu\n"); 1221 return -1; 1222 } 1223 } 1224 1225 enum ib_max_vl_num { 1226 __IB_MAX_VL_0 = 1, 1227 __IB_MAX_VL_0_1 = 2, 1228 __IB_MAX_VL_0_3 = 3, 1229 __IB_MAX_VL_0_7 = 4, 1230 __IB_MAX_VL_0_14 = 5, 1231 }; 1232 1233 enum mlx5_vl_hw_cap { 1234 MLX5_VL_HW_0 = 1, 1235 MLX5_VL_HW_0_1 = 2, 1236 MLX5_VL_HW_0_2 = 3, 1237 MLX5_VL_HW_0_3 = 4, 1238 MLX5_VL_HW_0_4 = 5, 1239 MLX5_VL_HW_0_5 = 6, 1240 MLX5_VL_HW_0_6 = 7, 1241 MLX5_VL_HW_0_7 = 8, 1242 MLX5_VL_HW_0_14 = 15 1243 }; 1244 1245 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 1246 u8 *max_vl_num) 1247 { 1248 switch (vl_hw_cap) { 1249 case MLX5_VL_HW_0: 1250 *max_vl_num = __IB_MAX_VL_0; 1251 break; 1252 case MLX5_VL_HW_0_1: 1253 *max_vl_num = __IB_MAX_VL_0_1; 1254 break; 1255 case MLX5_VL_HW_0_3: 1256 *max_vl_num = __IB_MAX_VL_0_3; 1257 break; 1258 case MLX5_VL_HW_0_7: 1259 *max_vl_num = __IB_MAX_VL_0_7; 1260 break; 1261 case MLX5_VL_HW_0_14: 1262 *max_vl_num = __IB_MAX_VL_0_14; 1263 break; 1264 1265 default: 1266 return -EINVAL; 1267 } 1268 1269 return 0; 1270 } 1271 1272 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port, 1273 struct ib_port_attr *props) 1274 { 1275 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1276 struct mlx5_core_dev *mdev = dev->mdev; 1277 struct mlx5_hca_vport_context *rep; 1278 u16 max_mtu; 1279 u16 oper_mtu; 1280 int err; 1281 u16 ib_link_width_oper; 1282 u8 vl_hw_cap; 1283 1284 rep = kzalloc(sizeof(*rep), GFP_KERNEL); 1285 if (!rep) { 1286 err = -ENOMEM; 1287 goto out; 1288 } 1289 1290 /* props being zeroed by the caller, avoid zeroing it here */ 1291 1292 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); 1293 if (err) 1294 goto out; 1295 1296 props->lid = rep->lid; 1297 props->lmc = rep->lmc; 1298 props->sm_lid = rep->sm_lid; 1299 props->sm_sl = rep->sm_sl; 1300 props->state = rep->vport_state; 1301 props->phys_state = rep->port_physical_state; 1302 props->port_cap_flags = rep->cap_mask1; 1303 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 1304 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 1305 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 1306 props->bad_pkey_cntr = rep->pkey_violation_counter; 1307 props->qkey_viol_cntr = rep->qkey_violation_counter; 1308 props->subnet_timeout = rep->subnet_timeout; 1309 props->init_type_reply = rep->init_type_reply; 1310 1311 if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP) 1312 props->port_cap_flags2 = rep->cap_mask2; 1313 1314 err = mlx5_query_ib_port_oper(mdev, &ib_link_width_oper, 1315 &props->active_speed, port); 1316 if (err) 1317 goto out; 1318 1319 translate_active_width(ibdev, ib_link_width_oper, &props->active_width); 1320 1321 mlx5_query_port_max_mtu(mdev, &max_mtu, port); 1322 1323 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); 1324 1325 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); 1326 1327 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); 1328 1329 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); 1330 if (err) 1331 goto out; 1332 1333 err = translate_max_vl_num(ibdev, vl_hw_cap, 1334 &props->max_vl_num); 1335 out: 1336 kfree(rep); 1337 return err; 1338 } 1339 1340 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 1341 struct ib_port_attr *props) 1342 { 1343 unsigned int count; 1344 int ret; 1345 1346 switch (mlx5_get_vport_access_method(ibdev)) { 1347 case MLX5_VPORT_ACCESS_METHOD_MAD: 1348 ret = mlx5_query_mad_ifc_port(ibdev, port, props); 1349 break; 1350 1351 case MLX5_VPORT_ACCESS_METHOD_HCA: 1352 ret = mlx5_query_hca_port(ibdev, port, props); 1353 break; 1354 1355 case MLX5_VPORT_ACCESS_METHOD_NIC: 1356 ret = mlx5_query_port_roce(ibdev, port, props); 1357 break; 1358 1359 default: 1360 ret = -EINVAL; 1361 } 1362 1363 if (!ret && props) { 1364 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1365 struct mlx5_core_dev *mdev; 1366 bool put_mdev = true; 1367 1368 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL); 1369 if (!mdev) { 1370 /* If the port isn't affiliated yet query the master. 1371 * The master and slave will have the same values. 1372 */ 1373 mdev = dev->mdev; 1374 port = 1; 1375 put_mdev = false; 1376 } 1377 count = mlx5_core_reserved_gids_count(mdev); 1378 if (put_mdev) 1379 mlx5_ib_put_native_port_mdev(dev, port); 1380 props->gid_tbl_len -= count; 1381 } 1382 return ret; 1383 } 1384 1385 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port, 1386 struct ib_port_attr *props) 1387 { 1388 int ret; 1389 1390 /* Only link layer == ethernet is valid for representors 1391 * and we always use port 1 1392 */ 1393 ret = mlx5_query_port_roce(ibdev, port, props); 1394 if (ret || !props) 1395 return ret; 1396 1397 /* We don't support GIDS */ 1398 props->gid_tbl_len = 0; 1399 1400 return ret; 1401 } 1402 1403 static int mlx5_ib_rep_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 1404 u16 *pkey) 1405 { 1406 /* Default special Pkey for representor device port as per the 1407 * IB specification 1.3 section 10.9.1.2. 1408 */ 1409 *pkey = 0xffff; 1410 return 0; 1411 } 1412 1413 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 1414 union ib_gid *gid) 1415 { 1416 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1417 struct mlx5_core_dev *mdev = dev->mdev; 1418 1419 switch (mlx5_get_vport_access_method(ibdev)) { 1420 case MLX5_VPORT_ACCESS_METHOD_MAD: 1421 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 1422 1423 case MLX5_VPORT_ACCESS_METHOD_HCA: 1424 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); 1425 1426 default: 1427 return -EINVAL; 1428 } 1429 1430 } 1431 1432 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port, 1433 u16 index, u16 *pkey) 1434 { 1435 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1436 struct mlx5_core_dev *mdev; 1437 bool put_mdev = true; 1438 u8 mdev_port_num; 1439 int err; 1440 1441 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num); 1442 if (!mdev) { 1443 /* The port isn't affiliated yet, get the PKey from the master 1444 * port. For RoCE the PKey tables will be the same. 1445 */ 1446 put_mdev = false; 1447 mdev = dev->mdev; 1448 mdev_port_num = 1; 1449 } 1450 1451 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0, 1452 index, pkey); 1453 if (put_mdev) 1454 mlx5_ib_put_native_port_mdev(dev, port); 1455 1456 return err; 1457 } 1458 1459 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 1460 u16 *pkey) 1461 { 1462 switch (mlx5_get_vport_access_method(ibdev)) { 1463 case MLX5_VPORT_ACCESS_METHOD_MAD: 1464 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 1465 1466 case MLX5_VPORT_ACCESS_METHOD_HCA: 1467 case MLX5_VPORT_ACCESS_METHOD_NIC: 1468 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey); 1469 default: 1470 return -EINVAL; 1471 } 1472 } 1473 1474 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 1475 struct ib_device_modify *props) 1476 { 1477 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1478 struct mlx5_reg_node_desc in; 1479 struct mlx5_reg_node_desc out; 1480 int err; 1481 1482 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 1483 return -EOPNOTSUPP; 1484 1485 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 1486 return 0; 1487 1488 /* 1489 * If possible, pass node desc to FW, so it can generate 1490 * a 144 trap. If cmd fails, just ignore. 1491 */ 1492 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1493 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 1494 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 1495 if (err) 1496 return err; 1497 1498 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1499 1500 return err; 1501 } 1502 1503 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask, 1504 u32 value) 1505 { 1506 struct mlx5_hca_vport_context ctx = {}; 1507 struct mlx5_core_dev *mdev; 1508 u8 mdev_port_num; 1509 int err; 1510 1511 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 1512 if (!mdev) 1513 return -ENODEV; 1514 1515 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx); 1516 if (err) 1517 goto out; 1518 1519 if (~ctx.cap_mask1_perm & mask) { 1520 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n", 1521 mask, ctx.cap_mask1_perm); 1522 err = -EINVAL; 1523 goto out; 1524 } 1525 1526 ctx.cap_mask1 = value; 1527 ctx.cap_mask1_perm = mask; 1528 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num, 1529 0, &ctx); 1530 1531 out: 1532 mlx5_ib_put_native_port_mdev(dev, port_num); 1533 1534 return err; 1535 } 1536 1537 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, 1538 struct ib_port_modify *props) 1539 { 1540 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1541 struct ib_port_attr attr; 1542 u32 tmp; 1543 int err; 1544 u32 change_mask; 1545 u32 value; 1546 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) == 1547 IB_LINK_LAYER_INFINIBAND); 1548 1549 /* CM layer calls ib_modify_port() regardless of the link layer. For 1550 * Ethernet ports, qkey violation and Port capabilities are meaningless. 1551 */ 1552 if (!is_ib) 1553 return 0; 1554 1555 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) { 1556 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask; 1557 value = ~props->clr_port_cap_mask | props->set_port_cap_mask; 1558 return set_port_caps_atomic(dev, port, change_mask, value); 1559 } 1560 1561 mutex_lock(&dev->cap_mask_mutex); 1562 1563 err = ib_query_port(ibdev, port, &attr); 1564 if (err) 1565 goto out; 1566 1567 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 1568 ~props->clr_port_cap_mask; 1569 1570 err = mlx5_set_port_caps(dev->mdev, port, tmp); 1571 1572 out: 1573 mutex_unlock(&dev->cap_mask_mutex); 1574 return err; 1575 } 1576 1577 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps) 1578 { 1579 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n", 1580 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n"); 1581 } 1582 1583 static u16 calc_dynamic_bfregs(int uars_per_sys_page) 1584 { 1585 /* Large page with non 4k uar support might limit the dynamic size */ 1586 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096) 1587 return MLX5_MIN_DYN_BFREGS; 1588 1589 return MLX5_MAX_DYN_BFREGS; 1590 } 1591 1592 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k, 1593 struct mlx5_ib_alloc_ucontext_req_v2 *req, 1594 struct mlx5_bfreg_info *bfregi) 1595 { 1596 int uars_per_sys_page; 1597 int bfregs_per_sys_page; 1598 int ref_bfregs = req->total_num_bfregs; 1599 1600 if (req->total_num_bfregs == 0) 1601 return -EINVAL; 1602 1603 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE); 1604 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE); 1605 1606 if (req->total_num_bfregs > MLX5_MAX_BFREGS) 1607 return -ENOMEM; 1608 1609 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k); 1610 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR; 1611 /* This holds the required static allocation asked by the user */ 1612 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page); 1613 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1) 1614 return -EINVAL; 1615 1616 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page; 1617 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page); 1618 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs; 1619 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page; 1620 1621 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n", 1622 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no", 1623 lib_uar_4k ? "yes" : "no", ref_bfregs, 1624 req->total_num_bfregs, bfregi->total_num_bfregs, 1625 bfregi->num_sys_pages); 1626 1627 return 0; 1628 } 1629 1630 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1631 { 1632 struct mlx5_bfreg_info *bfregi; 1633 int err; 1634 int i; 1635 1636 bfregi = &context->bfregi; 1637 for (i = 0; i < bfregi->num_static_sys_pages; i++) { 1638 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]); 1639 if (err) 1640 goto error; 1641 1642 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]); 1643 } 1644 1645 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++) 1646 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX; 1647 1648 return 0; 1649 1650 error: 1651 for (--i; i >= 0; i--) 1652 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i])) 1653 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1654 1655 return err; 1656 } 1657 1658 static void deallocate_uars(struct mlx5_ib_dev *dev, 1659 struct mlx5_ib_ucontext *context) 1660 { 1661 struct mlx5_bfreg_info *bfregi; 1662 int i; 1663 1664 bfregi = &context->bfregi; 1665 for (i = 0; i < bfregi->num_sys_pages; i++) 1666 if (i < bfregi->num_static_sys_pages || 1667 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) 1668 mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]); 1669 } 1670 1671 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 1672 { 1673 int err = 0; 1674 1675 mutex_lock(&dev->lb.mutex); 1676 if (td) 1677 dev->lb.user_td++; 1678 if (qp) 1679 dev->lb.qps++; 1680 1681 if (dev->lb.user_td == 2 || 1682 dev->lb.qps == 1) { 1683 if (!dev->lb.enabled) { 1684 err = mlx5_nic_vport_update_local_lb(dev->mdev, true); 1685 dev->lb.enabled = true; 1686 } 1687 } 1688 1689 mutex_unlock(&dev->lb.mutex); 1690 1691 return err; 1692 } 1693 1694 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 1695 { 1696 mutex_lock(&dev->lb.mutex); 1697 if (td) 1698 dev->lb.user_td--; 1699 if (qp) 1700 dev->lb.qps--; 1701 1702 if (dev->lb.user_td == 1 && 1703 dev->lb.qps == 0) { 1704 if (dev->lb.enabled) { 1705 mlx5_nic_vport_update_local_lb(dev->mdev, false); 1706 dev->lb.enabled = false; 1707 } 1708 } 1709 1710 mutex_unlock(&dev->lb.mutex); 1711 } 1712 1713 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn, 1714 u16 uid) 1715 { 1716 int err; 1717 1718 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1719 return 0; 1720 1721 err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid); 1722 if (err) 1723 return err; 1724 1725 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1726 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1727 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1728 return err; 1729 1730 return mlx5_ib_enable_lb(dev, true, false); 1731 } 1732 1733 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn, 1734 u16 uid) 1735 { 1736 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1737 return; 1738 1739 mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid); 1740 1741 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1742 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1743 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1744 return; 1745 1746 mlx5_ib_disable_lb(dev, true, false); 1747 } 1748 1749 static int set_ucontext_resp(struct ib_ucontext *uctx, 1750 struct mlx5_ib_alloc_ucontext_resp *resp) 1751 { 1752 struct ib_device *ibdev = uctx->device; 1753 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1754 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 1755 struct mlx5_bfreg_info *bfregi = &context->bfregi; 1756 int err; 1757 1758 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) { 1759 err = mlx5_cmd_dump_fill_mkey(dev->mdev, 1760 &resp->dump_fill_mkey); 1761 if (err) 1762 return err; 1763 resp->comp_mask |= 1764 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY; 1765 } 1766 1767 resp->qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 1768 if (dev->wc_support) 1769 resp->bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, 1770 log_bf_reg_size); 1771 resp->cache_line_size = cache_line_size(); 1772 resp->max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 1773 resp->max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 1774 resp->max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1775 resp->max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1776 resp->max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 1777 resp->cqe_version = context->cqe_version; 1778 resp->log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1779 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT; 1780 resp->num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1781 MLX5_CAP_GEN(dev->mdev, 1782 num_of_uars_per_page) : 1; 1783 1784 if (mlx5_accel_ipsec_device_caps(dev->mdev) & 1785 MLX5_ACCEL_IPSEC_CAP_DEVICE) { 1786 if (mlx5_get_flow_namespace(dev->mdev, 1787 MLX5_FLOW_NAMESPACE_EGRESS)) 1788 resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM; 1789 if (mlx5_accel_ipsec_device_caps(dev->mdev) & 1790 MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA) 1791 resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA; 1792 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi)) 1793 resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING; 1794 if (mlx5_accel_ipsec_device_caps(dev->mdev) & 1795 MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN) 1796 resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN; 1797 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */ 1798 } 1799 1800 resp->tot_bfregs = bfregi->lib_uar_dyn ? 0 : 1801 bfregi->total_num_bfregs - bfregi->num_dyn_bfregs; 1802 resp->num_ports = dev->num_ports; 1803 resp->cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 1804 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 1805 1806 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) { 1807 mlx5_query_min_inline(dev->mdev, &resp->eth_min_inline); 1808 resp->eth_min_inline++; 1809 } 1810 1811 if (dev->mdev->clock_info) 1812 resp->clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1); 1813 1814 /* 1815 * We don't want to expose information from the PCI bar that is located 1816 * after 4096 bytes, so if the arch only supports larger pages, let's 1817 * pretend we don't support reading the HCA's core clock. This is also 1818 * forced by mmap function. 1819 */ 1820 if (PAGE_SIZE <= 4096) { 1821 resp->comp_mask |= 1822 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 1823 resp->hca_core_clock_offset = 1824 offsetof(struct mlx5_init_seg, 1825 internal_timer_h) % PAGE_SIZE; 1826 } 1827 1828 if (MLX5_CAP_GEN(dev->mdev, ece_support)) 1829 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE; 1830 1831 resp->num_dyn_bfregs = bfregi->num_dyn_bfregs; 1832 return 0; 1833 } 1834 1835 static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx, 1836 struct ib_udata *udata) 1837 { 1838 struct ib_device *ibdev = uctx->device; 1839 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1840 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 1841 struct mlx5_ib_alloc_ucontext_resp resp = {}; 1842 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 1843 struct mlx5_bfreg_info *bfregi; 1844 int ver; 1845 int err; 1846 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 1847 max_cqe_version); 1848 bool lib_uar_4k; 1849 bool lib_uar_dyn; 1850 1851 if (!dev->ib_active) 1852 return -EAGAIN; 1853 1854 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 1855 ver = 0; 1856 else if (udata->inlen >= min_req_v2) 1857 ver = 2; 1858 else 1859 return -EINVAL; 1860 1861 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req))); 1862 if (err) 1863 return err; 1864 1865 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX) 1866 return -EOPNOTSUPP; 1867 1868 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 1869 return -EOPNOTSUPP; 1870 1871 req.total_num_bfregs = ALIGN(req.total_num_bfregs, 1872 MLX5_NON_FP_BFREGS_PER_UAR); 1873 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1) 1874 return -EINVAL; 1875 1876 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR; 1877 lib_uar_dyn = req.lib_caps & MLX5_LIB_CAP_DYN_UAR; 1878 bfregi = &context->bfregi; 1879 1880 if (lib_uar_dyn) { 1881 bfregi->lib_uar_dyn = lib_uar_dyn; 1882 goto uar_done; 1883 } 1884 1885 /* updates req->total_num_bfregs */ 1886 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi); 1887 if (err) 1888 goto out_ctx; 1889 1890 mutex_init(&bfregi->lock); 1891 bfregi->lib_uar_4k = lib_uar_4k; 1892 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count), 1893 GFP_KERNEL); 1894 if (!bfregi->count) { 1895 err = -ENOMEM; 1896 goto out_ctx; 1897 } 1898 1899 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages, 1900 sizeof(*bfregi->sys_pages), 1901 GFP_KERNEL); 1902 if (!bfregi->sys_pages) { 1903 err = -ENOMEM; 1904 goto out_count; 1905 } 1906 1907 err = allocate_uars(dev, context); 1908 if (err) 1909 goto out_sys_pages; 1910 1911 uar_done: 1912 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) { 1913 err = mlx5_ib_devx_create(dev, true); 1914 if (err < 0) 1915 goto out_uars; 1916 context->devx_uid = err; 1917 } 1918 1919 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn, 1920 context->devx_uid); 1921 if (err) 1922 goto out_devx; 1923 1924 INIT_LIST_HEAD(&context->db_page_list); 1925 mutex_init(&context->db_page_mutex); 1926 1927 context->cqe_version = min_t(__u8, 1928 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 1929 req.max_cqe_version); 1930 1931 err = set_ucontext_resp(uctx, &resp); 1932 if (err) 1933 goto out_mdev; 1934 1935 resp.response_length = min(udata->outlen, sizeof(resp)); 1936 err = ib_copy_to_udata(udata, &resp, resp.response_length); 1937 if (err) 1938 goto out_mdev; 1939 1940 bfregi->ver = ver; 1941 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs; 1942 context->lib_caps = req.lib_caps; 1943 print_lib_caps(dev, context->lib_caps); 1944 1945 if (mlx5_ib_lag_should_assign_affinity(dev)) { 1946 u8 port = mlx5_core_native_port_num(dev->mdev) - 1; 1947 1948 atomic_set(&context->tx_port_affinity, 1949 atomic_add_return( 1950 1, &dev->port[port].roce.tx_port_affinity)); 1951 } 1952 1953 return 0; 1954 1955 out_mdev: 1956 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 1957 out_devx: 1958 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) 1959 mlx5_ib_devx_destroy(dev, context->devx_uid); 1960 1961 out_uars: 1962 deallocate_uars(dev, context); 1963 1964 out_sys_pages: 1965 kfree(bfregi->sys_pages); 1966 1967 out_count: 1968 kfree(bfregi->count); 1969 1970 out_ctx: 1971 return err; 1972 } 1973 1974 static int mlx5_ib_query_ucontext(struct ib_ucontext *ibcontext, 1975 struct uverbs_attr_bundle *attrs) 1976 { 1977 struct mlx5_ib_alloc_ucontext_resp uctx_resp = {}; 1978 int ret; 1979 1980 ret = set_ucontext_resp(ibcontext, &uctx_resp); 1981 if (ret) 1982 return ret; 1983 1984 uctx_resp.response_length = 1985 min_t(size_t, 1986 uverbs_attr_get_len(attrs, 1987 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX), 1988 sizeof(uctx_resp)); 1989 1990 ret = uverbs_copy_to_struct_or_zero(attrs, 1991 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX, 1992 &uctx_resp, 1993 sizeof(uctx_resp)); 1994 return ret; 1995 } 1996 1997 static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1998 { 1999 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2000 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2001 struct mlx5_bfreg_info *bfregi; 2002 2003 bfregi = &context->bfregi; 2004 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 2005 2006 if (context->devx_uid) 2007 mlx5_ib_devx_destroy(dev, context->devx_uid); 2008 2009 deallocate_uars(dev, context); 2010 kfree(bfregi->sys_pages); 2011 kfree(bfregi->count); 2012 } 2013 2014 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, 2015 int uar_idx) 2016 { 2017 int fw_uars_per_page; 2018 2019 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1; 2020 2021 return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page; 2022 } 2023 2024 static u64 uar_index2paddress(struct mlx5_ib_dev *dev, 2025 int uar_idx) 2026 { 2027 unsigned int fw_uars_per_page; 2028 2029 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 2030 MLX5_UARS_IN_PAGE : 1; 2031 2032 return (dev->mdev->bar_addr + (uar_idx / fw_uars_per_page) * PAGE_SIZE); 2033 } 2034 2035 static int get_command(unsigned long offset) 2036 { 2037 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 2038 } 2039 2040 static int get_arg(unsigned long offset) 2041 { 2042 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 2043 } 2044 2045 static int get_index(unsigned long offset) 2046 { 2047 return get_arg(offset); 2048 } 2049 2050 /* Index resides in an extra byte to enable larger values than 255 */ 2051 static int get_extended_index(unsigned long offset) 2052 { 2053 return get_arg(offset) | ((offset >> 16) & 0xff) << 8; 2054 } 2055 2056 2057 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 2058 { 2059 } 2060 2061 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 2062 { 2063 switch (cmd) { 2064 case MLX5_IB_MMAP_WC_PAGE: 2065 return "WC"; 2066 case MLX5_IB_MMAP_REGULAR_PAGE: 2067 return "best effort WC"; 2068 case MLX5_IB_MMAP_NC_PAGE: 2069 return "NC"; 2070 case MLX5_IB_MMAP_DEVICE_MEM: 2071 return "Device Memory"; 2072 default: 2073 return NULL; 2074 } 2075 } 2076 2077 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev, 2078 struct vm_area_struct *vma, 2079 struct mlx5_ib_ucontext *context) 2080 { 2081 if ((vma->vm_end - vma->vm_start != PAGE_SIZE) || 2082 !(vma->vm_flags & VM_SHARED)) 2083 return -EINVAL; 2084 2085 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1) 2086 return -EOPNOTSUPP; 2087 2088 if (vma->vm_flags & (VM_WRITE | VM_EXEC)) 2089 return -EPERM; 2090 vma->vm_flags &= ~VM_MAYWRITE; 2091 2092 if (!dev->mdev->clock_info) 2093 return -EOPNOTSUPP; 2094 2095 return vm_insert_page(vma, vma->vm_start, 2096 virt_to_page(dev->mdev->clock_info)); 2097 } 2098 2099 static void mlx5_ib_mmap_free(struct rdma_user_mmap_entry *entry) 2100 { 2101 struct mlx5_user_mmap_entry *mentry = to_mmmap(entry); 2102 struct mlx5_ib_dev *dev = to_mdev(entry->ucontext->device); 2103 struct mlx5_var_table *var_table = &dev->var_table; 2104 struct mlx5_ib_dm *mdm; 2105 2106 switch (mentry->mmap_flag) { 2107 case MLX5_IB_MMAP_TYPE_MEMIC: 2108 mdm = container_of(mentry, struct mlx5_ib_dm, mentry); 2109 mlx5_cmd_dealloc_memic(&dev->dm, mdm->dev_addr, 2110 mdm->size); 2111 kfree(mdm); 2112 break; 2113 case MLX5_IB_MMAP_TYPE_VAR: 2114 mutex_lock(&var_table->bitmap_lock); 2115 clear_bit(mentry->page_idx, var_table->bitmap); 2116 mutex_unlock(&var_table->bitmap_lock); 2117 kfree(mentry); 2118 break; 2119 case MLX5_IB_MMAP_TYPE_UAR_WC: 2120 case MLX5_IB_MMAP_TYPE_UAR_NC: 2121 mlx5_cmd_free_uar(dev->mdev, mentry->page_idx); 2122 kfree(mentry); 2123 break; 2124 default: 2125 WARN_ON(true); 2126 } 2127 } 2128 2129 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 2130 struct vm_area_struct *vma, 2131 struct mlx5_ib_ucontext *context) 2132 { 2133 struct mlx5_bfreg_info *bfregi = &context->bfregi; 2134 int err; 2135 unsigned long idx; 2136 phys_addr_t pfn; 2137 pgprot_t prot; 2138 u32 bfreg_dyn_idx = 0; 2139 u32 uar_index; 2140 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC); 2141 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages : 2142 bfregi->num_static_sys_pages; 2143 2144 if (bfregi->lib_uar_dyn) 2145 return -EINVAL; 2146 2147 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2148 return -EINVAL; 2149 2150 if (dyn_uar) 2151 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages; 2152 else 2153 idx = get_index(vma->vm_pgoff); 2154 2155 if (idx >= max_valid_idx) { 2156 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n", 2157 idx, max_valid_idx); 2158 return -EINVAL; 2159 } 2160 2161 switch (cmd) { 2162 case MLX5_IB_MMAP_WC_PAGE: 2163 case MLX5_IB_MMAP_ALLOC_WC: 2164 case MLX5_IB_MMAP_REGULAR_PAGE: 2165 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 2166 prot = pgprot_writecombine(vma->vm_page_prot); 2167 break; 2168 case MLX5_IB_MMAP_NC_PAGE: 2169 prot = pgprot_noncached(vma->vm_page_prot); 2170 break; 2171 default: 2172 return -EINVAL; 2173 } 2174 2175 if (dyn_uar) { 2176 int uars_per_page; 2177 2178 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k); 2179 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR); 2180 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) { 2181 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n", 2182 bfreg_dyn_idx, bfregi->total_num_bfregs); 2183 return -EINVAL; 2184 } 2185 2186 mutex_lock(&bfregi->lock); 2187 /* Fail if uar already allocated, first bfreg index of each 2188 * page holds its count. 2189 */ 2190 if (bfregi->count[bfreg_dyn_idx]) { 2191 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx); 2192 mutex_unlock(&bfregi->lock); 2193 return -EINVAL; 2194 } 2195 2196 bfregi->count[bfreg_dyn_idx]++; 2197 mutex_unlock(&bfregi->lock); 2198 2199 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index); 2200 if (err) { 2201 mlx5_ib_warn(dev, "UAR alloc failed\n"); 2202 goto free_bfreg; 2203 } 2204 } else { 2205 uar_index = bfregi->sys_pages[idx]; 2206 } 2207 2208 pfn = uar_index2pfn(dev, uar_index); 2209 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 2210 2211 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE, 2212 prot, NULL); 2213 if (err) { 2214 mlx5_ib_err(dev, 2215 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n", 2216 err, mmap_cmd2str(cmd)); 2217 goto err; 2218 } 2219 2220 if (dyn_uar) 2221 bfregi->sys_pages[idx] = uar_index; 2222 return 0; 2223 2224 err: 2225 if (!dyn_uar) 2226 return err; 2227 2228 mlx5_cmd_free_uar(dev->mdev, idx); 2229 2230 free_bfreg: 2231 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx); 2232 2233 return err; 2234 } 2235 2236 static int add_dm_mmap_entry(struct ib_ucontext *context, 2237 struct mlx5_ib_dm *mdm, 2238 u64 address) 2239 { 2240 mdm->mentry.mmap_flag = MLX5_IB_MMAP_TYPE_MEMIC; 2241 mdm->mentry.address = address; 2242 return rdma_user_mmap_entry_insert_range( 2243 context, &mdm->mentry.rdma_entry, 2244 mdm->size, 2245 MLX5_IB_MMAP_DEVICE_MEM << 16, 2246 (MLX5_IB_MMAP_DEVICE_MEM << 16) + (1UL << 16) - 1); 2247 } 2248 2249 static unsigned long mlx5_vma_to_pgoff(struct vm_area_struct *vma) 2250 { 2251 unsigned long idx; 2252 u8 command; 2253 2254 command = get_command(vma->vm_pgoff); 2255 idx = get_extended_index(vma->vm_pgoff); 2256 2257 return (command << 16 | idx); 2258 } 2259 2260 static int mlx5_ib_mmap_offset(struct mlx5_ib_dev *dev, 2261 struct vm_area_struct *vma, 2262 struct ib_ucontext *ucontext) 2263 { 2264 struct mlx5_user_mmap_entry *mentry; 2265 struct rdma_user_mmap_entry *entry; 2266 unsigned long pgoff; 2267 pgprot_t prot; 2268 phys_addr_t pfn; 2269 int ret; 2270 2271 pgoff = mlx5_vma_to_pgoff(vma); 2272 entry = rdma_user_mmap_entry_get_pgoff(ucontext, pgoff); 2273 if (!entry) 2274 return -EINVAL; 2275 2276 mentry = to_mmmap(entry); 2277 pfn = (mentry->address >> PAGE_SHIFT); 2278 if (mentry->mmap_flag == MLX5_IB_MMAP_TYPE_VAR || 2279 mentry->mmap_flag == MLX5_IB_MMAP_TYPE_UAR_NC) 2280 prot = pgprot_noncached(vma->vm_page_prot); 2281 else 2282 prot = pgprot_writecombine(vma->vm_page_prot); 2283 ret = rdma_user_mmap_io(ucontext, vma, pfn, 2284 entry->npages * PAGE_SIZE, 2285 prot, 2286 entry); 2287 rdma_user_mmap_entry_put(&mentry->rdma_entry); 2288 return ret; 2289 } 2290 2291 static u64 mlx5_entry_to_mmap_offset(struct mlx5_user_mmap_entry *entry) 2292 { 2293 u64 cmd = (entry->rdma_entry.start_pgoff >> 16) & 0xFFFF; 2294 u64 index = entry->rdma_entry.start_pgoff & 0xFFFF; 2295 2296 return (((index >> 8) << 16) | (cmd << MLX5_IB_MMAP_CMD_SHIFT) | 2297 (index & 0xFF)) << PAGE_SHIFT; 2298 } 2299 2300 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 2301 { 2302 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2303 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2304 unsigned long command; 2305 phys_addr_t pfn; 2306 2307 command = get_command(vma->vm_pgoff); 2308 switch (command) { 2309 case MLX5_IB_MMAP_WC_PAGE: 2310 case MLX5_IB_MMAP_ALLOC_WC: 2311 if (!dev->wc_support) 2312 return -EPERM; 2313 fallthrough; 2314 case MLX5_IB_MMAP_NC_PAGE: 2315 case MLX5_IB_MMAP_REGULAR_PAGE: 2316 return uar_mmap(dev, command, vma, context); 2317 2318 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 2319 return -ENOSYS; 2320 2321 case MLX5_IB_MMAP_CORE_CLOCK: 2322 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2323 return -EINVAL; 2324 2325 if (vma->vm_flags & VM_WRITE) 2326 return -EPERM; 2327 vma->vm_flags &= ~VM_MAYWRITE; 2328 2329 /* Don't expose to user-space information it shouldn't have */ 2330 if (PAGE_SIZE > 4096) 2331 return -EOPNOTSUPP; 2332 2333 pfn = (dev->mdev->iseg_base + 2334 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 2335 PAGE_SHIFT; 2336 return rdma_user_mmap_io(&context->ibucontext, vma, pfn, 2337 PAGE_SIZE, 2338 pgprot_noncached(vma->vm_page_prot), 2339 NULL); 2340 case MLX5_IB_MMAP_CLOCK_INFO: 2341 return mlx5_ib_mmap_clock_info_page(dev, vma, context); 2342 2343 default: 2344 return mlx5_ib_mmap_offset(dev, vma, ibcontext); 2345 } 2346 2347 return 0; 2348 } 2349 2350 static inline int check_dm_type_support(struct mlx5_ib_dev *dev, 2351 u32 type) 2352 { 2353 switch (type) { 2354 case MLX5_IB_UAPI_DM_TYPE_MEMIC: 2355 if (!MLX5_CAP_DEV_MEM(dev->mdev, memic)) 2356 return -EOPNOTSUPP; 2357 break; 2358 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM: 2359 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM: 2360 if (!capable(CAP_SYS_RAWIO) || 2361 !capable(CAP_NET_RAW)) 2362 return -EPERM; 2363 2364 if (!(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) || 2365 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, sw_owner) || 2366 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner_v2) || 2367 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, sw_owner_v2))) 2368 return -EOPNOTSUPP; 2369 break; 2370 } 2371 2372 return 0; 2373 } 2374 2375 static int handle_alloc_dm_memic(struct ib_ucontext *ctx, 2376 struct mlx5_ib_dm *dm, 2377 struct ib_dm_alloc_attr *attr, 2378 struct uverbs_attr_bundle *attrs) 2379 { 2380 struct mlx5_dm *dm_db = &to_mdev(ctx->device)->dm; 2381 u64 start_offset; 2382 u16 page_idx; 2383 int err; 2384 u64 address; 2385 2386 dm->size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE); 2387 2388 err = mlx5_cmd_alloc_memic(dm_db, &dm->dev_addr, 2389 dm->size, attr->alignment); 2390 if (err) 2391 return err; 2392 2393 address = dm->dev_addr & PAGE_MASK; 2394 err = add_dm_mmap_entry(ctx, dm, address); 2395 if (err) 2396 goto err_dealloc; 2397 2398 page_idx = dm->mentry.rdma_entry.start_pgoff & 0xFFFF; 2399 err = uverbs_copy_to(attrs, 2400 MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX, 2401 &page_idx, 2402 sizeof(page_idx)); 2403 if (err) 2404 goto err_copy; 2405 2406 start_offset = dm->dev_addr & ~PAGE_MASK; 2407 err = uverbs_copy_to(attrs, 2408 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET, 2409 &start_offset, sizeof(start_offset)); 2410 if (err) 2411 goto err_copy; 2412 2413 return 0; 2414 2415 err_copy: 2416 rdma_user_mmap_entry_remove(&dm->mentry.rdma_entry); 2417 err_dealloc: 2418 mlx5_cmd_dealloc_memic(dm_db, dm->dev_addr, dm->size); 2419 2420 return err; 2421 } 2422 2423 static int handle_alloc_dm_sw_icm(struct ib_ucontext *ctx, 2424 struct mlx5_ib_dm *dm, 2425 struct ib_dm_alloc_attr *attr, 2426 struct uverbs_attr_bundle *attrs, 2427 int type) 2428 { 2429 struct mlx5_core_dev *dev = to_mdev(ctx->device)->mdev; 2430 u64 act_size; 2431 int err; 2432 2433 /* Allocation size must a multiple of the basic block size 2434 * and a power of 2. 2435 */ 2436 act_size = round_up(attr->length, MLX5_SW_ICM_BLOCK_SIZE(dev)); 2437 act_size = roundup_pow_of_two(act_size); 2438 2439 dm->size = act_size; 2440 err = mlx5_dm_sw_icm_alloc(dev, type, act_size, attr->alignment, 2441 to_mucontext(ctx)->devx_uid, &dm->dev_addr, 2442 &dm->icm_dm.obj_id); 2443 if (err) 2444 return err; 2445 2446 err = uverbs_copy_to(attrs, 2447 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET, 2448 &dm->dev_addr, sizeof(dm->dev_addr)); 2449 if (err) 2450 mlx5_dm_sw_icm_dealloc(dev, type, dm->size, 2451 to_mucontext(ctx)->devx_uid, dm->dev_addr, 2452 dm->icm_dm.obj_id); 2453 2454 return err; 2455 } 2456 2457 struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev, 2458 struct ib_ucontext *context, 2459 struct ib_dm_alloc_attr *attr, 2460 struct uverbs_attr_bundle *attrs) 2461 { 2462 struct mlx5_ib_dm *dm; 2463 enum mlx5_ib_uapi_dm_type type; 2464 int err; 2465 2466 err = uverbs_get_const_default(&type, attrs, 2467 MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE, 2468 MLX5_IB_UAPI_DM_TYPE_MEMIC); 2469 if (err) 2470 return ERR_PTR(err); 2471 2472 mlx5_ib_dbg(to_mdev(ibdev), "alloc_dm req: dm_type=%d user_length=0x%llx log_alignment=%d\n", 2473 type, attr->length, attr->alignment); 2474 2475 err = check_dm_type_support(to_mdev(ibdev), type); 2476 if (err) 2477 return ERR_PTR(err); 2478 2479 dm = kzalloc(sizeof(*dm), GFP_KERNEL); 2480 if (!dm) 2481 return ERR_PTR(-ENOMEM); 2482 2483 dm->type = type; 2484 2485 switch (type) { 2486 case MLX5_IB_UAPI_DM_TYPE_MEMIC: 2487 err = handle_alloc_dm_memic(context, dm, 2488 attr, 2489 attrs); 2490 break; 2491 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM: 2492 err = handle_alloc_dm_sw_icm(context, dm, 2493 attr, attrs, 2494 MLX5_SW_ICM_TYPE_STEERING); 2495 break; 2496 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM: 2497 err = handle_alloc_dm_sw_icm(context, dm, 2498 attr, attrs, 2499 MLX5_SW_ICM_TYPE_HEADER_MODIFY); 2500 break; 2501 default: 2502 err = -EOPNOTSUPP; 2503 } 2504 2505 if (err) 2506 goto err_free; 2507 2508 return &dm->ibdm; 2509 2510 err_free: 2511 kfree(dm); 2512 return ERR_PTR(err); 2513 } 2514 2515 int mlx5_ib_dealloc_dm(struct ib_dm *ibdm, struct uverbs_attr_bundle *attrs) 2516 { 2517 struct mlx5_ib_ucontext *ctx = rdma_udata_to_drv_context( 2518 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext); 2519 struct mlx5_core_dev *dev = to_mdev(ibdm->device)->mdev; 2520 struct mlx5_ib_dm *dm = to_mdm(ibdm); 2521 int ret; 2522 2523 switch (dm->type) { 2524 case MLX5_IB_UAPI_DM_TYPE_MEMIC: 2525 rdma_user_mmap_entry_remove(&dm->mentry.rdma_entry); 2526 return 0; 2527 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM: 2528 ret = mlx5_dm_sw_icm_dealloc(dev, MLX5_SW_ICM_TYPE_STEERING, 2529 dm->size, ctx->devx_uid, dm->dev_addr, 2530 dm->icm_dm.obj_id); 2531 if (ret) 2532 return ret; 2533 break; 2534 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM: 2535 ret = mlx5_dm_sw_icm_dealloc(dev, MLX5_SW_ICM_TYPE_HEADER_MODIFY, 2536 dm->size, ctx->devx_uid, dm->dev_addr, 2537 dm->icm_dm.obj_id); 2538 if (ret) 2539 return ret; 2540 break; 2541 default: 2542 return -EOPNOTSUPP; 2543 } 2544 2545 kfree(dm); 2546 2547 return 0; 2548 } 2549 2550 static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata) 2551 { 2552 struct mlx5_ib_pd *pd = to_mpd(ibpd); 2553 struct ib_device *ibdev = ibpd->device; 2554 struct mlx5_ib_alloc_pd_resp resp; 2555 int err; 2556 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {}; 2557 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {}; 2558 u16 uid = 0; 2559 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 2560 udata, struct mlx5_ib_ucontext, ibucontext); 2561 2562 uid = context ? context->devx_uid : 0; 2563 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2564 MLX5_SET(alloc_pd_in, in, uid, uid); 2565 err = mlx5_cmd_exec_inout(to_mdev(ibdev)->mdev, alloc_pd, in, out); 2566 if (err) 2567 return err; 2568 2569 pd->pdn = MLX5_GET(alloc_pd_out, out, pd); 2570 pd->uid = uid; 2571 if (udata) { 2572 resp.pdn = pd->pdn; 2573 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 2574 mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid); 2575 return -EFAULT; 2576 } 2577 } 2578 2579 return 0; 2580 } 2581 2582 static int mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata) 2583 { 2584 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 2585 struct mlx5_ib_pd *mpd = to_mpd(pd); 2586 2587 return mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid); 2588 } 2589 2590 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2591 { 2592 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2593 struct mlx5_ib_qp *mqp = to_mqp(ibqp); 2594 int err; 2595 u16 uid; 2596 2597 uid = ibqp->pd ? 2598 to_mpd(ibqp->pd)->uid : 0; 2599 2600 if (mqp->flags & IB_QP_CREATE_SOURCE_QPN) { 2601 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n"); 2602 return -EOPNOTSUPP; 2603 } 2604 2605 err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 2606 if (err) 2607 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 2608 ibqp->qp_num, gid->raw); 2609 2610 return err; 2611 } 2612 2613 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2614 { 2615 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2616 int err; 2617 u16 uid; 2618 2619 uid = ibqp->pd ? 2620 to_mpd(ibqp->pd)->uid : 0; 2621 err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 2622 if (err) 2623 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 2624 ibqp->qp_num, gid->raw); 2625 2626 return err; 2627 } 2628 2629 static int init_node_data(struct mlx5_ib_dev *dev) 2630 { 2631 int err; 2632 2633 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 2634 if (err) 2635 return err; 2636 2637 dev->mdev->rev_id = dev->mdev->pdev->revision; 2638 2639 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 2640 } 2641 2642 static ssize_t fw_pages_show(struct device *device, 2643 struct device_attribute *attr, char *buf) 2644 { 2645 struct mlx5_ib_dev *dev = 2646 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2647 2648 return sysfs_emit(buf, "%d\n", dev->mdev->priv.fw_pages); 2649 } 2650 static DEVICE_ATTR_RO(fw_pages); 2651 2652 static ssize_t reg_pages_show(struct device *device, 2653 struct device_attribute *attr, char *buf) 2654 { 2655 struct mlx5_ib_dev *dev = 2656 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2657 2658 return sysfs_emit(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 2659 } 2660 static DEVICE_ATTR_RO(reg_pages); 2661 2662 static ssize_t hca_type_show(struct device *device, 2663 struct device_attribute *attr, char *buf) 2664 { 2665 struct mlx5_ib_dev *dev = 2666 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2667 2668 return sysfs_emit(buf, "MT%d\n", dev->mdev->pdev->device); 2669 } 2670 static DEVICE_ATTR_RO(hca_type); 2671 2672 static ssize_t hw_rev_show(struct device *device, 2673 struct device_attribute *attr, char *buf) 2674 { 2675 struct mlx5_ib_dev *dev = 2676 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2677 2678 return sysfs_emit(buf, "%x\n", dev->mdev->rev_id); 2679 } 2680 static DEVICE_ATTR_RO(hw_rev); 2681 2682 static ssize_t board_id_show(struct device *device, 2683 struct device_attribute *attr, char *buf) 2684 { 2685 struct mlx5_ib_dev *dev = 2686 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2687 2688 return sysfs_emit(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 2689 dev->mdev->board_id); 2690 } 2691 static DEVICE_ATTR_RO(board_id); 2692 2693 static struct attribute *mlx5_class_attributes[] = { 2694 &dev_attr_hw_rev.attr, 2695 &dev_attr_hca_type.attr, 2696 &dev_attr_board_id.attr, 2697 &dev_attr_fw_pages.attr, 2698 &dev_attr_reg_pages.attr, 2699 NULL, 2700 }; 2701 2702 static const struct attribute_group mlx5_attr_group = { 2703 .attrs = mlx5_class_attributes, 2704 }; 2705 2706 static void pkey_change_handler(struct work_struct *work) 2707 { 2708 struct mlx5_ib_port_resources *ports = 2709 container_of(work, struct mlx5_ib_port_resources, 2710 pkey_change_work); 2711 2712 mlx5_ib_gsi_pkey_change(ports->gsi); 2713 } 2714 2715 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 2716 { 2717 struct mlx5_ib_qp *mqp; 2718 struct mlx5_ib_cq *send_mcq, *recv_mcq; 2719 struct mlx5_core_cq *mcq; 2720 struct list_head cq_armed_list; 2721 unsigned long flags_qp; 2722 unsigned long flags_cq; 2723 unsigned long flags; 2724 2725 INIT_LIST_HEAD(&cq_armed_list); 2726 2727 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 2728 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 2729 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 2730 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 2731 if (mqp->sq.tail != mqp->sq.head) { 2732 send_mcq = to_mcq(mqp->ibqp.send_cq); 2733 spin_lock_irqsave(&send_mcq->lock, flags_cq); 2734 if (send_mcq->mcq.comp && 2735 mqp->ibqp.send_cq->comp_handler) { 2736 if (!send_mcq->mcq.reset_notify_added) { 2737 send_mcq->mcq.reset_notify_added = 1; 2738 list_add_tail(&send_mcq->mcq.reset_notify, 2739 &cq_armed_list); 2740 } 2741 } 2742 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 2743 } 2744 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 2745 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 2746 /* no handling is needed for SRQ */ 2747 if (!mqp->ibqp.srq) { 2748 if (mqp->rq.tail != mqp->rq.head) { 2749 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 2750 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 2751 if (recv_mcq->mcq.comp && 2752 mqp->ibqp.recv_cq->comp_handler) { 2753 if (!recv_mcq->mcq.reset_notify_added) { 2754 recv_mcq->mcq.reset_notify_added = 1; 2755 list_add_tail(&recv_mcq->mcq.reset_notify, 2756 &cq_armed_list); 2757 } 2758 } 2759 spin_unlock_irqrestore(&recv_mcq->lock, 2760 flags_cq); 2761 } 2762 } 2763 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 2764 } 2765 /*At that point all inflight post send were put to be executed as of we 2766 * lock/unlock above locks Now need to arm all involved CQs. 2767 */ 2768 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 2769 mcq->comp(mcq, NULL); 2770 } 2771 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 2772 } 2773 2774 static void delay_drop_handler(struct work_struct *work) 2775 { 2776 int err; 2777 struct mlx5_ib_delay_drop *delay_drop = 2778 container_of(work, struct mlx5_ib_delay_drop, 2779 delay_drop_work); 2780 2781 atomic_inc(&delay_drop->events_cnt); 2782 2783 mutex_lock(&delay_drop->lock); 2784 err = mlx5_core_set_delay_drop(delay_drop->dev, delay_drop->timeout); 2785 if (err) { 2786 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n", 2787 delay_drop->timeout); 2788 delay_drop->activate = false; 2789 } 2790 mutex_unlock(&delay_drop->lock); 2791 } 2792 2793 static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 2794 struct ib_event *ibev) 2795 { 2796 u8 port = (eqe->data.port.port >> 4) & 0xf; 2797 2798 switch (eqe->sub_type) { 2799 case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT: 2800 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2801 IB_LINK_LAYER_ETHERNET) 2802 schedule_work(&ibdev->delay_drop.delay_drop_work); 2803 break; 2804 default: /* do nothing */ 2805 return; 2806 } 2807 } 2808 2809 static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 2810 struct ib_event *ibev) 2811 { 2812 u8 port = (eqe->data.port.port >> 4) & 0xf; 2813 2814 ibev->element.port_num = port; 2815 2816 switch (eqe->sub_type) { 2817 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 2818 case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 2819 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED: 2820 /* In RoCE, port up/down events are handled in 2821 * mlx5_netdev_event(). 2822 */ 2823 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2824 IB_LINK_LAYER_ETHERNET) 2825 return -EINVAL; 2826 2827 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ? 2828 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 2829 break; 2830 2831 case MLX5_PORT_CHANGE_SUBTYPE_LID: 2832 ibev->event = IB_EVENT_LID_CHANGE; 2833 break; 2834 2835 case MLX5_PORT_CHANGE_SUBTYPE_PKEY: 2836 ibev->event = IB_EVENT_PKEY_CHANGE; 2837 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 2838 break; 2839 2840 case MLX5_PORT_CHANGE_SUBTYPE_GUID: 2841 ibev->event = IB_EVENT_GID_CHANGE; 2842 break; 2843 2844 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG: 2845 ibev->event = IB_EVENT_CLIENT_REREGISTER; 2846 break; 2847 default: 2848 return -EINVAL; 2849 } 2850 2851 return 0; 2852 } 2853 2854 static void mlx5_ib_handle_event(struct work_struct *_work) 2855 { 2856 struct mlx5_ib_event_work *work = 2857 container_of(_work, struct mlx5_ib_event_work, work); 2858 struct mlx5_ib_dev *ibdev; 2859 struct ib_event ibev; 2860 bool fatal = false; 2861 2862 if (work->is_slave) { 2863 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi); 2864 if (!ibdev) 2865 goto out; 2866 } else { 2867 ibdev = work->dev; 2868 } 2869 2870 switch (work->event) { 2871 case MLX5_DEV_EVENT_SYS_ERROR: 2872 ibev.event = IB_EVENT_DEVICE_FATAL; 2873 mlx5_ib_handle_internal_error(ibdev); 2874 ibev.element.port_num = (u8)(unsigned long)work->param; 2875 fatal = true; 2876 break; 2877 case MLX5_EVENT_TYPE_PORT_CHANGE: 2878 if (handle_port_change(ibdev, work->param, &ibev)) 2879 goto out; 2880 break; 2881 case MLX5_EVENT_TYPE_GENERAL_EVENT: 2882 handle_general_event(ibdev, work->param, &ibev); 2883 fallthrough; 2884 default: 2885 goto out; 2886 } 2887 2888 ibev.device = &ibdev->ib_dev; 2889 2890 if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) { 2891 mlx5_ib_warn(ibdev, "warning: event on port %d\n", ibev.element.port_num); 2892 goto out; 2893 } 2894 2895 if (ibdev->ib_active) 2896 ib_dispatch_event(&ibev); 2897 2898 if (fatal) 2899 ibdev->ib_active = false; 2900 out: 2901 kfree(work); 2902 } 2903 2904 static int mlx5_ib_event(struct notifier_block *nb, 2905 unsigned long event, void *param) 2906 { 2907 struct mlx5_ib_event_work *work; 2908 2909 work = kmalloc(sizeof(*work), GFP_ATOMIC); 2910 if (!work) 2911 return NOTIFY_DONE; 2912 2913 INIT_WORK(&work->work, mlx5_ib_handle_event); 2914 work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events); 2915 work->is_slave = false; 2916 work->param = param; 2917 work->event = event; 2918 2919 queue_work(mlx5_ib_event_wq, &work->work); 2920 2921 return NOTIFY_OK; 2922 } 2923 2924 static int mlx5_ib_event_slave_port(struct notifier_block *nb, 2925 unsigned long event, void *param) 2926 { 2927 struct mlx5_ib_event_work *work; 2928 2929 work = kmalloc(sizeof(*work), GFP_ATOMIC); 2930 if (!work) 2931 return NOTIFY_DONE; 2932 2933 INIT_WORK(&work->work, mlx5_ib_handle_event); 2934 work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events); 2935 work->is_slave = true; 2936 work->param = param; 2937 work->event = event; 2938 queue_work(mlx5_ib_event_wq, &work->work); 2939 2940 return NOTIFY_OK; 2941 } 2942 2943 static int set_has_smi_cap(struct mlx5_ib_dev *dev) 2944 { 2945 struct mlx5_hca_vport_context vport_ctx; 2946 int err; 2947 int port; 2948 2949 for (port = 1; port <= ARRAY_SIZE(dev->port_caps); port++) { 2950 dev->port_caps[port - 1].has_smi = false; 2951 if (MLX5_CAP_GEN(dev->mdev, port_type) == 2952 MLX5_CAP_PORT_TYPE_IB) { 2953 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) { 2954 err = mlx5_query_hca_vport_context(dev->mdev, 0, 2955 port, 0, 2956 &vport_ctx); 2957 if (err) { 2958 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n", 2959 port, err); 2960 return err; 2961 } 2962 dev->port_caps[port - 1].has_smi = 2963 vport_ctx.has_smi; 2964 } else { 2965 dev->port_caps[port - 1].has_smi = true; 2966 } 2967 } 2968 } 2969 return 0; 2970 } 2971 2972 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 2973 { 2974 int port; 2975 2976 for (port = 1; port <= dev->num_ports; port++) 2977 mlx5_query_ext_port_caps(dev, port); 2978 } 2979 2980 static int __get_port_caps(struct mlx5_ib_dev *dev, u8 port) 2981 { 2982 struct ib_device_attr *dprops = NULL; 2983 struct ib_port_attr *pprops = NULL; 2984 int err = -ENOMEM; 2985 2986 pprops = kzalloc(sizeof(*pprops), GFP_KERNEL); 2987 if (!pprops) 2988 goto out; 2989 2990 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL); 2991 if (!dprops) 2992 goto out; 2993 2994 err = mlx5_ib_query_device(&dev->ib_dev, dprops, NULL); 2995 if (err) { 2996 mlx5_ib_warn(dev, "query_device failed %d\n", err); 2997 goto out; 2998 } 2999 3000 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops); 3001 if (err) { 3002 mlx5_ib_warn(dev, "query_port %d failed %d\n", 3003 port, err); 3004 goto out; 3005 } 3006 3007 dev->port_caps[port - 1].pkey_table_len = dprops->max_pkeys; 3008 dev->port_caps[port - 1].gid_table_len = pprops->gid_tbl_len; 3009 mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n", 3010 port, dprops->max_pkeys, pprops->gid_tbl_len); 3011 3012 out: 3013 kfree(pprops); 3014 kfree(dprops); 3015 3016 return err; 3017 } 3018 3019 static int get_port_caps(struct mlx5_ib_dev *dev, u8 port) 3020 { 3021 /* For representors use port 1, is this is the only native 3022 * port 3023 */ 3024 if (dev->is_rep) 3025 return __get_port_caps(dev, 1); 3026 return __get_port_caps(dev, port); 3027 } 3028 3029 static u8 mlx5_get_umr_fence(u8 umr_fence_cap) 3030 { 3031 switch (umr_fence_cap) { 3032 case MLX5_CAP_UMR_FENCE_NONE: 3033 return MLX5_FENCE_MODE_NONE; 3034 case MLX5_CAP_UMR_FENCE_SMALL: 3035 return MLX5_FENCE_MODE_INITIATOR_SMALL; 3036 default: 3037 return MLX5_FENCE_MODE_STRONG_ORDERING; 3038 } 3039 } 3040 3041 static int mlx5_ib_dev_res_init(struct mlx5_ib_dev *dev) 3042 { 3043 struct mlx5_ib_resources *devr = &dev->devr; 3044 struct ib_srq_init_attr attr; 3045 struct ib_device *ibdev; 3046 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 3047 int port; 3048 int ret = 0; 3049 3050 ibdev = &dev->ib_dev; 3051 3052 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 3053 return -EOPNOTSUPP; 3054 3055 mutex_init(&devr->mutex); 3056 3057 devr->p0 = rdma_zalloc_drv_obj(ibdev, ib_pd); 3058 if (!devr->p0) 3059 return -ENOMEM; 3060 3061 devr->p0->device = ibdev; 3062 devr->p0->uobject = NULL; 3063 atomic_set(&devr->p0->usecnt, 0); 3064 3065 ret = mlx5_ib_alloc_pd(devr->p0, NULL); 3066 if (ret) 3067 goto error0; 3068 3069 devr->c0 = rdma_zalloc_drv_obj(ibdev, ib_cq); 3070 if (!devr->c0) { 3071 ret = -ENOMEM; 3072 goto error1; 3073 } 3074 3075 devr->c0->device = &dev->ib_dev; 3076 atomic_set(&devr->c0->usecnt, 0); 3077 3078 ret = mlx5_ib_create_cq(devr->c0, &cq_attr, NULL); 3079 if (ret) 3080 goto err_create_cq; 3081 3082 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn0, 0); 3083 if (ret) 3084 goto error2; 3085 3086 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn1, 0); 3087 if (ret) 3088 goto error3; 3089 3090 memset(&attr, 0, sizeof(attr)); 3091 attr.attr.max_sge = 1; 3092 attr.attr.max_wr = 1; 3093 attr.srq_type = IB_SRQT_XRC; 3094 attr.ext.cq = devr->c0; 3095 3096 devr->s0 = rdma_zalloc_drv_obj(ibdev, ib_srq); 3097 if (!devr->s0) { 3098 ret = -ENOMEM; 3099 goto error4; 3100 } 3101 3102 devr->s0->device = &dev->ib_dev; 3103 devr->s0->pd = devr->p0; 3104 devr->s0->srq_type = IB_SRQT_XRC; 3105 devr->s0->ext.cq = devr->c0; 3106 ret = mlx5_ib_create_srq(devr->s0, &attr, NULL); 3107 if (ret) 3108 goto err_create; 3109 3110 atomic_inc(&devr->s0->ext.cq->usecnt); 3111 atomic_inc(&devr->p0->usecnt); 3112 atomic_set(&devr->s0->usecnt, 0); 3113 3114 memset(&attr, 0, sizeof(attr)); 3115 attr.attr.max_sge = 1; 3116 attr.attr.max_wr = 1; 3117 attr.srq_type = IB_SRQT_BASIC; 3118 devr->s1 = rdma_zalloc_drv_obj(ibdev, ib_srq); 3119 if (!devr->s1) { 3120 ret = -ENOMEM; 3121 goto error5; 3122 } 3123 3124 devr->s1->device = &dev->ib_dev; 3125 devr->s1->pd = devr->p0; 3126 devr->s1->srq_type = IB_SRQT_BASIC; 3127 devr->s1->ext.cq = devr->c0; 3128 3129 ret = mlx5_ib_create_srq(devr->s1, &attr, NULL); 3130 if (ret) 3131 goto error6; 3132 3133 atomic_inc(&devr->p0->usecnt); 3134 atomic_set(&devr->s1->usecnt, 0); 3135 3136 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) 3137 INIT_WORK(&devr->ports[port].pkey_change_work, 3138 pkey_change_handler); 3139 3140 return 0; 3141 3142 error6: 3143 kfree(devr->s1); 3144 error5: 3145 mlx5_ib_destroy_srq(devr->s0, NULL); 3146 err_create: 3147 kfree(devr->s0); 3148 error4: 3149 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0); 3150 error3: 3151 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0); 3152 error2: 3153 mlx5_ib_destroy_cq(devr->c0, NULL); 3154 err_create_cq: 3155 kfree(devr->c0); 3156 error1: 3157 mlx5_ib_dealloc_pd(devr->p0, NULL); 3158 error0: 3159 kfree(devr->p0); 3160 return ret; 3161 } 3162 3163 static void mlx5_ib_dev_res_cleanup(struct mlx5_ib_dev *dev) 3164 { 3165 struct mlx5_ib_resources *devr = &dev->devr; 3166 int port; 3167 3168 mlx5_ib_destroy_srq(devr->s1, NULL); 3169 kfree(devr->s1); 3170 mlx5_ib_destroy_srq(devr->s0, NULL); 3171 kfree(devr->s0); 3172 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0); 3173 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0); 3174 mlx5_ib_destroy_cq(devr->c0, NULL); 3175 kfree(devr->c0); 3176 mlx5_ib_dealloc_pd(devr->p0, NULL); 3177 kfree(devr->p0); 3178 3179 /* Make sure no change P_Key work items are still executing */ 3180 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) 3181 cancel_work_sync(&devr->ports[port].pkey_change_work); 3182 } 3183 3184 static u32 get_core_cap_flags(struct ib_device *ibdev, 3185 struct mlx5_hca_vport_context *rep) 3186 { 3187 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3188 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 3189 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 3190 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 3191 bool raw_support = !mlx5_core_mp_enabled(dev->mdev); 3192 u32 ret = 0; 3193 3194 if (rep->grh_required) 3195 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED; 3196 3197 if (ll == IB_LINK_LAYER_INFINIBAND) 3198 return ret | RDMA_CORE_PORT_IBA_IB; 3199 3200 if (raw_support) 3201 ret |= RDMA_CORE_PORT_RAW_PACKET; 3202 3203 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 3204 return ret; 3205 3206 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 3207 return ret; 3208 3209 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 3210 ret |= RDMA_CORE_PORT_IBA_ROCE; 3211 3212 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 3213 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 3214 3215 return ret; 3216 } 3217 3218 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num, 3219 struct ib_port_immutable *immutable) 3220 { 3221 struct ib_port_attr attr; 3222 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3223 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num); 3224 struct mlx5_hca_vport_context rep = {0}; 3225 int err; 3226 3227 err = ib_query_port(ibdev, port_num, &attr); 3228 if (err) 3229 return err; 3230 3231 if (ll == IB_LINK_LAYER_INFINIBAND) { 3232 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0, 3233 &rep); 3234 if (err) 3235 return err; 3236 } 3237 3238 immutable->pkey_tbl_len = attr.pkey_tbl_len; 3239 immutable->gid_tbl_len = attr.gid_tbl_len; 3240 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep); 3241 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 3242 3243 return 0; 3244 } 3245 3246 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num, 3247 struct ib_port_immutable *immutable) 3248 { 3249 struct ib_port_attr attr; 3250 int err; 3251 3252 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 3253 3254 err = ib_query_port(ibdev, port_num, &attr); 3255 if (err) 3256 return err; 3257 3258 immutable->pkey_tbl_len = attr.pkey_tbl_len; 3259 immutable->gid_tbl_len = attr.gid_tbl_len; 3260 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 3261 3262 return 0; 3263 } 3264 3265 static void get_dev_fw_str(struct ib_device *ibdev, char *str) 3266 { 3267 struct mlx5_ib_dev *dev = 3268 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 3269 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d", 3270 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev), 3271 fw_rev_sub(dev->mdev)); 3272 } 3273 3274 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev) 3275 { 3276 struct mlx5_core_dev *mdev = dev->mdev; 3277 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev, 3278 MLX5_FLOW_NAMESPACE_LAG); 3279 struct mlx5_flow_table *ft; 3280 int err; 3281 3282 if (!ns || !mlx5_lag_is_roce(mdev)) 3283 return 0; 3284 3285 err = mlx5_cmd_create_vport_lag(mdev); 3286 if (err) 3287 return err; 3288 3289 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0); 3290 if (IS_ERR(ft)) { 3291 err = PTR_ERR(ft); 3292 goto err_destroy_vport_lag; 3293 } 3294 3295 dev->flow_db->lag_demux_ft = ft; 3296 dev->lag_active = true; 3297 return 0; 3298 3299 err_destroy_vport_lag: 3300 mlx5_cmd_destroy_vport_lag(mdev); 3301 return err; 3302 } 3303 3304 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev) 3305 { 3306 struct mlx5_core_dev *mdev = dev->mdev; 3307 3308 if (dev->lag_active) { 3309 dev->lag_active = false; 3310 3311 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft); 3312 dev->flow_db->lag_demux_ft = NULL; 3313 3314 mlx5_cmd_destroy_vport_lag(mdev); 3315 } 3316 } 3317 3318 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num) 3319 { 3320 int err; 3321 3322 dev->port[port_num].roce.nb.notifier_call = mlx5_netdev_event; 3323 err = register_netdevice_notifier_net(mlx5_core_net(dev->mdev), 3324 &dev->port[port_num].roce.nb); 3325 if (err) { 3326 dev->port[port_num].roce.nb.notifier_call = NULL; 3327 return err; 3328 } 3329 3330 return 0; 3331 } 3332 3333 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num) 3334 { 3335 if (dev->port[port_num].roce.nb.notifier_call) { 3336 unregister_netdevice_notifier_net(mlx5_core_net(dev->mdev), 3337 &dev->port[port_num].roce.nb); 3338 dev->port[port_num].roce.nb.notifier_call = NULL; 3339 } 3340 } 3341 3342 static int mlx5_enable_eth(struct mlx5_ib_dev *dev) 3343 { 3344 int err; 3345 3346 err = mlx5_nic_vport_enable_roce(dev->mdev); 3347 if (err) 3348 return err; 3349 3350 err = mlx5_eth_lag_init(dev); 3351 if (err) 3352 goto err_disable_roce; 3353 3354 return 0; 3355 3356 err_disable_roce: 3357 mlx5_nic_vport_disable_roce(dev->mdev); 3358 3359 return err; 3360 } 3361 3362 static void mlx5_disable_eth(struct mlx5_ib_dev *dev) 3363 { 3364 mlx5_eth_lag_cleanup(dev); 3365 mlx5_nic_vport_disable_roce(dev->mdev); 3366 } 3367 3368 static int mlx5_ib_rn_get_params(struct ib_device *device, u8 port_num, 3369 enum rdma_netdev_t type, 3370 struct rdma_netdev_alloc_params *params) 3371 { 3372 if (type != RDMA_NETDEV_IPOIB) 3373 return -EOPNOTSUPP; 3374 3375 return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params); 3376 } 3377 3378 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf, 3379 size_t count, loff_t *pos) 3380 { 3381 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3382 char lbuf[20]; 3383 int len; 3384 3385 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout); 3386 return simple_read_from_buffer(buf, count, pos, lbuf, len); 3387 } 3388 3389 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf, 3390 size_t count, loff_t *pos) 3391 { 3392 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3393 u32 timeout; 3394 u32 var; 3395 3396 if (kstrtouint_from_user(buf, count, 0, &var)) 3397 return -EFAULT; 3398 3399 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 3400 1000); 3401 if (timeout != var) 3402 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n", 3403 timeout); 3404 3405 delay_drop->timeout = timeout; 3406 3407 return count; 3408 } 3409 3410 static const struct file_operations fops_delay_drop_timeout = { 3411 .owner = THIS_MODULE, 3412 .open = simple_open, 3413 .write = delay_drop_timeout_write, 3414 .read = delay_drop_timeout_read, 3415 }; 3416 3417 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev, 3418 struct mlx5_ib_multiport_info *mpi) 3419 { 3420 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 3421 struct mlx5_ib_port *port = &ibdev->port[port_num]; 3422 int comps; 3423 int err; 3424 int i; 3425 3426 lockdep_assert_held(&mlx5_ib_multiport_mutex); 3427 3428 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num); 3429 3430 spin_lock(&port->mp.mpi_lock); 3431 if (!mpi->ibdev) { 3432 spin_unlock(&port->mp.mpi_lock); 3433 return; 3434 } 3435 3436 mpi->ibdev = NULL; 3437 3438 spin_unlock(&port->mp.mpi_lock); 3439 if (mpi->mdev_events.notifier_call) 3440 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events); 3441 mpi->mdev_events.notifier_call = NULL; 3442 mlx5_remove_netdev_notifier(ibdev, port_num); 3443 spin_lock(&port->mp.mpi_lock); 3444 3445 comps = mpi->mdev_refcnt; 3446 if (comps) { 3447 mpi->unaffiliate = true; 3448 init_completion(&mpi->unref_comp); 3449 spin_unlock(&port->mp.mpi_lock); 3450 3451 for (i = 0; i < comps; i++) 3452 wait_for_completion(&mpi->unref_comp); 3453 3454 spin_lock(&port->mp.mpi_lock); 3455 mpi->unaffiliate = false; 3456 } 3457 3458 port->mp.mpi = NULL; 3459 3460 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 3461 3462 spin_unlock(&port->mp.mpi_lock); 3463 3464 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev); 3465 3466 mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1); 3467 /* Log an error, still needed to cleanup the pointers and add 3468 * it back to the list. 3469 */ 3470 if (err) 3471 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n", 3472 port_num + 1); 3473 3474 ibdev->port[port_num].roce.last_port_state = IB_PORT_DOWN; 3475 } 3476 3477 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev, 3478 struct mlx5_ib_multiport_info *mpi) 3479 { 3480 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 3481 int err; 3482 3483 lockdep_assert_held(&mlx5_ib_multiport_mutex); 3484 3485 spin_lock(&ibdev->port[port_num].mp.mpi_lock); 3486 if (ibdev->port[port_num].mp.mpi) { 3487 mlx5_ib_dbg(ibdev, "port %d already affiliated.\n", 3488 port_num + 1); 3489 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 3490 return false; 3491 } 3492 3493 ibdev->port[port_num].mp.mpi = mpi; 3494 mpi->ibdev = ibdev; 3495 mpi->mdev_events.notifier_call = NULL; 3496 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 3497 3498 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev); 3499 if (err) 3500 goto unbind; 3501 3502 err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev)); 3503 if (err) 3504 goto unbind; 3505 3506 err = mlx5_add_netdev_notifier(ibdev, port_num); 3507 if (err) { 3508 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n", 3509 port_num + 1); 3510 goto unbind; 3511 } 3512 3513 mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port; 3514 mlx5_notifier_register(mpi->mdev, &mpi->mdev_events); 3515 3516 mlx5_ib_init_cong_debugfs(ibdev, port_num); 3517 3518 return true; 3519 3520 unbind: 3521 mlx5_ib_unbind_slave_port(ibdev, mpi); 3522 return false; 3523 } 3524 3525 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev) 3526 { 3527 int port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3528 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 3529 port_num + 1); 3530 struct mlx5_ib_multiport_info *mpi; 3531 int err; 3532 int i; 3533 3534 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 3535 return 0; 3536 3537 err = mlx5_query_nic_vport_system_image_guid(dev->mdev, 3538 &dev->sys_image_guid); 3539 if (err) 3540 return err; 3541 3542 err = mlx5_nic_vport_enable_roce(dev->mdev); 3543 if (err) 3544 return err; 3545 3546 mutex_lock(&mlx5_ib_multiport_mutex); 3547 for (i = 0; i < dev->num_ports; i++) { 3548 bool bound = false; 3549 3550 /* build a stub multiport info struct for the native port. */ 3551 if (i == port_num) { 3552 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 3553 if (!mpi) { 3554 mutex_unlock(&mlx5_ib_multiport_mutex); 3555 mlx5_nic_vport_disable_roce(dev->mdev); 3556 return -ENOMEM; 3557 } 3558 3559 mpi->is_master = true; 3560 mpi->mdev = dev->mdev; 3561 mpi->sys_image_guid = dev->sys_image_guid; 3562 dev->port[i].mp.mpi = mpi; 3563 mpi->ibdev = dev; 3564 mpi = NULL; 3565 continue; 3566 } 3567 3568 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list, 3569 list) { 3570 if (dev->sys_image_guid == mpi->sys_image_guid && 3571 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) { 3572 bound = mlx5_ib_bind_slave_port(dev, mpi); 3573 } 3574 3575 if (bound) { 3576 dev_dbg(mpi->mdev->device, 3577 "removing port from unaffiliated list.\n"); 3578 mlx5_ib_dbg(dev, "port %d bound\n", i + 1); 3579 list_del(&mpi->list); 3580 break; 3581 } 3582 } 3583 if (!bound) { 3584 get_port_caps(dev, i + 1); 3585 mlx5_ib_dbg(dev, "no free port found for port %d\n", 3586 i + 1); 3587 } 3588 } 3589 3590 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list); 3591 mutex_unlock(&mlx5_ib_multiport_mutex); 3592 return err; 3593 } 3594 3595 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev) 3596 { 3597 int port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3598 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 3599 port_num + 1); 3600 int i; 3601 3602 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 3603 return; 3604 3605 mutex_lock(&mlx5_ib_multiport_mutex); 3606 for (i = 0; i < dev->num_ports; i++) { 3607 if (dev->port[i].mp.mpi) { 3608 /* Destroy the native port stub */ 3609 if (i == port_num) { 3610 kfree(dev->port[i].mp.mpi); 3611 dev->port[i].mp.mpi = NULL; 3612 } else { 3613 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1); 3614 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi); 3615 } 3616 } 3617 } 3618 3619 mlx5_ib_dbg(dev, "removing from devlist\n"); 3620 list_del(&dev->ib_dev_list); 3621 mutex_unlock(&mlx5_ib_multiport_mutex); 3622 3623 mlx5_nic_vport_disable_roce(dev->mdev); 3624 } 3625 3626 static int mmap_obj_cleanup(struct ib_uobject *uobject, 3627 enum rdma_remove_reason why, 3628 struct uverbs_attr_bundle *attrs) 3629 { 3630 struct mlx5_user_mmap_entry *obj = uobject->object; 3631 3632 rdma_user_mmap_entry_remove(&obj->rdma_entry); 3633 return 0; 3634 } 3635 3636 static int mlx5_rdma_user_mmap_entry_insert(struct mlx5_ib_ucontext *c, 3637 struct mlx5_user_mmap_entry *entry, 3638 size_t length) 3639 { 3640 return rdma_user_mmap_entry_insert_range( 3641 &c->ibucontext, &entry->rdma_entry, length, 3642 (MLX5_IB_MMAP_OFFSET_START << 16), 3643 ((MLX5_IB_MMAP_OFFSET_END << 16) + (1UL << 16) - 1)); 3644 } 3645 3646 static struct mlx5_user_mmap_entry * 3647 alloc_var_entry(struct mlx5_ib_ucontext *c) 3648 { 3649 struct mlx5_user_mmap_entry *entry; 3650 struct mlx5_var_table *var_table; 3651 u32 page_idx; 3652 int err; 3653 3654 var_table = &to_mdev(c->ibucontext.device)->var_table; 3655 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 3656 if (!entry) 3657 return ERR_PTR(-ENOMEM); 3658 3659 mutex_lock(&var_table->bitmap_lock); 3660 page_idx = find_first_zero_bit(var_table->bitmap, 3661 var_table->num_var_hw_entries); 3662 if (page_idx >= var_table->num_var_hw_entries) { 3663 err = -ENOSPC; 3664 mutex_unlock(&var_table->bitmap_lock); 3665 goto end; 3666 } 3667 3668 set_bit(page_idx, var_table->bitmap); 3669 mutex_unlock(&var_table->bitmap_lock); 3670 3671 entry->address = var_table->hw_start_addr + 3672 (page_idx * var_table->stride_size); 3673 entry->page_idx = page_idx; 3674 entry->mmap_flag = MLX5_IB_MMAP_TYPE_VAR; 3675 3676 err = mlx5_rdma_user_mmap_entry_insert(c, entry, 3677 var_table->stride_size); 3678 if (err) 3679 goto err_insert; 3680 3681 return entry; 3682 3683 err_insert: 3684 mutex_lock(&var_table->bitmap_lock); 3685 clear_bit(page_idx, var_table->bitmap); 3686 mutex_unlock(&var_table->bitmap_lock); 3687 end: 3688 kfree(entry); 3689 return ERR_PTR(err); 3690 } 3691 3692 static int UVERBS_HANDLER(MLX5_IB_METHOD_VAR_OBJ_ALLOC)( 3693 struct uverbs_attr_bundle *attrs) 3694 { 3695 struct ib_uobject *uobj = uverbs_attr_get_uobject( 3696 attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE); 3697 struct mlx5_ib_ucontext *c; 3698 struct mlx5_user_mmap_entry *entry; 3699 u64 mmap_offset; 3700 u32 length; 3701 int err; 3702 3703 c = to_mucontext(ib_uverbs_get_ucontext(attrs)); 3704 if (IS_ERR(c)) 3705 return PTR_ERR(c); 3706 3707 entry = alloc_var_entry(c); 3708 if (IS_ERR(entry)) 3709 return PTR_ERR(entry); 3710 3711 mmap_offset = mlx5_entry_to_mmap_offset(entry); 3712 length = entry->rdma_entry.npages * PAGE_SIZE; 3713 uobj->object = entry; 3714 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE); 3715 3716 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET, 3717 &mmap_offset, sizeof(mmap_offset)); 3718 if (err) 3719 return err; 3720 3721 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID, 3722 &entry->page_idx, sizeof(entry->page_idx)); 3723 if (err) 3724 return err; 3725 3726 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH, 3727 &length, sizeof(length)); 3728 return err; 3729 } 3730 3731 DECLARE_UVERBS_NAMED_METHOD( 3732 MLX5_IB_METHOD_VAR_OBJ_ALLOC, 3733 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE, 3734 MLX5_IB_OBJECT_VAR, 3735 UVERBS_ACCESS_NEW, 3736 UA_MANDATORY), 3737 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID, 3738 UVERBS_ATTR_TYPE(u32), 3739 UA_MANDATORY), 3740 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH, 3741 UVERBS_ATTR_TYPE(u32), 3742 UA_MANDATORY), 3743 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET, 3744 UVERBS_ATTR_TYPE(u64), 3745 UA_MANDATORY)); 3746 3747 DECLARE_UVERBS_NAMED_METHOD_DESTROY( 3748 MLX5_IB_METHOD_VAR_OBJ_DESTROY, 3749 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_DESTROY_HANDLE, 3750 MLX5_IB_OBJECT_VAR, 3751 UVERBS_ACCESS_DESTROY, 3752 UA_MANDATORY)); 3753 3754 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_VAR, 3755 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup), 3756 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_ALLOC), 3757 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_DESTROY)); 3758 3759 static bool var_is_supported(struct ib_device *device) 3760 { 3761 struct mlx5_ib_dev *dev = to_mdev(device); 3762 3763 return (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 3764 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q); 3765 } 3766 3767 static struct mlx5_user_mmap_entry * 3768 alloc_uar_entry(struct mlx5_ib_ucontext *c, 3769 enum mlx5_ib_uapi_uar_alloc_type alloc_type) 3770 { 3771 struct mlx5_user_mmap_entry *entry; 3772 struct mlx5_ib_dev *dev; 3773 u32 uar_index; 3774 int err; 3775 3776 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 3777 if (!entry) 3778 return ERR_PTR(-ENOMEM); 3779 3780 dev = to_mdev(c->ibucontext.device); 3781 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index); 3782 if (err) 3783 goto end; 3784 3785 entry->page_idx = uar_index; 3786 entry->address = uar_index2paddress(dev, uar_index); 3787 if (alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF) 3788 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_WC; 3789 else 3790 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_NC; 3791 3792 err = mlx5_rdma_user_mmap_entry_insert(c, entry, PAGE_SIZE); 3793 if (err) 3794 goto err_insert; 3795 3796 return entry; 3797 3798 err_insert: 3799 mlx5_cmd_free_uar(dev->mdev, uar_index); 3800 end: 3801 kfree(entry); 3802 return ERR_PTR(err); 3803 } 3804 3805 static int UVERBS_HANDLER(MLX5_IB_METHOD_UAR_OBJ_ALLOC)( 3806 struct uverbs_attr_bundle *attrs) 3807 { 3808 struct ib_uobject *uobj = uverbs_attr_get_uobject( 3809 attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE); 3810 enum mlx5_ib_uapi_uar_alloc_type alloc_type; 3811 struct mlx5_ib_ucontext *c; 3812 struct mlx5_user_mmap_entry *entry; 3813 u64 mmap_offset; 3814 u32 length; 3815 int err; 3816 3817 c = to_mucontext(ib_uverbs_get_ucontext(attrs)); 3818 if (IS_ERR(c)) 3819 return PTR_ERR(c); 3820 3821 err = uverbs_get_const(&alloc_type, attrs, 3822 MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE); 3823 if (err) 3824 return err; 3825 3826 if (alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF && 3827 alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_NC) 3828 return -EOPNOTSUPP; 3829 3830 if (!to_mdev(c->ibucontext.device)->wc_support && 3831 alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF) 3832 return -EOPNOTSUPP; 3833 3834 entry = alloc_uar_entry(c, alloc_type); 3835 if (IS_ERR(entry)) 3836 return PTR_ERR(entry); 3837 3838 mmap_offset = mlx5_entry_to_mmap_offset(entry); 3839 length = entry->rdma_entry.npages * PAGE_SIZE; 3840 uobj->object = entry; 3841 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE); 3842 3843 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET, 3844 &mmap_offset, sizeof(mmap_offset)); 3845 if (err) 3846 return err; 3847 3848 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID, 3849 &entry->page_idx, sizeof(entry->page_idx)); 3850 if (err) 3851 return err; 3852 3853 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH, 3854 &length, sizeof(length)); 3855 return err; 3856 } 3857 3858 DECLARE_UVERBS_NAMED_METHOD( 3859 MLX5_IB_METHOD_UAR_OBJ_ALLOC, 3860 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE, 3861 MLX5_IB_OBJECT_UAR, 3862 UVERBS_ACCESS_NEW, 3863 UA_MANDATORY), 3864 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE, 3865 enum mlx5_ib_uapi_uar_alloc_type, 3866 UA_MANDATORY), 3867 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID, 3868 UVERBS_ATTR_TYPE(u32), 3869 UA_MANDATORY), 3870 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH, 3871 UVERBS_ATTR_TYPE(u32), 3872 UA_MANDATORY), 3873 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET, 3874 UVERBS_ATTR_TYPE(u64), 3875 UA_MANDATORY)); 3876 3877 DECLARE_UVERBS_NAMED_METHOD_DESTROY( 3878 MLX5_IB_METHOD_UAR_OBJ_DESTROY, 3879 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_DESTROY_HANDLE, 3880 MLX5_IB_OBJECT_UAR, 3881 UVERBS_ACCESS_DESTROY, 3882 UA_MANDATORY)); 3883 3884 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_UAR, 3885 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup), 3886 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_ALLOC), 3887 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_DESTROY)); 3888 3889 ADD_UVERBS_ATTRIBUTES_SIMPLE( 3890 mlx5_ib_dm, 3891 UVERBS_OBJECT_DM, 3892 UVERBS_METHOD_DM_ALLOC, 3893 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET, 3894 UVERBS_ATTR_TYPE(u64), 3895 UA_MANDATORY), 3896 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX, 3897 UVERBS_ATTR_TYPE(u16), 3898 UA_OPTIONAL), 3899 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE, 3900 enum mlx5_ib_uapi_dm_type, 3901 UA_OPTIONAL)); 3902 3903 ADD_UVERBS_ATTRIBUTES_SIMPLE( 3904 mlx5_ib_flow_action, 3905 UVERBS_OBJECT_FLOW_ACTION, 3906 UVERBS_METHOD_FLOW_ACTION_ESP_CREATE, 3907 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS, 3908 enum mlx5_ib_uapi_flow_action_flags)); 3909 3910 ADD_UVERBS_ATTRIBUTES_SIMPLE( 3911 mlx5_ib_query_context, 3912 UVERBS_OBJECT_DEVICE, 3913 UVERBS_METHOD_QUERY_CONTEXT, 3914 UVERBS_ATTR_PTR_OUT( 3915 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX, 3916 UVERBS_ATTR_STRUCT(struct mlx5_ib_alloc_ucontext_resp, 3917 dump_fill_mkey), 3918 UA_MANDATORY)); 3919 3920 static const struct uapi_definition mlx5_ib_defs[] = { 3921 UAPI_DEF_CHAIN(mlx5_ib_devx_defs), 3922 UAPI_DEF_CHAIN(mlx5_ib_flow_defs), 3923 UAPI_DEF_CHAIN(mlx5_ib_qos_defs), 3924 UAPI_DEF_CHAIN(mlx5_ib_std_types_defs), 3925 3926 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_FLOW_ACTION, 3927 &mlx5_ib_flow_action), 3928 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DM, &mlx5_ib_dm), 3929 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DEVICE, &mlx5_ib_query_context), 3930 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_VAR, 3931 UAPI_DEF_IS_OBJ_SUPPORTED(var_is_supported)), 3932 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_UAR), 3933 {} 3934 }; 3935 3936 static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev) 3937 { 3938 mlx5_ib_cleanup_multiport_master(dev); 3939 WARN_ON(!xa_empty(&dev->odp_mkeys)); 3940 cleanup_srcu_struct(&dev->odp_srcu); 3941 mutex_destroy(&dev->cap_mask_mutex); 3942 WARN_ON(!xa_empty(&dev->sig_mrs)); 3943 WARN_ON(!bitmap_empty(dev->dm.memic_alloc_pages, MLX5_MAX_MEMIC_PAGES)); 3944 } 3945 3946 static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev) 3947 { 3948 struct mlx5_core_dev *mdev = dev->mdev; 3949 int err; 3950 int i; 3951 3952 for (i = 0; i < dev->num_ports; i++) { 3953 spin_lock_init(&dev->port[i].mp.mpi_lock); 3954 rwlock_init(&dev->port[i].roce.netdev_lock); 3955 dev->port[i].roce.dev = dev; 3956 dev->port[i].roce.native_port_num = i + 1; 3957 dev->port[i].roce.last_port_state = IB_PORT_DOWN; 3958 } 3959 3960 mlx5_ib_internal_fill_odp_caps(dev); 3961 3962 err = mlx5_ib_init_multiport_master(dev); 3963 if (err) 3964 return err; 3965 3966 err = set_has_smi_cap(dev); 3967 if (err) 3968 goto err_mp; 3969 3970 if (!mlx5_core_mp_enabled(mdev)) { 3971 for (i = 1; i <= dev->num_ports; i++) { 3972 err = get_port_caps(dev, i); 3973 if (err) 3974 break; 3975 } 3976 } else { 3977 err = get_port_caps(dev, mlx5_core_native_port_num(mdev)); 3978 } 3979 if (err) 3980 goto err_mp; 3981 3982 if (mlx5_use_mad_ifc(dev)) 3983 get_ext_port_caps(dev); 3984 3985 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 3986 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 3987 dev->ib_dev.phys_port_cnt = dev->num_ports; 3988 dev->ib_dev.num_comp_vectors = mlx5_comp_vectors_count(mdev); 3989 dev->ib_dev.dev.parent = mdev->device; 3990 dev->ib_dev.lag_flags = RDMA_LAG_FLAGS_HASH_ALL_SLAVES; 3991 3992 err = init_srcu_struct(&dev->odp_srcu); 3993 if (err) 3994 goto err_mp; 3995 3996 mutex_init(&dev->cap_mask_mutex); 3997 INIT_LIST_HEAD(&dev->qp_list); 3998 spin_lock_init(&dev->reset_flow_resource_lock); 3999 xa_init(&dev->odp_mkeys); 4000 xa_init(&dev->sig_mrs); 4001 atomic_set(&dev->mkey_var, 0); 4002 4003 spin_lock_init(&dev->dm.lock); 4004 dev->dm.dev = mdev; 4005 return 0; 4006 4007 err_mp: 4008 mlx5_ib_cleanup_multiport_master(dev); 4009 return err; 4010 } 4011 4012 static int mlx5_ib_enable_driver(struct ib_device *dev) 4013 { 4014 struct mlx5_ib_dev *mdev = to_mdev(dev); 4015 int ret; 4016 4017 ret = mlx5_ib_test_wc(mdev); 4018 mlx5_ib_dbg(mdev, "Write-Combining %s", 4019 mdev->wc_support ? "supported" : "not supported"); 4020 4021 return ret; 4022 } 4023 4024 static const struct ib_device_ops mlx5_ib_dev_ops = { 4025 .owner = THIS_MODULE, 4026 .driver_id = RDMA_DRIVER_MLX5, 4027 .uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION, 4028 4029 .add_gid = mlx5_ib_add_gid, 4030 .alloc_mr = mlx5_ib_alloc_mr, 4031 .alloc_mr_integrity = mlx5_ib_alloc_mr_integrity, 4032 .alloc_pd = mlx5_ib_alloc_pd, 4033 .alloc_ucontext = mlx5_ib_alloc_ucontext, 4034 .attach_mcast = mlx5_ib_mcg_attach, 4035 .check_mr_status = mlx5_ib_check_mr_status, 4036 .create_ah = mlx5_ib_create_ah, 4037 .create_cq = mlx5_ib_create_cq, 4038 .create_qp = mlx5_ib_create_qp, 4039 .create_srq = mlx5_ib_create_srq, 4040 .create_user_ah = mlx5_ib_create_ah, 4041 .dealloc_pd = mlx5_ib_dealloc_pd, 4042 .dealloc_ucontext = mlx5_ib_dealloc_ucontext, 4043 .del_gid = mlx5_ib_del_gid, 4044 .dereg_mr = mlx5_ib_dereg_mr, 4045 .destroy_ah = mlx5_ib_destroy_ah, 4046 .destroy_cq = mlx5_ib_destroy_cq, 4047 .destroy_qp = mlx5_ib_destroy_qp, 4048 .destroy_srq = mlx5_ib_destroy_srq, 4049 .detach_mcast = mlx5_ib_mcg_detach, 4050 .disassociate_ucontext = mlx5_ib_disassociate_ucontext, 4051 .drain_rq = mlx5_ib_drain_rq, 4052 .drain_sq = mlx5_ib_drain_sq, 4053 .enable_driver = mlx5_ib_enable_driver, 4054 .get_dev_fw_str = get_dev_fw_str, 4055 .get_dma_mr = mlx5_ib_get_dma_mr, 4056 .get_link_layer = mlx5_ib_port_link_layer, 4057 .map_mr_sg = mlx5_ib_map_mr_sg, 4058 .map_mr_sg_pi = mlx5_ib_map_mr_sg_pi, 4059 .mmap = mlx5_ib_mmap, 4060 .mmap_free = mlx5_ib_mmap_free, 4061 .modify_cq = mlx5_ib_modify_cq, 4062 .modify_device = mlx5_ib_modify_device, 4063 .modify_port = mlx5_ib_modify_port, 4064 .modify_qp = mlx5_ib_modify_qp, 4065 .modify_srq = mlx5_ib_modify_srq, 4066 .poll_cq = mlx5_ib_poll_cq, 4067 .post_recv = mlx5_ib_post_recv_nodrain, 4068 .post_send = mlx5_ib_post_send_nodrain, 4069 .post_srq_recv = mlx5_ib_post_srq_recv, 4070 .process_mad = mlx5_ib_process_mad, 4071 .query_ah = mlx5_ib_query_ah, 4072 .query_device = mlx5_ib_query_device, 4073 .query_gid = mlx5_ib_query_gid, 4074 .query_pkey = mlx5_ib_query_pkey, 4075 .query_qp = mlx5_ib_query_qp, 4076 .query_srq = mlx5_ib_query_srq, 4077 .query_ucontext = mlx5_ib_query_ucontext, 4078 .reg_user_mr = mlx5_ib_reg_user_mr, 4079 .reg_user_mr_dmabuf = mlx5_ib_reg_user_mr_dmabuf, 4080 .req_notify_cq = mlx5_ib_arm_cq, 4081 .rereg_user_mr = mlx5_ib_rereg_user_mr, 4082 .resize_cq = mlx5_ib_resize_cq, 4083 4084 INIT_RDMA_OBJ_SIZE(ib_ah, mlx5_ib_ah, ibah), 4085 INIT_RDMA_OBJ_SIZE(ib_counters, mlx5_ib_mcounters, ibcntrs), 4086 INIT_RDMA_OBJ_SIZE(ib_cq, mlx5_ib_cq, ibcq), 4087 INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd), 4088 INIT_RDMA_OBJ_SIZE(ib_srq, mlx5_ib_srq, ibsrq), 4089 INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext), 4090 }; 4091 4092 static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = { 4093 .rdma_netdev_get_params = mlx5_ib_rn_get_params, 4094 }; 4095 4096 static const struct ib_device_ops mlx5_ib_dev_sriov_ops = { 4097 .get_vf_config = mlx5_ib_get_vf_config, 4098 .get_vf_guid = mlx5_ib_get_vf_guid, 4099 .get_vf_stats = mlx5_ib_get_vf_stats, 4100 .set_vf_guid = mlx5_ib_set_vf_guid, 4101 .set_vf_link_state = mlx5_ib_set_vf_link_state, 4102 }; 4103 4104 static const struct ib_device_ops mlx5_ib_dev_mw_ops = { 4105 .alloc_mw = mlx5_ib_alloc_mw, 4106 .dealloc_mw = mlx5_ib_dealloc_mw, 4107 4108 INIT_RDMA_OBJ_SIZE(ib_mw, mlx5_ib_mw, ibmw), 4109 }; 4110 4111 static const struct ib_device_ops mlx5_ib_dev_xrc_ops = { 4112 .alloc_xrcd = mlx5_ib_alloc_xrcd, 4113 .dealloc_xrcd = mlx5_ib_dealloc_xrcd, 4114 4115 INIT_RDMA_OBJ_SIZE(ib_xrcd, mlx5_ib_xrcd, ibxrcd), 4116 }; 4117 4118 static const struct ib_device_ops mlx5_ib_dev_dm_ops = { 4119 .alloc_dm = mlx5_ib_alloc_dm, 4120 .dealloc_dm = mlx5_ib_dealloc_dm, 4121 .reg_dm_mr = mlx5_ib_reg_dm_mr, 4122 }; 4123 4124 static int mlx5_ib_init_var_table(struct mlx5_ib_dev *dev) 4125 { 4126 struct mlx5_core_dev *mdev = dev->mdev; 4127 struct mlx5_var_table *var_table = &dev->var_table; 4128 u8 log_doorbell_bar_size; 4129 u8 log_doorbell_stride; 4130 u64 bar_size; 4131 4132 log_doorbell_bar_size = MLX5_CAP_DEV_VDPA_EMULATION(mdev, 4133 log_doorbell_bar_size); 4134 log_doorbell_stride = MLX5_CAP_DEV_VDPA_EMULATION(mdev, 4135 log_doorbell_stride); 4136 var_table->hw_start_addr = dev->mdev->bar_addr + 4137 MLX5_CAP64_DEV_VDPA_EMULATION(mdev, 4138 doorbell_bar_offset); 4139 bar_size = (1ULL << log_doorbell_bar_size) * 4096; 4140 var_table->stride_size = 1ULL << log_doorbell_stride; 4141 var_table->num_var_hw_entries = div_u64(bar_size, 4142 var_table->stride_size); 4143 mutex_init(&var_table->bitmap_lock); 4144 var_table->bitmap = bitmap_zalloc(var_table->num_var_hw_entries, 4145 GFP_KERNEL); 4146 return (var_table->bitmap) ? 0 : -ENOMEM; 4147 } 4148 4149 static void mlx5_ib_stage_caps_cleanup(struct mlx5_ib_dev *dev) 4150 { 4151 bitmap_free(dev->var_table.bitmap); 4152 } 4153 4154 static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev) 4155 { 4156 struct mlx5_core_dev *mdev = dev->mdev; 4157 int err; 4158 4159 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 4160 IS_ENABLED(CONFIG_MLX5_CORE_IPOIB)) 4161 ib_set_device_ops(&dev->ib_dev, 4162 &mlx5_ib_dev_ipoib_enhanced_ops); 4163 4164 if (mlx5_core_is_pf(mdev)) 4165 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops); 4166 4167 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence)); 4168 4169 if (MLX5_CAP_GEN(mdev, imaicl)) 4170 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops); 4171 4172 if (MLX5_CAP_GEN(mdev, xrc)) 4173 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops); 4174 4175 if (MLX5_CAP_DEV_MEM(mdev, memic) || 4176 MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 4177 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM) 4178 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops); 4179 4180 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops); 4181 4182 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)) 4183 dev->ib_dev.driver_def = mlx5_ib_defs; 4184 4185 err = init_node_data(dev); 4186 if (err) 4187 return err; 4188 4189 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && 4190 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) || 4191 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 4192 mutex_init(&dev->lb.mutex); 4193 4194 if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 4195 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) { 4196 err = mlx5_ib_init_var_table(dev); 4197 if (err) 4198 return err; 4199 } 4200 4201 dev->ib_dev.use_cq_dim = true; 4202 4203 return 0; 4204 } 4205 4206 static const struct ib_device_ops mlx5_ib_dev_port_ops = { 4207 .get_port_immutable = mlx5_port_immutable, 4208 .query_port = mlx5_ib_query_port, 4209 }; 4210 4211 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev) 4212 { 4213 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops); 4214 return 0; 4215 } 4216 4217 static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = { 4218 .get_port_immutable = mlx5_port_rep_immutable, 4219 .query_port = mlx5_ib_rep_query_port, 4220 .query_pkey = mlx5_ib_rep_query_pkey, 4221 }; 4222 4223 static int mlx5_ib_stage_raw_eth_non_default_cb(struct mlx5_ib_dev *dev) 4224 { 4225 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops); 4226 return 0; 4227 } 4228 4229 static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = { 4230 .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table, 4231 .create_wq = mlx5_ib_create_wq, 4232 .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table, 4233 .destroy_wq = mlx5_ib_destroy_wq, 4234 .get_netdev = mlx5_ib_get_netdev, 4235 .modify_wq = mlx5_ib_modify_wq, 4236 4237 INIT_RDMA_OBJ_SIZE(ib_rwq_ind_table, mlx5_ib_rwq_ind_table, 4238 ib_rwq_ind_tbl), 4239 }; 4240 4241 static int mlx5_ib_roce_init(struct mlx5_ib_dev *dev) 4242 { 4243 struct mlx5_core_dev *mdev = dev->mdev; 4244 enum rdma_link_layer ll; 4245 int port_type_cap; 4246 u8 port_num = 0; 4247 int err; 4248 4249 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4250 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4251 4252 if (ll == IB_LINK_LAYER_ETHERNET) { 4253 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops); 4254 4255 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4256 4257 /* Register only for native ports */ 4258 err = mlx5_add_netdev_notifier(dev, port_num); 4259 if (err || dev->is_rep || !mlx5_is_roce_enabled(mdev)) 4260 /* 4261 * We don't enable ETH interface for 4262 * 1. IB representors 4263 * 2. User disabled ROCE through devlink interface 4264 */ 4265 return err; 4266 4267 err = mlx5_enable_eth(dev); 4268 if (err) 4269 goto cleanup; 4270 } 4271 4272 return 0; 4273 cleanup: 4274 mlx5_remove_netdev_notifier(dev, port_num); 4275 return err; 4276 } 4277 4278 static void mlx5_ib_roce_cleanup(struct mlx5_ib_dev *dev) 4279 { 4280 struct mlx5_core_dev *mdev = dev->mdev; 4281 enum rdma_link_layer ll; 4282 int port_type_cap; 4283 u8 port_num; 4284 4285 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4286 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4287 4288 if (ll == IB_LINK_LAYER_ETHERNET) { 4289 if (!dev->is_rep) 4290 mlx5_disable_eth(dev); 4291 4292 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4293 mlx5_remove_netdev_notifier(dev, port_num); 4294 } 4295 } 4296 4297 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev) 4298 { 4299 mlx5_ib_init_cong_debugfs(dev, 4300 mlx5_core_native_port_num(dev->mdev) - 1); 4301 return 0; 4302 } 4303 4304 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev) 4305 { 4306 mlx5_ib_cleanup_cong_debugfs(dev, 4307 mlx5_core_native_port_num(dev->mdev) - 1); 4308 } 4309 4310 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev) 4311 { 4312 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev); 4313 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar); 4314 } 4315 4316 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev) 4317 { 4318 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar); 4319 } 4320 4321 static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev) 4322 { 4323 int err; 4324 4325 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false); 4326 if (err) 4327 return err; 4328 4329 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true); 4330 if (err) 4331 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4332 4333 return err; 4334 } 4335 4336 static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev) 4337 { 4338 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 4339 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4340 } 4341 4342 static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev) 4343 { 4344 const char *name; 4345 4346 rdma_set_device_sysfs_group(&dev->ib_dev, &mlx5_attr_group); 4347 if (!mlx5_lag_is_roce(dev->mdev)) 4348 name = "mlx5_%d"; 4349 else 4350 name = "mlx5_bond_%d"; 4351 return ib_register_device(&dev->ib_dev, name, &dev->mdev->pdev->dev); 4352 } 4353 4354 static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev) 4355 { 4356 int err; 4357 4358 err = mlx5_mr_cache_cleanup(dev); 4359 if (err) 4360 mlx5_ib_warn(dev, "mr cache cleanup failed\n"); 4361 4362 if (dev->umrc.qp) 4363 mlx5_ib_destroy_qp(dev->umrc.qp, NULL); 4364 if (dev->umrc.cq) 4365 ib_free_cq(dev->umrc.cq); 4366 if (dev->umrc.pd) 4367 ib_dealloc_pd(dev->umrc.pd); 4368 } 4369 4370 static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev) 4371 { 4372 ib_unregister_device(&dev->ib_dev); 4373 } 4374 4375 enum { 4376 MAX_UMR_WR = 128, 4377 }; 4378 4379 static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev) 4380 { 4381 struct ib_qp_init_attr *init_attr = NULL; 4382 struct ib_qp_attr *attr = NULL; 4383 struct ib_pd *pd; 4384 struct ib_cq *cq; 4385 struct ib_qp *qp; 4386 int ret; 4387 4388 attr = kzalloc(sizeof(*attr), GFP_KERNEL); 4389 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL); 4390 if (!attr || !init_attr) { 4391 ret = -ENOMEM; 4392 goto error_0; 4393 } 4394 4395 pd = ib_alloc_pd(&dev->ib_dev, 0); 4396 if (IS_ERR(pd)) { 4397 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n"); 4398 ret = PTR_ERR(pd); 4399 goto error_0; 4400 } 4401 4402 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ); 4403 if (IS_ERR(cq)) { 4404 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n"); 4405 ret = PTR_ERR(cq); 4406 goto error_2; 4407 } 4408 4409 init_attr->send_cq = cq; 4410 init_attr->recv_cq = cq; 4411 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR; 4412 init_attr->cap.max_send_wr = MAX_UMR_WR; 4413 init_attr->cap.max_send_sge = 1; 4414 init_attr->qp_type = MLX5_IB_QPT_REG_UMR; 4415 init_attr->port_num = 1; 4416 qp = mlx5_ib_create_qp(pd, init_attr, NULL); 4417 if (IS_ERR(qp)) { 4418 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n"); 4419 ret = PTR_ERR(qp); 4420 goto error_3; 4421 } 4422 qp->device = &dev->ib_dev; 4423 qp->real_qp = qp; 4424 qp->uobject = NULL; 4425 qp->qp_type = MLX5_IB_QPT_REG_UMR; 4426 qp->send_cq = init_attr->send_cq; 4427 qp->recv_cq = init_attr->recv_cq; 4428 4429 attr->qp_state = IB_QPS_INIT; 4430 attr->port_num = 1; 4431 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX | 4432 IB_QP_PORT, NULL); 4433 if (ret) { 4434 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n"); 4435 goto error_4; 4436 } 4437 4438 memset(attr, 0, sizeof(*attr)); 4439 attr->qp_state = IB_QPS_RTR; 4440 attr->path_mtu = IB_MTU_256; 4441 4442 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 4443 if (ret) { 4444 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n"); 4445 goto error_4; 4446 } 4447 4448 memset(attr, 0, sizeof(*attr)); 4449 attr->qp_state = IB_QPS_RTS; 4450 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 4451 if (ret) { 4452 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n"); 4453 goto error_4; 4454 } 4455 4456 dev->umrc.qp = qp; 4457 dev->umrc.cq = cq; 4458 dev->umrc.pd = pd; 4459 4460 sema_init(&dev->umrc.sem, MAX_UMR_WR); 4461 ret = mlx5_mr_cache_init(dev); 4462 if (ret) { 4463 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 4464 goto error_4; 4465 } 4466 4467 kfree(attr); 4468 kfree(init_attr); 4469 4470 return 0; 4471 4472 error_4: 4473 mlx5_ib_destroy_qp(qp, NULL); 4474 dev->umrc.qp = NULL; 4475 4476 error_3: 4477 ib_free_cq(cq); 4478 dev->umrc.cq = NULL; 4479 4480 error_2: 4481 ib_dealloc_pd(pd); 4482 dev->umrc.pd = NULL; 4483 4484 error_0: 4485 kfree(attr); 4486 kfree(init_attr); 4487 return ret; 4488 } 4489 4490 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev) 4491 { 4492 struct dentry *root; 4493 4494 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4495 return 0; 4496 4497 mutex_init(&dev->delay_drop.lock); 4498 dev->delay_drop.dev = dev; 4499 dev->delay_drop.activate = false; 4500 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000; 4501 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler); 4502 atomic_set(&dev->delay_drop.rqs_cnt, 0); 4503 atomic_set(&dev->delay_drop.events_cnt, 0); 4504 4505 if (!mlx5_debugfs_root) 4506 return 0; 4507 4508 root = debugfs_create_dir("delay_drop", dev->mdev->priv.dbg_root); 4509 dev->delay_drop.dir_debugfs = root; 4510 4511 debugfs_create_atomic_t("num_timeout_events", 0400, root, 4512 &dev->delay_drop.events_cnt); 4513 debugfs_create_atomic_t("num_rqs", 0400, root, 4514 &dev->delay_drop.rqs_cnt); 4515 debugfs_create_file("timeout", 0600, root, &dev->delay_drop, 4516 &fops_delay_drop_timeout); 4517 return 0; 4518 } 4519 4520 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev) 4521 { 4522 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4523 return; 4524 4525 cancel_work_sync(&dev->delay_drop.delay_drop_work); 4526 if (!dev->delay_drop.dir_debugfs) 4527 return; 4528 4529 debugfs_remove_recursive(dev->delay_drop.dir_debugfs); 4530 dev->delay_drop.dir_debugfs = NULL; 4531 } 4532 4533 static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev) 4534 { 4535 dev->mdev_events.notifier_call = mlx5_ib_event; 4536 mlx5_notifier_register(dev->mdev, &dev->mdev_events); 4537 return 0; 4538 } 4539 4540 static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev) 4541 { 4542 mlx5_notifier_unregister(dev->mdev, &dev->mdev_events); 4543 } 4544 4545 void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 4546 const struct mlx5_ib_profile *profile, 4547 int stage) 4548 { 4549 dev->ib_active = false; 4550 4551 /* Number of stages to cleanup */ 4552 while (stage) { 4553 stage--; 4554 if (profile->stage[stage].cleanup) 4555 profile->stage[stage].cleanup(dev); 4556 } 4557 4558 kfree(dev->port); 4559 ib_dealloc_device(&dev->ib_dev); 4560 } 4561 4562 int __mlx5_ib_add(struct mlx5_ib_dev *dev, 4563 const struct mlx5_ib_profile *profile) 4564 { 4565 int err; 4566 int i; 4567 4568 dev->profile = profile; 4569 4570 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) { 4571 if (profile->stage[i].init) { 4572 err = profile->stage[i].init(dev); 4573 if (err) 4574 goto err_out; 4575 } 4576 } 4577 4578 dev->ib_active = true; 4579 return 0; 4580 4581 err_out: 4582 /* Clean up stages which were initialized */ 4583 while (i) { 4584 i--; 4585 if (profile->stage[i].cleanup) 4586 profile->stage[i].cleanup(dev); 4587 } 4588 return -ENOMEM; 4589 } 4590 4591 static const struct mlx5_ib_profile pf_profile = { 4592 STAGE_CREATE(MLX5_IB_STAGE_INIT, 4593 mlx5_ib_stage_init_init, 4594 mlx5_ib_stage_init_cleanup), 4595 STAGE_CREATE(MLX5_IB_STAGE_FS, 4596 mlx5_ib_fs_init, 4597 mlx5_ib_fs_cleanup), 4598 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 4599 mlx5_ib_stage_caps_init, 4600 mlx5_ib_stage_caps_cleanup), 4601 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 4602 mlx5_ib_stage_non_default_cb, 4603 NULL), 4604 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 4605 mlx5_ib_roce_init, 4606 mlx5_ib_roce_cleanup), 4607 STAGE_CREATE(MLX5_IB_STAGE_QP, 4608 mlx5_init_qp_table, 4609 mlx5_cleanup_qp_table), 4610 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 4611 mlx5_init_srq_table, 4612 mlx5_cleanup_srq_table), 4613 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 4614 mlx5_ib_dev_res_init, 4615 mlx5_ib_dev_res_cleanup), 4616 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 4617 mlx5_ib_stage_dev_notifier_init, 4618 mlx5_ib_stage_dev_notifier_cleanup), 4619 STAGE_CREATE(MLX5_IB_STAGE_ODP, 4620 mlx5_ib_odp_init_one, 4621 mlx5_ib_odp_cleanup_one), 4622 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 4623 mlx5_ib_counters_init, 4624 mlx5_ib_counters_cleanup), 4625 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 4626 mlx5_ib_stage_cong_debugfs_init, 4627 mlx5_ib_stage_cong_debugfs_cleanup), 4628 STAGE_CREATE(MLX5_IB_STAGE_UAR, 4629 mlx5_ib_stage_uar_init, 4630 mlx5_ib_stage_uar_cleanup), 4631 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 4632 mlx5_ib_stage_bfrag_init, 4633 mlx5_ib_stage_bfrag_cleanup), 4634 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 4635 NULL, 4636 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 4637 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 4638 mlx5_ib_devx_init, 4639 mlx5_ib_devx_cleanup), 4640 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 4641 mlx5_ib_stage_ib_reg_init, 4642 mlx5_ib_stage_ib_reg_cleanup), 4643 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 4644 mlx5_ib_stage_post_ib_reg_umr_init, 4645 NULL), 4646 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP, 4647 mlx5_ib_stage_delay_drop_init, 4648 mlx5_ib_stage_delay_drop_cleanup), 4649 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK, 4650 mlx5_ib_restrack_init, 4651 NULL), 4652 }; 4653 4654 const struct mlx5_ib_profile raw_eth_profile = { 4655 STAGE_CREATE(MLX5_IB_STAGE_INIT, 4656 mlx5_ib_stage_init_init, 4657 mlx5_ib_stage_init_cleanup), 4658 STAGE_CREATE(MLX5_IB_STAGE_FS, 4659 mlx5_ib_fs_init, 4660 mlx5_ib_fs_cleanup), 4661 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 4662 mlx5_ib_stage_caps_init, 4663 mlx5_ib_stage_caps_cleanup), 4664 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 4665 mlx5_ib_stage_raw_eth_non_default_cb, 4666 NULL), 4667 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 4668 mlx5_ib_roce_init, 4669 mlx5_ib_roce_cleanup), 4670 STAGE_CREATE(MLX5_IB_STAGE_QP, 4671 mlx5_init_qp_table, 4672 mlx5_cleanup_qp_table), 4673 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 4674 mlx5_init_srq_table, 4675 mlx5_cleanup_srq_table), 4676 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 4677 mlx5_ib_dev_res_init, 4678 mlx5_ib_dev_res_cleanup), 4679 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 4680 mlx5_ib_stage_dev_notifier_init, 4681 mlx5_ib_stage_dev_notifier_cleanup), 4682 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 4683 mlx5_ib_counters_init, 4684 mlx5_ib_counters_cleanup), 4685 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 4686 mlx5_ib_stage_cong_debugfs_init, 4687 mlx5_ib_stage_cong_debugfs_cleanup), 4688 STAGE_CREATE(MLX5_IB_STAGE_UAR, 4689 mlx5_ib_stage_uar_init, 4690 mlx5_ib_stage_uar_cleanup), 4691 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 4692 mlx5_ib_stage_bfrag_init, 4693 mlx5_ib_stage_bfrag_cleanup), 4694 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 4695 NULL, 4696 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 4697 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 4698 mlx5_ib_devx_init, 4699 mlx5_ib_devx_cleanup), 4700 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 4701 mlx5_ib_stage_ib_reg_init, 4702 mlx5_ib_stage_ib_reg_cleanup), 4703 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 4704 mlx5_ib_stage_post_ib_reg_umr_init, 4705 NULL), 4706 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK, 4707 mlx5_ib_restrack_init, 4708 NULL), 4709 }; 4710 4711 static int mlx5r_mp_probe(struct auxiliary_device *adev, 4712 const struct auxiliary_device_id *id) 4713 { 4714 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev); 4715 struct mlx5_core_dev *mdev = idev->mdev; 4716 struct mlx5_ib_multiport_info *mpi; 4717 struct mlx5_ib_dev *dev; 4718 bool bound = false; 4719 int err; 4720 4721 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 4722 if (!mpi) 4723 return -ENOMEM; 4724 4725 mpi->mdev = mdev; 4726 err = mlx5_query_nic_vport_system_image_guid(mdev, 4727 &mpi->sys_image_guid); 4728 if (err) { 4729 kfree(mpi); 4730 return err; 4731 } 4732 4733 mutex_lock(&mlx5_ib_multiport_mutex); 4734 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) { 4735 if (dev->sys_image_guid == mpi->sys_image_guid) 4736 bound = mlx5_ib_bind_slave_port(dev, mpi); 4737 4738 if (bound) { 4739 rdma_roce_rescan_device(&dev->ib_dev); 4740 break; 4741 } 4742 } 4743 4744 if (!bound) { 4745 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 4746 dev_dbg(mdev->device, 4747 "no suitable IB device found to bind to, added to unaffiliated list.\n"); 4748 } 4749 mutex_unlock(&mlx5_ib_multiport_mutex); 4750 4751 dev_set_drvdata(&adev->dev, mpi); 4752 return 0; 4753 } 4754 4755 static void mlx5r_mp_remove(struct auxiliary_device *adev) 4756 { 4757 struct mlx5_ib_multiport_info *mpi; 4758 4759 mpi = dev_get_drvdata(&adev->dev); 4760 mutex_lock(&mlx5_ib_multiport_mutex); 4761 if (mpi->ibdev) 4762 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi); 4763 list_del(&mpi->list); 4764 mutex_unlock(&mlx5_ib_multiport_mutex); 4765 kfree(mpi); 4766 } 4767 4768 static int mlx5r_probe(struct auxiliary_device *adev, 4769 const struct auxiliary_device_id *id) 4770 { 4771 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev); 4772 struct mlx5_core_dev *mdev = idev->mdev; 4773 const struct mlx5_ib_profile *profile; 4774 int port_type_cap, num_ports, ret; 4775 enum rdma_link_layer ll; 4776 struct mlx5_ib_dev *dev; 4777 4778 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4779 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4780 4781 num_ports = max(MLX5_CAP_GEN(mdev, num_ports), 4782 MLX5_CAP_GEN(mdev, num_vhca_ports)); 4783 dev = ib_alloc_device(mlx5_ib_dev, ib_dev); 4784 if (!dev) 4785 return -ENOMEM; 4786 dev->port = kcalloc(num_ports, sizeof(*dev->port), 4787 GFP_KERNEL); 4788 if (!dev->port) { 4789 ib_dealloc_device(&dev->ib_dev); 4790 return -ENOMEM; 4791 } 4792 4793 dev->mdev = mdev; 4794 dev->num_ports = num_ports; 4795 4796 if (ll == IB_LINK_LAYER_ETHERNET && !mlx5_is_roce_enabled(mdev)) 4797 profile = &raw_eth_profile; 4798 else 4799 profile = &pf_profile; 4800 4801 ret = __mlx5_ib_add(dev, profile); 4802 if (ret) { 4803 kfree(dev->port); 4804 ib_dealloc_device(&dev->ib_dev); 4805 return ret; 4806 } 4807 4808 dev_set_drvdata(&adev->dev, dev); 4809 return 0; 4810 } 4811 4812 static void mlx5r_remove(struct auxiliary_device *adev) 4813 { 4814 struct mlx5_ib_dev *dev; 4815 4816 dev = dev_get_drvdata(&adev->dev); 4817 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX); 4818 } 4819 4820 static const struct auxiliary_device_id mlx5r_mp_id_table[] = { 4821 { .name = MLX5_ADEV_NAME ".multiport", }, 4822 {}, 4823 }; 4824 4825 static const struct auxiliary_device_id mlx5r_id_table[] = { 4826 { .name = MLX5_ADEV_NAME ".rdma", }, 4827 {}, 4828 }; 4829 4830 MODULE_DEVICE_TABLE(auxiliary, mlx5r_mp_id_table); 4831 MODULE_DEVICE_TABLE(auxiliary, mlx5r_id_table); 4832 4833 static struct auxiliary_driver mlx5r_mp_driver = { 4834 .name = "multiport", 4835 .probe = mlx5r_mp_probe, 4836 .remove = mlx5r_mp_remove, 4837 .id_table = mlx5r_mp_id_table, 4838 }; 4839 4840 static struct auxiliary_driver mlx5r_driver = { 4841 .name = "rdma", 4842 .probe = mlx5r_probe, 4843 .remove = mlx5r_remove, 4844 .id_table = mlx5r_id_table, 4845 }; 4846 4847 static int __init mlx5_ib_init(void) 4848 { 4849 int ret; 4850 4851 xlt_emergency_page = (void *)__get_free_page(GFP_KERNEL); 4852 if (!xlt_emergency_page) 4853 return -ENOMEM; 4854 4855 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0); 4856 if (!mlx5_ib_event_wq) { 4857 free_page((unsigned long)xlt_emergency_page); 4858 return -ENOMEM; 4859 } 4860 4861 mlx5_ib_odp_init(); 4862 ret = mlx5r_rep_init(); 4863 if (ret) 4864 goto rep_err; 4865 ret = auxiliary_driver_register(&mlx5r_mp_driver); 4866 if (ret) 4867 goto mp_err; 4868 ret = auxiliary_driver_register(&mlx5r_driver); 4869 if (ret) 4870 goto drv_err; 4871 return 0; 4872 4873 drv_err: 4874 auxiliary_driver_unregister(&mlx5r_mp_driver); 4875 mp_err: 4876 mlx5r_rep_cleanup(); 4877 rep_err: 4878 destroy_workqueue(mlx5_ib_event_wq); 4879 free_page((unsigned long)xlt_emergency_page); 4880 return ret; 4881 } 4882 4883 static void __exit mlx5_ib_cleanup(void) 4884 { 4885 auxiliary_driver_unregister(&mlx5r_driver); 4886 auxiliary_driver_unregister(&mlx5r_mp_driver); 4887 mlx5r_rep_cleanup(); 4888 4889 destroy_workqueue(mlx5_ib_event_wq); 4890 free_page((unsigned long)xlt_emergency_page); 4891 } 4892 4893 module_init(mlx5_ib_init); 4894 module_exit(mlx5_ib_cleanup); 4895