1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/highmem.h> 34 #include <linux/module.h> 35 #include <linux/init.h> 36 #include <linux/errno.h> 37 #include <linux/pci.h> 38 #include <linux/dma-mapping.h> 39 #include <linux/slab.h> 40 #include <linux/io-mapping.h> 41 #if defined(CONFIG_X86) 42 #include <asm/pat.h> 43 #endif 44 #include <linux/sched.h> 45 #include <rdma/ib_user_verbs.h> 46 #include <rdma/ib_addr.h> 47 #include <rdma/ib_cache.h> 48 #include <linux/mlx5/port.h> 49 #include <linux/mlx5/vport.h> 50 #include <rdma/ib_smi.h> 51 #include <rdma/ib_umem.h> 52 #include <linux/in.h> 53 #include <linux/etherdevice.h> 54 #include <linux/mlx5/fs.h> 55 #include "user.h" 56 #include "mlx5_ib.h" 57 58 #define DRIVER_NAME "mlx5_ib" 59 #define DRIVER_VERSION "2.2-1" 60 #define DRIVER_RELDATE "Feb 2014" 61 62 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 63 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver"); 64 MODULE_LICENSE("Dual BSD/GPL"); 65 MODULE_VERSION(DRIVER_VERSION); 66 67 static int deprecated_prof_sel = 2; 68 module_param_named(prof_sel, deprecated_prof_sel, int, 0444); 69 MODULE_PARM_DESC(prof_sel, "profile selector. Deprecated here. Moved to module mlx5_core"); 70 71 static char mlx5_version[] = 72 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v" 73 DRIVER_VERSION " (" DRIVER_RELDATE ")\n"; 74 75 enum { 76 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 77 }; 78 79 static enum rdma_link_layer 80 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 81 { 82 switch (port_type_cap) { 83 case MLX5_CAP_PORT_TYPE_IB: 84 return IB_LINK_LAYER_INFINIBAND; 85 case MLX5_CAP_PORT_TYPE_ETH: 86 return IB_LINK_LAYER_ETHERNET; 87 default: 88 return IB_LINK_LAYER_UNSPECIFIED; 89 } 90 } 91 92 static enum rdma_link_layer 93 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num) 94 { 95 struct mlx5_ib_dev *dev = to_mdev(device); 96 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 97 98 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 99 } 100 101 static int mlx5_netdev_event(struct notifier_block *this, 102 unsigned long event, void *ptr) 103 { 104 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 105 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev, 106 roce.nb); 107 108 if ((event != NETDEV_UNREGISTER) && (event != NETDEV_REGISTER)) 109 return NOTIFY_DONE; 110 111 write_lock(&ibdev->roce.netdev_lock); 112 if (ndev->dev.parent == &ibdev->mdev->pdev->dev) 113 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ? NULL : ndev; 114 write_unlock(&ibdev->roce.netdev_lock); 115 116 return NOTIFY_DONE; 117 } 118 119 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device, 120 u8 port_num) 121 { 122 struct mlx5_ib_dev *ibdev = to_mdev(device); 123 struct net_device *ndev; 124 125 /* Ensure ndev does not disappear before we invoke dev_hold() 126 */ 127 read_lock(&ibdev->roce.netdev_lock); 128 ndev = ibdev->roce.netdev; 129 if (ndev) 130 dev_hold(ndev); 131 read_unlock(&ibdev->roce.netdev_lock); 132 133 return ndev; 134 } 135 136 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num, 137 struct ib_port_attr *props) 138 { 139 struct mlx5_ib_dev *dev = to_mdev(device); 140 struct net_device *ndev; 141 enum ib_mtu ndev_ib_mtu; 142 u16 qkey_viol_cntr; 143 144 memset(props, 0, sizeof(*props)); 145 146 props->port_cap_flags |= IB_PORT_CM_SUP; 147 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS; 148 149 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 150 roce_address_table_size); 151 props->max_mtu = IB_MTU_4096; 152 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 153 props->pkey_tbl_len = 1; 154 props->state = IB_PORT_DOWN; 155 props->phys_state = 3; 156 157 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr); 158 props->qkey_viol_cntr = qkey_viol_cntr; 159 160 ndev = mlx5_ib_get_netdev(device, port_num); 161 if (!ndev) 162 return 0; 163 164 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 165 props->state = IB_PORT_ACTIVE; 166 props->phys_state = 5; 167 } 168 169 ndev_ib_mtu = iboe_get_mtu(ndev->mtu); 170 171 dev_put(ndev); 172 173 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 174 175 props->active_width = IB_WIDTH_4X; /* TODO */ 176 props->active_speed = IB_SPEED_QDR; /* TODO */ 177 178 return 0; 179 } 180 181 static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid, 182 const struct ib_gid_attr *attr, 183 void *mlx5_addr) 184 { 185 #define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v) 186 char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr, 187 source_l3_address); 188 void *mlx5_addr_mac = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr, 189 source_mac_47_32); 190 191 if (!gid) 192 return; 193 194 ether_addr_copy(mlx5_addr_mac, attr->ndev->dev_addr); 195 196 if (is_vlan_dev(attr->ndev)) { 197 MLX5_SET_RA(mlx5_addr, vlan_valid, 1); 198 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_dev_vlan_id(attr->ndev)); 199 } 200 201 switch (attr->gid_type) { 202 case IB_GID_TYPE_IB: 203 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1); 204 break; 205 case IB_GID_TYPE_ROCE_UDP_ENCAP: 206 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2); 207 break; 208 209 default: 210 WARN_ON(true); 211 } 212 213 if (attr->gid_type != IB_GID_TYPE_IB) { 214 if (ipv6_addr_v4mapped((void *)gid)) 215 MLX5_SET_RA(mlx5_addr, roce_l3_type, 216 MLX5_ROCE_L3_TYPE_IPV4); 217 else 218 MLX5_SET_RA(mlx5_addr, roce_l3_type, 219 MLX5_ROCE_L3_TYPE_IPV6); 220 } 221 222 if ((attr->gid_type == IB_GID_TYPE_IB) || 223 !ipv6_addr_v4mapped((void *)gid)) 224 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid)); 225 else 226 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4); 227 } 228 229 static int set_roce_addr(struct ib_device *device, u8 port_num, 230 unsigned int index, 231 const union ib_gid *gid, 232 const struct ib_gid_attr *attr) 233 { 234 struct mlx5_ib_dev *dev = to_mdev(device); 235 u32 in[MLX5_ST_SZ_DW(set_roce_address_in)]; 236 u32 out[MLX5_ST_SZ_DW(set_roce_address_out)]; 237 void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address); 238 enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num); 239 240 if (ll != IB_LINK_LAYER_ETHERNET) 241 return -EINVAL; 242 243 memset(in, 0, sizeof(in)); 244 245 ib_gid_to_mlx5_roce_addr(gid, attr, in_addr); 246 247 MLX5_SET(set_roce_address_in, in, roce_address_index, index); 248 MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS); 249 250 memset(out, 0, sizeof(out)); 251 return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out)); 252 } 253 254 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num, 255 unsigned int index, const union ib_gid *gid, 256 const struct ib_gid_attr *attr, 257 __always_unused void **context) 258 { 259 return set_roce_addr(device, port_num, index, gid, attr); 260 } 261 262 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num, 263 unsigned int index, __always_unused void **context) 264 { 265 return set_roce_addr(device, port_num, index, NULL, NULL); 266 } 267 268 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num, 269 int index) 270 { 271 struct ib_gid_attr attr; 272 union ib_gid gid; 273 274 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr)) 275 return 0; 276 277 if (!attr.ndev) 278 return 0; 279 280 dev_put(attr.ndev); 281 282 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 283 return 0; 284 285 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 286 } 287 288 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 289 { 290 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 291 } 292 293 enum { 294 MLX5_VPORT_ACCESS_METHOD_MAD, 295 MLX5_VPORT_ACCESS_METHOD_HCA, 296 MLX5_VPORT_ACCESS_METHOD_NIC, 297 }; 298 299 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 300 { 301 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 302 return MLX5_VPORT_ACCESS_METHOD_MAD; 303 304 if (mlx5_ib_port_link_layer(ibdev, 1) == 305 IB_LINK_LAYER_ETHERNET) 306 return MLX5_VPORT_ACCESS_METHOD_NIC; 307 308 return MLX5_VPORT_ACCESS_METHOD_HCA; 309 } 310 311 static void get_atomic_caps(struct mlx5_ib_dev *dev, 312 struct ib_device_attr *props) 313 { 314 u8 tmp; 315 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 316 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 317 u8 atomic_req_8B_endianness_mode = 318 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode); 319 320 /* Check if HW supports 8 bytes standard atomic operations and capable 321 * of host endianness respond 322 */ 323 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 324 if (((atomic_operations & tmp) == tmp) && 325 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 326 (atomic_req_8B_endianness_mode)) { 327 props->atomic_cap = IB_ATOMIC_HCA; 328 } else { 329 props->atomic_cap = IB_ATOMIC_NONE; 330 } 331 } 332 333 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 334 __be64 *sys_image_guid) 335 { 336 struct mlx5_ib_dev *dev = to_mdev(ibdev); 337 struct mlx5_core_dev *mdev = dev->mdev; 338 u64 tmp; 339 int err; 340 341 switch (mlx5_get_vport_access_method(ibdev)) { 342 case MLX5_VPORT_ACCESS_METHOD_MAD: 343 return mlx5_query_mad_ifc_system_image_guid(ibdev, 344 sys_image_guid); 345 346 case MLX5_VPORT_ACCESS_METHOD_HCA: 347 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 348 break; 349 350 case MLX5_VPORT_ACCESS_METHOD_NIC: 351 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 352 break; 353 354 default: 355 return -EINVAL; 356 } 357 358 if (!err) 359 *sys_image_guid = cpu_to_be64(tmp); 360 361 return err; 362 363 } 364 365 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 366 u16 *max_pkeys) 367 { 368 struct mlx5_ib_dev *dev = to_mdev(ibdev); 369 struct mlx5_core_dev *mdev = dev->mdev; 370 371 switch (mlx5_get_vport_access_method(ibdev)) { 372 case MLX5_VPORT_ACCESS_METHOD_MAD: 373 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 374 375 case MLX5_VPORT_ACCESS_METHOD_HCA: 376 case MLX5_VPORT_ACCESS_METHOD_NIC: 377 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 378 pkey_table_size)); 379 return 0; 380 381 default: 382 return -EINVAL; 383 } 384 } 385 386 static int mlx5_query_vendor_id(struct ib_device *ibdev, 387 u32 *vendor_id) 388 { 389 struct mlx5_ib_dev *dev = to_mdev(ibdev); 390 391 switch (mlx5_get_vport_access_method(ibdev)) { 392 case MLX5_VPORT_ACCESS_METHOD_MAD: 393 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 394 395 case MLX5_VPORT_ACCESS_METHOD_HCA: 396 case MLX5_VPORT_ACCESS_METHOD_NIC: 397 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 398 399 default: 400 return -EINVAL; 401 } 402 } 403 404 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 405 __be64 *node_guid) 406 { 407 u64 tmp; 408 int err; 409 410 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 411 case MLX5_VPORT_ACCESS_METHOD_MAD: 412 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 413 414 case MLX5_VPORT_ACCESS_METHOD_HCA: 415 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 416 break; 417 418 case MLX5_VPORT_ACCESS_METHOD_NIC: 419 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 420 break; 421 422 default: 423 return -EINVAL; 424 } 425 426 if (!err) 427 *node_guid = cpu_to_be64(tmp); 428 429 return err; 430 } 431 432 struct mlx5_reg_node_desc { 433 u8 desc[64]; 434 }; 435 436 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 437 { 438 struct mlx5_reg_node_desc in; 439 440 if (mlx5_use_mad_ifc(dev)) 441 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 442 443 memset(&in, 0, sizeof(in)); 444 445 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 446 sizeof(struct mlx5_reg_node_desc), 447 MLX5_REG_NODE_DESC, 0, 0); 448 } 449 450 static int mlx5_ib_query_device(struct ib_device *ibdev, 451 struct ib_device_attr *props, 452 struct ib_udata *uhw) 453 { 454 struct mlx5_ib_dev *dev = to_mdev(ibdev); 455 struct mlx5_core_dev *mdev = dev->mdev; 456 int err = -ENOMEM; 457 int max_rq_sg; 458 int max_sq_sg; 459 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 460 461 if (uhw->inlen || uhw->outlen) 462 return -EINVAL; 463 464 memset(props, 0, sizeof(*props)); 465 err = mlx5_query_system_image_guid(ibdev, 466 &props->sys_image_guid); 467 if (err) 468 return err; 469 470 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys); 471 if (err) 472 return err; 473 474 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 475 if (err) 476 return err; 477 478 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 479 (fw_rev_min(dev->mdev) << 16) | 480 fw_rev_sub(dev->mdev); 481 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 482 IB_DEVICE_PORT_ACTIVE_EVENT | 483 IB_DEVICE_SYS_IMAGE_GUID | 484 IB_DEVICE_RC_RNR_NAK_GEN; 485 486 if (MLX5_CAP_GEN(mdev, pkv)) 487 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 488 if (MLX5_CAP_GEN(mdev, qkv)) 489 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 490 if (MLX5_CAP_GEN(mdev, apm)) 491 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 492 if (MLX5_CAP_GEN(mdev, xrc)) 493 props->device_cap_flags |= IB_DEVICE_XRC; 494 if (MLX5_CAP_GEN(mdev, imaicl)) { 495 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 496 IB_DEVICE_MEM_WINDOW_TYPE_2B; 497 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 498 /* We support 'Gappy' memory registration too */ 499 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG; 500 } 501 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 502 if (MLX5_CAP_GEN(mdev, sho)) { 503 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER; 504 /* At this stage no support for signature handover */ 505 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 506 IB_PROT_T10DIF_TYPE_2 | 507 IB_PROT_T10DIF_TYPE_3; 508 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 509 IB_GUARD_T10DIF_CSUM; 510 } 511 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 512 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 513 514 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 515 (MLX5_CAP_ETH(dev->mdev, csum_cap))) 516 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 517 518 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 519 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 520 props->device_cap_flags |= IB_DEVICE_UD_TSO; 521 } 522 523 props->vendor_part_id = mdev->pdev->device; 524 props->hw_ver = mdev->pdev->revision; 525 526 props->max_mr_size = ~0ull; 527 props->page_size_cap = ~(min_page_size - 1); 528 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 529 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 530 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 531 sizeof(struct mlx5_wqe_data_seg); 532 max_sq_sg = (MLX5_CAP_GEN(mdev, max_wqe_sz_sq) - 533 sizeof(struct mlx5_wqe_ctrl_seg)) / 534 sizeof(struct mlx5_wqe_data_seg); 535 props->max_sge = min(max_rq_sg, max_sq_sg); 536 props->max_sge_rd = MLX5_MAX_SGE_RD; 537 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 538 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 539 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 540 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 541 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 542 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 543 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 544 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 545 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 546 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 547 props->max_srq_sge = max_rq_sg - 1; 548 props->max_fast_reg_page_list_len = 549 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 550 get_atomic_caps(dev, props); 551 props->masked_atomic_cap = IB_ATOMIC_NONE; 552 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 553 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 554 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 555 props->max_mcast_grp; 556 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */ 557 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 558 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 559 560 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 561 if (MLX5_CAP_GEN(mdev, pg)) 562 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING; 563 props->odp_caps = dev->odp_caps; 564 #endif 565 566 if (MLX5_CAP_GEN(mdev, cd)) 567 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL; 568 569 if (!mlx5_core_is_pf(mdev)) 570 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION; 571 572 return 0; 573 } 574 575 enum mlx5_ib_width { 576 MLX5_IB_WIDTH_1X = 1 << 0, 577 MLX5_IB_WIDTH_2X = 1 << 1, 578 MLX5_IB_WIDTH_4X = 1 << 2, 579 MLX5_IB_WIDTH_8X = 1 << 3, 580 MLX5_IB_WIDTH_12X = 1 << 4 581 }; 582 583 static int translate_active_width(struct ib_device *ibdev, u8 active_width, 584 u8 *ib_width) 585 { 586 struct mlx5_ib_dev *dev = to_mdev(ibdev); 587 int err = 0; 588 589 if (active_width & MLX5_IB_WIDTH_1X) { 590 *ib_width = IB_WIDTH_1X; 591 } else if (active_width & MLX5_IB_WIDTH_2X) { 592 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n", 593 (int)active_width); 594 err = -EINVAL; 595 } else if (active_width & MLX5_IB_WIDTH_4X) { 596 *ib_width = IB_WIDTH_4X; 597 } else if (active_width & MLX5_IB_WIDTH_8X) { 598 *ib_width = IB_WIDTH_8X; 599 } else if (active_width & MLX5_IB_WIDTH_12X) { 600 *ib_width = IB_WIDTH_12X; 601 } else { 602 mlx5_ib_dbg(dev, "Invalid active_width %d\n", 603 (int)active_width); 604 err = -EINVAL; 605 } 606 607 return err; 608 } 609 610 static int mlx5_mtu_to_ib_mtu(int mtu) 611 { 612 switch (mtu) { 613 case 256: return 1; 614 case 512: return 2; 615 case 1024: return 3; 616 case 2048: return 4; 617 case 4096: return 5; 618 default: 619 pr_warn("invalid mtu\n"); 620 return -1; 621 } 622 } 623 624 enum ib_max_vl_num { 625 __IB_MAX_VL_0 = 1, 626 __IB_MAX_VL_0_1 = 2, 627 __IB_MAX_VL_0_3 = 3, 628 __IB_MAX_VL_0_7 = 4, 629 __IB_MAX_VL_0_14 = 5, 630 }; 631 632 enum mlx5_vl_hw_cap { 633 MLX5_VL_HW_0 = 1, 634 MLX5_VL_HW_0_1 = 2, 635 MLX5_VL_HW_0_2 = 3, 636 MLX5_VL_HW_0_3 = 4, 637 MLX5_VL_HW_0_4 = 5, 638 MLX5_VL_HW_0_5 = 6, 639 MLX5_VL_HW_0_6 = 7, 640 MLX5_VL_HW_0_7 = 8, 641 MLX5_VL_HW_0_14 = 15 642 }; 643 644 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 645 u8 *max_vl_num) 646 { 647 switch (vl_hw_cap) { 648 case MLX5_VL_HW_0: 649 *max_vl_num = __IB_MAX_VL_0; 650 break; 651 case MLX5_VL_HW_0_1: 652 *max_vl_num = __IB_MAX_VL_0_1; 653 break; 654 case MLX5_VL_HW_0_3: 655 *max_vl_num = __IB_MAX_VL_0_3; 656 break; 657 case MLX5_VL_HW_0_7: 658 *max_vl_num = __IB_MAX_VL_0_7; 659 break; 660 case MLX5_VL_HW_0_14: 661 *max_vl_num = __IB_MAX_VL_0_14; 662 break; 663 664 default: 665 return -EINVAL; 666 } 667 668 return 0; 669 } 670 671 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port, 672 struct ib_port_attr *props) 673 { 674 struct mlx5_ib_dev *dev = to_mdev(ibdev); 675 struct mlx5_core_dev *mdev = dev->mdev; 676 struct mlx5_hca_vport_context *rep; 677 u16 max_mtu; 678 u16 oper_mtu; 679 int err; 680 u8 ib_link_width_oper; 681 u8 vl_hw_cap; 682 683 rep = kzalloc(sizeof(*rep), GFP_KERNEL); 684 if (!rep) { 685 err = -ENOMEM; 686 goto out; 687 } 688 689 memset(props, 0, sizeof(*props)); 690 691 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); 692 if (err) 693 goto out; 694 695 props->lid = rep->lid; 696 props->lmc = rep->lmc; 697 props->sm_lid = rep->sm_lid; 698 props->sm_sl = rep->sm_sl; 699 props->state = rep->vport_state; 700 props->phys_state = rep->port_physical_state; 701 props->port_cap_flags = rep->cap_mask1; 702 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 703 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 704 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 705 props->bad_pkey_cntr = rep->pkey_violation_counter; 706 props->qkey_viol_cntr = rep->qkey_violation_counter; 707 props->subnet_timeout = rep->subnet_timeout; 708 props->init_type_reply = rep->init_type_reply; 709 props->grh_required = rep->grh_required; 710 711 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port); 712 if (err) 713 goto out; 714 715 err = translate_active_width(ibdev, ib_link_width_oper, 716 &props->active_width); 717 if (err) 718 goto out; 719 err = mlx5_query_port_proto_oper(mdev, &props->active_speed, MLX5_PTYS_IB, 720 port); 721 if (err) 722 goto out; 723 724 mlx5_query_port_max_mtu(mdev, &max_mtu, port); 725 726 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); 727 728 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); 729 730 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); 731 732 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); 733 if (err) 734 goto out; 735 736 err = translate_max_vl_num(ibdev, vl_hw_cap, 737 &props->max_vl_num); 738 out: 739 kfree(rep); 740 return err; 741 } 742 743 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 744 struct ib_port_attr *props) 745 { 746 switch (mlx5_get_vport_access_method(ibdev)) { 747 case MLX5_VPORT_ACCESS_METHOD_MAD: 748 return mlx5_query_mad_ifc_port(ibdev, port, props); 749 750 case MLX5_VPORT_ACCESS_METHOD_HCA: 751 return mlx5_query_hca_port(ibdev, port, props); 752 753 case MLX5_VPORT_ACCESS_METHOD_NIC: 754 return mlx5_query_port_roce(ibdev, port, props); 755 756 default: 757 return -EINVAL; 758 } 759 } 760 761 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 762 union ib_gid *gid) 763 { 764 struct mlx5_ib_dev *dev = to_mdev(ibdev); 765 struct mlx5_core_dev *mdev = dev->mdev; 766 767 switch (mlx5_get_vport_access_method(ibdev)) { 768 case MLX5_VPORT_ACCESS_METHOD_MAD: 769 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 770 771 case MLX5_VPORT_ACCESS_METHOD_HCA: 772 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); 773 774 default: 775 return -EINVAL; 776 } 777 778 } 779 780 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 781 u16 *pkey) 782 { 783 struct mlx5_ib_dev *dev = to_mdev(ibdev); 784 struct mlx5_core_dev *mdev = dev->mdev; 785 786 switch (mlx5_get_vport_access_method(ibdev)) { 787 case MLX5_VPORT_ACCESS_METHOD_MAD: 788 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 789 790 case MLX5_VPORT_ACCESS_METHOD_HCA: 791 case MLX5_VPORT_ACCESS_METHOD_NIC: 792 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index, 793 pkey); 794 default: 795 return -EINVAL; 796 } 797 } 798 799 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 800 struct ib_device_modify *props) 801 { 802 struct mlx5_ib_dev *dev = to_mdev(ibdev); 803 struct mlx5_reg_node_desc in; 804 struct mlx5_reg_node_desc out; 805 int err; 806 807 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 808 return -EOPNOTSUPP; 809 810 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 811 return 0; 812 813 /* 814 * If possible, pass node desc to FW, so it can generate 815 * a 144 trap. If cmd fails, just ignore. 816 */ 817 memcpy(&in, props->node_desc, 64); 818 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 819 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 820 if (err) 821 return err; 822 823 memcpy(ibdev->node_desc, props->node_desc, 64); 824 825 return err; 826 } 827 828 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, 829 struct ib_port_modify *props) 830 { 831 struct mlx5_ib_dev *dev = to_mdev(ibdev); 832 struct ib_port_attr attr; 833 u32 tmp; 834 int err; 835 836 mutex_lock(&dev->cap_mask_mutex); 837 838 err = mlx5_ib_query_port(ibdev, port, &attr); 839 if (err) 840 goto out; 841 842 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 843 ~props->clr_port_cap_mask; 844 845 err = mlx5_set_port_caps(dev->mdev, port, tmp); 846 847 out: 848 mutex_unlock(&dev->cap_mask_mutex); 849 return err; 850 } 851 852 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev, 853 struct ib_udata *udata) 854 { 855 struct mlx5_ib_dev *dev = to_mdev(ibdev); 856 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 857 struct mlx5_ib_alloc_ucontext_resp resp = {}; 858 struct mlx5_ib_ucontext *context; 859 struct mlx5_uuar_info *uuari; 860 struct mlx5_uar *uars; 861 int gross_uuars; 862 int num_uars; 863 int ver; 864 int uuarn; 865 int err; 866 int i; 867 size_t reqlen; 868 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 869 max_cqe_version); 870 871 if (!dev->ib_active) 872 return ERR_PTR(-EAGAIN); 873 874 if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr)) 875 return ERR_PTR(-EINVAL); 876 877 reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr); 878 if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 879 ver = 0; 880 else if (reqlen >= min_req_v2) 881 ver = 2; 882 else 883 return ERR_PTR(-EINVAL); 884 885 err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req))); 886 if (err) 887 return ERR_PTR(err); 888 889 if (req.flags) 890 return ERR_PTR(-EINVAL); 891 892 if (req.total_num_uuars > MLX5_MAX_UUARS) 893 return ERR_PTR(-ENOMEM); 894 895 if (req.total_num_uuars == 0) 896 return ERR_PTR(-EINVAL); 897 898 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 899 return ERR_PTR(-EOPNOTSUPP); 900 901 if (reqlen > sizeof(req) && 902 !ib_is_udata_cleared(udata, sizeof(req), 903 reqlen - sizeof(req))) 904 return ERR_PTR(-EOPNOTSUPP); 905 906 req.total_num_uuars = ALIGN(req.total_num_uuars, 907 MLX5_NON_FP_BF_REGS_PER_PAGE); 908 if (req.num_low_latency_uuars > req.total_num_uuars - 1) 909 return ERR_PTR(-EINVAL); 910 911 num_uars = req.total_num_uuars / MLX5_NON_FP_BF_REGS_PER_PAGE; 912 gross_uuars = num_uars * MLX5_BF_REGS_PER_PAGE; 913 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 914 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size); 915 resp.cache_line_size = L1_CACHE_BYTES; 916 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 917 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 918 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 919 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 920 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 921 resp.cqe_version = min_t(__u8, 922 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 923 req.max_cqe_version); 924 resp.response_length = min(offsetof(typeof(resp), response_length) + 925 sizeof(resp.response_length), udata->outlen); 926 927 context = kzalloc(sizeof(*context), GFP_KERNEL); 928 if (!context) 929 return ERR_PTR(-ENOMEM); 930 931 uuari = &context->uuari; 932 mutex_init(&uuari->lock); 933 uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL); 934 if (!uars) { 935 err = -ENOMEM; 936 goto out_ctx; 937 } 938 939 uuari->bitmap = kcalloc(BITS_TO_LONGS(gross_uuars), 940 sizeof(*uuari->bitmap), 941 GFP_KERNEL); 942 if (!uuari->bitmap) { 943 err = -ENOMEM; 944 goto out_uar_ctx; 945 } 946 /* 947 * clear all fast path uuars 948 */ 949 for (i = 0; i < gross_uuars; i++) { 950 uuarn = i & 3; 951 if (uuarn == 2 || uuarn == 3) 952 set_bit(i, uuari->bitmap); 953 } 954 955 uuari->count = kcalloc(gross_uuars, sizeof(*uuari->count), GFP_KERNEL); 956 if (!uuari->count) { 957 err = -ENOMEM; 958 goto out_bitmap; 959 } 960 961 for (i = 0; i < num_uars; i++) { 962 err = mlx5_cmd_alloc_uar(dev->mdev, &uars[i].index); 963 if (err) 964 goto out_count; 965 } 966 967 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 968 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range; 969 #endif 970 971 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) { 972 err = mlx5_core_alloc_transport_domain(dev->mdev, 973 &context->tdn); 974 if (err) 975 goto out_uars; 976 } 977 978 INIT_LIST_HEAD(&context->db_page_list); 979 mutex_init(&context->db_page_mutex); 980 981 resp.tot_uuars = req.total_num_uuars; 982 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports); 983 984 if (field_avail(typeof(resp), cqe_version, udata->outlen)) 985 resp.response_length += sizeof(resp.cqe_version); 986 987 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) { 988 resp.comp_mask |= 989 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 990 resp.hca_core_clock_offset = 991 offsetof(struct mlx5_init_seg, internal_timer_h) % 992 PAGE_SIZE; 993 resp.response_length += sizeof(resp.hca_core_clock_offset) + 994 sizeof(resp.reserved2) + 995 sizeof(resp.reserved3); 996 } 997 998 err = ib_copy_to_udata(udata, &resp, resp.response_length); 999 if (err) 1000 goto out_td; 1001 1002 uuari->ver = ver; 1003 uuari->num_low_latency_uuars = req.num_low_latency_uuars; 1004 uuari->uars = uars; 1005 uuari->num_uars = num_uars; 1006 context->cqe_version = resp.cqe_version; 1007 1008 return &context->ibucontext; 1009 1010 out_td: 1011 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1012 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn); 1013 1014 out_uars: 1015 for (i--; i >= 0; i--) 1016 mlx5_cmd_free_uar(dev->mdev, uars[i].index); 1017 out_count: 1018 kfree(uuari->count); 1019 1020 out_bitmap: 1021 kfree(uuari->bitmap); 1022 1023 out_uar_ctx: 1024 kfree(uars); 1025 1026 out_ctx: 1027 kfree(context); 1028 return ERR_PTR(err); 1029 } 1030 1031 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1032 { 1033 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1034 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1035 struct mlx5_uuar_info *uuari = &context->uuari; 1036 int i; 1037 1038 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1039 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn); 1040 1041 for (i = 0; i < uuari->num_uars; i++) { 1042 if (mlx5_cmd_free_uar(dev->mdev, uuari->uars[i].index)) 1043 mlx5_ib_warn(dev, "failed to free UAR 0x%x\n", uuari->uars[i].index); 1044 } 1045 1046 kfree(uuari->count); 1047 kfree(uuari->bitmap); 1048 kfree(uuari->uars); 1049 kfree(context); 1050 1051 return 0; 1052 } 1053 1054 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index) 1055 { 1056 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + index; 1057 } 1058 1059 static int get_command(unsigned long offset) 1060 { 1061 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 1062 } 1063 1064 static int get_arg(unsigned long offset) 1065 { 1066 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 1067 } 1068 1069 static int get_index(unsigned long offset) 1070 { 1071 return get_arg(offset); 1072 } 1073 1074 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 1075 { 1076 switch (cmd) { 1077 case MLX5_IB_MMAP_WC_PAGE: 1078 return "WC"; 1079 case MLX5_IB_MMAP_REGULAR_PAGE: 1080 return "best effort WC"; 1081 case MLX5_IB_MMAP_NC_PAGE: 1082 return "NC"; 1083 default: 1084 return NULL; 1085 } 1086 } 1087 1088 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 1089 struct vm_area_struct *vma, struct mlx5_uuar_info *uuari) 1090 { 1091 int err; 1092 unsigned long idx; 1093 phys_addr_t pfn, pa; 1094 pgprot_t prot; 1095 1096 switch (cmd) { 1097 case MLX5_IB_MMAP_WC_PAGE: 1098 /* Some architectures don't support WC memory */ 1099 #if defined(CONFIG_X86) 1100 if (!pat_enabled()) 1101 return -EPERM; 1102 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU))) 1103 return -EPERM; 1104 #endif 1105 /* fall through */ 1106 case MLX5_IB_MMAP_REGULAR_PAGE: 1107 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 1108 prot = pgprot_writecombine(vma->vm_page_prot); 1109 break; 1110 case MLX5_IB_MMAP_NC_PAGE: 1111 prot = pgprot_noncached(vma->vm_page_prot); 1112 break; 1113 default: 1114 return -EINVAL; 1115 } 1116 1117 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1118 return -EINVAL; 1119 1120 idx = get_index(vma->vm_pgoff); 1121 if (idx >= uuari->num_uars) 1122 return -EINVAL; 1123 1124 pfn = uar_index2pfn(dev, uuari->uars[idx].index); 1125 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 1126 1127 vma->vm_page_prot = prot; 1128 err = io_remap_pfn_range(vma, vma->vm_start, pfn, 1129 PAGE_SIZE, vma->vm_page_prot); 1130 if (err) { 1131 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n", 1132 err, vma->vm_start, &pfn, mmap_cmd2str(cmd)); 1133 return -EAGAIN; 1134 } 1135 1136 pa = pfn << PAGE_SHIFT; 1137 mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd), 1138 vma->vm_start, &pa); 1139 1140 return 0; 1141 } 1142 1143 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 1144 { 1145 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1146 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1147 struct mlx5_uuar_info *uuari = &context->uuari; 1148 unsigned long command; 1149 phys_addr_t pfn; 1150 1151 command = get_command(vma->vm_pgoff); 1152 switch (command) { 1153 case MLX5_IB_MMAP_WC_PAGE: 1154 case MLX5_IB_MMAP_NC_PAGE: 1155 case MLX5_IB_MMAP_REGULAR_PAGE: 1156 return uar_mmap(dev, command, vma, uuari); 1157 1158 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 1159 return -ENOSYS; 1160 1161 case MLX5_IB_MMAP_CORE_CLOCK: 1162 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1163 return -EINVAL; 1164 1165 if (vma->vm_flags & VM_WRITE) 1166 return -EPERM; 1167 1168 /* Don't expose to user-space information it shouldn't have */ 1169 if (PAGE_SIZE > 4096) 1170 return -EOPNOTSUPP; 1171 1172 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 1173 pfn = (dev->mdev->iseg_base + 1174 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 1175 PAGE_SHIFT; 1176 if (io_remap_pfn_range(vma, vma->vm_start, pfn, 1177 PAGE_SIZE, vma->vm_page_prot)) 1178 return -EAGAIN; 1179 1180 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n", 1181 vma->vm_start, 1182 (unsigned long long)pfn << PAGE_SHIFT); 1183 break; 1184 1185 default: 1186 return -EINVAL; 1187 } 1188 1189 return 0; 1190 } 1191 1192 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev, 1193 struct ib_ucontext *context, 1194 struct ib_udata *udata) 1195 { 1196 struct mlx5_ib_alloc_pd_resp resp; 1197 struct mlx5_ib_pd *pd; 1198 int err; 1199 1200 pd = kmalloc(sizeof(*pd), GFP_KERNEL); 1201 if (!pd) 1202 return ERR_PTR(-ENOMEM); 1203 1204 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn); 1205 if (err) { 1206 kfree(pd); 1207 return ERR_PTR(err); 1208 } 1209 1210 if (context) { 1211 resp.pdn = pd->pdn; 1212 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 1213 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn); 1214 kfree(pd); 1215 return ERR_PTR(-EFAULT); 1216 } 1217 } 1218 1219 return &pd->ibpd; 1220 } 1221 1222 static int mlx5_ib_dealloc_pd(struct ib_pd *pd) 1223 { 1224 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 1225 struct mlx5_ib_pd *mpd = to_mpd(pd); 1226 1227 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn); 1228 kfree(mpd); 1229 1230 return 0; 1231 } 1232 1233 static bool outer_header_zero(u32 *match_criteria) 1234 { 1235 int size = MLX5_ST_SZ_BYTES(fte_match_param); 1236 char *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_criteria, 1237 outer_headers); 1238 1239 return outer_headers_c[0] == 0 && !memcmp(outer_headers_c, 1240 outer_headers_c + 1, 1241 size - 1); 1242 } 1243 1244 static int parse_flow_attr(u32 *match_c, u32 *match_v, 1245 union ib_flow_spec *ib_spec) 1246 { 1247 void *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 1248 outer_headers); 1249 void *outer_headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 1250 outer_headers); 1251 switch (ib_spec->type) { 1252 case IB_FLOW_SPEC_ETH: 1253 if (ib_spec->size != sizeof(ib_spec->eth)) 1254 return -EINVAL; 1255 1256 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1257 dmac_47_16), 1258 ib_spec->eth.mask.dst_mac); 1259 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1260 dmac_47_16), 1261 ib_spec->eth.val.dst_mac); 1262 1263 if (ib_spec->eth.mask.vlan_tag) { 1264 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1265 vlan_tag, 1); 1266 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1267 vlan_tag, 1); 1268 1269 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1270 first_vid, ntohs(ib_spec->eth.mask.vlan_tag)); 1271 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1272 first_vid, ntohs(ib_spec->eth.val.vlan_tag)); 1273 1274 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1275 first_cfi, 1276 ntohs(ib_spec->eth.mask.vlan_tag) >> 12); 1277 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1278 first_cfi, 1279 ntohs(ib_spec->eth.val.vlan_tag) >> 12); 1280 1281 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1282 first_prio, 1283 ntohs(ib_spec->eth.mask.vlan_tag) >> 13); 1284 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1285 first_prio, 1286 ntohs(ib_spec->eth.val.vlan_tag) >> 13); 1287 } 1288 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1289 ethertype, ntohs(ib_spec->eth.mask.ether_type)); 1290 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1291 ethertype, ntohs(ib_spec->eth.val.ether_type)); 1292 break; 1293 case IB_FLOW_SPEC_IPV4: 1294 if (ib_spec->size != sizeof(ib_spec->ipv4)) 1295 return -EINVAL; 1296 1297 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1298 ethertype, 0xffff); 1299 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1300 ethertype, ETH_P_IP); 1301 1302 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1303 src_ipv4_src_ipv6.ipv4_layout.ipv4), 1304 &ib_spec->ipv4.mask.src_ip, 1305 sizeof(ib_spec->ipv4.mask.src_ip)); 1306 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1307 src_ipv4_src_ipv6.ipv4_layout.ipv4), 1308 &ib_spec->ipv4.val.src_ip, 1309 sizeof(ib_spec->ipv4.val.src_ip)); 1310 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1311 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 1312 &ib_spec->ipv4.mask.dst_ip, 1313 sizeof(ib_spec->ipv4.mask.dst_ip)); 1314 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1315 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 1316 &ib_spec->ipv4.val.dst_ip, 1317 sizeof(ib_spec->ipv4.val.dst_ip)); 1318 break; 1319 case IB_FLOW_SPEC_TCP: 1320 if (ib_spec->size != sizeof(ib_spec->tcp_udp)) 1321 return -EINVAL; 1322 1323 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol, 1324 0xff); 1325 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol, 1326 IPPROTO_TCP); 1327 1328 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_sport, 1329 ntohs(ib_spec->tcp_udp.mask.src_port)); 1330 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_sport, 1331 ntohs(ib_spec->tcp_udp.val.src_port)); 1332 1333 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_dport, 1334 ntohs(ib_spec->tcp_udp.mask.dst_port)); 1335 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_dport, 1336 ntohs(ib_spec->tcp_udp.val.dst_port)); 1337 break; 1338 case IB_FLOW_SPEC_UDP: 1339 if (ib_spec->size != sizeof(ib_spec->tcp_udp)) 1340 return -EINVAL; 1341 1342 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol, 1343 0xff); 1344 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol, 1345 IPPROTO_UDP); 1346 1347 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_sport, 1348 ntohs(ib_spec->tcp_udp.mask.src_port)); 1349 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_sport, 1350 ntohs(ib_spec->tcp_udp.val.src_port)); 1351 1352 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_dport, 1353 ntohs(ib_spec->tcp_udp.mask.dst_port)); 1354 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_dport, 1355 ntohs(ib_spec->tcp_udp.val.dst_port)); 1356 break; 1357 default: 1358 return -EINVAL; 1359 } 1360 1361 return 0; 1362 } 1363 1364 /* If a flow could catch both multicast and unicast packets, 1365 * it won't fall into the multicast flow steering table and this rule 1366 * could steal other multicast packets. 1367 */ 1368 static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr) 1369 { 1370 struct ib_flow_spec_eth *eth_spec; 1371 1372 if (ib_attr->type != IB_FLOW_ATTR_NORMAL || 1373 ib_attr->size < sizeof(struct ib_flow_attr) + 1374 sizeof(struct ib_flow_spec_eth) || 1375 ib_attr->num_of_specs < 1) 1376 return false; 1377 1378 eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1); 1379 if (eth_spec->type != IB_FLOW_SPEC_ETH || 1380 eth_spec->size != sizeof(*eth_spec)) 1381 return false; 1382 1383 return is_multicast_ether_addr(eth_spec->mask.dst_mac) && 1384 is_multicast_ether_addr(eth_spec->val.dst_mac); 1385 } 1386 1387 static bool is_valid_attr(struct ib_flow_attr *flow_attr) 1388 { 1389 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1); 1390 bool has_ipv4_spec = false; 1391 bool eth_type_ipv4 = true; 1392 unsigned int spec_index; 1393 1394 /* Validate that ethertype is correct */ 1395 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 1396 if (ib_spec->type == IB_FLOW_SPEC_ETH && 1397 ib_spec->eth.mask.ether_type) { 1398 if (!((ib_spec->eth.mask.ether_type == htons(0xffff)) && 1399 ib_spec->eth.val.ether_type == htons(ETH_P_IP))) 1400 eth_type_ipv4 = false; 1401 } else if (ib_spec->type == IB_FLOW_SPEC_IPV4) { 1402 has_ipv4_spec = true; 1403 } 1404 ib_spec = (void *)ib_spec + ib_spec->size; 1405 } 1406 return !has_ipv4_spec || eth_type_ipv4; 1407 } 1408 1409 static void put_flow_table(struct mlx5_ib_dev *dev, 1410 struct mlx5_ib_flow_prio *prio, bool ft_added) 1411 { 1412 prio->refcount -= !!ft_added; 1413 if (!prio->refcount) { 1414 mlx5_destroy_flow_table(prio->flow_table); 1415 prio->flow_table = NULL; 1416 } 1417 } 1418 1419 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id) 1420 { 1421 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device); 1422 struct mlx5_ib_flow_handler *handler = container_of(flow_id, 1423 struct mlx5_ib_flow_handler, 1424 ibflow); 1425 struct mlx5_ib_flow_handler *iter, *tmp; 1426 1427 mutex_lock(&dev->flow_db.lock); 1428 1429 list_for_each_entry_safe(iter, tmp, &handler->list, list) { 1430 mlx5_del_flow_rule(iter->rule); 1431 list_del(&iter->list); 1432 kfree(iter); 1433 } 1434 1435 mlx5_del_flow_rule(handler->rule); 1436 put_flow_table(dev, &dev->flow_db.prios[handler->prio], true); 1437 mutex_unlock(&dev->flow_db.lock); 1438 1439 kfree(handler); 1440 1441 return 0; 1442 } 1443 1444 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap) 1445 { 1446 priority *= 2; 1447 if (!dont_trap) 1448 priority++; 1449 return priority; 1450 } 1451 1452 #define MLX5_FS_MAX_TYPES 10 1453 #define MLX5_FS_MAX_ENTRIES 32000UL 1454 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev, 1455 struct ib_flow_attr *flow_attr) 1456 { 1457 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP; 1458 struct mlx5_flow_namespace *ns = NULL; 1459 struct mlx5_ib_flow_prio *prio; 1460 struct mlx5_flow_table *ft; 1461 int num_entries; 1462 int num_groups; 1463 int priority; 1464 int err = 0; 1465 1466 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 1467 if (flow_is_multicast_only(flow_attr) && 1468 !dont_trap) 1469 priority = MLX5_IB_FLOW_MCAST_PRIO; 1470 else 1471 priority = ib_prio_to_core_prio(flow_attr->priority, 1472 dont_trap); 1473 ns = mlx5_get_flow_namespace(dev->mdev, 1474 MLX5_FLOW_NAMESPACE_BYPASS); 1475 num_entries = MLX5_FS_MAX_ENTRIES; 1476 num_groups = MLX5_FS_MAX_TYPES; 1477 prio = &dev->flow_db.prios[priority]; 1478 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 1479 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 1480 ns = mlx5_get_flow_namespace(dev->mdev, 1481 MLX5_FLOW_NAMESPACE_LEFTOVERS); 1482 build_leftovers_ft_param(&priority, 1483 &num_entries, 1484 &num_groups); 1485 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO]; 1486 } 1487 1488 if (!ns) 1489 return ERR_PTR(-ENOTSUPP); 1490 1491 ft = prio->flow_table; 1492 if (!ft) { 1493 ft = mlx5_create_auto_grouped_flow_table(ns, priority, 1494 num_entries, 1495 num_groups); 1496 1497 if (!IS_ERR(ft)) { 1498 prio->refcount = 0; 1499 prio->flow_table = ft; 1500 } else { 1501 err = PTR_ERR(ft); 1502 } 1503 } 1504 1505 return err ? ERR_PTR(err) : prio; 1506 } 1507 1508 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev, 1509 struct mlx5_ib_flow_prio *ft_prio, 1510 struct ib_flow_attr *flow_attr, 1511 struct mlx5_flow_destination *dst) 1512 { 1513 struct mlx5_flow_table *ft = ft_prio->flow_table; 1514 struct mlx5_ib_flow_handler *handler; 1515 void *ib_flow = flow_attr + 1; 1516 u8 match_criteria_enable = 0; 1517 unsigned int spec_index; 1518 u32 *match_c; 1519 u32 *match_v; 1520 u32 action; 1521 int err = 0; 1522 1523 if (!is_valid_attr(flow_attr)) 1524 return ERR_PTR(-EINVAL); 1525 1526 match_c = kzalloc(MLX5_ST_SZ_BYTES(fte_match_param), GFP_KERNEL); 1527 match_v = kzalloc(MLX5_ST_SZ_BYTES(fte_match_param), GFP_KERNEL); 1528 handler = kzalloc(sizeof(*handler), GFP_KERNEL); 1529 if (!handler || !match_c || !match_v) { 1530 err = -ENOMEM; 1531 goto free; 1532 } 1533 1534 INIT_LIST_HEAD(&handler->list); 1535 1536 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 1537 err = parse_flow_attr(match_c, match_v, ib_flow); 1538 if (err < 0) 1539 goto free; 1540 1541 ib_flow += ((union ib_flow_spec *)ib_flow)->size; 1542 } 1543 1544 /* Outer header support only */ 1545 match_criteria_enable = (!outer_header_zero(match_c)) << 0; 1546 action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST : 1547 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO; 1548 handler->rule = mlx5_add_flow_rule(ft, match_criteria_enable, 1549 match_c, match_v, 1550 action, 1551 MLX5_FS_DEFAULT_FLOW_TAG, 1552 dst); 1553 1554 if (IS_ERR(handler->rule)) { 1555 err = PTR_ERR(handler->rule); 1556 goto free; 1557 } 1558 1559 handler->prio = ft_prio - dev->flow_db.prios; 1560 1561 ft_prio->flow_table = ft; 1562 free: 1563 if (err) 1564 kfree(handler); 1565 kfree(match_c); 1566 kfree(match_v); 1567 return err ? ERR_PTR(err) : handler; 1568 } 1569 1570 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev, 1571 struct mlx5_ib_flow_prio *ft_prio, 1572 struct ib_flow_attr *flow_attr, 1573 struct mlx5_flow_destination *dst) 1574 { 1575 struct mlx5_ib_flow_handler *handler_dst = NULL; 1576 struct mlx5_ib_flow_handler *handler = NULL; 1577 1578 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL); 1579 if (!IS_ERR(handler)) { 1580 handler_dst = create_flow_rule(dev, ft_prio, 1581 flow_attr, dst); 1582 if (IS_ERR(handler_dst)) { 1583 mlx5_del_flow_rule(handler->rule); 1584 kfree(handler); 1585 handler = handler_dst; 1586 } else { 1587 list_add(&handler_dst->list, &handler->list); 1588 } 1589 } 1590 1591 return handler; 1592 } 1593 enum { 1594 LEFTOVERS_MC, 1595 LEFTOVERS_UC, 1596 }; 1597 1598 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev, 1599 struct mlx5_ib_flow_prio *ft_prio, 1600 struct ib_flow_attr *flow_attr, 1601 struct mlx5_flow_destination *dst) 1602 { 1603 struct mlx5_ib_flow_handler *handler_ucast = NULL; 1604 struct mlx5_ib_flow_handler *handler = NULL; 1605 1606 static struct { 1607 struct ib_flow_attr flow_attr; 1608 struct ib_flow_spec_eth eth_flow; 1609 } leftovers_specs[] = { 1610 [LEFTOVERS_MC] = { 1611 .flow_attr = { 1612 .num_of_specs = 1, 1613 .size = sizeof(leftovers_specs[0]) 1614 }, 1615 .eth_flow = { 1616 .type = IB_FLOW_SPEC_ETH, 1617 .size = sizeof(struct ib_flow_spec_eth), 1618 .mask = {.dst_mac = {0x1} }, 1619 .val = {.dst_mac = {0x1} } 1620 } 1621 }, 1622 [LEFTOVERS_UC] = { 1623 .flow_attr = { 1624 .num_of_specs = 1, 1625 .size = sizeof(leftovers_specs[0]) 1626 }, 1627 .eth_flow = { 1628 .type = IB_FLOW_SPEC_ETH, 1629 .size = sizeof(struct ib_flow_spec_eth), 1630 .mask = {.dst_mac = {0x1} }, 1631 .val = {.dst_mac = {} } 1632 } 1633 } 1634 }; 1635 1636 handler = create_flow_rule(dev, ft_prio, 1637 &leftovers_specs[LEFTOVERS_MC].flow_attr, 1638 dst); 1639 if (!IS_ERR(handler) && 1640 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) { 1641 handler_ucast = create_flow_rule(dev, ft_prio, 1642 &leftovers_specs[LEFTOVERS_UC].flow_attr, 1643 dst); 1644 if (IS_ERR(handler_ucast)) { 1645 kfree(handler); 1646 handler = handler_ucast; 1647 } else { 1648 list_add(&handler_ucast->list, &handler->list); 1649 } 1650 } 1651 1652 return handler; 1653 } 1654 1655 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp, 1656 struct ib_flow_attr *flow_attr, 1657 int domain) 1658 { 1659 struct mlx5_ib_dev *dev = to_mdev(qp->device); 1660 struct mlx5_ib_flow_handler *handler = NULL; 1661 struct mlx5_flow_destination *dst = NULL; 1662 struct mlx5_ib_flow_prio *ft_prio; 1663 int err; 1664 1665 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) 1666 return ERR_PTR(-ENOSPC); 1667 1668 if (domain != IB_FLOW_DOMAIN_USER || 1669 flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) || 1670 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP)) 1671 return ERR_PTR(-EINVAL); 1672 1673 dst = kzalloc(sizeof(*dst), GFP_KERNEL); 1674 if (!dst) 1675 return ERR_PTR(-ENOMEM); 1676 1677 mutex_lock(&dev->flow_db.lock); 1678 1679 ft_prio = get_flow_table(dev, flow_attr); 1680 if (IS_ERR(ft_prio)) { 1681 err = PTR_ERR(ft_prio); 1682 goto unlock; 1683 } 1684 1685 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR; 1686 dst->tir_num = to_mqp(qp)->raw_packet_qp.rq.tirn; 1687 1688 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 1689 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) { 1690 handler = create_dont_trap_rule(dev, ft_prio, 1691 flow_attr, dst); 1692 } else { 1693 handler = create_flow_rule(dev, ft_prio, flow_attr, 1694 dst); 1695 } 1696 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 1697 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 1698 handler = create_leftovers_rule(dev, ft_prio, flow_attr, 1699 dst); 1700 } else { 1701 err = -EINVAL; 1702 goto destroy_ft; 1703 } 1704 1705 if (IS_ERR(handler)) { 1706 err = PTR_ERR(handler); 1707 handler = NULL; 1708 goto destroy_ft; 1709 } 1710 1711 ft_prio->refcount++; 1712 mutex_unlock(&dev->flow_db.lock); 1713 kfree(dst); 1714 1715 return &handler->ibflow; 1716 1717 destroy_ft: 1718 put_flow_table(dev, ft_prio, false); 1719 unlock: 1720 mutex_unlock(&dev->flow_db.lock); 1721 kfree(dst); 1722 kfree(handler); 1723 return ERR_PTR(err); 1724 } 1725 1726 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 1727 { 1728 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 1729 int err; 1730 1731 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num); 1732 if (err) 1733 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 1734 ibqp->qp_num, gid->raw); 1735 1736 return err; 1737 } 1738 1739 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 1740 { 1741 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 1742 int err; 1743 1744 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num); 1745 if (err) 1746 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 1747 ibqp->qp_num, gid->raw); 1748 1749 return err; 1750 } 1751 1752 static int init_node_data(struct mlx5_ib_dev *dev) 1753 { 1754 int err; 1755 1756 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 1757 if (err) 1758 return err; 1759 1760 dev->mdev->rev_id = dev->mdev->pdev->revision; 1761 1762 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 1763 } 1764 1765 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr, 1766 char *buf) 1767 { 1768 struct mlx5_ib_dev *dev = 1769 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 1770 1771 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages); 1772 } 1773 1774 static ssize_t show_reg_pages(struct device *device, 1775 struct device_attribute *attr, char *buf) 1776 { 1777 struct mlx5_ib_dev *dev = 1778 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 1779 1780 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 1781 } 1782 1783 static ssize_t show_hca(struct device *device, struct device_attribute *attr, 1784 char *buf) 1785 { 1786 struct mlx5_ib_dev *dev = 1787 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 1788 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device); 1789 } 1790 1791 static ssize_t show_fw_ver(struct device *device, struct device_attribute *attr, 1792 char *buf) 1793 { 1794 struct mlx5_ib_dev *dev = 1795 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 1796 return sprintf(buf, "%d.%d.%d\n", fw_rev_maj(dev->mdev), 1797 fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev)); 1798 } 1799 1800 static ssize_t show_rev(struct device *device, struct device_attribute *attr, 1801 char *buf) 1802 { 1803 struct mlx5_ib_dev *dev = 1804 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 1805 return sprintf(buf, "%x\n", dev->mdev->rev_id); 1806 } 1807 1808 static ssize_t show_board(struct device *device, struct device_attribute *attr, 1809 char *buf) 1810 { 1811 struct mlx5_ib_dev *dev = 1812 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 1813 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 1814 dev->mdev->board_id); 1815 } 1816 1817 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL); 1818 static DEVICE_ATTR(fw_ver, S_IRUGO, show_fw_ver, NULL); 1819 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL); 1820 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL); 1821 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL); 1822 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL); 1823 1824 static struct device_attribute *mlx5_class_attributes[] = { 1825 &dev_attr_hw_rev, 1826 &dev_attr_fw_ver, 1827 &dev_attr_hca_type, 1828 &dev_attr_board_id, 1829 &dev_attr_fw_pages, 1830 &dev_attr_reg_pages, 1831 }; 1832 1833 static void pkey_change_handler(struct work_struct *work) 1834 { 1835 struct mlx5_ib_port_resources *ports = 1836 container_of(work, struct mlx5_ib_port_resources, 1837 pkey_change_work); 1838 1839 mutex_lock(&ports->devr->mutex); 1840 mlx5_ib_gsi_pkey_change(ports->gsi); 1841 mutex_unlock(&ports->devr->mutex); 1842 } 1843 1844 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context, 1845 enum mlx5_dev_event event, unsigned long param) 1846 { 1847 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context; 1848 struct ib_event ibev; 1849 1850 u8 port = 0; 1851 1852 switch (event) { 1853 case MLX5_DEV_EVENT_SYS_ERROR: 1854 ibdev->ib_active = false; 1855 ibev.event = IB_EVENT_DEVICE_FATAL; 1856 break; 1857 1858 case MLX5_DEV_EVENT_PORT_UP: 1859 ibev.event = IB_EVENT_PORT_ACTIVE; 1860 port = (u8)param; 1861 break; 1862 1863 case MLX5_DEV_EVENT_PORT_DOWN: 1864 ibev.event = IB_EVENT_PORT_ERR; 1865 port = (u8)param; 1866 break; 1867 1868 case MLX5_DEV_EVENT_PORT_INITIALIZED: 1869 /* not used by ULPs */ 1870 return; 1871 1872 case MLX5_DEV_EVENT_LID_CHANGE: 1873 ibev.event = IB_EVENT_LID_CHANGE; 1874 port = (u8)param; 1875 break; 1876 1877 case MLX5_DEV_EVENT_PKEY_CHANGE: 1878 ibev.event = IB_EVENT_PKEY_CHANGE; 1879 port = (u8)param; 1880 1881 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 1882 break; 1883 1884 case MLX5_DEV_EVENT_GUID_CHANGE: 1885 ibev.event = IB_EVENT_GID_CHANGE; 1886 port = (u8)param; 1887 break; 1888 1889 case MLX5_DEV_EVENT_CLIENT_REREG: 1890 ibev.event = IB_EVENT_CLIENT_REREGISTER; 1891 port = (u8)param; 1892 break; 1893 } 1894 1895 ibev.device = &ibdev->ib_dev; 1896 ibev.element.port_num = port; 1897 1898 if (port < 1 || port > ibdev->num_ports) { 1899 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port); 1900 return; 1901 } 1902 1903 if (ibdev->ib_active) 1904 ib_dispatch_event(&ibev); 1905 } 1906 1907 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 1908 { 1909 int port; 1910 1911 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) 1912 mlx5_query_ext_port_caps(dev, port); 1913 } 1914 1915 static int get_port_caps(struct mlx5_ib_dev *dev) 1916 { 1917 struct ib_device_attr *dprops = NULL; 1918 struct ib_port_attr *pprops = NULL; 1919 int err = -ENOMEM; 1920 int port; 1921 struct ib_udata uhw = {.inlen = 0, .outlen = 0}; 1922 1923 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL); 1924 if (!pprops) 1925 goto out; 1926 1927 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL); 1928 if (!dprops) 1929 goto out; 1930 1931 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw); 1932 if (err) { 1933 mlx5_ib_warn(dev, "query_device failed %d\n", err); 1934 goto out; 1935 } 1936 1937 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) { 1938 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops); 1939 if (err) { 1940 mlx5_ib_warn(dev, "query_port %d failed %d\n", 1941 port, err); 1942 break; 1943 } 1944 dev->mdev->port_caps[port - 1].pkey_table_len = 1945 dprops->max_pkeys; 1946 dev->mdev->port_caps[port - 1].gid_table_len = 1947 pprops->gid_tbl_len; 1948 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n", 1949 dprops->max_pkeys, pprops->gid_tbl_len); 1950 } 1951 1952 out: 1953 kfree(pprops); 1954 kfree(dprops); 1955 1956 return err; 1957 } 1958 1959 static void destroy_umrc_res(struct mlx5_ib_dev *dev) 1960 { 1961 int err; 1962 1963 err = mlx5_mr_cache_cleanup(dev); 1964 if (err) 1965 mlx5_ib_warn(dev, "mr cache cleanup failed\n"); 1966 1967 mlx5_ib_destroy_qp(dev->umrc.qp); 1968 ib_free_cq(dev->umrc.cq); 1969 ib_dealloc_pd(dev->umrc.pd); 1970 } 1971 1972 enum { 1973 MAX_UMR_WR = 128, 1974 }; 1975 1976 static int create_umr_res(struct mlx5_ib_dev *dev) 1977 { 1978 struct ib_qp_init_attr *init_attr = NULL; 1979 struct ib_qp_attr *attr = NULL; 1980 struct ib_pd *pd; 1981 struct ib_cq *cq; 1982 struct ib_qp *qp; 1983 int ret; 1984 1985 attr = kzalloc(sizeof(*attr), GFP_KERNEL); 1986 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL); 1987 if (!attr || !init_attr) { 1988 ret = -ENOMEM; 1989 goto error_0; 1990 } 1991 1992 pd = ib_alloc_pd(&dev->ib_dev); 1993 if (IS_ERR(pd)) { 1994 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n"); 1995 ret = PTR_ERR(pd); 1996 goto error_0; 1997 } 1998 1999 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ); 2000 if (IS_ERR(cq)) { 2001 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n"); 2002 ret = PTR_ERR(cq); 2003 goto error_2; 2004 } 2005 2006 init_attr->send_cq = cq; 2007 init_attr->recv_cq = cq; 2008 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR; 2009 init_attr->cap.max_send_wr = MAX_UMR_WR; 2010 init_attr->cap.max_send_sge = 1; 2011 init_attr->qp_type = MLX5_IB_QPT_REG_UMR; 2012 init_attr->port_num = 1; 2013 qp = mlx5_ib_create_qp(pd, init_attr, NULL); 2014 if (IS_ERR(qp)) { 2015 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n"); 2016 ret = PTR_ERR(qp); 2017 goto error_3; 2018 } 2019 qp->device = &dev->ib_dev; 2020 qp->real_qp = qp; 2021 qp->uobject = NULL; 2022 qp->qp_type = MLX5_IB_QPT_REG_UMR; 2023 2024 attr->qp_state = IB_QPS_INIT; 2025 attr->port_num = 1; 2026 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX | 2027 IB_QP_PORT, NULL); 2028 if (ret) { 2029 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n"); 2030 goto error_4; 2031 } 2032 2033 memset(attr, 0, sizeof(*attr)); 2034 attr->qp_state = IB_QPS_RTR; 2035 attr->path_mtu = IB_MTU_256; 2036 2037 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 2038 if (ret) { 2039 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n"); 2040 goto error_4; 2041 } 2042 2043 memset(attr, 0, sizeof(*attr)); 2044 attr->qp_state = IB_QPS_RTS; 2045 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 2046 if (ret) { 2047 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n"); 2048 goto error_4; 2049 } 2050 2051 dev->umrc.qp = qp; 2052 dev->umrc.cq = cq; 2053 dev->umrc.pd = pd; 2054 2055 sema_init(&dev->umrc.sem, MAX_UMR_WR); 2056 ret = mlx5_mr_cache_init(dev); 2057 if (ret) { 2058 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 2059 goto error_4; 2060 } 2061 2062 kfree(attr); 2063 kfree(init_attr); 2064 2065 return 0; 2066 2067 error_4: 2068 mlx5_ib_destroy_qp(qp); 2069 2070 error_3: 2071 ib_free_cq(cq); 2072 2073 error_2: 2074 ib_dealloc_pd(pd); 2075 2076 error_0: 2077 kfree(attr); 2078 kfree(init_attr); 2079 return ret; 2080 } 2081 2082 static int create_dev_resources(struct mlx5_ib_resources *devr) 2083 { 2084 struct ib_srq_init_attr attr; 2085 struct mlx5_ib_dev *dev; 2086 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 2087 int port; 2088 int ret = 0; 2089 2090 dev = container_of(devr, struct mlx5_ib_dev, devr); 2091 2092 mutex_init(&devr->mutex); 2093 2094 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL); 2095 if (IS_ERR(devr->p0)) { 2096 ret = PTR_ERR(devr->p0); 2097 goto error0; 2098 } 2099 devr->p0->device = &dev->ib_dev; 2100 devr->p0->uobject = NULL; 2101 atomic_set(&devr->p0->usecnt, 0); 2102 2103 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL); 2104 if (IS_ERR(devr->c0)) { 2105 ret = PTR_ERR(devr->c0); 2106 goto error1; 2107 } 2108 devr->c0->device = &dev->ib_dev; 2109 devr->c0->uobject = NULL; 2110 devr->c0->comp_handler = NULL; 2111 devr->c0->event_handler = NULL; 2112 devr->c0->cq_context = NULL; 2113 atomic_set(&devr->c0->usecnt, 0); 2114 2115 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 2116 if (IS_ERR(devr->x0)) { 2117 ret = PTR_ERR(devr->x0); 2118 goto error2; 2119 } 2120 devr->x0->device = &dev->ib_dev; 2121 devr->x0->inode = NULL; 2122 atomic_set(&devr->x0->usecnt, 0); 2123 mutex_init(&devr->x0->tgt_qp_mutex); 2124 INIT_LIST_HEAD(&devr->x0->tgt_qp_list); 2125 2126 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 2127 if (IS_ERR(devr->x1)) { 2128 ret = PTR_ERR(devr->x1); 2129 goto error3; 2130 } 2131 devr->x1->device = &dev->ib_dev; 2132 devr->x1->inode = NULL; 2133 atomic_set(&devr->x1->usecnt, 0); 2134 mutex_init(&devr->x1->tgt_qp_mutex); 2135 INIT_LIST_HEAD(&devr->x1->tgt_qp_list); 2136 2137 memset(&attr, 0, sizeof(attr)); 2138 attr.attr.max_sge = 1; 2139 attr.attr.max_wr = 1; 2140 attr.srq_type = IB_SRQT_XRC; 2141 attr.ext.xrc.cq = devr->c0; 2142 attr.ext.xrc.xrcd = devr->x0; 2143 2144 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 2145 if (IS_ERR(devr->s0)) { 2146 ret = PTR_ERR(devr->s0); 2147 goto error4; 2148 } 2149 devr->s0->device = &dev->ib_dev; 2150 devr->s0->pd = devr->p0; 2151 devr->s0->uobject = NULL; 2152 devr->s0->event_handler = NULL; 2153 devr->s0->srq_context = NULL; 2154 devr->s0->srq_type = IB_SRQT_XRC; 2155 devr->s0->ext.xrc.xrcd = devr->x0; 2156 devr->s0->ext.xrc.cq = devr->c0; 2157 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt); 2158 atomic_inc(&devr->s0->ext.xrc.cq->usecnt); 2159 atomic_inc(&devr->p0->usecnt); 2160 atomic_set(&devr->s0->usecnt, 0); 2161 2162 memset(&attr, 0, sizeof(attr)); 2163 attr.attr.max_sge = 1; 2164 attr.attr.max_wr = 1; 2165 attr.srq_type = IB_SRQT_BASIC; 2166 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 2167 if (IS_ERR(devr->s1)) { 2168 ret = PTR_ERR(devr->s1); 2169 goto error5; 2170 } 2171 devr->s1->device = &dev->ib_dev; 2172 devr->s1->pd = devr->p0; 2173 devr->s1->uobject = NULL; 2174 devr->s1->event_handler = NULL; 2175 devr->s1->srq_context = NULL; 2176 devr->s1->srq_type = IB_SRQT_BASIC; 2177 devr->s1->ext.xrc.cq = devr->c0; 2178 atomic_inc(&devr->p0->usecnt); 2179 atomic_set(&devr->s0->usecnt, 0); 2180 2181 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) { 2182 INIT_WORK(&devr->ports[port].pkey_change_work, 2183 pkey_change_handler); 2184 devr->ports[port].devr = devr; 2185 } 2186 2187 return 0; 2188 2189 error5: 2190 mlx5_ib_destroy_srq(devr->s0); 2191 error4: 2192 mlx5_ib_dealloc_xrcd(devr->x1); 2193 error3: 2194 mlx5_ib_dealloc_xrcd(devr->x0); 2195 error2: 2196 mlx5_ib_destroy_cq(devr->c0); 2197 error1: 2198 mlx5_ib_dealloc_pd(devr->p0); 2199 error0: 2200 return ret; 2201 } 2202 2203 static void destroy_dev_resources(struct mlx5_ib_resources *devr) 2204 { 2205 struct mlx5_ib_dev *dev = 2206 container_of(devr, struct mlx5_ib_dev, devr); 2207 int port; 2208 2209 mlx5_ib_destroy_srq(devr->s1); 2210 mlx5_ib_destroy_srq(devr->s0); 2211 mlx5_ib_dealloc_xrcd(devr->x0); 2212 mlx5_ib_dealloc_xrcd(devr->x1); 2213 mlx5_ib_destroy_cq(devr->c0); 2214 mlx5_ib_dealloc_pd(devr->p0); 2215 2216 /* Make sure no change P_Key work items are still executing */ 2217 for (port = 0; port < dev->num_ports; ++port) 2218 cancel_work_sync(&devr->ports[port].pkey_change_work); 2219 } 2220 2221 static u32 get_core_cap_flags(struct ib_device *ibdev) 2222 { 2223 struct mlx5_ib_dev *dev = to_mdev(ibdev); 2224 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 2225 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 2226 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 2227 u32 ret = 0; 2228 2229 if (ll == IB_LINK_LAYER_INFINIBAND) 2230 return RDMA_CORE_PORT_IBA_IB; 2231 2232 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 2233 return 0; 2234 2235 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 2236 return 0; 2237 2238 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 2239 ret |= RDMA_CORE_PORT_IBA_ROCE; 2240 2241 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 2242 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 2243 2244 return ret; 2245 } 2246 2247 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num, 2248 struct ib_port_immutable *immutable) 2249 { 2250 struct ib_port_attr attr; 2251 int err; 2252 2253 err = mlx5_ib_query_port(ibdev, port_num, &attr); 2254 if (err) 2255 return err; 2256 2257 immutable->pkey_tbl_len = attr.pkey_tbl_len; 2258 immutable->gid_tbl_len = attr.gid_tbl_len; 2259 immutable->core_cap_flags = get_core_cap_flags(ibdev); 2260 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 2261 2262 return 0; 2263 } 2264 2265 static int mlx5_enable_roce(struct mlx5_ib_dev *dev) 2266 { 2267 int err; 2268 2269 dev->roce.nb.notifier_call = mlx5_netdev_event; 2270 err = register_netdevice_notifier(&dev->roce.nb); 2271 if (err) 2272 return err; 2273 2274 err = mlx5_nic_vport_enable_roce(dev->mdev); 2275 if (err) 2276 goto err_unregister_netdevice_notifier; 2277 2278 return 0; 2279 2280 err_unregister_netdevice_notifier: 2281 unregister_netdevice_notifier(&dev->roce.nb); 2282 return err; 2283 } 2284 2285 static void mlx5_disable_roce(struct mlx5_ib_dev *dev) 2286 { 2287 mlx5_nic_vport_disable_roce(dev->mdev); 2288 unregister_netdevice_notifier(&dev->roce.nb); 2289 } 2290 2291 static void *mlx5_ib_add(struct mlx5_core_dev *mdev) 2292 { 2293 struct mlx5_ib_dev *dev; 2294 enum rdma_link_layer ll; 2295 int port_type_cap; 2296 int err; 2297 int i; 2298 2299 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 2300 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 2301 2302 if ((ll == IB_LINK_LAYER_ETHERNET) && !MLX5_CAP_GEN(mdev, roce)) 2303 return NULL; 2304 2305 printk_once(KERN_INFO "%s", mlx5_version); 2306 2307 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev)); 2308 if (!dev) 2309 return NULL; 2310 2311 dev->mdev = mdev; 2312 2313 rwlock_init(&dev->roce.netdev_lock); 2314 err = get_port_caps(dev); 2315 if (err) 2316 goto err_dealloc; 2317 2318 if (mlx5_use_mad_ifc(dev)) 2319 get_ext_port_caps(dev); 2320 2321 MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock); 2322 2323 strlcpy(dev->ib_dev.name, "mlx5_%d", IB_DEVICE_NAME_MAX); 2324 dev->ib_dev.owner = THIS_MODULE; 2325 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 2326 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 2327 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports); 2328 dev->ib_dev.phys_port_cnt = dev->num_ports; 2329 dev->ib_dev.num_comp_vectors = 2330 dev->mdev->priv.eq_table.num_comp_vectors; 2331 dev->ib_dev.dma_device = &mdev->pdev->dev; 2332 2333 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION; 2334 dev->ib_dev.uverbs_cmd_mask = 2335 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | 2336 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | 2337 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | 2338 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | 2339 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | 2340 (1ull << IB_USER_VERBS_CMD_REG_MR) | 2341 (1ull << IB_USER_VERBS_CMD_REREG_MR) | 2342 (1ull << IB_USER_VERBS_CMD_DEREG_MR) | 2343 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 2344 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | 2345 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) | 2346 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | 2347 (1ull << IB_USER_VERBS_CMD_CREATE_QP) | 2348 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | 2349 (1ull << IB_USER_VERBS_CMD_QUERY_QP) | 2350 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | 2351 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) | 2352 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) | 2353 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | 2354 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | 2355 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | 2356 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | 2357 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) | 2358 (1ull << IB_USER_VERBS_CMD_OPEN_QP); 2359 dev->ib_dev.uverbs_ex_cmd_mask = 2360 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) | 2361 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) | 2362 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP); 2363 2364 dev->ib_dev.query_device = mlx5_ib_query_device; 2365 dev->ib_dev.query_port = mlx5_ib_query_port; 2366 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer; 2367 if (ll == IB_LINK_LAYER_ETHERNET) 2368 dev->ib_dev.get_netdev = mlx5_ib_get_netdev; 2369 dev->ib_dev.query_gid = mlx5_ib_query_gid; 2370 dev->ib_dev.add_gid = mlx5_ib_add_gid; 2371 dev->ib_dev.del_gid = mlx5_ib_del_gid; 2372 dev->ib_dev.query_pkey = mlx5_ib_query_pkey; 2373 dev->ib_dev.modify_device = mlx5_ib_modify_device; 2374 dev->ib_dev.modify_port = mlx5_ib_modify_port; 2375 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext; 2376 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext; 2377 dev->ib_dev.mmap = mlx5_ib_mmap; 2378 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd; 2379 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd; 2380 dev->ib_dev.create_ah = mlx5_ib_create_ah; 2381 dev->ib_dev.query_ah = mlx5_ib_query_ah; 2382 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah; 2383 dev->ib_dev.create_srq = mlx5_ib_create_srq; 2384 dev->ib_dev.modify_srq = mlx5_ib_modify_srq; 2385 dev->ib_dev.query_srq = mlx5_ib_query_srq; 2386 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq; 2387 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv; 2388 dev->ib_dev.create_qp = mlx5_ib_create_qp; 2389 dev->ib_dev.modify_qp = mlx5_ib_modify_qp; 2390 dev->ib_dev.query_qp = mlx5_ib_query_qp; 2391 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp; 2392 dev->ib_dev.post_send = mlx5_ib_post_send; 2393 dev->ib_dev.post_recv = mlx5_ib_post_recv; 2394 dev->ib_dev.create_cq = mlx5_ib_create_cq; 2395 dev->ib_dev.modify_cq = mlx5_ib_modify_cq; 2396 dev->ib_dev.resize_cq = mlx5_ib_resize_cq; 2397 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq; 2398 dev->ib_dev.poll_cq = mlx5_ib_poll_cq; 2399 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq; 2400 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr; 2401 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr; 2402 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr; 2403 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr; 2404 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach; 2405 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach; 2406 dev->ib_dev.process_mad = mlx5_ib_process_mad; 2407 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr; 2408 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg; 2409 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status; 2410 dev->ib_dev.get_port_immutable = mlx5_port_immutable; 2411 if (mlx5_core_is_pf(mdev)) { 2412 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config; 2413 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state; 2414 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats; 2415 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid; 2416 } 2417 2418 mlx5_ib_internal_fill_odp_caps(dev); 2419 2420 if (MLX5_CAP_GEN(mdev, imaicl)) { 2421 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw; 2422 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw; 2423 dev->ib_dev.uverbs_cmd_mask |= 2424 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) | 2425 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW); 2426 } 2427 2428 if (MLX5_CAP_GEN(mdev, xrc)) { 2429 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd; 2430 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd; 2431 dev->ib_dev.uverbs_cmd_mask |= 2432 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) | 2433 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD); 2434 } 2435 2436 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) == 2437 IB_LINK_LAYER_ETHERNET) { 2438 dev->ib_dev.create_flow = mlx5_ib_create_flow; 2439 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow; 2440 dev->ib_dev.uverbs_ex_cmd_mask |= 2441 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) | 2442 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW); 2443 } 2444 err = init_node_data(dev); 2445 if (err) 2446 goto err_dealloc; 2447 2448 mutex_init(&dev->flow_db.lock); 2449 mutex_init(&dev->cap_mask_mutex); 2450 2451 if (ll == IB_LINK_LAYER_ETHERNET) { 2452 err = mlx5_enable_roce(dev); 2453 if (err) 2454 goto err_dealloc; 2455 } 2456 2457 err = create_dev_resources(&dev->devr); 2458 if (err) 2459 goto err_disable_roce; 2460 2461 err = mlx5_ib_odp_init_one(dev); 2462 if (err) 2463 goto err_rsrc; 2464 2465 err = ib_register_device(&dev->ib_dev, NULL); 2466 if (err) 2467 goto err_odp; 2468 2469 err = create_umr_res(dev); 2470 if (err) 2471 goto err_dev; 2472 2473 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) { 2474 err = device_create_file(&dev->ib_dev.dev, 2475 mlx5_class_attributes[i]); 2476 if (err) 2477 goto err_umrc; 2478 } 2479 2480 dev->ib_active = true; 2481 2482 return dev; 2483 2484 err_umrc: 2485 destroy_umrc_res(dev); 2486 2487 err_dev: 2488 ib_unregister_device(&dev->ib_dev); 2489 2490 err_odp: 2491 mlx5_ib_odp_remove_one(dev); 2492 2493 err_rsrc: 2494 destroy_dev_resources(&dev->devr); 2495 2496 err_disable_roce: 2497 if (ll == IB_LINK_LAYER_ETHERNET) 2498 mlx5_disable_roce(dev); 2499 2500 err_dealloc: 2501 ib_dealloc_device((struct ib_device *)dev); 2502 2503 return NULL; 2504 } 2505 2506 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context) 2507 { 2508 struct mlx5_ib_dev *dev = context; 2509 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1); 2510 2511 ib_unregister_device(&dev->ib_dev); 2512 destroy_umrc_res(dev); 2513 mlx5_ib_odp_remove_one(dev); 2514 destroy_dev_resources(&dev->devr); 2515 if (ll == IB_LINK_LAYER_ETHERNET) 2516 mlx5_disable_roce(dev); 2517 ib_dealloc_device(&dev->ib_dev); 2518 } 2519 2520 static struct mlx5_interface mlx5_ib_interface = { 2521 .add = mlx5_ib_add, 2522 .remove = mlx5_ib_remove, 2523 .event = mlx5_ib_event, 2524 .protocol = MLX5_INTERFACE_PROTOCOL_IB, 2525 }; 2526 2527 static int __init mlx5_ib_init(void) 2528 { 2529 int err; 2530 2531 if (deprecated_prof_sel != 2) 2532 pr_warn("prof_sel is deprecated for mlx5_ib, set it for mlx5_core\n"); 2533 2534 err = mlx5_ib_odp_init(); 2535 if (err) 2536 return err; 2537 2538 err = mlx5_register_interface(&mlx5_ib_interface); 2539 if (err) 2540 goto clean_odp; 2541 2542 return err; 2543 2544 clean_odp: 2545 mlx5_ib_odp_cleanup(); 2546 return err; 2547 } 2548 2549 static void __exit mlx5_ib_cleanup(void) 2550 { 2551 mlx5_unregister_interface(&mlx5_ib_interface); 2552 mlx5_ib_odp_cleanup(); 2553 } 2554 2555 module_init(mlx5_ib_init); 2556 module_exit(mlx5_ib_cleanup); 2557