1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/debugfs.h> 34 #include <linux/highmem.h> 35 #include <linux/module.h> 36 #include <linux/init.h> 37 #include <linux/errno.h> 38 #include <linux/pci.h> 39 #include <linux/dma-mapping.h> 40 #include <linux/slab.h> 41 #include <linux/bitmap.h> 42 #if defined(CONFIG_X86) 43 #include <asm/pat.h> 44 #endif 45 #include <linux/sched.h> 46 #include <linux/sched/mm.h> 47 #include <linux/sched/task.h> 48 #include <linux/delay.h> 49 #include <rdma/ib_user_verbs.h> 50 #include <rdma/ib_addr.h> 51 #include <rdma/ib_cache.h> 52 #include <linux/mlx5/port.h> 53 #include <linux/mlx5/vport.h> 54 #include <linux/mlx5/fs.h> 55 #include <linux/list.h> 56 #include <rdma/ib_smi.h> 57 #include <rdma/ib_umem.h> 58 #include <linux/in.h> 59 #include <linux/etherdevice.h> 60 #include "mlx5_ib.h" 61 #include "ib_rep.h" 62 #include "cmd.h" 63 #include <linux/mlx5/fs_helpers.h> 64 #include <linux/mlx5/accel.h> 65 #include <rdma/uverbs_std_types.h> 66 #include <rdma/mlx5_user_ioctl_verbs.h> 67 #include <rdma/mlx5_user_ioctl_cmds.h> 68 69 #define UVERBS_MODULE_NAME mlx5_ib 70 #include <rdma/uverbs_named_ioctl.h> 71 72 #define DRIVER_NAME "mlx5_ib" 73 #define DRIVER_VERSION "5.0-0" 74 75 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 76 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver"); 77 MODULE_LICENSE("Dual BSD/GPL"); 78 79 static char mlx5_version[] = 80 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v" 81 DRIVER_VERSION "\n"; 82 83 struct mlx5_ib_event_work { 84 struct work_struct work; 85 struct mlx5_core_dev *dev; 86 void *context; 87 enum mlx5_dev_event event; 88 unsigned long param; 89 }; 90 91 enum { 92 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 93 }; 94 95 static struct workqueue_struct *mlx5_ib_event_wq; 96 static LIST_HEAD(mlx5_ib_unaffiliated_port_list); 97 static LIST_HEAD(mlx5_ib_dev_list); 98 /* 99 * This mutex should be held when accessing either of the above lists 100 */ 101 static DEFINE_MUTEX(mlx5_ib_multiport_mutex); 102 103 /* We can't use an array for xlt_emergency_page because dma_map_single 104 * doesn't work on kernel modules memory 105 */ 106 static unsigned long xlt_emergency_page; 107 static struct mutex xlt_emergency_page_mutex; 108 109 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi) 110 { 111 struct mlx5_ib_dev *dev; 112 113 mutex_lock(&mlx5_ib_multiport_mutex); 114 dev = mpi->ibdev; 115 mutex_unlock(&mlx5_ib_multiport_mutex); 116 return dev; 117 } 118 119 static enum rdma_link_layer 120 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 121 { 122 switch (port_type_cap) { 123 case MLX5_CAP_PORT_TYPE_IB: 124 return IB_LINK_LAYER_INFINIBAND; 125 case MLX5_CAP_PORT_TYPE_ETH: 126 return IB_LINK_LAYER_ETHERNET; 127 default: 128 return IB_LINK_LAYER_UNSPECIFIED; 129 } 130 } 131 132 static enum rdma_link_layer 133 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num) 134 { 135 struct mlx5_ib_dev *dev = to_mdev(device); 136 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 137 138 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 139 } 140 141 static int get_port_state(struct ib_device *ibdev, 142 u8 port_num, 143 enum ib_port_state *state) 144 { 145 struct ib_port_attr attr; 146 int ret; 147 148 memset(&attr, 0, sizeof(attr)); 149 ret = ibdev->query_port(ibdev, port_num, &attr); 150 if (!ret) 151 *state = attr.state; 152 return ret; 153 } 154 155 static int mlx5_netdev_event(struct notifier_block *this, 156 unsigned long event, void *ptr) 157 { 158 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb); 159 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 160 u8 port_num = roce->native_port_num; 161 struct mlx5_core_dev *mdev; 162 struct mlx5_ib_dev *ibdev; 163 164 ibdev = roce->dev; 165 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 166 if (!mdev) 167 return NOTIFY_DONE; 168 169 switch (event) { 170 case NETDEV_REGISTER: 171 case NETDEV_UNREGISTER: 172 write_lock(&roce->netdev_lock); 173 if (ibdev->rep) { 174 struct mlx5_eswitch *esw = ibdev->mdev->priv.eswitch; 175 struct net_device *rep_ndev; 176 177 rep_ndev = mlx5_ib_get_rep_netdev(esw, 178 ibdev->rep->vport); 179 if (rep_ndev == ndev) 180 roce->netdev = (event == NETDEV_UNREGISTER) ? 181 NULL : ndev; 182 } else if (ndev->dev.parent == &mdev->pdev->dev) { 183 roce->netdev = (event == NETDEV_UNREGISTER) ? 184 NULL : ndev; 185 } 186 write_unlock(&roce->netdev_lock); 187 break; 188 189 case NETDEV_CHANGE: 190 case NETDEV_UP: 191 case NETDEV_DOWN: { 192 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev); 193 struct net_device *upper = NULL; 194 195 if (lag_ndev) { 196 upper = netdev_master_upper_dev_get(lag_ndev); 197 dev_put(lag_ndev); 198 } 199 200 if ((upper == ndev || (!upper && ndev == roce->netdev)) 201 && ibdev->ib_active) { 202 struct ib_event ibev = { }; 203 enum ib_port_state port_state; 204 205 if (get_port_state(&ibdev->ib_dev, port_num, 206 &port_state)) 207 goto done; 208 209 if (roce->last_port_state == port_state) 210 goto done; 211 212 roce->last_port_state = port_state; 213 ibev.device = &ibdev->ib_dev; 214 if (port_state == IB_PORT_DOWN) 215 ibev.event = IB_EVENT_PORT_ERR; 216 else if (port_state == IB_PORT_ACTIVE) 217 ibev.event = IB_EVENT_PORT_ACTIVE; 218 else 219 goto done; 220 221 ibev.element.port_num = port_num; 222 ib_dispatch_event(&ibev); 223 } 224 break; 225 } 226 227 default: 228 break; 229 } 230 done: 231 mlx5_ib_put_native_port_mdev(ibdev, port_num); 232 return NOTIFY_DONE; 233 } 234 235 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device, 236 u8 port_num) 237 { 238 struct mlx5_ib_dev *ibdev = to_mdev(device); 239 struct net_device *ndev; 240 struct mlx5_core_dev *mdev; 241 242 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 243 if (!mdev) 244 return NULL; 245 246 ndev = mlx5_lag_get_roce_netdev(mdev); 247 if (ndev) 248 goto out; 249 250 /* Ensure ndev does not disappear before we invoke dev_hold() 251 */ 252 read_lock(&ibdev->roce[port_num - 1].netdev_lock); 253 ndev = ibdev->roce[port_num - 1].netdev; 254 if (ndev) 255 dev_hold(ndev); 256 read_unlock(&ibdev->roce[port_num - 1].netdev_lock); 257 258 out: 259 mlx5_ib_put_native_port_mdev(ibdev, port_num); 260 return ndev; 261 } 262 263 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev, 264 u8 ib_port_num, 265 u8 *native_port_num) 266 { 267 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 268 ib_port_num); 269 struct mlx5_core_dev *mdev = NULL; 270 struct mlx5_ib_multiport_info *mpi; 271 struct mlx5_ib_port *port; 272 273 if (!mlx5_core_mp_enabled(ibdev->mdev) || 274 ll != IB_LINK_LAYER_ETHERNET) { 275 if (native_port_num) 276 *native_port_num = ib_port_num; 277 return ibdev->mdev; 278 } 279 280 if (native_port_num) 281 *native_port_num = 1; 282 283 port = &ibdev->port[ib_port_num - 1]; 284 if (!port) 285 return NULL; 286 287 spin_lock(&port->mp.mpi_lock); 288 mpi = ibdev->port[ib_port_num - 1].mp.mpi; 289 if (mpi && !mpi->unaffiliate) { 290 mdev = mpi->mdev; 291 /* If it's the master no need to refcount, it'll exist 292 * as long as the ib_dev exists. 293 */ 294 if (!mpi->is_master) 295 mpi->mdev_refcnt++; 296 } 297 spin_unlock(&port->mp.mpi_lock); 298 299 return mdev; 300 } 301 302 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num) 303 { 304 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 305 port_num); 306 struct mlx5_ib_multiport_info *mpi; 307 struct mlx5_ib_port *port; 308 309 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 310 return; 311 312 port = &ibdev->port[port_num - 1]; 313 314 spin_lock(&port->mp.mpi_lock); 315 mpi = ibdev->port[port_num - 1].mp.mpi; 316 if (mpi->is_master) 317 goto out; 318 319 mpi->mdev_refcnt--; 320 if (mpi->unaffiliate) 321 complete(&mpi->unref_comp); 322 out: 323 spin_unlock(&port->mp.mpi_lock); 324 } 325 326 static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed, 327 u8 *active_width) 328 { 329 switch (eth_proto_oper) { 330 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII): 331 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX): 332 case MLX5E_PROT_MASK(MLX5E_100BASE_TX): 333 case MLX5E_PROT_MASK(MLX5E_1000BASE_T): 334 *active_width = IB_WIDTH_1X; 335 *active_speed = IB_SPEED_SDR; 336 break; 337 case MLX5E_PROT_MASK(MLX5E_10GBASE_T): 338 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4): 339 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4): 340 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR): 341 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR): 342 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR): 343 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER): 344 *active_width = IB_WIDTH_1X; 345 *active_speed = IB_SPEED_QDR; 346 break; 347 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR): 348 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR): 349 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR): 350 *active_width = IB_WIDTH_1X; 351 *active_speed = IB_SPEED_EDR; 352 break; 353 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4): 354 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4): 355 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4): 356 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4): 357 *active_width = IB_WIDTH_4X; 358 *active_speed = IB_SPEED_QDR; 359 break; 360 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2): 361 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2): 362 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2): 363 *active_width = IB_WIDTH_1X; 364 *active_speed = IB_SPEED_HDR; 365 break; 366 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4): 367 *active_width = IB_WIDTH_4X; 368 *active_speed = IB_SPEED_FDR; 369 break; 370 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4): 371 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4): 372 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4): 373 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4): 374 *active_width = IB_WIDTH_4X; 375 *active_speed = IB_SPEED_EDR; 376 break; 377 default: 378 return -EINVAL; 379 } 380 381 return 0; 382 } 383 384 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num, 385 struct ib_port_attr *props) 386 { 387 struct mlx5_ib_dev *dev = to_mdev(device); 388 struct mlx5_core_dev *mdev; 389 struct net_device *ndev, *upper; 390 enum ib_mtu ndev_ib_mtu; 391 bool put_mdev = true; 392 u16 qkey_viol_cntr; 393 u32 eth_prot_oper; 394 u8 mdev_port_num; 395 int err; 396 397 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 398 if (!mdev) { 399 /* This means the port isn't affiliated yet. Get the 400 * info for the master port instead. 401 */ 402 put_mdev = false; 403 mdev = dev->mdev; 404 mdev_port_num = 1; 405 port_num = 1; 406 } 407 408 /* Possible bad flows are checked before filling out props so in case 409 * of an error it will still be zeroed out. 410 */ 411 err = mlx5_query_port_eth_proto_oper(mdev, ð_prot_oper, 412 mdev_port_num); 413 if (err) 414 goto out; 415 416 props->active_width = IB_WIDTH_4X; 417 props->active_speed = IB_SPEED_QDR; 418 419 translate_eth_proto_oper(eth_prot_oper, &props->active_speed, 420 &props->active_width); 421 422 props->port_cap_flags |= IB_PORT_CM_SUP; 423 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS; 424 425 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 426 roce_address_table_size); 427 props->max_mtu = IB_MTU_4096; 428 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 429 props->pkey_tbl_len = 1; 430 props->state = IB_PORT_DOWN; 431 props->phys_state = 3; 432 433 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr); 434 props->qkey_viol_cntr = qkey_viol_cntr; 435 436 /* If this is a stub query for an unaffiliated port stop here */ 437 if (!put_mdev) 438 goto out; 439 440 ndev = mlx5_ib_get_netdev(device, port_num); 441 if (!ndev) 442 goto out; 443 444 if (mlx5_lag_is_active(dev->mdev)) { 445 rcu_read_lock(); 446 upper = netdev_master_upper_dev_get_rcu(ndev); 447 if (upper) { 448 dev_put(ndev); 449 ndev = upper; 450 dev_hold(ndev); 451 } 452 rcu_read_unlock(); 453 } 454 455 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 456 props->state = IB_PORT_ACTIVE; 457 props->phys_state = 5; 458 } 459 460 ndev_ib_mtu = iboe_get_mtu(ndev->mtu); 461 462 dev_put(ndev); 463 464 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 465 out: 466 if (put_mdev) 467 mlx5_ib_put_native_port_mdev(dev, port_num); 468 return err; 469 } 470 471 static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num, 472 unsigned int index, const union ib_gid *gid, 473 const struct ib_gid_attr *attr) 474 { 475 enum ib_gid_type gid_type = IB_GID_TYPE_IB; 476 u8 roce_version = 0; 477 u8 roce_l3_type = 0; 478 bool vlan = false; 479 u8 mac[ETH_ALEN]; 480 u16 vlan_id = 0; 481 482 if (gid) { 483 gid_type = attr->gid_type; 484 ether_addr_copy(mac, attr->ndev->dev_addr); 485 486 if (is_vlan_dev(attr->ndev)) { 487 vlan = true; 488 vlan_id = vlan_dev_vlan_id(attr->ndev); 489 } 490 } 491 492 switch (gid_type) { 493 case IB_GID_TYPE_IB: 494 roce_version = MLX5_ROCE_VERSION_1; 495 break; 496 case IB_GID_TYPE_ROCE_UDP_ENCAP: 497 roce_version = MLX5_ROCE_VERSION_2; 498 if (ipv6_addr_v4mapped((void *)gid)) 499 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4; 500 else 501 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6; 502 break; 503 504 default: 505 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type); 506 } 507 508 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version, 509 roce_l3_type, gid->raw, mac, vlan, 510 vlan_id, port_num); 511 } 512 513 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr, 514 __always_unused void **context) 515 { 516 return set_roce_addr(to_mdev(attr->device), attr->port_num, 517 attr->index, &attr->gid, attr); 518 } 519 520 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr, 521 __always_unused void **context) 522 { 523 return set_roce_addr(to_mdev(attr->device), attr->port_num, 524 attr->index, NULL, NULL); 525 } 526 527 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, 528 const struct ib_gid_attr *attr) 529 { 530 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 531 return 0; 532 533 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 534 } 535 536 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 537 { 538 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 539 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 540 return 0; 541 } 542 543 enum { 544 MLX5_VPORT_ACCESS_METHOD_MAD, 545 MLX5_VPORT_ACCESS_METHOD_HCA, 546 MLX5_VPORT_ACCESS_METHOD_NIC, 547 }; 548 549 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 550 { 551 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 552 return MLX5_VPORT_ACCESS_METHOD_MAD; 553 554 if (mlx5_ib_port_link_layer(ibdev, 1) == 555 IB_LINK_LAYER_ETHERNET) 556 return MLX5_VPORT_ACCESS_METHOD_NIC; 557 558 return MLX5_VPORT_ACCESS_METHOD_HCA; 559 } 560 561 static void get_atomic_caps(struct mlx5_ib_dev *dev, 562 u8 atomic_size_qp, 563 struct ib_device_attr *props) 564 { 565 u8 tmp; 566 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 567 u8 atomic_req_8B_endianness_mode = 568 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode); 569 570 /* Check if HW supports 8 bytes standard atomic operations and capable 571 * of host endianness respond 572 */ 573 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 574 if (((atomic_operations & tmp) == tmp) && 575 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 576 (atomic_req_8B_endianness_mode)) { 577 props->atomic_cap = IB_ATOMIC_HCA; 578 } else { 579 props->atomic_cap = IB_ATOMIC_NONE; 580 } 581 } 582 583 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev, 584 struct ib_device_attr *props) 585 { 586 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 587 588 get_atomic_caps(dev, atomic_size_qp, props); 589 } 590 591 static void get_atomic_caps_dc(struct mlx5_ib_dev *dev, 592 struct ib_device_attr *props) 593 { 594 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc); 595 596 get_atomic_caps(dev, atomic_size_qp, props); 597 } 598 599 bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev) 600 { 601 struct ib_device_attr props = {}; 602 603 get_atomic_caps_dc(dev, &props); 604 return (props.atomic_cap == IB_ATOMIC_HCA) ? true : false; 605 } 606 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 607 __be64 *sys_image_guid) 608 { 609 struct mlx5_ib_dev *dev = to_mdev(ibdev); 610 struct mlx5_core_dev *mdev = dev->mdev; 611 u64 tmp; 612 int err; 613 614 switch (mlx5_get_vport_access_method(ibdev)) { 615 case MLX5_VPORT_ACCESS_METHOD_MAD: 616 return mlx5_query_mad_ifc_system_image_guid(ibdev, 617 sys_image_guid); 618 619 case MLX5_VPORT_ACCESS_METHOD_HCA: 620 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 621 break; 622 623 case MLX5_VPORT_ACCESS_METHOD_NIC: 624 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 625 break; 626 627 default: 628 return -EINVAL; 629 } 630 631 if (!err) 632 *sys_image_guid = cpu_to_be64(tmp); 633 634 return err; 635 636 } 637 638 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 639 u16 *max_pkeys) 640 { 641 struct mlx5_ib_dev *dev = to_mdev(ibdev); 642 struct mlx5_core_dev *mdev = dev->mdev; 643 644 switch (mlx5_get_vport_access_method(ibdev)) { 645 case MLX5_VPORT_ACCESS_METHOD_MAD: 646 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 647 648 case MLX5_VPORT_ACCESS_METHOD_HCA: 649 case MLX5_VPORT_ACCESS_METHOD_NIC: 650 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 651 pkey_table_size)); 652 return 0; 653 654 default: 655 return -EINVAL; 656 } 657 } 658 659 static int mlx5_query_vendor_id(struct ib_device *ibdev, 660 u32 *vendor_id) 661 { 662 struct mlx5_ib_dev *dev = to_mdev(ibdev); 663 664 switch (mlx5_get_vport_access_method(ibdev)) { 665 case MLX5_VPORT_ACCESS_METHOD_MAD: 666 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 667 668 case MLX5_VPORT_ACCESS_METHOD_HCA: 669 case MLX5_VPORT_ACCESS_METHOD_NIC: 670 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 671 672 default: 673 return -EINVAL; 674 } 675 } 676 677 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 678 __be64 *node_guid) 679 { 680 u64 tmp; 681 int err; 682 683 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 684 case MLX5_VPORT_ACCESS_METHOD_MAD: 685 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 686 687 case MLX5_VPORT_ACCESS_METHOD_HCA: 688 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 689 break; 690 691 case MLX5_VPORT_ACCESS_METHOD_NIC: 692 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 693 break; 694 695 default: 696 return -EINVAL; 697 } 698 699 if (!err) 700 *node_guid = cpu_to_be64(tmp); 701 702 return err; 703 } 704 705 struct mlx5_reg_node_desc { 706 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 707 }; 708 709 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 710 { 711 struct mlx5_reg_node_desc in; 712 713 if (mlx5_use_mad_ifc(dev)) 714 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 715 716 memset(&in, 0, sizeof(in)); 717 718 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 719 sizeof(struct mlx5_reg_node_desc), 720 MLX5_REG_NODE_DESC, 0, 0); 721 } 722 723 static int mlx5_ib_query_device(struct ib_device *ibdev, 724 struct ib_device_attr *props, 725 struct ib_udata *uhw) 726 { 727 struct mlx5_ib_dev *dev = to_mdev(ibdev); 728 struct mlx5_core_dev *mdev = dev->mdev; 729 int err = -ENOMEM; 730 int max_sq_desc; 731 int max_rq_sg; 732 int max_sq_sg; 733 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 734 bool raw_support = !mlx5_core_mp_enabled(mdev); 735 struct mlx5_ib_query_device_resp resp = {}; 736 size_t resp_len; 737 u64 max_tso; 738 739 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 740 if (uhw->outlen && uhw->outlen < resp_len) 741 return -EINVAL; 742 else 743 resp.response_length = resp_len; 744 745 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) 746 return -EINVAL; 747 748 memset(props, 0, sizeof(*props)); 749 err = mlx5_query_system_image_guid(ibdev, 750 &props->sys_image_guid); 751 if (err) 752 return err; 753 754 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys); 755 if (err) 756 return err; 757 758 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 759 if (err) 760 return err; 761 762 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 763 (fw_rev_min(dev->mdev) << 16) | 764 fw_rev_sub(dev->mdev); 765 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 766 IB_DEVICE_PORT_ACTIVE_EVENT | 767 IB_DEVICE_SYS_IMAGE_GUID | 768 IB_DEVICE_RC_RNR_NAK_GEN; 769 770 if (MLX5_CAP_GEN(mdev, pkv)) 771 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 772 if (MLX5_CAP_GEN(mdev, qkv)) 773 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 774 if (MLX5_CAP_GEN(mdev, apm)) 775 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 776 if (MLX5_CAP_GEN(mdev, xrc)) 777 props->device_cap_flags |= IB_DEVICE_XRC; 778 if (MLX5_CAP_GEN(mdev, imaicl)) { 779 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 780 IB_DEVICE_MEM_WINDOW_TYPE_2B; 781 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 782 /* We support 'Gappy' memory registration too */ 783 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG; 784 } 785 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 786 if (MLX5_CAP_GEN(mdev, sho)) { 787 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER; 788 /* At this stage no support for signature handover */ 789 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 790 IB_PROT_T10DIF_TYPE_2 | 791 IB_PROT_T10DIF_TYPE_3; 792 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 793 IB_GUARD_T10DIF_CSUM; 794 } 795 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 796 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 797 798 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) { 799 if (MLX5_CAP_ETH(mdev, csum_cap)) { 800 /* Legacy bit to support old userspace libraries */ 801 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 802 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM; 803 } 804 805 if (MLX5_CAP_ETH(dev->mdev, vlan_cap)) 806 props->raw_packet_caps |= 807 IB_RAW_PACKET_CAP_CVLAN_STRIPPING; 808 809 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) { 810 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 811 if (max_tso) { 812 resp.tso_caps.max_tso = 1 << max_tso; 813 resp.tso_caps.supported_qpts |= 814 1 << IB_QPT_RAW_PACKET; 815 resp.response_length += sizeof(resp.tso_caps); 816 } 817 } 818 819 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) { 820 resp.rss_caps.rx_hash_function = 821 MLX5_RX_HASH_FUNC_TOEPLITZ; 822 resp.rss_caps.rx_hash_fields_mask = 823 MLX5_RX_HASH_SRC_IPV4 | 824 MLX5_RX_HASH_DST_IPV4 | 825 MLX5_RX_HASH_SRC_IPV6 | 826 MLX5_RX_HASH_DST_IPV6 | 827 MLX5_RX_HASH_SRC_PORT_TCP | 828 MLX5_RX_HASH_DST_PORT_TCP | 829 MLX5_RX_HASH_SRC_PORT_UDP | 830 MLX5_RX_HASH_DST_PORT_UDP | 831 MLX5_RX_HASH_INNER; 832 if (mlx5_accel_ipsec_device_caps(dev->mdev) & 833 MLX5_ACCEL_IPSEC_CAP_DEVICE) 834 resp.rss_caps.rx_hash_fields_mask |= 835 MLX5_RX_HASH_IPSEC_SPI; 836 resp.response_length += sizeof(resp.rss_caps); 837 } 838 } else { 839 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) 840 resp.response_length += sizeof(resp.tso_caps); 841 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) 842 resp.response_length += sizeof(resp.rss_caps); 843 } 844 845 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 846 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 847 props->device_cap_flags |= IB_DEVICE_UD_TSO; 848 } 849 850 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) && 851 MLX5_CAP_GEN(dev->mdev, general_notification_event) && 852 raw_support) 853 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP; 854 855 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 856 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap)) 857 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 858 859 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 860 MLX5_CAP_ETH(dev->mdev, scatter_fcs) && 861 raw_support) { 862 /* Legacy bit to support old userspace libraries */ 863 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 864 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; 865 } 866 867 if (MLX5_CAP_DEV_MEM(mdev, memic)) { 868 props->max_dm_size = 869 MLX5_CAP_DEV_MEM(mdev, max_memic_size); 870 } 871 872 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 873 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 874 875 if (MLX5_CAP_GEN(mdev, end_pad)) 876 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING; 877 878 props->vendor_part_id = mdev->pdev->device; 879 props->hw_ver = mdev->pdev->revision; 880 881 props->max_mr_size = ~0ull; 882 props->page_size_cap = ~(min_page_size - 1); 883 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 884 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 885 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 886 sizeof(struct mlx5_wqe_data_seg); 887 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512); 888 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) - 889 sizeof(struct mlx5_wqe_raddr_seg)) / 890 sizeof(struct mlx5_wqe_data_seg); 891 props->max_send_sge = max_sq_sg; 892 props->max_recv_sge = max_rq_sg; 893 props->max_sge_rd = MLX5_MAX_SGE_RD; 894 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 895 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 896 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 897 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 898 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 899 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 900 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 901 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 902 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 903 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 904 props->max_srq_sge = max_rq_sg - 1; 905 props->max_fast_reg_page_list_len = 906 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 907 get_atomic_caps_qp(dev, props); 908 props->masked_atomic_cap = IB_ATOMIC_NONE; 909 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 910 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 911 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 912 props->max_mcast_grp; 913 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */ 914 props->max_ah = INT_MAX; 915 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 916 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 917 918 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 919 if (MLX5_CAP_GEN(mdev, pg)) 920 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING; 921 props->odp_caps = dev->odp_caps; 922 #endif 923 924 if (MLX5_CAP_GEN(mdev, cd)) 925 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL; 926 927 if (!mlx5_core_is_pf(mdev)) 928 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION; 929 930 if (mlx5_ib_port_link_layer(ibdev, 1) == 931 IB_LINK_LAYER_ETHERNET && raw_support) { 932 props->rss_caps.max_rwq_indirection_tables = 933 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 934 props->rss_caps.max_rwq_indirection_table_size = 935 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 936 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 937 props->max_wq_type_rq = 938 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 939 } 940 941 if (MLX5_CAP_GEN(mdev, tag_matching)) { 942 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE; 943 props->tm_caps.max_num_tags = 944 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1; 945 props->tm_caps.flags = IB_TM_CAP_RC; 946 props->tm_caps.max_ops = 947 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 948 props->tm_caps.max_sge = MLX5_TM_MAX_SGE; 949 } 950 951 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) { 952 props->cq_caps.max_cq_moderation_count = 953 MLX5_MAX_CQ_COUNT; 954 props->cq_caps.max_cq_moderation_period = 955 MLX5_MAX_CQ_PERIOD; 956 } 957 958 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) { 959 resp.response_length += sizeof(resp.cqe_comp_caps); 960 961 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) { 962 resp.cqe_comp_caps.max_num = 963 MLX5_CAP_GEN(dev->mdev, 964 cqe_compression_max_num); 965 966 resp.cqe_comp_caps.supported_format = 967 MLX5_IB_CQE_RES_FORMAT_HASH | 968 MLX5_IB_CQE_RES_FORMAT_CSUM; 969 970 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index)) 971 resp.cqe_comp_caps.supported_format |= 972 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX; 973 } 974 } 975 976 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen) && 977 raw_support) { 978 if (MLX5_CAP_QOS(mdev, packet_pacing) && 979 MLX5_CAP_GEN(mdev, qos)) { 980 resp.packet_pacing_caps.qp_rate_limit_max = 981 MLX5_CAP_QOS(mdev, packet_pacing_max_rate); 982 resp.packet_pacing_caps.qp_rate_limit_min = 983 MLX5_CAP_QOS(mdev, packet_pacing_min_rate); 984 resp.packet_pacing_caps.supported_qpts |= 985 1 << IB_QPT_RAW_PACKET; 986 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) && 987 MLX5_CAP_QOS(mdev, packet_pacing_typical_size)) 988 resp.packet_pacing_caps.cap_flags |= 989 MLX5_IB_PP_SUPPORT_BURST; 990 } 991 resp.response_length += sizeof(resp.packet_pacing_caps); 992 } 993 994 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes, 995 uhw->outlen)) { 996 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe)) 997 resp.mlx5_ib_support_multi_pkt_send_wqes = 998 MLX5_IB_ALLOW_MPW; 999 1000 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe)) 1001 resp.mlx5_ib_support_multi_pkt_send_wqes |= 1002 MLX5_IB_SUPPORT_EMPW; 1003 1004 resp.response_length += 1005 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes); 1006 } 1007 1008 if (field_avail(typeof(resp), flags, uhw->outlen)) { 1009 resp.response_length += sizeof(resp.flags); 1010 1011 if (MLX5_CAP_GEN(mdev, cqe_compression_128)) 1012 resp.flags |= 1013 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP; 1014 1015 if (MLX5_CAP_GEN(mdev, cqe_128_always)) 1016 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD; 1017 } 1018 1019 if (field_avail(typeof(resp), sw_parsing_caps, 1020 uhw->outlen)) { 1021 resp.response_length += sizeof(resp.sw_parsing_caps); 1022 if (MLX5_CAP_ETH(mdev, swp)) { 1023 resp.sw_parsing_caps.sw_parsing_offloads |= 1024 MLX5_IB_SW_PARSING; 1025 1026 if (MLX5_CAP_ETH(mdev, swp_csum)) 1027 resp.sw_parsing_caps.sw_parsing_offloads |= 1028 MLX5_IB_SW_PARSING_CSUM; 1029 1030 if (MLX5_CAP_ETH(mdev, swp_lso)) 1031 resp.sw_parsing_caps.sw_parsing_offloads |= 1032 MLX5_IB_SW_PARSING_LSO; 1033 1034 if (resp.sw_parsing_caps.sw_parsing_offloads) 1035 resp.sw_parsing_caps.supported_qpts = 1036 BIT(IB_QPT_RAW_PACKET); 1037 } 1038 } 1039 1040 if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen) && 1041 raw_support) { 1042 resp.response_length += sizeof(resp.striding_rq_caps); 1043 if (MLX5_CAP_GEN(mdev, striding_rq)) { 1044 resp.striding_rq_caps.min_single_stride_log_num_of_bytes = 1045 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES; 1046 resp.striding_rq_caps.max_single_stride_log_num_of_bytes = 1047 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES; 1048 resp.striding_rq_caps.min_single_wqe_log_num_of_strides = 1049 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1050 resp.striding_rq_caps.max_single_wqe_log_num_of_strides = 1051 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES; 1052 resp.striding_rq_caps.supported_qpts = 1053 BIT(IB_QPT_RAW_PACKET); 1054 } 1055 } 1056 1057 if (field_avail(typeof(resp), tunnel_offloads_caps, 1058 uhw->outlen)) { 1059 resp.response_length += sizeof(resp.tunnel_offloads_caps); 1060 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan)) 1061 resp.tunnel_offloads_caps |= 1062 MLX5_IB_TUNNELED_OFFLOADS_VXLAN; 1063 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx)) 1064 resp.tunnel_offloads_caps |= 1065 MLX5_IB_TUNNELED_OFFLOADS_GENEVE; 1066 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) 1067 resp.tunnel_offloads_caps |= 1068 MLX5_IB_TUNNELED_OFFLOADS_GRE; 1069 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) & 1070 MLX5_FLEX_PROTO_CW_MPLS_GRE) 1071 resp.tunnel_offloads_caps |= 1072 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE; 1073 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) & 1074 MLX5_FLEX_PROTO_CW_MPLS_UDP) 1075 resp.tunnel_offloads_caps |= 1076 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP; 1077 } 1078 1079 if (uhw->outlen) { 1080 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 1081 1082 if (err) 1083 return err; 1084 } 1085 1086 return 0; 1087 } 1088 1089 enum mlx5_ib_width { 1090 MLX5_IB_WIDTH_1X = 1 << 0, 1091 MLX5_IB_WIDTH_2X = 1 << 1, 1092 MLX5_IB_WIDTH_4X = 1 << 2, 1093 MLX5_IB_WIDTH_8X = 1 << 3, 1094 MLX5_IB_WIDTH_12X = 1 << 4 1095 }; 1096 1097 static int translate_active_width(struct ib_device *ibdev, u8 active_width, 1098 u8 *ib_width) 1099 { 1100 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1101 int err = 0; 1102 1103 if (active_width & MLX5_IB_WIDTH_1X) { 1104 *ib_width = IB_WIDTH_1X; 1105 } else if (active_width & MLX5_IB_WIDTH_2X) { 1106 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n", 1107 (int)active_width); 1108 err = -EINVAL; 1109 } else if (active_width & MLX5_IB_WIDTH_4X) { 1110 *ib_width = IB_WIDTH_4X; 1111 } else if (active_width & MLX5_IB_WIDTH_8X) { 1112 *ib_width = IB_WIDTH_8X; 1113 } else if (active_width & MLX5_IB_WIDTH_12X) { 1114 *ib_width = IB_WIDTH_12X; 1115 } else { 1116 mlx5_ib_dbg(dev, "Invalid active_width %d\n", 1117 (int)active_width); 1118 err = -EINVAL; 1119 } 1120 1121 return err; 1122 } 1123 1124 static int mlx5_mtu_to_ib_mtu(int mtu) 1125 { 1126 switch (mtu) { 1127 case 256: return 1; 1128 case 512: return 2; 1129 case 1024: return 3; 1130 case 2048: return 4; 1131 case 4096: return 5; 1132 default: 1133 pr_warn("invalid mtu\n"); 1134 return -1; 1135 } 1136 } 1137 1138 enum ib_max_vl_num { 1139 __IB_MAX_VL_0 = 1, 1140 __IB_MAX_VL_0_1 = 2, 1141 __IB_MAX_VL_0_3 = 3, 1142 __IB_MAX_VL_0_7 = 4, 1143 __IB_MAX_VL_0_14 = 5, 1144 }; 1145 1146 enum mlx5_vl_hw_cap { 1147 MLX5_VL_HW_0 = 1, 1148 MLX5_VL_HW_0_1 = 2, 1149 MLX5_VL_HW_0_2 = 3, 1150 MLX5_VL_HW_0_3 = 4, 1151 MLX5_VL_HW_0_4 = 5, 1152 MLX5_VL_HW_0_5 = 6, 1153 MLX5_VL_HW_0_6 = 7, 1154 MLX5_VL_HW_0_7 = 8, 1155 MLX5_VL_HW_0_14 = 15 1156 }; 1157 1158 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 1159 u8 *max_vl_num) 1160 { 1161 switch (vl_hw_cap) { 1162 case MLX5_VL_HW_0: 1163 *max_vl_num = __IB_MAX_VL_0; 1164 break; 1165 case MLX5_VL_HW_0_1: 1166 *max_vl_num = __IB_MAX_VL_0_1; 1167 break; 1168 case MLX5_VL_HW_0_3: 1169 *max_vl_num = __IB_MAX_VL_0_3; 1170 break; 1171 case MLX5_VL_HW_0_7: 1172 *max_vl_num = __IB_MAX_VL_0_7; 1173 break; 1174 case MLX5_VL_HW_0_14: 1175 *max_vl_num = __IB_MAX_VL_0_14; 1176 break; 1177 1178 default: 1179 return -EINVAL; 1180 } 1181 1182 return 0; 1183 } 1184 1185 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port, 1186 struct ib_port_attr *props) 1187 { 1188 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1189 struct mlx5_core_dev *mdev = dev->mdev; 1190 struct mlx5_hca_vport_context *rep; 1191 u16 max_mtu; 1192 u16 oper_mtu; 1193 int err; 1194 u8 ib_link_width_oper; 1195 u8 vl_hw_cap; 1196 1197 rep = kzalloc(sizeof(*rep), GFP_KERNEL); 1198 if (!rep) { 1199 err = -ENOMEM; 1200 goto out; 1201 } 1202 1203 /* props being zeroed by the caller, avoid zeroing it here */ 1204 1205 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); 1206 if (err) 1207 goto out; 1208 1209 props->lid = rep->lid; 1210 props->lmc = rep->lmc; 1211 props->sm_lid = rep->sm_lid; 1212 props->sm_sl = rep->sm_sl; 1213 props->state = rep->vport_state; 1214 props->phys_state = rep->port_physical_state; 1215 props->port_cap_flags = rep->cap_mask1; 1216 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 1217 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 1218 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 1219 props->bad_pkey_cntr = rep->pkey_violation_counter; 1220 props->qkey_viol_cntr = rep->qkey_violation_counter; 1221 props->subnet_timeout = rep->subnet_timeout; 1222 props->init_type_reply = rep->init_type_reply; 1223 props->grh_required = rep->grh_required; 1224 1225 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port); 1226 if (err) 1227 goto out; 1228 1229 err = translate_active_width(ibdev, ib_link_width_oper, 1230 &props->active_width); 1231 if (err) 1232 goto out; 1233 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port); 1234 if (err) 1235 goto out; 1236 1237 mlx5_query_port_max_mtu(mdev, &max_mtu, port); 1238 1239 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); 1240 1241 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); 1242 1243 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); 1244 1245 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); 1246 if (err) 1247 goto out; 1248 1249 err = translate_max_vl_num(ibdev, vl_hw_cap, 1250 &props->max_vl_num); 1251 out: 1252 kfree(rep); 1253 return err; 1254 } 1255 1256 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 1257 struct ib_port_attr *props) 1258 { 1259 unsigned int count; 1260 int ret; 1261 1262 switch (mlx5_get_vport_access_method(ibdev)) { 1263 case MLX5_VPORT_ACCESS_METHOD_MAD: 1264 ret = mlx5_query_mad_ifc_port(ibdev, port, props); 1265 break; 1266 1267 case MLX5_VPORT_ACCESS_METHOD_HCA: 1268 ret = mlx5_query_hca_port(ibdev, port, props); 1269 break; 1270 1271 case MLX5_VPORT_ACCESS_METHOD_NIC: 1272 ret = mlx5_query_port_roce(ibdev, port, props); 1273 break; 1274 1275 default: 1276 ret = -EINVAL; 1277 } 1278 1279 if (!ret && props) { 1280 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1281 struct mlx5_core_dev *mdev; 1282 bool put_mdev = true; 1283 1284 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL); 1285 if (!mdev) { 1286 /* If the port isn't affiliated yet query the master. 1287 * The master and slave will have the same values. 1288 */ 1289 mdev = dev->mdev; 1290 port = 1; 1291 put_mdev = false; 1292 } 1293 count = mlx5_core_reserved_gids_count(mdev); 1294 if (put_mdev) 1295 mlx5_ib_put_native_port_mdev(dev, port); 1296 props->gid_tbl_len -= count; 1297 } 1298 return ret; 1299 } 1300 1301 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port, 1302 struct ib_port_attr *props) 1303 { 1304 int ret; 1305 1306 /* Only link layer == ethernet is valid for representors */ 1307 ret = mlx5_query_port_roce(ibdev, port, props); 1308 if (ret || !props) 1309 return ret; 1310 1311 /* We don't support GIDS */ 1312 props->gid_tbl_len = 0; 1313 1314 return ret; 1315 } 1316 1317 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 1318 union ib_gid *gid) 1319 { 1320 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1321 struct mlx5_core_dev *mdev = dev->mdev; 1322 1323 switch (mlx5_get_vport_access_method(ibdev)) { 1324 case MLX5_VPORT_ACCESS_METHOD_MAD: 1325 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 1326 1327 case MLX5_VPORT_ACCESS_METHOD_HCA: 1328 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); 1329 1330 default: 1331 return -EINVAL; 1332 } 1333 1334 } 1335 1336 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port, 1337 u16 index, u16 *pkey) 1338 { 1339 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1340 struct mlx5_core_dev *mdev; 1341 bool put_mdev = true; 1342 u8 mdev_port_num; 1343 int err; 1344 1345 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num); 1346 if (!mdev) { 1347 /* The port isn't affiliated yet, get the PKey from the master 1348 * port. For RoCE the PKey tables will be the same. 1349 */ 1350 put_mdev = false; 1351 mdev = dev->mdev; 1352 mdev_port_num = 1; 1353 } 1354 1355 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0, 1356 index, pkey); 1357 if (put_mdev) 1358 mlx5_ib_put_native_port_mdev(dev, port); 1359 1360 return err; 1361 } 1362 1363 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 1364 u16 *pkey) 1365 { 1366 switch (mlx5_get_vport_access_method(ibdev)) { 1367 case MLX5_VPORT_ACCESS_METHOD_MAD: 1368 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 1369 1370 case MLX5_VPORT_ACCESS_METHOD_HCA: 1371 case MLX5_VPORT_ACCESS_METHOD_NIC: 1372 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey); 1373 default: 1374 return -EINVAL; 1375 } 1376 } 1377 1378 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 1379 struct ib_device_modify *props) 1380 { 1381 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1382 struct mlx5_reg_node_desc in; 1383 struct mlx5_reg_node_desc out; 1384 int err; 1385 1386 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 1387 return -EOPNOTSUPP; 1388 1389 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 1390 return 0; 1391 1392 /* 1393 * If possible, pass node desc to FW, so it can generate 1394 * a 144 trap. If cmd fails, just ignore. 1395 */ 1396 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1397 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 1398 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 1399 if (err) 1400 return err; 1401 1402 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1403 1404 return err; 1405 } 1406 1407 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask, 1408 u32 value) 1409 { 1410 struct mlx5_hca_vport_context ctx = {}; 1411 struct mlx5_core_dev *mdev; 1412 u8 mdev_port_num; 1413 int err; 1414 1415 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 1416 if (!mdev) 1417 return -ENODEV; 1418 1419 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx); 1420 if (err) 1421 goto out; 1422 1423 if (~ctx.cap_mask1_perm & mask) { 1424 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n", 1425 mask, ctx.cap_mask1_perm); 1426 err = -EINVAL; 1427 goto out; 1428 } 1429 1430 ctx.cap_mask1 = value; 1431 ctx.cap_mask1_perm = mask; 1432 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num, 1433 0, &ctx); 1434 1435 out: 1436 mlx5_ib_put_native_port_mdev(dev, port_num); 1437 1438 return err; 1439 } 1440 1441 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, 1442 struct ib_port_modify *props) 1443 { 1444 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1445 struct ib_port_attr attr; 1446 u32 tmp; 1447 int err; 1448 u32 change_mask; 1449 u32 value; 1450 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) == 1451 IB_LINK_LAYER_INFINIBAND); 1452 1453 /* CM layer calls ib_modify_port() regardless of the link layer. For 1454 * Ethernet ports, qkey violation and Port capabilities are meaningless. 1455 */ 1456 if (!is_ib) 1457 return 0; 1458 1459 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) { 1460 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask; 1461 value = ~props->clr_port_cap_mask | props->set_port_cap_mask; 1462 return set_port_caps_atomic(dev, port, change_mask, value); 1463 } 1464 1465 mutex_lock(&dev->cap_mask_mutex); 1466 1467 err = ib_query_port(ibdev, port, &attr); 1468 if (err) 1469 goto out; 1470 1471 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 1472 ~props->clr_port_cap_mask; 1473 1474 err = mlx5_set_port_caps(dev->mdev, port, tmp); 1475 1476 out: 1477 mutex_unlock(&dev->cap_mask_mutex); 1478 return err; 1479 } 1480 1481 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps) 1482 { 1483 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n", 1484 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n"); 1485 } 1486 1487 static u16 calc_dynamic_bfregs(int uars_per_sys_page) 1488 { 1489 /* Large page with non 4k uar support might limit the dynamic size */ 1490 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096) 1491 return MLX5_MIN_DYN_BFREGS; 1492 1493 return MLX5_MAX_DYN_BFREGS; 1494 } 1495 1496 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k, 1497 struct mlx5_ib_alloc_ucontext_req_v2 *req, 1498 struct mlx5_bfreg_info *bfregi) 1499 { 1500 int uars_per_sys_page; 1501 int bfregs_per_sys_page; 1502 int ref_bfregs = req->total_num_bfregs; 1503 1504 if (req->total_num_bfregs == 0) 1505 return -EINVAL; 1506 1507 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE); 1508 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE); 1509 1510 if (req->total_num_bfregs > MLX5_MAX_BFREGS) 1511 return -ENOMEM; 1512 1513 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k); 1514 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR; 1515 /* This holds the required static allocation asked by the user */ 1516 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page); 1517 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1) 1518 return -EINVAL; 1519 1520 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page; 1521 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page); 1522 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs; 1523 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page; 1524 1525 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n", 1526 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no", 1527 lib_uar_4k ? "yes" : "no", ref_bfregs, 1528 req->total_num_bfregs, bfregi->total_num_bfregs, 1529 bfregi->num_sys_pages); 1530 1531 return 0; 1532 } 1533 1534 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1535 { 1536 struct mlx5_bfreg_info *bfregi; 1537 int err; 1538 int i; 1539 1540 bfregi = &context->bfregi; 1541 for (i = 0; i < bfregi->num_static_sys_pages; i++) { 1542 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]); 1543 if (err) 1544 goto error; 1545 1546 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]); 1547 } 1548 1549 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++) 1550 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX; 1551 1552 return 0; 1553 1554 error: 1555 for (--i; i >= 0; i--) 1556 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i])) 1557 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1558 1559 return err; 1560 } 1561 1562 static int deallocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1563 { 1564 struct mlx5_bfreg_info *bfregi; 1565 int err; 1566 int i; 1567 1568 bfregi = &context->bfregi; 1569 for (i = 0; i < bfregi->num_sys_pages; i++) { 1570 if (i < bfregi->num_static_sys_pages || 1571 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) { 1572 err = mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]); 1573 if (err) { 1574 mlx5_ib_warn(dev, "failed to free uar %d, err=%d\n", i, err); 1575 return err; 1576 } 1577 } 1578 } 1579 1580 return 0; 1581 } 1582 1583 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn) 1584 { 1585 int err; 1586 1587 err = mlx5_core_alloc_transport_domain(dev->mdev, tdn); 1588 if (err) 1589 return err; 1590 1591 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1592 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1593 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1594 return err; 1595 1596 mutex_lock(&dev->lb_mutex); 1597 dev->user_td++; 1598 1599 if (dev->user_td == 2) 1600 err = mlx5_nic_vport_update_local_lb(dev->mdev, true); 1601 1602 mutex_unlock(&dev->lb_mutex); 1603 return err; 1604 } 1605 1606 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn) 1607 { 1608 mlx5_core_dealloc_transport_domain(dev->mdev, tdn); 1609 1610 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1611 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1612 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1613 return; 1614 1615 mutex_lock(&dev->lb_mutex); 1616 dev->user_td--; 1617 1618 if (dev->user_td < 2) 1619 mlx5_nic_vport_update_local_lb(dev->mdev, false); 1620 1621 mutex_unlock(&dev->lb_mutex); 1622 } 1623 1624 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev, 1625 struct ib_udata *udata) 1626 { 1627 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1628 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 1629 struct mlx5_ib_alloc_ucontext_resp resp = {}; 1630 struct mlx5_core_dev *mdev = dev->mdev; 1631 struct mlx5_ib_ucontext *context; 1632 struct mlx5_bfreg_info *bfregi; 1633 int ver; 1634 int err; 1635 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 1636 max_cqe_version); 1637 bool lib_uar_4k; 1638 1639 if (!dev->ib_active) 1640 return ERR_PTR(-EAGAIN); 1641 1642 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 1643 ver = 0; 1644 else if (udata->inlen >= min_req_v2) 1645 ver = 2; 1646 else 1647 return ERR_PTR(-EINVAL); 1648 1649 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req))); 1650 if (err) 1651 return ERR_PTR(err); 1652 1653 if (req.flags) 1654 return ERR_PTR(-EINVAL); 1655 1656 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 1657 return ERR_PTR(-EOPNOTSUPP); 1658 1659 req.total_num_bfregs = ALIGN(req.total_num_bfregs, 1660 MLX5_NON_FP_BFREGS_PER_UAR); 1661 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1) 1662 return ERR_PTR(-EINVAL); 1663 1664 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 1665 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf)) 1666 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size); 1667 resp.cache_line_size = cache_line_size(); 1668 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 1669 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 1670 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1671 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1672 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 1673 resp.cqe_version = min_t(__u8, 1674 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 1675 req.max_cqe_version); 1676 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1677 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT; 1678 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1679 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1; 1680 resp.response_length = min(offsetof(typeof(resp), response_length) + 1681 sizeof(resp.response_length), udata->outlen); 1682 1683 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE) { 1684 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_EGRESS)) 1685 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM; 1686 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA) 1687 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA; 1688 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi)) 1689 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING; 1690 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN) 1691 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN; 1692 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */ 1693 } 1694 1695 context = kzalloc(sizeof(*context), GFP_KERNEL); 1696 if (!context) 1697 return ERR_PTR(-ENOMEM); 1698 1699 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR; 1700 bfregi = &context->bfregi; 1701 1702 /* updates req->total_num_bfregs */ 1703 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi); 1704 if (err) 1705 goto out_ctx; 1706 1707 mutex_init(&bfregi->lock); 1708 bfregi->lib_uar_4k = lib_uar_4k; 1709 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count), 1710 GFP_KERNEL); 1711 if (!bfregi->count) { 1712 err = -ENOMEM; 1713 goto out_ctx; 1714 } 1715 1716 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages, 1717 sizeof(*bfregi->sys_pages), 1718 GFP_KERNEL); 1719 if (!bfregi->sys_pages) { 1720 err = -ENOMEM; 1721 goto out_count; 1722 } 1723 1724 err = allocate_uars(dev, context); 1725 if (err) 1726 goto out_sys_pages; 1727 1728 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1729 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range; 1730 #endif 1731 1732 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) { 1733 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn); 1734 if (err) 1735 goto out_uars; 1736 } 1737 1738 INIT_LIST_HEAD(&context->vma_private_list); 1739 mutex_init(&context->vma_private_list_mutex); 1740 INIT_LIST_HEAD(&context->db_page_list); 1741 mutex_init(&context->db_page_mutex); 1742 1743 resp.tot_bfregs = req.total_num_bfregs; 1744 resp.num_ports = dev->num_ports; 1745 1746 if (field_avail(typeof(resp), cqe_version, udata->outlen)) 1747 resp.response_length += sizeof(resp.cqe_version); 1748 1749 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) { 1750 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 1751 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 1752 resp.response_length += sizeof(resp.cmds_supp_uhw); 1753 } 1754 1755 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) { 1756 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) { 1757 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline); 1758 resp.eth_min_inline++; 1759 } 1760 resp.response_length += sizeof(resp.eth_min_inline); 1761 } 1762 1763 if (field_avail(typeof(resp), clock_info_versions, udata->outlen)) { 1764 if (mdev->clock_info) 1765 resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1); 1766 resp.response_length += sizeof(resp.clock_info_versions); 1767 } 1768 1769 /* 1770 * We don't want to expose information from the PCI bar that is located 1771 * after 4096 bytes, so if the arch only supports larger pages, let's 1772 * pretend we don't support reading the HCA's core clock. This is also 1773 * forced by mmap function. 1774 */ 1775 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) { 1776 if (PAGE_SIZE <= 4096) { 1777 resp.comp_mask |= 1778 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 1779 resp.hca_core_clock_offset = 1780 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE; 1781 } 1782 resp.response_length += sizeof(resp.hca_core_clock_offset); 1783 } 1784 1785 if (field_avail(typeof(resp), log_uar_size, udata->outlen)) 1786 resp.response_length += sizeof(resp.log_uar_size); 1787 1788 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen)) 1789 resp.response_length += sizeof(resp.num_uars_per_page); 1790 1791 if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) { 1792 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs; 1793 resp.response_length += sizeof(resp.num_dyn_bfregs); 1794 } 1795 1796 err = ib_copy_to_udata(udata, &resp, resp.response_length); 1797 if (err) 1798 goto out_td; 1799 1800 bfregi->ver = ver; 1801 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs; 1802 context->cqe_version = resp.cqe_version; 1803 context->lib_caps = req.lib_caps; 1804 print_lib_caps(dev, context->lib_caps); 1805 1806 return &context->ibucontext; 1807 1808 out_td: 1809 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1810 mlx5_ib_dealloc_transport_domain(dev, context->tdn); 1811 1812 out_uars: 1813 deallocate_uars(dev, context); 1814 1815 out_sys_pages: 1816 kfree(bfregi->sys_pages); 1817 1818 out_count: 1819 kfree(bfregi->count); 1820 1821 out_ctx: 1822 kfree(context); 1823 1824 return ERR_PTR(err); 1825 } 1826 1827 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1828 { 1829 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1830 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1831 struct mlx5_bfreg_info *bfregi; 1832 1833 bfregi = &context->bfregi; 1834 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1835 mlx5_ib_dealloc_transport_domain(dev, context->tdn); 1836 1837 deallocate_uars(dev, context); 1838 kfree(bfregi->sys_pages); 1839 kfree(bfregi->count); 1840 kfree(context); 1841 1842 return 0; 1843 } 1844 1845 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, 1846 int uar_idx) 1847 { 1848 int fw_uars_per_page; 1849 1850 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1; 1851 1852 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + uar_idx / fw_uars_per_page; 1853 } 1854 1855 static int get_command(unsigned long offset) 1856 { 1857 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 1858 } 1859 1860 static int get_arg(unsigned long offset) 1861 { 1862 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 1863 } 1864 1865 static int get_index(unsigned long offset) 1866 { 1867 return get_arg(offset); 1868 } 1869 1870 /* Index resides in an extra byte to enable larger values than 255 */ 1871 static int get_extended_index(unsigned long offset) 1872 { 1873 return get_arg(offset) | ((offset >> 16) & 0xff) << 8; 1874 } 1875 1876 static void mlx5_ib_vma_open(struct vm_area_struct *area) 1877 { 1878 /* vma_open is called when a new VMA is created on top of our VMA. This 1879 * is done through either mremap flow or split_vma (usually due to 1880 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA, 1881 * as this VMA is strongly hardware related. Therefore we set the 1882 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from 1883 * calling us again and trying to do incorrect actions. We assume that 1884 * the original VMA size is exactly a single page, and therefore all 1885 * "splitting" operation will not happen to it. 1886 */ 1887 area->vm_ops = NULL; 1888 } 1889 1890 static void mlx5_ib_vma_close(struct vm_area_struct *area) 1891 { 1892 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data; 1893 1894 /* It's guaranteed that all VMAs opened on a FD are closed before the 1895 * file itself is closed, therefore no sync is needed with the regular 1896 * closing flow. (e.g. mlx5 ib_dealloc_ucontext) 1897 * However need a sync with accessing the vma as part of 1898 * mlx5_ib_disassociate_ucontext. 1899 * The close operation is usually called under mm->mmap_sem except when 1900 * process is exiting. 1901 * The exiting case is handled explicitly as part of 1902 * mlx5_ib_disassociate_ucontext. 1903 */ 1904 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data; 1905 1906 /* setting the vma context pointer to null in the mlx5_ib driver's 1907 * private data, to protect a race condition in 1908 * mlx5_ib_disassociate_ucontext(). 1909 */ 1910 mlx5_ib_vma_priv_data->vma = NULL; 1911 mutex_lock(mlx5_ib_vma_priv_data->vma_private_list_mutex); 1912 list_del(&mlx5_ib_vma_priv_data->list); 1913 mutex_unlock(mlx5_ib_vma_priv_data->vma_private_list_mutex); 1914 kfree(mlx5_ib_vma_priv_data); 1915 } 1916 1917 static const struct vm_operations_struct mlx5_ib_vm_ops = { 1918 .open = mlx5_ib_vma_open, 1919 .close = mlx5_ib_vma_close 1920 }; 1921 1922 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma, 1923 struct mlx5_ib_ucontext *ctx) 1924 { 1925 struct mlx5_ib_vma_private_data *vma_prv; 1926 struct list_head *vma_head = &ctx->vma_private_list; 1927 1928 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL); 1929 if (!vma_prv) 1930 return -ENOMEM; 1931 1932 vma_prv->vma = vma; 1933 vma_prv->vma_private_list_mutex = &ctx->vma_private_list_mutex; 1934 vma->vm_private_data = vma_prv; 1935 vma->vm_ops = &mlx5_ib_vm_ops; 1936 1937 mutex_lock(&ctx->vma_private_list_mutex); 1938 list_add(&vma_prv->list, vma_head); 1939 mutex_unlock(&ctx->vma_private_list_mutex); 1940 1941 return 0; 1942 } 1943 1944 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 1945 { 1946 struct vm_area_struct *vma; 1947 struct mlx5_ib_vma_private_data *vma_private, *n; 1948 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1949 1950 mutex_lock(&context->vma_private_list_mutex); 1951 list_for_each_entry_safe(vma_private, n, &context->vma_private_list, 1952 list) { 1953 vma = vma_private->vma; 1954 zap_vma_ptes(vma, vma->vm_start, PAGE_SIZE); 1955 /* context going to be destroyed, should 1956 * not access ops any more. 1957 */ 1958 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE); 1959 vma->vm_ops = NULL; 1960 list_del(&vma_private->list); 1961 kfree(vma_private); 1962 } 1963 mutex_unlock(&context->vma_private_list_mutex); 1964 } 1965 1966 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 1967 { 1968 switch (cmd) { 1969 case MLX5_IB_MMAP_WC_PAGE: 1970 return "WC"; 1971 case MLX5_IB_MMAP_REGULAR_PAGE: 1972 return "best effort WC"; 1973 case MLX5_IB_MMAP_NC_PAGE: 1974 return "NC"; 1975 case MLX5_IB_MMAP_DEVICE_MEM: 1976 return "Device Memory"; 1977 default: 1978 return NULL; 1979 } 1980 } 1981 1982 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev, 1983 struct vm_area_struct *vma, 1984 struct mlx5_ib_ucontext *context) 1985 { 1986 phys_addr_t pfn; 1987 int err; 1988 1989 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1990 return -EINVAL; 1991 1992 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1) 1993 return -EOPNOTSUPP; 1994 1995 if (vma->vm_flags & VM_WRITE) 1996 return -EPERM; 1997 1998 if (!dev->mdev->clock_info_page) 1999 return -EOPNOTSUPP; 2000 2001 pfn = page_to_pfn(dev->mdev->clock_info_page); 2002 err = remap_pfn_range(vma, vma->vm_start, pfn, PAGE_SIZE, 2003 vma->vm_page_prot); 2004 if (err) 2005 return err; 2006 2007 return mlx5_ib_set_vma_data(vma, context); 2008 } 2009 2010 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 2011 struct vm_area_struct *vma, 2012 struct mlx5_ib_ucontext *context) 2013 { 2014 struct mlx5_bfreg_info *bfregi = &context->bfregi; 2015 int err; 2016 unsigned long idx; 2017 phys_addr_t pfn, pa; 2018 pgprot_t prot; 2019 u32 bfreg_dyn_idx = 0; 2020 u32 uar_index; 2021 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC); 2022 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages : 2023 bfregi->num_static_sys_pages; 2024 2025 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2026 return -EINVAL; 2027 2028 if (dyn_uar) 2029 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages; 2030 else 2031 idx = get_index(vma->vm_pgoff); 2032 2033 if (idx >= max_valid_idx) { 2034 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n", 2035 idx, max_valid_idx); 2036 return -EINVAL; 2037 } 2038 2039 switch (cmd) { 2040 case MLX5_IB_MMAP_WC_PAGE: 2041 case MLX5_IB_MMAP_ALLOC_WC: 2042 /* Some architectures don't support WC memory */ 2043 #if defined(CONFIG_X86) 2044 if (!pat_enabled()) 2045 return -EPERM; 2046 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU))) 2047 return -EPERM; 2048 #endif 2049 /* fall through */ 2050 case MLX5_IB_MMAP_REGULAR_PAGE: 2051 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 2052 prot = pgprot_writecombine(vma->vm_page_prot); 2053 break; 2054 case MLX5_IB_MMAP_NC_PAGE: 2055 prot = pgprot_noncached(vma->vm_page_prot); 2056 break; 2057 default: 2058 return -EINVAL; 2059 } 2060 2061 if (dyn_uar) { 2062 int uars_per_page; 2063 2064 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k); 2065 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR); 2066 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) { 2067 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n", 2068 bfreg_dyn_idx, bfregi->total_num_bfregs); 2069 return -EINVAL; 2070 } 2071 2072 mutex_lock(&bfregi->lock); 2073 /* Fail if uar already allocated, first bfreg index of each 2074 * page holds its count. 2075 */ 2076 if (bfregi->count[bfreg_dyn_idx]) { 2077 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx); 2078 mutex_unlock(&bfregi->lock); 2079 return -EINVAL; 2080 } 2081 2082 bfregi->count[bfreg_dyn_idx]++; 2083 mutex_unlock(&bfregi->lock); 2084 2085 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index); 2086 if (err) { 2087 mlx5_ib_warn(dev, "UAR alloc failed\n"); 2088 goto free_bfreg; 2089 } 2090 } else { 2091 uar_index = bfregi->sys_pages[idx]; 2092 } 2093 2094 pfn = uar_index2pfn(dev, uar_index); 2095 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 2096 2097 vma->vm_page_prot = prot; 2098 err = io_remap_pfn_range(vma, vma->vm_start, pfn, 2099 PAGE_SIZE, vma->vm_page_prot); 2100 if (err) { 2101 mlx5_ib_err(dev, 2102 "io_remap_pfn_range failed with error=%d, mmap_cmd=%s\n", 2103 err, mmap_cmd2str(cmd)); 2104 err = -EAGAIN; 2105 goto err; 2106 } 2107 2108 pa = pfn << PAGE_SHIFT; 2109 2110 err = mlx5_ib_set_vma_data(vma, context); 2111 if (err) 2112 goto err; 2113 2114 if (dyn_uar) 2115 bfregi->sys_pages[idx] = uar_index; 2116 return 0; 2117 2118 err: 2119 if (!dyn_uar) 2120 return err; 2121 2122 mlx5_cmd_free_uar(dev->mdev, idx); 2123 2124 free_bfreg: 2125 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx); 2126 2127 return err; 2128 } 2129 2130 static int dm_mmap(struct ib_ucontext *context, struct vm_area_struct *vma) 2131 { 2132 struct mlx5_ib_ucontext *mctx = to_mucontext(context); 2133 struct mlx5_ib_dev *dev = to_mdev(context->device); 2134 u16 page_idx = get_extended_index(vma->vm_pgoff); 2135 size_t map_size = vma->vm_end - vma->vm_start; 2136 u32 npages = map_size >> PAGE_SHIFT; 2137 phys_addr_t pfn; 2138 pgprot_t prot; 2139 2140 if (find_next_zero_bit(mctx->dm_pages, page_idx + npages, page_idx) != 2141 page_idx + npages) 2142 return -EINVAL; 2143 2144 pfn = ((pci_resource_start(dev->mdev->pdev, 0) + 2145 MLX5_CAP64_DEV_MEM(dev->mdev, memic_bar_start_addr)) >> 2146 PAGE_SHIFT) + 2147 page_idx; 2148 prot = pgprot_writecombine(vma->vm_page_prot); 2149 vma->vm_page_prot = prot; 2150 2151 if (io_remap_pfn_range(vma, vma->vm_start, pfn, map_size, 2152 vma->vm_page_prot)) 2153 return -EAGAIN; 2154 2155 return mlx5_ib_set_vma_data(vma, mctx); 2156 } 2157 2158 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 2159 { 2160 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2161 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2162 unsigned long command; 2163 phys_addr_t pfn; 2164 2165 command = get_command(vma->vm_pgoff); 2166 switch (command) { 2167 case MLX5_IB_MMAP_WC_PAGE: 2168 case MLX5_IB_MMAP_NC_PAGE: 2169 case MLX5_IB_MMAP_REGULAR_PAGE: 2170 case MLX5_IB_MMAP_ALLOC_WC: 2171 return uar_mmap(dev, command, vma, context); 2172 2173 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 2174 return -ENOSYS; 2175 2176 case MLX5_IB_MMAP_CORE_CLOCK: 2177 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2178 return -EINVAL; 2179 2180 if (vma->vm_flags & VM_WRITE) 2181 return -EPERM; 2182 2183 /* Don't expose to user-space information it shouldn't have */ 2184 if (PAGE_SIZE > 4096) 2185 return -EOPNOTSUPP; 2186 2187 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 2188 pfn = (dev->mdev->iseg_base + 2189 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 2190 PAGE_SHIFT; 2191 if (io_remap_pfn_range(vma, vma->vm_start, pfn, 2192 PAGE_SIZE, vma->vm_page_prot)) 2193 return -EAGAIN; 2194 break; 2195 case MLX5_IB_MMAP_CLOCK_INFO: 2196 return mlx5_ib_mmap_clock_info_page(dev, vma, context); 2197 2198 case MLX5_IB_MMAP_DEVICE_MEM: 2199 return dm_mmap(ibcontext, vma); 2200 2201 default: 2202 return -EINVAL; 2203 } 2204 2205 return 0; 2206 } 2207 2208 struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev, 2209 struct ib_ucontext *context, 2210 struct ib_dm_alloc_attr *attr, 2211 struct uverbs_attr_bundle *attrs) 2212 { 2213 u64 act_size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE); 2214 struct mlx5_memic *memic = &to_mdev(ibdev)->memic; 2215 phys_addr_t memic_addr; 2216 struct mlx5_ib_dm *dm; 2217 u64 start_offset; 2218 u32 page_idx; 2219 int err; 2220 2221 dm = kzalloc(sizeof(*dm), GFP_KERNEL); 2222 if (!dm) 2223 return ERR_PTR(-ENOMEM); 2224 2225 mlx5_ib_dbg(to_mdev(ibdev), "alloc_memic req: user_length=0x%llx act_length=0x%llx log_alignment=%d\n", 2226 attr->length, act_size, attr->alignment); 2227 2228 err = mlx5_cmd_alloc_memic(memic, &memic_addr, 2229 act_size, attr->alignment); 2230 if (err) 2231 goto err_free; 2232 2233 start_offset = memic_addr & ~PAGE_MASK; 2234 page_idx = (memic_addr - pci_resource_start(memic->dev->pdev, 0) - 2235 MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >> 2236 PAGE_SHIFT; 2237 2238 err = uverbs_copy_to(attrs, 2239 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET, 2240 &start_offset, sizeof(start_offset)); 2241 if (err) 2242 goto err_dealloc; 2243 2244 err = uverbs_copy_to(attrs, 2245 MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX, 2246 &page_idx, sizeof(page_idx)); 2247 if (err) 2248 goto err_dealloc; 2249 2250 bitmap_set(to_mucontext(context)->dm_pages, page_idx, 2251 DIV_ROUND_UP(act_size, PAGE_SIZE)); 2252 2253 dm->dev_addr = memic_addr; 2254 2255 return &dm->ibdm; 2256 2257 err_dealloc: 2258 mlx5_cmd_dealloc_memic(memic, memic_addr, 2259 act_size); 2260 err_free: 2261 kfree(dm); 2262 return ERR_PTR(err); 2263 } 2264 2265 int mlx5_ib_dealloc_dm(struct ib_dm *ibdm) 2266 { 2267 struct mlx5_memic *memic = &to_mdev(ibdm->device)->memic; 2268 struct mlx5_ib_dm *dm = to_mdm(ibdm); 2269 u64 act_size = roundup(dm->ibdm.length, MLX5_MEMIC_BASE_SIZE); 2270 u32 page_idx; 2271 int ret; 2272 2273 ret = mlx5_cmd_dealloc_memic(memic, dm->dev_addr, act_size); 2274 if (ret) 2275 return ret; 2276 2277 page_idx = (dm->dev_addr - pci_resource_start(memic->dev->pdev, 0) - 2278 MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >> 2279 PAGE_SHIFT; 2280 bitmap_clear(to_mucontext(ibdm->uobject->context)->dm_pages, 2281 page_idx, 2282 DIV_ROUND_UP(act_size, PAGE_SIZE)); 2283 2284 kfree(dm); 2285 2286 return 0; 2287 } 2288 2289 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev, 2290 struct ib_ucontext *context, 2291 struct ib_udata *udata) 2292 { 2293 struct mlx5_ib_alloc_pd_resp resp; 2294 struct mlx5_ib_pd *pd; 2295 int err; 2296 2297 pd = kmalloc(sizeof(*pd), GFP_KERNEL); 2298 if (!pd) 2299 return ERR_PTR(-ENOMEM); 2300 2301 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn); 2302 if (err) { 2303 kfree(pd); 2304 return ERR_PTR(err); 2305 } 2306 2307 if (context) { 2308 resp.pdn = pd->pdn; 2309 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 2310 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn); 2311 kfree(pd); 2312 return ERR_PTR(-EFAULT); 2313 } 2314 } 2315 2316 return &pd->ibpd; 2317 } 2318 2319 static int mlx5_ib_dealloc_pd(struct ib_pd *pd) 2320 { 2321 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 2322 struct mlx5_ib_pd *mpd = to_mpd(pd); 2323 2324 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn); 2325 kfree(mpd); 2326 2327 return 0; 2328 } 2329 2330 enum { 2331 MATCH_CRITERIA_ENABLE_OUTER_BIT, 2332 MATCH_CRITERIA_ENABLE_MISC_BIT, 2333 MATCH_CRITERIA_ENABLE_INNER_BIT, 2334 MATCH_CRITERIA_ENABLE_MISC2_BIT 2335 }; 2336 2337 #define HEADER_IS_ZERO(match_criteria, headers) \ 2338 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \ 2339 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \ 2340 2341 static u8 get_match_criteria_enable(u32 *match_criteria) 2342 { 2343 u8 match_criteria_enable; 2344 2345 match_criteria_enable = 2346 (!HEADER_IS_ZERO(match_criteria, outer_headers)) << 2347 MATCH_CRITERIA_ENABLE_OUTER_BIT; 2348 match_criteria_enable |= 2349 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) << 2350 MATCH_CRITERIA_ENABLE_MISC_BIT; 2351 match_criteria_enable |= 2352 (!HEADER_IS_ZERO(match_criteria, inner_headers)) << 2353 MATCH_CRITERIA_ENABLE_INNER_BIT; 2354 match_criteria_enable |= 2355 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) << 2356 MATCH_CRITERIA_ENABLE_MISC2_BIT; 2357 2358 return match_criteria_enable; 2359 } 2360 2361 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val) 2362 { 2363 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask); 2364 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val); 2365 } 2366 2367 static void set_flow_label(void *misc_c, void *misc_v, u32 mask, u32 val, 2368 bool inner) 2369 { 2370 if (inner) { 2371 MLX5_SET(fte_match_set_misc, 2372 misc_c, inner_ipv6_flow_label, mask); 2373 MLX5_SET(fte_match_set_misc, 2374 misc_v, inner_ipv6_flow_label, val); 2375 } else { 2376 MLX5_SET(fte_match_set_misc, 2377 misc_c, outer_ipv6_flow_label, mask); 2378 MLX5_SET(fte_match_set_misc, 2379 misc_v, outer_ipv6_flow_label, val); 2380 } 2381 } 2382 2383 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val) 2384 { 2385 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask); 2386 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val); 2387 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2); 2388 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2); 2389 } 2390 2391 static int check_mpls_supp_fields(u32 field_support, const __be32 *set_mask) 2392 { 2393 if (MLX5_GET(fte_match_mpls, set_mask, mpls_label) && 2394 !(field_support & MLX5_FIELD_SUPPORT_MPLS_LABEL)) 2395 return -EOPNOTSUPP; 2396 2397 if (MLX5_GET(fte_match_mpls, set_mask, mpls_exp) && 2398 !(field_support & MLX5_FIELD_SUPPORT_MPLS_EXP)) 2399 return -EOPNOTSUPP; 2400 2401 if (MLX5_GET(fte_match_mpls, set_mask, mpls_s_bos) && 2402 !(field_support & MLX5_FIELD_SUPPORT_MPLS_S_BOS)) 2403 return -EOPNOTSUPP; 2404 2405 if (MLX5_GET(fte_match_mpls, set_mask, mpls_ttl) && 2406 !(field_support & MLX5_FIELD_SUPPORT_MPLS_TTL)) 2407 return -EOPNOTSUPP; 2408 2409 return 0; 2410 } 2411 2412 #define LAST_ETH_FIELD vlan_tag 2413 #define LAST_IB_FIELD sl 2414 #define LAST_IPV4_FIELD tos 2415 #define LAST_IPV6_FIELD traffic_class 2416 #define LAST_TCP_UDP_FIELD src_port 2417 #define LAST_TUNNEL_FIELD tunnel_id 2418 #define LAST_FLOW_TAG_FIELD tag_id 2419 #define LAST_DROP_FIELD size 2420 #define LAST_COUNTERS_FIELD counters 2421 2422 /* Field is the last supported field */ 2423 #define FIELDS_NOT_SUPPORTED(filter, field)\ 2424 memchr_inv((void *)&filter.field +\ 2425 sizeof(filter.field), 0,\ 2426 sizeof(filter) -\ 2427 offsetof(typeof(filter), field) -\ 2428 sizeof(filter.field)) 2429 2430 static int parse_flow_flow_action(const union ib_flow_spec *ib_spec, 2431 const struct ib_flow_attr *flow_attr, 2432 struct mlx5_flow_act *action) 2433 { 2434 struct mlx5_ib_flow_action *maction = to_mflow_act(ib_spec->action.act); 2435 2436 switch (maction->ib_action.type) { 2437 case IB_FLOW_ACTION_ESP: 2438 /* Currently only AES_GCM keymat is supported by the driver */ 2439 action->esp_id = (uintptr_t)maction->esp_aes_gcm.ctx; 2440 action->action |= flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS ? 2441 MLX5_FLOW_CONTEXT_ACTION_ENCRYPT : 2442 MLX5_FLOW_CONTEXT_ACTION_DECRYPT; 2443 return 0; 2444 default: 2445 return -EOPNOTSUPP; 2446 } 2447 } 2448 2449 static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c, 2450 u32 *match_v, const union ib_flow_spec *ib_spec, 2451 const struct ib_flow_attr *flow_attr, 2452 struct mlx5_flow_act *action, u32 prev_type) 2453 { 2454 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c, 2455 misc_parameters); 2456 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v, 2457 misc_parameters); 2458 void *misc_params2_c = MLX5_ADDR_OF(fte_match_param, match_c, 2459 misc_parameters_2); 2460 void *misc_params2_v = MLX5_ADDR_OF(fte_match_param, match_v, 2461 misc_parameters_2); 2462 void *headers_c; 2463 void *headers_v; 2464 int match_ipv; 2465 int ret; 2466 2467 if (ib_spec->type & IB_FLOW_SPEC_INNER) { 2468 headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 2469 inner_headers); 2470 headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 2471 inner_headers); 2472 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2473 ft_field_support.inner_ip_version); 2474 } else { 2475 headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 2476 outer_headers); 2477 headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 2478 outer_headers); 2479 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2480 ft_field_support.outer_ip_version); 2481 } 2482 2483 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) { 2484 case IB_FLOW_SPEC_ETH: 2485 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD)) 2486 return -EOPNOTSUPP; 2487 2488 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2489 dmac_47_16), 2490 ib_spec->eth.mask.dst_mac); 2491 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2492 dmac_47_16), 2493 ib_spec->eth.val.dst_mac); 2494 2495 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2496 smac_47_16), 2497 ib_spec->eth.mask.src_mac); 2498 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2499 smac_47_16), 2500 ib_spec->eth.val.src_mac); 2501 2502 if (ib_spec->eth.mask.vlan_tag) { 2503 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2504 cvlan_tag, 1); 2505 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2506 cvlan_tag, 1); 2507 2508 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2509 first_vid, ntohs(ib_spec->eth.mask.vlan_tag)); 2510 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2511 first_vid, ntohs(ib_spec->eth.val.vlan_tag)); 2512 2513 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2514 first_cfi, 2515 ntohs(ib_spec->eth.mask.vlan_tag) >> 12); 2516 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2517 first_cfi, 2518 ntohs(ib_spec->eth.val.vlan_tag) >> 12); 2519 2520 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2521 first_prio, 2522 ntohs(ib_spec->eth.mask.vlan_tag) >> 13); 2523 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2524 first_prio, 2525 ntohs(ib_spec->eth.val.vlan_tag) >> 13); 2526 } 2527 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2528 ethertype, ntohs(ib_spec->eth.mask.ether_type)); 2529 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2530 ethertype, ntohs(ib_spec->eth.val.ether_type)); 2531 break; 2532 case IB_FLOW_SPEC_IPV4: 2533 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD)) 2534 return -EOPNOTSUPP; 2535 2536 if (match_ipv) { 2537 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2538 ip_version, 0xf); 2539 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2540 ip_version, MLX5_FS_IPV4_VERSION); 2541 } else { 2542 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2543 ethertype, 0xffff); 2544 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2545 ethertype, ETH_P_IP); 2546 } 2547 2548 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2549 src_ipv4_src_ipv6.ipv4_layout.ipv4), 2550 &ib_spec->ipv4.mask.src_ip, 2551 sizeof(ib_spec->ipv4.mask.src_ip)); 2552 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2553 src_ipv4_src_ipv6.ipv4_layout.ipv4), 2554 &ib_spec->ipv4.val.src_ip, 2555 sizeof(ib_spec->ipv4.val.src_ip)); 2556 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2557 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 2558 &ib_spec->ipv4.mask.dst_ip, 2559 sizeof(ib_spec->ipv4.mask.dst_ip)); 2560 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2561 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 2562 &ib_spec->ipv4.val.dst_ip, 2563 sizeof(ib_spec->ipv4.val.dst_ip)); 2564 2565 set_tos(headers_c, headers_v, 2566 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos); 2567 2568 set_proto(headers_c, headers_v, 2569 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto); 2570 break; 2571 case IB_FLOW_SPEC_IPV6: 2572 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD)) 2573 return -EOPNOTSUPP; 2574 2575 if (match_ipv) { 2576 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2577 ip_version, 0xf); 2578 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2579 ip_version, MLX5_FS_IPV6_VERSION); 2580 } else { 2581 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2582 ethertype, 0xffff); 2583 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2584 ethertype, ETH_P_IPV6); 2585 } 2586 2587 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2588 src_ipv4_src_ipv6.ipv6_layout.ipv6), 2589 &ib_spec->ipv6.mask.src_ip, 2590 sizeof(ib_spec->ipv6.mask.src_ip)); 2591 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2592 src_ipv4_src_ipv6.ipv6_layout.ipv6), 2593 &ib_spec->ipv6.val.src_ip, 2594 sizeof(ib_spec->ipv6.val.src_ip)); 2595 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2596 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 2597 &ib_spec->ipv6.mask.dst_ip, 2598 sizeof(ib_spec->ipv6.mask.dst_ip)); 2599 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2600 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 2601 &ib_spec->ipv6.val.dst_ip, 2602 sizeof(ib_spec->ipv6.val.dst_ip)); 2603 2604 set_tos(headers_c, headers_v, 2605 ib_spec->ipv6.mask.traffic_class, 2606 ib_spec->ipv6.val.traffic_class); 2607 2608 set_proto(headers_c, headers_v, 2609 ib_spec->ipv6.mask.next_hdr, 2610 ib_spec->ipv6.val.next_hdr); 2611 2612 set_flow_label(misc_params_c, misc_params_v, 2613 ntohl(ib_spec->ipv6.mask.flow_label), 2614 ntohl(ib_spec->ipv6.val.flow_label), 2615 ib_spec->type & IB_FLOW_SPEC_INNER); 2616 break; 2617 case IB_FLOW_SPEC_ESP: 2618 if (ib_spec->esp.mask.seq) 2619 return -EOPNOTSUPP; 2620 2621 MLX5_SET(fte_match_set_misc, misc_params_c, outer_esp_spi, 2622 ntohl(ib_spec->esp.mask.spi)); 2623 MLX5_SET(fte_match_set_misc, misc_params_v, outer_esp_spi, 2624 ntohl(ib_spec->esp.val.spi)); 2625 break; 2626 case IB_FLOW_SPEC_TCP: 2627 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 2628 LAST_TCP_UDP_FIELD)) 2629 return -EOPNOTSUPP; 2630 2631 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol, 2632 0xff); 2633 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, 2634 IPPROTO_TCP); 2635 2636 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport, 2637 ntohs(ib_spec->tcp_udp.mask.src_port)); 2638 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport, 2639 ntohs(ib_spec->tcp_udp.val.src_port)); 2640 2641 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport, 2642 ntohs(ib_spec->tcp_udp.mask.dst_port)); 2643 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport, 2644 ntohs(ib_spec->tcp_udp.val.dst_port)); 2645 break; 2646 case IB_FLOW_SPEC_UDP: 2647 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 2648 LAST_TCP_UDP_FIELD)) 2649 return -EOPNOTSUPP; 2650 2651 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol, 2652 0xff); 2653 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, 2654 IPPROTO_UDP); 2655 2656 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport, 2657 ntohs(ib_spec->tcp_udp.mask.src_port)); 2658 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport, 2659 ntohs(ib_spec->tcp_udp.val.src_port)); 2660 2661 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport, 2662 ntohs(ib_spec->tcp_udp.mask.dst_port)); 2663 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, 2664 ntohs(ib_spec->tcp_udp.val.dst_port)); 2665 break; 2666 case IB_FLOW_SPEC_GRE: 2667 if (ib_spec->gre.mask.c_ks_res0_ver) 2668 return -EOPNOTSUPP; 2669 2670 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol, 2671 0xff); 2672 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, 2673 IPPROTO_GRE); 2674 2675 MLX5_SET(fte_match_set_misc, misc_params_c, gre_protocol, 2676 0xffff); 2677 MLX5_SET(fte_match_set_misc, misc_params_v, gre_protocol, 2678 ntohs(ib_spec->gre.val.protocol)); 2679 2680 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_c, 2681 gre_key_h), 2682 &ib_spec->gre.mask.key, 2683 sizeof(ib_spec->gre.mask.key)); 2684 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_v, 2685 gre_key_h), 2686 &ib_spec->gre.val.key, 2687 sizeof(ib_spec->gre.val.key)); 2688 break; 2689 case IB_FLOW_SPEC_MPLS: 2690 switch (prev_type) { 2691 case IB_FLOW_SPEC_UDP: 2692 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2693 ft_field_support.outer_first_mpls_over_udp), 2694 &ib_spec->mpls.mask.tag)) 2695 return -EOPNOTSUPP; 2696 2697 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v, 2698 outer_first_mpls_over_udp), 2699 &ib_spec->mpls.val.tag, 2700 sizeof(ib_spec->mpls.val.tag)); 2701 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c, 2702 outer_first_mpls_over_udp), 2703 &ib_spec->mpls.mask.tag, 2704 sizeof(ib_spec->mpls.mask.tag)); 2705 break; 2706 case IB_FLOW_SPEC_GRE: 2707 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2708 ft_field_support.outer_first_mpls_over_gre), 2709 &ib_spec->mpls.mask.tag)) 2710 return -EOPNOTSUPP; 2711 2712 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v, 2713 outer_first_mpls_over_gre), 2714 &ib_spec->mpls.val.tag, 2715 sizeof(ib_spec->mpls.val.tag)); 2716 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c, 2717 outer_first_mpls_over_gre), 2718 &ib_spec->mpls.mask.tag, 2719 sizeof(ib_spec->mpls.mask.tag)); 2720 break; 2721 default: 2722 if (ib_spec->type & IB_FLOW_SPEC_INNER) { 2723 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2724 ft_field_support.inner_first_mpls), 2725 &ib_spec->mpls.mask.tag)) 2726 return -EOPNOTSUPP; 2727 2728 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v, 2729 inner_first_mpls), 2730 &ib_spec->mpls.val.tag, 2731 sizeof(ib_spec->mpls.val.tag)); 2732 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c, 2733 inner_first_mpls), 2734 &ib_spec->mpls.mask.tag, 2735 sizeof(ib_spec->mpls.mask.tag)); 2736 } else { 2737 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2738 ft_field_support.outer_first_mpls), 2739 &ib_spec->mpls.mask.tag)) 2740 return -EOPNOTSUPP; 2741 2742 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v, 2743 outer_first_mpls), 2744 &ib_spec->mpls.val.tag, 2745 sizeof(ib_spec->mpls.val.tag)); 2746 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c, 2747 outer_first_mpls), 2748 &ib_spec->mpls.mask.tag, 2749 sizeof(ib_spec->mpls.mask.tag)); 2750 } 2751 } 2752 break; 2753 case IB_FLOW_SPEC_VXLAN_TUNNEL: 2754 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask, 2755 LAST_TUNNEL_FIELD)) 2756 return -EOPNOTSUPP; 2757 2758 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni, 2759 ntohl(ib_spec->tunnel.mask.tunnel_id)); 2760 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni, 2761 ntohl(ib_spec->tunnel.val.tunnel_id)); 2762 break; 2763 case IB_FLOW_SPEC_ACTION_TAG: 2764 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag, 2765 LAST_FLOW_TAG_FIELD)) 2766 return -EOPNOTSUPP; 2767 if (ib_spec->flow_tag.tag_id >= BIT(24)) 2768 return -EINVAL; 2769 2770 action->flow_tag = ib_spec->flow_tag.tag_id; 2771 action->has_flow_tag = true; 2772 break; 2773 case IB_FLOW_SPEC_ACTION_DROP: 2774 if (FIELDS_NOT_SUPPORTED(ib_spec->drop, 2775 LAST_DROP_FIELD)) 2776 return -EOPNOTSUPP; 2777 action->action |= MLX5_FLOW_CONTEXT_ACTION_DROP; 2778 break; 2779 case IB_FLOW_SPEC_ACTION_HANDLE: 2780 ret = parse_flow_flow_action(ib_spec, flow_attr, action); 2781 if (ret) 2782 return ret; 2783 break; 2784 case IB_FLOW_SPEC_ACTION_COUNT: 2785 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_count, 2786 LAST_COUNTERS_FIELD)) 2787 return -EOPNOTSUPP; 2788 2789 /* for now support only one counters spec per flow */ 2790 if (action->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) 2791 return -EINVAL; 2792 2793 action->counters = ib_spec->flow_count.counters; 2794 action->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT; 2795 break; 2796 default: 2797 return -EINVAL; 2798 } 2799 2800 return 0; 2801 } 2802 2803 /* If a flow could catch both multicast and unicast packets, 2804 * it won't fall into the multicast flow steering table and this rule 2805 * could steal other multicast packets. 2806 */ 2807 static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr) 2808 { 2809 union ib_flow_spec *flow_spec; 2810 2811 if (ib_attr->type != IB_FLOW_ATTR_NORMAL || 2812 ib_attr->num_of_specs < 1) 2813 return false; 2814 2815 flow_spec = (union ib_flow_spec *)(ib_attr + 1); 2816 if (flow_spec->type == IB_FLOW_SPEC_IPV4) { 2817 struct ib_flow_spec_ipv4 *ipv4_spec; 2818 2819 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec; 2820 if (ipv4_is_multicast(ipv4_spec->val.dst_ip)) 2821 return true; 2822 2823 return false; 2824 } 2825 2826 if (flow_spec->type == IB_FLOW_SPEC_ETH) { 2827 struct ib_flow_spec_eth *eth_spec; 2828 2829 eth_spec = (struct ib_flow_spec_eth *)flow_spec; 2830 return is_multicast_ether_addr(eth_spec->mask.dst_mac) && 2831 is_multicast_ether_addr(eth_spec->val.dst_mac); 2832 } 2833 2834 return false; 2835 } 2836 2837 enum valid_spec { 2838 VALID_SPEC_INVALID, 2839 VALID_SPEC_VALID, 2840 VALID_SPEC_NA, 2841 }; 2842 2843 static enum valid_spec 2844 is_valid_esp_aes_gcm(struct mlx5_core_dev *mdev, 2845 const struct mlx5_flow_spec *spec, 2846 const struct mlx5_flow_act *flow_act, 2847 bool egress) 2848 { 2849 const u32 *match_c = spec->match_criteria; 2850 bool is_crypto = 2851 (flow_act->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT | 2852 MLX5_FLOW_CONTEXT_ACTION_DECRYPT)); 2853 bool is_ipsec = mlx5_fs_is_ipsec_flow(match_c); 2854 bool is_drop = flow_act->action & MLX5_FLOW_CONTEXT_ACTION_DROP; 2855 2856 /* 2857 * Currently only crypto is supported in egress, when regular egress 2858 * rules would be supported, always return VALID_SPEC_NA. 2859 */ 2860 if (!is_crypto) 2861 return egress ? VALID_SPEC_INVALID : VALID_SPEC_NA; 2862 2863 return is_crypto && is_ipsec && 2864 (!egress || (!is_drop && !flow_act->has_flow_tag)) ? 2865 VALID_SPEC_VALID : VALID_SPEC_INVALID; 2866 } 2867 2868 static bool is_valid_spec(struct mlx5_core_dev *mdev, 2869 const struct mlx5_flow_spec *spec, 2870 const struct mlx5_flow_act *flow_act, 2871 bool egress) 2872 { 2873 /* We curretly only support ipsec egress flow */ 2874 return is_valid_esp_aes_gcm(mdev, spec, flow_act, egress) != VALID_SPEC_INVALID; 2875 } 2876 2877 static bool is_valid_ethertype(struct mlx5_core_dev *mdev, 2878 const struct ib_flow_attr *flow_attr, 2879 bool check_inner) 2880 { 2881 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1); 2882 int match_ipv = check_inner ? 2883 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2884 ft_field_support.inner_ip_version) : 2885 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2886 ft_field_support.outer_ip_version); 2887 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0; 2888 bool ipv4_spec_valid, ipv6_spec_valid; 2889 unsigned int ip_spec_type = 0; 2890 bool has_ethertype = false; 2891 unsigned int spec_index; 2892 bool mask_valid = true; 2893 u16 eth_type = 0; 2894 bool type_valid; 2895 2896 /* Validate that ethertype is correct */ 2897 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 2898 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) && 2899 ib_spec->eth.mask.ether_type) { 2900 mask_valid = (ib_spec->eth.mask.ether_type == 2901 htons(0xffff)); 2902 has_ethertype = true; 2903 eth_type = ntohs(ib_spec->eth.val.ether_type); 2904 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) || 2905 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) { 2906 ip_spec_type = ib_spec->type; 2907 } 2908 ib_spec = (void *)ib_spec + ib_spec->size; 2909 } 2910 2911 type_valid = (!has_ethertype) || (!ip_spec_type); 2912 if (!type_valid && mask_valid) { 2913 ipv4_spec_valid = (eth_type == ETH_P_IP) && 2914 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit)); 2915 ipv6_spec_valid = (eth_type == ETH_P_IPV6) && 2916 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit)); 2917 2918 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) || 2919 (((eth_type == ETH_P_MPLS_UC) || 2920 (eth_type == ETH_P_MPLS_MC)) && match_ipv); 2921 } 2922 2923 return type_valid; 2924 } 2925 2926 static bool is_valid_attr(struct mlx5_core_dev *mdev, 2927 const struct ib_flow_attr *flow_attr) 2928 { 2929 return is_valid_ethertype(mdev, flow_attr, false) && 2930 is_valid_ethertype(mdev, flow_attr, true); 2931 } 2932 2933 static void put_flow_table(struct mlx5_ib_dev *dev, 2934 struct mlx5_ib_flow_prio *prio, bool ft_added) 2935 { 2936 prio->refcount -= !!ft_added; 2937 if (!prio->refcount) { 2938 mlx5_destroy_flow_table(prio->flow_table); 2939 prio->flow_table = NULL; 2940 } 2941 } 2942 2943 static void counters_clear_description(struct ib_counters *counters) 2944 { 2945 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters); 2946 2947 mutex_lock(&mcounters->mcntrs_mutex); 2948 kfree(mcounters->counters_data); 2949 mcounters->counters_data = NULL; 2950 mcounters->cntrs_max_index = 0; 2951 mutex_unlock(&mcounters->mcntrs_mutex); 2952 } 2953 2954 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id) 2955 { 2956 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device); 2957 struct mlx5_ib_flow_handler *handler = container_of(flow_id, 2958 struct mlx5_ib_flow_handler, 2959 ibflow); 2960 struct mlx5_ib_flow_handler *iter, *tmp; 2961 2962 mutex_lock(&dev->flow_db->lock); 2963 2964 list_for_each_entry_safe(iter, tmp, &handler->list, list) { 2965 mlx5_del_flow_rules(iter->rule); 2966 put_flow_table(dev, iter->prio, true); 2967 list_del(&iter->list); 2968 kfree(iter); 2969 } 2970 2971 mlx5_del_flow_rules(handler->rule); 2972 put_flow_table(dev, handler->prio, true); 2973 if (handler->ibcounters && 2974 atomic_read(&handler->ibcounters->usecnt) == 1) 2975 counters_clear_description(handler->ibcounters); 2976 2977 mutex_unlock(&dev->flow_db->lock); 2978 kfree(handler); 2979 2980 return 0; 2981 } 2982 2983 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap) 2984 { 2985 priority *= 2; 2986 if (!dont_trap) 2987 priority++; 2988 return priority; 2989 } 2990 2991 enum flow_table_type { 2992 MLX5_IB_FT_RX, 2993 MLX5_IB_FT_TX 2994 }; 2995 2996 #define MLX5_FS_MAX_TYPES 6 2997 #define MLX5_FS_MAX_ENTRIES BIT(16) 2998 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev, 2999 struct ib_flow_attr *flow_attr, 3000 enum flow_table_type ft_type) 3001 { 3002 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP; 3003 struct mlx5_flow_namespace *ns = NULL; 3004 struct mlx5_ib_flow_prio *prio; 3005 struct mlx5_flow_table *ft; 3006 int max_table_size; 3007 int num_entries; 3008 int num_groups; 3009 int priority; 3010 int err = 0; 3011 3012 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 3013 log_max_ft_size)); 3014 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 3015 if (ft_type == MLX5_IB_FT_TX) 3016 priority = 0; 3017 else if (flow_is_multicast_only(flow_attr) && 3018 !dont_trap) 3019 priority = MLX5_IB_FLOW_MCAST_PRIO; 3020 else 3021 priority = ib_prio_to_core_prio(flow_attr->priority, 3022 dont_trap); 3023 ns = mlx5_get_flow_namespace(dev->mdev, 3024 ft_type == MLX5_IB_FT_TX ? 3025 MLX5_FLOW_NAMESPACE_EGRESS : 3026 MLX5_FLOW_NAMESPACE_BYPASS); 3027 num_entries = MLX5_FS_MAX_ENTRIES; 3028 num_groups = MLX5_FS_MAX_TYPES; 3029 prio = &dev->flow_db->prios[priority]; 3030 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 3031 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 3032 ns = mlx5_get_flow_namespace(dev->mdev, 3033 MLX5_FLOW_NAMESPACE_LEFTOVERS); 3034 build_leftovers_ft_param(&priority, 3035 &num_entries, 3036 &num_groups); 3037 prio = &dev->flow_db->prios[MLX5_IB_FLOW_LEFTOVERS_PRIO]; 3038 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 3039 if (!MLX5_CAP_FLOWTABLE(dev->mdev, 3040 allow_sniffer_and_nic_rx_shared_tir)) 3041 return ERR_PTR(-ENOTSUPP); 3042 3043 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ? 3044 MLX5_FLOW_NAMESPACE_SNIFFER_RX : 3045 MLX5_FLOW_NAMESPACE_SNIFFER_TX); 3046 3047 prio = &dev->flow_db->sniffer[ft_type]; 3048 priority = 0; 3049 num_entries = 1; 3050 num_groups = 1; 3051 } 3052 3053 if (!ns) 3054 return ERR_PTR(-ENOTSUPP); 3055 3056 if (num_entries > max_table_size) 3057 return ERR_PTR(-ENOMEM); 3058 3059 ft = prio->flow_table; 3060 if (!ft) { 3061 ft = mlx5_create_auto_grouped_flow_table(ns, priority, 3062 num_entries, 3063 num_groups, 3064 0, 0); 3065 3066 if (!IS_ERR(ft)) { 3067 prio->refcount = 0; 3068 prio->flow_table = ft; 3069 } else { 3070 err = PTR_ERR(ft); 3071 } 3072 } 3073 3074 return err ? ERR_PTR(err) : prio; 3075 } 3076 3077 static void set_underlay_qp(struct mlx5_ib_dev *dev, 3078 struct mlx5_flow_spec *spec, 3079 u32 underlay_qpn) 3080 { 3081 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, 3082 spec->match_criteria, 3083 misc_parameters); 3084 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, 3085 misc_parameters); 3086 3087 if (underlay_qpn && 3088 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 3089 ft_field_support.bth_dst_qp)) { 3090 MLX5_SET(fte_match_set_misc, 3091 misc_params_v, bth_dst_qp, underlay_qpn); 3092 MLX5_SET(fte_match_set_misc, 3093 misc_params_c, bth_dst_qp, 0xffffff); 3094 } 3095 } 3096 3097 static int read_flow_counters(struct ib_device *ibdev, 3098 struct mlx5_read_counters_attr *read_attr) 3099 { 3100 struct mlx5_fc *fc = read_attr->hw_cntrs_hndl; 3101 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3102 3103 return mlx5_fc_query(dev->mdev, fc, 3104 &read_attr->out[IB_COUNTER_PACKETS], 3105 &read_attr->out[IB_COUNTER_BYTES]); 3106 } 3107 3108 /* flow counters currently expose two counters packets and bytes */ 3109 #define FLOW_COUNTERS_NUM 2 3110 static int counters_set_description(struct ib_counters *counters, 3111 enum mlx5_ib_counters_type counters_type, 3112 struct mlx5_ib_flow_counters_desc *desc_data, 3113 u32 ncounters) 3114 { 3115 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters); 3116 u32 cntrs_max_index = 0; 3117 int i; 3118 3119 if (counters_type != MLX5_IB_COUNTERS_FLOW) 3120 return -EINVAL; 3121 3122 /* init the fields for the object */ 3123 mcounters->type = counters_type; 3124 mcounters->read_counters = read_flow_counters; 3125 mcounters->counters_num = FLOW_COUNTERS_NUM; 3126 mcounters->ncounters = ncounters; 3127 /* each counter entry have both description and index pair */ 3128 for (i = 0; i < ncounters; i++) { 3129 if (desc_data[i].description > IB_COUNTER_BYTES) 3130 return -EINVAL; 3131 3132 if (cntrs_max_index <= desc_data[i].index) 3133 cntrs_max_index = desc_data[i].index + 1; 3134 } 3135 3136 mutex_lock(&mcounters->mcntrs_mutex); 3137 mcounters->counters_data = desc_data; 3138 mcounters->cntrs_max_index = cntrs_max_index; 3139 mutex_unlock(&mcounters->mcntrs_mutex); 3140 3141 return 0; 3142 } 3143 3144 #define MAX_COUNTERS_NUM (USHRT_MAX / (sizeof(u32) * 2)) 3145 static int flow_counters_set_data(struct ib_counters *ibcounters, 3146 struct mlx5_ib_create_flow *ucmd) 3147 { 3148 struct mlx5_ib_mcounters *mcounters = to_mcounters(ibcounters); 3149 struct mlx5_ib_flow_counters_data *cntrs_data = NULL; 3150 struct mlx5_ib_flow_counters_desc *desc_data = NULL; 3151 bool hw_hndl = false; 3152 int ret = 0; 3153 3154 if (ucmd && ucmd->ncounters_data != 0) { 3155 cntrs_data = ucmd->data; 3156 if (cntrs_data->ncounters > MAX_COUNTERS_NUM) 3157 return -EINVAL; 3158 3159 desc_data = kcalloc(cntrs_data->ncounters, 3160 sizeof(*desc_data), 3161 GFP_KERNEL); 3162 if (!desc_data) 3163 return -ENOMEM; 3164 3165 if (copy_from_user(desc_data, 3166 u64_to_user_ptr(cntrs_data->counters_data), 3167 sizeof(*desc_data) * cntrs_data->ncounters)) { 3168 ret = -EFAULT; 3169 goto free; 3170 } 3171 } 3172 3173 if (!mcounters->hw_cntrs_hndl) { 3174 mcounters->hw_cntrs_hndl = mlx5_fc_create( 3175 to_mdev(ibcounters->device)->mdev, false); 3176 if (!mcounters->hw_cntrs_hndl) { 3177 ret = -ENOMEM; 3178 goto free; 3179 } 3180 hw_hndl = true; 3181 } 3182 3183 if (desc_data) { 3184 /* counters already bound to at least one flow */ 3185 if (mcounters->cntrs_max_index) { 3186 ret = -EINVAL; 3187 goto free_hndl; 3188 } 3189 3190 ret = counters_set_description(ibcounters, 3191 MLX5_IB_COUNTERS_FLOW, 3192 desc_data, 3193 cntrs_data->ncounters); 3194 if (ret) 3195 goto free_hndl; 3196 3197 } else if (!mcounters->cntrs_max_index) { 3198 /* counters not bound yet, must have udata passed */ 3199 ret = -EINVAL; 3200 goto free_hndl; 3201 } 3202 3203 return 0; 3204 3205 free_hndl: 3206 if (hw_hndl) { 3207 mlx5_fc_destroy(to_mdev(ibcounters->device)->mdev, 3208 mcounters->hw_cntrs_hndl); 3209 mcounters->hw_cntrs_hndl = NULL; 3210 } 3211 free: 3212 kfree(desc_data); 3213 return ret; 3214 } 3215 3216 static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev, 3217 struct mlx5_ib_flow_prio *ft_prio, 3218 const struct ib_flow_attr *flow_attr, 3219 struct mlx5_flow_destination *dst, 3220 u32 underlay_qpn, 3221 struct mlx5_ib_create_flow *ucmd) 3222 { 3223 struct mlx5_flow_table *ft = ft_prio->flow_table; 3224 struct mlx5_ib_flow_handler *handler; 3225 struct mlx5_flow_act flow_act = {.flow_tag = MLX5_FS_DEFAULT_FLOW_TAG}; 3226 struct mlx5_flow_spec *spec; 3227 struct mlx5_flow_destination dest_arr[2] = {}; 3228 struct mlx5_flow_destination *rule_dst = dest_arr; 3229 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr); 3230 unsigned int spec_index; 3231 u32 prev_type = 0; 3232 int err = 0; 3233 int dest_num = 0; 3234 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS; 3235 3236 if (!is_valid_attr(dev->mdev, flow_attr)) 3237 return ERR_PTR(-EINVAL); 3238 3239 spec = kvzalloc(sizeof(*spec), GFP_KERNEL); 3240 handler = kzalloc(sizeof(*handler), GFP_KERNEL); 3241 if (!handler || !spec) { 3242 err = -ENOMEM; 3243 goto free; 3244 } 3245 3246 INIT_LIST_HEAD(&handler->list); 3247 if (dst) { 3248 memcpy(&dest_arr[0], dst, sizeof(*dst)); 3249 dest_num++; 3250 } 3251 3252 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 3253 err = parse_flow_attr(dev->mdev, spec->match_criteria, 3254 spec->match_value, 3255 ib_flow, flow_attr, &flow_act, 3256 prev_type); 3257 if (err < 0) 3258 goto free; 3259 3260 prev_type = ((union ib_flow_spec *)ib_flow)->type; 3261 ib_flow += ((union ib_flow_spec *)ib_flow)->size; 3262 } 3263 3264 if (!flow_is_multicast_only(flow_attr)) 3265 set_underlay_qp(dev, spec, underlay_qpn); 3266 3267 if (dev->rep) { 3268 void *misc; 3269 3270 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, 3271 misc_parameters); 3272 MLX5_SET(fte_match_set_misc, misc, source_port, 3273 dev->rep->vport); 3274 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, 3275 misc_parameters); 3276 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port); 3277 } 3278 3279 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria); 3280 3281 if (is_egress && 3282 !is_valid_spec(dev->mdev, spec, &flow_act, is_egress)) { 3283 err = -EINVAL; 3284 goto free; 3285 } 3286 3287 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) { 3288 err = flow_counters_set_data(flow_act.counters, ucmd); 3289 if (err) 3290 goto free; 3291 3292 handler->ibcounters = flow_act.counters; 3293 dest_arr[dest_num].type = 3294 MLX5_FLOW_DESTINATION_TYPE_COUNTER; 3295 dest_arr[dest_num].counter = 3296 to_mcounters(flow_act.counters)->hw_cntrs_hndl; 3297 dest_num++; 3298 } 3299 3300 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP) { 3301 if (!(flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT)) { 3302 rule_dst = NULL; 3303 dest_num = 0; 3304 } 3305 } else { 3306 if (is_egress) 3307 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW; 3308 else 3309 flow_act.action |= 3310 dest_num ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST : 3311 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO; 3312 } 3313 3314 if (flow_act.has_flow_tag && 3315 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 3316 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) { 3317 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n", 3318 flow_act.flow_tag, flow_attr->type); 3319 err = -EINVAL; 3320 goto free; 3321 } 3322 handler->rule = mlx5_add_flow_rules(ft, spec, 3323 &flow_act, 3324 rule_dst, dest_num); 3325 3326 if (IS_ERR(handler->rule)) { 3327 err = PTR_ERR(handler->rule); 3328 goto free; 3329 } 3330 3331 ft_prio->refcount++; 3332 handler->prio = ft_prio; 3333 3334 ft_prio->flow_table = ft; 3335 free: 3336 if (err && handler) { 3337 if (handler->ibcounters && 3338 atomic_read(&handler->ibcounters->usecnt) == 1) 3339 counters_clear_description(handler->ibcounters); 3340 kfree(handler); 3341 } 3342 kvfree(spec); 3343 return err ? ERR_PTR(err) : handler; 3344 } 3345 3346 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev, 3347 struct mlx5_ib_flow_prio *ft_prio, 3348 const struct ib_flow_attr *flow_attr, 3349 struct mlx5_flow_destination *dst) 3350 { 3351 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0, NULL); 3352 } 3353 3354 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev, 3355 struct mlx5_ib_flow_prio *ft_prio, 3356 struct ib_flow_attr *flow_attr, 3357 struct mlx5_flow_destination *dst) 3358 { 3359 struct mlx5_ib_flow_handler *handler_dst = NULL; 3360 struct mlx5_ib_flow_handler *handler = NULL; 3361 3362 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL); 3363 if (!IS_ERR(handler)) { 3364 handler_dst = create_flow_rule(dev, ft_prio, 3365 flow_attr, dst); 3366 if (IS_ERR(handler_dst)) { 3367 mlx5_del_flow_rules(handler->rule); 3368 ft_prio->refcount--; 3369 kfree(handler); 3370 handler = handler_dst; 3371 } else { 3372 list_add(&handler_dst->list, &handler->list); 3373 } 3374 } 3375 3376 return handler; 3377 } 3378 enum { 3379 LEFTOVERS_MC, 3380 LEFTOVERS_UC, 3381 }; 3382 3383 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev, 3384 struct mlx5_ib_flow_prio *ft_prio, 3385 struct ib_flow_attr *flow_attr, 3386 struct mlx5_flow_destination *dst) 3387 { 3388 struct mlx5_ib_flow_handler *handler_ucast = NULL; 3389 struct mlx5_ib_flow_handler *handler = NULL; 3390 3391 static struct { 3392 struct ib_flow_attr flow_attr; 3393 struct ib_flow_spec_eth eth_flow; 3394 } leftovers_specs[] = { 3395 [LEFTOVERS_MC] = { 3396 .flow_attr = { 3397 .num_of_specs = 1, 3398 .size = sizeof(leftovers_specs[0]) 3399 }, 3400 .eth_flow = { 3401 .type = IB_FLOW_SPEC_ETH, 3402 .size = sizeof(struct ib_flow_spec_eth), 3403 .mask = {.dst_mac = {0x1} }, 3404 .val = {.dst_mac = {0x1} } 3405 } 3406 }, 3407 [LEFTOVERS_UC] = { 3408 .flow_attr = { 3409 .num_of_specs = 1, 3410 .size = sizeof(leftovers_specs[0]) 3411 }, 3412 .eth_flow = { 3413 .type = IB_FLOW_SPEC_ETH, 3414 .size = sizeof(struct ib_flow_spec_eth), 3415 .mask = {.dst_mac = {0x1} }, 3416 .val = {.dst_mac = {} } 3417 } 3418 } 3419 }; 3420 3421 handler = create_flow_rule(dev, ft_prio, 3422 &leftovers_specs[LEFTOVERS_MC].flow_attr, 3423 dst); 3424 if (!IS_ERR(handler) && 3425 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) { 3426 handler_ucast = create_flow_rule(dev, ft_prio, 3427 &leftovers_specs[LEFTOVERS_UC].flow_attr, 3428 dst); 3429 if (IS_ERR(handler_ucast)) { 3430 mlx5_del_flow_rules(handler->rule); 3431 ft_prio->refcount--; 3432 kfree(handler); 3433 handler = handler_ucast; 3434 } else { 3435 list_add(&handler_ucast->list, &handler->list); 3436 } 3437 } 3438 3439 return handler; 3440 } 3441 3442 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev, 3443 struct mlx5_ib_flow_prio *ft_rx, 3444 struct mlx5_ib_flow_prio *ft_tx, 3445 struct mlx5_flow_destination *dst) 3446 { 3447 struct mlx5_ib_flow_handler *handler_rx; 3448 struct mlx5_ib_flow_handler *handler_tx; 3449 int err; 3450 static const struct ib_flow_attr flow_attr = { 3451 .num_of_specs = 0, 3452 .size = sizeof(flow_attr) 3453 }; 3454 3455 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst); 3456 if (IS_ERR(handler_rx)) { 3457 err = PTR_ERR(handler_rx); 3458 goto err; 3459 } 3460 3461 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst); 3462 if (IS_ERR(handler_tx)) { 3463 err = PTR_ERR(handler_tx); 3464 goto err_tx; 3465 } 3466 3467 list_add(&handler_tx->list, &handler_rx->list); 3468 3469 return handler_rx; 3470 3471 err_tx: 3472 mlx5_del_flow_rules(handler_rx->rule); 3473 ft_rx->refcount--; 3474 kfree(handler_rx); 3475 err: 3476 return ERR_PTR(err); 3477 } 3478 3479 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp, 3480 struct ib_flow_attr *flow_attr, 3481 int domain, 3482 struct ib_udata *udata) 3483 { 3484 struct mlx5_ib_dev *dev = to_mdev(qp->device); 3485 struct mlx5_ib_qp *mqp = to_mqp(qp); 3486 struct mlx5_ib_flow_handler *handler = NULL; 3487 struct mlx5_flow_destination *dst = NULL; 3488 struct mlx5_ib_flow_prio *ft_prio_tx = NULL; 3489 struct mlx5_ib_flow_prio *ft_prio; 3490 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS; 3491 struct mlx5_ib_create_flow *ucmd = NULL, ucmd_hdr; 3492 size_t min_ucmd_sz, required_ucmd_sz; 3493 int err; 3494 int underlay_qpn; 3495 3496 if (udata && udata->inlen) { 3497 min_ucmd_sz = offsetof(typeof(ucmd_hdr), reserved) + 3498 sizeof(ucmd_hdr.reserved); 3499 if (udata->inlen < min_ucmd_sz) 3500 return ERR_PTR(-EOPNOTSUPP); 3501 3502 err = ib_copy_from_udata(&ucmd_hdr, udata, min_ucmd_sz); 3503 if (err) 3504 return ERR_PTR(err); 3505 3506 /* currently supports only one counters data */ 3507 if (ucmd_hdr.ncounters_data > 1) 3508 return ERR_PTR(-EINVAL); 3509 3510 required_ucmd_sz = min_ucmd_sz + 3511 sizeof(struct mlx5_ib_flow_counters_data) * 3512 ucmd_hdr.ncounters_data; 3513 if (udata->inlen > required_ucmd_sz && 3514 !ib_is_udata_cleared(udata, required_ucmd_sz, 3515 udata->inlen - required_ucmd_sz)) 3516 return ERR_PTR(-EOPNOTSUPP); 3517 3518 ucmd = kzalloc(required_ucmd_sz, GFP_KERNEL); 3519 if (!ucmd) 3520 return ERR_PTR(-ENOMEM); 3521 3522 err = ib_copy_from_udata(ucmd, udata, required_ucmd_sz); 3523 if (err) { 3524 kfree(ucmd); 3525 return ERR_PTR(err); 3526 } 3527 } 3528 3529 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) 3530 return ERR_PTR(-ENOMEM); 3531 3532 if (domain != IB_FLOW_DOMAIN_USER || 3533 flow_attr->port > dev->num_ports || 3534 (flow_attr->flags & ~(IB_FLOW_ATTR_FLAGS_DONT_TRAP | 3535 IB_FLOW_ATTR_FLAGS_EGRESS))) 3536 return ERR_PTR(-EINVAL); 3537 3538 if (is_egress && 3539 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 3540 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) 3541 return ERR_PTR(-EINVAL); 3542 3543 dst = kzalloc(sizeof(*dst), GFP_KERNEL); 3544 if (!dst) 3545 return ERR_PTR(-ENOMEM); 3546 3547 mutex_lock(&dev->flow_db->lock); 3548 3549 ft_prio = get_flow_table(dev, flow_attr, 3550 is_egress ? MLX5_IB_FT_TX : MLX5_IB_FT_RX); 3551 if (IS_ERR(ft_prio)) { 3552 err = PTR_ERR(ft_prio); 3553 goto unlock; 3554 } 3555 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 3556 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX); 3557 if (IS_ERR(ft_prio_tx)) { 3558 err = PTR_ERR(ft_prio_tx); 3559 ft_prio_tx = NULL; 3560 goto destroy_ft; 3561 } 3562 } 3563 3564 if (is_egress) { 3565 dst->type = MLX5_FLOW_DESTINATION_TYPE_PORT; 3566 } else { 3567 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR; 3568 if (mqp->flags & MLX5_IB_QP_RSS) 3569 dst->tir_num = mqp->rss_qp.tirn; 3570 else 3571 dst->tir_num = mqp->raw_packet_qp.rq.tirn; 3572 } 3573 3574 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 3575 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) { 3576 handler = create_dont_trap_rule(dev, ft_prio, 3577 flow_attr, dst); 3578 } else { 3579 underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ? 3580 mqp->underlay_qpn : 0; 3581 handler = _create_flow_rule(dev, ft_prio, flow_attr, 3582 dst, underlay_qpn, ucmd); 3583 } 3584 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 3585 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 3586 handler = create_leftovers_rule(dev, ft_prio, flow_attr, 3587 dst); 3588 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 3589 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst); 3590 } else { 3591 err = -EINVAL; 3592 goto destroy_ft; 3593 } 3594 3595 if (IS_ERR(handler)) { 3596 err = PTR_ERR(handler); 3597 handler = NULL; 3598 goto destroy_ft; 3599 } 3600 3601 mutex_unlock(&dev->flow_db->lock); 3602 kfree(dst); 3603 kfree(ucmd); 3604 3605 return &handler->ibflow; 3606 3607 destroy_ft: 3608 put_flow_table(dev, ft_prio, false); 3609 if (ft_prio_tx) 3610 put_flow_table(dev, ft_prio_tx, false); 3611 unlock: 3612 mutex_unlock(&dev->flow_db->lock); 3613 kfree(dst); 3614 kfree(ucmd); 3615 kfree(handler); 3616 return ERR_PTR(err); 3617 } 3618 3619 static u32 mlx5_ib_flow_action_flags_to_accel_xfrm_flags(u32 mlx5_flags) 3620 { 3621 u32 flags = 0; 3622 3623 if (mlx5_flags & MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA) 3624 flags |= MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA; 3625 3626 return flags; 3627 } 3628 3629 #define MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA 3630 static struct ib_flow_action * 3631 mlx5_ib_create_flow_action_esp(struct ib_device *device, 3632 const struct ib_flow_action_attrs_esp *attr, 3633 struct uverbs_attr_bundle *attrs) 3634 { 3635 struct mlx5_ib_dev *mdev = to_mdev(device); 3636 struct ib_uverbs_flow_action_esp_keymat_aes_gcm *aes_gcm; 3637 struct mlx5_accel_esp_xfrm_attrs accel_attrs = {}; 3638 struct mlx5_ib_flow_action *action; 3639 u64 action_flags; 3640 u64 flags; 3641 int err = 0; 3642 3643 if (IS_UVERBS_COPY_ERR(uverbs_copy_from(&action_flags, attrs, 3644 MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS))) 3645 return ERR_PTR(-EFAULT); 3646 3647 if (action_flags >= (MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED << 1)) 3648 return ERR_PTR(-EOPNOTSUPP); 3649 3650 flags = mlx5_ib_flow_action_flags_to_accel_xfrm_flags(action_flags); 3651 3652 /* We current only support a subset of the standard features. Only a 3653 * keymat of type AES_GCM, with icv_len == 16, iv_algo == SEQ and esn 3654 * (with overlap). Full offload mode isn't supported. 3655 */ 3656 if (!attr->keymat || attr->replay || attr->encap || 3657 attr->spi || attr->seq || attr->tfc_pad || 3658 attr->hard_limit_pkts || 3659 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED | 3660 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT))) 3661 return ERR_PTR(-EOPNOTSUPP); 3662 3663 if (attr->keymat->protocol != 3664 IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM) 3665 return ERR_PTR(-EOPNOTSUPP); 3666 3667 aes_gcm = &attr->keymat->keymat.aes_gcm; 3668 3669 if (aes_gcm->icv_len != 16 || 3670 aes_gcm->iv_algo != IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ) 3671 return ERR_PTR(-EOPNOTSUPP); 3672 3673 action = kmalloc(sizeof(*action), GFP_KERNEL); 3674 if (!action) 3675 return ERR_PTR(-ENOMEM); 3676 3677 action->esp_aes_gcm.ib_flags = attr->flags; 3678 memcpy(&accel_attrs.keymat.aes_gcm.aes_key, &aes_gcm->aes_key, 3679 sizeof(accel_attrs.keymat.aes_gcm.aes_key)); 3680 accel_attrs.keymat.aes_gcm.key_len = aes_gcm->key_len * 8; 3681 memcpy(&accel_attrs.keymat.aes_gcm.salt, &aes_gcm->salt, 3682 sizeof(accel_attrs.keymat.aes_gcm.salt)); 3683 memcpy(&accel_attrs.keymat.aes_gcm.seq_iv, &aes_gcm->iv, 3684 sizeof(accel_attrs.keymat.aes_gcm.seq_iv)); 3685 accel_attrs.keymat.aes_gcm.icv_len = aes_gcm->icv_len * 8; 3686 accel_attrs.keymat.aes_gcm.iv_algo = MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ; 3687 accel_attrs.keymat_type = MLX5_ACCEL_ESP_KEYMAT_AES_GCM; 3688 3689 accel_attrs.esn = attr->esn; 3690 if (attr->flags & IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) 3691 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED; 3692 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW) 3693 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP; 3694 3695 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT) 3696 accel_attrs.action |= MLX5_ACCEL_ESP_ACTION_ENCRYPT; 3697 3698 action->esp_aes_gcm.ctx = 3699 mlx5_accel_esp_create_xfrm(mdev->mdev, &accel_attrs, flags); 3700 if (IS_ERR(action->esp_aes_gcm.ctx)) { 3701 err = PTR_ERR(action->esp_aes_gcm.ctx); 3702 goto err_parse; 3703 } 3704 3705 action->esp_aes_gcm.ib_flags = attr->flags; 3706 3707 return &action->ib_action; 3708 3709 err_parse: 3710 kfree(action); 3711 return ERR_PTR(err); 3712 } 3713 3714 static int 3715 mlx5_ib_modify_flow_action_esp(struct ib_flow_action *action, 3716 const struct ib_flow_action_attrs_esp *attr, 3717 struct uverbs_attr_bundle *attrs) 3718 { 3719 struct mlx5_ib_flow_action *maction = to_mflow_act(action); 3720 struct mlx5_accel_esp_xfrm_attrs accel_attrs; 3721 int err = 0; 3722 3723 if (attr->keymat || attr->replay || attr->encap || 3724 attr->spi || attr->seq || attr->tfc_pad || 3725 attr->hard_limit_pkts || 3726 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED | 3727 IB_FLOW_ACTION_ESP_FLAGS_MOD_ESP_ATTRS | 3728 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW))) 3729 return -EOPNOTSUPP; 3730 3731 /* Only the ESN value or the MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP can 3732 * be modified. 3733 */ 3734 if (!(maction->esp_aes_gcm.ib_flags & 3735 IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) && 3736 attr->flags & (IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED | 3737 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)) 3738 return -EINVAL; 3739 3740 memcpy(&accel_attrs, &maction->esp_aes_gcm.ctx->attrs, 3741 sizeof(accel_attrs)); 3742 3743 accel_attrs.esn = attr->esn; 3744 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW) 3745 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP; 3746 else 3747 accel_attrs.flags &= ~MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP; 3748 3749 err = mlx5_accel_esp_modify_xfrm(maction->esp_aes_gcm.ctx, 3750 &accel_attrs); 3751 if (err) 3752 return err; 3753 3754 maction->esp_aes_gcm.ib_flags &= 3755 ~IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW; 3756 maction->esp_aes_gcm.ib_flags |= 3757 attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW; 3758 3759 return 0; 3760 } 3761 3762 static int mlx5_ib_destroy_flow_action(struct ib_flow_action *action) 3763 { 3764 struct mlx5_ib_flow_action *maction = to_mflow_act(action); 3765 3766 switch (action->type) { 3767 case IB_FLOW_ACTION_ESP: 3768 /* 3769 * We only support aes_gcm by now, so we implicitly know this is 3770 * the underline crypto. 3771 */ 3772 mlx5_accel_esp_destroy_xfrm(maction->esp_aes_gcm.ctx); 3773 break; 3774 default: 3775 WARN_ON(true); 3776 break; 3777 } 3778 3779 kfree(maction); 3780 return 0; 3781 } 3782 3783 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 3784 { 3785 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3786 struct mlx5_ib_qp *mqp = to_mqp(ibqp); 3787 int err; 3788 3789 if (mqp->flags & MLX5_IB_QP_UNDERLAY) { 3790 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n"); 3791 return -EOPNOTSUPP; 3792 } 3793 3794 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num); 3795 if (err) 3796 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 3797 ibqp->qp_num, gid->raw); 3798 3799 return err; 3800 } 3801 3802 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 3803 { 3804 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3805 int err; 3806 3807 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num); 3808 if (err) 3809 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 3810 ibqp->qp_num, gid->raw); 3811 3812 return err; 3813 } 3814 3815 static int init_node_data(struct mlx5_ib_dev *dev) 3816 { 3817 int err; 3818 3819 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 3820 if (err) 3821 return err; 3822 3823 dev->mdev->rev_id = dev->mdev->pdev->revision; 3824 3825 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 3826 } 3827 3828 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr, 3829 char *buf) 3830 { 3831 struct mlx5_ib_dev *dev = 3832 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 3833 3834 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages); 3835 } 3836 3837 static ssize_t show_reg_pages(struct device *device, 3838 struct device_attribute *attr, char *buf) 3839 { 3840 struct mlx5_ib_dev *dev = 3841 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 3842 3843 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 3844 } 3845 3846 static ssize_t show_hca(struct device *device, struct device_attribute *attr, 3847 char *buf) 3848 { 3849 struct mlx5_ib_dev *dev = 3850 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 3851 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device); 3852 } 3853 3854 static ssize_t show_rev(struct device *device, struct device_attribute *attr, 3855 char *buf) 3856 { 3857 struct mlx5_ib_dev *dev = 3858 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 3859 return sprintf(buf, "%x\n", dev->mdev->rev_id); 3860 } 3861 3862 static ssize_t show_board(struct device *device, struct device_attribute *attr, 3863 char *buf) 3864 { 3865 struct mlx5_ib_dev *dev = 3866 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 3867 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 3868 dev->mdev->board_id); 3869 } 3870 3871 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL); 3872 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL); 3873 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL); 3874 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL); 3875 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL); 3876 3877 static struct device_attribute *mlx5_class_attributes[] = { 3878 &dev_attr_hw_rev, 3879 &dev_attr_hca_type, 3880 &dev_attr_board_id, 3881 &dev_attr_fw_pages, 3882 &dev_attr_reg_pages, 3883 }; 3884 3885 static void pkey_change_handler(struct work_struct *work) 3886 { 3887 struct mlx5_ib_port_resources *ports = 3888 container_of(work, struct mlx5_ib_port_resources, 3889 pkey_change_work); 3890 3891 mutex_lock(&ports->devr->mutex); 3892 mlx5_ib_gsi_pkey_change(ports->gsi); 3893 mutex_unlock(&ports->devr->mutex); 3894 } 3895 3896 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 3897 { 3898 struct mlx5_ib_qp *mqp; 3899 struct mlx5_ib_cq *send_mcq, *recv_mcq; 3900 struct mlx5_core_cq *mcq; 3901 struct list_head cq_armed_list; 3902 unsigned long flags_qp; 3903 unsigned long flags_cq; 3904 unsigned long flags; 3905 3906 INIT_LIST_HEAD(&cq_armed_list); 3907 3908 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 3909 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 3910 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 3911 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 3912 if (mqp->sq.tail != mqp->sq.head) { 3913 send_mcq = to_mcq(mqp->ibqp.send_cq); 3914 spin_lock_irqsave(&send_mcq->lock, flags_cq); 3915 if (send_mcq->mcq.comp && 3916 mqp->ibqp.send_cq->comp_handler) { 3917 if (!send_mcq->mcq.reset_notify_added) { 3918 send_mcq->mcq.reset_notify_added = 1; 3919 list_add_tail(&send_mcq->mcq.reset_notify, 3920 &cq_armed_list); 3921 } 3922 } 3923 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 3924 } 3925 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 3926 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 3927 /* no handling is needed for SRQ */ 3928 if (!mqp->ibqp.srq) { 3929 if (mqp->rq.tail != mqp->rq.head) { 3930 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 3931 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 3932 if (recv_mcq->mcq.comp && 3933 mqp->ibqp.recv_cq->comp_handler) { 3934 if (!recv_mcq->mcq.reset_notify_added) { 3935 recv_mcq->mcq.reset_notify_added = 1; 3936 list_add_tail(&recv_mcq->mcq.reset_notify, 3937 &cq_armed_list); 3938 } 3939 } 3940 spin_unlock_irqrestore(&recv_mcq->lock, 3941 flags_cq); 3942 } 3943 } 3944 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 3945 } 3946 /*At that point all inflight post send were put to be executed as of we 3947 * lock/unlock above locks Now need to arm all involved CQs. 3948 */ 3949 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 3950 mcq->comp(mcq); 3951 } 3952 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 3953 } 3954 3955 static void delay_drop_handler(struct work_struct *work) 3956 { 3957 int err; 3958 struct mlx5_ib_delay_drop *delay_drop = 3959 container_of(work, struct mlx5_ib_delay_drop, 3960 delay_drop_work); 3961 3962 atomic_inc(&delay_drop->events_cnt); 3963 3964 mutex_lock(&delay_drop->lock); 3965 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev, 3966 delay_drop->timeout); 3967 if (err) { 3968 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n", 3969 delay_drop->timeout); 3970 delay_drop->activate = false; 3971 } 3972 mutex_unlock(&delay_drop->lock); 3973 } 3974 3975 static void mlx5_ib_handle_event(struct work_struct *_work) 3976 { 3977 struct mlx5_ib_event_work *work = 3978 container_of(_work, struct mlx5_ib_event_work, work); 3979 struct mlx5_ib_dev *ibdev; 3980 struct ib_event ibev; 3981 bool fatal = false; 3982 u8 port = (u8)work->param; 3983 3984 if (mlx5_core_is_mp_slave(work->dev)) { 3985 ibdev = mlx5_ib_get_ibdev_from_mpi(work->context); 3986 if (!ibdev) 3987 goto out; 3988 } else { 3989 ibdev = work->context; 3990 } 3991 3992 switch (work->event) { 3993 case MLX5_DEV_EVENT_SYS_ERROR: 3994 ibev.event = IB_EVENT_DEVICE_FATAL; 3995 mlx5_ib_handle_internal_error(ibdev); 3996 fatal = true; 3997 break; 3998 3999 case MLX5_DEV_EVENT_PORT_UP: 4000 case MLX5_DEV_EVENT_PORT_DOWN: 4001 case MLX5_DEV_EVENT_PORT_INITIALIZED: 4002 /* In RoCE, port up/down events are handled in 4003 * mlx5_netdev_event(). 4004 */ 4005 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 4006 IB_LINK_LAYER_ETHERNET) 4007 goto out; 4008 4009 ibev.event = (work->event == MLX5_DEV_EVENT_PORT_UP) ? 4010 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 4011 break; 4012 4013 case MLX5_DEV_EVENT_LID_CHANGE: 4014 ibev.event = IB_EVENT_LID_CHANGE; 4015 break; 4016 4017 case MLX5_DEV_EVENT_PKEY_CHANGE: 4018 ibev.event = IB_EVENT_PKEY_CHANGE; 4019 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 4020 break; 4021 4022 case MLX5_DEV_EVENT_GUID_CHANGE: 4023 ibev.event = IB_EVENT_GID_CHANGE; 4024 break; 4025 4026 case MLX5_DEV_EVENT_CLIENT_REREG: 4027 ibev.event = IB_EVENT_CLIENT_REREGISTER; 4028 break; 4029 case MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT: 4030 schedule_work(&ibdev->delay_drop.delay_drop_work); 4031 goto out; 4032 default: 4033 goto out; 4034 } 4035 4036 ibev.device = &ibdev->ib_dev; 4037 ibev.element.port_num = port; 4038 4039 if (!rdma_is_port_valid(&ibdev->ib_dev, port)) { 4040 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port); 4041 goto out; 4042 } 4043 4044 if (ibdev->ib_active) 4045 ib_dispatch_event(&ibev); 4046 4047 if (fatal) 4048 ibdev->ib_active = false; 4049 out: 4050 kfree(work); 4051 } 4052 4053 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context, 4054 enum mlx5_dev_event event, unsigned long param) 4055 { 4056 struct mlx5_ib_event_work *work; 4057 4058 work = kmalloc(sizeof(*work), GFP_ATOMIC); 4059 if (!work) 4060 return; 4061 4062 INIT_WORK(&work->work, mlx5_ib_handle_event); 4063 work->dev = dev; 4064 work->param = param; 4065 work->context = context; 4066 work->event = event; 4067 4068 queue_work(mlx5_ib_event_wq, &work->work); 4069 } 4070 4071 static int set_has_smi_cap(struct mlx5_ib_dev *dev) 4072 { 4073 struct mlx5_hca_vport_context vport_ctx; 4074 int err; 4075 int port; 4076 4077 for (port = 1; port <= dev->num_ports; port++) { 4078 dev->mdev->port_caps[port - 1].has_smi = false; 4079 if (MLX5_CAP_GEN(dev->mdev, port_type) == 4080 MLX5_CAP_PORT_TYPE_IB) { 4081 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) { 4082 err = mlx5_query_hca_vport_context(dev->mdev, 0, 4083 port, 0, 4084 &vport_ctx); 4085 if (err) { 4086 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n", 4087 port, err); 4088 return err; 4089 } 4090 dev->mdev->port_caps[port - 1].has_smi = 4091 vport_ctx.has_smi; 4092 } else { 4093 dev->mdev->port_caps[port - 1].has_smi = true; 4094 } 4095 } 4096 } 4097 return 0; 4098 } 4099 4100 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 4101 { 4102 int port; 4103 4104 for (port = 1; port <= dev->num_ports; port++) 4105 mlx5_query_ext_port_caps(dev, port); 4106 } 4107 4108 static int get_port_caps(struct mlx5_ib_dev *dev, u8 port) 4109 { 4110 struct ib_device_attr *dprops = NULL; 4111 struct ib_port_attr *pprops = NULL; 4112 int err = -ENOMEM; 4113 struct ib_udata uhw = {.inlen = 0, .outlen = 0}; 4114 4115 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL); 4116 if (!pprops) 4117 goto out; 4118 4119 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL); 4120 if (!dprops) 4121 goto out; 4122 4123 err = set_has_smi_cap(dev); 4124 if (err) 4125 goto out; 4126 4127 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw); 4128 if (err) { 4129 mlx5_ib_warn(dev, "query_device failed %d\n", err); 4130 goto out; 4131 } 4132 4133 memset(pprops, 0, sizeof(*pprops)); 4134 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops); 4135 if (err) { 4136 mlx5_ib_warn(dev, "query_port %d failed %d\n", 4137 port, err); 4138 goto out; 4139 } 4140 4141 dev->mdev->port_caps[port - 1].pkey_table_len = 4142 dprops->max_pkeys; 4143 dev->mdev->port_caps[port - 1].gid_table_len = 4144 pprops->gid_tbl_len; 4145 mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n", 4146 port, dprops->max_pkeys, pprops->gid_tbl_len); 4147 4148 out: 4149 kfree(pprops); 4150 kfree(dprops); 4151 4152 return err; 4153 } 4154 4155 static void destroy_umrc_res(struct mlx5_ib_dev *dev) 4156 { 4157 int err; 4158 4159 err = mlx5_mr_cache_cleanup(dev); 4160 if (err) 4161 mlx5_ib_warn(dev, "mr cache cleanup failed\n"); 4162 4163 if (dev->umrc.qp) 4164 mlx5_ib_destroy_qp(dev->umrc.qp); 4165 if (dev->umrc.cq) 4166 ib_free_cq(dev->umrc.cq); 4167 if (dev->umrc.pd) 4168 ib_dealloc_pd(dev->umrc.pd); 4169 } 4170 4171 enum { 4172 MAX_UMR_WR = 128, 4173 }; 4174 4175 static int create_umr_res(struct mlx5_ib_dev *dev) 4176 { 4177 struct ib_qp_init_attr *init_attr = NULL; 4178 struct ib_qp_attr *attr = NULL; 4179 struct ib_pd *pd; 4180 struct ib_cq *cq; 4181 struct ib_qp *qp; 4182 int ret; 4183 4184 attr = kzalloc(sizeof(*attr), GFP_KERNEL); 4185 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL); 4186 if (!attr || !init_attr) { 4187 ret = -ENOMEM; 4188 goto error_0; 4189 } 4190 4191 pd = ib_alloc_pd(&dev->ib_dev, 0); 4192 if (IS_ERR(pd)) { 4193 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n"); 4194 ret = PTR_ERR(pd); 4195 goto error_0; 4196 } 4197 4198 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ); 4199 if (IS_ERR(cq)) { 4200 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n"); 4201 ret = PTR_ERR(cq); 4202 goto error_2; 4203 } 4204 4205 init_attr->send_cq = cq; 4206 init_attr->recv_cq = cq; 4207 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR; 4208 init_attr->cap.max_send_wr = MAX_UMR_WR; 4209 init_attr->cap.max_send_sge = 1; 4210 init_attr->qp_type = MLX5_IB_QPT_REG_UMR; 4211 init_attr->port_num = 1; 4212 qp = mlx5_ib_create_qp(pd, init_attr, NULL); 4213 if (IS_ERR(qp)) { 4214 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n"); 4215 ret = PTR_ERR(qp); 4216 goto error_3; 4217 } 4218 qp->device = &dev->ib_dev; 4219 qp->real_qp = qp; 4220 qp->uobject = NULL; 4221 qp->qp_type = MLX5_IB_QPT_REG_UMR; 4222 qp->send_cq = init_attr->send_cq; 4223 qp->recv_cq = init_attr->recv_cq; 4224 4225 attr->qp_state = IB_QPS_INIT; 4226 attr->port_num = 1; 4227 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX | 4228 IB_QP_PORT, NULL); 4229 if (ret) { 4230 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n"); 4231 goto error_4; 4232 } 4233 4234 memset(attr, 0, sizeof(*attr)); 4235 attr->qp_state = IB_QPS_RTR; 4236 attr->path_mtu = IB_MTU_256; 4237 4238 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 4239 if (ret) { 4240 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n"); 4241 goto error_4; 4242 } 4243 4244 memset(attr, 0, sizeof(*attr)); 4245 attr->qp_state = IB_QPS_RTS; 4246 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 4247 if (ret) { 4248 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n"); 4249 goto error_4; 4250 } 4251 4252 dev->umrc.qp = qp; 4253 dev->umrc.cq = cq; 4254 dev->umrc.pd = pd; 4255 4256 sema_init(&dev->umrc.sem, MAX_UMR_WR); 4257 ret = mlx5_mr_cache_init(dev); 4258 if (ret) { 4259 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 4260 goto error_4; 4261 } 4262 4263 kfree(attr); 4264 kfree(init_attr); 4265 4266 return 0; 4267 4268 error_4: 4269 mlx5_ib_destroy_qp(qp); 4270 dev->umrc.qp = NULL; 4271 4272 error_3: 4273 ib_free_cq(cq); 4274 dev->umrc.cq = NULL; 4275 4276 error_2: 4277 ib_dealloc_pd(pd); 4278 dev->umrc.pd = NULL; 4279 4280 error_0: 4281 kfree(attr); 4282 kfree(init_attr); 4283 return ret; 4284 } 4285 4286 static u8 mlx5_get_umr_fence(u8 umr_fence_cap) 4287 { 4288 switch (umr_fence_cap) { 4289 case MLX5_CAP_UMR_FENCE_NONE: 4290 return MLX5_FENCE_MODE_NONE; 4291 case MLX5_CAP_UMR_FENCE_SMALL: 4292 return MLX5_FENCE_MODE_INITIATOR_SMALL; 4293 default: 4294 return MLX5_FENCE_MODE_STRONG_ORDERING; 4295 } 4296 } 4297 4298 static int create_dev_resources(struct mlx5_ib_resources *devr) 4299 { 4300 struct ib_srq_init_attr attr; 4301 struct mlx5_ib_dev *dev; 4302 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 4303 int port; 4304 int ret = 0; 4305 4306 dev = container_of(devr, struct mlx5_ib_dev, devr); 4307 4308 mutex_init(&devr->mutex); 4309 4310 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL); 4311 if (IS_ERR(devr->p0)) { 4312 ret = PTR_ERR(devr->p0); 4313 goto error0; 4314 } 4315 devr->p0->device = &dev->ib_dev; 4316 devr->p0->uobject = NULL; 4317 atomic_set(&devr->p0->usecnt, 0); 4318 4319 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL); 4320 if (IS_ERR(devr->c0)) { 4321 ret = PTR_ERR(devr->c0); 4322 goto error1; 4323 } 4324 devr->c0->device = &dev->ib_dev; 4325 devr->c0->uobject = NULL; 4326 devr->c0->comp_handler = NULL; 4327 devr->c0->event_handler = NULL; 4328 devr->c0->cq_context = NULL; 4329 atomic_set(&devr->c0->usecnt, 0); 4330 4331 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 4332 if (IS_ERR(devr->x0)) { 4333 ret = PTR_ERR(devr->x0); 4334 goto error2; 4335 } 4336 devr->x0->device = &dev->ib_dev; 4337 devr->x0->inode = NULL; 4338 atomic_set(&devr->x0->usecnt, 0); 4339 mutex_init(&devr->x0->tgt_qp_mutex); 4340 INIT_LIST_HEAD(&devr->x0->tgt_qp_list); 4341 4342 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 4343 if (IS_ERR(devr->x1)) { 4344 ret = PTR_ERR(devr->x1); 4345 goto error3; 4346 } 4347 devr->x1->device = &dev->ib_dev; 4348 devr->x1->inode = NULL; 4349 atomic_set(&devr->x1->usecnt, 0); 4350 mutex_init(&devr->x1->tgt_qp_mutex); 4351 INIT_LIST_HEAD(&devr->x1->tgt_qp_list); 4352 4353 memset(&attr, 0, sizeof(attr)); 4354 attr.attr.max_sge = 1; 4355 attr.attr.max_wr = 1; 4356 attr.srq_type = IB_SRQT_XRC; 4357 attr.ext.cq = devr->c0; 4358 attr.ext.xrc.xrcd = devr->x0; 4359 4360 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 4361 if (IS_ERR(devr->s0)) { 4362 ret = PTR_ERR(devr->s0); 4363 goto error4; 4364 } 4365 devr->s0->device = &dev->ib_dev; 4366 devr->s0->pd = devr->p0; 4367 devr->s0->uobject = NULL; 4368 devr->s0->event_handler = NULL; 4369 devr->s0->srq_context = NULL; 4370 devr->s0->srq_type = IB_SRQT_XRC; 4371 devr->s0->ext.xrc.xrcd = devr->x0; 4372 devr->s0->ext.cq = devr->c0; 4373 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt); 4374 atomic_inc(&devr->s0->ext.cq->usecnt); 4375 atomic_inc(&devr->p0->usecnt); 4376 atomic_set(&devr->s0->usecnt, 0); 4377 4378 memset(&attr, 0, sizeof(attr)); 4379 attr.attr.max_sge = 1; 4380 attr.attr.max_wr = 1; 4381 attr.srq_type = IB_SRQT_BASIC; 4382 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 4383 if (IS_ERR(devr->s1)) { 4384 ret = PTR_ERR(devr->s1); 4385 goto error5; 4386 } 4387 devr->s1->device = &dev->ib_dev; 4388 devr->s1->pd = devr->p0; 4389 devr->s1->uobject = NULL; 4390 devr->s1->event_handler = NULL; 4391 devr->s1->srq_context = NULL; 4392 devr->s1->srq_type = IB_SRQT_BASIC; 4393 devr->s1->ext.cq = devr->c0; 4394 atomic_inc(&devr->p0->usecnt); 4395 atomic_set(&devr->s1->usecnt, 0); 4396 4397 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) { 4398 INIT_WORK(&devr->ports[port].pkey_change_work, 4399 pkey_change_handler); 4400 devr->ports[port].devr = devr; 4401 } 4402 4403 return 0; 4404 4405 error5: 4406 mlx5_ib_destroy_srq(devr->s0); 4407 error4: 4408 mlx5_ib_dealloc_xrcd(devr->x1); 4409 error3: 4410 mlx5_ib_dealloc_xrcd(devr->x0); 4411 error2: 4412 mlx5_ib_destroy_cq(devr->c0); 4413 error1: 4414 mlx5_ib_dealloc_pd(devr->p0); 4415 error0: 4416 return ret; 4417 } 4418 4419 static void destroy_dev_resources(struct mlx5_ib_resources *devr) 4420 { 4421 struct mlx5_ib_dev *dev = 4422 container_of(devr, struct mlx5_ib_dev, devr); 4423 int port; 4424 4425 mlx5_ib_destroy_srq(devr->s1); 4426 mlx5_ib_destroy_srq(devr->s0); 4427 mlx5_ib_dealloc_xrcd(devr->x0); 4428 mlx5_ib_dealloc_xrcd(devr->x1); 4429 mlx5_ib_destroy_cq(devr->c0); 4430 mlx5_ib_dealloc_pd(devr->p0); 4431 4432 /* Make sure no change P_Key work items are still executing */ 4433 for (port = 0; port < dev->num_ports; ++port) 4434 cancel_work_sync(&devr->ports[port].pkey_change_work); 4435 } 4436 4437 static u32 get_core_cap_flags(struct ib_device *ibdev) 4438 { 4439 struct mlx5_ib_dev *dev = to_mdev(ibdev); 4440 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 4441 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 4442 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 4443 bool raw_support = !mlx5_core_mp_enabled(dev->mdev); 4444 u32 ret = 0; 4445 4446 if (ll == IB_LINK_LAYER_INFINIBAND) 4447 return RDMA_CORE_PORT_IBA_IB; 4448 4449 if (raw_support) 4450 ret = RDMA_CORE_PORT_RAW_PACKET; 4451 4452 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 4453 return ret; 4454 4455 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 4456 return ret; 4457 4458 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 4459 ret |= RDMA_CORE_PORT_IBA_ROCE; 4460 4461 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 4462 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 4463 4464 return ret; 4465 } 4466 4467 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num, 4468 struct ib_port_immutable *immutable) 4469 { 4470 struct ib_port_attr attr; 4471 struct mlx5_ib_dev *dev = to_mdev(ibdev); 4472 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num); 4473 int err; 4474 4475 immutable->core_cap_flags = get_core_cap_flags(ibdev); 4476 4477 err = ib_query_port(ibdev, port_num, &attr); 4478 if (err) 4479 return err; 4480 4481 immutable->pkey_tbl_len = attr.pkey_tbl_len; 4482 immutable->gid_tbl_len = attr.gid_tbl_len; 4483 immutable->core_cap_flags = get_core_cap_flags(ibdev); 4484 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce)) 4485 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 4486 4487 return 0; 4488 } 4489 4490 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num, 4491 struct ib_port_immutable *immutable) 4492 { 4493 struct ib_port_attr attr; 4494 int err; 4495 4496 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 4497 4498 err = ib_query_port(ibdev, port_num, &attr); 4499 if (err) 4500 return err; 4501 4502 immutable->pkey_tbl_len = attr.pkey_tbl_len; 4503 immutable->gid_tbl_len = attr.gid_tbl_len; 4504 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 4505 4506 return 0; 4507 } 4508 4509 static void get_dev_fw_str(struct ib_device *ibdev, char *str) 4510 { 4511 struct mlx5_ib_dev *dev = 4512 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 4513 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d", 4514 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev), 4515 fw_rev_sub(dev->mdev)); 4516 } 4517 4518 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev) 4519 { 4520 struct mlx5_core_dev *mdev = dev->mdev; 4521 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev, 4522 MLX5_FLOW_NAMESPACE_LAG); 4523 struct mlx5_flow_table *ft; 4524 int err; 4525 4526 if (!ns || !mlx5_lag_is_active(mdev)) 4527 return 0; 4528 4529 err = mlx5_cmd_create_vport_lag(mdev); 4530 if (err) 4531 return err; 4532 4533 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0); 4534 if (IS_ERR(ft)) { 4535 err = PTR_ERR(ft); 4536 goto err_destroy_vport_lag; 4537 } 4538 4539 dev->flow_db->lag_demux_ft = ft; 4540 return 0; 4541 4542 err_destroy_vport_lag: 4543 mlx5_cmd_destroy_vport_lag(mdev); 4544 return err; 4545 } 4546 4547 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev) 4548 { 4549 struct mlx5_core_dev *mdev = dev->mdev; 4550 4551 if (dev->flow_db->lag_demux_ft) { 4552 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft); 4553 dev->flow_db->lag_demux_ft = NULL; 4554 4555 mlx5_cmd_destroy_vport_lag(mdev); 4556 } 4557 } 4558 4559 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num) 4560 { 4561 int err; 4562 4563 dev->roce[port_num].nb.notifier_call = mlx5_netdev_event; 4564 err = register_netdevice_notifier(&dev->roce[port_num].nb); 4565 if (err) { 4566 dev->roce[port_num].nb.notifier_call = NULL; 4567 return err; 4568 } 4569 4570 return 0; 4571 } 4572 4573 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num) 4574 { 4575 if (dev->roce[port_num].nb.notifier_call) { 4576 unregister_netdevice_notifier(&dev->roce[port_num].nb); 4577 dev->roce[port_num].nb.notifier_call = NULL; 4578 } 4579 } 4580 4581 static int mlx5_enable_eth(struct mlx5_ib_dev *dev, u8 port_num) 4582 { 4583 int err; 4584 4585 if (MLX5_CAP_GEN(dev->mdev, roce)) { 4586 err = mlx5_nic_vport_enable_roce(dev->mdev); 4587 if (err) 4588 return err; 4589 } 4590 4591 err = mlx5_eth_lag_init(dev); 4592 if (err) 4593 goto err_disable_roce; 4594 4595 return 0; 4596 4597 err_disable_roce: 4598 if (MLX5_CAP_GEN(dev->mdev, roce)) 4599 mlx5_nic_vport_disable_roce(dev->mdev); 4600 4601 return err; 4602 } 4603 4604 static void mlx5_disable_eth(struct mlx5_ib_dev *dev) 4605 { 4606 mlx5_eth_lag_cleanup(dev); 4607 if (MLX5_CAP_GEN(dev->mdev, roce)) 4608 mlx5_nic_vport_disable_roce(dev->mdev); 4609 } 4610 4611 struct mlx5_ib_counter { 4612 const char *name; 4613 size_t offset; 4614 }; 4615 4616 #define INIT_Q_COUNTER(_name) \ 4617 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)} 4618 4619 static const struct mlx5_ib_counter basic_q_cnts[] = { 4620 INIT_Q_COUNTER(rx_write_requests), 4621 INIT_Q_COUNTER(rx_read_requests), 4622 INIT_Q_COUNTER(rx_atomic_requests), 4623 INIT_Q_COUNTER(out_of_buffer), 4624 }; 4625 4626 static const struct mlx5_ib_counter out_of_seq_q_cnts[] = { 4627 INIT_Q_COUNTER(out_of_sequence), 4628 }; 4629 4630 static const struct mlx5_ib_counter retrans_q_cnts[] = { 4631 INIT_Q_COUNTER(duplicate_request), 4632 INIT_Q_COUNTER(rnr_nak_retry_err), 4633 INIT_Q_COUNTER(packet_seq_err), 4634 INIT_Q_COUNTER(implied_nak_seq_err), 4635 INIT_Q_COUNTER(local_ack_timeout_err), 4636 }; 4637 4638 #define INIT_CONG_COUNTER(_name) \ 4639 { .name = #_name, .offset = \ 4640 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)} 4641 4642 static const struct mlx5_ib_counter cong_cnts[] = { 4643 INIT_CONG_COUNTER(rp_cnp_ignored), 4644 INIT_CONG_COUNTER(rp_cnp_handled), 4645 INIT_CONG_COUNTER(np_ecn_marked_roce_packets), 4646 INIT_CONG_COUNTER(np_cnp_sent), 4647 }; 4648 4649 static const struct mlx5_ib_counter extended_err_cnts[] = { 4650 INIT_Q_COUNTER(resp_local_length_error), 4651 INIT_Q_COUNTER(resp_cqe_error), 4652 INIT_Q_COUNTER(req_cqe_error), 4653 INIT_Q_COUNTER(req_remote_invalid_request), 4654 INIT_Q_COUNTER(req_remote_access_errors), 4655 INIT_Q_COUNTER(resp_remote_access_errors), 4656 INIT_Q_COUNTER(resp_cqe_flush_error), 4657 INIT_Q_COUNTER(req_cqe_flush_error), 4658 }; 4659 4660 static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev) 4661 { 4662 int i; 4663 4664 for (i = 0; i < dev->num_ports; i++) { 4665 if (dev->port[i].cnts.set_id) 4666 mlx5_core_dealloc_q_counter(dev->mdev, 4667 dev->port[i].cnts.set_id); 4668 kfree(dev->port[i].cnts.names); 4669 kfree(dev->port[i].cnts.offsets); 4670 } 4671 } 4672 4673 static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev, 4674 struct mlx5_ib_counters *cnts) 4675 { 4676 u32 num_counters; 4677 4678 num_counters = ARRAY_SIZE(basic_q_cnts); 4679 4680 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) 4681 num_counters += ARRAY_SIZE(out_of_seq_q_cnts); 4682 4683 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) 4684 num_counters += ARRAY_SIZE(retrans_q_cnts); 4685 4686 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) 4687 num_counters += ARRAY_SIZE(extended_err_cnts); 4688 4689 cnts->num_q_counters = num_counters; 4690 4691 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 4692 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts); 4693 num_counters += ARRAY_SIZE(cong_cnts); 4694 } 4695 4696 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL); 4697 if (!cnts->names) 4698 return -ENOMEM; 4699 4700 cnts->offsets = kcalloc(num_counters, 4701 sizeof(cnts->offsets), GFP_KERNEL); 4702 if (!cnts->offsets) 4703 goto err_names; 4704 4705 return 0; 4706 4707 err_names: 4708 kfree(cnts->names); 4709 cnts->names = NULL; 4710 return -ENOMEM; 4711 } 4712 4713 static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev, 4714 const char **names, 4715 size_t *offsets) 4716 { 4717 int i; 4718 int j = 0; 4719 4720 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) { 4721 names[j] = basic_q_cnts[i].name; 4722 offsets[j] = basic_q_cnts[i].offset; 4723 } 4724 4725 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) { 4726 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) { 4727 names[j] = out_of_seq_q_cnts[i].name; 4728 offsets[j] = out_of_seq_q_cnts[i].offset; 4729 } 4730 } 4731 4732 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) { 4733 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) { 4734 names[j] = retrans_q_cnts[i].name; 4735 offsets[j] = retrans_q_cnts[i].offset; 4736 } 4737 } 4738 4739 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) { 4740 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) { 4741 names[j] = extended_err_cnts[i].name; 4742 offsets[j] = extended_err_cnts[i].offset; 4743 } 4744 } 4745 4746 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 4747 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) { 4748 names[j] = cong_cnts[i].name; 4749 offsets[j] = cong_cnts[i].offset; 4750 } 4751 } 4752 } 4753 4754 static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev) 4755 { 4756 int err = 0; 4757 int i; 4758 4759 for (i = 0; i < dev->num_ports; i++) { 4760 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts); 4761 if (err) 4762 goto err_alloc; 4763 4764 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names, 4765 dev->port[i].cnts.offsets); 4766 4767 err = mlx5_core_alloc_q_counter(dev->mdev, 4768 &dev->port[i].cnts.set_id); 4769 if (err) { 4770 mlx5_ib_warn(dev, 4771 "couldn't allocate queue counter for port %d, err %d\n", 4772 i + 1, err); 4773 goto err_alloc; 4774 } 4775 dev->port[i].cnts.set_id_valid = true; 4776 } 4777 4778 return 0; 4779 4780 err_alloc: 4781 mlx5_ib_dealloc_counters(dev); 4782 return err; 4783 } 4784 4785 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev, 4786 u8 port_num) 4787 { 4788 struct mlx5_ib_dev *dev = to_mdev(ibdev); 4789 struct mlx5_ib_port *port = &dev->port[port_num - 1]; 4790 4791 /* We support only per port stats */ 4792 if (port_num == 0) 4793 return NULL; 4794 4795 return rdma_alloc_hw_stats_struct(port->cnts.names, 4796 port->cnts.num_q_counters + 4797 port->cnts.num_cong_counters, 4798 RDMA_HW_STATS_DEFAULT_LIFESPAN); 4799 } 4800 4801 static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev, 4802 struct mlx5_ib_port *port, 4803 struct rdma_hw_stats *stats) 4804 { 4805 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out); 4806 void *out; 4807 __be32 val; 4808 int ret, i; 4809 4810 out = kvzalloc(outlen, GFP_KERNEL); 4811 if (!out) 4812 return -ENOMEM; 4813 4814 ret = mlx5_core_query_q_counter(mdev, 4815 port->cnts.set_id, 0, 4816 out, outlen); 4817 if (ret) 4818 goto free; 4819 4820 for (i = 0; i < port->cnts.num_q_counters; i++) { 4821 val = *(__be32 *)(out + port->cnts.offsets[i]); 4822 stats->value[i] = (u64)be32_to_cpu(val); 4823 } 4824 4825 free: 4826 kvfree(out); 4827 return ret; 4828 } 4829 4830 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev, 4831 struct rdma_hw_stats *stats, 4832 u8 port_num, int index) 4833 { 4834 struct mlx5_ib_dev *dev = to_mdev(ibdev); 4835 struct mlx5_ib_port *port = &dev->port[port_num - 1]; 4836 struct mlx5_core_dev *mdev; 4837 int ret, num_counters; 4838 u8 mdev_port_num; 4839 4840 if (!stats) 4841 return -EINVAL; 4842 4843 num_counters = port->cnts.num_q_counters + port->cnts.num_cong_counters; 4844 4845 /* q_counters are per IB device, query the master mdev */ 4846 ret = mlx5_ib_query_q_counters(dev->mdev, port, stats); 4847 if (ret) 4848 return ret; 4849 4850 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 4851 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, 4852 &mdev_port_num); 4853 if (!mdev) { 4854 /* If port is not affiliated yet, its in down state 4855 * which doesn't have any counters yet, so it would be 4856 * zero. So no need to read from the HCA. 4857 */ 4858 goto done; 4859 } 4860 ret = mlx5_lag_query_cong_counters(dev->mdev, 4861 stats->value + 4862 port->cnts.num_q_counters, 4863 port->cnts.num_cong_counters, 4864 port->cnts.offsets + 4865 port->cnts.num_q_counters); 4866 4867 mlx5_ib_put_native_port_mdev(dev, port_num); 4868 if (ret) 4869 return ret; 4870 } 4871 4872 done: 4873 return num_counters; 4874 } 4875 4876 static void mlx5_ib_free_rdma_netdev(struct net_device *netdev) 4877 { 4878 return mlx5_rdma_netdev_free(netdev); 4879 } 4880 4881 static struct net_device* 4882 mlx5_ib_alloc_rdma_netdev(struct ib_device *hca, 4883 u8 port_num, 4884 enum rdma_netdev_t type, 4885 const char *name, 4886 unsigned char name_assign_type, 4887 void (*setup)(struct net_device *)) 4888 { 4889 struct net_device *netdev; 4890 struct rdma_netdev *rn; 4891 4892 if (type != RDMA_NETDEV_IPOIB) 4893 return ERR_PTR(-EOPNOTSUPP); 4894 4895 netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca, 4896 name, setup); 4897 if (likely(!IS_ERR_OR_NULL(netdev))) { 4898 rn = netdev_priv(netdev); 4899 rn->free_rdma_netdev = mlx5_ib_free_rdma_netdev; 4900 } 4901 return netdev; 4902 } 4903 4904 static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev) 4905 { 4906 if (!dev->delay_drop.dbg) 4907 return; 4908 debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs); 4909 kfree(dev->delay_drop.dbg); 4910 dev->delay_drop.dbg = NULL; 4911 } 4912 4913 static void cancel_delay_drop(struct mlx5_ib_dev *dev) 4914 { 4915 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4916 return; 4917 4918 cancel_work_sync(&dev->delay_drop.delay_drop_work); 4919 delay_drop_debugfs_cleanup(dev); 4920 } 4921 4922 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf, 4923 size_t count, loff_t *pos) 4924 { 4925 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 4926 char lbuf[20]; 4927 int len; 4928 4929 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout); 4930 return simple_read_from_buffer(buf, count, pos, lbuf, len); 4931 } 4932 4933 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf, 4934 size_t count, loff_t *pos) 4935 { 4936 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 4937 u32 timeout; 4938 u32 var; 4939 4940 if (kstrtouint_from_user(buf, count, 0, &var)) 4941 return -EFAULT; 4942 4943 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 4944 1000); 4945 if (timeout != var) 4946 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n", 4947 timeout); 4948 4949 delay_drop->timeout = timeout; 4950 4951 return count; 4952 } 4953 4954 static const struct file_operations fops_delay_drop_timeout = { 4955 .owner = THIS_MODULE, 4956 .open = simple_open, 4957 .write = delay_drop_timeout_write, 4958 .read = delay_drop_timeout_read, 4959 }; 4960 4961 static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev) 4962 { 4963 struct mlx5_ib_dbg_delay_drop *dbg; 4964 4965 if (!mlx5_debugfs_root) 4966 return 0; 4967 4968 dbg = kzalloc(sizeof(*dbg), GFP_KERNEL); 4969 if (!dbg) 4970 return -ENOMEM; 4971 4972 dev->delay_drop.dbg = dbg; 4973 4974 dbg->dir_debugfs = 4975 debugfs_create_dir("delay_drop", 4976 dev->mdev->priv.dbg_root); 4977 if (!dbg->dir_debugfs) 4978 goto out_debugfs; 4979 4980 dbg->events_cnt_debugfs = 4981 debugfs_create_atomic_t("num_timeout_events", 0400, 4982 dbg->dir_debugfs, 4983 &dev->delay_drop.events_cnt); 4984 if (!dbg->events_cnt_debugfs) 4985 goto out_debugfs; 4986 4987 dbg->rqs_cnt_debugfs = 4988 debugfs_create_atomic_t("num_rqs", 0400, 4989 dbg->dir_debugfs, 4990 &dev->delay_drop.rqs_cnt); 4991 if (!dbg->rqs_cnt_debugfs) 4992 goto out_debugfs; 4993 4994 dbg->timeout_debugfs = 4995 debugfs_create_file("timeout", 0600, 4996 dbg->dir_debugfs, 4997 &dev->delay_drop, 4998 &fops_delay_drop_timeout); 4999 if (!dbg->timeout_debugfs) 5000 goto out_debugfs; 5001 5002 return 0; 5003 5004 out_debugfs: 5005 delay_drop_debugfs_cleanup(dev); 5006 return -ENOMEM; 5007 } 5008 5009 static void init_delay_drop(struct mlx5_ib_dev *dev) 5010 { 5011 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 5012 return; 5013 5014 mutex_init(&dev->delay_drop.lock); 5015 dev->delay_drop.dev = dev; 5016 dev->delay_drop.activate = false; 5017 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000; 5018 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler); 5019 atomic_set(&dev->delay_drop.rqs_cnt, 0); 5020 atomic_set(&dev->delay_drop.events_cnt, 0); 5021 5022 if (delay_drop_debugfs_init(dev)) 5023 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n"); 5024 } 5025 5026 static const struct cpumask * 5027 mlx5_ib_get_vector_affinity(struct ib_device *ibdev, int comp_vector) 5028 { 5029 struct mlx5_ib_dev *dev = to_mdev(ibdev); 5030 5031 return mlx5_get_vector_affinity_hint(dev->mdev, comp_vector); 5032 } 5033 5034 /* The mlx5_ib_multiport_mutex should be held when calling this function */ 5035 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev, 5036 struct mlx5_ib_multiport_info *mpi) 5037 { 5038 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 5039 struct mlx5_ib_port *port = &ibdev->port[port_num]; 5040 int comps; 5041 int err; 5042 int i; 5043 5044 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num); 5045 5046 spin_lock(&port->mp.mpi_lock); 5047 if (!mpi->ibdev) { 5048 spin_unlock(&port->mp.mpi_lock); 5049 return; 5050 } 5051 mpi->ibdev = NULL; 5052 5053 spin_unlock(&port->mp.mpi_lock); 5054 mlx5_remove_netdev_notifier(ibdev, port_num); 5055 spin_lock(&port->mp.mpi_lock); 5056 5057 comps = mpi->mdev_refcnt; 5058 if (comps) { 5059 mpi->unaffiliate = true; 5060 init_completion(&mpi->unref_comp); 5061 spin_unlock(&port->mp.mpi_lock); 5062 5063 for (i = 0; i < comps; i++) 5064 wait_for_completion(&mpi->unref_comp); 5065 5066 spin_lock(&port->mp.mpi_lock); 5067 mpi->unaffiliate = false; 5068 } 5069 5070 port->mp.mpi = NULL; 5071 5072 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 5073 5074 spin_unlock(&port->mp.mpi_lock); 5075 5076 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev); 5077 5078 mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1); 5079 /* Log an error, still needed to cleanup the pointers and add 5080 * it back to the list. 5081 */ 5082 if (err) 5083 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n", 5084 port_num + 1); 5085 5086 ibdev->roce[port_num].last_port_state = IB_PORT_DOWN; 5087 } 5088 5089 /* The mlx5_ib_multiport_mutex should be held when calling this function */ 5090 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev, 5091 struct mlx5_ib_multiport_info *mpi) 5092 { 5093 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 5094 int err; 5095 5096 spin_lock(&ibdev->port[port_num].mp.mpi_lock); 5097 if (ibdev->port[port_num].mp.mpi) { 5098 mlx5_ib_warn(ibdev, "port %d already affiliated.\n", 5099 port_num + 1); 5100 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 5101 return false; 5102 } 5103 5104 ibdev->port[port_num].mp.mpi = mpi; 5105 mpi->ibdev = ibdev; 5106 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 5107 5108 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev); 5109 if (err) 5110 goto unbind; 5111 5112 err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev)); 5113 if (err) 5114 goto unbind; 5115 5116 err = mlx5_add_netdev_notifier(ibdev, port_num); 5117 if (err) { 5118 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n", 5119 port_num + 1); 5120 goto unbind; 5121 } 5122 5123 err = mlx5_ib_init_cong_debugfs(ibdev, port_num); 5124 if (err) 5125 goto unbind; 5126 5127 return true; 5128 5129 unbind: 5130 mlx5_ib_unbind_slave_port(ibdev, mpi); 5131 return false; 5132 } 5133 5134 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev) 5135 { 5136 int port_num = mlx5_core_native_port_num(dev->mdev) - 1; 5137 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 5138 port_num + 1); 5139 struct mlx5_ib_multiport_info *mpi; 5140 int err; 5141 int i; 5142 5143 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 5144 return 0; 5145 5146 err = mlx5_query_nic_vport_system_image_guid(dev->mdev, 5147 &dev->sys_image_guid); 5148 if (err) 5149 return err; 5150 5151 err = mlx5_nic_vport_enable_roce(dev->mdev); 5152 if (err) 5153 return err; 5154 5155 mutex_lock(&mlx5_ib_multiport_mutex); 5156 for (i = 0; i < dev->num_ports; i++) { 5157 bool bound = false; 5158 5159 /* build a stub multiport info struct for the native port. */ 5160 if (i == port_num) { 5161 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 5162 if (!mpi) { 5163 mutex_unlock(&mlx5_ib_multiport_mutex); 5164 mlx5_nic_vport_disable_roce(dev->mdev); 5165 return -ENOMEM; 5166 } 5167 5168 mpi->is_master = true; 5169 mpi->mdev = dev->mdev; 5170 mpi->sys_image_guid = dev->sys_image_guid; 5171 dev->port[i].mp.mpi = mpi; 5172 mpi->ibdev = dev; 5173 mpi = NULL; 5174 continue; 5175 } 5176 5177 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list, 5178 list) { 5179 if (dev->sys_image_guid == mpi->sys_image_guid && 5180 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) { 5181 bound = mlx5_ib_bind_slave_port(dev, mpi); 5182 } 5183 5184 if (bound) { 5185 dev_dbg(&mpi->mdev->pdev->dev, "removing port from unaffiliated list.\n"); 5186 mlx5_ib_dbg(dev, "port %d bound\n", i + 1); 5187 list_del(&mpi->list); 5188 break; 5189 } 5190 } 5191 if (!bound) { 5192 get_port_caps(dev, i + 1); 5193 mlx5_ib_dbg(dev, "no free port found for port %d\n", 5194 i + 1); 5195 } 5196 } 5197 5198 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list); 5199 mutex_unlock(&mlx5_ib_multiport_mutex); 5200 return err; 5201 } 5202 5203 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev) 5204 { 5205 int port_num = mlx5_core_native_port_num(dev->mdev) - 1; 5206 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 5207 port_num + 1); 5208 int i; 5209 5210 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 5211 return; 5212 5213 mutex_lock(&mlx5_ib_multiport_mutex); 5214 for (i = 0; i < dev->num_ports; i++) { 5215 if (dev->port[i].mp.mpi) { 5216 /* Destroy the native port stub */ 5217 if (i == port_num) { 5218 kfree(dev->port[i].mp.mpi); 5219 dev->port[i].mp.mpi = NULL; 5220 } else { 5221 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1); 5222 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi); 5223 } 5224 } 5225 } 5226 5227 mlx5_ib_dbg(dev, "removing from devlist\n"); 5228 list_del(&dev->ib_dev_list); 5229 mutex_unlock(&mlx5_ib_multiport_mutex); 5230 5231 mlx5_nic_vport_disable_roce(dev->mdev); 5232 } 5233 5234 ADD_UVERBS_ATTRIBUTES_SIMPLE(mlx5_ib_dm, UVERBS_OBJECT_DM, 5235 UVERBS_METHOD_DM_ALLOC, 5236 &UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET, 5237 UVERBS_ATTR_TYPE(u64), 5238 UA_FLAGS(UVERBS_ATTR_SPEC_F_MANDATORY)), 5239 &UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX, 5240 UVERBS_ATTR_TYPE(u16), 5241 UA_FLAGS(UVERBS_ATTR_SPEC_F_MANDATORY))); 5242 5243 ADD_UVERBS_ATTRIBUTES_SIMPLE(mlx5_ib_flow_action, UVERBS_OBJECT_FLOW_ACTION, 5244 UVERBS_METHOD_FLOW_ACTION_ESP_CREATE, 5245 &UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS, 5246 UVERBS_ATTR_TYPE(u64), 5247 UA_FLAGS(UVERBS_ATTR_SPEC_F_MANDATORY))); 5248 5249 #define NUM_TREES 2 5250 static int populate_specs_root(struct mlx5_ib_dev *dev) 5251 { 5252 const struct uverbs_object_tree_def *default_root[NUM_TREES + 1] = { 5253 uverbs_default_get_objects()}; 5254 size_t num_trees = 1; 5255 5256 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE && 5257 !WARN_ON(num_trees >= ARRAY_SIZE(default_root))) 5258 default_root[num_trees++] = &mlx5_ib_flow_action; 5259 5260 if (MLX5_CAP_DEV_MEM(dev->mdev, memic) && 5261 !WARN_ON(num_trees >= ARRAY_SIZE(default_root))) 5262 default_root[num_trees++] = &mlx5_ib_dm; 5263 5264 dev->ib_dev.specs_root = 5265 uverbs_alloc_spec_tree(num_trees, default_root); 5266 5267 return PTR_ERR_OR_ZERO(dev->ib_dev.specs_root); 5268 } 5269 5270 static void depopulate_specs_root(struct mlx5_ib_dev *dev) 5271 { 5272 uverbs_free_spec_tree(dev->ib_dev.specs_root); 5273 } 5274 5275 static int mlx5_ib_read_counters(struct ib_counters *counters, 5276 struct ib_counters_read_attr *read_attr, 5277 struct uverbs_attr_bundle *attrs) 5278 { 5279 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters); 5280 struct mlx5_read_counters_attr mread_attr = {}; 5281 struct mlx5_ib_flow_counters_desc *desc; 5282 int ret, i; 5283 5284 mutex_lock(&mcounters->mcntrs_mutex); 5285 if (mcounters->cntrs_max_index > read_attr->ncounters) { 5286 ret = -EINVAL; 5287 goto err_bound; 5288 } 5289 5290 mread_attr.out = kcalloc(mcounters->counters_num, sizeof(u64), 5291 GFP_KERNEL); 5292 if (!mread_attr.out) { 5293 ret = -ENOMEM; 5294 goto err_bound; 5295 } 5296 5297 mread_attr.hw_cntrs_hndl = mcounters->hw_cntrs_hndl; 5298 mread_attr.flags = read_attr->flags; 5299 ret = mcounters->read_counters(counters->device, &mread_attr); 5300 if (ret) 5301 goto err_read; 5302 5303 /* do the pass over the counters data array to assign according to the 5304 * descriptions and indexing pairs 5305 */ 5306 desc = mcounters->counters_data; 5307 for (i = 0; i < mcounters->ncounters; i++) 5308 read_attr->counters_buff[desc[i].index] += mread_attr.out[desc[i].description]; 5309 5310 err_read: 5311 kfree(mread_attr.out); 5312 err_bound: 5313 mutex_unlock(&mcounters->mcntrs_mutex); 5314 return ret; 5315 } 5316 5317 static int mlx5_ib_destroy_counters(struct ib_counters *counters) 5318 { 5319 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters); 5320 5321 counters_clear_description(counters); 5322 if (mcounters->hw_cntrs_hndl) 5323 mlx5_fc_destroy(to_mdev(counters->device)->mdev, 5324 mcounters->hw_cntrs_hndl); 5325 5326 kfree(mcounters); 5327 5328 return 0; 5329 } 5330 5331 static struct ib_counters *mlx5_ib_create_counters(struct ib_device *device, 5332 struct uverbs_attr_bundle *attrs) 5333 { 5334 struct mlx5_ib_mcounters *mcounters; 5335 5336 mcounters = kzalloc(sizeof(*mcounters), GFP_KERNEL); 5337 if (!mcounters) 5338 return ERR_PTR(-ENOMEM); 5339 5340 mutex_init(&mcounters->mcntrs_mutex); 5341 5342 return &mcounters->ibcntrs; 5343 } 5344 5345 void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev) 5346 { 5347 mlx5_ib_cleanup_multiport_master(dev); 5348 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 5349 cleanup_srcu_struct(&dev->mr_srcu); 5350 #endif 5351 kfree(dev->port); 5352 } 5353 5354 int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev) 5355 { 5356 struct mlx5_core_dev *mdev = dev->mdev; 5357 const char *name; 5358 int err; 5359 int i; 5360 5361 dev->port = kcalloc(dev->num_ports, sizeof(*dev->port), 5362 GFP_KERNEL); 5363 if (!dev->port) 5364 return -ENOMEM; 5365 5366 for (i = 0; i < dev->num_ports; i++) { 5367 spin_lock_init(&dev->port[i].mp.mpi_lock); 5368 rwlock_init(&dev->roce[i].netdev_lock); 5369 } 5370 5371 err = mlx5_ib_init_multiport_master(dev); 5372 if (err) 5373 goto err_free_port; 5374 5375 if (!mlx5_core_mp_enabled(mdev)) { 5376 for (i = 1; i <= dev->num_ports; i++) { 5377 err = get_port_caps(dev, i); 5378 if (err) 5379 break; 5380 } 5381 } else { 5382 err = get_port_caps(dev, mlx5_core_native_port_num(mdev)); 5383 } 5384 if (err) 5385 goto err_mp; 5386 5387 if (mlx5_use_mad_ifc(dev)) 5388 get_ext_port_caps(dev); 5389 5390 if (!mlx5_lag_is_active(mdev)) 5391 name = "mlx5_%d"; 5392 else 5393 name = "mlx5_bond_%d"; 5394 5395 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX); 5396 dev->ib_dev.owner = THIS_MODULE; 5397 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 5398 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 5399 dev->ib_dev.phys_port_cnt = dev->num_ports; 5400 dev->ib_dev.num_comp_vectors = 5401 dev->mdev->priv.eq_table.num_comp_vectors; 5402 dev->ib_dev.dev.parent = &mdev->pdev->dev; 5403 5404 mutex_init(&dev->cap_mask_mutex); 5405 INIT_LIST_HEAD(&dev->qp_list); 5406 spin_lock_init(&dev->reset_flow_resource_lock); 5407 5408 spin_lock_init(&dev->memic.memic_lock); 5409 dev->memic.dev = mdev; 5410 5411 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 5412 err = init_srcu_struct(&dev->mr_srcu); 5413 if (err) 5414 goto err_free_port; 5415 #endif 5416 5417 return 0; 5418 err_mp: 5419 mlx5_ib_cleanup_multiport_master(dev); 5420 5421 err_free_port: 5422 kfree(dev->port); 5423 5424 return -ENOMEM; 5425 } 5426 5427 static int mlx5_ib_stage_flow_db_init(struct mlx5_ib_dev *dev) 5428 { 5429 dev->flow_db = kzalloc(sizeof(*dev->flow_db), GFP_KERNEL); 5430 5431 if (!dev->flow_db) 5432 return -ENOMEM; 5433 5434 mutex_init(&dev->flow_db->lock); 5435 5436 return 0; 5437 } 5438 5439 int mlx5_ib_stage_rep_flow_db_init(struct mlx5_ib_dev *dev) 5440 { 5441 struct mlx5_ib_dev *nic_dev; 5442 5443 nic_dev = mlx5_ib_get_uplink_ibdev(dev->mdev->priv.eswitch); 5444 5445 if (!nic_dev) 5446 return -EINVAL; 5447 5448 dev->flow_db = nic_dev->flow_db; 5449 5450 return 0; 5451 } 5452 5453 static void mlx5_ib_stage_flow_db_cleanup(struct mlx5_ib_dev *dev) 5454 { 5455 kfree(dev->flow_db); 5456 } 5457 5458 int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev) 5459 { 5460 struct mlx5_core_dev *mdev = dev->mdev; 5461 int err; 5462 5463 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION; 5464 dev->ib_dev.uverbs_cmd_mask = 5465 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | 5466 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | 5467 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | 5468 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | 5469 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | 5470 (1ull << IB_USER_VERBS_CMD_CREATE_AH) | 5471 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) | 5472 (1ull << IB_USER_VERBS_CMD_REG_MR) | 5473 (1ull << IB_USER_VERBS_CMD_REREG_MR) | 5474 (1ull << IB_USER_VERBS_CMD_DEREG_MR) | 5475 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 5476 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | 5477 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) | 5478 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | 5479 (1ull << IB_USER_VERBS_CMD_CREATE_QP) | 5480 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | 5481 (1ull << IB_USER_VERBS_CMD_QUERY_QP) | 5482 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | 5483 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) | 5484 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) | 5485 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | 5486 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | 5487 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | 5488 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | 5489 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) | 5490 (1ull << IB_USER_VERBS_CMD_OPEN_QP); 5491 dev->ib_dev.uverbs_ex_cmd_mask = 5492 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) | 5493 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) | 5494 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) | 5495 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP) | 5496 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ); 5497 5498 dev->ib_dev.query_device = mlx5_ib_query_device; 5499 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer; 5500 dev->ib_dev.query_gid = mlx5_ib_query_gid; 5501 dev->ib_dev.add_gid = mlx5_ib_add_gid; 5502 dev->ib_dev.del_gid = mlx5_ib_del_gid; 5503 dev->ib_dev.query_pkey = mlx5_ib_query_pkey; 5504 dev->ib_dev.modify_device = mlx5_ib_modify_device; 5505 dev->ib_dev.modify_port = mlx5_ib_modify_port; 5506 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext; 5507 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext; 5508 dev->ib_dev.mmap = mlx5_ib_mmap; 5509 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd; 5510 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd; 5511 dev->ib_dev.create_ah = mlx5_ib_create_ah; 5512 dev->ib_dev.query_ah = mlx5_ib_query_ah; 5513 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah; 5514 dev->ib_dev.create_srq = mlx5_ib_create_srq; 5515 dev->ib_dev.modify_srq = mlx5_ib_modify_srq; 5516 dev->ib_dev.query_srq = mlx5_ib_query_srq; 5517 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq; 5518 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv; 5519 dev->ib_dev.create_qp = mlx5_ib_create_qp; 5520 dev->ib_dev.modify_qp = mlx5_ib_modify_qp; 5521 dev->ib_dev.query_qp = mlx5_ib_query_qp; 5522 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp; 5523 dev->ib_dev.post_send = mlx5_ib_post_send; 5524 dev->ib_dev.post_recv = mlx5_ib_post_recv; 5525 dev->ib_dev.create_cq = mlx5_ib_create_cq; 5526 dev->ib_dev.modify_cq = mlx5_ib_modify_cq; 5527 dev->ib_dev.resize_cq = mlx5_ib_resize_cq; 5528 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq; 5529 dev->ib_dev.poll_cq = mlx5_ib_poll_cq; 5530 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq; 5531 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr; 5532 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr; 5533 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr; 5534 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr; 5535 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach; 5536 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach; 5537 dev->ib_dev.process_mad = mlx5_ib_process_mad; 5538 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr; 5539 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg; 5540 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status; 5541 dev->ib_dev.get_dev_fw_str = get_dev_fw_str; 5542 dev->ib_dev.get_vector_affinity = mlx5_ib_get_vector_affinity; 5543 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads)) 5544 dev->ib_dev.alloc_rdma_netdev = mlx5_ib_alloc_rdma_netdev; 5545 5546 if (mlx5_core_is_pf(mdev)) { 5547 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config; 5548 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state; 5549 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats; 5550 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid; 5551 } 5552 5553 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext; 5554 5555 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence)); 5556 5557 if (MLX5_CAP_GEN(mdev, imaicl)) { 5558 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw; 5559 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw; 5560 dev->ib_dev.uverbs_cmd_mask |= 5561 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) | 5562 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW); 5563 } 5564 5565 if (MLX5_CAP_GEN(mdev, xrc)) { 5566 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd; 5567 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd; 5568 dev->ib_dev.uverbs_cmd_mask |= 5569 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) | 5570 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD); 5571 } 5572 5573 if (MLX5_CAP_DEV_MEM(mdev, memic)) { 5574 dev->ib_dev.alloc_dm = mlx5_ib_alloc_dm; 5575 dev->ib_dev.dealloc_dm = mlx5_ib_dealloc_dm; 5576 dev->ib_dev.reg_dm_mr = mlx5_ib_reg_dm_mr; 5577 } 5578 5579 dev->ib_dev.create_flow = mlx5_ib_create_flow; 5580 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow; 5581 dev->ib_dev.uverbs_ex_cmd_mask |= 5582 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) | 5583 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW); 5584 dev->ib_dev.create_flow_action_esp = mlx5_ib_create_flow_action_esp; 5585 dev->ib_dev.destroy_flow_action = mlx5_ib_destroy_flow_action; 5586 dev->ib_dev.modify_flow_action_esp = mlx5_ib_modify_flow_action_esp; 5587 dev->ib_dev.driver_id = RDMA_DRIVER_MLX5; 5588 dev->ib_dev.create_counters = mlx5_ib_create_counters; 5589 dev->ib_dev.destroy_counters = mlx5_ib_destroy_counters; 5590 dev->ib_dev.read_counters = mlx5_ib_read_counters; 5591 5592 err = init_node_data(dev); 5593 if (err) 5594 return err; 5595 5596 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && 5597 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) || 5598 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 5599 mutex_init(&dev->lb_mutex); 5600 5601 return 0; 5602 } 5603 5604 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev) 5605 { 5606 dev->ib_dev.get_port_immutable = mlx5_port_immutable; 5607 dev->ib_dev.query_port = mlx5_ib_query_port; 5608 5609 return 0; 5610 } 5611 5612 int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev) 5613 { 5614 dev->ib_dev.get_port_immutable = mlx5_port_rep_immutable; 5615 dev->ib_dev.query_port = mlx5_ib_rep_query_port; 5616 5617 return 0; 5618 } 5619 5620 static int mlx5_ib_stage_common_roce_init(struct mlx5_ib_dev *dev, 5621 u8 port_num) 5622 { 5623 int i; 5624 5625 for (i = 0; i < dev->num_ports; i++) { 5626 dev->roce[i].dev = dev; 5627 dev->roce[i].native_port_num = i + 1; 5628 dev->roce[i].last_port_state = IB_PORT_DOWN; 5629 } 5630 5631 dev->ib_dev.get_netdev = mlx5_ib_get_netdev; 5632 dev->ib_dev.create_wq = mlx5_ib_create_wq; 5633 dev->ib_dev.modify_wq = mlx5_ib_modify_wq; 5634 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq; 5635 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table; 5636 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table; 5637 5638 dev->ib_dev.uverbs_ex_cmd_mask |= 5639 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) | 5640 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) | 5641 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) | 5642 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) | 5643 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL); 5644 5645 return mlx5_add_netdev_notifier(dev, port_num); 5646 } 5647 5648 static void mlx5_ib_stage_common_roce_cleanup(struct mlx5_ib_dev *dev) 5649 { 5650 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 5651 5652 mlx5_remove_netdev_notifier(dev, port_num); 5653 } 5654 5655 int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev) 5656 { 5657 struct mlx5_core_dev *mdev = dev->mdev; 5658 enum rdma_link_layer ll; 5659 int port_type_cap; 5660 int err = 0; 5661 u8 port_num; 5662 5663 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 5664 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 5665 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 5666 5667 if (ll == IB_LINK_LAYER_ETHERNET) 5668 err = mlx5_ib_stage_common_roce_init(dev, port_num); 5669 5670 return err; 5671 } 5672 5673 void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev) 5674 { 5675 mlx5_ib_stage_common_roce_cleanup(dev); 5676 } 5677 5678 static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev) 5679 { 5680 struct mlx5_core_dev *mdev = dev->mdev; 5681 enum rdma_link_layer ll; 5682 int port_type_cap; 5683 u8 port_num; 5684 int err; 5685 5686 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 5687 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 5688 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 5689 5690 if (ll == IB_LINK_LAYER_ETHERNET) { 5691 err = mlx5_ib_stage_common_roce_init(dev, port_num); 5692 if (err) 5693 return err; 5694 5695 err = mlx5_enable_eth(dev, port_num); 5696 if (err) 5697 goto cleanup; 5698 } 5699 5700 return 0; 5701 cleanup: 5702 mlx5_ib_stage_common_roce_cleanup(dev); 5703 5704 return err; 5705 } 5706 5707 static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev) 5708 { 5709 struct mlx5_core_dev *mdev = dev->mdev; 5710 enum rdma_link_layer ll; 5711 int port_type_cap; 5712 u8 port_num; 5713 5714 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 5715 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 5716 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 5717 5718 if (ll == IB_LINK_LAYER_ETHERNET) { 5719 mlx5_disable_eth(dev); 5720 mlx5_ib_stage_common_roce_cleanup(dev); 5721 } 5722 } 5723 5724 int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev) 5725 { 5726 return create_dev_resources(&dev->devr); 5727 } 5728 5729 void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev) 5730 { 5731 destroy_dev_resources(&dev->devr); 5732 } 5733 5734 static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev) 5735 { 5736 mlx5_ib_internal_fill_odp_caps(dev); 5737 5738 return mlx5_ib_odp_init_one(dev); 5739 } 5740 5741 int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev) 5742 { 5743 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) { 5744 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats; 5745 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats; 5746 5747 return mlx5_ib_alloc_counters(dev); 5748 } 5749 5750 return 0; 5751 } 5752 5753 void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev) 5754 { 5755 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) 5756 mlx5_ib_dealloc_counters(dev); 5757 } 5758 5759 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev) 5760 { 5761 return mlx5_ib_init_cong_debugfs(dev, 5762 mlx5_core_native_port_num(dev->mdev) - 1); 5763 } 5764 5765 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev) 5766 { 5767 mlx5_ib_cleanup_cong_debugfs(dev, 5768 mlx5_core_native_port_num(dev->mdev) - 1); 5769 } 5770 5771 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev) 5772 { 5773 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev); 5774 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar); 5775 } 5776 5777 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev) 5778 { 5779 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar); 5780 } 5781 5782 int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev) 5783 { 5784 int err; 5785 5786 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false); 5787 if (err) 5788 return err; 5789 5790 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true); 5791 if (err) 5792 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 5793 5794 return err; 5795 } 5796 5797 void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev) 5798 { 5799 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 5800 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 5801 } 5802 5803 static int mlx5_ib_stage_populate_specs(struct mlx5_ib_dev *dev) 5804 { 5805 return populate_specs_root(dev); 5806 } 5807 5808 int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev) 5809 { 5810 return ib_register_device(&dev->ib_dev, NULL); 5811 } 5812 5813 static void mlx5_ib_stage_depopulate_specs(struct mlx5_ib_dev *dev) 5814 { 5815 depopulate_specs_root(dev); 5816 } 5817 5818 void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev) 5819 { 5820 destroy_umrc_res(dev); 5821 } 5822 5823 void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev) 5824 { 5825 ib_unregister_device(&dev->ib_dev); 5826 } 5827 5828 int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev) 5829 { 5830 return create_umr_res(dev); 5831 } 5832 5833 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev) 5834 { 5835 init_delay_drop(dev); 5836 5837 return 0; 5838 } 5839 5840 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev) 5841 { 5842 cancel_delay_drop(dev); 5843 } 5844 5845 int mlx5_ib_stage_class_attr_init(struct mlx5_ib_dev *dev) 5846 { 5847 int err; 5848 int i; 5849 5850 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) { 5851 err = device_create_file(&dev->ib_dev.dev, 5852 mlx5_class_attributes[i]); 5853 if (err) 5854 return err; 5855 } 5856 5857 return 0; 5858 } 5859 5860 static int mlx5_ib_stage_rep_reg_init(struct mlx5_ib_dev *dev) 5861 { 5862 mlx5_ib_register_vport_reps(dev); 5863 5864 return 0; 5865 } 5866 5867 static void mlx5_ib_stage_rep_reg_cleanup(struct mlx5_ib_dev *dev) 5868 { 5869 mlx5_ib_unregister_vport_reps(dev); 5870 } 5871 5872 void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 5873 const struct mlx5_ib_profile *profile, 5874 int stage) 5875 { 5876 /* Number of stages to cleanup */ 5877 while (stage) { 5878 stage--; 5879 if (profile->stage[stage].cleanup) 5880 profile->stage[stage].cleanup(dev); 5881 } 5882 5883 ib_dealloc_device((struct ib_device *)dev); 5884 } 5885 5886 static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev, u8 port_num); 5887 5888 void *__mlx5_ib_add(struct mlx5_ib_dev *dev, 5889 const struct mlx5_ib_profile *profile) 5890 { 5891 int err; 5892 int i; 5893 5894 printk_once(KERN_INFO "%s", mlx5_version); 5895 5896 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) { 5897 if (profile->stage[i].init) { 5898 err = profile->stage[i].init(dev); 5899 if (err) 5900 goto err_out; 5901 } 5902 } 5903 5904 dev->profile = profile; 5905 dev->ib_active = true; 5906 5907 return dev; 5908 5909 err_out: 5910 __mlx5_ib_remove(dev, profile, i); 5911 5912 return NULL; 5913 } 5914 5915 static const struct mlx5_ib_profile pf_profile = { 5916 STAGE_CREATE(MLX5_IB_STAGE_INIT, 5917 mlx5_ib_stage_init_init, 5918 mlx5_ib_stage_init_cleanup), 5919 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB, 5920 mlx5_ib_stage_flow_db_init, 5921 mlx5_ib_stage_flow_db_cleanup), 5922 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 5923 mlx5_ib_stage_caps_init, 5924 NULL), 5925 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 5926 mlx5_ib_stage_non_default_cb, 5927 NULL), 5928 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 5929 mlx5_ib_stage_roce_init, 5930 mlx5_ib_stage_roce_cleanup), 5931 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 5932 mlx5_ib_stage_dev_res_init, 5933 mlx5_ib_stage_dev_res_cleanup), 5934 STAGE_CREATE(MLX5_IB_STAGE_ODP, 5935 mlx5_ib_stage_odp_init, 5936 NULL), 5937 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 5938 mlx5_ib_stage_counters_init, 5939 mlx5_ib_stage_counters_cleanup), 5940 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 5941 mlx5_ib_stage_cong_debugfs_init, 5942 mlx5_ib_stage_cong_debugfs_cleanup), 5943 STAGE_CREATE(MLX5_IB_STAGE_UAR, 5944 mlx5_ib_stage_uar_init, 5945 mlx5_ib_stage_uar_cleanup), 5946 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 5947 mlx5_ib_stage_bfrag_init, 5948 mlx5_ib_stage_bfrag_cleanup), 5949 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 5950 NULL, 5951 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 5952 STAGE_CREATE(MLX5_IB_STAGE_SPECS, 5953 mlx5_ib_stage_populate_specs, 5954 mlx5_ib_stage_depopulate_specs), 5955 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 5956 mlx5_ib_stage_ib_reg_init, 5957 mlx5_ib_stage_ib_reg_cleanup), 5958 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 5959 mlx5_ib_stage_post_ib_reg_umr_init, 5960 NULL), 5961 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP, 5962 mlx5_ib_stage_delay_drop_init, 5963 mlx5_ib_stage_delay_drop_cleanup), 5964 STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR, 5965 mlx5_ib_stage_class_attr_init, 5966 NULL), 5967 }; 5968 5969 static const struct mlx5_ib_profile nic_rep_profile = { 5970 STAGE_CREATE(MLX5_IB_STAGE_INIT, 5971 mlx5_ib_stage_init_init, 5972 mlx5_ib_stage_init_cleanup), 5973 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB, 5974 mlx5_ib_stage_flow_db_init, 5975 mlx5_ib_stage_flow_db_cleanup), 5976 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 5977 mlx5_ib_stage_caps_init, 5978 NULL), 5979 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 5980 mlx5_ib_stage_rep_non_default_cb, 5981 NULL), 5982 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 5983 mlx5_ib_stage_rep_roce_init, 5984 mlx5_ib_stage_rep_roce_cleanup), 5985 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 5986 mlx5_ib_stage_dev_res_init, 5987 mlx5_ib_stage_dev_res_cleanup), 5988 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 5989 mlx5_ib_stage_counters_init, 5990 mlx5_ib_stage_counters_cleanup), 5991 STAGE_CREATE(MLX5_IB_STAGE_UAR, 5992 mlx5_ib_stage_uar_init, 5993 mlx5_ib_stage_uar_cleanup), 5994 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 5995 mlx5_ib_stage_bfrag_init, 5996 mlx5_ib_stage_bfrag_cleanup), 5997 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 5998 NULL, 5999 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 6000 STAGE_CREATE(MLX5_IB_STAGE_SPECS, 6001 mlx5_ib_stage_populate_specs, 6002 mlx5_ib_stage_depopulate_specs), 6003 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 6004 mlx5_ib_stage_ib_reg_init, 6005 mlx5_ib_stage_ib_reg_cleanup), 6006 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 6007 mlx5_ib_stage_post_ib_reg_umr_init, 6008 NULL), 6009 STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR, 6010 mlx5_ib_stage_class_attr_init, 6011 NULL), 6012 STAGE_CREATE(MLX5_IB_STAGE_REP_REG, 6013 mlx5_ib_stage_rep_reg_init, 6014 mlx5_ib_stage_rep_reg_cleanup), 6015 }; 6016 6017 static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev, u8 port_num) 6018 { 6019 struct mlx5_ib_multiport_info *mpi; 6020 struct mlx5_ib_dev *dev; 6021 bool bound = false; 6022 int err; 6023 6024 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 6025 if (!mpi) 6026 return NULL; 6027 6028 mpi->mdev = mdev; 6029 6030 err = mlx5_query_nic_vport_system_image_guid(mdev, 6031 &mpi->sys_image_guid); 6032 if (err) { 6033 kfree(mpi); 6034 return NULL; 6035 } 6036 6037 mutex_lock(&mlx5_ib_multiport_mutex); 6038 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) { 6039 if (dev->sys_image_guid == mpi->sys_image_guid) 6040 bound = mlx5_ib_bind_slave_port(dev, mpi); 6041 6042 if (bound) { 6043 rdma_roce_rescan_device(&dev->ib_dev); 6044 break; 6045 } 6046 } 6047 6048 if (!bound) { 6049 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 6050 dev_dbg(&mdev->pdev->dev, "no suitable IB device found to bind to, added to unaffiliated list.\n"); 6051 } else { 6052 mlx5_ib_dbg(dev, "bound port %u\n", port_num + 1); 6053 } 6054 mutex_unlock(&mlx5_ib_multiport_mutex); 6055 6056 return mpi; 6057 } 6058 6059 static void *mlx5_ib_add(struct mlx5_core_dev *mdev) 6060 { 6061 enum rdma_link_layer ll; 6062 struct mlx5_ib_dev *dev; 6063 int port_type_cap; 6064 6065 printk_once(KERN_INFO "%s", mlx5_version); 6066 6067 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 6068 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 6069 6070 if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET) { 6071 u8 port_num = mlx5_core_native_port_num(mdev) - 1; 6072 6073 return mlx5_ib_add_slave_port(mdev, port_num); 6074 } 6075 6076 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev)); 6077 if (!dev) 6078 return NULL; 6079 6080 dev->mdev = mdev; 6081 dev->num_ports = max(MLX5_CAP_GEN(mdev, num_ports), 6082 MLX5_CAP_GEN(mdev, num_vhca_ports)); 6083 6084 if (MLX5_VPORT_MANAGER(mdev) && 6085 mlx5_ib_eswitch_mode(mdev->priv.eswitch) == SRIOV_OFFLOADS) { 6086 dev->rep = mlx5_ib_vport_rep(mdev->priv.eswitch, 0); 6087 6088 return __mlx5_ib_add(dev, &nic_rep_profile); 6089 } 6090 6091 return __mlx5_ib_add(dev, &pf_profile); 6092 } 6093 6094 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context) 6095 { 6096 struct mlx5_ib_multiport_info *mpi; 6097 struct mlx5_ib_dev *dev; 6098 6099 if (mlx5_core_is_mp_slave(mdev)) { 6100 mpi = context; 6101 mutex_lock(&mlx5_ib_multiport_mutex); 6102 if (mpi->ibdev) 6103 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi); 6104 list_del(&mpi->list); 6105 mutex_unlock(&mlx5_ib_multiport_mutex); 6106 return; 6107 } 6108 6109 dev = context; 6110 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX); 6111 } 6112 6113 static struct mlx5_interface mlx5_ib_interface = { 6114 .add = mlx5_ib_add, 6115 .remove = mlx5_ib_remove, 6116 .event = mlx5_ib_event, 6117 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 6118 .pfault = mlx5_ib_pfault, 6119 #endif 6120 .protocol = MLX5_INTERFACE_PROTOCOL_IB, 6121 }; 6122 6123 unsigned long mlx5_ib_get_xlt_emergency_page(void) 6124 { 6125 mutex_lock(&xlt_emergency_page_mutex); 6126 return xlt_emergency_page; 6127 } 6128 6129 void mlx5_ib_put_xlt_emergency_page(void) 6130 { 6131 mutex_unlock(&xlt_emergency_page_mutex); 6132 } 6133 6134 static int __init mlx5_ib_init(void) 6135 { 6136 int err; 6137 6138 xlt_emergency_page = __get_free_page(GFP_KERNEL); 6139 if (!xlt_emergency_page) 6140 return -ENOMEM; 6141 6142 mutex_init(&xlt_emergency_page_mutex); 6143 6144 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0); 6145 if (!mlx5_ib_event_wq) { 6146 free_page(xlt_emergency_page); 6147 return -ENOMEM; 6148 } 6149 6150 mlx5_ib_odp_init(); 6151 6152 err = mlx5_register_interface(&mlx5_ib_interface); 6153 6154 return err; 6155 } 6156 6157 static void __exit mlx5_ib_cleanup(void) 6158 { 6159 mlx5_unregister_interface(&mlx5_ib_interface); 6160 destroy_workqueue(mlx5_ib_event_wq); 6161 mutex_destroy(&xlt_emergency_page_mutex); 6162 free_page(xlt_emergency_page); 6163 } 6164 6165 module_init(mlx5_ib_init); 6166 module_exit(mlx5_ib_cleanup); 6167