1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/debugfs.h> 34 #include <linux/highmem.h> 35 #include <linux/module.h> 36 #include <linux/init.h> 37 #include <linux/errno.h> 38 #include <linux/pci.h> 39 #include <linux/dma-mapping.h> 40 #include <linux/slab.h> 41 #include <linux/bitmap.h> 42 #if defined(CONFIG_X86) 43 #include <asm/pat.h> 44 #endif 45 #include <linux/sched.h> 46 #include <linux/sched/mm.h> 47 #include <linux/sched/task.h> 48 #include <linux/delay.h> 49 #include <rdma/ib_user_verbs.h> 50 #include <rdma/ib_addr.h> 51 #include <rdma/ib_cache.h> 52 #include <linux/mlx5/port.h> 53 #include <linux/mlx5/vport.h> 54 #include <linux/mlx5/fs.h> 55 #include <linux/mlx5/fs_helpers.h> 56 #include <linux/list.h> 57 #include <rdma/ib_smi.h> 58 #include <rdma/ib_umem.h> 59 #include <linux/in.h> 60 #include <linux/etherdevice.h> 61 #include "mlx5_ib.h" 62 #include "ib_rep.h" 63 #include "cmd.h" 64 #include <linux/mlx5/fs_helpers.h> 65 #include <linux/mlx5/accel.h> 66 #include <rdma/uverbs_std_types.h> 67 #include <rdma/mlx5_user_ioctl_verbs.h> 68 #include <rdma/mlx5_user_ioctl_cmds.h> 69 70 #define UVERBS_MODULE_NAME mlx5_ib 71 #include <rdma/uverbs_named_ioctl.h> 72 73 #define DRIVER_NAME "mlx5_ib" 74 #define DRIVER_VERSION "5.0-0" 75 76 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 77 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver"); 78 MODULE_LICENSE("Dual BSD/GPL"); 79 80 static char mlx5_version[] = 81 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v" 82 DRIVER_VERSION "\n"; 83 84 struct mlx5_ib_event_work { 85 struct work_struct work; 86 struct mlx5_core_dev *dev; 87 void *context; 88 enum mlx5_dev_event event; 89 unsigned long param; 90 }; 91 92 enum { 93 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 94 }; 95 96 static struct workqueue_struct *mlx5_ib_event_wq; 97 static LIST_HEAD(mlx5_ib_unaffiliated_port_list); 98 static LIST_HEAD(mlx5_ib_dev_list); 99 /* 100 * This mutex should be held when accessing either of the above lists 101 */ 102 static DEFINE_MUTEX(mlx5_ib_multiport_mutex); 103 104 /* We can't use an array for xlt_emergency_page because dma_map_single 105 * doesn't work on kernel modules memory 106 */ 107 static unsigned long xlt_emergency_page; 108 static struct mutex xlt_emergency_page_mutex; 109 110 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi) 111 { 112 struct mlx5_ib_dev *dev; 113 114 mutex_lock(&mlx5_ib_multiport_mutex); 115 dev = mpi->ibdev; 116 mutex_unlock(&mlx5_ib_multiport_mutex); 117 return dev; 118 } 119 120 static enum rdma_link_layer 121 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 122 { 123 switch (port_type_cap) { 124 case MLX5_CAP_PORT_TYPE_IB: 125 return IB_LINK_LAYER_INFINIBAND; 126 case MLX5_CAP_PORT_TYPE_ETH: 127 return IB_LINK_LAYER_ETHERNET; 128 default: 129 return IB_LINK_LAYER_UNSPECIFIED; 130 } 131 } 132 133 static enum rdma_link_layer 134 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num) 135 { 136 struct mlx5_ib_dev *dev = to_mdev(device); 137 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 138 139 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 140 } 141 142 static int get_port_state(struct ib_device *ibdev, 143 u8 port_num, 144 enum ib_port_state *state) 145 { 146 struct ib_port_attr attr; 147 int ret; 148 149 memset(&attr, 0, sizeof(attr)); 150 ret = ibdev->query_port(ibdev, port_num, &attr); 151 if (!ret) 152 *state = attr.state; 153 return ret; 154 } 155 156 static int mlx5_netdev_event(struct notifier_block *this, 157 unsigned long event, void *ptr) 158 { 159 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb); 160 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 161 u8 port_num = roce->native_port_num; 162 struct mlx5_core_dev *mdev; 163 struct mlx5_ib_dev *ibdev; 164 165 ibdev = roce->dev; 166 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 167 if (!mdev) 168 return NOTIFY_DONE; 169 170 switch (event) { 171 case NETDEV_REGISTER: 172 case NETDEV_UNREGISTER: 173 write_lock(&roce->netdev_lock); 174 if (ibdev->rep) { 175 struct mlx5_eswitch *esw = ibdev->mdev->priv.eswitch; 176 struct net_device *rep_ndev; 177 178 rep_ndev = mlx5_ib_get_rep_netdev(esw, 179 ibdev->rep->vport); 180 if (rep_ndev == ndev) 181 roce->netdev = (event == NETDEV_UNREGISTER) ? 182 NULL : ndev; 183 } else if (ndev->dev.parent == &ibdev->mdev->pdev->dev) { 184 roce->netdev = (event == NETDEV_UNREGISTER) ? 185 NULL : ndev; 186 } 187 write_unlock(&roce->netdev_lock); 188 break; 189 190 case NETDEV_CHANGE: 191 case NETDEV_UP: 192 case NETDEV_DOWN: { 193 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev); 194 struct net_device *upper = NULL; 195 196 if (lag_ndev) { 197 upper = netdev_master_upper_dev_get(lag_ndev); 198 dev_put(lag_ndev); 199 } 200 201 if ((upper == ndev || (!upper && ndev == roce->netdev)) 202 && ibdev->ib_active) { 203 struct ib_event ibev = { }; 204 enum ib_port_state port_state; 205 206 if (get_port_state(&ibdev->ib_dev, port_num, 207 &port_state)) 208 goto done; 209 210 if (roce->last_port_state == port_state) 211 goto done; 212 213 roce->last_port_state = port_state; 214 ibev.device = &ibdev->ib_dev; 215 if (port_state == IB_PORT_DOWN) 216 ibev.event = IB_EVENT_PORT_ERR; 217 else if (port_state == IB_PORT_ACTIVE) 218 ibev.event = IB_EVENT_PORT_ACTIVE; 219 else 220 goto done; 221 222 ibev.element.port_num = port_num; 223 ib_dispatch_event(&ibev); 224 } 225 break; 226 } 227 228 default: 229 break; 230 } 231 done: 232 mlx5_ib_put_native_port_mdev(ibdev, port_num); 233 return NOTIFY_DONE; 234 } 235 236 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device, 237 u8 port_num) 238 { 239 struct mlx5_ib_dev *ibdev = to_mdev(device); 240 struct net_device *ndev; 241 struct mlx5_core_dev *mdev; 242 243 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 244 if (!mdev) 245 return NULL; 246 247 ndev = mlx5_lag_get_roce_netdev(mdev); 248 if (ndev) 249 goto out; 250 251 /* Ensure ndev does not disappear before we invoke dev_hold() 252 */ 253 read_lock(&ibdev->roce[port_num - 1].netdev_lock); 254 ndev = ibdev->roce[port_num - 1].netdev; 255 if (ndev) 256 dev_hold(ndev); 257 read_unlock(&ibdev->roce[port_num - 1].netdev_lock); 258 259 out: 260 mlx5_ib_put_native_port_mdev(ibdev, port_num); 261 return ndev; 262 } 263 264 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev, 265 u8 ib_port_num, 266 u8 *native_port_num) 267 { 268 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 269 ib_port_num); 270 struct mlx5_core_dev *mdev = NULL; 271 struct mlx5_ib_multiport_info *mpi; 272 struct mlx5_ib_port *port; 273 274 if (!mlx5_core_mp_enabled(ibdev->mdev) || 275 ll != IB_LINK_LAYER_ETHERNET) { 276 if (native_port_num) 277 *native_port_num = ib_port_num; 278 return ibdev->mdev; 279 } 280 281 if (native_port_num) 282 *native_port_num = 1; 283 284 port = &ibdev->port[ib_port_num - 1]; 285 if (!port) 286 return NULL; 287 288 spin_lock(&port->mp.mpi_lock); 289 mpi = ibdev->port[ib_port_num - 1].mp.mpi; 290 if (mpi && !mpi->unaffiliate) { 291 mdev = mpi->mdev; 292 /* If it's the master no need to refcount, it'll exist 293 * as long as the ib_dev exists. 294 */ 295 if (!mpi->is_master) 296 mpi->mdev_refcnt++; 297 } 298 spin_unlock(&port->mp.mpi_lock); 299 300 return mdev; 301 } 302 303 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num) 304 { 305 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 306 port_num); 307 struct mlx5_ib_multiport_info *mpi; 308 struct mlx5_ib_port *port; 309 310 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 311 return; 312 313 port = &ibdev->port[port_num - 1]; 314 315 spin_lock(&port->mp.mpi_lock); 316 mpi = ibdev->port[port_num - 1].mp.mpi; 317 if (mpi->is_master) 318 goto out; 319 320 mpi->mdev_refcnt--; 321 if (mpi->unaffiliate) 322 complete(&mpi->unref_comp); 323 out: 324 spin_unlock(&port->mp.mpi_lock); 325 } 326 327 static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed, 328 u8 *active_width) 329 { 330 switch (eth_proto_oper) { 331 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII): 332 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX): 333 case MLX5E_PROT_MASK(MLX5E_100BASE_TX): 334 case MLX5E_PROT_MASK(MLX5E_1000BASE_T): 335 *active_width = IB_WIDTH_1X; 336 *active_speed = IB_SPEED_SDR; 337 break; 338 case MLX5E_PROT_MASK(MLX5E_10GBASE_T): 339 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4): 340 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4): 341 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR): 342 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR): 343 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR): 344 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER): 345 *active_width = IB_WIDTH_1X; 346 *active_speed = IB_SPEED_QDR; 347 break; 348 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR): 349 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR): 350 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR): 351 *active_width = IB_WIDTH_1X; 352 *active_speed = IB_SPEED_EDR; 353 break; 354 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4): 355 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4): 356 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4): 357 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4): 358 *active_width = IB_WIDTH_4X; 359 *active_speed = IB_SPEED_QDR; 360 break; 361 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2): 362 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2): 363 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2): 364 *active_width = IB_WIDTH_1X; 365 *active_speed = IB_SPEED_HDR; 366 break; 367 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4): 368 *active_width = IB_WIDTH_4X; 369 *active_speed = IB_SPEED_FDR; 370 break; 371 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4): 372 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4): 373 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4): 374 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4): 375 *active_width = IB_WIDTH_4X; 376 *active_speed = IB_SPEED_EDR; 377 break; 378 default: 379 return -EINVAL; 380 } 381 382 return 0; 383 } 384 385 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num, 386 struct ib_port_attr *props) 387 { 388 struct mlx5_ib_dev *dev = to_mdev(device); 389 struct mlx5_core_dev *mdev; 390 struct net_device *ndev, *upper; 391 enum ib_mtu ndev_ib_mtu; 392 bool put_mdev = true; 393 u16 qkey_viol_cntr; 394 u32 eth_prot_oper; 395 u8 mdev_port_num; 396 int err; 397 398 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 399 if (!mdev) { 400 /* This means the port isn't affiliated yet. Get the 401 * info for the master port instead. 402 */ 403 put_mdev = false; 404 mdev = dev->mdev; 405 mdev_port_num = 1; 406 port_num = 1; 407 } 408 409 /* Possible bad flows are checked before filling out props so in case 410 * of an error it will still be zeroed out. 411 */ 412 err = mlx5_query_port_eth_proto_oper(mdev, ð_prot_oper, 413 mdev_port_num); 414 if (err) 415 goto out; 416 417 props->active_width = IB_WIDTH_4X; 418 props->active_speed = IB_SPEED_QDR; 419 420 translate_eth_proto_oper(eth_prot_oper, &props->active_speed, 421 &props->active_width); 422 423 props->port_cap_flags |= IB_PORT_CM_SUP; 424 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS; 425 426 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 427 roce_address_table_size); 428 props->max_mtu = IB_MTU_4096; 429 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 430 props->pkey_tbl_len = 1; 431 props->state = IB_PORT_DOWN; 432 props->phys_state = 3; 433 434 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr); 435 props->qkey_viol_cntr = qkey_viol_cntr; 436 437 /* If this is a stub query for an unaffiliated port stop here */ 438 if (!put_mdev) 439 goto out; 440 441 ndev = mlx5_ib_get_netdev(device, port_num); 442 if (!ndev) 443 goto out; 444 445 if (mlx5_lag_is_active(dev->mdev)) { 446 rcu_read_lock(); 447 upper = netdev_master_upper_dev_get_rcu(ndev); 448 if (upper) { 449 dev_put(ndev); 450 ndev = upper; 451 dev_hold(ndev); 452 } 453 rcu_read_unlock(); 454 } 455 456 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 457 props->state = IB_PORT_ACTIVE; 458 props->phys_state = 5; 459 } 460 461 ndev_ib_mtu = iboe_get_mtu(ndev->mtu); 462 463 dev_put(ndev); 464 465 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 466 out: 467 if (put_mdev) 468 mlx5_ib_put_native_port_mdev(dev, port_num); 469 return err; 470 } 471 472 static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num, 473 unsigned int index, const union ib_gid *gid, 474 const struct ib_gid_attr *attr) 475 { 476 enum ib_gid_type gid_type = IB_GID_TYPE_IB; 477 u8 roce_version = 0; 478 u8 roce_l3_type = 0; 479 bool vlan = false; 480 u8 mac[ETH_ALEN]; 481 u16 vlan_id = 0; 482 483 if (gid) { 484 gid_type = attr->gid_type; 485 ether_addr_copy(mac, attr->ndev->dev_addr); 486 487 if (is_vlan_dev(attr->ndev)) { 488 vlan = true; 489 vlan_id = vlan_dev_vlan_id(attr->ndev); 490 } 491 } 492 493 switch (gid_type) { 494 case IB_GID_TYPE_IB: 495 roce_version = MLX5_ROCE_VERSION_1; 496 break; 497 case IB_GID_TYPE_ROCE_UDP_ENCAP: 498 roce_version = MLX5_ROCE_VERSION_2; 499 if (ipv6_addr_v4mapped((void *)gid)) 500 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4; 501 else 502 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6; 503 break; 504 505 default: 506 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type); 507 } 508 509 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version, 510 roce_l3_type, gid->raw, mac, vlan, 511 vlan_id, port_num); 512 } 513 514 static int mlx5_ib_add_gid(const union ib_gid *gid, 515 const struct ib_gid_attr *attr, 516 __always_unused void **context) 517 { 518 return set_roce_addr(to_mdev(attr->device), attr->port_num, 519 attr->index, gid, attr); 520 } 521 522 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr, 523 __always_unused void **context) 524 { 525 return set_roce_addr(to_mdev(attr->device), attr->port_num, 526 attr->index, NULL, NULL); 527 } 528 529 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num, 530 int index) 531 { 532 struct ib_gid_attr attr; 533 union ib_gid gid; 534 535 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr)) 536 return 0; 537 538 dev_put(attr.ndev); 539 540 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 541 return 0; 542 543 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 544 } 545 546 int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num, 547 int index, enum ib_gid_type *gid_type) 548 { 549 struct ib_gid_attr attr; 550 union ib_gid gid; 551 int ret; 552 553 ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr); 554 if (ret) 555 return ret; 556 557 dev_put(attr.ndev); 558 559 *gid_type = attr.gid_type; 560 561 return 0; 562 } 563 564 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 565 { 566 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 567 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 568 return 0; 569 } 570 571 enum { 572 MLX5_VPORT_ACCESS_METHOD_MAD, 573 MLX5_VPORT_ACCESS_METHOD_HCA, 574 MLX5_VPORT_ACCESS_METHOD_NIC, 575 }; 576 577 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 578 { 579 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 580 return MLX5_VPORT_ACCESS_METHOD_MAD; 581 582 if (mlx5_ib_port_link_layer(ibdev, 1) == 583 IB_LINK_LAYER_ETHERNET) 584 return MLX5_VPORT_ACCESS_METHOD_NIC; 585 586 return MLX5_VPORT_ACCESS_METHOD_HCA; 587 } 588 589 static void get_atomic_caps(struct mlx5_ib_dev *dev, 590 u8 atomic_size_qp, 591 struct ib_device_attr *props) 592 { 593 u8 tmp; 594 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 595 u8 atomic_req_8B_endianness_mode = 596 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode); 597 598 /* Check if HW supports 8 bytes standard atomic operations and capable 599 * of host endianness respond 600 */ 601 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 602 if (((atomic_operations & tmp) == tmp) && 603 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 604 (atomic_req_8B_endianness_mode)) { 605 props->atomic_cap = IB_ATOMIC_HCA; 606 } else { 607 props->atomic_cap = IB_ATOMIC_NONE; 608 } 609 } 610 611 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev, 612 struct ib_device_attr *props) 613 { 614 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 615 616 get_atomic_caps(dev, atomic_size_qp, props); 617 } 618 619 static void get_atomic_caps_dc(struct mlx5_ib_dev *dev, 620 struct ib_device_attr *props) 621 { 622 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc); 623 624 get_atomic_caps(dev, atomic_size_qp, props); 625 } 626 627 bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev) 628 { 629 struct ib_device_attr props = {}; 630 631 get_atomic_caps_dc(dev, &props); 632 return (props.atomic_cap == IB_ATOMIC_HCA) ? true : false; 633 } 634 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 635 __be64 *sys_image_guid) 636 { 637 struct mlx5_ib_dev *dev = to_mdev(ibdev); 638 struct mlx5_core_dev *mdev = dev->mdev; 639 u64 tmp; 640 int err; 641 642 switch (mlx5_get_vport_access_method(ibdev)) { 643 case MLX5_VPORT_ACCESS_METHOD_MAD: 644 return mlx5_query_mad_ifc_system_image_guid(ibdev, 645 sys_image_guid); 646 647 case MLX5_VPORT_ACCESS_METHOD_HCA: 648 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 649 break; 650 651 case MLX5_VPORT_ACCESS_METHOD_NIC: 652 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 653 break; 654 655 default: 656 return -EINVAL; 657 } 658 659 if (!err) 660 *sys_image_guid = cpu_to_be64(tmp); 661 662 return err; 663 664 } 665 666 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 667 u16 *max_pkeys) 668 { 669 struct mlx5_ib_dev *dev = to_mdev(ibdev); 670 struct mlx5_core_dev *mdev = dev->mdev; 671 672 switch (mlx5_get_vport_access_method(ibdev)) { 673 case MLX5_VPORT_ACCESS_METHOD_MAD: 674 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 675 676 case MLX5_VPORT_ACCESS_METHOD_HCA: 677 case MLX5_VPORT_ACCESS_METHOD_NIC: 678 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 679 pkey_table_size)); 680 return 0; 681 682 default: 683 return -EINVAL; 684 } 685 } 686 687 static int mlx5_query_vendor_id(struct ib_device *ibdev, 688 u32 *vendor_id) 689 { 690 struct mlx5_ib_dev *dev = to_mdev(ibdev); 691 692 switch (mlx5_get_vport_access_method(ibdev)) { 693 case MLX5_VPORT_ACCESS_METHOD_MAD: 694 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 695 696 case MLX5_VPORT_ACCESS_METHOD_HCA: 697 case MLX5_VPORT_ACCESS_METHOD_NIC: 698 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 699 700 default: 701 return -EINVAL; 702 } 703 } 704 705 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 706 __be64 *node_guid) 707 { 708 u64 tmp; 709 int err; 710 711 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 712 case MLX5_VPORT_ACCESS_METHOD_MAD: 713 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 714 715 case MLX5_VPORT_ACCESS_METHOD_HCA: 716 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 717 break; 718 719 case MLX5_VPORT_ACCESS_METHOD_NIC: 720 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 721 break; 722 723 default: 724 return -EINVAL; 725 } 726 727 if (!err) 728 *node_guid = cpu_to_be64(tmp); 729 730 return err; 731 } 732 733 struct mlx5_reg_node_desc { 734 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 735 }; 736 737 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 738 { 739 struct mlx5_reg_node_desc in; 740 741 if (mlx5_use_mad_ifc(dev)) 742 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 743 744 memset(&in, 0, sizeof(in)); 745 746 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 747 sizeof(struct mlx5_reg_node_desc), 748 MLX5_REG_NODE_DESC, 0, 0); 749 } 750 751 static int mlx5_ib_query_device(struct ib_device *ibdev, 752 struct ib_device_attr *props, 753 struct ib_udata *uhw) 754 { 755 struct mlx5_ib_dev *dev = to_mdev(ibdev); 756 struct mlx5_core_dev *mdev = dev->mdev; 757 int err = -ENOMEM; 758 int max_sq_desc; 759 int max_rq_sg; 760 int max_sq_sg; 761 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 762 bool raw_support = !mlx5_core_mp_enabled(mdev); 763 struct mlx5_ib_query_device_resp resp = {}; 764 size_t resp_len; 765 u64 max_tso; 766 767 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 768 if (uhw->outlen && uhw->outlen < resp_len) 769 return -EINVAL; 770 else 771 resp.response_length = resp_len; 772 773 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) 774 return -EINVAL; 775 776 memset(props, 0, sizeof(*props)); 777 err = mlx5_query_system_image_guid(ibdev, 778 &props->sys_image_guid); 779 if (err) 780 return err; 781 782 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys); 783 if (err) 784 return err; 785 786 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 787 if (err) 788 return err; 789 790 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 791 (fw_rev_min(dev->mdev) << 16) | 792 fw_rev_sub(dev->mdev); 793 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 794 IB_DEVICE_PORT_ACTIVE_EVENT | 795 IB_DEVICE_SYS_IMAGE_GUID | 796 IB_DEVICE_RC_RNR_NAK_GEN; 797 798 if (MLX5_CAP_GEN(mdev, pkv)) 799 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 800 if (MLX5_CAP_GEN(mdev, qkv)) 801 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 802 if (MLX5_CAP_GEN(mdev, apm)) 803 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 804 if (MLX5_CAP_GEN(mdev, xrc)) 805 props->device_cap_flags |= IB_DEVICE_XRC; 806 if (MLX5_CAP_GEN(mdev, imaicl)) { 807 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 808 IB_DEVICE_MEM_WINDOW_TYPE_2B; 809 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 810 /* We support 'Gappy' memory registration too */ 811 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG; 812 } 813 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 814 if (MLX5_CAP_GEN(mdev, sho)) { 815 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER; 816 /* At this stage no support for signature handover */ 817 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 818 IB_PROT_T10DIF_TYPE_2 | 819 IB_PROT_T10DIF_TYPE_3; 820 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 821 IB_GUARD_T10DIF_CSUM; 822 } 823 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 824 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 825 826 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) { 827 if (MLX5_CAP_ETH(mdev, csum_cap)) { 828 /* Legacy bit to support old userspace libraries */ 829 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 830 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM; 831 } 832 833 if (MLX5_CAP_ETH(dev->mdev, vlan_cap)) 834 props->raw_packet_caps |= 835 IB_RAW_PACKET_CAP_CVLAN_STRIPPING; 836 837 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) { 838 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 839 if (max_tso) { 840 resp.tso_caps.max_tso = 1 << max_tso; 841 resp.tso_caps.supported_qpts |= 842 1 << IB_QPT_RAW_PACKET; 843 resp.response_length += sizeof(resp.tso_caps); 844 } 845 } 846 847 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) { 848 resp.rss_caps.rx_hash_function = 849 MLX5_RX_HASH_FUNC_TOEPLITZ; 850 resp.rss_caps.rx_hash_fields_mask = 851 MLX5_RX_HASH_SRC_IPV4 | 852 MLX5_RX_HASH_DST_IPV4 | 853 MLX5_RX_HASH_SRC_IPV6 | 854 MLX5_RX_HASH_DST_IPV6 | 855 MLX5_RX_HASH_SRC_PORT_TCP | 856 MLX5_RX_HASH_DST_PORT_TCP | 857 MLX5_RX_HASH_SRC_PORT_UDP | 858 MLX5_RX_HASH_DST_PORT_UDP | 859 MLX5_RX_HASH_INNER; 860 if (mlx5_accel_ipsec_device_caps(dev->mdev) & 861 MLX5_ACCEL_IPSEC_CAP_DEVICE) 862 resp.rss_caps.rx_hash_fields_mask |= 863 MLX5_RX_HASH_IPSEC_SPI; 864 resp.response_length += sizeof(resp.rss_caps); 865 } 866 } else { 867 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) 868 resp.response_length += sizeof(resp.tso_caps); 869 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) 870 resp.response_length += sizeof(resp.rss_caps); 871 } 872 873 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 874 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 875 props->device_cap_flags |= IB_DEVICE_UD_TSO; 876 } 877 878 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) && 879 MLX5_CAP_GEN(dev->mdev, general_notification_event) && 880 raw_support) 881 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP; 882 883 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 884 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap)) 885 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 886 887 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 888 MLX5_CAP_ETH(dev->mdev, scatter_fcs) && 889 raw_support) { 890 /* Legacy bit to support old userspace libraries */ 891 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 892 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; 893 } 894 895 if (MLX5_CAP_DEV_MEM(mdev, memic)) { 896 props->max_dm_size = 897 MLX5_CAP_DEV_MEM(mdev, max_memic_size); 898 } 899 900 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 901 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 902 903 if (MLX5_CAP_GEN(mdev, end_pad)) 904 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING; 905 906 props->vendor_part_id = mdev->pdev->device; 907 props->hw_ver = mdev->pdev->revision; 908 909 props->max_mr_size = ~0ull; 910 props->page_size_cap = ~(min_page_size - 1); 911 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 912 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 913 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 914 sizeof(struct mlx5_wqe_data_seg); 915 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512); 916 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) - 917 sizeof(struct mlx5_wqe_raddr_seg)) / 918 sizeof(struct mlx5_wqe_data_seg); 919 props->max_sge = min(max_rq_sg, max_sq_sg); 920 props->max_sge_rd = MLX5_MAX_SGE_RD; 921 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 922 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 923 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 924 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 925 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 926 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 927 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 928 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 929 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 930 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 931 props->max_srq_sge = max_rq_sg - 1; 932 props->max_fast_reg_page_list_len = 933 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 934 get_atomic_caps_qp(dev, props); 935 props->masked_atomic_cap = IB_ATOMIC_NONE; 936 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 937 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 938 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 939 props->max_mcast_grp; 940 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */ 941 props->max_ah = INT_MAX; 942 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 943 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 944 945 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 946 if (MLX5_CAP_GEN(mdev, pg)) 947 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING; 948 props->odp_caps = dev->odp_caps; 949 #endif 950 951 if (MLX5_CAP_GEN(mdev, cd)) 952 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL; 953 954 if (!mlx5_core_is_pf(mdev)) 955 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION; 956 957 if (mlx5_ib_port_link_layer(ibdev, 1) == 958 IB_LINK_LAYER_ETHERNET && raw_support) { 959 props->rss_caps.max_rwq_indirection_tables = 960 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 961 props->rss_caps.max_rwq_indirection_table_size = 962 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 963 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 964 props->max_wq_type_rq = 965 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 966 } 967 968 if (MLX5_CAP_GEN(mdev, tag_matching)) { 969 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE; 970 props->tm_caps.max_num_tags = 971 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1; 972 props->tm_caps.flags = IB_TM_CAP_RC; 973 props->tm_caps.max_ops = 974 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 975 props->tm_caps.max_sge = MLX5_TM_MAX_SGE; 976 } 977 978 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) { 979 props->cq_caps.max_cq_moderation_count = 980 MLX5_MAX_CQ_COUNT; 981 props->cq_caps.max_cq_moderation_period = 982 MLX5_MAX_CQ_PERIOD; 983 } 984 985 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) { 986 resp.cqe_comp_caps.max_num = 987 MLX5_CAP_GEN(dev->mdev, cqe_compression) ? 988 MLX5_CAP_GEN(dev->mdev, cqe_compression_max_num) : 0; 989 resp.cqe_comp_caps.supported_format = 990 MLX5_IB_CQE_RES_FORMAT_HASH | 991 MLX5_IB_CQE_RES_FORMAT_CSUM; 992 resp.response_length += sizeof(resp.cqe_comp_caps); 993 } 994 995 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen) && 996 raw_support) { 997 if (MLX5_CAP_QOS(mdev, packet_pacing) && 998 MLX5_CAP_GEN(mdev, qos)) { 999 resp.packet_pacing_caps.qp_rate_limit_max = 1000 MLX5_CAP_QOS(mdev, packet_pacing_max_rate); 1001 resp.packet_pacing_caps.qp_rate_limit_min = 1002 MLX5_CAP_QOS(mdev, packet_pacing_min_rate); 1003 resp.packet_pacing_caps.supported_qpts |= 1004 1 << IB_QPT_RAW_PACKET; 1005 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) && 1006 MLX5_CAP_QOS(mdev, packet_pacing_typical_size)) 1007 resp.packet_pacing_caps.cap_flags |= 1008 MLX5_IB_PP_SUPPORT_BURST; 1009 } 1010 resp.response_length += sizeof(resp.packet_pacing_caps); 1011 } 1012 1013 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes, 1014 uhw->outlen)) { 1015 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe)) 1016 resp.mlx5_ib_support_multi_pkt_send_wqes = 1017 MLX5_IB_ALLOW_MPW; 1018 1019 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe)) 1020 resp.mlx5_ib_support_multi_pkt_send_wqes |= 1021 MLX5_IB_SUPPORT_EMPW; 1022 1023 resp.response_length += 1024 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes); 1025 } 1026 1027 if (field_avail(typeof(resp), flags, uhw->outlen)) { 1028 resp.response_length += sizeof(resp.flags); 1029 1030 if (MLX5_CAP_GEN(mdev, cqe_compression_128)) 1031 resp.flags |= 1032 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP; 1033 1034 if (MLX5_CAP_GEN(mdev, cqe_128_always)) 1035 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD; 1036 } 1037 1038 if (field_avail(typeof(resp), sw_parsing_caps, 1039 uhw->outlen)) { 1040 resp.response_length += sizeof(resp.sw_parsing_caps); 1041 if (MLX5_CAP_ETH(mdev, swp)) { 1042 resp.sw_parsing_caps.sw_parsing_offloads |= 1043 MLX5_IB_SW_PARSING; 1044 1045 if (MLX5_CAP_ETH(mdev, swp_csum)) 1046 resp.sw_parsing_caps.sw_parsing_offloads |= 1047 MLX5_IB_SW_PARSING_CSUM; 1048 1049 if (MLX5_CAP_ETH(mdev, swp_lso)) 1050 resp.sw_parsing_caps.sw_parsing_offloads |= 1051 MLX5_IB_SW_PARSING_LSO; 1052 1053 if (resp.sw_parsing_caps.sw_parsing_offloads) 1054 resp.sw_parsing_caps.supported_qpts = 1055 BIT(IB_QPT_RAW_PACKET); 1056 } 1057 } 1058 1059 if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen) && 1060 raw_support) { 1061 resp.response_length += sizeof(resp.striding_rq_caps); 1062 if (MLX5_CAP_GEN(mdev, striding_rq)) { 1063 resp.striding_rq_caps.min_single_stride_log_num_of_bytes = 1064 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES; 1065 resp.striding_rq_caps.max_single_stride_log_num_of_bytes = 1066 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES; 1067 resp.striding_rq_caps.min_single_wqe_log_num_of_strides = 1068 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1069 resp.striding_rq_caps.max_single_wqe_log_num_of_strides = 1070 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES; 1071 resp.striding_rq_caps.supported_qpts = 1072 BIT(IB_QPT_RAW_PACKET); 1073 } 1074 } 1075 1076 if (field_avail(typeof(resp), tunnel_offloads_caps, 1077 uhw->outlen)) { 1078 resp.response_length += sizeof(resp.tunnel_offloads_caps); 1079 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan)) 1080 resp.tunnel_offloads_caps |= 1081 MLX5_IB_TUNNELED_OFFLOADS_VXLAN; 1082 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx)) 1083 resp.tunnel_offloads_caps |= 1084 MLX5_IB_TUNNELED_OFFLOADS_GENEVE; 1085 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) 1086 resp.tunnel_offloads_caps |= 1087 MLX5_IB_TUNNELED_OFFLOADS_GRE; 1088 } 1089 1090 if (uhw->outlen) { 1091 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 1092 1093 if (err) 1094 return err; 1095 } 1096 1097 return 0; 1098 } 1099 1100 enum mlx5_ib_width { 1101 MLX5_IB_WIDTH_1X = 1 << 0, 1102 MLX5_IB_WIDTH_2X = 1 << 1, 1103 MLX5_IB_WIDTH_4X = 1 << 2, 1104 MLX5_IB_WIDTH_8X = 1 << 3, 1105 MLX5_IB_WIDTH_12X = 1 << 4 1106 }; 1107 1108 static int translate_active_width(struct ib_device *ibdev, u8 active_width, 1109 u8 *ib_width) 1110 { 1111 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1112 int err = 0; 1113 1114 if (active_width & MLX5_IB_WIDTH_1X) { 1115 *ib_width = IB_WIDTH_1X; 1116 } else if (active_width & MLX5_IB_WIDTH_2X) { 1117 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n", 1118 (int)active_width); 1119 err = -EINVAL; 1120 } else if (active_width & MLX5_IB_WIDTH_4X) { 1121 *ib_width = IB_WIDTH_4X; 1122 } else if (active_width & MLX5_IB_WIDTH_8X) { 1123 *ib_width = IB_WIDTH_8X; 1124 } else if (active_width & MLX5_IB_WIDTH_12X) { 1125 *ib_width = IB_WIDTH_12X; 1126 } else { 1127 mlx5_ib_dbg(dev, "Invalid active_width %d\n", 1128 (int)active_width); 1129 err = -EINVAL; 1130 } 1131 1132 return err; 1133 } 1134 1135 static int mlx5_mtu_to_ib_mtu(int mtu) 1136 { 1137 switch (mtu) { 1138 case 256: return 1; 1139 case 512: return 2; 1140 case 1024: return 3; 1141 case 2048: return 4; 1142 case 4096: return 5; 1143 default: 1144 pr_warn("invalid mtu\n"); 1145 return -1; 1146 } 1147 } 1148 1149 enum ib_max_vl_num { 1150 __IB_MAX_VL_0 = 1, 1151 __IB_MAX_VL_0_1 = 2, 1152 __IB_MAX_VL_0_3 = 3, 1153 __IB_MAX_VL_0_7 = 4, 1154 __IB_MAX_VL_0_14 = 5, 1155 }; 1156 1157 enum mlx5_vl_hw_cap { 1158 MLX5_VL_HW_0 = 1, 1159 MLX5_VL_HW_0_1 = 2, 1160 MLX5_VL_HW_0_2 = 3, 1161 MLX5_VL_HW_0_3 = 4, 1162 MLX5_VL_HW_0_4 = 5, 1163 MLX5_VL_HW_0_5 = 6, 1164 MLX5_VL_HW_0_6 = 7, 1165 MLX5_VL_HW_0_7 = 8, 1166 MLX5_VL_HW_0_14 = 15 1167 }; 1168 1169 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 1170 u8 *max_vl_num) 1171 { 1172 switch (vl_hw_cap) { 1173 case MLX5_VL_HW_0: 1174 *max_vl_num = __IB_MAX_VL_0; 1175 break; 1176 case MLX5_VL_HW_0_1: 1177 *max_vl_num = __IB_MAX_VL_0_1; 1178 break; 1179 case MLX5_VL_HW_0_3: 1180 *max_vl_num = __IB_MAX_VL_0_3; 1181 break; 1182 case MLX5_VL_HW_0_7: 1183 *max_vl_num = __IB_MAX_VL_0_7; 1184 break; 1185 case MLX5_VL_HW_0_14: 1186 *max_vl_num = __IB_MAX_VL_0_14; 1187 break; 1188 1189 default: 1190 return -EINVAL; 1191 } 1192 1193 return 0; 1194 } 1195 1196 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port, 1197 struct ib_port_attr *props) 1198 { 1199 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1200 struct mlx5_core_dev *mdev = dev->mdev; 1201 struct mlx5_hca_vport_context *rep; 1202 u16 max_mtu; 1203 u16 oper_mtu; 1204 int err; 1205 u8 ib_link_width_oper; 1206 u8 vl_hw_cap; 1207 1208 rep = kzalloc(sizeof(*rep), GFP_KERNEL); 1209 if (!rep) { 1210 err = -ENOMEM; 1211 goto out; 1212 } 1213 1214 /* props being zeroed by the caller, avoid zeroing it here */ 1215 1216 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); 1217 if (err) 1218 goto out; 1219 1220 props->lid = rep->lid; 1221 props->lmc = rep->lmc; 1222 props->sm_lid = rep->sm_lid; 1223 props->sm_sl = rep->sm_sl; 1224 props->state = rep->vport_state; 1225 props->phys_state = rep->port_physical_state; 1226 props->port_cap_flags = rep->cap_mask1; 1227 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 1228 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 1229 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 1230 props->bad_pkey_cntr = rep->pkey_violation_counter; 1231 props->qkey_viol_cntr = rep->qkey_violation_counter; 1232 props->subnet_timeout = rep->subnet_timeout; 1233 props->init_type_reply = rep->init_type_reply; 1234 props->grh_required = rep->grh_required; 1235 1236 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port); 1237 if (err) 1238 goto out; 1239 1240 err = translate_active_width(ibdev, ib_link_width_oper, 1241 &props->active_width); 1242 if (err) 1243 goto out; 1244 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port); 1245 if (err) 1246 goto out; 1247 1248 mlx5_query_port_max_mtu(mdev, &max_mtu, port); 1249 1250 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); 1251 1252 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); 1253 1254 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); 1255 1256 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); 1257 if (err) 1258 goto out; 1259 1260 err = translate_max_vl_num(ibdev, vl_hw_cap, 1261 &props->max_vl_num); 1262 out: 1263 kfree(rep); 1264 return err; 1265 } 1266 1267 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 1268 struct ib_port_attr *props) 1269 { 1270 unsigned int count; 1271 int ret; 1272 1273 switch (mlx5_get_vport_access_method(ibdev)) { 1274 case MLX5_VPORT_ACCESS_METHOD_MAD: 1275 ret = mlx5_query_mad_ifc_port(ibdev, port, props); 1276 break; 1277 1278 case MLX5_VPORT_ACCESS_METHOD_HCA: 1279 ret = mlx5_query_hca_port(ibdev, port, props); 1280 break; 1281 1282 case MLX5_VPORT_ACCESS_METHOD_NIC: 1283 ret = mlx5_query_port_roce(ibdev, port, props); 1284 break; 1285 1286 default: 1287 ret = -EINVAL; 1288 } 1289 1290 if (!ret && props) { 1291 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1292 struct mlx5_core_dev *mdev; 1293 bool put_mdev = true; 1294 1295 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL); 1296 if (!mdev) { 1297 /* If the port isn't affiliated yet query the master. 1298 * The master and slave will have the same values. 1299 */ 1300 mdev = dev->mdev; 1301 port = 1; 1302 put_mdev = false; 1303 } 1304 count = mlx5_core_reserved_gids_count(mdev); 1305 if (put_mdev) 1306 mlx5_ib_put_native_port_mdev(dev, port); 1307 props->gid_tbl_len -= count; 1308 } 1309 return ret; 1310 } 1311 1312 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port, 1313 struct ib_port_attr *props) 1314 { 1315 int ret; 1316 1317 /* Only link layer == ethernet is valid for representors */ 1318 ret = mlx5_query_port_roce(ibdev, port, props); 1319 if (ret || !props) 1320 return ret; 1321 1322 /* We don't support GIDS */ 1323 props->gid_tbl_len = 0; 1324 1325 return ret; 1326 } 1327 1328 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 1329 union ib_gid *gid) 1330 { 1331 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1332 struct mlx5_core_dev *mdev = dev->mdev; 1333 1334 switch (mlx5_get_vport_access_method(ibdev)) { 1335 case MLX5_VPORT_ACCESS_METHOD_MAD: 1336 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 1337 1338 case MLX5_VPORT_ACCESS_METHOD_HCA: 1339 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); 1340 1341 default: 1342 return -EINVAL; 1343 } 1344 1345 } 1346 1347 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port, 1348 u16 index, u16 *pkey) 1349 { 1350 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1351 struct mlx5_core_dev *mdev; 1352 bool put_mdev = true; 1353 u8 mdev_port_num; 1354 int err; 1355 1356 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num); 1357 if (!mdev) { 1358 /* The port isn't affiliated yet, get the PKey from the master 1359 * port. For RoCE the PKey tables will be the same. 1360 */ 1361 put_mdev = false; 1362 mdev = dev->mdev; 1363 mdev_port_num = 1; 1364 } 1365 1366 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0, 1367 index, pkey); 1368 if (put_mdev) 1369 mlx5_ib_put_native_port_mdev(dev, port); 1370 1371 return err; 1372 } 1373 1374 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 1375 u16 *pkey) 1376 { 1377 switch (mlx5_get_vport_access_method(ibdev)) { 1378 case MLX5_VPORT_ACCESS_METHOD_MAD: 1379 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 1380 1381 case MLX5_VPORT_ACCESS_METHOD_HCA: 1382 case MLX5_VPORT_ACCESS_METHOD_NIC: 1383 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey); 1384 default: 1385 return -EINVAL; 1386 } 1387 } 1388 1389 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 1390 struct ib_device_modify *props) 1391 { 1392 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1393 struct mlx5_reg_node_desc in; 1394 struct mlx5_reg_node_desc out; 1395 int err; 1396 1397 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 1398 return -EOPNOTSUPP; 1399 1400 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 1401 return 0; 1402 1403 /* 1404 * If possible, pass node desc to FW, so it can generate 1405 * a 144 trap. If cmd fails, just ignore. 1406 */ 1407 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1408 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 1409 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 1410 if (err) 1411 return err; 1412 1413 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1414 1415 return err; 1416 } 1417 1418 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask, 1419 u32 value) 1420 { 1421 struct mlx5_hca_vport_context ctx = {}; 1422 struct mlx5_core_dev *mdev; 1423 u8 mdev_port_num; 1424 int err; 1425 1426 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 1427 if (!mdev) 1428 return -ENODEV; 1429 1430 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx); 1431 if (err) 1432 goto out; 1433 1434 if (~ctx.cap_mask1_perm & mask) { 1435 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n", 1436 mask, ctx.cap_mask1_perm); 1437 err = -EINVAL; 1438 goto out; 1439 } 1440 1441 ctx.cap_mask1 = value; 1442 ctx.cap_mask1_perm = mask; 1443 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num, 1444 0, &ctx); 1445 1446 out: 1447 mlx5_ib_put_native_port_mdev(dev, port_num); 1448 1449 return err; 1450 } 1451 1452 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, 1453 struct ib_port_modify *props) 1454 { 1455 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1456 struct ib_port_attr attr; 1457 u32 tmp; 1458 int err; 1459 u32 change_mask; 1460 u32 value; 1461 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) == 1462 IB_LINK_LAYER_INFINIBAND); 1463 1464 /* CM layer calls ib_modify_port() regardless of the link layer. For 1465 * Ethernet ports, qkey violation and Port capabilities are meaningless. 1466 */ 1467 if (!is_ib) 1468 return 0; 1469 1470 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) { 1471 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask; 1472 value = ~props->clr_port_cap_mask | props->set_port_cap_mask; 1473 return set_port_caps_atomic(dev, port, change_mask, value); 1474 } 1475 1476 mutex_lock(&dev->cap_mask_mutex); 1477 1478 err = ib_query_port(ibdev, port, &attr); 1479 if (err) 1480 goto out; 1481 1482 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 1483 ~props->clr_port_cap_mask; 1484 1485 err = mlx5_set_port_caps(dev->mdev, port, tmp); 1486 1487 out: 1488 mutex_unlock(&dev->cap_mask_mutex); 1489 return err; 1490 } 1491 1492 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps) 1493 { 1494 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n", 1495 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n"); 1496 } 1497 1498 static u16 calc_dynamic_bfregs(int uars_per_sys_page) 1499 { 1500 /* Large page with non 4k uar support might limit the dynamic size */ 1501 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096) 1502 return MLX5_MIN_DYN_BFREGS; 1503 1504 return MLX5_MAX_DYN_BFREGS; 1505 } 1506 1507 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k, 1508 struct mlx5_ib_alloc_ucontext_req_v2 *req, 1509 struct mlx5_bfreg_info *bfregi) 1510 { 1511 int uars_per_sys_page; 1512 int bfregs_per_sys_page; 1513 int ref_bfregs = req->total_num_bfregs; 1514 1515 if (req->total_num_bfregs == 0) 1516 return -EINVAL; 1517 1518 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE); 1519 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE); 1520 1521 if (req->total_num_bfregs > MLX5_MAX_BFREGS) 1522 return -ENOMEM; 1523 1524 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k); 1525 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR; 1526 /* This holds the required static allocation asked by the user */ 1527 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page); 1528 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1) 1529 return -EINVAL; 1530 1531 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page; 1532 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page); 1533 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs; 1534 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page; 1535 1536 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n", 1537 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no", 1538 lib_uar_4k ? "yes" : "no", ref_bfregs, 1539 req->total_num_bfregs, bfregi->total_num_bfregs, 1540 bfregi->num_sys_pages); 1541 1542 return 0; 1543 } 1544 1545 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1546 { 1547 struct mlx5_bfreg_info *bfregi; 1548 int err; 1549 int i; 1550 1551 bfregi = &context->bfregi; 1552 for (i = 0; i < bfregi->num_static_sys_pages; i++) { 1553 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]); 1554 if (err) 1555 goto error; 1556 1557 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]); 1558 } 1559 1560 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++) 1561 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX; 1562 1563 return 0; 1564 1565 error: 1566 for (--i; i >= 0; i--) 1567 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i])) 1568 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1569 1570 return err; 1571 } 1572 1573 static int deallocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1574 { 1575 struct mlx5_bfreg_info *bfregi; 1576 int err; 1577 int i; 1578 1579 bfregi = &context->bfregi; 1580 for (i = 0; i < bfregi->num_sys_pages; i++) { 1581 if (i < bfregi->num_static_sys_pages || 1582 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) { 1583 err = mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]); 1584 if (err) { 1585 mlx5_ib_warn(dev, "failed to free uar %d, err=%d\n", i, err); 1586 return err; 1587 } 1588 } 1589 } 1590 1591 return 0; 1592 } 1593 1594 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn) 1595 { 1596 int err; 1597 1598 err = mlx5_core_alloc_transport_domain(dev->mdev, tdn); 1599 if (err) 1600 return err; 1601 1602 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1603 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1604 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1605 return err; 1606 1607 mutex_lock(&dev->lb_mutex); 1608 dev->user_td++; 1609 1610 if (dev->user_td == 2) 1611 err = mlx5_nic_vport_update_local_lb(dev->mdev, true); 1612 1613 mutex_unlock(&dev->lb_mutex); 1614 return err; 1615 } 1616 1617 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn) 1618 { 1619 mlx5_core_dealloc_transport_domain(dev->mdev, tdn); 1620 1621 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1622 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1623 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1624 return; 1625 1626 mutex_lock(&dev->lb_mutex); 1627 dev->user_td--; 1628 1629 if (dev->user_td < 2) 1630 mlx5_nic_vport_update_local_lb(dev->mdev, false); 1631 1632 mutex_unlock(&dev->lb_mutex); 1633 } 1634 1635 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev, 1636 struct ib_udata *udata) 1637 { 1638 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1639 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 1640 struct mlx5_ib_alloc_ucontext_resp resp = {}; 1641 struct mlx5_core_dev *mdev = dev->mdev; 1642 struct mlx5_ib_ucontext *context; 1643 struct mlx5_bfreg_info *bfregi; 1644 int ver; 1645 int err; 1646 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 1647 max_cqe_version); 1648 bool lib_uar_4k; 1649 1650 if (!dev->ib_active) 1651 return ERR_PTR(-EAGAIN); 1652 1653 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 1654 ver = 0; 1655 else if (udata->inlen >= min_req_v2) 1656 ver = 2; 1657 else 1658 return ERR_PTR(-EINVAL); 1659 1660 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req))); 1661 if (err) 1662 return ERR_PTR(err); 1663 1664 if (req.flags) 1665 return ERR_PTR(-EINVAL); 1666 1667 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 1668 return ERR_PTR(-EOPNOTSUPP); 1669 1670 req.total_num_bfregs = ALIGN(req.total_num_bfregs, 1671 MLX5_NON_FP_BFREGS_PER_UAR); 1672 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1) 1673 return ERR_PTR(-EINVAL); 1674 1675 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 1676 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf)) 1677 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size); 1678 resp.cache_line_size = cache_line_size(); 1679 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 1680 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 1681 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1682 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1683 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 1684 resp.cqe_version = min_t(__u8, 1685 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 1686 req.max_cqe_version); 1687 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1688 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT; 1689 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1690 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1; 1691 resp.response_length = min(offsetof(typeof(resp), response_length) + 1692 sizeof(resp.response_length), udata->outlen); 1693 1694 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE) { 1695 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_EGRESS)) 1696 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM; 1697 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA) 1698 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA; 1699 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi)) 1700 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING; 1701 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN) 1702 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN; 1703 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */ 1704 } 1705 1706 context = kzalloc(sizeof(*context), GFP_KERNEL); 1707 if (!context) 1708 return ERR_PTR(-ENOMEM); 1709 1710 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR; 1711 bfregi = &context->bfregi; 1712 1713 /* updates req->total_num_bfregs */ 1714 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi); 1715 if (err) 1716 goto out_ctx; 1717 1718 mutex_init(&bfregi->lock); 1719 bfregi->lib_uar_4k = lib_uar_4k; 1720 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count), 1721 GFP_KERNEL); 1722 if (!bfregi->count) { 1723 err = -ENOMEM; 1724 goto out_ctx; 1725 } 1726 1727 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages, 1728 sizeof(*bfregi->sys_pages), 1729 GFP_KERNEL); 1730 if (!bfregi->sys_pages) { 1731 err = -ENOMEM; 1732 goto out_count; 1733 } 1734 1735 err = allocate_uars(dev, context); 1736 if (err) 1737 goto out_sys_pages; 1738 1739 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1740 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range; 1741 #endif 1742 1743 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) { 1744 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn); 1745 if (err) 1746 goto out_uars; 1747 } 1748 1749 INIT_LIST_HEAD(&context->vma_private_list); 1750 mutex_init(&context->vma_private_list_mutex); 1751 INIT_LIST_HEAD(&context->db_page_list); 1752 mutex_init(&context->db_page_mutex); 1753 1754 resp.tot_bfregs = req.total_num_bfregs; 1755 resp.num_ports = dev->num_ports; 1756 1757 if (field_avail(typeof(resp), cqe_version, udata->outlen)) 1758 resp.response_length += sizeof(resp.cqe_version); 1759 1760 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) { 1761 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 1762 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 1763 resp.response_length += sizeof(resp.cmds_supp_uhw); 1764 } 1765 1766 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) { 1767 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) { 1768 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline); 1769 resp.eth_min_inline++; 1770 } 1771 resp.response_length += sizeof(resp.eth_min_inline); 1772 } 1773 1774 if (field_avail(typeof(resp), clock_info_versions, udata->outlen)) { 1775 if (mdev->clock_info) 1776 resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1); 1777 resp.response_length += sizeof(resp.clock_info_versions); 1778 } 1779 1780 /* 1781 * We don't want to expose information from the PCI bar that is located 1782 * after 4096 bytes, so if the arch only supports larger pages, let's 1783 * pretend we don't support reading the HCA's core clock. This is also 1784 * forced by mmap function. 1785 */ 1786 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) { 1787 if (PAGE_SIZE <= 4096) { 1788 resp.comp_mask |= 1789 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 1790 resp.hca_core_clock_offset = 1791 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE; 1792 } 1793 resp.response_length += sizeof(resp.hca_core_clock_offset); 1794 } 1795 1796 if (field_avail(typeof(resp), log_uar_size, udata->outlen)) 1797 resp.response_length += sizeof(resp.log_uar_size); 1798 1799 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen)) 1800 resp.response_length += sizeof(resp.num_uars_per_page); 1801 1802 if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) { 1803 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs; 1804 resp.response_length += sizeof(resp.num_dyn_bfregs); 1805 } 1806 1807 err = ib_copy_to_udata(udata, &resp, resp.response_length); 1808 if (err) 1809 goto out_td; 1810 1811 bfregi->ver = ver; 1812 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs; 1813 context->cqe_version = resp.cqe_version; 1814 context->lib_caps = req.lib_caps; 1815 print_lib_caps(dev, context->lib_caps); 1816 1817 return &context->ibucontext; 1818 1819 out_td: 1820 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1821 mlx5_ib_dealloc_transport_domain(dev, context->tdn); 1822 1823 out_uars: 1824 deallocate_uars(dev, context); 1825 1826 out_sys_pages: 1827 kfree(bfregi->sys_pages); 1828 1829 out_count: 1830 kfree(bfregi->count); 1831 1832 out_ctx: 1833 kfree(context); 1834 1835 return ERR_PTR(err); 1836 } 1837 1838 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1839 { 1840 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1841 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1842 struct mlx5_bfreg_info *bfregi; 1843 1844 bfregi = &context->bfregi; 1845 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1846 mlx5_ib_dealloc_transport_domain(dev, context->tdn); 1847 1848 deallocate_uars(dev, context); 1849 kfree(bfregi->sys_pages); 1850 kfree(bfregi->count); 1851 kfree(context); 1852 1853 return 0; 1854 } 1855 1856 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, 1857 int uar_idx) 1858 { 1859 int fw_uars_per_page; 1860 1861 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1; 1862 1863 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + uar_idx / fw_uars_per_page; 1864 } 1865 1866 static int get_command(unsigned long offset) 1867 { 1868 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 1869 } 1870 1871 static int get_arg(unsigned long offset) 1872 { 1873 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 1874 } 1875 1876 static int get_index(unsigned long offset) 1877 { 1878 return get_arg(offset); 1879 } 1880 1881 /* Index resides in an extra byte to enable larger values than 255 */ 1882 static int get_extended_index(unsigned long offset) 1883 { 1884 return get_arg(offset) | ((offset >> 16) & 0xff) << 8; 1885 } 1886 1887 static void mlx5_ib_vma_open(struct vm_area_struct *area) 1888 { 1889 /* vma_open is called when a new VMA is created on top of our VMA. This 1890 * is done through either mremap flow or split_vma (usually due to 1891 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA, 1892 * as this VMA is strongly hardware related. Therefore we set the 1893 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from 1894 * calling us again and trying to do incorrect actions. We assume that 1895 * the original VMA size is exactly a single page, and therefore all 1896 * "splitting" operation will not happen to it. 1897 */ 1898 area->vm_ops = NULL; 1899 } 1900 1901 static void mlx5_ib_vma_close(struct vm_area_struct *area) 1902 { 1903 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data; 1904 1905 /* It's guaranteed that all VMAs opened on a FD are closed before the 1906 * file itself is closed, therefore no sync is needed with the regular 1907 * closing flow. (e.g. mlx5 ib_dealloc_ucontext) 1908 * However need a sync with accessing the vma as part of 1909 * mlx5_ib_disassociate_ucontext. 1910 * The close operation is usually called under mm->mmap_sem except when 1911 * process is exiting. 1912 * The exiting case is handled explicitly as part of 1913 * mlx5_ib_disassociate_ucontext. 1914 */ 1915 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data; 1916 1917 /* setting the vma context pointer to null in the mlx5_ib driver's 1918 * private data, to protect a race condition in 1919 * mlx5_ib_disassociate_ucontext(). 1920 */ 1921 mlx5_ib_vma_priv_data->vma = NULL; 1922 mutex_lock(mlx5_ib_vma_priv_data->vma_private_list_mutex); 1923 list_del(&mlx5_ib_vma_priv_data->list); 1924 mutex_unlock(mlx5_ib_vma_priv_data->vma_private_list_mutex); 1925 kfree(mlx5_ib_vma_priv_data); 1926 } 1927 1928 static const struct vm_operations_struct mlx5_ib_vm_ops = { 1929 .open = mlx5_ib_vma_open, 1930 .close = mlx5_ib_vma_close 1931 }; 1932 1933 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma, 1934 struct mlx5_ib_ucontext *ctx) 1935 { 1936 struct mlx5_ib_vma_private_data *vma_prv; 1937 struct list_head *vma_head = &ctx->vma_private_list; 1938 1939 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL); 1940 if (!vma_prv) 1941 return -ENOMEM; 1942 1943 vma_prv->vma = vma; 1944 vma_prv->vma_private_list_mutex = &ctx->vma_private_list_mutex; 1945 vma->vm_private_data = vma_prv; 1946 vma->vm_ops = &mlx5_ib_vm_ops; 1947 1948 mutex_lock(&ctx->vma_private_list_mutex); 1949 list_add(&vma_prv->list, vma_head); 1950 mutex_unlock(&ctx->vma_private_list_mutex); 1951 1952 return 0; 1953 } 1954 1955 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 1956 { 1957 int ret; 1958 struct vm_area_struct *vma; 1959 struct mlx5_ib_vma_private_data *vma_private, *n; 1960 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1961 struct task_struct *owning_process = NULL; 1962 struct mm_struct *owning_mm = NULL; 1963 1964 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID); 1965 if (!owning_process) 1966 return; 1967 1968 owning_mm = get_task_mm(owning_process); 1969 if (!owning_mm) { 1970 pr_info("no mm, disassociate ucontext is pending task termination\n"); 1971 while (1) { 1972 put_task_struct(owning_process); 1973 usleep_range(1000, 2000); 1974 owning_process = get_pid_task(ibcontext->tgid, 1975 PIDTYPE_PID); 1976 if (!owning_process || 1977 owning_process->state == TASK_DEAD) { 1978 pr_info("disassociate ucontext done, task was terminated\n"); 1979 /* in case task was dead need to release the 1980 * task struct. 1981 */ 1982 if (owning_process) 1983 put_task_struct(owning_process); 1984 return; 1985 } 1986 } 1987 } 1988 1989 /* need to protect from a race on closing the vma as part of 1990 * mlx5_ib_vma_close. 1991 */ 1992 down_write(&owning_mm->mmap_sem); 1993 mutex_lock(&context->vma_private_list_mutex); 1994 list_for_each_entry_safe(vma_private, n, &context->vma_private_list, 1995 list) { 1996 vma = vma_private->vma; 1997 ret = zap_vma_ptes(vma, vma->vm_start, 1998 PAGE_SIZE); 1999 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__); 2000 /* context going to be destroyed, should 2001 * not access ops any more. 2002 */ 2003 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE); 2004 vma->vm_ops = NULL; 2005 list_del(&vma_private->list); 2006 kfree(vma_private); 2007 } 2008 mutex_unlock(&context->vma_private_list_mutex); 2009 up_write(&owning_mm->mmap_sem); 2010 mmput(owning_mm); 2011 put_task_struct(owning_process); 2012 } 2013 2014 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 2015 { 2016 switch (cmd) { 2017 case MLX5_IB_MMAP_WC_PAGE: 2018 return "WC"; 2019 case MLX5_IB_MMAP_REGULAR_PAGE: 2020 return "best effort WC"; 2021 case MLX5_IB_MMAP_NC_PAGE: 2022 return "NC"; 2023 case MLX5_IB_MMAP_DEVICE_MEM: 2024 return "Device Memory"; 2025 default: 2026 return NULL; 2027 } 2028 } 2029 2030 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev, 2031 struct vm_area_struct *vma, 2032 struct mlx5_ib_ucontext *context) 2033 { 2034 phys_addr_t pfn; 2035 int err; 2036 2037 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2038 return -EINVAL; 2039 2040 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1) 2041 return -EOPNOTSUPP; 2042 2043 if (vma->vm_flags & VM_WRITE) 2044 return -EPERM; 2045 2046 if (!dev->mdev->clock_info_page) 2047 return -EOPNOTSUPP; 2048 2049 pfn = page_to_pfn(dev->mdev->clock_info_page); 2050 err = remap_pfn_range(vma, vma->vm_start, pfn, PAGE_SIZE, 2051 vma->vm_page_prot); 2052 if (err) 2053 return err; 2054 2055 mlx5_ib_dbg(dev, "mapped clock info at 0x%lx, PA 0x%llx\n", 2056 vma->vm_start, 2057 (unsigned long long)pfn << PAGE_SHIFT); 2058 2059 return mlx5_ib_set_vma_data(vma, context); 2060 } 2061 2062 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 2063 struct vm_area_struct *vma, 2064 struct mlx5_ib_ucontext *context) 2065 { 2066 struct mlx5_bfreg_info *bfregi = &context->bfregi; 2067 int err; 2068 unsigned long idx; 2069 phys_addr_t pfn, pa; 2070 pgprot_t prot; 2071 u32 bfreg_dyn_idx = 0; 2072 u32 uar_index; 2073 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC); 2074 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages : 2075 bfregi->num_static_sys_pages; 2076 2077 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2078 return -EINVAL; 2079 2080 if (dyn_uar) 2081 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages; 2082 else 2083 idx = get_index(vma->vm_pgoff); 2084 2085 if (idx >= max_valid_idx) { 2086 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n", 2087 idx, max_valid_idx); 2088 return -EINVAL; 2089 } 2090 2091 switch (cmd) { 2092 case MLX5_IB_MMAP_WC_PAGE: 2093 case MLX5_IB_MMAP_ALLOC_WC: 2094 /* Some architectures don't support WC memory */ 2095 #if defined(CONFIG_X86) 2096 if (!pat_enabled()) 2097 return -EPERM; 2098 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU))) 2099 return -EPERM; 2100 #endif 2101 /* fall through */ 2102 case MLX5_IB_MMAP_REGULAR_PAGE: 2103 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 2104 prot = pgprot_writecombine(vma->vm_page_prot); 2105 break; 2106 case MLX5_IB_MMAP_NC_PAGE: 2107 prot = pgprot_noncached(vma->vm_page_prot); 2108 break; 2109 default: 2110 return -EINVAL; 2111 } 2112 2113 if (dyn_uar) { 2114 int uars_per_page; 2115 2116 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k); 2117 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR); 2118 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) { 2119 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n", 2120 bfreg_dyn_idx, bfregi->total_num_bfregs); 2121 return -EINVAL; 2122 } 2123 2124 mutex_lock(&bfregi->lock); 2125 /* Fail if uar already allocated, first bfreg index of each 2126 * page holds its count. 2127 */ 2128 if (bfregi->count[bfreg_dyn_idx]) { 2129 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx); 2130 mutex_unlock(&bfregi->lock); 2131 return -EINVAL; 2132 } 2133 2134 bfregi->count[bfreg_dyn_idx]++; 2135 mutex_unlock(&bfregi->lock); 2136 2137 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index); 2138 if (err) { 2139 mlx5_ib_warn(dev, "UAR alloc failed\n"); 2140 goto free_bfreg; 2141 } 2142 } else { 2143 uar_index = bfregi->sys_pages[idx]; 2144 } 2145 2146 pfn = uar_index2pfn(dev, uar_index); 2147 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 2148 2149 vma->vm_page_prot = prot; 2150 err = io_remap_pfn_range(vma, vma->vm_start, pfn, 2151 PAGE_SIZE, vma->vm_page_prot); 2152 if (err) { 2153 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n", 2154 err, vma->vm_start, &pfn, mmap_cmd2str(cmd)); 2155 err = -EAGAIN; 2156 goto err; 2157 } 2158 2159 pa = pfn << PAGE_SHIFT; 2160 mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd), 2161 vma->vm_start, &pa); 2162 2163 err = mlx5_ib_set_vma_data(vma, context); 2164 if (err) 2165 goto err; 2166 2167 if (dyn_uar) 2168 bfregi->sys_pages[idx] = uar_index; 2169 return 0; 2170 2171 err: 2172 if (!dyn_uar) 2173 return err; 2174 2175 mlx5_cmd_free_uar(dev->mdev, idx); 2176 2177 free_bfreg: 2178 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx); 2179 2180 return err; 2181 } 2182 2183 static int dm_mmap(struct ib_ucontext *context, struct vm_area_struct *vma) 2184 { 2185 struct mlx5_ib_ucontext *mctx = to_mucontext(context); 2186 struct mlx5_ib_dev *dev = to_mdev(context->device); 2187 u16 page_idx = get_extended_index(vma->vm_pgoff); 2188 size_t map_size = vma->vm_end - vma->vm_start; 2189 u32 npages = map_size >> PAGE_SHIFT; 2190 phys_addr_t pfn; 2191 pgprot_t prot; 2192 2193 if (find_next_zero_bit(mctx->dm_pages, page_idx + npages, page_idx) != 2194 page_idx + npages) 2195 return -EINVAL; 2196 2197 pfn = ((pci_resource_start(dev->mdev->pdev, 0) + 2198 MLX5_CAP64_DEV_MEM(dev->mdev, memic_bar_start_addr)) >> 2199 PAGE_SHIFT) + 2200 page_idx; 2201 prot = pgprot_writecombine(vma->vm_page_prot); 2202 vma->vm_page_prot = prot; 2203 2204 if (io_remap_pfn_range(vma, vma->vm_start, pfn, map_size, 2205 vma->vm_page_prot)) 2206 return -EAGAIN; 2207 2208 return mlx5_ib_set_vma_data(vma, mctx); 2209 } 2210 2211 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 2212 { 2213 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2214 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2215 unsigned long command; 2216 phys_addr_t pfn; 2217 2218 command = get_command(vma->vm_pgoff); 2219 switch (command) { 2220 case MLX5_IB_MMAP_WC_PAGE: 2221 case MLX5_IB_MMAP_NC_PAGE: 2222 case MLX5_IB_MMAP_REGULAR_PAGE: 2223 case MLX5_IB_MMAP_ALLOC_WC: 2224 return uar_mmap(dev, command, vma, context); 2225 2226 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 2227 return -ENOSYS; 2228 2229 case MLX5_IB_MMAP_CORE_CLOCK: 2230 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2231 return -EINVAL; 2232 2233 if (vma->vm_flags & VM_WRITE) 2234 return -EPERM; 2235 2236 /* Don't expose to user-space information it shouldn't have */ 2237 if (PAGE_SIZE > 4096) 2238 return -EOPNOTSUPP; 2239 2240 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 2241 pfn = (dev->mdev->iseg_base + 2242 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 2243 PAGE_SHIFT; 2244 if (io_remap_pfn_range(vma, vma->vm_start, pfn, 2245 PAGE_SIZE, vma->vm_page_prot)) 2246 return -EAGAIN; 2247 2248 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n", 2249 vma->vm_start, 2250 (unsigned long long)pfn << PAGE_SHIFT); 2251 break; 2252 case MLX5_IB_MMAP_CLOCK_INFO: 2253 return mlx5_ib_mmap_clock_info_page(dev, vma, context); 2254 2255 case MLX5_IB_MMAP_DEVICE_MEM: 2256 return dm_mmap(ibcontext, vma); 2257 2258 default: 2259 return -EINVAL; 2260 } 2261 2262 return 0; 2263 } 2264 2265 struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev, 2266 struct ib_ucontext *context, 2267 struct ib_dm_alloc_attr *attr, 2268 struct uverbs_attr_bundle *attrs) 2269 { 2270 u64 act_size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE); 2271 struct mlx5_memic *memic = &to_mdev(ibdev)->memic; 2272 phys_addr_t memic_addr; 2273 struct mlx5_ib_dm *dm; 2274 u64 start_offset; 2275 u32 page_idx; 2276 int err; 2277 2278 dm = kzalloc(sizeof(*dm), GFP_KERNEL); 2279 if (!dm) 2280 return ERR_PTR(-ENOMEM); 2281 2282 mlx5_ib_dbg(to_mdev(ibdev), "alloc_memic req: user_length=0x%llx act_length=0x%llx log_alignment=%d\n", 2283 attr->length, act_size, attr->alignment); 2284 2285 err = mlx5_cmd_alloc_memic(memic, &memic_addr, 2286 act_size, attr->alignment); 2287 if (err) 2288 goto err_free; 2289 2290 start_offset = memic_addr & ~PAGE_MASK; 2291 page_idx = (memic_addr - pci_resource_start(memic->dev->pdev, 0) - 2292 MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >> 2293 PAGE_SHIFT; 2294 2295 err = uverbs_copy_to(attrs, 2296 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET, 2297 &start_offset, sizeof(start_offset)); 2298 if (err) 2299 goto err_dealloc; 2300 2301 err = uverbs_copy_to(attrs, 2302 MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX, 2303 &page_idx, sizeof(page_idx)); 2304 if (err) 2305 goto err_dealloc; 2306 2307 bitmap_set(to_mucontext(context)->dm_pages, page_idx, 2308 DIV_ROUND_UP(act_size, PAGE_SIZE)); 2309 2310 dm->dev_addr = memic_addr; 2311 2312 return &dm->ibdm; 2313 2314 err_dealloc: 2315 mlx5_cmd_dealloc_memic(memic, memic_addr, 2316 act_size); 2317 err_free: 2318 kfree(dm); 2319 return ERR_PTR(err); 2320 } 2321 2322 int mlx5_ib_dealloc_dm(struct ib_dm *ibdm) 2323 { 2324 struct mlx5_memic *memic = &to_mdev(ibdm->device)->memic; 2325 struct mlx5_ib_dm *dm = to_mdm(ibdm); 2326 u64 act_size = roundup(dm->ibdm.length, MLX5_MEMIC_BASE_SIZE); 2327 u32 page_idx; 2328 int ret; 2329 2330 ret = mlx5_cmd_dealloc_memic(memic, dm->dev_addr, act_size); 2331 if (ret) 2332 return ret; 2333 2334 page_idx = (dm->dev_addr - pci_resource_start(memic->dev->pdev, 0) - 2335 MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >> 2336 PAGE_SHIFT; 2337 bitmap_clear(to_mucontext(ibdm->uobject->context)->dm_pages, 2338 page_idx, 2339 DIV_ROUND_UP(act_size, PAGE_SIZE)); 2340 2341 kfree(dm); 2342 2343 return 0; 2344 } 2345 2346 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev, 2347 struct ib_ucontext *context, 2348 struct ib_udata *udata) 2349 { 2350 struct mlx5_ib_alloc_pd_resp resp; 2351 struct mlx5_ib_pd *pd; 2352 int err; 2353 2354 pd = kmalloc(sizeof(*pd), GFP_KERNEL); 2355 if (!pd) 2356 return ERR_PTR(-ENOMEM); 2357 2358 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn); 2359 if (err) { 2360 kfree(pd); 2361 return ERR_PTR(err); 2362 } 2363 2364 if (context) { 2365 resp.pdn = pd->pdn; 2366 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 2367 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn); 2368 kfree(pd); 2369 return ERR_PTR(-EFAULT); 2370 } 2371 } 2372 2373 return &pd->ibpd; 2374 } 2375 2376 static int mlx5_ib_dealloc_pd(struct ib_pd *pd) 2377 { 2378 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 2379 struct mlx5_ib_pd *mpd = to_mpd(pd); 2380 2381 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn); 2382 kfree(mpd); 2383 2384 return 0; 2385 } 2386 2387 enum { 2388 MATCH_CRITERIA_ENABLE_OUTER_BIT, 2389 MATCH_CRITERIA_ENABLE_MISC_BIT, 2390 MATCH_CRITERIA_ENABLE_INNER_BIT 2391 }; 2392 2393 #define HEADER_IS_ZERO(match_criteria, headers) \ 2394 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \ 2395 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \ 2396 2397 static u8 get_match_criteria_enable(u32 *match_criteria) 2398 { 2399 u8 match_criteria_enable; 2400 2401 match_criteria_enable = 2402 (!HEADER_IS_ZERO(match_criteria, outer_headers)) << 2403 MATCH_CRITERIA_ENABLE_OUTER_BIT; 2404 match_criteria_enable |= 2405 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) << 2406 MATCH_CRITERIA_ENABLE_MISC_BIT; 2407 match_criteria_enable |= 2408 (!HEADER_IS_ZERO(match_criteria, inner_headers)) << 2409 MATCH_CRITERIA_ENABLE_INNER_BIT; 2410 2411 return match_criteria_enable; 2412 } 2413 2414 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val) 2415 { 2416 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask); 2417 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val); 2418 } 2419 2420 static void set_flow_label(void *misc_c, void *misc_v, u8 mask, u8 val, 2421 bool inner) 2422 { 2423 if (inner) { 2424 MLX5_SET(fte_match_set_misc, 2425 misc_c, inner_ipv6_flow_label, mask); 2426 MLX5_SET(fte_match_set_misc, 2427 misc_v, inner_ipv6_flow_label, val); 2428 } else { 2429 MLX5_SET(fte_match_set_misc, 2430 misc_c, outer_ipv6_flow_label, mask); 2431 MLX5_SET(fte_match_set_misc, 2432 misc_v, outer_ipv6_flow_label, val); 2433 } 2434 } 2435 2436 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val) 2437 { 2438 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask); 2439 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val); 2440 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2); 2441 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2); 2442 } 2443 2444 #define LAST_ETH_FIELD vlan_tag 2445 #define LAST_IB_FIELD sl 2446 #define LAST_IPV4_FIELD tos 2447 #define LAST_IPV6_FIELD traffic_class 2448 #define LAST_TCP_UDP_FIELD src_port 2449 #define LAST_TUNNEL_FIELD tunnel_id 2450 #define LAST_FLOW_TAG_FIELD tag_id 2451 #define LAST_DROP_FIELD size 2452 2453 /* Field is the last supported field */ 2454 #define FIELDS_NOT_SUPPORTED(filter, field)\ 2455 memchr_inv((void *)&filter.field +\ 2456 sizeof(filter.field), 0,\ 2457 sizeof(filter) -\ 2458 offsetof(typeof(filter), field) -\ 2459 sizeof(filter.field)) 2460 2461 static int parse_flow_flow_action(const union ib_flow_spec *ib_spec, 2462 const struct ib_flow_attr *flow_attr, 2463 struct mlx5_flow_act *action) 2464 { 2465 struct mlx5_ib_flow_action *maction = to_mflow_act(ib_spec->action.act); 2466 2467 switch (maction->ib_action.type) { 2468 case IB_FLOW_ACTION_ESP: 2469 /* Currently only AES_GCM keymat is supported by the driver */ 2470 action->esp_id = (uintptr_t)maction->esp_aes_gcm.ctx; 2471 action->action |= flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS ? 2472 MLX5_FLOW_CONTEXT_ACTION_ENCRYPT : 2473 MLX5_FLOW_CONTEXT_ACTION_DECRYPT; 2474 return 0; 2475 default: 2476 return -EOPNOTSUPP; 2477 } 2478 } 2479 2480 static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c, 2481 u32 *match_v, const union ib_flow_spec *ib_spec, 2482 const struct ib_flow_attr *flow_attr, 2483 struct mlx5_flow_act *action) 2484 { 2485 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c, 2486 misc_parameters); 2487 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v, 2488 misc_parameters); 2489 void *headers_c; 2490 void *headers_v; 2491 int match_ipv; 2492 int ret; 2493 2494 if (ib_spec->type & IB_FLOW_SPEC_INNER) { 2495 headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 2496 inner_headers); 2497 headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 2498 inner_headers); 2499 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2500 ft_field_support.inner_ip_version); 2501 } else { 2502 headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 2503 outer_headers); 2504 headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 2505 outer_headers); 2506 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2507 ft_field_support.outer_ip_version); 2508 } 2509 2510 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) { 2511 case IB_FLOW_SPEC_ETH: 2512 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD)) 2513 return -EOPNOTSUPP; 2514 2515 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2516 dmac_47_16), 2517 ib_spec->eth.mask.dst_mac); 2518 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2519 dmac_47_16), 2520 ib_spec->eth.val.dst_mac); 2521 2522 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2523 smac_47_16), 2524 ib_spec->eth.mask.src_mac); 2525 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2526 smac_47_16), 2527 ib_spec->eth.val.src_mac); 2528 2529 if (ib_spec->eth.mask.vlan_tag) { 2530 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2531 cvlan_tag, 1); 2532 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2533 cvlan_tag, 1); 2534 2535 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2536 first_vid, ntohs(ib_spec->eth.mask.vlan_tag)); 2537 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2538 first_vid, ntohs(ib_spec->eth.val.vlan_tag)); 2539 2540 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2541 first_cfi, 2542 ntohs(ib_spec->eth.mask.vlan_tag) >> 12); 2543 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2544 first_cfi, 2545 ntohs(ib_spec->eth.val.vlan_tag) >> 12); 2546 2547 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2548 first_prio, 2549 ntohs(ib_spec->eth.mask.vlan_tag) >> 13); 2550 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2551 first_prio, 2552 ntohs(ib_spec->eth.val.vlan_tag) >> 13); 2553 } 2554 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2555 ethertype, ntohs(ib_spec->eth.mask.ether_type)); 2556 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2557 ethertype, ntohs(ib_spec->eth.val.ether_type)); 2558 break; 2559 case IB_FLOW_SPEC_IPV4: 2560 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD)) 2561 return -EOPNOTSUPP; 2562 2563 if (match_ipv) { 2564 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2565 ip_version, 0xf); 2566 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2567 ip_version, MLX5_FS_IPV4_VERSION); 2568 } else { 2569 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2570 ethertype, 0xffff); 2571 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2572 ethertype, ETH_P_IP); 2573 } 2574 2575 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2576 src_ipv4_src_ipv6.ipv4_layout.ipv4), 2577 &ib_spec->ipv4.mask.src_ip, 2578 sizeof(ib_spec->ipv4.mask.src_ip)); 2579 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2580 src_ipv4_src_ipv6.ipv4_layout.ipv4), 2581 &ib_spec->ipv4.val.src_ip, 2582 sizeof(ib_spec->ipv4.val.src_ip)); 2583 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2584 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 2585 &ib_spec->ipv4.mask.dst_ip, 2586 sizeof(ib_spec->ipv4.mask.dst_ip)); 2587 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2588 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 2589 &ib_spec->ipv4.val.dst_ip, 2590 sizeof(ib_spec->ipv4.val.dst_ip)); 2591 2592 set_tos(headers_c, headers_v, 2593 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos); 2594 2595 set_proto(headers_c, headers_v, 2596 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto); 2597 break; 2598 case IB_FLOW_SPEC_IPV6: 2599 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD)) 2600 return -EOPNOTSUPP; 2601 2602 if (match_ipv) { 2603 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2604 ip_version, 0xf); 2605 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2606 ip_version, MLX5_FS_IPV6_VERSION); 2607 } else { 2608 MLX5_SET(fte_match_set_lyr_2_4, headers_c, 2609 ethertype, 0xffff); 2610 MLX5_SET(fte_match_set_lyr_2_4, headers_v, 2611 ethertype, ETH_P_IPV6); 2612 } 2613 2614 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2615 src_ipv4_src_ipv6.ipv6_layout.ipv6), 2616 &ib_spec->ipv6.mask.src_ip, 2617 sizeof(ib_spec->ipv6.mask.src_ip)); 2618 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2619 src_ipv4_src_ipv6.ipv6_layout.ipv6), 2620 &ib_spec->ipv6.val.src_ip, 2621 sizeof(ib_spec->ipv6.val.src_ip)); 2622 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, 2623 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 2624 &ib_spec->ipv6.mask.dst_ip, 2625 sizeof(ib_spec->ipv6.mask.dst_ip)); 2626 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, 2627 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 2628 &ib_spec->ipv6.val.dst_ip, 2629 sizeof(ib_spec->ipv6.val.dst_ip)); 2630 2631 set_tos(headers_c, headers_v, 2632 ib_spec->ipv6.mask.traffic_class, 2633 ib_spec->ipv6.val.traffic_class); 2634 2635 set_proto(headers_c, headers_v, 2636 ib_spec->ipv6.mask.next_hdr, 2637 ib_spec->ipv6.val.next_hdr); 2638 2639 set_flow_label(misc_params_c, misc_params_v, 2640 ntohl(ib_spec->ipv6.mask.flow_label), 2641 ntohl(ib_spec->ipv6.val.flow_label), 2642 ib_spec->type & IB_FLOW_SPEC_INNER); 2643 break; 2644 case IB_FLOW_SPEC_ESP: 2645 if (ib_spec->esp.mask.seq) 2646 return -EOPNOTSUPP; 2647 2648 MLX5_SET(fte_match_set_misc, misc_params_c, outer_esp_spi, 2649 ntohl(ib_spec->esp.mask.spi)); 2650 MLX5_SET(fte_match_set_misc, misc_params_v, outer_esp_spi, 2651 ntohl(ib_spec->esp.val.spi)); 2652 break; 2653 case IB_FLOW_SPEC_TCP: 2654 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 2655 LAST_TCP_UDP_FIELD)) 2656 return -EOPNOTSUPP; 2657 2658 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol, 2659 0xff); 2660 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, 2661 IPPROTO_TCP); 2662 2663 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport, 2664 ntohs(ib_spec->tcp_udp.mask.src_port)); 2665 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport, 2666 ntohs(ib_spec->tcp_udp.val.src_port)); 2667 2668 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport, 2669 ntohs(ib_spec->tcp_udp.mask.dst_port)); 2670 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport, 2671 ntohs(ib_spec->tcp_udp.val.dst_port)); 2672 break; 2673 case IB_FLOW_SPEC_UDP: 2674 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 2675 LAST_TCP_UDP_FIELD)) 2676 return -EOPNOTSUPP; 2677 2678 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol, 2679 0xff); 2680 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, 2681 IPPROTO_UDP); 2682 2683 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport, 2684 ntohs(ib_spec->tcp_udp.mask.src_port)); 2685 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport, 2686 ntohs(ib_spec->tcp_udp.val.src_port)); 2687 2688 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport, 2689 ntohs(ib_spec->tcp_udp.mask.dst_port)); 2690 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, 2691 ntohs(ib_spec->tcp_udp.val.dst_port)); 2692 break; 2693 case IB_FLOW_SPEC_VXLAN_TUNNEL: 2694 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask, 2695 LAST_TUNNEL_FIELD)) 2696 return -EOPNOTSUPP; 2697 2698 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni, 2699 ntohl(ib_spec->tunnel.mask.tunnel_id)); 2700 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni, 2701 ntohl(ib_spec->tunnel.val.tunnel_id)); 2702 break; 2703 case IB_FLOW_SPEC_ACTION_TAG: 2704 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag, 2705 LAST_FLOW_TAG_FIELD)) 2706 return -EOPNOTSUPP; 2707 if (ib_spec->flow_tag.tag_id >= BIT(24)) 2708 return -EINVAL; 2709 2710 action->flow_tag = ib_spec->flow_tag.tag_id; 2711 action->has_flow_tag = true; 2712 break; 2713 case IB_FLOW_SPEC_ACTION_DROP: 2714 if (FIELDS_NOT_SUPPORTED(ib_spec->drop, 2715 LAST_DROP_FIELD)) 2716 return -EOPNOTSUPP; 2717 action->action |= MLX5_FLOW_CONTEXT_ACTION_DROP; 2718 break; 2719 case IB_FLOW_SPEC_ACTION_HANDLE: 2720 ret = parse_flow_flow_action(ib_spec, flow_attr, action); 2721 if (ret) 2722 return ret; 2723 break; 2724 default: 2725 return -EINVAL; 2726 } 2727 2728 return 0; 2729 } 2730 2731 /* If a flow could catch both multicast and unicast packets, 2732 * it won't fall into the multicast flow steering table and this rule 2733 * could steal other multicast packets. 2734 */ 2735 static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr) 2736 { 2737 union ib_flow_spec *flow_spec; 2738 2739 if (ib_attr->type != IB_FLOW_ATTR_NORMAL || 2740 ib_attr->num_of_specs < 1) 2741 return false; 2742 2743 flow_spec = (union ib_flow_spec *)(ib_attr + 1); 2744 if (flow_spec->type == IB_FLOW_SPEC_IPV4) { 2745 struct ib_flow_spec_ipv4 *ipv4_spec; 2746 2747 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec; 2748 if (ipv4_is_multicast(ipv4_spec->val.dst_ip)) 2749 return true; 2750 2751 return false; 2752 } 2753 2754 if (flow_spec->type == IB_FLOW_SPEC_ETH) { 2755 struct ib_flow_spec_eth *eth_spec; 2756 2757 eth_spec = (struct ib_flow_spec_eth *)flow_spec; 2758 return is_multicast_ether_addr(eth_spec->mask.dst_mac) && 2759 is_multicast_ether_addr(eth_spec->val.dst_mac); 2760 } 2761 2762 return false; 2763 } 2764 2765 enum valid_spec { 2766 VALID_SPEC_INVALID, 2767 VALID_SPEC_VALID, 2768 VALID_SPEC_NA, 2769 }; 2770 2771 static enum valid_spec 2772 is_valid_esp_aes_gcm(struct mlx5_core_dev *mdev, 2773 const struct mlx5_flow_spec *spec, 2774 const struct mlx5_flow_act *flow_act, 2775 bool egress) 2776 { 2777 const u32 *match_c = spec->match_criteria; 2778 bool is_crypto = 2779 (flow_act->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT | 2780 MLX5_FLOW_CONTEXT_ACTION_DECRYPT)); 2781 bool is_ipsec = mlx5_fs_is_ipsec_flow(match_c); 2782 bool is_drop = flow_act->action & MLX5_FLOW_CONTEXT_ACTION_DROP; 2783 2784 /* 2785 * Currently only crypto is supported in egress, when regular egress 2786 * rules would be supported, always return VALID_SPEC_NA. 2787 */ 2788 if (!is_crypto) 2789 return egress ? VALID_SPEC_INVALID : VALID_SPEC_NA; 2790 2791 return is_crypto && is_ipsec && 2792 (!egress || (!is_drop && !flow_act->has_flow_tag)) ? 2793 VALID_SPEC_VALID : VALID_SPEC_INVALID; 2794 } 2795 2796 static bool is_valid_spec(struct mlx5_core_dev *mdev, 2797 const struct mlx5_flow_spec *spec, 2798 const struct mlx5_flow_act *flow_act, 2799 bool egress) 2800 { 2801 /* We curretly only support ipsec egress flow */ 2802 return is_valid_esp_aes_gcm(mdev, spec, flow_act, egress) != VALID_SPEC_INVALID; 2803 } 2804 2805 static bool is_valid_ethertype(struct mlx5_core_dev *mdev, 2806 const struct ib_flow_attr *flow_attr, 2807 bool check_inner) 2808 { 2809 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1); 2810 int match_ipv = check_inner ? 2811 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2812 ft_field_support.inner_ip_version) : 2813 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 2814 ft_field_support.outer_ip_version); 2815 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0; 2816 bool ipv4_spec_valid, ipv6_spec_valid; 2817 unsigned int ip_spec_type = 0; 2818 bool has_ethertype = false; 2819 unsigned int spec_index; 2820 bool mask_valid = true; 2821 u16 eth_type = 0; 2822 bool type_valid; 2823 2824 /* Validate that ethertype is correct */ 2825 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 2826 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) && 2827 ib_spec->eth.mask.ether_type) { 2828 mask_valid = (ib_spec->eth.mask.ether_type == 2829 htons(0xffff)); 2830 has_ethertype = true; 2831 eth_type = ntohs(ib_spec->eth.val.ether_type); 2832 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) || 2833 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) { 2834 ip_spec_type = ib_spec->type; 2835 } 2836 ib_spec = (void *)ib_spec + ib_spec->size; 2837 } 2838 2839 type_valid = (!has_ethertype) || (!ip_spec_type); 2840 if (!type_valid && mask_valid) { 2841 ipv4_spec_valid = (eth_type == ETH_P_IP) && 2842 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit)); 2843 ipv6_spec_valid = (eth_type == ETH_P_IPV6) && 2844 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit)); 2845 2846 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) || 2847 (((eth_type == ETH_P_MPLS_UC) || 2848 (eth_type == ETH_P_MPLS_MC)) && match_ipv); 2849 } 2850 2851 return type_valid; 2852 } 2853 2854 static bool is_valid_attr(struct mlx5_core_dev *mdev, 2855 const struct ib_flow_attr *flow_attr) 2856 { 2857 return is_valid_ethertype(mdev, flow_attr, false) && 2858 is_valid_ethertype(mdev, flow_attr, true); 2859 } 2860 2861 static void put_flow_table(struct mlx5_ib_dev *dev, 2862 struct mlx5_ib_flow_prio *prio, bool ft_added) 2863 { 2864 prio->refcount -= !!ft_added; 2865 if (!prio->refcount) { 2866 mlx5_destroy_flow_table(prio->flow_table); 2867 prio->flow_table = NULL; 2868 } 2869 } 2870 2871 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id) 2872 { 2873 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device); 2874 struct mlx5_ib_flow_handler *handler = container_of(flow_id, 2875 struct mlx5_ib_flow_handler, 2876 ibflow); 2877 struct mlx5_ib_flow_handler *iter, *tmp; 2878 2879 mutex_lock(&dev->flow_db->lock); 2880 2881 list_for_each_entry_safe(iter, tmp, &handler->list, list) { 2882 mlx5_del_flow_rules(iter->rule); 2883 put_flow_table(dev, iter->prio, true); 2884 list_del(&iter->list); 2885 kfree(iter); 2886 } 2887 2888 mlx5_del_flow_rules(handler->rule); 2889 put_flow_table(dev, handler->prio, true); 2890 mutex_unlock(&dev->flow_db->lock); 2891 2892 kfree(handler); 2893 2894 return 0; 2895 } 2896 2897 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap) 2898 { 2899 priority *= 2; 2900 if (!dont_trap) 2901 priority++; 2902 return priority; 2903 } 2904 2905 enum flow_table_type { 2906 MLX5_IB_FT_RX, 2907 MLX5_IB_FT_TX 2908 }; 2909 2910 #define MLX5_FS_MAX_TYPES 6 2911 #define MLX5_FS_MAX_ENTRIES BIT(16) 2912 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev, 2913 struct ib_flow_attr *flow_attr, 2914 enum flow_table_type ft_type) 2915 { 2916 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP; 2917 struct mlx5_flow_namespace *ns = NULL; 2918 struct mlx5_ib_flow_prio *prio; 2919 struct mlx5_flow_table *ft; 2920 int max_table_size; 2921 int num_entries; 2922 int num_groups; 2923 int priority; 2924 int err = 0; 2925 2926 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 2927 log_max_ft_size)); 2928 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 2929 if (ft_type == MLX5_IB_FT_TX) 2930 priority = 0; 2931 else if (flow_is_multicast_only(flow_attr) && 2932 !dont_trap) 2933 priority = MLX5_IB_FLOW_MCAST_PRIO; 2934 else 2935 priority = ib_prio_to_core_prio(flow_attr->priority, 2936 dont_trap); 2937 ns = mlx5_get_flow_namespace(dev->mdev, 2938 ft_type == MLX5_IB_FT_TX ? 2939 MLX5_FLOW_NAMESPACE_EGRESS : 2940 MLX5_FLOW_NAMESPACE_BYPASS); 2941 num_entries = MLX5_FS_MAX_ENTRIES; 2942 num_groups = MLX5_FS_MAX_TYPES; 2943 prio = &dev->flow_db->prios[priority]; 2944 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 2945 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 2946 ns = mlx5_get_flow_namespace(dev->mdev, 2947 MLX5_FLOW_NAMESPACE_LEFTOVERS); 2948 build_leftovers_ft_param(&priority, 2949 &num_entries, 2950 &num_groups); 2951 prio = &dev->flow_db->prios[MLX5_IB_FLOW_LEFTOVERS_PRIO]; 2952 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 2953 if (!MLX5_CAP_FLOWTABLE(dev->mdev, 2954 allow_sniffer_and_nic_rx_shared_tir)) 2955 return ERR_PTR(-ENOTSUPP); 2956 2957 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ? 2958 MLX5_FLOW_NAMESPACE_SNIFFER_RX : 2959 MLX5_FLOW_NAMESPACE_SNIFFER_TX); 2960 2961 prio = &dev->flow_db->sniffer[ft_type]; 2962 priority = 0; 2963 num_entries = 1; 2964 num_groups = 1; 2965 } 2966 2967 if (!ns) 2968 return ERR_PTR(-ENOTSUPP); 2969 2970 if (num_entries > max_table_size) 2971 return ERR_PTR(-ENOMEM); 2972 2973 ft = prio->flow_table; 2974 if (!ft) { 2975 ft = mlx5_create_auto_grouped_flow_table(ns, priority, 2976 num_entries, 2977 num_groups, 2978 0, 0); 2979 2980 if (!IS_ERR(ft)) { 2981 prio->refcount = 0; 2982 prio->flow_table = ft; 2983 } else { 2984 err = PTR_ERR(ft); 2985 } 2986 } 2987 2988 return err ? ERR_PTR(err) : prio; 2989 } 2990 2991 static void set_underlay_qp(struct mlx5_ib_dev *dev, 2992 struct mlx5_flow_spec *spec, 2993 u32 underlay_qpn) 2994 { 2995 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, 2996 spec->match_criteria, 2997 misc_parameters); 2998 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, 2999 misc_parameters); 3000 3001 if (underlay_qpn && 3002 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, 3003 ft_field_support.bth_dst_qp)) { 3004 MLX5_SET(fte_match_set_misc, 3005 misc_params_v, bth_dst_qp, underlay_qpn); 3006 MLX5_SET(fte_match_set_misc, 3007 misc_params_c, bth_dst_qp, 0xffffff); 3008 } 3009 } 3010 3011 static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev, 3012 struct mlx5_ib_flow_prio *ft_prio, 3013 const struct ib_flow_attr *flow_attr, 3014 struct mlx5_flow_destination *dst, 3015 u32 underlay_qpn) 3016 { 3017 struct mlx5_flow_table *ft = ft_prio->flow_table; 3018 struct mlx5_ib_flow_handler *handler; 3019 struct mlx5_flow_act flow_act = {.flow_tag = MLX5_FS_DEFAULT_FLOW_TAG}; 3020 struct mlx5_flow_spec *spec; 3021 struct mlx5_flow_destination *rule_dst = dst; 3022 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr); 3023 unsigned int spec_index; 3024 int err = 0; 3025 int dest_num = 1; 3026 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS; 3027 3028 if (!is_valid_attr(dev->mdev, flow_attr)) 3029 return ERR_PTR(-EINVAL); 3030 3031 spec = kvzalloc(sizeof(*spec), GFP_KERNEL); 3032 handler = kzalloc(sizeof(*handler), GFP_KERNEL); 3033 if (!handler || !spec) { 3034 err = -ENOMEM; 3035 goto free; 3036 } 3037 3038 INIT_LIST_HEAD(&handler->list); 3039 3040 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 3041 err = parse_flow_attr(dev->mdev, spec->match_criteria, 3042 spec->match_value, 3043 ib_flow, flow_attr, &flow_act); 3044 if (err < 0) 3045 goto free; 3046 3047 ib_flow += ((union ib_flow_spec *)ib_flow)->size; 3048 } 3049 3050 if (!flow_is_multicast_only(flow_attr)) 3051 set_underlay_qp(dev, spec, underlay_qpn); 3052 3053 if (dev->rep) { 3054 void *misc; 3055 3056 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, 3057 misc_parameters); 3058 MLX5_SET(fte_match_set_misc, misc, source_port, 3059 dev->rep->vport); 3060 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, 3061 misc_parameters); 3062 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port); 3063 } 3064 3065 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria); 3066 3067 if (is_egress && 3068 !is_valid_spec(dev->mdev, spec, &flow_act, is_egress)) { 3069 err = -EINVAL; 3070 goto free; 3071 } 3072 3073 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP) { 3074 rule_dst = NULL; 3075 dest_num = 0; 3076 } else { 3077 if (is_egress) 3078 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW; 3079 else 3080 flow_act.action |= 3081 dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST : 3082 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO; 3083 } 3084 3085 if (flow_act.has_flow_tag && 3086 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 3087 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) { 3088 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n", 3089 flow_act.flow_tag, flow_attr->type); 3090 err = -EINVAL; 3091 goto free; 3092 } 3093 handler->rule = mlx5_add_flow_rules(ft, spec, 3094 &flow_act, 3095 rule_dst, dest_num); 3096 3097 if (IS_ERR(handler->rule)) { 3098 err = PTR_ERR(handler->rule); 3099 goto free; 3100 } 3101 3102 ft_prio->refcount++; 3103 handler->prio = ft_prio; 3104 3105 ft_prio->flow_table = ft; 3106 free: 3107 if (err) 3108 kfree(handler); 3109 kvfree(spec); 3110 return err ? ERR_PTR(err) : handler; 3111 } 3112 3113 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev, 3114 struct mlx5_ib_flow_prio *ft_prio, 3115 const struct ib_flow_attr *flow_attr, 3116 struct mlx5_flow_destination *dst) 3117 { 3118 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0); 3119 } 3120 3121 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev, 3122 struct mlx5_ib_flow_prio *ft_prio, 3123 struct ib_flow_attr *flow_attr, 3124 struct mlx5_flow_destination *dst) 3125 { 3126 struct mlx5_ib_flow_handler *handler_dst = NULL; 3127 struct mlx5_ib_flow_handler *handler = NULL; 3128 3129 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL); 3130 if (!IS_ERR(handler)) { 3131 handler_dst = create_flow_rule(dev, ft_prio, 3132 flow_attr, dst); 3133 if (IS_ERR(handler_dst)) { 3134 mlx5_del_flow_rules(handler->rule); 3135 ft_prio->refcount--; 3136 kfree(handler); 3137 handler = handler_dst; 3138 } else { 3139 list_add(&handler_dst->list, &handler->list); 3140 } 3141 } 3142 3143 return handler; 3144 } 3145 enum { 3146 LEFTOVERS_MC, 3147 LEFTOVERS_UC, 3148 }; 3149 3150 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev, 3151 struct mlx5_ib_flow_prio *ft_prio, 3152 struct ib_flow_attr *flow_attr, 3153 struct mlx5_flow_destination *dst) 3154 { 3155 struct mlx5_ib_flow_handler *handler_ucast = NULL; 3156 struct mlx5_ib_flow_handler *handler = NULL; 3157 3158 static struct { 3159 struct ib_flow_attr flow_attr; 3160 struct ib_flow_spec_eth eth_flow; 3161 } leftovers_specs[] = { 3162 [LEFTOVERS_MC] = { 3163 .flow_attr = { 3164 .num_of_specs = 1, 3165 .size = sizeof(leftovers_specs[0]) 3166 }, 3167 .eth_flow = { 3168 .type = IB_FLOW_SPEC_ETH, 3169 .size = sizeof(struct ib_flow_spec_eth), 3170 .mask = {.dst_mac = {0x1} }, 3171 .val = {.dst_mac = {0x1} } 3172 } 3173 }, 3174 [LEFTOVERS_UC] = { 3175 .flow_attr = { 3176 .num_of_specs = 1, 3177 .size = sizeof(leftovers_specs[0]) 3178 }, 3179 .eth_flow = { 3180 .type = IB_FLOW_SPEC_ETH, 3181 .size = sizeof(struct ib_flow_spec_eth), 3182 .mask = {.dst_mac = {0x1} }, 3183 .val = {.dst_mac = {} } 3184 } 3185 } 3186 }; 3187 3188 handler = create_flow_rule(dev, ft_prio, 3189 &leftovers_specs[LEFTOVERS_MC].flow_attr, 3190 dst); 3191 if (!IS_ERR(handler) && 3192 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) { 3193 handler_ucast = create_flow_rule(dev, ft_prio, 3194 &leftovers_specs[LEFTOVERS_UC].flow_attr, 3195 dst); 3196 if (IS_ERR(handler_ucast)) { 3197 mlx5_del_flow_rules(handler->rule); 3198 ft_prio->refcount--; 3199 kfree(handler); 3200 handler = handler_ucast; 3201 } else { 3202 list_add(&handler_ucast->list, &handler->list); 3203 } 3204 } 3205 3206 return handler; 3207 } 3208 3209 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev, 3210 struct mlx5_ib_flow_prio *ft_rx, 3211 struct mlx5_ib_flow_prio *ft_tx, 3212 struct mlx5_flow_destination *dst) 3213 { 3214 struct mlx5_ib_flow_handler *handler_rx; 3215 struct mlx5_ib_flow_handler *handler_tx; 3216 int err; 3217 static const struct ib_flow_attr flow_attr = { 3218 .num_of_specs = 0, 3219 .size = sizeof(flow_attr) 3220 }; 3221 3222 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst); 3223 if (IS_ERR(handler_rx)) { 3224 err = PTR_ERR(handler_rx); 3225 goto err; 3226 } 3227 3228 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst); 3229 if (IS_ERR(handler_tx)) { 3230 err = PTR_ERR(handler_tx); 3231 goto err_tx; 3232 } 3233 3234 list_add(&handler_tx->list, &handler_rx->list); 3235 3236 return handler_rx; 3237 3238 err_tx: 3239 mlx5_del_flow_rules(handler_rx->rule); 3240 ft_rx->refcount--; 3241 kfree(handler_rx); 3242 err: 3243 return ERR_PTR(err); 3244 } 3245 3246 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp, 3247 struct ib_flow_attr *flow_attr, 3248 int domain) 3249 { 3250 struct mlx5_ib_dev *dev = to_mdev(qp->device); 3251 struct mlx5_ib_qp *mqp = to_mqp(qp); 3252 struct mlx5_ib_flow_handler *handler = NULL; 3253 struct mlx5_flow_destination *dst = NULL; 3254 struct mlx5_ib_flow_prio *ft_prio_tx = NULL; 3255 struct mlx5_ib_flow_prio *ft_prio; 3256 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS; 3257 int err; 3258 int underlay_qpn; 3259 3260 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) 3261 return ERR_PTR(-ENOMEM); 3262 3263 if (domain != IB_FLOW_DOMAIN_USER || 3264 flow_attr->port > dev->num_ports || 3265 (flow_attr->flags & ~(IB_FLOW_ATTR_FLAGS_DONT_TRAP | 3266 IB_FLOW_ATTR_FLAGS_EGRESS))) 3267 return ERR_PTR(-EINVAL); 3268 3269 if (is_egress && 3270 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 3271 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) 3272 return ERR_PTR(-EINVAL); 3273 3274 dst = kzalloc(sizeof(*dst), GFP_KERNEL); 3275 if (!dst) 3276 return ERR_PTR(-ENOMEM); 3277 3278 mutex_lock(&dev->flow_db->lock); 3279 3280 ft_prio = get_flow_table(dev, flow_attr, 3281 is_egress ? MLX5_IB_FT_TX : MLX5_IB_FT_RX); 3282 if (IS_ERR(ft_prio)) { 3283 err = PTR_ERR(ft_prio); 3284 goto unlock; 3285 } 3286 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 3287 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX); 3288 if (IS_ERR(ft_prio_tx)) { 3289 err = PTR_ERR(ft_prio_tx); 3290 ft_prio_tx = NULL; 3291 goto destroy_ft; 3292 } 3293 } 3294 3295 if (is_egress) { 3296 dst->type = MLX5_FLOW_DESTINATION_TYPE_PORT; 3297 } else { 3298 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR; 3299 if (mqp->flags & MLX5_IB_QP_RSS) 3300 dst->tir_num = mqp->rss_qp.tirn; 3301 else 3302 dst->tir_num = mqp->raw_packet_qp.rq.tirn; 3303 } 3304 3305 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 3306 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) { 3307 handler = create_dont_trap_rule(dev, ft_prio, 3308 flow_attr, dst); 3309 } else { 3310 underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ? 3311 mqp->underlay_qpn : 0; 3312 handler = _create_flow_rule(dev, ft_prio, flow_attr, 3313 dst, underlay_qpn); 3314 } 3315 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 3316 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 3317 handler = create_leftovers_rule(dev, ft_prio, flow_attr, 3318 dst); 3319 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 3320 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst); 3321 } else { 3322 err = -EINVAL; 3323 goto destroy_ft; 3324 } 3325 3326 if (IS_ERR(handler)) { 3327 err = PTR_ERR(handler); 3328 handler = NULL; 3329 goto destroy_ft; 3330 } 3331 3332 mutex_unlock(&dev->flow_db->lock); 3333 kfree(dst); 3334 3335 return &handler->ibflow; 3336 3337 destroy_ft: 3338 put_flow_table(dev, ft_prio, false); 3339 if (ft_prio_tx) 3340 put_flow_table(dev, ft_prio_tx, false); 3341 unlock: 3342 mutex_unlock(&dev->flow_db->lock); 3343 kfree(dst); 3344 kfree(handler); 3345 return ERR_PTR(err); 3346 } 3347 3348 static u32 mlx5_ib_flow_action_flags_to_accel_xfrm_flags(u32 mlx5_flags) 3349 { 3350 u32 flags = 0; 3351 3352 if (mlx5_flags & MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA) 3353 flags |= MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA; 3354 3355 return flags; 3356 } 3357 3358 #define MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA 3359 static struct ib_flow_action * 3360 mlx5_ib_create_flow_action_esp(struct ib_device *device, 3361 const struct ib_flow_action_attrs_esp *attr, 3362 struct uverbs_attr_bundle *attrs) 3363 { 3364 struct mlx5_ib_dev *mdev = to_mdev(device); 3365 struct ib_uverbs_flow_action_esp_keymat_aes_gcm *aes_gcm; 3366 struct mlx5_accel_esp_xfrm_attrs accel_attrs = {}; 3367 struct mlx5_ib_flow_action *action; 3368 u64 action_flags; 3369 u64 flags; 3370 int err = 0; 3371 3372 if (IS_UVERBS_COPY_ERR(uverbs_copy_from(&action_flags, attrs, 3373 MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS))) 3374 return ERR_PTR(-EFAULT); 3375 3376 if (action_flags >= (MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED << 1)) 3377 return ERR_PTR(-EOPNOTSUPP); 3378 3379 flags = mlx5_ib_flow_action_flags_to_accel_xfrm_flags(action_flags); 3380 3381 /* We current only support a subset of the standard features. Only a 3382 * keymat of type AES_GCM, with icv_len == 16, iv_algo == SEQ and esn 3383 * (with overlap). Full offload mode isn't supported. 3384 */ 3385 if (!attr->keymat || attr->replay || attr->encap || 3386 attr->spi || attr->seq || attr->tfc_pad || 3387 attr->hard_limit_pkts || 3388 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED | 3389 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT))) 3390 return ERR_PTR(-EOPNOTSUPP); 3391 3392 if (attr->keymat->protocol != 3393 IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM) 3394 return ERR_PTR(-EOPNOTSUPP); 3395 3396 aes_gcm = &attr->keymat->keymat.aes_gcm; 3397 3398 if (aes_gcm->icv_len != 16 || 3399 aes_gcm->iv_algo != IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ) 3400 return ERR_PTR(-EOPNOTSUPP); 3401 3402 action = kmalloc(sizeof(*action), GFP_KERNEL); 3403 if (!action) 3404 return ERR_PTR(-ENOMEM); 3405 3406 action->esp_aes_gcm.ib_flags = attr->flags; 3407 memcpy(&accel_attrs.keymat.aes_gcm.aes_key, &aes_gcm->aes_key, 3408 sizeof(accel_attrs.keymat.aes_gcm.aes_key)); 3409 accel_attrs.keymat.aes_gcm.key_len = aes_gcm->key_len * 8; 3410 memcpy(&accel_attrs.keymat.aes_gcm.salt, &aes_gcm->salt, 3411 sizeof(accel_attrs.keymat.aes_gcm.salt)); 3412 memcpy(&accel_attrs.keymat.aes_gcm.seq_iv, &aes_gcm->iv, 3413 sizeof(accel_attrs.keymat.aes_gcm.seq_iv)); 3414 accel_attrs.keymat.aes_gcm.icv_len = aes_gcm->icv_len * 8; 3415 accel_attrs.keymat.aes_gcm.iv_algo = MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ; 3416 accel_attrs.keymat_type = MLX5_ACCEL_ESP_KEYMAT_AES_GCM; 3417 3418 accel_attrs.esn = attr->esn; 3419 if (attr->flags & IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) 3420 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED; 3421 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW) 3422 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP; 3423 3424 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT) 3425 accel_attrs.action |= MLX5_ACCEL_ESP_ACTION_ENCRYPT; 3426 3427 action->esp_aes_gcm.ctx = 3428 mlx5_accel_esp_create_xfrm(mdev->mdev, &accel_attrs, flags); 3429 if (IS_ERR(action->esp_aes_gcm.ctx)) { 3430 err = PTR_ERR(action->esp_aes_gcm.ctx); 3431 goto err_parse; 3432 } 3433 3434 action->esp_aes_gcm.ib_flags = attr->flags; 3435 3436 return &action->ib_action; 3437 3438 err_parse: 3439 kfree(action); 3440 return ERR_PTR(err); 3441 } 3442 3443 static int 3444 mlx5_ib_modify_flow_action_esp(struct ib_flow_action *action, 3445 const struct ib_flow_action_attrs_esp *attr, 3446 struct uverbs_attr_bundle *attrs) 3447 { 3448 struct mlx5_ib_flow_action *maction = to_mflow_act(action); 3449 struct mlx5_accel_esp_xfrm_attrs accel_attrs; 3450 int err = 0; 3451 3452 if (attr->keymat || attr->replay || attr->encap || 3453 attr->spi || attr->seq || attr->tfc_pad || 3454 attr->hard_limit_pkts || 3455 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED | 3456 IB_FLOW_ACTION_ESP_FLAGS_MOD_ESP_ATTRS | 3457 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW))) 3458 return -EOPNOTSUPP; 3459 3460 /* Only the ESN value or the MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP can 3461 * be modified. 3462 */ 3463 if (!(maction->esp_aes_gcm.ib_flags & 3464 IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) && 3465 attr->flags & (IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED | 3466 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)) 3467 return -EINVAL; 3468 3469 memcpy(&accel_attrs, &maction->esp_aes_gcm.ctx->attrs, 3470 sizeof(accel_attrs)); 3471 3472 accel_attrs.esn = attr->esn; 3473 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW) 3474 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP; 3475 else 3476 accel_attrs.flags &= ~MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP; 3477 3478 err = mlx5_accel_esp_modify_xfrm(maction->esp_aes_gcm.ctx, 3479 &accel_attrs); 3480 if (err) 3481 return err; 3482 3483 maction->esp_aes_gcm.ib_flags &= 3484 ~IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW; 3485 maction->esp_aes_gcm.ib_flags |= 3486 attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW; 3487 3488 return 0; 3489 } 3490 3491 static int mlx5_ib_destroy_flow_action(struct ib_flow_action *action) 3492 { 3493 struct mlx5_ib_flow_action *maction = to_mflow_act(action); 3494 3495 switch (action->type) { 3496 case IB_FLOW_ACTION_ESP: 3497 /* 3498 * We only support aes_gcm by now, so we implicitly know this is 3499 * the underline crypto. 3500 */ 3501 mlx5_accel_esp_destroy_xfrm(maction->esp_aes_gcm.ctx); 3502 break; 3503 default: 3504 WARN_ON(true); 3505 break; 3506 } 3507 3508 kfree(maction); 3509 return 0; 3510 } 3511 3512 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 3513 { 3514 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3515 struct mlx5_ib_qp *mqp = to_mqp(ibqp); 3516 int err; 3517 3518 if (mqp->flags & MLX5_IB_QP_UNDERLAY) { 3519 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n"); 3520 return -EOPNOTSUPP; 3521 } 3522 3523 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num); 3524 if (err) 3525 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 3526 ibqp->qp_num, gid->raw); 3527 3528 return err; 3529 } 3530 3531 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 3532 { 3533 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3534 int err; 3535 3536 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num); 3537 if (err) 3538 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 3539 ibqp->qp_num, gid->raw); 3540 3541 return err; 3542 } 3543 3544 static int init_node_data(struct mlx5_ib_dev *dev) 3545 { 3546 int err; 3547 3548 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 3549 if (err) 3550 return err; 3551 3552 dev->mdev->rev_id = dev->mdev->pdev->revision; 3553 3554 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 3555 } 3556 3557 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr, 3558 char *buf) 3559 { 3560 struct mlx5_ib_dev *dev = 3561 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 3562 3563 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages); 3564 } 3565 3566 static ssize_t show_reg_pages(struct device *device, 3567 struct device_attribute *attr, char *buf) 3568 { 3569 struct mlx5_ib_dev *dev = 3570 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 3571 3572 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 3573 } 3574 3575 static ssize_t show_hca(struct device *device, struct device_attribute *attr, 3576 char *buf) 3577 { 3578 struct mlx5_ib_dev *dev = 3579 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 3580 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device); 3581 } 3582 3583 static ssize_t show_rev(struct device *device, struct device_attribute *attr, 3584 char *buf) 3585 { 3586 struct mlx5_ib_dev *dev = 3587 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 3588 return sprintf(buf, "%x\n", dev->mdev->rev_id); 3589 } 3590 3591 static ssize_t show_board(struct device *device, struct device_attribute *attr, 3592 char *buf) 3593 { 3594 struct mlx5_ib_dev *dev = 3595 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 3596 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 3597 dev->mdev->board_id); 3598 } 3599 3600 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL); 3601 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL); 3602 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL); 3603 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL); 3604 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL); 3605 3606 static struct device_attribute *mlx5_class_attributes[] = { 3607 &dev_attr_hw_rev, 3608 &dev_attr_hca_type, 3609 &dev_attr_board_id, 3610 &dev_attr_fw_pages, 3611 &dev_attr_reg_pages, 3612 }; 3613 3614 static void pkey_change_handler(struct work_struct *work) 3615 { 3616 struct mlx5_ib_port_resources *ports = 3617 container_of(work, struct mlx5_ib_port_resources, 3618 pkey_change_work); 3619 3620 mutex_lock(&ports->devr->mutex); 3621 mlx5_ib_gsi_pkey_change(ports->gsi); 3622 mutex_unlock(&ports->devr->mutex); 3623 } 3624 3625 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 3626 { 3627 struct mlx5_ib_qp *mqp; 3628 struct mlx5_ib_cq *send_mcq, *recv_mcq; 3629 struct mlx5_core_cq *mcq; 3630 struct list_head cq_armed_list; 3631 unsigned long flags_qp; 3632 unsigned long flags_cq; 3633 unsigned long flags; 3634 3635 INIT_LIST_HEAD(&cq_armed_list); 3636 3637 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 3638 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 3639 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 3640 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 3641 if (mqp->sq.tail != mqp->sq.head) { 3642 send_mcq = to_mcq(mqp->ibqp.send_cq); 3643 spin_lock_irqsave(&send_mcq->lock, flags_cq); 3644 if (send_mcq->mcq.comp && 3645 mqp->ibqp.send_cq->comp_handler) { 3646 if (!send_mcq->mcq.reset_notify_added) { 3647 send_mcq->mcq.reset_notify_added = 1; 3648 list_add_tail(&send_mcq->mcq.reset_notify, 3649 &cq_armed_list); 3650 } 3651 } 3652 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 3653 } 3654 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 3655 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 3656 /* no handling is needed for SRQ */ 3657 if (!mqp->ibqp.srq) { 3658 if (mqp->rq.tail != mqp->rq.head) { 3659 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 3660 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 3661 if (recv_mcq->mcq.comp && 3662 mqp->ibqp.recv_cq->comp_handler) { 3663 if (!recv_mcq->mcq.reset_notify_added) { 3664 recv_mcq->mcq.reset_notify_added = 1; 3665 list_add_tail(&recv_mcq->mcq.reset_notify, 3666 &cq_armed_list); 3667 } 3668 } 3669 spin_unlock_irqrestore(&recv_mcq->lock, 3670 flags_cq); 3671 } 3672 } 3673 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 3674 } 3675 /*At that point all inflight post send were put to be executed as of we 3676 * lock/unlock above locks Now need to arm all involved CQs. 3677 */ 3678 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 3679 mcq->comp(mcq); 3680 } 3681 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 3682 } 3683 3684 static void delay_drop_handler(struct work_struct *work) 3685 { 3686 int err; 3687 struct mlx5_ib_delay_drop *delay_drop = 3688 container_of(work, struct mlx5_ib_delay_drop, 3689 delay_drop_work); 3690 3691 atomic_inc(&delay_drop->events_cnt); 3692 3693 mutex_lock(&delay_drop->lock); 3694 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev, 3695 delay_drop->timeout); 3696 if (err) { 3697 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n", 3698 delay_drop->timeout); 3699 delay_drop->activate = false; 3700 } 3701 mutex_unlock(&delay_drop->lock); 3702 } 3703 3704 static void mlx5_ib_handle_event(struct work_struct *_work) 3705 { 3706 struct mlx5_ib_event_work *work = 3707 container_of(_work, struct mlx5_ib_event_work, work); 3708 struct mlx5_ib_dev *ibdev; 3709 struct ib_event ibev; 3710 bool fatal = false; 3711 u8 port = (u8)work->param; 3712 3713 if (mlx5_core_is_mp_slave(work->dev)) { 3714 ibdev = mlx5_ib_get_ibdev_from_mpi(work->context); 3715 if (!ibdev) 3716 goto out; 3717 } else { 3718 ibdev = work->context; 3719 } 3720 3721 switch (work->event) { 3722 case MLX5_DEV_EVENT_SYS_ERROR: 3723 ibev.event = IB_EVENT_DEVICE_FATAL; 3724 mlx5_ib_handle_internal_error(ibdev); 3725 fatal = true; 3726 break; 3727 3728 case MLX5_DEV_EVENT_PORT_UP: 3729 case MLX5_DEV_EVENT_PORT_DOWN: 3730 case MLX5_DEV_EVENT_PORT_INITIALIZED: 3731 /* In RoCE, port up/down events are handled in 3732 * mlx5_netdev_event(). 3733 */ 3734 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 3735 IB_LINK_LAYER_ETHERNET) 3736 goto out; 3737 3738 ibev.event = (work->event == MLX5_DEV_EVENT_PORT_UP) ? 3739 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 3740 break; 3741 3742 case MLX5_DEV_EVENT_LID_CHANGE: 3743 ibev.event = IB_EVENT_LID_CHANGE; 3744 break; 3745 3746 case MLX5_DEV_EVENT_PKEY_CHANGE: 3747 ibev.event = IB_EVENT_PKEY_CHANGE; 3748 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 3749 break; 3750 3751 case MLX5_DEV_EVENT_GUID_CHANGE: 3752 ibev.event = IB_EVENT_GID_CHANGE; 3753 break; 3754 3755 case MLX5_DEV_EVENT_CLIENT_REREG: 3756 ibev.event = IB_EVENT_CLIENT_REREGISTER; 3757 break; 3758 case MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT: 3759 schedule_work(&ibdev->delay_drop.delay_drop_work); 3760 goto out; 3761 default: 3762 goto out; 3763 } 3764 3765 ibev.device = &ibdev->ib_dev; 3766 ibev.element.port_num = port; 3767 3768 if (!rdma_is_port_valid(&ibdev->ib_dev, port)) { 3769 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port); 3770 goto out; 3771 } 3772 3773 if (ibdev->ib_active) 3774 ib_dispatch_event(&ibev); 3775 3776 if (fatal) 3777 ibdev->ib_active = false; 3778 out: 3779 kfree(work); 3780 } 3781 3782 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context, 3783 enum mlx5_dev_event event, unsigned long param) 3784 { 3785 struct mlx5_ib_event_work *work; 3786 3787 work = kmalloc(sizeof(*work), GFP_ATOMIC); 3788 if (!work) 3789 return; 3790 3791 INIT_WORK(&work->work, mlx5_ib_handle_event); 3792 work->dev = dev; 3793 work->param = param; 3794 work->context = context; 3795 work->event = event; 3796 3797 queue_work(mlx5_ib_event_wq, &work->work); 3798 } 3799 3800 static int set_has_smi_cap(struct mlx5_ib_dev *dev) 3801 { 3802 struct mlx5_hca_vport_context vport_ctx; 3803 int err; 3804 int port; 3805 3806 for (port = 1; port <= dev->num_ports; port++) { 3807 dev->mdev->port_caps[port - 1].has_smi = false; 3808 if (MLX5_CAP_GEN(dev->mdev, port_type) == 3809 MLX5_CAP_PORT_TYPE_IB) { 3810 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) { 3811 err = mlx5_query_hca_vport_context(dev->mdev, 0, 3812 port, 0, 3813 &vport_ctx); 3814 if (err) { 3815 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n", 3816 port, err); 3817 return err; 3818 } 3819 dev->mdev->port_caps[port - 1].has_smi = 3820 vport_ctx.has_smi; 3821 } else { 3822 dev->mdev->port_caps[port - 1].has_smi = true; 3823 } 3824 } 3825 } 3826 return 0; 3827 } 3828 3829 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 3830 { 3831 int port; 3832 3833 for (port = 1; port <= dev->num_ports; port++) 3834 mlx5_query_ext_port_caps(dev, port); 3835 } 3836 3837 static int get_port_caps(struct mlx5_ib_dev *dev, u8 port) 3838 { 3839 struct ib_device_attr *dprops = NULL; 3840 struct ib_port_attr *pprops = NULL; 3841 int err = -ENOMEM; 3842 struct ib_udata uhw = {.inlen = 0, .outlen = 0}; 3843 3844 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL); 3845 if (!pprops) 3846 goto out; 3847 3848 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL); 3849 if (!dprops) 3850 goto out; 3851 3852 err = set_has_smi_cap(dev); 3853 if (err) 3854 goto out; 3855 3856 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw); 3857 if (err) { 3858 mlx5_ib_warn(dev, "query_device failed %d\n", err); 3859 goto out; 3860 } 3861 3862 memset(pprops, 0, sizeof(*pprops)); 3863 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops); 3864 if (err) { 3865 mlx5_ib_warn(dev, "query_port %d failed %d\n", 3866 port, err); 3867 goto out; 3868 } 3869 3870 dev->mdev->port_caps[port - 1].pkey_table_len = 3871 dprops->max_pkeys; 3872 dev->mdev->port_caps[port - 1].gid_table_len = 3873 pprops->gid_tbl_len; 3874 mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n", 3875 port, dprops->max_pkeys, pprops->gid_tbl_len); 3876 3877 out: 3878 kfree(pprops); 3879 kfree(dprops); 3880 3881 return err; 3882 } 3883 3884 static void destroy_umrc_res(struct mlx5_ib_dev *dev) 3885 { 3886 int err; 3887 3888 err = mlx5_mr_cache_cleanup(dev); 3889 if (err) 3890 mlx5_ib_warn(dev, "mr cache cleanup failed\n"); 3891 3892 mlx5_ib_destroy_qp(dev->umrc.qp); 3893 ib_free_cq(dev->umrc.cq); 3894 ib_dealloc_pd(dev->umrc.pd); 3895 } 3896 3897 enum { 3898 MAX_UMR_WR = 128, 3899 }; 3900 3901 static int create_umr_res(struct mlx5_ib_dev *dev) 3902 { 3903 struct ib_qp_init_attr *init_attr = NULL; 3904 struct ib_qp_attr *attr = NULL; 3905 struct ib_pd *pd; 3906 struct ib_cq *cq; 3907 struct ib_qp *qp; 3908 int ret; 3909 3910 attr = kzalloc(sizeof(*attr), GFP_KERNEL); 3911 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL); 3912 if (!attr || !init_attr) { 3913 ret = -ENOMEM; 3914 goto error_0; 3915 } 3916 3917 pd = ib_alloc_pd(&dev->ib_dev, 0); 3918 if (IS_ERR(pd)) { 3919 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n"); 3920 ret = PTR_ERR(pd); 3921 goto error_0; 3922 } 3923 3924 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ); 3925 if (IS_ERR(cq)) { 3926 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n"); 3927 ret = PTR_ERR(cq); 3928 goto error_2; 3929 } 3930 3931 init_attr->send_cq = cq; 3932 init_attr->recv_cq = cq; 3933 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR; 3934 init_attr->cap.max_send_wr = MAX_UMR_WR; 3935 init_attr->cap.max_send_sge = 1; 3936 init_attr->qp_type = MLX5_IB_QPT_REG_UMR; 3937 init_attr->port_num = 1; 3938 qp = mlx5_ib_create_qp(pd, init_attr, NULL); 3939 if (IS_ERR(qp)) { 3940 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n"); 3941 ret = PTR_ERR(qp); 3942 goto error_3; 3943 } 3944 qp->device = &dev->ib_dev; 3945 qp->real_qp = qp; 3946 qp->uobject = NULL; 3947 qp->qp_type = MLX5_IB_QPT_REG_UMR; 3948 qp->send_cq = init_attr->send_cq; 3949 qp->recv_cq = init_attr->recv_cq; 3950 3951 attr->qp_state = IB_QPS_INIT; 3952 attr->port_num = 1; 3953 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX | 3954 IB_QP_PORT, NULL); 3955 if (ret) { 3956 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n"); 3957 goto error_4; 3958 } 3959 3960 memset(attr, 0, sizeof(*attr)); 3961 attr->qp_state = IB_QPS_RTR; 3962 attr->path_mtu = IB_MTU_256; 3963 3964 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 3965 if (ret) { 3966 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n"); 3967 goto error_4; 3968 } 3969 3970 memset(attr, 0, sizeof(*attr)); 3971 attr->qp_state = IB_QPS_RTS; 3972 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 3973 if (ret) { 3974 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n"); 3975 goto error_4; 3976 } 3977 3978 dev->umrc.qp = qp; 3979 dev->umrc.cq = cq; 3980 dev->umrc.pd = pd; 3981 3982 sema_init(&dev->umrc.sem, MAX_UMR_WR); 3983 ret = mlx5_mr_cache_init(dev); 3984 if (ret) { 3985 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 3986 goto error_4; 3987 } 3988 3989 kfree(attr); 3990 kfree(init_attr); 3991 3992 return 0; 3993 3994 error_4: 3995 mlx5_ib_destroy_qp(qp); 3996 3997 error_3: 3998 ib_free_cq(cq); 3999 4000 error_2: 4001 ib_dealloc_pd(pd); 4002 4003 error_0: 4004 kfree(attr); 4005 kfree(init_attr); 4006 return ret; 4007 } 4008 4009 static u8 mlx5_get_umr_fence(u8 umr_fence_cap) 4010 { 4011 switch (umr_fence_cap) { 4012 case MLX5_CAP_UMR_FENCE_NONE: 4013 return MLX5_FENCE_MODE_NONE; 4014 case MLX5_CAP_UMR_FENCE_SMALL: 4015 return MLX5_FENCE_MODE_INITIATOR_SMALL; 4016 default: 4017 return MLX5_FENCE_MODE_STRONG_ORDERING; 4018 } 4019 } 4020 4021 static int create_dev_resources(struct mlx5_ib_resources *devr) 4022 { 4023 struct ib_srq_init_attr attr; 4024 struct mlx5_ib_dev *dev; 4025 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 4026 int port; 4027 int ret = 0; 4028 4029 dev = container_of(devr, struct mlx5_ib_dev, devr); 4030 4031 mutex_init(&devr->mutex); 4032 4033 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL); 4034 if (IS_ERR(devr->p0)) { 4035 ret = PTR_ERR(devr->p0); 4036 goto error0; 4037 } 4038 devr->p0->device = &dev->ib_dev; 4039 devr->p0->uobject = NULL; 4040 atomic_set(&devr->p0->usecnt, 0); 4041 4042 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL); 4043 if (IS_ERR(devr->c0)) { 4044 ret = PTR_ERR(devr->c0); 4045 goto error1; 4046 } 4047 devr->c0->device = &dev->ib_dev; 4048 devr->c0->uobject = NULL; 4049 devr->c0->comp_handler = NULL; 4050 devr->c0->event_handler = NULL; 4051 devr->c0->cq_context = NULL; 4052 atomic_set(&devr->c0->usecnt, 0); 4053 4054 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 4055 if (IS_ERR(devr->x0)) { 4056 ret = PTR_ERR(devr->x0); 4057 goto error2; 4058 } 4059 devr->x0->device = &dev->ib_dev; 4060 devr->x0->inode = NULL; 4061 atomic_set(&devr->x0->usecnt, 0); 4062 mutex_init(&devr->x0->tgt_qp_mutex); 4063 INIT_LIST_HEAD(&devr->x0->tgt_qp_list); 4064 4065 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 4066 if (IS_ERR(devr->x1)) { 4067 ret = PTR_ERR(devr->x1); 4068 goto error3; 4069 } 4070 devr->x1->device = &dev->ib_dev; 4071 devr->x1->inode = NULL; 4072 atomic_set(&devr->x1->usecnt, 0); 4073 mutex_init(&devr->x1->tgt_qp_mutex); 4074 INIT_LIST_HEAD(&devr->x1->tgt_qp_list); 4075 4076 memset(&attr, 0, sizeof(attr)); 4077 attr.attr.max_sge = 1; 4078 attr.attr.max_wr = 1; 4079 attr.srq_type = IB_SRQT_XRC; 4080 attr.ext.cq = devr->c0; 4081 attr.ext.xrc.xrcd = devr->x0; 4082 4083 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 4084 if (IS_ERR(devr->s0)) { 4085 ret = PTR_ERR(devr->s0); 4086 goto error4; 4087 } 4088 devr->s0->device = &dev->ib_dev; 4089 devr->s0->pd = devr->p0; 4090 devr->s0->uobject = NULL; 4091 devr->s0->event_handler = NULL; 4092 devr->s0->srq_context = NULL; 4093 devr->s0->srq_type = IB_SRQT_XRC; 4094 devr->s0->ext.xrc.xrcd = devr->x0; 4095 devr->s0->ext.cq = devr->c0; 4096 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt); 4097 atomic_inc(&devr->s0->ext.cq->usecnt); 4098 atomic_inc(&devr->p0->usecnt); 4099 atomic_set(&devr->s0->usecnt, 0); 4100 4101 memset(&attr, 0, sizeof(attr)); 4102 attr.attr.max_sge = 1; 4103 attr.attr.max_wr = 1; 4104 attr.srq_type = IB_SRQT_BASIC; 4105 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 4106 if (IS_ERR(devr->s1)) { 4107 ret = PTR_ERR(devr->s1); 4108 goto error5; 4109 } 4110 devr->s1->device = &dev->ib_dev; 4111 devr->s1->pd = devr->p0; 4112 devr->s1->uobject = NULL; 4113 devr->s1->event_handler = NULL; 4114 devr->s1->srq_context = NULL; 4115 devr->s1->srq_type = IB_SRQT_BASIC; 4116 devr->s1->ext.cq = devr->c0; 4117 atomic_inc(&devr->p0->usecnt); 4118 atomic_set(&devr->s1->usecnt, 0); 4119 4120 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) { 4121 INIT_WORK(&devr->ports[port].pkey_change_work, 4122 pkey_change_handler); 4123 devr->ports[port].devr = devr; 4124 } 4125 4126 return 0; 4127 4128 error5: 4129 mlx5_ib_destroy_srq(devr->s0); 4130 error4: 4131 mlx5_ib_dealloc_xrcd(devr->x1); 4132 error3: 4133 mlx5_ib_dealloc_xrcd(devr->x0); 4134 error2: 4135 mlx5_ib_destroy_cq(devr->c0); 4136 error1: 4137 mlx5_ib_dealloc_pd(devr->p0); 4138 error0: 4139 return ret; 4140 } 4141 4142 static void destroy_dev_resources(struct mlx5_ib_resources *devr) 4143 { 4144 struct mlx5_ib_dev *dev = 4145 container_of(devr, struct mlx5_ib_dev, devr); 4146 int port; 4147 4148 mlx5_ib_destroy_srq(devr->s1); 4149 mlx5_ib_destroy_srq(devr->s0); 4150 mlx5_ib_dealloc_xrcd(devr->x0); 4151 mlx5_ib_dealloc_xrcd(devr->x1); 4152 mlx5_ib_destroy_cq(devr->c0); 4153 mlx5_ib_dealloc_pd(devr->p0); 4154 4155 /* Make sure no change P_Key work items are still executing */ 4156 for (port = 0; port < dev->num_ports; ++port) 4157 cancel_work_sync(&devr->ports[port].pkey_change_work); 4158 } 4159 4160 static u32 get_core_cap_flags(struct ib_device *ibdev) 4161 { 4162 struct mlx5_ib_dev *dev = to_mdev(ibdev); 4163 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 4164 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 4165 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 4166 bool raw_support = !mlx5_core_mp_enabled(dev->mdev); 4167 u32 ret = 0; 4168 4169 if (ll == IB_LINK_LAYER_INFINIBAND) 4170 return RDMA_CORE_PORT_IBA_IB; 4171 4172 if (raw_support) 4173 ret = RDMA_CORE_PORT_RAW_PACKET; 4174 4175 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 4176 return ret; 4177 4178 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 4179 return ret; 4180 4181 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 4182 ret |= RDMA_CORE_PORT_IBA_ROCE; 4183 4184 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 4185 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 4186 4187 return ret; 4188 } 4189 4190 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num, 4191 struct ib_port_immutable *immutable) 4192 { 4193 struct ib_port_attr attr; 4194 struct mlx5_ib_dev *dev = to_mdev(ibdev); 4195 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num); 4196 int err; 4197 4198 immutable->core_cap_flags = get_core_cap_flags(ibdev); 4199 4200 err = ib_query_port(ibdev, port_num, &attr); 4201 if (err) 4202 return err; 4203 4204 immutable->pkey_tbl_len = attr.pkey_tbl_len; 4205 immutable->gid_tbl_len = attr.gid_tbl_len; 4206 immutable->core_cap_flags = get_core_cap_flags(ibdev); 4207 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce)) 4208 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 4209 4210 return 0; 4211 } 4212 4213 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num, 4214 struct ib_port_immutable *immutable) 4215 { 4216 struct ib_port_attr attr; 4217 int err; 4218 4219 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 4220 4221 err = ib_query_port(ibdev, port_num, &attr); 4222 if (err) 4223 return err; 4224 4225 immutable->pkey_tbl_len = attr.pkey_tbl_len; 4226 immutable->gid_tbl_len = attr.gid_tbl_len; 4227 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 4228 4229 return 0; 4230 } 4231 4232 static void get_dev_fw_str(struct ib_device *ibdev, char *str) 4233 { 4234 struct mlx5_ib_dev *dev = 4235 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 4236 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d", 4237 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev), 4238 fw_rev_sub(dev->mdev)); 4239 } 4240 4241 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev) 4242 { 4243 struct mlx5_core_dev *mdev = dev->mdev; 4244 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev, 4245 MLX5_FLOW_NAMESPACE_LAG); 4246 struct mlx5_flow_table *ft; 4247 int err; 4248 4249 if (!ns || !mlx5_lag_is_active(mdev)) 4250 return 0; 4251 4252 err = mlx5_cmd_create_vport_lag(mdev); 4253 if (err) 4254 return err; 4255 4256 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0); 4257 if (IS_ERR(ft)) { 4258 err = PTR_ERR(ft); 4259 goto err_destroy_vport_lag; 4260 } 4261 4262 dev->flow_db->lag_demux_ft = ft; 4263 return 0; 4264 4265 err_destroy_vport_lag: 4266 mlx5_cmd_destroy_vport_lag(mdev); 4267 return err; 4268 } 4269 4270 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev) 4271 { 4272 struct mlx5_core_dev *mdev = dev->mdev; 4273 4274 if (dev->flow_db->lag_demux_ft) { 4275 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft); 4276 dev->flow_db->lag_demux_ft = NULL; 4277 4278 mlx5_cmd_destroy_vport_lag(mdev); 4279 } 4280 } 4281 4282 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num) 4283 { 4284 int err; 4285 4286 dev->roce[port_num].nb.notifier_call = mlx5_netdev_event; 4287 err = register_netdevice_notifier(&dev->roce[port_num].nb); 4288 if (err) { 4289 dev->roce[port_num].nb.notifier_call = NULL; 4290 return err; 4291 } 4292 4293 return 0; 4294 } 4295 4296 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num) 4297 { 4298 if (dev->roce[port_num].nb.notifier_call) { 4299 unregister_netdevice_notifier(&dev->roce[port_num].nb); 4300 dev->roce[port_num].nb.notifier_call = NULL; 4301 } 4302 } 4303 4304 static int mlx5_enable_eth(struct mlx5_ib_dev *dev, u8 port_num) 4305 { 4306 int err; 4307 4308 if (MLX5_CAP_GEN(dev->mdev, roce)) { 4309 err = mlx5_nic_vport_enable_roce(dev->mdev); 4310 if (err) 4311 return err; 4312 } 4313 4314 err = mlx5_eth_lag_init(dev); 4315 if (err) 4316 goto err_disable_roce; 4317 4318 return 0; 4319 4320 err_disable_roce: 4321 if (MLX5_CAP_GEN(dev->mdev, roce)) 4322 mlx5_nic_vport_disable_roce(dev->mdev); 4323 4324 return err; 4325 } 4326 4327 static void mlx5_disable_eth(struct mlx5_ib_dev *dev) 4328 { 4329 mlx5_eth_lag_cleanup(dev); 4330 if (MLX5_CAP_GEN(dev->mdev, roce)) 4331 mlx5_nic_vport_disable_roce(dev->mdev); 4332 } 4333 4334 struct mlx5_ib_counter { 4335 const char *name; 4336 size_t offset; 4337 }; 4338 4339 #define INIT_Q_COUNTER(_name) \ 4340 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)} 4341 4342 static const struct mlx5_ib_counter basic_q_cnts[] = { 4343 INIT_Q_COUNTER(rx_write_requests), 4344 INIT_Q_COUNTER(rx_read_requests), 4345 INIT_Q_COUNTER(rx_atomic_requests), 4346 INIT_Q_COUNTER(out_of_buffer), 4347 }; 4348 4349 static const struct mlx5_ib_counter out_of_seq_q_cnts[] = { 4350 INIT_Q_COUNTER(out_of_sequence), 4351 }; 4352 4353 static const struct mlx5_ib_counter retrans_q_cnts[] = { 4354 INIT_Q_COUNTER(duplicate_request), 4355 INIT_Q_COUNTER(rnr_nak_retry_err), 4356 INIT_Q_COUNTER(packet_seq_err), 4357 INIT_Q_COUNTER(implied_nak_seq_err), 4358 INIT_Q_COUNTER(local_ack_timeout_err), 4359 }; 4360 4361 #define INIT_CONG_COUNTER(_name) \ 4362 { .name = #_name, .offset = \ 4363 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)} 4364 4365 static const struct mlx5_ib_counter cong_cnts[] = { 4366 INIT_CONG_COUNTER(rp_cnp_ignored), 4367 INIT_CONG_COUNTER(rp_cnp_handled), 4368 INIT_CONG_COUNTER(np_ecn_marked_roce_packets), 4369 INIT_CONG_COUNTER(np_cnp_sent), 4370 }; 4371 4372 static const struct mlx5_ib_counter extended_err_cnts[] = { 4373 INIT_Q_COUNTER(resp_local_length_error), 4374 INIT_Q_COUNTER(resp_cqe_error), 4375 INIT_Q_COUNTER(req_cqe_error), 4376 INIT_Q_COUNTER(req_remote_invalid_request), 4377 INIT_Q_COUNTER(req_remote_access_errors), 4378 INIT_Q_COUNTER(resp_remote_access_errors), 4379 INIT_Q_COUNTER(resp_cqe_flush_error), 4380 INIT_Q_COUNTER(req_cqe_flush_error), 4381 }; 4382 4383 static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev) 4384 { 4385 int i; 4386 4387 for (i = 0; i < dev->num_ports; i++) { 4388 if (dev->port[i].cnts.set_id) 4389 mlx5_core_dealloc_q_counter(dev->mdev, 4390 dev->port[i].cnts.set_id); 4391 kfree(dev->port[i].cnts.names); 4392 kfree(dev->port[i].cnts.offsets); 4393 } 4394 } 4395 4396 static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev, 4397 struct mlx5_ib_counters *cnts) 4398 { 4399 u32 num_counters; 4400 4401 num_counters = ARRAY_SIZE(basic_q_cnts); 4402 4403 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) 4404 num_counters += ARRAY_SIZE(out_of_seq_q_cnts); 4405 4406 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) 4407 num_counters += ARRAY_SIZE(retrans_q_cnts); 4408 4409 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) 4410 num_counters += ARRAY_SIZE(extended_err_cnts); 4411 4412 cnts->num_q_counters = num_counters; 4413 4414 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 4415 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts); 4416 num_counters += ARRAY_SIZE(cong_cnts); 4417 } 4418 4419 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL); 4420 if (!cnts->names) 4421 return -ENOMEM; 4422 4423 cnts->offsets = kcalloc(num_counters, 4424 sizeof(cnts->offsets), GFP_KERNEL); 4425 if (!cnts->offsets) 4426 goto err_names; 4427 4428 return 0; 4429 4430 err_names: 4431 kfree(cnts->names); 4432 cnts->names = NULL; 4433 return -ENOMEM; 4434 } 4435 4436 static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev, 4437 const char **names, 4438 size_t *offsets) 4439 { 4440 int i; 4441 int j = 0; 4442 4443 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) { 4444 names[j] = basic_q_cnts[i].name; 4445 offsets[j] = basic_q_cnts[i].offset; 4446 } 4447 4448 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) { 4449 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) { 4450 names[j] = out_of_seq_q_cnts[i].name; 4451 offsets[j] = out_of_seq_q_cnts[i].offset; 4452 } 4453 } 4454 4455 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) { 4456 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) { 4457 names[j] = retrans_q_cnts[i].name; 4458 offsets[j] = retrans_q_cnts[i].offset; 4459 } 4460 } 4461 4462 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) { 4463 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) { 4464 names[j] = extended_err_cnts[i].name; 4465 offsets[j] = extended_err_cnts[i].offset; 4466 } 4467 } 4468 4469 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 4470 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) { 4471 names[j] = cong_cnts[i].name; 4472 offsets[j] = cong_cnts[i].offset; 4473 } 4474 } 4475 } 4476 4477 static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev) 4478 { 4479 int err = 0; 4480 int i; 4481 4482 for (i = 0; i < dev->num_ports; i++) { 4483 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts); 4484 if (err) 4485 goto err_alloc; 4486 4487 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names, 4488 dev->port[i].cnts.offsets); 4489 4490 err = mlx5_core_alloc_q_counter(dev->mdev, 4491 &dev->port[i].cnts.set_id); 4492 if (err) { 4493 mlx5_ib_warn(dev, 4494 "couldn't allocate queue counter for port %d, err %d\n", 4495 i + 1, err); 4496 goto err_alloc; 4497 } 4498 dev->port[i].cnts.set_id_valid = true; 4499 } 4500 4501 return 0; 4502 4503 err_alloc: 4504 mlx5_ib_dealloc_counters(dev); 4505 return err; 4506 } 4507 4508 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev, 4509 u8 port_num) 4510 { 4511 struct mlx5_ib_dev *dev = to_mdev(ibdev); 4512 struct mlx5_ib_port *port = &dev->port[port_num - 1]; 4513 4514 /* We support only per port stats */ 4515 if (port_num == 0) 4516 return NULL; 4517 4518 return rdma_alloc_hw_stats_struct(port->cnts.names, 4519 port->cnts.num_q_counters + 4520 port->cnts.num_cong_counters, 4521 RDMA_HW_STATS_DEFAULT_LIFESPAN); 4522 } 4523 4524 static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev, 4525 struct mlx5_ib_port *port, 4526 struct rdma_hw_stats *stats) 4527 { 4528 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out); 4529 void *out; 4530 __be32 val; 4531 int ret, i; 4532 4533 out = kvzalloc(outlen, GFP_KERNEL); 4534 if (!out) 4535 return -ENOMEM; 4536 4537 ret = mlx5_core_query_q_counter(mdev, 4538 port->cnts.set_id, 0, 4539 out, outlen); 4540 if (ret) 4541 goto free; 4542 4543 for (i = 0; i < port->cnts.num_q_counters; i++) { 4544 val = *(__be32 *)(out + port->cnts.offsets[i]); 4545 stats->value[i] = (u64)be32_to_cpu(val); 4546 } 4547 4548 free: 4549 kvfree(out); 4550 return ret; 4551 } 4552 4553 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev, 4554 struct rdma_hw_stats *stats, 4555 u8 port_num, int index) 4556 { 4557 struct mlx5_ib_dev *dev = to_mdev(ibdev); 4558 struct mlx5_ib_port *port = &dev->port[port_num - 1]; 4559 struct mlx5_core_dev *mdev; 4560 int ret, num_counters; 4561 u8 mdev_port_num; 4562 4563 if (!stats) 4564 return -EINVAL; 4565 4566 num_counters = port->cnts.num_q_counters + port->cnts.num_cong_counters; 4567 4568 /* q_counters are per IB device, query the master mdev */ 4569 ret = mlx5_ib_query_q_counters(dev->mdev, port, stats); 4570 if (ret) 4571 return ret; 4572 4573 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) { 4574 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, 4575 &mdev_port_num); 4576 if (!mdev) { 4577 /* If port is not affiliated yet, its in down state 4578 * which doesn't have any counters yet, so it would be 4579 * zero. So no need to read from the HCA. 4580 */ 4581 goto done; 4582 } 4583 ret = mlx5_lag_query_cong_counters(dev->mdev, 4584 stats->value + 4585 port->cnts.num_q_counters, 4586 port->cnts.num_cong_counters, 4587 port->cnts.offsets + 4588 port->cnts.num_q_counters); 4589 4590 mlx5_ib_put_native_port_mdev(dev, port_num); 4591 if (ret) 4592 return ret; 4593 } 4594 4595 done: 4596 return num_counters; 4597 } 4598 4599 static void mlx5_ib_free_rdma_netdev(struct net_device *netdev) 4600 { 4601 return mlx5_rdma_netdev_free(netdev); 4602 } 4603 4604 static struct net_device* 4605 mlx5_ib_alloc_rdma_netdev(struct ib_device *hca, 4606 u8 port_num, 4607 enum rdma_netdev_t type, 4608 const char *name, 4609 unsigned char name_assign_type, 4610 void (*setup)(struct net_device *)) 4611 { 4612 struct net_device *netdev; 4613 struct rdma_netdev *rn; 4614 4615 if (type != RDMA_NETDEV_IPOIB) 4616 return ERR_PTR(-EOPNOTSUPP); 4617 4618 netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca, 4619 name, setup); 4620 if (likely(!IS_ERR_OR_NULL(netdev))) { 4621 rn = netdev_priv(netdev); 4622 rn->free_rdma_netdev = mlx5_ib_free_rdma_netdev; 4623 } 4624 return netdev; 4625 } 4626 4627 static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev) 4628 { 4629 if (!dev->delay_drop.dbg) 4630 return; 4631 debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs); 4632 kfree(dev->delay_drop.dbg); 4633 dev->delay_drop.dbg = NULL; 4634 } 4635 4636 static void cancel_delay_drop(struct mlx5_ib_dev *dev) 4637 { 4638 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4639 return; 4640 4641 cancel_work_sync(&dev->delay_drop.delay_drop_work); 4642 delay_drop_debugfs_cleanup(dev); 4643 } 4644 4645 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf, 4646 size_t count, loff_t *pos) 4647 { 4648 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 4649 char lbuf[20]; 4650 int len; 4651 4652 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout); 4653 return simple_read_from_buffer(buf, count, pos, lbuf, len); 4654 } 4655 4656 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf, 4657 size_t count, loff_t *pos) 4658 { 4659 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 4660 u32 timeout; 4661 u32 var; 4662 4663 if (kstrtouint_from_user(buf, count, 0, &var)) 4664 return -EFAULT; 4665 4666 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 4667 1000); 4668 if (timeout != var) 4669 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n", 4670 timeout); 4671 4672 delay_drop->timeout = timeout; 4673 4674 return count; 4675 } 4676 4677 static const struct file_operations fops_delay_drop_timeout = { 4678 .owner = THIS_MODULE, 4679 .open = simple_open, 4680 .write = delay_drop_timeout_write, 4681 .read = delay_drop_timeout_read, 4682 }; 4683 4684 static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev) 4685 { 4686 struct mlx5_ib_dbg_delay_drop *dbg; 4687 4688 if (!mlx5_debugfs_root) 4689 return 0; 4690 4691 dbg = kzalloc(sizeof(*dbg), GFP_KERNEL); 4692 if (!dbg) 4693 return -ENOMEM; 4694 4695 dev->delay_drop.dbg = dbg; 4696 4697 dbg->dir_debugfs = 4698 debugfs_create_dir("delay_drop", 4699 dev->mdev->priv.dbg_root); 4700 if (!dbg->dir_debugfs) 4701 goto out_debugfs; 4702 4703 dbg->events_cnt_debugfs = 4704 debugfs_create_atomic_t("num_timeout_events", 0400, 4705 dbg->dir_debugfs, 4706 &dev->delay_drop.events_cnt); 4707 if (!dbg->events_cnt_debugfs) 4708 goto out_debugfs; 4709 4710 dbg->rqs_cnt_debugfs = 4711 debugfs_create_atomic_t("num_rqs", 0400, 4712 dbg->dir_debugfs, 4713 &dev->delay_drop.rqs_cnt); 4714 if (!dbg->rqs_cnt_debugfs) 4715 goto out_debugfs; 4716 4717 dbg->timeout_debugfs = 4718 debugfs_create_file("timeout", 0600, 4719 dbg->dir_debugfs, 4720 &dev->delay_drop, 4721 &fops_delay_drop_timeout); 4722 if (!dbg->timeout_debugfs) 4723 goto out_debugfs; 4724 4725 return 0; 4726 4727 out_debugfs: 4728 delay_drop_debugfs_cleanup(dev); 4729 return -ENOMEM; 4730 } 4731 4732 static void init_delay_drop(struct mlx5_ib_dev *dev) 4733 { 4734 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4735 return; 4736 4737 mutex_init(&dev->delay_drop.lock); 4738 dev->delay_drop.dev = dev; 4739 dev->delay_drop.activate = false; 4740 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000; 4741 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler); 4742 atomic_set(&dev->delay_drop.rqs_cnt, 0); 4743 atomic_set(&dev->delay_drop.events_cnt, 0); 4744 4745 if (delay_drop_debugfs_init(dev)) 4746 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n"); 4747 } 4748 4749 static const struct cpumask * 4750 mlx5_ib_get_vector_affinity(struct ib_device *ibdev, int comp_vector) 4751 { 4752 struct mlx5_ib_dev *dev = to_mdev(ibdev); 4753 4754 return mlx5_get_vector_affinity(dev->mdev, comp_vector); 4755 } 4756 4757 /* The mlx5_ib_multiport_mutex should be held when calling this function */ 4758 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev, 4759 struct mlx5_ib_multiport_info *mpi) 4760 { 4761 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 4762 struct mlx5_ib_port *port = &ibdev->port[port_num]; 4763 int comps; 4764 int err; 4765 int i; 4766 4767 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num); 4768 4769 spin_lock(&port->mp.mpi_lock); 4770 if (!mpi->ibdev) { 4771 spin_unlock(&port->mp.mpi_lock); 4772 return; 4773 } 4774 mpi->ibdev = NULL; 4775 4776 spin_unlock(&port->mp.mpi_lock); 4777 mlx5_remove_netdev_notifier(ibdev, port_num); 4778 spin_lock(&port->mp.mpi_lock); 4779 4780 comps = mpi->mdev_refcnt; 4781 if (comps) { 4782 mpi->unaffiliate = true; 4783 init_completion(&mpi->unref_comp); 4784 spin_unlock(&port->mp.mpi_lock); 4785 4786 for (i = 0; i < comps; i++) 4787 wait_for_completion(&mpi->unref_comp); 4788 4789 spin_lock(&port->mp.mpi_lock); 4790 mpi->unaffiliate = false; 4791 } 4792 4793 port->mp.mpi = NULL; 4794 4795 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 4796 4797 spin_unlock(&port->mp.mpi_lock); 4798 4799 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev); 4800 4801 mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1); 4802 /* Log an error, still needed to cleanup the pointers and add 4803 * it back to the list. 4804 */ 4805 if (err) 4806 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n", 4807 port_num + 1); 4808 4809 ibdev->roce[port_num].last_port_state = IB_PORT_DOWN; 4810 } 4811 4812 /* The mlx5_ib_multiport_mutex should be held when calling this function */ 4813 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev, 4814 struct mlx5_ib_multiport_info *mpi) 4815 { 4816 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 4817 int err; 4818 4819 spin_lock(&ibdev->port[port_num].mp.mpi_lock); 4820 if (ibdev->port[port_num].mp.mpi) { 4821 mlx5_ib_warn(ibdev, "port %d already affiliated.\n", 4822 port_num + 1); 4823 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 4824 return false; 4825 } 4826 4827 ibdev->port[port_num].mp.mpi = mpi; 4828 mpi->ibdev = ibdev; 4829 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 4830 4831 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev); 4832 if (err) 4833 goto unbind; 4834 4835 err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev)); 4836 if (err) 4837 goto unbind; 4838 4839 err = mlx5_add_netdev_notifier(ibdev, port_num); 4840 if (err) { 4841 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n", 4842 port_num + 1); 4843 goto unbind; 4844 } 4845 4846 err = mlx5_ib_init_cong_debugfs(ibdev, port_num); 4847 if (err) 4848 goto unbind; 4849 4850 return true; 4851 4852 unbind: 4853 mlx5_ib_unbind_slave_port(ibdev, mpi); 4854 return false; 4855 } 4856 4857 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev) 4858 { 4859 int port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4860 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 4861 port_num + 1); 4862 struct mlx5_ib_multiport_info *mpi; 4863 int err; 4864 int i; 4865 4866 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 4867 return 0; 4868 4869 err = mlx5_query_nic_vport_system_image_guid(dev->mdev, 4870 &dev->sys_image_guid); 4871 if (err) 4872 return err; 4873 4874 err = mlx5_nic_vport_enable_roce(dev->mdev); 4875 if (err) 4876 return err; 4877 4878 mutex_lock(&mlx5_ib_multiport_mutex); 4879 for (i = 0; i < dev->num_ports; i++) { 4880 bool bound = false; 4881 4882 /* build a stub multiport info struct for the native port. */ 4883 if (i == port_num) { 4884 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 4885 if (!mpi) { 4886 mutex_unlock(&mlx5_ib_multiport_mutex); 4887 mlx5_nic_vport_disable_roce(dev->mdev); 4888 return -ENOMEM; 4889 } 4890 4891 mpi->is_master = true; 4892 mpi->mdev = dev->mdev; 4893 mpi->sys_image_guid = dev->sys_image_guid; 4894 dev->port[i].mp.mpi = mpi; 4895 mpi->ibdev = dev; 4896 mpi = NULL; 4897 continue; 4898 } 4899 4900 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list, 4901 list) { 4902 if (dev->sys_image_guid == mpi->sys_image_guid && 4903 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) { 4904 bound = mlx5_ib_bind_slave_port(dev, mpi); 4905 } 4906 4907 if (bound) { 4908 dev_dbg(&mpi->mdev->pdev->dev, "removing port from unaffiliated list.\n"); 4909 mlx5_ib_dbg(dev, "port %d bound\n", i + 1); 4910 list_del(&mpi->list); 4911 break; 4912 } 4913 } 4914 if (!bound) { 4915 get_port_caps(dev, i + 1); 4916 mlx5_ib_dbg(dev, "no free port found for port %d\n", 4917 i + 1); 4918 } 4919 } 4920 4921 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list); 4922 mutex_unlock(&mlx5_ib_multiport_mutex); 4923 return err; 4924 } 4925 4926 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev) 4927 { 4928 int port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4929 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 4930 port_num + 1); 4931 int i; 4932 4933 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 4934 return; 4935 4936 mutex_lock(&mlx5_ib_multiport_mutex); 4937 for (i = 0; i < dev->num_ports; i++) { 4938 if (dev->port[i].mp.mpi) { 4939 /* Destroy the native port stub */ 4940 if (i == port_num) { 4941 kfree(dev->port[i].mp.mpi); 4942 dev->port[i].mp.mpi = NULL; 4943 } else { 4944 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1); 4945 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi); 4946 } 4947 } 4948 } 4949 4950 mlx5_ib_dbg(dev, "removing from devlist\n"); 4951 list_del(&dev->ib_dev_list); 4952 mutex_unlock(&mlx5_ib_multiport_mutex); 4953 4954 mlx5_nic_vport_disable_roce(dev->mdev); 4955 } 4956 4957 ADD_UVERBS_ATTRIBUTES_SIMPLE(mlx5_ib_dm, UVERBS_OBJECT_DM, 4958 UVERBS_METHOD_DM_ALLOC, 4959 &UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET, 4960 UVERBS_ATTR_TYPE(u64), 4961 UA_FLAGS(UVERBS_ATTR_SPEC_F_MANDATORY)), 4962 &UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX, 4963 UVERBS_ATTR_TYPE(u16), 4964 UA_FLAGS(UVERBS_ATTR_SPEC_F_MANDATORY))); 4965 4966 ADD_UVERBS_ATTRIBUTES_SIMPLE(mlx5_ib_flow_action, UVERBS_OBJECT_FLOW_ACTION, 4967 UVERBS_METHOD_FLOW_ACTION_ESP_CREATE, 4968 &UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS, 4969 UVERBS_ATTR_TYPE(u64), 4970 UA_FLAGS(UVERBS_ATTR_SPEC_F_MANDATORY))); 4971 4972 #define NUM_TREES 2 4973 static int populate_specs_root(struct mlx5_ib_dev *dev) 4974 { 4975 const struct uverbs_object_tree_def *default_root[NUM_TREES + 1] = { 4976 uverbs_default_get_objects()}; 4977 size_t num_trees = 1; 4978 4979 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE && 4980 !WARN_ON(num_trees >= ARRAY_SIZE(default_root))) 4981 default_root[num_trees++] = &mlx5_ib_flow_action; 4982 4983 if (MLX5_CAP_DEV_MEM(dev->mdev, memic) && 4984 !WARN_ON(num_trees >= ARRAY_SIZE(default_root))) 4985 default_root[num_trees++] = &mlx5_ib_dm; 4986 4987 dev->ib_dev.specs_root = 4988 uverbs_alloc_spec_tree(num_trees, default_root); 4989 4990 return PTR_ERR_OR_ZERO(dev->ib_dev.specs_root); 4991 } 4992 4993 static void depopulate_specs_root(struct mlx5_ib_dev *dev) 4994 { 4995 uverbs_free_spec_tree(dev->ib_dev.specs_root); 4996 } 4997 4998 void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev) 4999 { 5000 mlx5_ib_cleanup_multiport_master(dev); 5001 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 5002 cleanup_srcu_struct(&dev->mr_srcu); 5003 #endif 5004 kfree(dev->port); 5005 } 5006 5007 int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev) 5008 { 5009 struct mlx5_core_dev *mdev = dev->mdev; 5010 const char *name; 5011 int err; 5012 int i; 5013 5014 dev->port = kcalloc(dev->num_ports, sizeof(*dev->port), 5015 GFP_KERNEL); 5016 if (!dev->port) 5017 return -ENOMEM; 5018 5019 for (i = 0; i < dev->num_ports; i++) { 5020 spin_lock_init(&dev->port[i].mp.mpi_lock); 5021 rwlock_init(&dev->roce[i].netdev_lock); 5022 } 5023 5024 err = mlx5_ib_init_multiport_master(dev); 5025 if (err) 5026 goto err_free_port; 5027 5028 if (!mlx5_core_mp_enabled(mdev)) { 5029 for (i = 1; i <= dev->num_ports; i++) { 5030 err = get_port_caps(dev, i); 5031 if (err) 5032 break; 5033 } 5034 } else { 5035 err = get_port_caps(dev, mlx5_core_native_port_num(mdev)); 5036 } 5037 if (err) 5038 goto err_mp; 5039 5040 if (mlx5_use_mad_ifc(dev)) 5041 get_ext_port_caps(dev); 5042 5043 if (!mlx5_lag_is_active(mdev)) 5044 name = "mlx5_%d"; 5045 else 5046 name = "mlx5_bond_%d"; 5047 5048 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX); 5049 dev->ib_dev.owner = THIS_MODULE; 5050 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 5051 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 5052 dev->ib_dev.phys_port_cnt = dev->num_ports; 5053 dev->ib_dev.num_comp_vectors = 5054 dev->mdev->priv.eq_table.num_comp_vectors; 5055 dev->ib_dev.dev.parent = &mdev->pdev->dev; 5056 5057 mutex_init(&dev->cap_mask_mutex); 5058 INIT_LIST_HEAD(&dev->qp_list); 5059 spin_lock_init(&dev->reset_flow_resource_lock); 5060 5061 spin_lock_init(&dev->memic.memic_lock); 5062 dev->memic.dev = mdev; 5063 5064 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 5065 err = init_srcu_struct(&dev->mr_srcu); 5066 if (err) 5067 goto err_free_port; 5068 #endif 5069 5070 return 0; 5071 err_mp: 5072 mlx5_ib_cleanup_multiport_master(dev); 5073 5074 err_free_port: 5075 kfree(dev->port); 5076 5077 return -ENOMEM; 5078 } 5079 5080 static int mlx5_ib_stage_flow_db_init(struct mlx5_ib_dev *dev) 5081 { 5082 dev->flow_db = kzalloc(sizeof(*dev->flow_db), GFP_KERNEL); 5083 5084 if (!dev->flow_db) 5085 return -ENOMEM; 5086 5087 mutex_init(&dev->flow_db->lock); 5088 5089 return 0; 5090 } 5091 5092 int mlx5_ib_stage_rep_flow_db_init(struct mlx5_ib_dev *dev) 5093 { 5094 struct mlx5_ib_dev *nic_dev; 5095 5096 nic_dev = mlx5_ib_get_uplink_ibdev(dev->mdev->priv.eswitch); 5097 5098 if (!nic_dev) 5099 return -EINVAL; 5100 5101 dev->flow_db = nic_dev->flow_db; 5102 5103 return 0; 5104 } 5105 5106 static void mlx5_ib_stage_flow_db_cleanup(struct mlx5_ib_dev *dev) 5107 { 5108 kfree(dev->flow_db); 5109 } 5110 5111 int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev) 5112 { 5113 struct mlx5_core_dev *mdev = dev->mdev; 5114 int err; 5115 5116 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION; 5117 dev->ib_dev.uverbs_cmd_mask = 5118 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | 5119 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | 5120 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | 5121 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | 5122 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | 5123 (1ull << IB_USER_VERBS_CMD_CREATE_AH) | 5124 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) | 5125 (1ull << IB_USER_VERBS_CMD_REG_MR) | 5126 (1ull << IB_USER_VERBS_CMD_REREG_MR) | 5127 (1ull << IB_USER_VERBS_CMD_DEREG_MR) | 5128 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 5129 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | 5130 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) | 5131 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | 5132 (1ull << IB_USER_VERBS_CMD_CREATE_QP) | 5133 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | 5134 (1ull << IB_USER_VERBS_CMD_QUERY_QP) | 5135 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | 5136 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) | 5137 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) | 5138 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | 5139 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | 5140 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | 5141 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | 5142 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) | 5143 (1ull << IB_USER_VERBS_CMD_OPEN_QP); 5144 dev->ib_dev.uverbs_ex_cmd_mask = 5145 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) | 5146 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) | 5147 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) | 5148 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP) | 5149 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ); 5150 5151 dev->ib_dev.query_device = mlx5_ib_query_device; 5152 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer; 5153 dev->ib_dev.query_gid = mlx5_ib_query_gid; 5154 dev->ib_dev.add_gid = mlx5_ib_add_gid; 5155 dev->ib_dev.del_gid = mlx5_ib_del_gid; 5156 dev->ib_dev.query_pkey = mlx5_ib_query_pkey; 5157 dev->ib_dev.modify_device = mlx5_ib_modify_device; 5158 dev->ib_dev.modify_port = mlx5_ib_modify_port; 5159 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext; 5160 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext; 5161 dev->ib_dev.mmap = mlx5_ib_mmap; 5162 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd; 5163 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd; 5164 dev->ib_dev.create_ah = mlx5_ib_create_ah; 5165 dev->ib_dev.query_ah = mlx5_ib_query_ah; 5166 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah; 5167 dev->ib_dev.create_srq = mlx5_ib_create_srq; 5168 dev->ib_dev.modify_srq = mlx5_ib_modify_srq; 5169 dev->ib_dev.query_srq = mlx5_ib_query_srq; 5170 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq; 5171 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv; 5172 dev->ib_dev.create_qp = mlx5_ib_create_qp; 5173 dev->ib_dev.modify_qp = mlx5_ib_modify_qp; 5174 dev->ib_dev.query_qp = mlx5_ib_query_qp; 5175 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp; 5176 dev->ib_dev.post_send = mlx5_ib_post_send; 5177 dev->ib_dev.post_recv = mlx5_ib_post_recv; 5178 dev->ib_dev.create_cq = mlx5_ib_create_cq; 5179 dev->ib_dev.modify_cq = mlx5_ib_modify_cq; 5180 dev->ib_dev.resize_cq = mlx5_ib_resize_cq; 5181 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq; 5182 dev->ib_dev.poll_cq = mlx5_ib_poll_cq; 5183 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq; 5184 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr; 5185 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr; 5186 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr; 5187 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr; 5188 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach; 5189 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach; 5190 dev->ib_dev.process_mad = mlx5_ib_process_mad; 5191 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr; 5192 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg; 5193 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status; 5194 dev->ib_dev.get_dev_fw_str = get_dev_fw_str; 5195 dev->ib_dev.get_vector_affinity = mlx5_ib_get_vector_affinity; 5196 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads)) 5197 dev->ib_dev.alloc_rdma_netdev = mlx5_ib_alloc_rdma_netdev; 5198 5199 if (mlx5_core_is_pf(mdev)) { 5200 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config; 5201 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state; 5202 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats; 5203 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid; 5204 } 5205 5206 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext; 5207 5208 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence)); 5209 5210 if (MLX5_CAP_GEN(mdev, imaicl)) { 5211 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw; 5212 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw; 5213 dev->ib_dev.uverbs_cmd_mask |= 5214 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) | 5215 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW); 5216 } 5217 5218 if (MLX5_CAP_GEN(mdev, xrc)) { 5219 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd; 5220 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd; 5221 dev->ib_dev.uverbs_cmd_mask |= 5222 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) | 5223 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD); 5224 } 5225 5226 if (MLX5_CAP_DEV_MEM(mdev, memic)) { 5227 dev->ib_dev.alloc_dm = mlx5_ib_alloc_dm; 5228 dev->ib_dev.dealloc_dm = mlx5_ib_dealloc_dm; 5229 } 5230 5231 dev->ib_dev.create_flow = mlx5_ib_create_flow; 5232 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow; 5233 dev->ib_dev.uverbs_ex_cmd_mask |= 5234 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) | 5235 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW); 5236 dev->ib_dev.create_flow_action_esp = mlx5_ib_create_flow_action_esp; 5237 dev->ib_dev.destroy_flow_action = mlx5_ib_destroy_flow_action; 5238 dev->ib_dev.modify_flow_action_esp = mlx5_ib_modify_flow_action_esp; 5239 dev->ib_dev.driver_id = RDMA_DRIVER_MLX5; 5240 5241 err = init_node_data(dev); 5242 if (err) 5243 return err; 5244 5245 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && 5246 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) || 5247 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 5248 mutex_init(&dev->lb_mutex); 5249 5250 return 0; 5251 } 5252 5253 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev) 5254 { 5255 dev->ib_dev.get_port_immutable = mlx5_port_immutable; 5256 dev->ib_dev.query_port = mlx5_ib_query_port; 5257 5258 return 0; 5259 } 5260 5261 int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev) 5262 { 5263 dev->ib_dev.get_port_immutable = mlx5_port_rep_immutable; 5264 dev->ib_dev.query_port = mlx5_ib_rep_query_port; 5265 5266 return 0; 5267 } 5268 5269 static int mlx5_ib_stage_common_roce_init(struct mlx5_ib_dev *dev, 5270 u8 port_num) 5271 { 5272 int i; 5273 5274 for (i = 0; i < dev->num_ports; i++) { 5275 dev->roce[i].dev = dev; 5276 dev->roce[i].native_port_num = i + 1; 5277 dev->roce[i].last_port_state = IB_PORT_DOWN; 5278 } 5279 5280 dev->ib_dev.get_netdev = mlx5_ib_get_netdev; 5281 dev->ib_dev.create_wq = mlx5_ib_create_wq; 5282 dev->ib_dev.modify_wq = mlx5_ib_modify_wq; 5283 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq; 5284 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table; 5285 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table; 5286 5287 dev->ib_dev.uverbs_ex_cmd_mask |= 5288 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) | 5289 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) | 5290 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) | 5291 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) | 5292 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL); 5293 5294 return mlx5_add_netdev_notifier(dev, port_num); 5295 } 5296 5297 static void mlx5_ib_stage_common_roce_cleanup(struct mlx5_ib_dev *dev) 5298 { 5299 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 5300 5301 mlx5_remove_netdev_notifier(dev, port_num); 5302 } 5303 5304 int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev) 5305 { 5306 struct mlx5_core_dev *mdev = dev->mdev; 5307 enum rdma_link_layer ll; 5308 int port_type_cap; 5309 int err = 0; 5310 u8 port_num; 5311 5312 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 5313 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 5314 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 5315 5316 if (ll == IB_LINK_LAYER_ETHERNET) 5317 err = mlx5_ib_stage_common_roce_init(dev, port_num); 5318 5319 return err; 5320 } 5321 5322 void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev) 5323 { 5324 mlx5_ib_stage_common_roce_cleanup(dev); 5325 } 5326 5327 static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev) 5328 { 5329 struct mlx5_core_dev *mdev = dev->mdev; 5330 enum rdma_link_layer ll; 5331 int port_type_cap; 5332 u8 port_num; 5333 int err; 5334 5335 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 5336 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 5337 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 5338 5339 if (ll == IB_LINK_LAYER_ETHERNET) { 5340 err = mlx5_ib_stage_common_roce_init(dev, port_num); 5341 if (err) 5342 return err; 5343 5344 err = mlx5_enable_eth(dev, port_num); 5345 if (err) 5346 goto cleanup; 5347 } 5348 5349 return 0; 5350 cleanup: 5351 mlx5_ib_stage_common_roce_cleanup(dev); 5352 5353 return err; 5354 } 5355 5356 static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev) 5357 { 5358 struct mlx5_core_dev *mdev = dev->mdev; 5359 enum rdma_link_layer ll; 5360 int port_type_cap; 5361 u8 port_num; 5362 5363 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 5364 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 5365 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 5366 5367 if (ll == IB_LINK_LAYER_ETHERNET) { 5368 mlx5_disable_eth(dev); 5369 mlx5_ib_stage_common_roce_cleanup(dev); 5370 } 5371 } 5372 5373 int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev) 5374 { 5375 return create_dev_resources(&dev->devr); 5376 } 5377 5378 void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev) 5379 { 5380 destroy_dev_resources(&dev->devr); 5381 } 5382 5383 static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev) 5384 { 5385 mlx5_ib_internal_fill_odp_caps(dev); 5386 5387 return mlx5_ib_odp_init_one(dev); 5388 } 5389 5390 int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev) 5391 { 5392 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) { 5393 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats; 5394 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats; 5395 5396 return mlx5_ib_alloc_counters(dev); 5397 } 5398 5399 return 0; 5400 } 5401 5402 void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev) 5403 { 5404 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) 5405 mlx5_ib_dealloc_counters(dev); 5406 } 5407 5408 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev) 5409 { 5410 return mlx5_ib_init_cong_debugfs(dev, 5411 mlx5_core_native_port_num(dev->mdev) - 1); 5412 } 5413 5414 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev) 5415 { 5416 mlx5_ib_cleanup_cong_debugfs(dev, 5417 mlx5_core_native_port_num(dev->mdev) - 1); 5418 } 5419 5420 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev) 5421 { 5422 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev); 5423 if (!dev->mdev->priv.uar) 5424 return -ENOMEM; 5425 return 0; 5426 } 5427 5428 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev) 5429 { 5430 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar); 5431 } 5432 5433 int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev) 5434 { 5435 int err; 5436 5437 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false); 5438 if (err) 5439 return err; 5440 5441 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true); 5442 if (err) 5443 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 5444 5445 return err; 5446 } 5447 5448 void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev) 5449 { 5450 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 5451 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 5452 } 5453 5454 static int mlx5_ib_stage_populate_specs(struct mlx5_ib_dev *dev) 5455 { 5456 return populate_specs_root(dev); 5457 } 5458 5459 int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev) 5460 { 5461 return ib_register_device(&dev->ib_dev, NULL); 5462 } 5463 5464 static void mlx5_ib_stage_depopulate_specs(struct mlx5_ib_dev *dev) 5465 { 5466 depopulate_specs_root(dev); 5467 } 5468 5469 void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev) 5470 { 5471 destroy_umrc_res(dev); 5472 } 5473 5474 void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev) 5475 { 5476 ib_unregister_device(&dev->ib_dev); 5477 } 5478 5479 int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev) 5480 { 5481 return create_umr_res(dev); 5482 } 5483 5484 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev) 5485 { 5486 init_delay_drop(dev); 5487 5488 return 0; 5489 } 5490 5491 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev) 5492 { 5493 cancel_delay_drop(dev); 5494 } 5495 5496 int mlx5_ib_stage_class_attr_init(struct mlx5_ib_dev *dev) 5497 { 5498 int err; 5499 int i; 5500 5501 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) { 5502 err = device_create_file(&dev->ib_dev.dev, 5503 mlx5_class_attributes[i]); 5504 if (err) 5505 return err; 5506 } 5507 5508 return 0; 5509 } 5510 5511 static int mlx5_ib_stage_rep_reg_init(struct mlx5_ib_dev *dev) 5512 { 5513 mlx5_ib_register_vport_reps(dev); 5514 5515 return 0; 5516 } 5517 5518 static void mlx5_ib_stage_rep_reg_cleanup(struct mlx5_ib_dev *dev) 5519 { 5520 mlx5_ib_unregister_vport_reps(dev); 5521 } 5522 5523 void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 5524 const struct mlx5_ib_profile *profile, 5525 int stage) 5526 { 5527 /* Number of stages to cleanup */ 5528 while (stage) { 5529 stage--; 5530 if (profile->stage[stage].cleanup) 5531 profile->stage[stage].cleanup(dev); 5532 } 5533 5534 ib_dealloc_device((struct ib_device *)dev); 5535 } 5536 5537 static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev, u8 port_num); 5538 5539 void *__mlx5_ib_add(struct mlx5_ib_dev *dev, 5540 const struct mlx5_ib_profile *profile) 5541 { 5542 int err; 5543 int i; 5544 5545 printk_once(KERN_INFO "%s", mlx5_version); 5546 5547 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) { 5548 if (profile->stage[i].init) { 5549 err = profile->stage[i].init(dev); 5550 if (err) 5551 goto err_out; 5552 } 5553 } 5554 5555 dev->profile = profile; 5556 dev->ib_active = true; 5557 5558 return dev; 5559 5560 err_out: 5561 __mlx5_ib_remove(dev, profile, i); 5562 5563 return NULL; 5564 } 5565 5566 static const struct mlx5_ib_profile pf_profile = { 5567 STAGE_CREATE(MLX5_IB_STAGE_INIT, 5568 mlx5_ib_stage_init_init, 5569 mlx5_ib_stage_init_cleanup), 5570 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB, 5571 mlx5_ib_stage_flow_db_init, 5572 mlx5_ib_stage_flow_db_cleanup), 5573 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 5574 mlx5_ib_stage_caps_init, 5575 NULL), 5576 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 5577 mlx5_ib_stage_non_default_cb, 5578 NULL), 5579 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 5580 mlx5_ib_stage_roce_init, 5581 mlx5_ib_stage_roce_cleanup), 5582 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 5583 mlx5_ib_stage_dev_res_init, 5584 mlx5_ib_stage_dev_res_cleanup), 5585 STAGE_CREATE(MLX5_IB_STAGE_ODP, 5586 mlx5_ib_stage_odp_init, 5587 NULL), 5588 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 5589 mlx5_ib_stage_counters_init, 5590 mlx5_ib_stage_counters_cleanup), 5591 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 5592 mlx5_ib_stage_cong_debugfs_init, 5593 mlx5_ib_stage_cong_debugfs_cleanup), 5594 STAGE_CREATE(MLX5_IB_STAGE_UAR, 5595 mlx5_ib_stage_uar_init, 5596 mlx5_ib_stage_uar_cleanup), 5597 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 5598 mlx5_ib_stage_bfrag_init, 5599 mlx5_ib_stage_bfrag_cleanup), 5600 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 5601 NULL, 5602 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 5603 STAGE_CREATE(MLX5_IB_STAGE_SPECS, 5604 mlx5_ib_stage_populate_specs, 5605 mlx5_ib_stage_depopulate_specs), 5606 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 5607 mlx5_ib_stage_ib_reg_init, 5608 mlx5_ib_stage_ib_reg_cleanup), 5609 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 5610 mlx5_ib_stage_post_ib_reg_umr_init, 5611 NULL), 5612 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP, 5613 mlx5_ib_stage_delay_drop_init, 5614 mlx5_ib_stage_delay_drop_cleanup), 5615 STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR, 5616 mlx5_ib_stage_class_attr_init, 5617 NULL), 5618 }; 5619 5620 static const struct mlx5_ib_profile nic_rep_profile = { 5621 STAGE_CREATE(MLX5_IB_STAGE_INIT, 5622 mlx5_ib_stage_init_init, 5623 mlx5_ib_stage_init_cleanup), 5624 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB, 5625 mlx5_ib_stage_flow_db_init, 5626 mlx5_ib_stage_flow_db_cleanup), 5627 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 5628 mlx5_ib_stage_caps_init, 5629 NULL), 5630 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 5631 mlx5_ib_stage_rep_non_default_cb, 5632 NULL), 5633 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 5634 mlx5_ib_stage_rep_roce_init, 5635 mlx5_ib_stage_rep_roce_cleanup), 5636 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 5637 mlx5_ib_stage_dev_res_init, 5638 mlx5_ib_stage_dev_res_cleanup), 5639 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 5640 mlx5_ib_stage_counters_init, 5641 mlx5_ib_stage_counters_cleanup), 5642 STAGE_CREATE(MLX5_IB_STAGE_UAR, 5643 mlx5_ib_stage_uar_init, 5644 mlx5_ib_stage_uar_cleanup), 5645 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 5646 mlx5_ib_stage_bfrag_init, 5647 mlx5_ib_stage_bfrag_cleanup), 5648 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 5649 NULL, 5650 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 5651 STAGE_CREATE(MLX5_IB_STAGE_SPECS, 5652 mlx5_ib_stage_populate_specs, 5653 mlx5_ib_stage_depopulate_specs), 5654 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 5655 mlx5_ib_stage_ib_reg_init, 5656 mlx5_ib_stage_ib_reg_cleanup), 5657 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 5658 mlx5_ib_stage_post_ib_reg_umr_init, 5659 NULL), 5660 STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR, 5661 mlx5_ib_stage_class_attr_init, 5662 NULL), 5663 STAGE_CREATE(MLX5_IB_STAGE_REP_REG, 5664 mlx5_ib_stage_rep_reg_init, 5665 mlx5_ib_stage_rep_reg_cleanup), 5666 }; 5667 5668 static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev, u8 port_num) 5669 { 5670 struct mlx5_ib_multiport_info *mpi; 5671 struct mlx5_ib_dev *dev; 5672 bool bound = false; 5673 int err; 5674 5675 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 5676 if (!mpi) 5677 return NULL; 5678 5679 mpi->mdev = mdev; 5680 5681 err = mlx5_query_nic_vport_system_image_guid(mdev, 5682 &mpi->sys_image_guid); 5683 if (err) { 5684 kfree(mpi); 5685 return NULL; 5686 } 5687 5688 mutex_lock(&mlx5_ib_multiport_mutex); 5689 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) { 5690 if (dev->sys_image_guid == mpi->sys_image_guid) 5691 bound = mlx5_ib_bind_slave_port(dev, mpi); 5692 5693 if (bound) { 5694 rdma_roce_rescan_device(&dev->ib_dev); 5695 break; 5696 } 5697 } 5698 5699 if (!bound) { 5700 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 5701 dev_dbg(&mdev->pdev->dev, "no suitable IB device found to bind to, added to unaffiliated list.\n"); 5702 } else { 5703 mlx5_ib_dbg(dev, "bound port %u\n", port_num + 1); 5704 } 5705 mutex_unlock(&mlx5_ib_multiport_mutex); 5706 5707 return mpi; 5708 } 5709 5710 static void *mlx5_ib_add(struct mlx5_core_dev *mdev) 5711 { 5712 enum rdma_link_layer ll; 5713 struct mlx5_ib_dev *dev; 5714 int port_type_cap; 5715 5716 printk_once(KERN_INFO "%s", mlx5_version); 5717 5718 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 5719 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 5720 5721 if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET) { 5722 u8 port_num = mlx5_core_native_port_num(mdev) - 1; 5723 5724 return mlx5_ib_add_slave_port(mdev, port_num); 5725 } 5726 5727 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev)); 5728 if (!dev) 5729 return NULL; 5730 5731 dev->mdev = mdev; 5732 dev->num_ports = max(MLX5_CAP_GEN(mdev, num_ports), 5733 MLX5_CAP_GEN(mdev, num_vhca_ports)); 5734 5735 if (MLX5_VPORT_MANAGER(mdev) && 5736 mlx5_ib_eswitch_mode(mdev->priv.eswitch) == SRIOV_OFFLOADS) { 5737 dev->rep = mlx5_ib_vport_rep(mdev->priv.eswitch, 0); 5738 5739 return __mlx5_ib_add(dev, &nic_rep_profile); 5740 } 5741 5742 return __mlx5_ib_add(dev, &pf_profile); 5743 } 5744 5745 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context) 5746 { 5747 struct mlx5_ib_multiport_info *mpi; 5748 struct mlx5_ib_dev *dev; 5749 5750 if (mlx5_core_is_mp_slave(mdev)) { 5751 mpi = context; 5752 mutex_lock(&mlx5_ib_multiport_mutex); 5753 if (mpi->ibdev) 5754 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi); 5755 list_del(&mpi->list); 5756 mutex_unlock(&mlx5_ib_multiport_mutex); 5757 return; 5758 } 5759 5760 dev = context; 5761 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX); 5762 } 5763 5764 static struct mlx5_interface mlx5_ib_interface = { 5765 .add = mlx5_ib_add, 5766 .remove = mlx5_ib_remove, 5767 .event = mlx5_ib_event, 5768 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 5769 .pfault = mlx5_ib_pfault, 5770 #endif 5771 .protocol = MLX5_INTERFACE_PROTOCOL_IB, 5772 }; 5773 5774 unsigned long mlx5_ib_get_xlt_emergency_page(void) 5775 { 5776 mutex_lock(&xlt_emergency_page_mutex); 5777 return xlt_emergency_page; 5778 } 5779 5780 void mlx5_ib_put_xlt_emergency_page(void) 5781 { 5782 mutex_unlock(&xlt_emergency_page_mutex); 5783 } 5784 5785 static int __init mlx5_ib_init(void) 5786 { 5787 int err; 5788 5789 xlt_emergency_page = __get_free_page(GFP_KERNEL); 5790 if (!xlt_emergency_page) 5791 return -ENOMEM; 5792 5793 mutex_init(&xlt_emergency_page_mutex); 5794 5795 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0); 5796 if (!mlx5_ib_event_wq) { 5797 free_page(xlt_emergency_page); 5798 return -ENOMEM; 5799 } 5800 5801 mlx5_ib_odp_init(); 5802 5803 err = mlx5_register_interface(&mlx5_ib_interface); 5804 5805 return err; 5806 } 5807 5808 static void __exit mlx5_ib_cleanup(void) 5809 { 5810 mlx5_unregister_interface(&mlx5_ib_interface); 5811 destroy_workqueue(mlx5_ib_event_wq); 5812 mutex_destroy(&xlt_emergency_page_mutex); 5813 free_page(xlt_emergency_page); 5814 } 5815 5816 module_init(mlx5_ib_init); 5817 module_exit(mlx5_ib_cleanup); 5818