1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 /* 3 * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved. 4 * Copyright (c) 2020, Intel Corporation. All rights reserved. 5 */ 6 7 #include <linux/debugfs.h> 8 #include <linux/highmem.h> 9 #include <linux/module.h> 10 #include <linux/init.h> 11 #include <linux/errno.h> 12 #include <linux/pci.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/slab.h> 15 #include <linux/bitmap.h> 16 #include <linux/sched.h> 17 #include <linux/sched/mm.h> 18 #include <linux/sched/task.h> 19 #include <linux/delay.h> 20 #include <rdma/ib_user_verbs.h> 21 #include <rdma/ib_addr.h> 22 #include <rdma/ib_cache.h> 23 #include <linux/mlx5/port.h> 24 #include <linux/mlx5/vport.h> 25 #include <linux/mlx5/fs.h> 26 #include <linux/mlx5/eswitch.h> 27 #include <linux/list.h> 28 #include <rdma/ib_smi.h> 29 #include <rdma/ib_umem.h> 30 #include <rdma/lag.h> 31 #include <linux/in.h> 32 #include <linux/etherdevice.h> 33 #include "mlx5_ib.h" 34 #include "ib_rep.h" 35 #include "cmd.h" 36 #include "devx.h" 37 #include "fs.h" 38 #include "srq.h" 39 #include "qp.h" 40 #include "wr.h" 41 #include "restrack.h" 42 #include "counters.h" 43 #include <linux/mlx5/accel.h> 44 #include <rdma/uverbs_std_types.h> 45 #include <rdma/mlx5_user_ioctl_verbs.h> 46 #include <rdma/mlx5_user_ioctl_cmds.h> 47 #include <rdma/ib_umem_odp.h> 48 49 #define UVERBS_MODULE_NAME mlx5_ib 50 #include <rdma/uverbs_named_ioctl.h> 51 52 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 53 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) IB driver"); 54 MODULE_LICENSE("Dual BSD/GPL"); 55 56 struct mlx5_ib_event_work { 57 struct work_struct work; 58 union { 59 struct mlx5_ib_dev *dev; 60 struct mlx5_ib_multiport_info *mpi; 61 }; 62 bool is_slave; 63 unsigned int event; 64 void *param; 65 }; 66 67 enum { 68 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 69 }; 70 71 static struct workqueue_struct *mlx5_ib_event_wq; 72 static LIST_HEAD(mlx5_ib_unaffiliated_port_list); 73 static LIST_HEAD(mlx5_ib_dev_list); 74 /* 75 * This mutex should be held when accessing either of the above lists 76 */ 77 static DEFINE_MUTEX(mlx5_ib_multiport_mutex); 78 79 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi) 80 { 81 struct mlx5_ib_dev *dev; 82 83 mutex_lock(&mlx5_ib_multiport_mutex); 84 dev = mpi->ibdev; 85 mutex_unlock(&mlx5_ib_multiport_mutex); 86 return dev; 87 } 88 89 static enum rdma_link_layer 90 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 91 { 92 switch (port_type_cap) { 93 case MLX5_CAP_PORT_TYPE_IB: 94 return IB_LINK_LAYER_INFINIBAND; 95 case MLX5_CAP_PORT_TYPE_ETH: 96 return IB_LINK_LAYER_ETHERNET; 97 default: 98 return IB_LINK_LAYER_UNSPECIFIED; 99 } 100 } 101 102 static enum rdma_link_layer 103 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num) 104 { 105 struct mlx5_ib_dev *dev = to_mdev(device); 106 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 107 108 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 109 } 110 111 static int get_port_state(struct ib_device *ibdev, 112 u8 port_num, 113 enum ib_port_state *state) 114 { 115 struct ib_port_attr attr; 116 int ret; 117 118 memset(&attr, 0, sizeof(attr)); 119 ret = ibdev->ops.query_port(ibdev, port_num, &attr); 120 if (!ret) 121 *state = attr.state; 122 return ret; 123 } 124 125 static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev, 126 struct net_device *ndev, 127 u8 *port_num) 128 { 129 struct mlx5_eswitch *esw = dev->mdev->priv.eswitch; 130 struct net_device *rep_ndev; 131 struct mlx5_ib_port *port; 132 int i; 133 134 for (i = 0; i < dev->num_ports; i++) { 135 port = &dev->port[i]; 136 if (!port->rep) 137 continue; 138 139 read_lock(&port->roce.netdev_lock); 140 rep_ndev = mlx5_ib_get_rep_netdev(esw, 141 port->rep->vport); 142 if (rep_ndev == ndev) { 143 read_unlock(&port->roce.netdev_lock); 144 *port_num = i + 1; 145 return &port->roce; 146 } 147 read_unlock(&port->roce.netdev_lock); 148 } 149 150 return NULL; 151 } 152 153 static int mlx5_netdev_event(struct notifier_block *this, 154 unsigned long event, void *ptr) 155 { 156 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb); 157 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 158 u8 port_num = roce->native_port_num; 159 struct mlx5_core_dev *mdev; 160 struct mlx5_ib_dev *ibdev; 161 162 ibdev = roce->dev; 163 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 164 if (!mdev) 165 return NOTIFY_DONE; 166 167 switch (event) { 168 case NETDEV_REGISTER: 169 /* Should already be registered during the load */ 170 if (ibdev->is_rep) 171 break; 172 write_lock(&roce->netdev_lock); 173 if (ndev->dev.parent == mdev->device) 174 roce->netdev = ndev; 175 write_unlock(&roce->netdev_lock); 176 break; 177 178 case NETDEV_UNREGISTER: 179 /* In case of reps, ib device goes away before the netdevs */ 180 write_lock(&roce->netdev_lock); 181 if (roce->netdev == ndev) 182 roce->netdev = NULL; 183 write_unlock(&roce->netdev_lock); 184 break; 185 186 case NETDEV_CHANGE: 187 case NETDEV_UP: 188 case NETDEV_DOWN: { 189 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev); 190 struct net_device *upper = NULL; 191 192 if (lag_ndev) { 193 upper = netdev_master_upper_dev_get(lag_ndev); 194 dev_put(lag_ndev); 195 } 196 197 if (ibdev->is_rep) 198 roce = mlx5_get_rep_roce(ibdev, ndev, &port_num); 199 if (!roce) 200 return NOTIFY_DONE; 201 if ((upper == ndev || (!upper && ndev == roce->netdev)) 202 && ibdev->ib_active) { 203 struct ib_event ibev = { }; 204 enum ib_port_state port_state; 205 206 if (get_port_state(&ibdev->ib_dev, port_num, 207 &port_state)) 208 goto done; 209 210 if (roce->last_port_state == port_state) 211 goto done; 212 213 roce->last_port_state = port_state; 214 ibev.device = &ibdev->ib_dev; 215 if (port_state == IB_PORT_DOWN) 216 ibev.event = IB_EVENT_PORT_ERR; 217 else if (port_state == IB_PORT_ACTIVE) 218 ibev.event = IB_EVENT_PORT_ACTIVE; 219 else 220 goto done; 221 222 ibev.element.port_num = port_num; 223 ib_dispatch_event(&ibev); 224 } 225 break; 226 } 227 228 default: 229 break; 230 } 231 done: 232 mlx5_ib_put_native_port_mdev(ibdev, port_num); 233 return NOTIFY_DONE; 234 } 235 236 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device, 237 u8 port_num) 238 { 239 struct mlx5_ib_dev *ibdev = to_mdev(device); 240 struct net_device *ndev; 241 struct mlx5_core_dev *mdev; 242 243 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 244 if (!mdev) 245 return NULL; 246 247 ndev = mlx5_lag_get_roce_netdev(mdev); 248 if (ndev) 249 goto out; 250 251 /* Ensure ndev does not disappear before we invoke dev_hold() 252 */ 253 read_lock(&ibdev->port[port_num - 1].roce.netdev_lock); 254 ndev = ibdev->port[port_num - 1].roce.netdev; 255 if (ndev) 256 dev_hold(ndev); 257 read_unlock(&ibdev->port[port_num - 1].roce.netdev_lock); 258 259 out: 260 mlx5_ib_put_native_port_mdev(ibdev, port_num); 261 return ndev; 262 } 263 264 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev, 265 u8 ib_port_num, 266 u8 *native_port_num) 267 { 268 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 269 ib_port_num); 270 struct mlx5_core_dev *mdev = NULL; 271 struct mlx5_ib_multiport_info *mpi; 272 struct mlx5_ib_port *port; 273 274 if (!mlx5_core_mp_enabled(ibdev->mdev) || 275 ll != IB_LINK_LAYER_ETHERNET) { 276 if (native_port_num) 277 *native_port_num = ib_port_num; 278 return ibdev->mdev; 279 } 280 281 if (native_port_num) 282 *native_port_num = 1; 283 284 port = &ibdev->port[ib_port_num - 1]; 285 spin_lock(&port->mp.mpi_lock); 286 mpi = ibdev->port[ib_port_num - 1].mp.mpi; 287 if (mpi && !mpi->unaffiliate) { 288 mdev = mpi->mdev; 289 /* If it's the master no need to refcount, it'll exist 290 * as long as the ib_dev exists. 291 */ 292 if (!mpi->is_master) 293 mpi->mdev_refcnt++; 294 } 295 spin_unlock(&port->mp.mpi_lock); 296 297 return mdev; 298 } 299 300 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num) 301 { 302 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 303 port_num); 304 struct mlx5_ib_multiport_info *mpi; 305 struct mlx5_ib_port *port; 306 307 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 308 return; 309 310 port = &ibdev->port[port_num - 1]; 311 312 spin_lock(&port->mp.mpi_lock); 313 mpi = ibdev->port[port_num - 1].mp.mpi; 314 if (mpi->is_master) 315 goto out; 316 317 mpi->mdev_refcnt--; 318 if (mpi->unaffiliate) 319 complete(&mpi->unref_comp); 320 out: 321 spin_unlock(&port->mp.mpi_lock); 322 } 323 324 static int translate_eth_legacy_proto_oper(u32 eth_proto_oper, 325 u16 *active_speed, u8 *active_width) 326 { 327 switch (eth_proto_oper) { 328 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII): 329 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX): 330 case MLX5E_PROT_MASK(MLX5E_100BASE_TX): 331 case MLX5E_PROT_MASK(MLX5E_1000BASE_T): 332 *active_width = IB_WIDTH_1X; 333 *active_speed = IB_SPEED_SDR; 334 break; 335 case MLX5E_PROT_MASK(MLX5E_10GBASE_T): 336 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4): 337 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4): 338 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR): 339 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR): 340 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR): 341 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER): 342 *active_width = IB_WIDTH_1X; 343 *active_speed = IB_SPEED_QDR; 344 break; 345 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR): 346 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR): 347 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR): 348 *active_width = IB_WIDTH_1X; 349 *active_speed = IB_SPEED_EDR; 350 break; 351 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4): 352 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4): 353 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4): 354 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4): 355 *active_width = IB_WIDTH_4X; 356 *active_speed = IB_SPEED_QDR; 357 break; 358 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2): 359 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2): 360 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2): 361 *active_width = IB_WIDTH_1X; 362 *active_speed = IB_SPEED_HDR; 363 break; 364 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4): 365 *active_width = IB_WIDTH_4X; 366 *active_speed = IB_SPEED_FDR; 367 break; 368 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4): 369 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4): 370 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4): 371 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4): 372 *active_width = IB_WIDTH_4X; 373 *active_speed = IB_SPEED_EDR; 374 break; 375 default: 376 return -EINVAL; 377 } 378 379 return 0; 380 } 381 382 static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u16 *active_speed, 383 u8 *active_width) 384 { 385 switch (eth_proto_oper) { 386 case MLX5E_PROT_MASK(MLX5E_SGMII_100M): 387 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII): 388 *active_width = IB_WIDTH_1X; 389 *active_speed = IB_SPEED_SDR; 390 break; 391 case MLX5E_PROT_MASK(MLX5E_5GBASE_R): 392 *active_width = IB_WIDTH_1X; 393 *active_speed = IB_SPEED_DDR; 394 break; 395 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1): 396 *active_width = IB_WIDTH_1X; 397 *active_speed = IB_SPEED_QDR; 398 break; 399 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4): 400 *active_width = IB_WIDTH_4X; 401 *active_speed = IB_SPEED_QDR; 402 break; 403 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR): 404 *active_width = IB_WIDTH_1X; 405 *active_speed = IB_SPEED_EDR; 406 break; 407 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2): 408 *active_width = IB_WIDTH_2X; 409 *active_speed = IB_SPEED_EDR; 410 break; 411 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR): 412 *active_width = IB_WIDTH_1X; 413 *active_speed = IB_SPEED_HDR; 414 break; 415 case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4): 416 *active_width = IB_WIDTH_4X; 417 *active_speed = IB_SPEED_EDR; 418 break; 419 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2): 420 *active_width = IB_WIDTH_2X; 421 *active_speed = IB_SPEED_HDR; 422 break; 423 case MLX5E_PROT_MASK(MLX5E_100GAUI_1_100GBASE_CR_KR): 424 *active_width = IB_WIDTH_1X; 425 *active_speed = IB_SPEED_NDR; 426 break; 427 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4): 428 *active_width = IB_WIDTH_4X; 429 *active_speed = IB_SPEED_HDR; 430 break; 431 case MLX5E_PROT_MASK(MLX5E_200GAUI_2_200GBASE_CR2_KR2): 432 *active_width = IB_WIDTH_2X; 433 *active_speed = IB_SPEED_NDR; 434 break; 435 case MLX5E_PROT_MASK(MLX5E_400GAUI_4_400GBASE_CR4_KR4): 436 *active_width = IB_WIDTH_4X; 437 *active_speed = IB_SPEED_NDR; 438 break; 439 default: 440 return -EINVAL; 441 } 442 443 return 0; 444 } 445 446 static int translate_eth_proto_oper(u32 eth_proto_oper, u16 *active_speed, 447 u8 *active_width, bool ext) 448 { 449 return ext ? 450 translate_eth_ext_proto_oper(eth_proto_oper, active_speed, 451 active_width) : 452 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed, 453 active_width); 454 } 455 456 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num, 457 struct ib_port_attr *props) 458 { 459 struct mlx5_ib_dev *dev = to_mdev(device); 460 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0}; 461 struct mlx5_core_dev *mdev; 462 struct net_device *ndev, *upper; 463 enum ib_mtu ndev_ib_mtu; 464 bool put_mdev = true; 465 u16 qkey_viol_cntr; 466 u32 eth_prot_oper; 467 u8 mdev_port_num; 468 bool ext; 469 int err; 470 471 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 472 if (!mdev) { 473 /* This means the port isn't affiliated yet. Get the 474 * info for the master port instead. 475 */ 476 put_mdev = false; 477 mdev = dev->mdev; 478 mdev_port_num = 1; 479 port_num = 1; 480 } 481 482 /* Possible bad flows are checked before filling out props so in case 483 * of an error it will still be zeroed out. 484 * Use native port in case of reps 485 */ 486 if (dev->is_rep) 487 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 488 1); 489 else 490 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 491 mdev_port_num); 492 if (err) 493 goto out; 494 ext = !!MLX5_GET_ETH_PROTO(ptys_reg, out, true, eth_proto_capability); 495 eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper); 496 497 props->active_width = IB_WIDTH_4X; 498 props->active_speed = IB_SPEED_QDR; 499 500 translate_eth_proto_oper(eth_prot_oper, &props->active_speed, 501 &props->active_width, ext); 502 503 props->port_cap_flags |= IB_PORT_CM_SUP; 504 props->ip_gids = true; 505 506 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 507 roce_address_table_size); 508 props->max_mtu = IB_MTU_4096; 509 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 510 props->pkey_tbl_len = 1; 511 props->state = IB_PORT_DOWN; 512 props->phys_state = IB_PORT_PHYS_STATE_DISABLED; 513 514 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr); 515 props->qkey_viol_cntr = qkey_viol_cntr; 516 517 /* If this is a stub query for an unaffiliated port stop here */ 518 if (!put_mdev) 519 goto out; 520 521 ndev = mlx5_ib_get_netdev(device, port_num); 522 if (!ndev) 523 goto out; 524 525 if (dev->lag_active) { 526 rcu_read_lock(); 527 upper = netdev_master_upper_dev_get_rcu(ndev); 528 if (upper) { 529 dev_put(ndev); 530 ndev = upper; 531 dev_hold(ndev); 532 } 533 rcu_read_unlock(); 534 } 535 536 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 537 props->state = IB_PORT_ACTIVE; 538 props->phys_state = IB_PORT_PHYS_STATE_LINK_UP; 539 } 540 541 ndev_ib_mtu = iboe_get_mtu(ndev->mtu); 542 543 dev_put(ndev); 544 545 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 546 out: 547 if (put_mdev) 548 mlx5_ib_put_native_port_mdev(dev, port_num); 549 return err; 550 } 551 552 static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num, 553 unsigned int index, const union ib_gid *gid, 554 const struct ib_gid_attr *attr) 555 { 556 enum ib_gid_type gid_type = IB_GID_TYPE_ROCE; 557 u16 vlan_id = 0xffff; 558 u8 roce_version = 0; 559 u8 roce_l3_type = 0; 560 u8 mac[ETH_ALEN]; 561 int ret; 562 563 if (gid) { 564 gid_type = attr->gid_type; 565 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]); 566 if (ret) 567 return ret; 568 } 569 570 switch (gid_type) { 571 case IB_GID_TYPE_ROCE: 572 roce_version = MLX5_ROCE_VERSION_1; 573 break; 574 case IB_GID_TYPE_ROCE_UDP_ENCAP: 575 roce_version = MLX5_ROCE_VERSION_2; 576 if (ipv6_addr_v4mapped((void *)gid)) 577 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4; 578 else 579 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6; 580 break; 581 582 default: 583 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type); 584 } 585 586 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version, 587 roce_l3_type, gid->raw, mac, 588 vlan_id < VLAN_CFI_MASK, vlan_id, 589 port_num); 590 } 591 592 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr, 593 __always_unused void **context) 594 { 595 return set_roce_addr(to_mdev(attr->device), attr->port_num, 596 attr->index, &attr->gid, attr); 597 } 598 599 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr, 600 __always_unused void **context) 601 { 602 return set_roce_addr(to_mdev(attr->device), attr->port_num, 603 attr->index, NULL, NULL); 604 } 605 606 __be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev, 607 const struct ib_gid_attr *attr) 608 { 609 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 610 return 0; 611 612 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 613 } 614 615 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 616 { 617 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 618 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 619 return 0; 620 } 621 622 enum { 623 MLX5_VPORT_ACCESS_METHOD_MAD, 624 MLX5_VPORT_ACCESS_METHOD_HCA, 625 MLX5_VPORT_ACCESS_METHOD_NIC, 626 }; 627 628 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 629 { 630 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 631 return MLX5_VPORT_ACCESS_METHOD_MAD; 632 633 if (mlx5_ib_port_link_layer(ibdev, 1) == 634 IB_LINK_LAYER_ETHERNET) 635 return MLX5_VPORT_ACCESS_METHOD_NIC; 636 637 return MLX5_VPORT_ACCESS_METHOD_HCA; 638 } 639 640 static void get_atomic_caps(struct mlx5_ib_dev *dev, 641 u8 atomic_size_qp, 642 struct ib_device_attr *props) 643 { 644 u8 tmp; 645 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 646 u8 atomic_req_8B_endianness_mode = 647 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode); 648 649 /* Check if HW supports 8 bytes standard atomic operations and capable 650 * of host endianness respond 651 */ 652 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 653 if (((atomic_operations & tmp) == tmp) && 654 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 655 (atomic_req_8B_endianness_mode)) { 656 props->atomic_cap = IB_ATOMIC_HCA; 657 } else { 658 props->atomic_cap = IB_ATOMIC_NONE; 659 } 660 } 661 662 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev, 663 struct ib_device_attr *props) 664 { 665 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 666 667 get_atomic_caps(dev, atomic_size_qp, props); 668 } 669 670 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 671 __be64 *sys_image_guid) 672 { 673 struct mlx5_ib_dev *dev = to_mdev(ibdev); 674 struct mlx5_core_dev *mdev = dev->mdev; 675 u64 tmp; 676 int err; 677 678 switch (mlx5_get_vport_access_method(ibdev)) { 679 case MLX5_VPORT_ACCESS_METHOD_MAD: 680 return mlx5_query_mad_ifc_system_image_guid(ibdev, 681 sys_image_guid); 682 683 case MLX5_VPORT_ACCESS_METHOD_HCA: 684 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 685 break; 686 687 case MLX5_VPORT_ACCESS_METHOD_NIC: 688 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 689 break; 690 691 default: 692 return -EINVAL; 693 } 694 695 if (!err) 696 *sys_image_guid = cpu_to_be64(tmp); 697 698 return err; 699 700 } 701 702 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 703 u16 *max_pkeys) 704 { 705 struct mlx5_ib_dev *dev = to_mdev(ibdev); 706 struct mlx5_core_dev *mdev = dev->mdev; 707 708 switch (mlx5_get_vport_access_method(ibdev)) { 709 case MLX5_VPORT_ACCESS_METHOD_MAD: 710 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 711 712 case MLX5_VPORT_ACCESS_METHOD_HCA: 713 case MLX5_VPORT_ACCESS_METHOD_NIC: 714 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 715 pkey_table_size)); 716 return 0; 717 718 default: 719 return -EINVAL; 720 } 721 } 722 723 static int mlx5_query_vendor_id(struct ib_device *ibdev, 724 u32 *vendor_id) 725 { 726 struct mlx5_ib_dev *dev = to_mdev(ibdev); 727 728 switch (mlx5_get_vport_access_method(ibdev)) { 729 case MLX5_VPORT_ACCESS_METHOD_MAD: 730 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 731 732 case MLX5_VPORT_ACCESS_METHOD_HCA: 733 case MLX5_VPORT_ACCESS_METHOD_NIC: 734 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 735 736 default: 737 return -EINVAL; 738 } 739 } 740 741 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 742 __be64 *node_guid) 743 { 744 u64 tmp; 745 int err; 746 747 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 748 case MLX5_VPORT_ACCESS_METHOD_MAD: 749 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 750 751 case MLX5_VPORT_ACCESS_METHOD_HCA: 752 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 753 break; 754 755 case MLX5_VPORT_ACCESS_METHOD_NIC: 756 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 757 break; 758 759 default: 760 return -EINVAL; 761 } 762 763 if (!err) 764 *node_guid = cpu_to_be64(tmp); 765 766 return err; 767 } 768 769 struct mlx5_reg_node_desc { 770 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 771 }; 772 773 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 774 { 775 struct mlx5_reg_node_desc in; 776 777 if (mlx5_use_mad_ifc(dev)) 778 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 779 780 memset(&in, 0, sizeof(in)); 781 782 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 783 sizeof(struct mlx5_reg_node_desc), 784 MLX5_REG_NODE_DESC, 0, 0); 785 } 786 787 static int mlx5_ib_query_device(struct ib_device *ibdev, 788 struct ib_device_attr *props, 789 struct ib_udata *uhw) 790 { 791 size_t uhw_outlen = (uhw) ? uhw->outlen : 0; 792 struct mlx5_ib_dev *dev = to_mdev(ibdev); 793 struct mlx5_core_dev *mdev = dev->mdev; 794 int err = -ENOMEM; 795 int max_sq_desc; 796 int max_rq_sg; 797 int max_sq_sg; 798 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 799 bool raw_support = !mlx5_core_mp_enabled(mdev); 800 struct mlx5_ib_query_device_resp resp = {}; 801 size_t resp_len; 802 u64 max_tso; 803 804 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 805 if (uhw_outlen && uhw_outlen < resp_len) 806 return -EINVAL; 807 808 resp.response_length = resp_len; 809 810 if (uhw && uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) 811 return -EINVAL; 812 813 memset(props, 0, sizeof(*props)); 814 err = mlx5_query_system_image_guid(ibdev, 815 &props->sys_image_guid); 816 if (err) 817 return err; 818 819 props->max_pkeys = dev->pkey_table_len; 820 821 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 822 if (err) 823 return err; 824 825 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 826 (fw_rev_min(dev->mdev) << 16) | 827 fw_rev_sub(dev->mdev); 828 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 829 IB_DEVICE_PORT_ACTIVE_EVENT | 830 IB_DEVICE_SYS_IMAGE_GUID | 831 IB_DEVICE_RC_RNR_NAK_GEN; 832 833 if (MLX5_CAP_GEN(mdev, pkv)) 834 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 835 if (MLX5_CAP_GEN(mdev, qkv)) 836 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 837 if (MLX5_CAP_GEN(mdev, apm)) 838 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 839 if (MLX5_CAP_GEN(mdev, xrc)) 840 props->device_cap_flags |= IB_DEVICE_XRC; 841 if (MLX5_CAP_GEN(mdev, imaicl)) { 842 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 843 IB_DEVICE_MEM_WINDOW_TYPE_2B; 844 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 845 /* We support 'Gappy' memory registration too */ 846 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG; 847 } 848 /* IB_WR_REG_MR always requires changing the entity size with UMR */ 849 if (!MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) 850 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 851 if (MLX5_CAP_GEN(mdev, sho)) { 852 props->device_cap_flags |= IB_DEVICE_INTEGRITY_HANDOVER; 853 /* At this stage no support for signature handover */ 854 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 855 IB_PROT_T10DIF_TYPE_2 | 856 IB_PROT_T10DIF_TYPE_3; 857 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 858 IB_GUARD_T10DIF_CSUM; 859 } 860 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 861 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 862 863 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) { 864 if (MLX5_CAP_ETH(mdev, csum_cap)) { 865 /* Legacy bit to support old userspace libraries */ 866 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 867 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM; 868 } 869 870 if (MLX5_CAP_ETH(dev->mdev, vlan_cap)) 871 props->raw_packet_caps |= 872 IB_RAW_PACKET_CAP_CVLAN_STRIPPING; 873 874 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) { 875 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 876 if (max_tso) { 877 resp.tso_caps.max_tso = 1 << max_tso; 878 resp.tso_caps.supported_qpts |= 879 1 << IB_QPT_RAW_PACKET; 880 resp.response_length += sizeof(resp.tso_caps); 881 } 882 } 883 884 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) { 885 resp.rss_caps.rx_hash_function = 886 MLX5_RX_HASH_FUNC_TOEPLITZ; 887 resp.rss_caps.rx_hash_fields_mask = 888 MLX5_RX_HASH_SRC_IPV4 | 889 MLX5_RX_HASH_DST_IPV4 | 890 MLX5_RX_HASH_SRC_IPV6 | 891 MLX5_RX_HASH_DST_IPV6 | 892 MLX5_RX_HASH_SRC_PORT_TCP | 893 MLX5_RX_HASH_DST_PORT_TCP | 894 MLX5_RX_HASH_SRC_PORT_UDP | 895 MLX5_RX_HASH_DST_PORT_UDP | 896 MLX5_RX_HASH_INNER; 897 if (mlx5_accel_ipsec_device_caps(dev->mdev) & 898 MLX5_ACCEL_IPSEC_CAP_DEVICE) 899 resp.rss_caps.rx_hash_fields_mask |= 900 MLX5_RX_HASH_IPSEC_SPI; 901 resp.response_length += sizeof(resp.rss_caps); 902 } 903 } else { 904 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) 905 resp.response_length += sizeof(resp.tso_caps); 906 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) 907 resp.response_length += sizeof(resp.rss_caps); 908 } 909 910 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 911 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 912 props->device_cap_flags |= IB_DEVICE_UD_TSO; 913 } 914 915 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) && 916 MLX5_CAP_GEN(dev->mdev, general_notification_event) && 917 raw_support) 918 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP; 919 920 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 921 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap)) 922 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 923 924 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 925 MLX5_CAP_ETH(dev->mdev, scatter_fcs) && 926 raw_support) { 927 /* Legacy bit to support old userspace libraries */ 928 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 929 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; 930 } 931 932 if (MLX5_CAP_DEV_MEM(mdev, memic)) { 933 props->max_dm_size = 934 MLX5_CAP_DEV_MEM(mdev, max_memic_size); 935 } 936 937 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 938 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 939 940 if (MLX5_CAP_GEN(mdev, end_pad)) 941 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING; 942 943 props->vendor_part_id = mdev->pdev->device; 944 props->hw_ver = mdev->pdev->revision; 945 946 props->max_mr_size = ~0ull; 947 props->page_size_cap = ~(min_page_size - 1); 948 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 949 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 950 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 951 sizeof(struct mlx5_wqe_data_seg); 952 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512); 953 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) - 954 sizeof(struct mlx5_wqe_raddr_seg)) / 955 sizeof(struct mlx5_wqe_data_seg); 956 props->max_send_sge = max_sq_sg; 957 props->max_recv_sge = max_rq_sg; 958 props->max_sge_rd = MLX5_MAX_SGE_RD; 959 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 960 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 961 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 962 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 963 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 964 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 965 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 966 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 967 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 968 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 969 props->max_srq_sge = max_rq_sg - 1; 970 props->max_fast_reg_page_list_len = 971 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 972 props->max_pi_fast_reg_page_list_len = 973 props->max_fast_reg_page_list_len / 2; 974 props->max_sgl_rd = 975 MLX5_CAP_GEN(mdev, max_sgl_for_optimized_performance); 976 get_atomic_caps_qp(dev, props); 977 props->masked_atomic_cap = IB_ATOMIC_NONE; 978 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 979 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 980 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 981 props->max_mcast_grp; 982 props->max_ah = INT_MAX; 983 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 984 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 985 986 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) { 987 if (dev->odp_caps.general_caps & IB_ODP_SUPPORT) 988 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING; 989 props->odp_caps = dev->odp_caps; 990 if (!uhw) { 991 /* ODP for kernel QPs is not implemented for receive 992 * WQEs and SRQ WQEs 993 */ 994 props->odp_caps.per_transport_caps.rc_odp_caps &= 995 ~(IB_ODP_SUPPORT_READ | 996 IB_ODP_SUPPORT_SRQ_RECV); 997 props->odp_caps.per_transport_caps.uc_odp_caps &= 998 ~(IB_ODP_SUPPORT_READ | 999 IB_ODP_SUPPORT_SRQ_RECV); 1000 props->odp_caps.per_transport_caps.ud_odp_caps &= 1001 ~(IB_ODP_SUPPORT_READ | 1002 IB_ODP_SUPPORT_SRQ_RECV); 1003 props->odp_caps.per_transport_caps.xrc_odp_caps &= 1004 ~(IB_ODP_SUPPORT_READ | 1005 IB_ODP_SUPPORT_SRQ_RECV); 1006 } 1007 } 1008 1009 if (MLX5_CAP_GEN(mdev, cd)) 1010 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL; 1011 1012 if (mlx5_core_is_vf(mdev)) 1013 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION; 1014 1015 if (mlx5_ib_port_link_layer(ibdev, 1) == 1016 IB_LINK_LAYER_ETHERNET && raw_support) { 1017 props->rss_caps.max_rwq_indirection_tables = 1018 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 1019 props->rss_caps.max_rwq_indirection_table_size = 1020 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 1021 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 1022 props->max_wq_type_rq = 1023 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 1024 } 1025 1026 if (MLX5_CAP_GEN(mdev, tag_matching)) { 1027 props->tm_caps.max_num_tags = 1028 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1; 1029 props->tm_caps.max_ops = 1030 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 1031 props->tm_caps.max_sge = MLX5_TM_MAX_SGE; 1032 } 1033 1034 if (MLX5_CAP_GEN(mdev, tag_matching) && 1035 MLX5_CAP_GEN(mdev, rndv_offload_rc)) { 1036 props->tm_caps.flags = IB_TM_CAP_RNDV_RC; 1037 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE; 1038 } 1039 1040 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) { 1041 props->cq_caps.max_cq_moderation_count = 1042 MLX5_MAX_CQ_COUNT; 1043 props->cq_caps.max_cq_moderation_period = 1044 MLX5_MAX_CQ_PERIOD; 1045 } 1046 1047 if (offsetofend(typeof(resp), cqe_comp_caps) <= uhw_outlen) { 1048 resp.response_length += sizeof(resp.cqe_comp_caps); 1049 1050 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) { 1051 resp.cqe_comp_caps.max_num = 1052 MLX5_CAP_GEN(dev->mdev, 1053 cqe_compression_max_num); 1054 1055 resp.cqe_comp_caps.supported_format = 1056 MLX5_IB_CQE_RES_FORMAT_HASH | 1057 MLX5_IB_CQE_RES_FORMAT_CSUM; 1058 1059 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index)) 1060 resp.cqe_comp_caps.supported_format |= 1061 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX; 1062 } 1063 } 1064 1065 if (offsetofend(typeof(resp), packet_pacing_caps) <= uhw_outlen && 1066 raw_support) { 1067 if (MLX5_CAP_QOS(mdev, packet_pacing) && 1068 MLX5_CAP_GEN(mdev, qos)) { 1069 resp.packet_pacing_caps.qp_rate_limit_max = 1070 MLX5_CAP_QOS(mdev, packet_pacing_max_rate); 1071 resp.packet_pacing_caps.qp_rate_limit_min = 1072 MLX5_CAP_QOS(mdev, packet_pacing_min_rate); 1073 resp.packet_pacing_caps.supported_qpts |= 1074 1 << IB_QPT_RAW_PACKET; 1075 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) && 1076 MLX5_CAP_QOS(mdev, packet_pacing_typical_size)) 1077 resp.packet_pacing_caps.cap_flags |= 1078 MLX5_IB_PP_SUPPORT_BURST; 1079 } 1080 resp.response_length += sizeof(resp.packet_pacing_caps); 1081 } 1082 1083 if (offsetofend(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes) <= 1084 uhw_outlen) { 1085 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe)) 1086 resp.mlx5_ib_support_multi_pkt_send_wqes = 1087 MLX5_IB_ALLOW_MPW; 1088 1089 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe)) 1090 resp.mlx5_ib_support_multi_pkt_send_wqes |= 1091 MLX5_IB_SUPPORT_EMPW; 1092 1093 resp.response_length += 1094 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes); 1095 } 1096 1097 if (offsetofend(typeof(resp), flags) <= uhw_outlen) { 1098 resp.response_length += sizeof(resp.flags); 1099 1100 if (MLX5_CAP_GEN(mdev, cqe_compression_128)) 1101 resp.flags |= 1102 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP; 1103 1104 if (MLX5_CAP_GEN(mdev, cqe_128_always)) 1105 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD; 1106 if (MLX5_CAP_GEN(mdev, qp_packet_based)) 1107 resp.flags |= 1108 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE; 1109 1110 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT; 1111 } 1112 1113 if (offsetofend(typeof(resp), sw_parsing_caps) <= uhw_outlen) { 1114 resp.response_length += sizeof(resp.sw_parsing_caps); 1115 if (MLX5_CAP_ETH(mdev, swp)) { 1116 resp.sw_parsing_caps.sw_parsing_offloads |= 1117 MLX5_IB_SW_PARSING; 1118 1119 if (MLX5_CAP_ETH(mdev, swp_csum)) 1120 resp.sw_parsing_caps.sw_parsing_offloads |= 1121 MLX5_IB_SW_PARSING_CSUM; 1122 1123 if (MLX5_CAP_ETH(mdev, swp_lso)) 1124 resp.sw_parsing_caps.sw_parsing_offloads |= 1125 MLX5_IB_SW_PARSING_LSO; 1126 1127 if (resp.sw_parsing_caps.sw_parsing_offloads) 1128 resp.sw_parsing_caps.supported_qpts = 1129 BIT(IB_QPT_RAW_PACKET); 1130 } 1131 } 1132 1133 if (offsetofend(typeof(resp), striding_rq_caps) <= uhw_outlen && 1134 raw_support) { 1135 resp.response_length += sizeof(resp.striding_rq_caps); 1136 if (MLX5_CAP_GEN(mdev, striding_rq)) { 1137 resp.striding_rq_caps.min_single_stride_log_num_of_bytes = 1138 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES; 1139 resp.striding_rq_caps.max_single_stride_log_num_of_bytes = 1140 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES; 1141 if (MLX5_CAP_GEN(dev->mdev, ext_stride_num_range)) 1142 resp.striding_rq_caps 1143 .min_single_wqe_log_num_of_strides = 1144 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1145 else 1146 resp.striding_rq_caps 1147 .min_single_wqe_log_num_of_strides = 1148 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1149 resp.striding_rq_caps.max_single_wqe_log_num_of_strides = 1150 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES; 1151 resp.striding_rq_caps.supported_qpts = 1152 BIT(IB_QPT_RAW_PACKET); 1153 } 1154 } 1155 1156 if (offsetofend(typeof(resp), tunnel_offloads_caps) <= uhw_outlen) { 1157 resp.response_length += sizeof(resp.tunnel_offloads_caps); 1158 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan)) 1159 resp.tunnel_offloads_caps |= 1160 MLX5_IB_TUNNELED_OFFLOADS_VXLAN; 1161 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx)) 1162 resp.tunnel_offloads_caps |= 1163 MLX5_IB_TUNNELED_OFFLOADS_GENEVE; 1164 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) 1165 resp.tunnel_offloads_caps |= 1166 MLX5_IB_TUNNELED_OFFLOADS_GRE; 1167 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre)) 1168 resp.tunnel_offloads_caps |= 1169 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE; 1170 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_udp)) 1171 resp.tunnel_offloads_caps |= 1172 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP; 1173 } 1174 1175 if (uhw_outlen) { 1176 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 1177 1178 if (err) 1179 return err; 1180 } 1181 1182 return 0; 1183 } 1184 1185 static void translate_active_width(struct ib_device *ibdev, u16 active_width, 1186 u8 *ib_width) 1187 { 1188 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1189 1190 if (active_width & MLX5_PTYS_WIDTH_1X) 1191 *ib_width = IB_WIDTH_1X; 1192 else if (active_width & MLX5_PTYS_WIDTH_2X) 1193 *ib_width = IB_WIDTH_2X; 1194 else if (active_width & MLX5_PTYS_WIDTH_4X) 1195 *ib_width = IB_WIDTH_4X; 1196 else if (active_width & MLX5_PTYS_WIDTH_8X) 1197 *ib_width = IB_WIDTH_8X; 1198 else if (active_width & MLX5_PTYS_WIDTH_12X) 1199 *ib_width = IB_WIDTH_12X; 1200 else { 1201 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n", 1202 active_width); 1203 *ib_width = IB_WIDTH_4X; 1204 } 1205 1206 return; 1207 } 1208 1209 static int mlx5_mtu_to_ib_mtu(int mtu) 1210 { 1211 switch (mtu) { 1212 case 256: return 1; 1213 case 512: return 2; 1214 case 1024: return 3; 1215 case 2048: return 4; 1216 case 4096: return 5; 1217 default: 1218 pr_warn("invalid mtu\n"); 1219 return -1; 1220 } 1221 } 1222 1223 enum ib_max_vl_num { 1224 __IB_MAX_VL_0 = 1, 1225 __IB_MAX_VL_0_1 = 2, 1226 __IB_MAX_VL_0_3 = 3, 1227 __IB_MAX_VL_0_7 = 4, 1228 __IB_MAX_VL_0_14 = 5, 1229 }; 1230 1231 enum mlx5_vl_hw_cap { 1232 MLX5_VL_HW_0 = 1, 1233 MLX5_VL_HW_0_1 = 2, 1234 MLX5_VL_HW_0_2 = 3, 1235 MLX5_VL_HW_0_3 = 4, 1236 MLX5_VL_HW_0_4 = 5, 1237 MLX5_VL_HW_0_5 = 6, 1238 MLX5_VL_HW_0_6 = 7, 1239 MLX5_VL_HW_0_7 = 8, 1240 MLX5_VL_HW_0_14 = 15 1241 }; 1242 1243 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 1244 u8 *max_vl_num) 1245 { 1246 switch (vl_hw_cap) { 1247 case MLX5_VL_HW_0: 1248 *max_vl_num = __IB_MAX_VL_0; 1249 break; 1250 case MLX5_VL_HW_0_1: 1251 *max_vl_num = __IB_MAX_VL_0_1; 1252 break; 1253 case MLX5_VL_HW_0_3: 1254 *max_vl_num = __IB_MAX_VL_0_3; 1255 break; 1256 case MLX5_VL_HW_0_7: 1257 *max_vl_num = __IB_MAX_VL_0_7; 1258 break; 1259 case MLX5_VL_HW_0_14: 1260 *max_vl_num = __IB_MAX_VL_0_14; 1261 break; 1262 1263 default: 1264 return -EINVAL; 1265 } 1266 1267 return 0; 1268 } 1269 1270 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port, 1271 struct ib_port_attr *props) 1272 { 1273 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1274 struct mlx5_core_dev *mdev = dev->mdev; 1275 struct mlx5_hca_vport_context *rep; 1276 u16 max_mtu; 1277 u16 oper_mtu; 1278 int err; 1279 u16 ib_link_width_oper; 1280 u8 vl_hw_cap; 1281 1282 rep = kzalloc(sizeof(*rep), GFP_KERNEL); 1283 if (!rep) { 1284 err = -ENOMEM; 1285 goto out; 1286 } 1287 1288 /* props being zeroed by the caller, avoid zeroing it here */ 1289 1290 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); 1291 if (err) 1292 goto out; 1293 1294 props->lid = rep->lid; 1295 props->lmc = rep->lmc; 1296 props->sm_lid = rep->sm_lid; 1297 props->sm_sl = rep->sm_sl; 1298 props->state = rep->vport_state; 1299 props->phys_state = rep->port_physical_state; 1300 props->port_cap_flags = rep->cap_mask1; 1301 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 1302 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 1303 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 1304 props->bad_pkey_cntr = rep->pkey_violation_counter; 1305 props->qkey_viol_cntr = rep->qkey_violation_counter; 1306 props->subnet_timeout = rep->subnet_timeout; 1307 props->init_type_reply = rep->init_type_reply; 1308 1309 if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP) 1310 props->port_cap_flags2 = rep->cap_mask2; 1311 1312 err = mlx5_query_ib_port_oper(mdev, &ib_link_width_oper, 1313 &props->active_speed, port); 1314 if (err) 1315 goto out; 1316 1317 translate_active_width(ibdev, ib_link_width_oper, &props->active_width); 1318 1319 mlx5_query_port_max_mtu(mdev, &max_mtu, port); 1320 1321 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); 1322 1323 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); 1324 1325 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); 1326 1327 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); 1328 if (err) 1329 goto out; 1330 1331 err = translate_max_vl_num(ibdev, vl_hw_cap, 1332 &props->max_vl_num); 1333 out: 1334 kfree(rep); 1335 return err; 1336 } 1337 1338 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 1339 struct ib_port_attr *props) 1340 { 1341 unsigned int count; 1342 int ret; 1343 1344 switch (mlx5_get_vport_access_method(ibdev)) { 1345 case MLX5_VPORT_ACCESS_METHOD_MAD: 1346 ret = mlx5_query_mad_ifc_port(ibdev, port, props); 1347 break; 1348 1349 case MLX5_VPORT_ACCESS_METHOD_HCA: 1350 ret = mlx5_query_hca_port(ibdev, port, props); 1351 break; 1352 1353 case MLX5_VPORT_ACCESS_METHOD_NIC: 1354 ret = mlx5_query_port_roce(ibdev, port, props); 1355 break; 1356 1357 default: 1358 ret = -EINVAL; 1359 } 1360 1361 if (!ret && props) { 1362 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1363 struct mlx5_core_dev *mdev; 1364 bool put_mdev = true; 1365 1366 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL); 1367 if (!mdev) { 1368 /* If the port isn't affiliated yet query the master. 1369 * The master and slave will have the same values. 1370 */ 1371 mdev = dev->mdev; 1372 port = 1; 1373 put_mdev = false; 1374 } 1375 count = mlx5_core_reserved_gids_count(mdev); 1376 if (put_mdev) 1377 mlx5_ib_put_native_port_mdev(dev, port); 1378 props->gid_tbl_len -= count; 1379 } 1380 return ret; 1381 } 1382 1383 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port, 1384 struct ib_port_attr *props) 1385 { 1386 int ret; 1387 1388 /* Only link layer == ethernet is valid for representors 1389 * and we always use port 1 1390 */ 1391 ret = mlx5_query_port_roce(ibdev, port, props); 1392 if (ret || !props) 1393 return ret; 1394 1395 /* We don't support GIDS */ 1396 props->gid_tbl_len = 0; 1397 1398 return ret; 1399 } 1400 1401 static int mlx5_ib_rep_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 1402 u16 *pkey) 1403 { 1404 /* Default special Pkey for representor device port as per the 1405 * IB specification 1.3 section 10.9.1.2. 1406 */ 1407 *pkey = 0xffff; 1408 return 0; 1409 } 1410 1411 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 1412 union ib_gid *gid) 1413 { 1414 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1415 struct mlx5_core_dev *mdev = dev->mdev; 1416 1417 switch (mlx5_get_vport_access_method(ibdev)) { 1418 case MLX5_VPORT_ACCESS_METHOD_MAD: 1419 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 1420 1421 case MLX5_VPORT_ACCESS_METHOD_HCA: 1422 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); 1423 1424 default: 1425 return -EINVAL; 1426 } 1427 1428 } 1429 1430 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port, 1431 u16 index, u16 *pkey) 1432 { 1433 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1434 struct mlx5_core_dev *mdev; 1435 bool put_mdev = true; 1436 u8 mdev_port_num; 1437 int err; 1438 1439 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num); 1440 if (!mdev) { 1441 /* The port isn't affiliated yet, get the PKey from the master 1442 * port. For RoCE the PKey tables will be the same. 1443 */ 1444 put_mdev = false; 1445 mdev = dev->mdev; 1446 mdev_port_num = 1; 1447 } 1448 1449 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0, 1450 index, pkey); 1451 if (put_mdev) 1452 mlx5_ib_put_native_port_mdev(dev, port); 1453 1454 return err; 1455 } 1456 1457 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 1458 u16 *pkey) 1459 { 1460 switch (mlx5_get_vport_access_method(ibdev)) { 1461 case MLX5_VPORT_ACCESS_METHOD_MAD: 1462 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 1463 1464 case MLX5_VPORT_ACCESS_METHOD_HCA: 1465 case MLX5_VPORT_ACCESS_METHOD_NIC: 1466 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey); 1467 default: 1468 return -EINVAL; 1469 } 1470 } 1471 1472 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 1473 struct ib_device_modify *props) 1474 { 1475 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1476 struct mlx5_reg_node_desc in; 1477 struct mlx5_reg_node_desc out; 1478 int err; 1479 1480 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 1481 return -EOPNOTSUPP; 1482 1483 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 1484 return 0; 1485 1486 /* 1487 * If possible, pass node desc to FW, so it can generate 1488 * a 144 trap. If cmd fails, just ignore. 1489 */ 1490 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1491 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 1492 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 1493 if (err) 1494 return err; 1495 1496 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1497 1498 return err; 1499 } 1500 1501 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask, 1502 u32 value) 1503 { 1504 struct mlx5_hca_vport_context ctx = {}; 1505 struct mlx5_core_dev *mdev; 1506 u8 mdev_port_num; 1507 int err; 1508 1509 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 1510 if (!mdev) 1511 return -ENODEV; 1512 1513 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx); 1514 if (err) 1515 goto out; 1516 1517 if (~ctx.cap_mask1_perm & mask) { 1518 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n", 1519 mask, ctx.cap_mask1_perm); 1520 err = -EINVAL; 1521 goto out; 1522 } 1523 1524 ctx.cap_mask1 = value; 1525 ctx.cap_mask1_perm = mask; 1526 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num, 1527 0, &ctx); 1528 1529 out: 1530 mlx5_ib_put_native_port_mdev(dev, port_num); 1531 1532 return err; 1533 } 1534 1535 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, 1536 struct ib_port_modify *props) 1537 { 1538 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1539 struct ib_port_attr attr; 1540 u32 tmp; 1541 int err; 1542 u32 change_mask; 1543 u32 value; 1544 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) == 1545 IB_LINK_LAYER_INFINIBAND); 1546 1547 /* CM layer calls ib_modify_port() regardless of the link layer. For 1548 * Ethernet ports, qkey violation and Port capabilities are meaningless. 1549 */ 1550 if (!is_ib) 1551 return 0; 1552 1553 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) { 1554 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask; 1555 value = ~props->clr_port_cap_mask | props->set_port_cap_mask; 1556 return set_port_caps_atomic(dev, port, change_mask, value); 1557 } 1558 1559 mutex_lock(&dev->cap_mask_mutex); 1560 1561 err = ib_query_port(ibdev, port, &attr); 1562 if (err) 1563 goto out; 1564 1565 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 1566 ~props->clr_port_cap_mask; 1567 1568 err = mlx5_set_port_caps(dev->mdev, port, tmp); 1569 1570 out: 1571 mutex_unlock(&dev->cap_mask_mutex); 1572 return err; 1573 } 1574 1575 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps) 1576 { 1577 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n", 1578 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n"); 1579 } 1580 1581 static u16 calc_dynamic_bfregs(int uars_per_sys_page) 1582 { 1583 /* Large page with non 4k uar support might limit the dynamic size */ 1584 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096) 1585 return MLX5_MIN_DYN_BFREGS; 1586 1587 return MLX5_MAX_DYN_BFREGS; 1588 } 1589 1590 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k, 1591 struct mlx5_ib_alloc_ucontext_req_v2 *req, 1592 struct mlx5_bfreg_info *bfregi) 1593 { 1594 int uars_per_sys_page; 1595 int bfregs_per_sys_page; 1596 int ref_bfregs = req->total_num_bfregs; 1597 1598 if (req->total_num_bfregs == 0) 1599 return -EINVAL; 1600 1601 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE); 1602 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE); 1603 1604 if (req->total_num_bfregs > MLX5_MAX_BFREGS) 1605 return -ENOMEM; 1606 1607 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k); 1608 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR; 1609 /* This holds the required static allocation asked by the user */ 1610 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page); 1611 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1) 1612 return -EINVAL; 1613 1614 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page; 1615 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page); 1616 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs; 1617 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page; 1618 1619 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n", 1620 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no", 1621 lib_uar_4k ? "yes" : "no", ref_bfregs, 1622 req->total_num_bfregs, bfregi->total_num_bfregs, 1623 bfregi->num_sys_pages); 1624 1625 return 0; 1626 } 1627 1628 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1629 { 1630 struct mlx5_bfreg_info *bfregi; 1631 int err; 1632 int i; 1633 1634 bfregi = &context->bfregi; 1635 for (i = 0; i < bfregi->num_static_sys_pages; i++) { 1636 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]); 1637 if (err) 1638 goto error; 1639 1640 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]); 1641 } 1642 1643 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++) 1644 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX; 1645 1646 return 0; 1647 1648 error: 1649 for (--i; i >= 0; i--) 1650 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i])) 1651 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1652 1653 return err; 1654 } 1655 1656 static void deallocate_uars(struct mlx5_ib_dev *dev, 1657 struct mlx5_ib_ucontext *context) 1658 { 1659 struct mlx5_bfreg_info *bfregi; 1660 int i; 1661 1662 bfregi = &context->bfregi; 1663 for (i = 0; i < bfregi->num_sys_pages; i++) 1664 if (i < bfregi->num_static_sys_pages || 1665 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) 1666 mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]); 1667 } 1668 1669 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 1670 { 1671 int err = 0; 1672 1673 mutex_lock(&dev->lb.mutex); 1674 if (td) 1675 dev->lb.user_td++; 1676 if (qp) 1677 dev->lb.qps++; 1678 1679 if (dev->lb.user_td == 2 || 1680 dev->lb.qps == 1) { 1681 if (!dev->lb.enabled) { 1682 err = mlx5_nic_vport_update_local_lb(dev->mdev, true); 1683 dev->lb.enabled = true; 1684 } 1685 } 1686 1687 mutex_unlock(&dev->lb.mutex); 1688 1689 return err; 1690 } 1691 1692 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 1693 { 1694 mutex_lock(&dev->lb.mutex); 1695 if (td) 1696 dev->lb.user_td--; 1697 if (qp) 1698 dev->lb.qps--; 1699 1700 if (dev->lb.user_td == 1 && 1701 dev->lb.qps == 0) { 1702 if (dev->lb.enabled) { 1703 mlx5_nic_vport_update_local_lb(dev->mdev, false); 1704 dev->lb.enabled = false; 1705 } 1706 } 1707 1708 mutex_unlock(&dev->lb.mutex); 1709 } 1710 1711 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn, 1712 u16 uid) 1713 { 1714 int err; 1715 1716 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1717 return 0; 1718 1719 err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid); 1720 if (err) 1721 return err; 1722 1723 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1724 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1725 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1726 return err; 1727 1728 return mlx5_ib_enable_lb(dev, true, false); 1729 } 1730 1731 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn, 1732 u16 uid) 1733 { 1734 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1735 return; 1736 1737 mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid); 1738 1739 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1740 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1741 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1742 return; 1743 1744 mlx5_ib_disable_lb(dev, true, false); 1745 } 1746 1747 static int set_ucontext_resp(struct ib_ucontext *uctx, 1748 struct mlx5_ib_alloc_ucontext_resp *resp) 1749 { 1750 struct ib_device *ibdev = uctx->device; 1751 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1752 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 1753 struct mlx5_bfreg_info *bfregi = &context->bfregi; 1754 int err; 1755 1756 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) { 1757 err = mlx5_cmd_dump_fill_mkey(dev->mdev, 1758 &resp->dump_fill_mkey); 1759 if (err) 1760 return err; 1761 resp->comp_mask |= 1762 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY; 1763 } 1764 1765 resp->qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 1766 if (dev->wc_support) 1767 resp->bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, 1768 log_bf_reg_size); 1769 resp->cache_line_size = cache_line_size(); 1770 resp->max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 1771 resp->max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 1772 resp->max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1773 resp->max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1774 resp->max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 1775 resp->cqe_version = context->cqe_version; 1776 resp->log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1777 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT; 1778 resp->num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1779 MLX5_CAP_GEN(dev->mdev, 1780 num_of_uars_per_page) : 1; 1781 1782 if (mlx5_accel_ipsec_device_caps(dev->mdev) & 1783 MLX5_ACCEL_IPSEC_CAP_DEVICE) { 1784 if (mlx5_get_flow_namespace(dev->mdev, 1785 MLX5_FLOW_NAMESPACE_EGRESS)) 1786 resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM; 1787 if (mlx5_accel_ipsec_device_caps(dev->mdev) & 1788 MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA) 1789 resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA; 1790 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi)) 1791 resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING; 1792 if (mlx5_accel_ipsec_device_caps(dev->mdev) & 1793 MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN) 1794 resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN; 1795 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */ 1796 } 1797 1798 resp->tot_bfregs = bfregi->lib_uar_dyn ? 0 : 1799 bfregi->total_num_bfregs - bfregi->num_dyn_bfregs; 1800 resp->num_ports = dev->num_ports; 1801 resp->cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 1802 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 1803 1804 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) { 1805 mlx5_query_min_inline(dev->mdev, &resp->eth_min_inline); 1806 resp->eth_min_inline++; 1807 } 1808 1809 if (dev->mdev->clock_info) 1810 resp->clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1); 1811 1812 /* 1813 * We don't want to expose information from the PCI bar that is located 1814 * after 4096 bytes, so if the arch only supports larger pages, let's 1815 * pretend we don't support reading the HCA's core clock. This is also 1816 * forced by mmap function. 1817 */ 1818 if (PAGE_SIZE <= 4096) { 1819 resp->comp_mask |= 1820 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 1821 resp->hca_core_clock_offset = 1822 offsetof(struct mlx5_init_seg, 1823 internal_timer_h) % PAGE_SIZE; 1824 } 1825 1826 if (MLX5_CAP_GEN(dev->mdev, ece_support)) 1827 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE; 1828 1829 resp->num_dyn_bfregs = bfregi->num_dyn_bfregs; 1830 return 0; 1831 } 1832 1833 static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx, 1834 struct ib_udata *udata) 1835 { 1836 struct ib_device *ibdev = uctx->device; 1837 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1838 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 1839 struct mlx5_ib_alloc_ucontext_resp resp = {}; 1840 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 1841 struct mlx5_bfreg_info *bfregi; 1842 int ver; 1843 int err; 1844 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 1845 max_cqe_version); 1846 bool lib_uar_4k; 1847 bool lib_uar_dyn; 1848 1849 if (!dev->ib_active) 1850 return -EAGAIN; 1851 1852 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 1853 ver = 0; 1854 else if (udata->inlen >= min_req_v2) 1855 ver = 2; 1856 else 1857 return -EINVAL; 1858 1859 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req))); 1860 if (err) 1861 return err; 1862 1863 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX) 1864 return -EOPNOTSUPP; 1865 1866 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 1867 return -EOPNOTSUPP; 1868 1869 req.total_num_bfregs = ALIGN(req.total_num_bfregs, 1870 MLX5_NON_FP_BFREGS_PER_UAR); 1871 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1) 1872 return -EINVAL; 1873 1874 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR; 1875 lib_uar_dyn = req.lib_caps & MLX5_LIB_CAP_DYN_UAR; 1876 bfregi = &context->bfregi; 1877 1878 if (lib_uar_dyn) { 1879 bfregi->lib_uar_dyn = lib_uar_dyn; 1880 goto uar_done; 1881 } 1882 1883 /* updates req->total_num_bfregs */ 1884 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi); 1885 if (err) 1886 goto out_ctx; 1887 1888 mutex_init(&bfregi->lock); 1889 bfregi->lib_uar_4k = lib_uar_4k; 1890 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count), 1891 GFP_KERNEL); 1892 if (!bfregi->count) { 1893 err = -ENOMEM; 1894 goto out_ctx; 1895 } 1896 1897 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages, 1898 sizeof(*bfregi->sys_pages), 1899 GFP_KERNEL); 1900 if (!bfregi->sys_pages) { 1901 err = -ENOMEM; 1902 goto out_count; 1903 } 1904 1905 err = allocate_uars(dev, context); 1906 if (err) 1907 goto out_sys_pages; 1908 1909 uar_done: 1910 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) { 1911 err = mlx5_ib_devx_create(dev, true); 1912 if (err < 0) 1913 goto out_uars; 1914 context->devx_uid = err; 1915 } 1916 1917 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn, 1918 context->devx_uid); 1919 if (err) 1920 goto out_devx; 1921 1922 INIT_LIST_HEAD(&context->db_page_list); 1923 mutex_init(&context->db_page_mutex); 1924 1925 context->cqe_version = min_t(__u8, 1926 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 1927 req.max_cqe_version); 1928 1929 err = set_ucontext_resp(uctx, &resp); 1930 if (err) 1931 goto out_mdev; 1932 1933 resp.response_length = min(udata->outlen, sizeof(resp)); 1934 err = ib_copy_to_udata(udata, &resp, resp.response_length); 1935 if (err) 1936 goto out_mdev; 1937 1938 bfregi->ver = ver; 1939 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs; 1940 context->lib_caps = req.lib_caps; 1941 print_lib_caps(dev, context->lib_caps); 1942 1943 if (mlx5_ib_lag_should_assign_affinity(dev)) { 1944 u8 port = mlx5_core_native_port_num(dev->mdev) - 1; 1945 1946 atomic_set(&context->tx_port_affinity, 1947 atomic_add_return( 1948 1, &dev->port[port].roce.tx_port_affinity)); 1949 } 1950 1951 return 0; 1952 1953 out_mdev: 1954 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 1955 out_devx: 1956 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) 1957 mlx5_ib_devx_destroy(dev, context->devx_uid); 1958 1959 out_uars: 1960 deallocate_uars(dev, context); 1961 1962 out_sys_pages: 1963 kfree(bfregi->sys_pages); 1964 1965 out_count: 1966 kfree(bfregi->count); 1967 1968 out_ctx: 1969 return err; 1970 } 1971 1972 static int mlx5_ib_query_ucontext(struct ib_ucontext *ibcontext, 1973 struct uverbs_attr_bundle *attrs) 1974 { 1975 struct mlx5_ib_alloc_ucontext_resp uctx_resp = {}; 1976 int ret; 1977 1978 ret = set_ucontext_resp(ibcontext, &uctx_resp); 1979 if (ret) 1980 return ret; 1981 1982 uctx_resp.response_length = 1983 min_t(size_t, 1984 uverbs_attr_get_len(attrs, 1985 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX), 1986 sizeof(uctx_resp)); 1987 1988 ret = uverbs_copy_to_struct_or_zero(attrs, 1989 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX, 1990 &uctx_resp, 1991 sizeof(uctx_resp)); 1992 return ret; 1993 } 1994 1995 static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1996 { 1997 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1998 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1999 struct mlx5_bfreg_info *bfregi; 2000 2001 bfregi = &context->bfregi; 2002 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 2003 2004 if (context->devx_uid) 2005 mlx5_ib_devx_destroy(dev, context->devx_uid); 2006 2007 deallocate_uars(dev, context); 2008 kfree(bfregi->sys_pages); 2009 kfree(bfregi->count); 2010 } 2011 2012 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, 2013 int uar_idx) 2014 { 2015 int fw_uars_per_page; 2016 2017 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1; 2018 2019 return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page; 2020 } 2021 2022 static u64 uar_index2paddress(struct mlx5_ib_dev *dev, 2023 int uar_idx) 2024 { 2025 unsigned int fw_uars_per_page; 2026 2027 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 2028 MLX5_UARS_IN_PAGE : 1; 2029 2030 return (dev->mdev->bar_addr + (uar_idx / fw_uars_per_page) * PAGE_SIZE); 2031 } 2032 2033 static int get_command(unsigned long offset) 2034 { 2035 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 2036 } 2037 2038 static int get_arg(unsigned long offset) 2039 { 2040 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 2041 } 2042 2043 static int get_index(unsigned long offset) 2044 { 2045 return get_arg(offset); 2046 } 2047 2048 /* Index resides in an extra byte to enable larger values than 255 */ 2049 static int get_extended_index(unsigned long offset) 2050 { 2051 return get_arg(offset) | ((offset >> 16) & 0xff) << 8; 2052 } 2053 2054 2055 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 2056 { 2057 } 2058 2059 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 2060 { 2061 switch (cmd) { 2062 case MLX5_IB_MMAP_WC_PAGE: 2063 return "WC"; 2064 case MLX5_IB_MMAP_REGULAR_PAGE: 2065 return "best effort WC"; 2066 case MLX5_IB_MMAP_NC_PAGE: 2067 return "NC"; 2068 case MLX5_IB_MMAP_DEVICE_MEM: 2069 return "Device Memory"; 2070 default: 2071 return NULL; 2072 } 2073 } 2074 2075 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev, 2076 struct vm_area_struct *vma, 2077 struct mlx5_ib_ucontext *context) 2078 { 2079 if ((vma->vm_end - vma->vm_start != PAGE_SIZE) || 2080 !(vma->vm_flags & VM_SHARED)) 2081 return -EINVAL; 2082 2083 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1) 2084 return -EOPNOTSUPP; 2085 2086 if (vma->vm_flags & (VM_WRITE | VM_EXEC)) 2087 return -EPERM; 2088 vma->vm_flags &= ~VM_MAYWRITE; 2089 2090 if (!dev->mdev->clock_info) 2091 return -EOPNOTSUPP; 2092 2093 return vm_insert_page(vma, vma->vm_start, 2094 virt_to_page(dev->mdev->clock_info)); 2095 } 2096 2097 static void mlx5_ib_mmap_free(struct rdma_user_mmap_entry *entry) 2098 { 2099 struct mlx5_user_mmap_entry *mentry = to_mmmap(entry); 2100 struct mlx5_ib_dev *dev = to_mdev(entry->ucontext->device); 2101 struct mlx5_var_table *var_table = &dev->var_table; 2102 struct mlx5_ib_dm *mdm; 2103 2104 switch (mentry->mmap_flag) { 2105 case MLX5_IB_MMAP_TYPE_MEMIC: 2106 mdm = container_of(mentry, struct mlx5_ib_dm, mentry); 2107 mlx5_cmd_dealloc_memic(&dev->dm, mdm->dev_addr, 2108 mdm->size); 2109 kfree(mdm); 2110 break; 2111 case MLX5_IB_MMAP_TYPE_VAR: 2112 mutex_lock(&var_table->bitmap_lock); 2113 clear_bit(mentry->page_idx, var_table->bitmap); 2114 mutex_unlock(&var_table->bitmap_lock); 2115 kfree(mentry); 2116 break; 2117 case MLX5_IB_MMAP_TYPE_UAR_WC: 2118 case MLX5_IB_MMAP_TYPE_UAR_NC: 2119 mlx5_cmd_free_uar(dev->mdev, mentry->page_idx); 2120 kfree(mentry); 2121 break; 2122 default: 2123 WARN_ON(true); 2124 } 2125 } 2126 2127 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 2128 struct vm_area_struct *vma, 2129 struct mlx5_ib_ucontext *context) 2130 { 2131 struct mlx5_bfreg_info *bfregi = &context->bfregi; 2132 int err; 2133 unsigned long idx; 2134 phys_addr_t pfn; 2135 pgprot_t prot; 2136 u32 bfreg_dyn_idx = 0; 2137 u32 uar_index; 2138 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC); 2139 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages : 2140 bfregi->num_static_sys_pages; 2141 2142 if (bfregi->lib_uar_dyn) 2143 return -EINVAL; 2144 2145 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2146 return -EINVAL; 2147 2148 if (dyn_uar) 2149 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages; 2150 else 2151 idx = get_index(vma->vm_pgoff); 2152 2153 if (idx >= max_valid_idx) { 2154 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n", 2155 idx, max_valid_idx); 2156 return -EINVAL; 2157 } 2158 2159 switch (cmd) { 2160 case MLX5_IB_MMAP_WC_PAGE: 2161 case MLX5_IB_MMAP_ALLOC_WC: 2162 case MLX5_IB_MMAP_REGULAR_PAGE: 2163 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 2164 prot = pgprot_writecombine(vma->vm_page_prot); 2165 break; 2166 case MLX5_IB_MMAP_NC_PAGE: 2167 prot = pgprot_noncached(vma->vm_page_prot); 2168 break; 2169 default: 2170 return -EINVAL; 2171 } 2172 2173 if (dyn_uar) { 2174 int uars_per_page; 2175 2176 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k); 2177 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR); 2178 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) { 2179 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n", 2180 bfreg_dyn_idx, bfregi->total_num_bfregs); 2181 return -EINVAL; 2182 } 2183 2184 mutex_lock(&bfregi->lock); 2185 /* Fail if uar already allocated, first bfreg index of each 2186 * page holds its count. 2187 */ 2188 if (bfregi->count[bfreg_dyn_idx]) { 2189 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx); 2190 mutex_unlock(&bfregi->lock); 2191 return -EINVAL; 2192 } 2193 2194 bfregi->count[bfreg_dyn_idx]++; 2195 mutex_unlock(&bfregi->lock); 2196 2197 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index); 2198 if (err) { 2199 mlx5_ib_warn(dev, "UAR alloc failed\n"); 2200 goto free_bfreg; 2201 } 2202 } else { 2203 uar_index = bfregi->sys_pages[idx]; 2204 } 2205 2206 pfn = uar_index2pfn(dev, uar_index); 2207 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 2208 2209 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE, 2210 prot, NULL); 2211 if (err) { 2212 mlx5_ib_err(dev, 2213 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n", 2214 err, mmap_cmd2str(cmd)); 2215 goto err; 2216 } 2217 2218 if (dyn_uar) 2219 bfregi->sys_pages[idx] = uar_index; 2220 return 0; 2221 2222 err: 2223 if (!dyn_uar) 2224 return err; 2225 2226 mlx5_cmd_free_uar(dev->mdev, idx); 2227 2228 free_bfreg: 2229 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx); 2230 2231 return err; 2232 } 2233 2234 static int add_dm_mmap_entry(struct ib_ucontext *context, 2235 struct mlx5_ib_dm *mdm, 2236 u64 address) 2237 { 2238 mdm->mentry.mmap_flag = MLX5_IB_MMAP_TYPE_MEMIC; 2239 mdm->mentry.address = address; 2240 return rdma_user_mmap_entry_insert_range( 2241 context, &mdm->mentry.rdma_entry, 2242 mdm->size, 2243 MLX5_IB_MMAP_DEVICE_MEM << 16, 2244 (MLX5_IB_MMAP_DEVICE_MEM << 16) + (1UL << 16) - 1); 2245 } 2246 2247 static unsigned long mlx5_vma_to_pgoff(struct vm_area_struct *vma) 2248 { 2249 unsigned long idx; 2250 u8 command; 2251 2252 command = get_command(vma->vm_pgoff); 2253 idx = get_extended_index(vma->vm_pgoff); 2254 2255 return (command << 16 | idx); 2256 } 2257 2258 static int mlx5_ib_mmap_offset(struct mlx5_ib_dev *dev, 2259 struct vm_area_struct *vma, 2260 struct ib_ucontext *ucontext) 2261 { 2262 struct mlx5_user_mmap_entry *mentry; 2263 struct rdma_user_mmap_entry *entry; 2264 unsigned long pgoff; 2265 pgprot_t prot; 2266 phys_addr_t pfn; 2267 int ret; 2268 2269 pgoff = mlx5_vma_to_pgoff(vma); 2270 entry = rdma_user_mmap_entry_get_pgoff(ucontext, pgoff); 2271 if (!entry) 2272 return -EINVAL; 2273 2274 mentry = to_mmmap(entry); 2275 pfn = (mentry->address >> PAGE_SHIFT); 2276 if (mentry->mmap_flag == MLX5_IB_MMAP_TYPE_VAR || 2277 mentry->mmap_flag == MLX5_IB_MMAP_TYPE_UAR_NC) 2278 prot = pgprot_noncached(vma->vm_page_prot); 2279 else 2280 prot = pgprot_writecombine(vma->vm_page_prot); 2281 ret = rdma_user_mmap_io(ucontext, vma, pfn, 2282 entry->npages * PAGE_SIZE, 2283 prot, 2284 entry); 2285 rdma_user_mmap_entry_put(&mentry->rdma_entry); 2286 return ret; 2287 } 2288 2289 static u64 mlx5_entry_to_mmap_offset(struct mlx5_user_mmap_entry *entry) 2290 { 2291 u64 cmd = (entry->rdma_entry.start_pgoff >> 16) & 0xFFFF; 2292 u64 index = entry->rdma_entry.start_pgoff & 0xFFFF; 2293 2294 return (((index >> 8) << 16) | (cmd << MLX5_IB_MMAP_CMD_SHIFT) | 2295 (index & 0xFF)) << PAGE_SHIFT; 2296 } 2297 2298 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 2299 { 2300 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2301 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2302 unsigned long command; 2303 phys_addr_t pfn; 2304 2305 command = get_command(vma->vm_pgoff); 2306 switch (command) { 2307 case MLX5_IB_MMAP_WC_PAGE: 2308 case MLX5_IB_MMAP_ALLOC_WC: 2309 if (!dev->wc_support) 2310 return -EPERM; 2311 fallthrough; 2312 case MLX5_IB_MMAP_NC_PAGE: 2313 case MLX5_IB_MMAP_REGULAR_PAGE: 2314 return uar_mmap(dev, command, vma, context); 2315 2316 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 2317 return -ENOSYS; 2318 2319 case MLX5_IB_MMAP_CORE_CLOCK: 2320 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2321 return -EINVAL; 2322 2323 if (vma->vm_flags & VM_WRITE) 2324 return -EPERM; 2325 vma->vm_flags &= ~VM_MAYWRITE; 2326 2327 /* Don't expose to user-space information it shouldn't have */ 2328 if (PAGE_SIZE > 4096) 2329 return -EOPNOTSUPP; 2330 2331 pfn = (dev->mdev->iseg_base + 2332 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 2333 PAGE_SHIFT; 2334 return rdma_user_mmap_io(&context->ibucontext, vma, pfn, 2335 PAGE_SIZE, 2336 pgprot_noncached(vma->vm_page_prot), 2337 NULL); 2338 case MLX5_IB_MMAP_CLOCK_INFO: 2339 return mlx5_ib_mmap_clock_info_page(dev, vma, context); 2340 2341 default: 2342 return mlx5_ib_mmap_offset(dev, vma, ibcontext); 2343 } 2344 2345 return 0; 2346 } 2347 2348 static inline int check_dm_type_support(struct mlx5_ib_dev *dev, 2349 u32 type) 2350 { 2351 switch (type) { 2352 case MLX5_IB_UAPI_DM_TYPE_MEMIC: 2353 if (!MLX5_CAP_DEV_MEM(dev->mdev, memic)) 2354 return -EOPNOTSUPP; 2355 break; 2356 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM: 2357 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM: 2358 if (!capable(CAP_SYS_RAWIO) || 2359 !capable(CAP_NET_RAW)) 2360 return -EPERM; 2361 2362 if (!(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) || 2363 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, sw_owner) || 2364 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner_v2) || 2365 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, sw_owner_v2))) 2366 return -EOPNOTSUPP; 2367 break; 2368 } 2369 2370 return 0; 2371 } 2372 2373 static int handle_alloc_dm_memic(struct ib_ucontext *ctx, 2374 struct mlx5_ib_dm *dm, 2375 struct ib_dm_alloc_attr *attr, 2376 struct uverbs_attr_bundle *attrs) 2377 { 2378 struct mlx5_dm *dm_db = &to_mdev(ctx->device)->dm; 2379 u64 start_offset; 2380 u16 page_idx; 2381 int err; 2382 u64 address; 2383 2384 dm->size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE); 2385 2386 err = mlx5_cmd_alloc_memic(dm_db, &dm->dev_addr, 2387 dm->size, attr->alignment); 2388 if (err) 2389 return err; 2390 2391 address = dm->dev_addr & PAGE_MASK; 2392 err = add_dm_mmap_entry(ctx, dm, address); 2393 if (err) 2394 goto err_dealloc; 2395 2396 page_idx = dm->mentry.rdma_entry.start_pgoff & 0xFFFF; 2397 err = uverbs_copy_to(attrs, 2398 MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX, 2399 &page_idx, 2400 sizeof(page_idx)); 2401 if (err) 2402 goto err_copy; 2403 2404 start_offset = dm->dev_addr & ~PAGE_MASK; 2405 err = uverbs_copy_to(attrs, 2406 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET, 2407 &start_offset, sizeof(start_offset)); 2408 if (err) 2409 goto err_copy; 2410 2411 return 0; 2412 2413 err_copy: 2414 rdma_user_mmap_entry_remove(&dm->mentry.rdma_entry); 2415 err_dealloc: 2416 mlx5_cmd_dealloc_memic(dm_db, dm->dev_addr, dm->size); 2417 2418 return err; 2419 } 2420 2421 static int handle_alloc_dm_sw_icm(struct ib_ucontext *ctx, 2422 struct mlx5_ib_dm *dm, 2423 struct ib_dm_alloc_attr *attr, 2424 struct uverbs_attr_bundle *attrs, 2425 int type) 2426 { 2427 struct mlx5_core_dev *dev = to_mdev(ctx->device)->mdev; 2428 u64 act_size; 2429 int err; 2430 2431 /* Allocation size must a multiple of the basic block size 2432 * and a power of 2. 2433 */ 2434 act_size = round_up(attr->length, MLX5_SW_ICM_BLOCK_SIZE(dev)); 2435 act_size = roundup_pow_of_two(act_size); 2436 2437 dm->size = act_size; 2438 err = mlx5_dm_sw_icm_alloc(dev, type, act_size, attr->alignment, 2439 to_mucontext(ctx)->devx_uid, &dm->dev_addr, 2440 &dm->icm_dm.obj_id); 2441 if (err) 2442 return err; 2443 2444 err = uverbs_copy_to(attrs, 2445 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET, 2446 &dm->dev_addr, sizeof(dm->dev_addr)); 2447 if (err) 2448 mlx5_dm_sw_icm_dealloc(dev, type, dm->size, 2449 to_mucontext(ctx)->devx_uid, dm->dev_addr, 2450 dm->icm_dm.obj_id); 2451 2452 return err; 2453 } 2454 2455 struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev, 2456 struct ib_ucontext *context, 2457 struct ib_dm_alloc_attr *attr, 2458 struct uverbs_attr_bundle *attrs) 2459 { 2460 struct mlx5_ib_dm *dm; 2461 enum mlx5_ib_uapi_dm_type type; 2462 int err; 2463 2464 err = uverbs_get_const_default(&type, attrs, 2465 MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE, 2466 MLX5_IB_UAPI_DM_TYPE_MEMIC); 2467 if (err) 2468 return ERR_PTR(err); 2469 2470 mlx5_ib_dbg(to_mdev(ibdev), "alloc_dm req: dm_type=%d user_length=0x%llx log_alignment=%d\n", 2471 type, attr->length, attr->alignment); 2472 2473 err = check_dm_type_support(to_mdev(ibdev), type); 2474 if (err) 2475 return ERR_PTR(err); 2476 2477 dm = kzalloc(sizeof(*dm), GFP_KERNEL); 2478 if (!dm) 2479 return ERR_PTR(-ENOMEM); 2480 2481 dm->type = type; 2482 2483 switch (type) { 2484 case MLX5_IB_UAPI_DM_TYPE_MEMIC: 2485 err = handle_alloc_dm_memic(context, dm, 2486 attr, 2487 attrs); 2488 break; 2489 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM: 2490 err = handle_alloc_dm_sw_icm(context, dm, 2491 attr, attrs, 2492 MLX5_SW_ICM_TYPE_STEERING); 2493 break; 2494 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM: 2495 err = handle_alloc_dm_sw_icm(context, dm, 2496 attr, attrs, 2497 MLX5_SW_ICM_TYPE_HEADER_MODIFY); 2498 break; 2499 default: 2500 err = -EOPNOTSUPP; 2501 } 2502 2503 if (err) 2504 goto err_free; 2505 2506 return &dm->ibdm; 2507 2508 err_free: 2509 kfree(dm); 2510 return ERR_PTR(err); 2511 } 2512 2513 int mlx5_ib_dealloc_dm(struct ib_dm *ibdm, struct uverbs_attr_bundle *attrs) 2514 { 2515 struct mlx5_ib_ucontext *ctx = rdma_udata_to_drv_context( 2516 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext); 2517 struct mlx5_core_dev *dev = to_mdev(ibdm->device)->mdev; 2518 struct mlx5_ib_dm *dm = to_mdm(ibdm); 2519 int ret; 2520 2521 switch (dm->type) { 2522 case MLX5_IB_UAPI_DM_TYPE_MEMIC: 2523 rdma_user_mmap_entry_remove(&dm->mentry.rdma_entry); 2524 return 0; 2525 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM: 2526 ret = mlx5_dm_sw_icm_dealloc(dev, MLX5_SW_ICM_TYPE_STEERING, 2527 dm->size, ctx->devx_uid, dm->dev_addr, 2528 dm->icm_dm.obj_id); 2529 if (ret) 2530 return ret; 2531 break; 2532 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM: 2533 ret = mlx5_dm_sw_icm_dealloc(dev, MLX5_SW_ICM_TYPE_HEADER_MODIFY, 2534 dm->size, ctx->devx_uid, dm->dev_addr, 2535 dm->icm_dm.obj_id); 2536 if (ret) 2537 return ret; 2538 break; 2539 default: 2540 return -EOPNOTSUPP; 2541 } 2542 2543 kfree(dm); 2544 2545 return 0; 2546 } 2547 2548 static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata) 2549 { 2550 struct mlx5_ib_pd *pd = to_mpd(ibpd); 2551 struct ib_device *ibdev = ibpd->device; 2552 struct mlx5_ib_alloc_pd_resp resp; 2553 int err; 2554 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {}; 2555 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {}; 2556 u16 uid = 0; 2557 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 2558 udata, struct mlx5_ib_ucontext, ibucontext); 2559 2560 uid = context ? context->devx_uid : 0; 2561 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2562 MLX5_SET(alloc_pd_in, in, uid, uid); 2563 err = mlx5_cmd_exec_inout(to_mdev(ibdev)->mdev, alloc_pd, in, out); 2564 if (err) 2565 return err; 2566 2567 pd->pdn = MLX5_GET(alloc_pd_out, out, pd); 2568 pd->uid = uid; 2569 if (udata) { 2570 resp.pdn = pd->pdn; 2571 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 2572 mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid); 2573 return -EFAULT; 2574 } 2575 } 2576 2577 return 0; 2578 } 2579 2580 static int mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata) 2581 { 2582 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 2583 struct mlx5_ib_pd *mpd = to_mpd(pd); 2584 2585 return mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid); 2586 } 2587 2588 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2589 { 2590 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2591 struct mlx5_ib_qp *mqp = to_mqp(ibqp); 2592 int err; 2593 u16 uid; 2594 2595 uid = ibqp->pd ? 2596 to_mpd(ibqp->pd)->uid : 0; 2597 2598 if (mqp->flags & IB_QP_CREATE_SOURCE_QPN) { 2599 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n"); 2600 return -EOPNOTSUPP; 2601 } 2602 2603 err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 2604 if (err) 2605 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 2606 ibqp->qp_num, gid->raw); 2607 2608 return err; 2609 } 2610 2611 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2612 { 2613 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2614 int err; 2615 u16 uid; 2616 2617 uid = ibqp->pd ? 2618 to_mpd(ibqp->pd)->uid : 0; 2619 err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 2620 if (err) 2621 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 2622 ibqp->qp_num, gid->raw); 2623 2624 return err; 2625 } 2626 2627 static int init_node_data(struct mlx5_ib_dev *dev) 2628 { 2629 int err; 2630 2631 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 2632 if (err) 2633 return err; 2634 2635 dev->mdev->rev_id = dev->mdev->pdev->revision; 2636 2637 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 2638 } 2639 2640 static ssize_t fw_pages_show(struct device *device, 2641 struct device_attribute *attr, char *buf) 2642 { 2643 struct mlx5_ib_dev *dev = 2644 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2645 2646 return sysfs_emit(buf, "%d\n", dev->mdev->priv.fw_pages); 2647 } 2648 static DEVICE_ATTR_RO(fw_pages); 2649 2650 static ssize_t reg_pages_show(struct device *device, 2651 struct device_attribute *attr, char *buf) 2652 { 2653 struct mlx5_ib_dev *dev = 2654 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2655 2656 return sysfs_emit(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 2657 } 2658 static DEVICE_ATTR_RO(reg_pages); 2659 2660 static ssize_t hca_type_show(struct device *device, 2661 struct device_attribute *attr, char *buf) 2662 { 2663 struct mlx5_ib_dev *dev = 2664 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2665 2666 return sysfs_emit(buf, "MT%d\n", dev->mdev->pdev->device); 2667 } 2668 static DEVICE_ATTR_RO(hca_type); 2669 2670 static ssize_t hw_rev_show(struct device *device, 2671 struct device_attribute *attr, char *buf) 2672 { 2673 struct mlx5_ib_dev *dev = 2674 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2675 2676 return sysfs_emit(buf, "%x\n", dev->mdev->rev_id); 2677 } 2678 static DEVICE_ATTR_RO(hw_rev); 2679 2680 static ssize_t board_id_show(struct device *device, 2681 struct device_attribute *attr, char *buf) 2682 { 2683 struct mlx5_ib_dev *dev = 2684 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2685 2686 return sysfs_emit(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 2687 dev->mdev->board_id); 2688 } 2689 static DEVICE_ATTR_RO(board_id); 2690 2691 static struct attribute *mlx5_class_attributes[] = { 2692 &dev_attr_hw_rev.attr, 2693 &dev_attr_hca_type.attr, 2694 &dev_attr_board_id.attr, 2695 &dev_attr_fw_pages.attr, 2696 &dev_attr_reg_pages.attr, 2697 NULL, 2698 }; 2699 2700 static const struct attribute_group mlx5_attr_group = { 2701 .attrs = mlx5_class_attributes, 2702 }; 2703 2704 static void pkey_change_handler(struct work_struct *work) 2705 { 2706 struct mlx5_ib_port_resources *ports = 2707 container_of(work, struct mlx5_ib_port_resources, 2708 pkey_change_work); 2709 2710 mlx5_ib_gsi_pkey_change(ports->gsi); 2711 } 2712 2713 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 2714 { 2715 struct mlx5_ib_qp *mqp; 2716 struct mlx5_ib_cq *send_mcq, *recv_mcq; 2717 struct mlx5_core_cq *mcq; 2718 struct list_head cq_armed_list; 2719 unsigned long flags_qp; 2720 unsigned long flags_cq; 2721 unsigned long flags; 2722 2723 INIT_LIST_HEAD(&cq_armed_list); 2724 2725 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 2726 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 2727 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 2728 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 2729 if (mqp->sq.tail != mqp->sq.head) { 2730 send_mcq = to_mcq(mqp->ibqp.send_cq); 2731 spin_lock_irqsave(&send_mcq->lock, flags_cq); 2732 if (send_mcq->mcq.comp && 2733 mqp->ibqp.send_cq->comp_handler) { 2734 if (!send_mcq->mcq.reset_notify_added) { 2735 send_mcq->mcq.reset_notify_added = 1; 2736 list_add_tail(&send_mcq->mcq.reset_notify, 2737 &cq_armed_list); 2738 } 2739 } 2740 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 2741 } 2742 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 2743 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 2744 /* no handling is needed for SRQ */ 2745 if (!mqp->ibqp.srq) { 2746 if (mqp->rq.tail != mqp->rq.head) { 2747 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 2748 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 2749 if (recv_mcq->mcq.comp && 2750 mqp->ibqp.recv_cq->comp_handler) { 2751 if (!recv_mcq->mcq.reset_notify_added) { 2752 recv_mcq->mcq.reset_notify_added = 1; 2753 list_add_tail(&recv_mcq->mcq.reset_notify, 2754 &cq_armed_list); 2755 } 2756 } 2757 spin_unlock_irqrestore(&recv_mcq->lock, 2758 flags_cq); 2759 } 2760 } 2761 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 2762 } 2763 /*At that point all inflight post send were put to be executed as of we 2764 * lock/unlock above locks Now need to arm all involved CQs. 2765 */ 2766 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 2767 mcq->comp(mcq, NULL); 2768 } 2769 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 2770 } 2771 2772 static void delay_drop_handler(struct work_struct *work) 2773 { 2774 int err; 2775 struct mlx5_ib_delay_drop *delay_drop = 2776 container_of(work, struct mlx5_ib_delay_drop, 2777 delay_drop_work); 2778 2779 atomic_inc(&delay_drop->events_cnt); 2780 2781 mutex_lock(&delay_drop->lock); 2782 err = mlx5_core_set_delay_drop(delay_drop->dev, delay_drop->timeout); 2783 if (err) { 2784 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n", 2785 delay_drop->timeout); 2786 delay_drop->activate = false; 2787 } 2788 mutex_unlock(&delay_drop->lock); 2789 } 2790 2791 static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 2792 struct ib_event *ibev) 2793 { 2794 u8 port = (eqe->data.port.port >> 4) & 0xf; 2795 2796 switch (eqe->sub_type) { 2797 case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT: 2798 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2799 IB_LINK_LAYER_ETHERNET) 2800 schedule_work(&ibdev->delay_drop.delay_drop_work); 2801 break; 2802 default: /* do nothing */ 2803 return; 2804 } 2805 } 2806 2807 static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 2808 struct ib_event *ibev) 2809 { 2810 u8 port = (eqe->data.port.port >> 4) & 0xf; 2811 2812 ibev->element.port_num = port; 2813 2814 switch (eqe->sub_type) { 2815 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 2816 case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 2817 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED: 2818 /* In RoCE, port up/down events are handled in 2819 * mlx5_netdev_event(). 2820 */ 2821 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2822 IB_LINK_LAYER_ETHERNET) 2823 return -EINVAL; 2824 2825 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ? 2826 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 2827 break; 2828 2829 case MLX5_PORT_CHANGE_SUBTYPE_LID: 2830 ibev->event = IB_EVENT_LID_CHANGE; 2831 break; 2832 2833 case MLX5_PORT_CHANGE_SUBTYPE_PKEY: 2834 ibev->event = IB_EVENT_PKEY_CHANGE; 2835 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 2836 break; 2837 2838 case MLX5_PORT_CHANGE_SUBTYPE_GUID: 2839 ibev->event = IB_EVENT_GID_CHANGE; 2840 break; 2841 2842 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG: 2843 ibev->event = IB_EVENT_CLIENT_REREGISTER; 2844 break; 2845 default: 2846 return -EINVAL; 2847 } 2848 2849 return 0; 2850 } 2851 2852 static void mlx5_ib_handle_event(struct work_struct *_work) 2853 { 2854 struct mlx5_ib_event_work *work = 2855 container_of(_work, struct mlx5_ib_event_work, work); 2856 struct mlx5_ib_dev *ibdev; 2857 struct ib_event ibev; 2858 bool fatal = false; 2859 2860 if (work->is_slave) { 2861 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi); 2862 if (!ibdev) 2863 goto out; 2864 } else { 2865 ibdev = work->dev; 2866 } 2867 2868 switch (work->event) { 2869 case MLX5_DEV_EVENT_SYS_ERROR: 2870 ibev.event = IB_EVENT_DEVICE_FATAL; 2871 mlx5_ib_handle_internal_error(ibdev); 2872 ibev.element.port_num = (u8)(unsigned long)work->param; 2873 fatal = true; 2874 break; 2875 case MLX5_EVENT_TYPE_PORT_CHANGE: 2876 if (handle_port_change(ibdev, work->param, &ibev)) 2877 goto out; 2878 break; 2879 case MLX5_EVENT_TYPE_GENERAL_EVENT: 2880 handle_general_event(ibdev, work->param, &ibev); 2881 fallthrough; 2882 default: 2883 goto out; 2884 } 2885 2886 ibev.device = &ibdev->ib_dev; 2887 2888 if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) { 2889 mlx5_ib_warn(ibdev, "warning: event on port %d\n", ibev.element.port_num); 2890 goto out; 2891 } 2892 2893 if (ibdev->ib_active) 2894 ib_dispatch_event(&ibev); 2895 2896 if (fatal) 2897 ibdev->ib_active = false; 2898 out: 2899 kfree(work); 2900 } 2901 2902 static int mlx5_ib_event(struct notifier_block *nb, 2903 unsigned long event, void *param) 2904 { 2905 struct mlx5_ib_event_work *work; 2906 2907 work = kmalloc(sizeof(*work), GFP_ATOMIC); 2908 if (!work) 2909 return NOTIFY_DONE; 2910 2911 INIT_WORK(&work->work, mlx5_ib_handle_event); 2912 work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events); 2913 work->is_slave = false; 2914 work->param = param; 2915 work->event = event; 2916 2917 queue_work(mlx5_ib_event_wq, &work->work); 2918 2919 return NOTIFY_OK; 2920 } 2921 2922 static int mlx5_ib_event_slave_port(struct notifier_block *nb, 2923 unsigned long event, void *param) 2924 { 2925 struct mlx5_ib_event_work *work; 2926 2927 work = kmalloc(sizeof(*work), GFP_ATOMIC); 2928 if (!work) 2929 return NOTIFY_DONE; 2930 2931 INIT_WORK(&work->work, mlx5_ib_handle_event); 2932 work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events); 2933 work->is_slave = true; 2934 work->param = param; 2935 work->event = event; 2936 queue_work(mlx5_ib_event_wq, &work->work); 2937 2938 return NOTIFY_OK; 2939 } 2940 2941 static int set_has_smi_cap(struct mlx5_ib_dev *dev) 2942 { 2943 struct mlx5_hca_vport_context vport_ctx; 2944 int err; 2945 int port; 2946 2947 for (port = 1; port <= ARRAY_SIZE(dev->port_caps); port++) { 2948 dev->port_caps[port - 1].has_smi = false; 2949 if (MLX5_CAP_GEN(dev->mdev, port_type) == 2950 MLX5_CAP_PORT_TYPE_IB) { 2951 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) { 2952 err = mlx5_query_hca_vport_context(dev->mdev, 0, 2953 port, 0, 2954 &vport_ctx); 2955 if (err) { 2956 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n", 2957 port, err); 2958 return err; 2959 } 2960 dev->port_caps[port - 1].has_smi = 2961 vport_ctx.has_smi; 2962 } else { 2963 dev->port_caps[port - 1].has_smi = true; 2964 } 2965 } 2966 } 2967 return 0; 2968 } 2969 2970 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 2971 { 2972 int port; 2973 2974 for (port = 1; port <= dev->num_ports; port++) 2975 mlx5_query_ext_port_caps(dev, port); 2976 } 2977 2978 static int __get_port_caps(struct mlx5_ib_dev *dev, u8 port) 2979 { 2980 struct ib_port_attr *pprops = NULL; 2981 int err = -ENOMEM; 2982 2983 pprops = kzalloc(sizeof(*pprops), GFP_KERNEL); 2984 if (!pprops) 2985 goto out; 2986 2987 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops); 2988 if (err) { 2989 mlx5_ib_warn(dev, "query_port %d failed %d\n", 2990 port, err); 2991 goto out; 2992 } 2993 2994 dev->port_caps[port - 1].gid_table_len = pprops->gid_tbl_len; 2995 mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n", 2996 port, dev->pkey_table_len, pprops->gid_tbl_len); 2997 2998 out: 2999 kfree(pprops); 3000 return err; 3001 } 3002 3003 static int get_port_caps(struct mlx5_ib_dev *dev, u8 port) 3004 { 3005 /* For representors use port 1, is this is the only native 3006 * port 3007 */ 3008 if (dev->is_rep) 3009 return __get_port_caps(dev, 1); 3010 return __get_port_caps(dev, port); 3011 } 3012 3013 static u8 mlx5_get_umr_fence(u8 umr_fence_cap) 3014 { 3015 switch (umr_fence_cap) { 3016 case MLX5_CAP_UMR_FENCE_NONE: 3017 return MLX5_FENCE_MODE_NONE; 3018 case MLX5_CAP_UMR_FENCE_SMALL: 3019 return MLX5_FENCE_MODE_INITIATOR_SMALL; 3020 default: 3021 return MLX5_FENCE_MODE_STRONG_ORDERING; 3022 } 3023 } 3024 3025 static int mlx5_ib_dev_res_init(struct mlx5_ib_dev *dev) 3026 { 3027 struct mlx5_ib_resources *devr = &dev->devr; 3028 struct ib_srq_init_attr attr; 3029 struct ib_device *ibdev; 3030 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 3031 int port; 3032 int ret = 0; 3033 3034 ibdev = &dev->ib_dev; 3035 3036 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 3037 return -EOPNOTSUPP; 3038 3039 mutex_init(&devr->mutex); 3040 3041 devr->p0 = rdma_zalloc_drv_obj(ibdev, ib_pd); 3042 if (!devr->p0) 3043 return -ENOMEM; 3044 3045 devr->p0->device = ibdev; 3046 devr->p0->uobject = NULL; 3047 atomic_set(&devr->p0->usecnt, 0); 3048 3049 ret = mlx5_ib_alloc_pd(devr->p0, NULL); 3050 if (ret) 3051 goto error0; 3052 3053 devr->c0 = rdma_zalloc_drv_obj(ibdev, ib_cq); 3054 if (!devr->c0) { 3055 ret = -ENOMEM; 3056 goto error1; 3057 } 3058 3059 devr->c0->device = &dev->ib_dev; 3060 atomic_set(&devr->c0->usecnt, 0); 3061 3062 ret = mlx5_ib_create_cq(devr->c0, &cq_attr, NULL); 3063 if (ret) 3064 goto err_create_cq; 3065 3066 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn0, 0); 3067 if (ret) 3068 goto error2; 3069 3070 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn1, 0); 3071 if (ret) 3072 goto error3; 3073 3074 memset(&attr, 0, sizeof(attr)); 3075 attr.attr.max_sge = 1; 3076 attr.attr.max_wr = 1; 3077 attr.srq_type = IB_SRQT_XRC; 3078 attr.ext.cq = devr->c0; 3079 3080 devr->s0 = rdma_zalloc_drv_obj(ibdev, ib_srq); 3081 if (!devr->s0) { 3082 ret = -ENOMEM; 3083 goto error4; 3084 } 3085 3086 devr->s0->device = &dev->ib_dev; 3087 devr->s0->pd = devr->p0; 3088 devr->s0->srq_type = IB_SRQT_XRC; 3089 devr->s0->ext.cq = devr->c0; 3090 ret = mlx5_ib_create_srq(devr->s0, &attr, NULL); 3091 if (ret) 3092 goto err_create; 3093 3094 atomic_inc(&devr->s0->ext.cq->usecnt); 3095 atomic_inc(&devr->p0->usecnt); 3096 atomic_set(&devr->s0->usecnt, 0); 3097 3098 memset(&attr, 0, sizeof(attr)); 3099 attr.attr.max_sge = 1; 3100 attr.attr.max_wr = 1; 3101 attr.srq_type = IB_SRQT_BASIC; 3102 devr->s1 = rdma_zalloc_drv_obj(ibdev, ib_srq); 3103 if (!devr->s1) { 3104 ret = -ENOMEM; 3105 goto error5; 3106 } 3107 3108 devr->s1->device = &dev->ib_dev; 3109 devr->s1->pd = devr->p0; 3110 devr->s1->srq_type = IB_SRQT_BASIC; 3111 devr->s1->ext.cq = devr->c0; 3112 3113 ret = mlx5_ib_create_srq(devr->s1, &attr, NULL); 3114 if (ret) 3115 goto error6; 3116 3117 atomic_inc(&devr->p0->usecnt); 3118 atomic_set(&devr->s1->usecnt, 0); 3119 3120 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) 3121 INIT_WORK(&devr->ports[port].pkey_change_work, 3122 pkey_change_handler); 3123 3124 return 0; 3125 3126 error6: 3127 kfree(devr->s1); 3128 error5: 3129 mlx5_ib_destroy_srq(devr->s0, NULL); 3130 err_create: 3131 kfree(devr->s0); 3132 error4: 3133 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0); 3134 error3: 3135 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0); 3136 error2: 3137 mlx5_ib_destroy_cq(devr->c0, NULL); 3138 err_create_cq: 3139 kfree(devr->c0); 3140 error1: 3141 mlx5_ib_dealloc_pd(devr->p0, NULL); 3142 error0: 3143 kfree(devr->p0); 3144 return ret; 3145 } 3146 3147 static void mlx5_ib_dev_res_cleanup(struct mlx5_ib_dev *dev) 3148 { 3149 struct mlx5_ib_resources *devr = &dev->devr; 3150 int port; 3151 3152 mlx5_ib_destroy_srq(devr->s1, NULL); 3153 kfree(devr->s1); 3154 mlx5_ib_destroy_srq(devr->s0, NULL); 3155 kfree(devr->s0); 3156 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0); 3157 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0); 3158 mlx5_ib_destroy_cq(devr->c0, NULL); 3159 kfree(devr->c0); 3160 mlx5_ib_dealloc_pd(devr->p0, NULL); 3161 kfree(devr->p0); 3162 3163 /* Make sure no change P_Key work items are still executing */ 3164 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) 3165 cancel_work_sync(&devr->ports[port].pkey_change_work); 3166 } 3167 3168 static u32 get_core_cap_flags(struct ib_device *ibdev, 3169 struct mlx5_hca_vport_context *rep) 3170 { 3171 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3172 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 3173 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 3174 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 3175 bool raw_support = !mlx5_core_mp_enabled(dev->mdev); 3176 u32 ret = 0; 3177 3178 if (rep->grh_required) 3179 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED; 3180 3181 if (ll == IB_LINK_LAYER_INFINIBAND) 3182 return ret | RDMA_CORE_PORT_IBA_IB; 3183 3184 if (raw_support) 3185 ret |= RDMA_CORE_PORT_RAW_PACKET; 3186 3187 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 3188 return ret; 3189 3190 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 3191 return ret; 3192 3193 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 3194 ret |= RDMA_CORE_PORT_IBA_ROCE; 3195 3196 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 3197 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 3198 3199 return ret; 3200 } 3201 3202 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num, 3203 struct ib_port_immutable *immutable) 3204 { 3205 struct ib_port_attr attr; 3206 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3207 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num); 3208 struct mlx5_hca_vport_context rep = {0}; 3209 int err; 3210 3211 err = ib_query_port(ibdev, port_num, &attr); 3212 if (err) 3213 return err; 3214 3215 if (ll == IB_LINK_LAYER_INFINIBAND) { 3216 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0, 3217 &rep); 3218 if (err) 3219 return err; 3220 } 3221 3222 immutable->pkey_tbl_len = attr.pkey_tbl_len; 3223 immutable->gid_tbl_len = attr.gid_tbl_len; 3224 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep); 3225 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 3226 3227 return 0; 3228 } 3229 3230 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num, 3231 struct ib_port_immutable *immutable) 3232 { 3233 struct ib_port_attr attr; 3234 int err; 3235 3236 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 3237 3238 err = ib_query_port(ibdev, port_num, &attr); 3239 if (err) 3240 return err; 3241 3242 immutable->pkey_tbl_len = attr.pkey_tbl_len; 3243 immutable->gid_tbl_len = attr.gid_tbl_len; 3244 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 3245 3246 return 0; 3247 } 3248 3249 static void get_dev_fw_str(struct ib_device *ibdev, char *str) 3250 { 3251 struct mlx5_ib_dev *dev = 3252 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 3253 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d", 3254 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev), 3255 fw_rev_sub(dev->mdev)); 3256 } 3257 3258 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev) 3259 { 3260 struct mlx5_core_dev *mdev = dev->mdev; 3261 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev, 3262 MLX5_FLOW_NAMESPACE_LAG); 3263 struct mlx5_flow_table *ft; 3264 int err; 3265 3266 if (!ns || !mlx5_lag_is_roce(mdev)) 3267 return 0; 3268 3269 err = mlx5_cmd_create_vport_lag(mdev); 3270 if (err) 3271 return err; 3272 3273 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0); 3274 if (IS_ERR(ft)) { 3275 err = PTR_ERR(ft); 3276 goto err_destroy_vport_lag; 3277 } 3278 3279 dev->flow_db->lag_demux_ft = ft; 3280 dev->lag_active = true; 3281 return 0; 3282 3283 err_destroy_vport_lag: 3284 mlx5_cmd_destroy_vport_lag(mdev); 3285 return err; 3286 } 3287 3288 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev) 3289 { 3290 struct mlx5_core_dev *mdev = dev->mdev; 3291 3292 if (dev->lag_active) { 3293 dev->lag_active = false; 3294 3295 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft); 3296 dev->flow_db->lag_demux_ft = NULL; 3297 3298 mlx5_cmd_destroy_vport_lag(mdev); 3299 } 3300 } 3301 3302 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num) 3303 { 3304 int err; 3305 3306 dev->port[port_num].roce.nb.notifier_call = mlx5_netdev_event; 3307 err = register_netdevice_notifier_net(mlx5_core_net(dev->mdev), 3308 &dev->port[port_num].roce.nb); 3309 if (err) { 3310 dev->port[port_num].roce.nb.notifier_call = NULL; 3311 return err; 3312 } 3313 3314 return 0; 3315 } 3316 3317 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num) 3318 { 3319 if (dev->port[port_num].roce.nb.notifier_call) { 3320 unregister_netdevice_notifier_net(mlx5_core_net(dev->mdev), 3321 &dev->port[port_num].roce.nb); 3322 dev->port[port_num].roce.nb.notifier_call = NULL; 3323 } 3324 } 3325 3326 static int mlx5_enable_eth(struct mlx5_ib_dev *dev) 3327 { 3328 int err; 3329 3330 err = mlx5_nic_vport_enable_roce(dev->mdev); 3331 if (err) 3332 return err; 3333 3334 err = mlx5_eth_lag_init(dev); 3335 if (err) 3336 goto err_disable_roce; 3337 3338 return 0; 3339 3340 err_disable_roce: 3341 mlx5_nic_vport_disable_roce(dev->mdev); 3342 3343 return err; 3344 } 3345 3346 static void mlx5_disable_eth(struct mlx5_ib_dev *dev) 3347 { 3348 mlx5_eth_lag_cleanup(dev); 3349 mlx5_nic_vport_disable_roce(dev->mdev); 3350 } 3351 3352 static int mlx5_ib_rn_get_params(struct ib_device *device, u8 port_num, 3353 enum rdma_netdev_t type, 3354 struct rdma_netdev_alloc_params *params) 3355 { 3356 if (type != RDMA_NETDEV_IPOIB) 3357 return -EOPNOTSUPP; 3358 3359 return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params); 3360 } 3361 3362 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf, 3363 size_t count, loff_t *pos) 3364 { 3365 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3366 char lbuf[20]; 3367 int len; 3368 3369 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout); 3370 return simple_read_from_buffer(buf, count, pos, lbuf, len); 3371 } 3372 3373 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf, 3374 size_t count, loff_t *pos) 3375 { 3376 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3377 u32 timeout; 3378 u32 var; 3379 3380 if (kstrtouint_from_user(buf, count, 0, &var)) 3381 return -EFAULT; 3382 3383 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 3384 1000); 3385 if (timeout != var) 3386 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n", 3387 timeout); 3388 3389 delay_drop->timeout = timeout; 3390 3391 return count; 3392 } 3393 3394 static const struct file_operations fops_delay_drop_timeout = { 3395 .owner = THIS_MODULE, 3396 .open = simple_open, 3397 .write = delay_drop_timeout_write, 3398 .read = delay_drop_timeout_read, 3399 }; 3400 3401 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev, 3402 struct mlx5_ib_multiport_info *mpi) 3403 { 3404 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 3405 struct mlx5_ib_port *port = &ibdev->port[port_num]; 3406 int comps; 3407 int err; 3408 int i; 3409 3410 lockdep_assert_held(&mlx5_ib_multiport_mutex); 3411 3412 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num); 3413 3414 spin_lock(&port->mp.mpi_lock); 3415 if (!mpi->ibdev) { 3416 spin_unlock(&port->mp.mpi_lock); 3417 return; 3418 } 3419 3420 mpi->ibdev = NULL; 3421 3422 spin_unlock(&port->mp.mpi_lock); 3423 if (mpi->mdev_events.notifier_call) 3424 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events); 3425 mpi->mdev_events.notifier_call = NULL; 3426 mlx5_remove_netdev_notifier(ibdev, port_num); 3427 spin_lock(&port->mp.mpi_lock); 3428 3429 comps = mpi->mdev_refcnt; 3430 if (comps) { 3431 mpi->unaffiliate = true; 3432 init_completion(&mpi->unref_comp); 3433 spin_unlock(&port->mp.mpi_lock); 3434 3435 for (i = 0; i < comps; i++) 3436 wait_for_completion(&mpi->unref_comp); 3437 3438 spin_lock(&port->mp.mpi_lock); 3439 mpi->unaffiliate = false; 3440 } 3441 3442 port->mp.mpi = NULL; 3443 3444 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 3445 3446 spin_unlock(&port->mp.mpi_lock); 3447 3448 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev); 3449 3450 mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1); 3451 /* Log an error, still needed to cleanup the pointers and add 3452 * it back to the list. 3453 */ 3454 if (err) 3455 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n", 3456 port_num + 1); 3457 3458 ibdev->port[port_num].roce.last_port_state = IB_PORT_DOWN; 3459 } 3460 3461 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev, 3462 struct mlx5_ib_multiport_info *mpi) 3463 { 3464 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 3465 int err; 3466 3467 lockdep_assert_held(&mlx5_ib_multiport_mutex); 3468 3469 spin_lock(&ibdev->port[port_num].mp.mpi_lock); 3470 if (ibdev->port[port_num].mp.mpi) { 3471 mlx5_ib_dbg(ibdev, "port %d already affiliated.\n", 3472 port_num + 1); 3473 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 3474 return false; 3475 } 3476 3477 ibdev->port[port_num].mp.mpi = mpi; 3478 mpi->ibdev = ibdev; 3479 mpi->mdev_events.notifier_call = NULL; 3480 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 3481 3482 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev); 3483 if (err) 3484 goto unbind; 3485 3486 err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev)); 3487 if (err) 3488 goto unbind; 3489 3490 err = mlx5_add_netdev_notifier(ibdev, port_num); 3491 if (err) { 3492 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n", 3493 port_num + 1); 3494 goto unbind; 3495 } 3496 3497 mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port; 3498 mlx5_notifier_register(mpi->mdev, &mpi->mdev_events); 3499 3500 mlx5_ib_init_cong_debugfs(ibdev, port_num); 3501 3502 return true; 3503 3504 unbind: 3505 mlx5_ib_unbind_slave_port(ibdev, mpi); 3506 return false; 3507 } 3508 3509 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev) 3510 { 3511 int port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3512 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 3513 port_num + 1); 3514 struct mlx5_ib_multiport_info *mpi; 3515 int err; 3516 int i; 3517 3518 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 3519 return 0; 3520 3521 err = mlx5_query_nic_vport_system_image_guid(dev->mdev, 3522 &dev->sys_image_guid); 3523 if (err) 3524 return err; 3525 3526 err = mlx5_nic_vport_enable_roce(dev->mdev); 3527 if (err) 3528 return err; 3529 3530 mutex_lock(&mlx5_ib_multiport_mutex); 3531 for (i = 0; i < dev->num_ports; i++) { 3532 bool bound = false; 3533 3534 /* build a stub multiport info struct for the native port. */ 3535 if (i == port_num) { 3536 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 3537 if (!mpi) { 3538 mutex_unlock(&mlx5_ib_multiport_mutex); 3539 mlx5_nic_vport_disable_roce(dev->mdev); 3540 return -ENOMEM; 3541 } 3542 3543 mpi->is_master = true; 3544 mpi->mdev = dev->mdev; 3545 mpi->sys_image_guid = dev->sys_image_guid; 3546 dev->port[i].mp.mpi = mpi; 3547 mpi->ibdev = dev; 3548 mpi = NULL; 3549 continue; 3550 } 3551 3552 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list, 3553 list) { 3554 if (dev->sys_image_guid == mpi->sys_image_guid && 3555 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) { 3556 bound = mlx5_ib_bind_slave_port(dev, mpi); 3557 } 3558 3559 if (bound) { 3560 dev_dbg(mpi->mdev->device, 3561 "removing port from unaffiliated list.\n"); 3562 mlx5_ib_dbg(dev, "port %d bound\n", i + 1); 3563 list_del(&mpi->list); 3564 break; 3565 } 3566 } 3567 if (!bound) { 3568 get_port_caps(dev, i + 1); 3569 mlx5_ib_dbg(dev, "no free port found for port %d\n", 3570 i + 1); 3571 } 3572 } 3573 3574 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list); 3575 mutex_unlock(&mlx5_ib_multiport_mutex); 3576 return err; 3577 } 3578 3579 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev) 3580 { 3581 int port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3582 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 3583 port_num + 1); 3584 int i; 3585 3586 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 3587 return; 3588 3589 mutex_lock(&mlx5_ib_multiport_mutex); 3590 for (i = 0; i < dev->num_ports; i++) { 3591 if (dev->port[i].mp.mpi) { 3592 /* Destroy the native port stub */ 3593 if (i == port_num) { 3594 kfree(dev->port[i].mp.mpi); 3595 dev->port[i].mp.mpi = NULL; 3596 } else { 3597 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1); 3598 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi); 3599 } 3600 } 3601 } 3602 3603 mlx5_ib_dbg(dev, "removing from devlist\n"); 3604 list_del(&dev->ib_dev_list); 3605 mutex_unlock(&mlx5_ib_multiport_mutex); 3606 3607 mlx5_nic_vport_disable_roce(dev->mdev); 3608 } 3609 3610 static int mmap_obj_cleanup(struct ib_uobject *uobject, 3611 enum rdma_remove_reason why, 3612 struct uverbs_attr_bundle *attrs) 3613 { 3614 struct mlx5_user_mmap_entry *obj = uobject->object; 3615 3616 rdma_user_mmap_entry_remove(&obj->rdma_entry); 3617 return 0; 3618 } 3619 3620 static int mlx5_rdma_user_mmap_entry_insert(struct mlx5_ib_ucontext *c, 3621 struct mlx5_user_mmap_entry *entry, 3622 size_t length) 3623 { 3624 return rdma_user_mmap_entry_insert_range( 3625 &c->ibucontext, &entry->rdma_entry, length, 3626 (MLX5_IB_MMAP_OFFSET_START << 16), 3627 ((MLX5_IB_MMAP_OFFSET_END << 16) + (1UL << 16) - 1)); 3628 } 3629 3630 static struct mlx5_user_mmap_entry * 3631 alloc_var_entry(struct mlx5_ib_ucontext *c) 3632 { 3633 struct mlx5_user_mmap_entry *entry; 3634 struct mlx5_var_table *var_table; 3635 u32 page_idx; 3636 int err; 3637 3638 var_table = &to_mdev(c->ibucontext.device)->var_table; 3639 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 3640 if (!entry) 3641 return ERR_PTR(-ENOMEM); 3642 3643 mutex_lock(&var_table->bitmap_lock); 3644 page_idx = find_first_zero_bit(var_table->bitmap, 3645 var_table->num_var_hw_entries); 3646 if (page_idx >= var_table->num_var_hw_entries) { 3647 err = -ENOSPC; 3648 mutex_unlock(&var_table->bitmap_lock); 3649 goto end; 3650 } 3651 3652 set_bit(page_idx, var_table->bitmap); 3653 mutex_unlock(&var_table->bitmap_lock); 3654 3655 entry->address = var_table->hw_start_addr + 3656 (page_idx * var_table->stride_size); 3657 entry->page_idx = page_idx; 3658 entry->mmap_flag = MLX5_IB_MMAP_TYPE_VAR; 3659 3660 err = mlx5_rdma_user_mmap_entry_insert(c, entry, 3661 var_table->stride_size); 3662 if (err) 3663 goto err_insert; 3664 3665 return entry; 3666 3667 err_insert: 3668 mutex_lock(&var_table->bitmap_lock); 3669 clear_bit(page_idx, var_table->bitmap); 3670 mutex_unlock(&var_table->bitmap_lock); 3671 end: 3672 kfree(entry); 3673 return ERR_PTR(err); 3674 } 3675 3676 static int UVERBS_HANDLER(MLX5_IB_METHOD_VAR_OBJ_ALLOC)( 3677 struct uverbs_attr_bundle *attrs) 3678 { 3679 struct ib_uobject *uobj = uverbs_attr_get_uobject( 3680 attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE); 3681 struct mlx5_ib_ucontext *c; 3682 struct mlx5_user_mmap_entry *entry; 3683 u64 mmap_offset; 3684 u32 length; 3685 int err; 3686 3687 c = to_mucontext(ib_uverbs_get_ucontext(attrs)); 3688 if (IS_ERR(c)) 3689 return PTR_ERR(c); 3690 3691 entry = alloc_var_entry(c); 3692 if (IS_ERR(entry)) 3693 return PTR_ERR(entry); 3694 3695 mmap_offset = mlx5_entry_to_mmap_offset(entry); 3696 length = entry->rdma_entry.npages * PAGE_SIZE; 3697 uobj->object = entry; 3698 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE); 3699 3700 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET, 3701 &mmap_offset, sizeof(mmap_offset)); 3702 if (err) 3703 return err; 3704 3705 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID, 3706 &entry->page_idx, sizeof(entry->page_idx)); 3707 if (err) 3708 return err; 3709 3710 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH, 3711 &length, sizeof(length)); 3712 return err; 3713 } 3714 3715 DECLARE_UVERBS_NAMED_METHOD( 3716 MLX5_IB_METHOD_VAR_OBJ_ALLOC, 3717 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE, 3718 MLX5_IB_OBJECT_VAR, 3719 UVERBS_ACCESS_NEW, 3720 UA_MANDATORY), 3721 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID, 3722 UVERBS_ATTR_TYPE(u32), 3723 UA_MANDATORY), 3724 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH, 3725 UVERBS_ATTR_TYPE(u32), 3726 UA_MANDATORY), 3727 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET, 3728 UVERBS_ATTR_TYPE(u64), 3729 UA_MANDATORY)); 3730 3731 DECLARE_UVERBS_NAMED_METHOD_DESTROY( 3732 MLX5_IB_METHOD_VAR_OBJ_DESTROY, 3733 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_DESTROY_HANDLE, 3734 MLX5_IB_OBJECT_VAR, 3735 UVERBS_ACCESS_DESTROY, 3736 UA_MANDATORY)); 3737 3738 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_VAR, 3739 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup), 3740 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_ALLOC), 3741 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_DESTROY)); 3742 3743 static bool var_is_supported(struct ib_device *device) 3744 { 3745 struct mlx5_ib_dev *dev = to_mdev(device); 3746 3747 return (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 3748 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q); 3749 } 3750 3751 static struct mlx5_user_mmap_entry * 3752 alloc_uar_entry(struct mlx5_ib_ucontext *c, 3753 enum mlx5_ib_uapi_uar_alloc_type alloc_type) 3754 { 3755 struct mlx5_user_mmap_entry *entry; 3756 struct mlx5_ib_dev *dev; 3757 u32 uar_index; 3758 int err; 3759 3760 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 3761 if (!entry) 3762 return ERR_PTR(-ENOMEM); 3763 3764 dev = to_mdev(c->ibucontext.device); 3765 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index); 3766 if (err) 3767 goto end; 3768 3769 entry->page_idx = uar_index; 3770 entry->address = uar_index2paddress(dev, uar_index); 3771 if (alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF) 3772 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_WC; 3773 else 3774 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_NC; 3775 3776 err = mlx5_rdma_user_mmap_entry_insert(c, entry, PAGE_SIZE); 3777 if (err) 3778 goto err_insert; 3779 3780 return entry; 3781 3782 err_insert: 3783 mlx5_cmd_free_uar(dev->mdev, uar_index); 3784 end: 3785 kfree(entry); 3786 return ERR_PTR(err); 3787 } 3788 3789 static int UVERBS_HANDLER(MLX5_IB_METHOD_UAR_OBJ_ALLOC)( 3790 struct uverbs_attr_bundle *attrs) 3791 { 3792 struct ib_uobject *uobj = uverbs_attr_get_uobject( 3793 attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE); 3794 enum mlx5_ib_uapi_uar_alloc_type alloc_type; 3795 struct mlx5_ib_ucontext *c; 3796 struct mlx5_user_mmap_entry *entry; 3797 u64 mmap_offset; 3798 u32 length; 3799 int err; 3800 3801 c = to_mucontext(ib_uverbs_get_ucontext(attrs)); 3802 if (IS_ERR(c)) 3803 return PTR_ERR(c); 3804 3805 err = uverbs_get_const(&alloc_type, attrs, 3806 MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE); 3807 if (err) 3808 return err; 3809 3810 if (alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF && 3811 alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_NC) 3812 return -EOPNOTSUPP; 3813 3814 if (!to_mdev(c->ibucontext.device)->wc_support && 3815 alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF) 3816 return -EOPNOTSUPP; 3817 3818 entry = alloc_uar_entry(c, alloc_type); 3819 if (IS_ERR(entry)) 3820 return PTR_ERR(entry); 3821 3822 mmap_offset = mlx5_entry_to_mmap_offset(entry); 3823 length = entry->rdma_entry.npages * PAGE_SIZE; 3824 uobj->object = entry; 3825 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE); 3826 3827 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET, 3828 &mmap_offset, sizeof(mmap_offset)); 3829 if (err) 3830 return err; 3831 3832 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID, 3833 &entry->page_idx, sizeof(entry->page_idx)); 3834 if (err) 3835 return err; 3836 3837 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH, 3838 &length, sizeof(length)); 3839 return err; 3840 } 3841 3842 DECLARE_UVERBS_NAMED_METHOD( 3843 MLX5_IB_METHOD_UAR_OBJ_ALLOC, 3844 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE, 3845 MLX5_IB_OBJECT_UAR, 3846 UVERBS_ACCESS_NEW, 3847 UA_MANDATORY), 3848 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE, 3849 enum mlx5_ib_uapi_uar_alloc_type, 3850 UA_MANDATORY), 3851 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID, 3852 UVERBS_ATTR_TYPE(u32), 3853 UA_MANDATORY), 3854 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH, 3855 UVERBS_ATTR_TYPE(u32), 3856 UA_MANDATORY), 3857 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET, 3858 UVERBS_ATTR_TYPE(u64), 3859 UA_MANDATORY)); 3860 3861 DECLARE_UVERBS_NAMED_METHOD_DESTROY( 3862 MLX5_IB_METHOD_UAR_OBJ_DESTROY, 3863 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_DESTROY_HANDLE, 3864 MLX5_IB_OBJECT_UAR, 3865 UVERBS_ACCESS_DESTROY, 3866 UA_MANDATORY)); 3867 3868 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_UAR, 3869 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup), 3870 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_ALLOC), 3871 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_DESTROY)); 3872 3873 ADD_UVERBS_ATTRIBUTES_SIMPLE( 3874 mlx5_ib_dm, 3875 UVERBS_OBJECT_DM, 3876 UVERBS_METHOD_DM_ALLOC, 3877 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET, 3878 UVERBS_ATTR_TYPE(u64), 3879 UA_MANDATORY), 3880 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX, 3881 UVERBS_ATTR_TYPE(u16), 3882 UA_OPTIONAL), 3883 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE, 3884 enum mlx5_ib_uapi_dm_type, 3885 UA_OPTIONAL)); 3886 3887 ADD_UVERBS_ATTRIBUTES_SIMPLE( 3888 mlx5_ib_flow_action, 3889 UVERBS_OBJECT_FLOW_ACTION, 3890 UVERBS_METHOD_FLOW_ACTION_ESP_CREATE, 3891 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS, 3892 enum mlx5_ib_uapi_flow_action_flags)); 3893 3894 ADD_UVERBS_ATTRIBUTES_SIMPLE( 3895 mlx5_ib_query_context, 3896 UVERBS_OBJECT_DEVICE, 3897 UVERBS_METHOD_QUERY_CONTEXT, 3898 UVERBS_ATTR_PTR_OUT( 3899 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX, 3900 UVERBS_ATTR_STRUCT(struct mlx5_ib_alloc_ucontext_resp, 3901 dump_fill_mkey), 3902 UA_MANDATORY)); 3903 3904 static const struct uapi_definition mlx5_ib_defs[] = { 3905 UAPI_DEF_CHAIN(mlx5_ib_devx_defs), 3906 UAPI_DEF_CHAIN(mlx5_ib_flow_defs), 3907 UAPI_DEF_CHAIN(mlx5_ib_qos_defs), 3908 UAPI_DEF_CHAIN(mlx5_ib_std_types_defs), 3909 3910 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_FLOW_ACTION, 3911 &mlx5_ib_flow_action), 3912 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DM, &mlx5_ib_dm), 3913 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DEVICE, &mlx5_ib_query_context), 3914 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_VAR, 3915 UAPI_DEF_IS_OBJ_SUPPORTED(var_is_supported)), 3916 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_UAR), 3917 {} 3918 }; 3919 3920 static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev) 3921 { 3922 mlx5_ib_cleanup_multiport_master(dev); 3923 WARN_ON(!xa_empty(&dev->odp_mkeys)); 3924 cleanup_srcu_struct(&dev->odp_srcu); 3925 mutex_destroy(&dev->cap_mask_mutex); 3926 WARN_ON(!xa_empty(&dev->sig_mrs)); 3927 WARN_ON(!bitmap_empty(dev->dm.memic_alloc_pages, MLX5_MAX_MEMIC_PAGES)); 3928 } 3929 3930 static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev) 3931 { 3932 struct mlx5_core_dev *mdev = dev->mdev; 3933 int err; 3934 int i; 3935 3936 for (i = 0; i < dev->num_ports; i++) { 3937 spin_lock_init(&dev->port[i].mp.mpi_lock); 3938 rwlock_init(&dev->port[i].roce.netdev_lock); 3939 dev->port[i].roce.dev = dev; 3940 dev->port[i].roce.native_port_num = i + 1; 3941 dev->port[i].roce.last_port_state = IB_PORT_DOWN; 3942 } 3943 3944 mlx5_ib_internal_fill_odp_caps(dev); 3945 3946 err = mlx5_ib_init_multiport_master(dev); 3947 if (err) 3948 return err; 3949 3950 err = set_has_smi_cap(dev); 3951 if (err) 3952 goto err_mp; 3953 3954 if (!mlx5_core_mp_enabled(mdev)) { 3955 for (i = 1; i <= dev->num_ports; i++) { 3956 err = get_port_caps(dev, i); 3957 if (err) 3958 break; 3959 } 3960 } else { 3961 err = get_port_caps(dev, mlx5_core_native_port_num(mdev)); 3962 } 3963 if (err) 3964 goto err_mp; 3965 3966 err = mlx5_query_max_pkeys(&dev->ib_dev, &dev->pkey_table_len); 3967 if (err) 3968 goto err_mp; 3969 3970 if (mlx5_use_mad_ifc(dev)) 3971 get_ext_port_caps(dev); 3972 3973 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 3974 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 3975 dev->ib_dev.phys_port_cnt = dev->num_ports; 3976 dev->ib_dev.num_comp_vectors = mlx5_comp_vectors_count(mdev); 3977 dev->ib_dev.dev.parent = mdev->device; 3978 dev->ib_dev.lag_flags = RDMA_LAG_FLAGS_HASH_ALL_SLAVES; 3979 3980 err = init_srcu_struct(&dev->odp_srcu); 3981 if (err) 3982 goto err_mp; 3983 3984 mutex_init(&dev->cap_mask_mutex); 3985 INIT_LIST_HEAD(&dev->qp_list); 3986 spin_lock_init(&dev->reset_flow_resource_lock); 3987 xa_init(&dev->odp_mkeys); 3988 xa_init(&dev->sig_mrs); 3989 atomic_set(&dev->mkey_var, 0); 3990 3991 spin_lock_init(&dev->dm.lock); 3992 dev->dm.dev = mdev; 3993 return 0; 3994 3995 err_mp: 3996 mlx5_ib_cleanup_multiport_master(dev); 3997 return err; 3998 } 3999 4000 static int mlx5_ib_enable_driver(struct ib_device *dev) 4001 { 4002 struct mlx5_ib_dev *mdev = to_mdev(dev); 4003 int ret; 4004 4005 ret = mlx5_ib_test_wc(mdev); 4006 mlx5_ib_dbg(mdev, "Write-Combining %s", 4007 mdev->wc_support ? "supported" : "not supported"); 4008 4009 return ret; 4010 } 4011 4012 static const struct ib_device_ops mlx5_ib_dev_ops = { 4013 .owner = THIS_MODULE, 4014 .driver_id = RDMA_DRIVER_MLX5, 4015 .uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION, 4016 4017 .add_gid = mlx5_ib_add_gid, 4018 .alloc_mr = mlx5_ib_alloc_mr, 4019 .alloc_mr_integrity = mlx5_ib_alloc_mr_integrity, 4020 .alloc_pd = mlx5_ib_alloc_pd, 4021 .alloc_ucontext = mlx5_ib_alloc_ucontext, 4022 .attach_mcast = mlx5_ib_mcg_attach, 4023 .check_mr_status = mlx5_ib_check_mr_status, 4024 .create_ah = mlx5_ib_create_ah, 4025 .create_cq = mlx5_ib_create_cq, 4026 .create_qp = mlx5_ib_create_qp, 4027 .create_srq = mlx5_ib_create_srq, 4028 .create_user_ah = mlx5_ib_create_ah, 4029 .dealloc_pd = mlx5_ib_dealloc_pd, 4030 .dealloc_ucontext = mlx5_ib_dealloc_ucontext, 4031 .del_gid = mlx5_ib_del_gid, 4032 .dereg_mr = mlx5_ib_dereg_mr, 4033 .destroy_ah = mlx5_ib_destroy_ah, 4034 .destroy_cq = mlx5_ib_destroy_cq, 4035 .destroy_qp = mlx5_ib_destroy_qp, 4036 .destroy_srq = mlx5_ib_destroy_srq, 4037 .detach_mcast = mlx5_ib_mcg_detach, 4038 .disassociate_ucontext = mlx5_ib_disassociate_ucontext, 4039 .drain_rq = mlx5_ib_drain_rq, 4040 .drain_sq = mlx5_ib_drain_sq, 4041 .enable_driver = mlx5_ib_enable_driver, 4042 .get_dev_fw_str = get_dev_fw_str, 4043 .get_dma_mr = mlx5_ib_get_dma_mr, 4044 .get_link_layer = mlx5_ib_port_link_layer, 4045 .map_mr_sg = mlx5_ib_map_mr_sg, 4046 .map_mr_sg_pi = mlx5_ib_map_mr_sg_pi, 4047 .mmap = mlx5_ib_mmap, 4048 .mmap_free = mlx5_ib_mmap_free, 4049 .modify_cq = mlx5_ib_modify_cq, 4050 .modify_device = mlx5_ib_modify_device, 4051 .modify_port = mlx5_ib_modify_port, 4052 .modify_qp = mlx5_ib_modify_qp, 4053 .modify_srq = mlx5_ib_modify_srq, 4054 .poll_cq = mlx5_ib_poll_cq, 4055 .post_recv = mlx5_ib_post_recv_nodrain, 4056 .post_send = mlx5_ib_post_send_nodrain, 4057 .post_srq_recv = mlx5_ib_post_srq_recv, 4058 .process_mad = mlx5_ib_process_mad, 4059 .query_ah = mlx5_ib_query_ah, 4060 .query_device = mlx5_ib_query_device, 4061 .query_gid = mlx5_ib_query_gid, 4062 .query_pkey = mlx5_ib_query_pkey, 4063 .query_qp = mlx5_ib_query_qp, 4064 .query_srq = mlx5_ib_query_srq, 4065 .query_ucontext = mlx5_ib_query_ucontext, 4066 .reg_user_mr = mlx5_ib_reg_user_mr, 4067 .reg_user_mr_dmabuf = mlx5_ib_reg_user_mr_dmabuf, 4068 .req_notify_cq = mlx5_ib_arm_cq, 4069 .rereg_user_mr = mlx5_ib_rereg_user_mr, 4070 .resize_cq = mlx5_ib_resize_cq, 4071 4072 INIT_RDMA_OBJ_SIZE(ib_ah, mlx5_ib_ah, ibah), 4073 INIT_RDMA_OBJ_SIZE(ib_counters, mlx5_ib_mcounters, ibcntrs), 4074 INIT_RDMA_OBJ_SIZE(ib_cq, mlx5_ib_cq, ibcq), 4075 INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd), 4076 INIT_RDMA_OBJ_SIZE(ib_srq, mlx5_ib_srq, ibsrq), 4077 INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext), 4078 }; 4079 4080 static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = { 4081 .rdma_netdev_get_params = mlx5_ib_rn_get_params, 4082 }; 4083 4084 static const struct ib_device_ops mlx5_ib_dev_sriov_ops = { 4085 .get_vf_config = mlx5_ib_get_vf_config, 4086 .get_vf_guid = mlx5_ib_get_vf_guid, 4087 .get_vf_stats = mlx5_ib_get_vf_stats, 4088 .set_vf_guid = mlx5_ib_set_vf_guid, 4089 .set_vf_link_state = mlx5_ib_set_vf_link_state, 4090 }; 4091 4092 static const struct ib_device_ops mlx5_ib_dev_mw_ops = { 4093 .alloc_mw = mlx5_ib_alloc_mw, 4094 .dealloc_mw = mlx5_ib_dealloc_mw, 4095 4096 INIT_RDMA_OBJ_SIZE(ib_mw, mlx5_ib_mw, ibmw), 4097 }; 4098 4099 static const struct ib_device_ops mlx5_ib_dev_xrc_ops = { 4100 .alloc_xrcd = mlx5_ib_alloc_xrcd, 4101 .dealloc_xrcd = mlx5_ib_dealloc_xrcd, 4102 4103 INIT_RDMA_OBJ_SIZE(ib_xrcd, mlx5_ib_xrcd, ibxrcd), 4104 }; 4105 4106 static const struct ib_device_ops mlx5_ib_dev_dm_ops = { 4107 .alloc_dm = mlx5_ib_alloc_dm, 4108 .dealloc_dm = mlx5_ib_dealloc_dm, 4109 .reg_dm_mr = mlx5_ib_reg_dm_mr, 4110 }; 4111 4112 static int mlx5_ib_init_var_table(struct mlx5_ib_dev *dev) 4113 { 4114 struct mlx5_core_dev *mdev = dev->mdev; 4115 struct mlx5_var_table *var_table = &dev->var_table; 4116 u8 log_doorbell_bar_size; 4117 u8 log_doorbell_stride; 4118 u64 bar_size; 4119 4120 log_doorbell_bar_size = MLX5_CAP_DEV_VDPA_EMULATION(mdev, 4121 log_doorbell_bar_size); 4122 log_doorbell_stride = MLX5_CAP_DEV_VDPA_EMULATION(mdev, 4123 log_doorbell_stride); 4124 var_table->hw_start_addr = dev->mdev->bar_addr + 4125 MLX5_CAP64_DEV_VDPA_EMULATION(mdev, 4126 doorbell_bar_offset); 4127 bar_size = (1ULL << log_doorbell_bar_size) * 4096; 4128 var_table->stride_size = 1ULL << log_doorbell_stride; 4129 var_table->num_var_hw_entries = div_u64(bar_size, 4130 var_table->stride_size); 4131 mutex_init(&var_table->bitmap_lock); 4132 var_table->bitmap = bitmap_zalloc(var_table->num_var_hw_entries, 4133 GFP_KERNEL); 4134 return (var_table->bitmap) ? 0 : -ENOMEM; 4135 } 4136 4137 static void mlx5_ib_stage_caps_cleanup(struct mlx5_ib_dev *dev) 4138 { 4139 bitmap_free(dev->var_table.bitmap); 4140 } 4141 4142 static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev) 4143 { 4144 struct mlx5_core_dev *mdev = dev->mdev; 4145 int err; 4146 4147 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 4148 IS_ENABLED(CONFIG_MLX5_CORE_IPOIB)) 4149 ib_set_device_ops(&dev->ib_dev, 4150 &mlx5_ib_dev_ipoib_enhanced_ops); 4151 4152 if (mlx5_core_is_pf(mdev)) 4153 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops); 4154 4155 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence)); 4156 4157 if (MLX5_CAP_GEN(mdev, imaicl)) 4158 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops); 4159 4160 if (MLX5_CAP_GEN(mdev, xrc)) 4161 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops); 4162 4163 if (MLX5_CAP_DEV_MEM(mdev, memic) || 4164 MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 4165 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM) 4166 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops); 4167 4168 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops); 4169 4170 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)) 4171 dev->ib_dev.driver_def = mlx5_ib_defs; 4172 4173 err = init_node_data(dev); 4174 if (err) 4175 return err; 4176 4177 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && 4178 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) || 4179 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 4180 mutex_init(&dev->lb.mutex); 4181 4182 if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 4183 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) { 4184 err = mlx5_ib_init_var_table(dev); 4185 if (err) 4186 return err; 4187 } 4188 4189 dev->ib_dev.use_cq_dim = true; 4190 4191 return 0; 4192 } 4193 4194 static const struct ib_device_ops mlx5_ib_dev_port_ops = { 4195 .get_port_immutable = mlx5_port_immutable, 4196 .query_port = mlx5_ib_query_port, 4197 }; 4198 4199 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev) 4200 { 4201 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops); 4202 return 0; 4203 } 4204 4205 static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = { 4206 .get_port_immutable = mlx5_port_rep_immutable, 4207 .query_port = mlx5_ib_rep_query_port, 4208 .query_pkey = mlx5_ib_rep_query_pkey, 4209 }; 4210 4211 static int mlx5_ib_stage_raw_eth_non_default_cb(struct mlx5_ib_dev *dev) 4212 { 4213 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops); 4214 return 0; 4215 } 4216 4217 static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = { 4218 .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table, 4219 .create_wq = mlx5_ib_create_wq, 4220 .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table, 4221 .destroy_wq = mlx5_ib_destroy_wq, 4222 .get_netdev = mlx5_ib_get_netdev, 4223 .modify_wq = mlx5_ib_modify_wq, 4224 4225 INIT_RDMA_OBJ_SIZE(ib_rwq_ind_table, mlx5_ib_rwq_ind_table, 4226 ib_rwq_ind_tbl), 4227 }; 4228 4229 static int mlx5_ib_roce_init(struct mlx5_ib_dev *dev) 4230 { 4231 struct mlx5_core_dev *mdev = dev->mdev; 4232 enum rdma_link_layer ll; 4233 int port_type_cap; 4234 u8 port_num = 0; 4235 int err; 4236 4237 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4238 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4239 4240 if (ll == IB_LINK_LAYER_ETHERNET) { 4241 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops); 4242 4243 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4244 4245 /* Register only for native ports */ 4246 err = mlx5_add_netdev_notifier(dev, port_num); 4247 if (err || dev->is_rep || !mlx5_is_roce_enabled(mdev)) 4248 /* 4249 * We don't enable ETH interface for 4250 * 1. IB representors 4251 * 2. User disabled ROCE through devlink interface 4252 */ 4253 return err; 4254 4255 err = mlx5_enable_eth(dev); 4256 if (err) 4257 goto cleanup; 4258 } 4259 4260 return 0; 4261 cleanup: 4262 mlx5_remove_netdev_notifier(dev, port_num); 4263 return err; 4264 } 4265 4266 static void mlx5_ib_roce_cleanup(struct mlx5_ib_dev *dev) 4267 { 4268 struct mlx5_core_dev *mdev = dev->mdev; 4269 enum rdma_link_layer ll; 4270 int port_type_cap; 4271 u8 port_num; 4272 4273 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4274 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4275 4276 if (ll == IB_LINK_LAYER_ETHERNET) { 4277 if (!dev->is_rep) 4278 mlx5_disable_eth(dev); 4279 4280 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4281 mlx5_remove_netdev_notifier(dev, port_num); 4282 } 4283 } 4284 4285 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev) 4286 { 4287 mlx5_ib_init_cong_debugfs(dev, 4288 mlx5_core_native_port_num(dev->mdev) - 1); 4289 return 0; 4290 } 4291 4292 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev) 4293 { 4294 mlx5_ib_cleanup_cong_debugfs(dev, 4295 mlx5_core_native_port_num(dev->mdev) - 1); 4296 } 4297 4298 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev) 4299 { 4300 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev); 4301 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar); 4302 } 4303 4304 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev) 4305 { 4306 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar); 4307 } 4308 4309 static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev) 4310 { 4311 int err; 4312 4313 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false); 4314 if (err) 4315 return err; 4316 4317 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true); 4318 if (err) 4319 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4320 4321 return err; 4322 } 4323 4324 static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev) 4325 { 4326 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 4327 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4328 } 4329 4330 static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev) 4331 { 4332 const char *name; 4333 4334 rdma_set_device_sysfs_group(&dev->ib_dev, &mlx5_attr_group); 4335 if (!mlx5_lag_is_roce(dev->mdev)) 4336 name = "mlx5_%d"; 4337 else 4338 name = "mlx5_bond_%d"; 4339 return ib_register_device(&dev->ib_dev, name, &dev->mdev->pdev->dev); 4340 } 4341 4342 static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev) 4343 { 4344 int err; 4345 4346 err = mlx5_mr_cache_cleanup(dev); 4347 if (err) 4348 mlx5_ib_warn(dev, "mr cache cleanup failed\n"); 4349 4350 if (dev->umrc.qp) 4351 mlx5_ib_destroy_qp(dev->umrc.qp, NULL); 4352 if (dev->umrc.cq) 4353 ib_free_cq(dev->umrc.cq); 4354 if (dev->umrc.pd) 4355 ib_dealloc_pd(dev->umrc.pd); 4356 } 4357 4358 static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev) 4359 { 4360 ib_unregister_device(&dev->ib_dev); 4361 } 4362 4363 enum { 4364 MAX_UMR_WR = 128, 4365 }; 4366 4367 static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev) 4368 { 4369 struct ib_qp_init_attr *init_attr = NULL; 4370 struct ib_qp_attr *attr = NULL; 4371 struct ib_pd *pd; 4372 struct ib_cq *cq; 4373 struct ib_qp *qp; 4374 int ret; 4375 4376 attr = kzalloc(sizeof(*attr), GFP_KERNEL); 4377 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL); 4378 if (!attr || !init_attr) { 4379 ret = -ENOMEM; 4380 goto error_0; 4381 } 4382 4383 pd = ib_alloc_pd(&dev->ib_dev, 0); 4384 if (IS_ERR(pd)) { 4385 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n"); 4386 ret = PTR_ERR(pd); 4387 goto error_0; 4388 } 4389 4390 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ); 4391 if (IS_ERR(cq)) { 4392 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n"); 4393 ret = PTR_ERR(cq); 4394 goto error_2; 4395 } 4396 4397 init_attr->send_cq = cq; 4398 init_attr->recv_cq = cq; 4399 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR; 4400 init_attr->cap.max_send_wr = MAX_UMR_WR; 4401 init_attr->cap.max_send_sge = 1; 4402 init_attr->qp_type = MLX5_IB_QPT_REG_UMR; 4403 init_attr->port_num = 1; 4404 qp = mlx5_ib_create_qp(pd, init_attr, NULL); 4405 if (IS_ERR(qp)) { 4406 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n"); 4407 ret = PTR_ERR(qp); 4408 goto error_3; 4409 } 4410 qp->device = &dev->ib_dev; 4411 qp->real_qp = qp; 4412 qp->uobject = NULL; 4413 qp->qp_type = MLX5_IB_QPT_REG_UMR; 4414 qp->send_cq = init_attr->send_cq; 4415 qp->recv_cq = init_attr->recv_cq; 4416 4417 attr->qp_state = IB_QPS_INIT; 4418 attr->port_num = 1; 4419 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX | 4420 IB_QP_PORT, NULL); 4421 if (ret) { 4422 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n"); 4423 goto error_4; 4424 } 4425 4426 memset(attr, 0, sizeof(*attr)); 4427 attr->qp_state = IB_QPS_RTR; 4428 attr->path_mtu = IB_MTU_256; 4429 4430 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 4431 if (ret) { 4432 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n"); 4433 goto error_4; 4434 } 4435 4436 memset(attr, 0, sizeof(*attr)); 4437 attr->qp_state = IB_QPS_RTS; 4438 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 4439 if (ret) { 4440 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n"); 4441 goto error_4; 4442 } 4443 4444 dev->umrc.qp = qp; 4445 dev->umrc.cq = cq; 4446 dev->umrc.pd = pd; 4447 4448 sema_init(&dev->umrc.sem, MAX_UMR_WR); 4449 ret = mlx5_mr_cache_init(dev); 4450 if (ret) { 4451 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 4452 goto error_4; 4453 } 4454 4455 kfree(attr); 4456 kfree(init_attr); 4457 4458 return 0; 4459 4460 error_4: 4461 mlx5_ib_destroy_qp(qp, NULL); 4462 dev->umrc.qp = NULL; 4463 4464 error_3: 4465 ib_free_cq(cq); 4466 dev->umrc.cq = NULL; 4467 4468 error_2: 4469 ib_dealloc_pd(pd); 4470 dev->umrc.pd = NULL; 4471 4472 error_0: 4473 kfree(attr); 4474 kfree(init_attr); 4475 return ret; 4476 } 4477 4478 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev) 4479 { 4480 struct dentry *root; 4481 4482 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4483 return 0; 4484 4485 mutex_init(&dev->delay_drop.lock); 4486 dev->delay_drop.dev = dev; 4487 dev->delay_drop.activate = false; 4488 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000; 4489 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler); 4490 atomic_set(&dev->delay_drop.rqs_cnt, 0); 4491 atomic_set(&dev->delay_drop.events_cnt, 0); 4492 4493 if (!mlx5_debugfs_root) 4494 return 0; 4495 4496 root = debugfs_create_dir("delay_drop", dev->mdev->priv.dbg_root); 4497 dev->delay_drop.dir_debugfs = root; 4498 4499 debugfs_create_atomic_t("num_timeout_events", 0400, root, 4500 &dev->delay_drop.events_cnt); 4501 debugfs_create_atomic_t("num_rqs", 0400, root, 4502 &dev->delay_drop.rqs_cnt); 4503 debugfs_create_file("timeout", 0600, root, &dev->delay_drop, 4504 &fops_delay_drop_timeout); 4505 return 0; 4506 } 4507 4508 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev) 4509 { 4510 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4511 return; 4512 4513 cancel_work_sync(&dev->delay_drop.delay_drop_work); 4514 if (!dev->delay_drop.dir_debugfs) 4515 return; 4516 4517 debugfs_remove_recursive(dev->delay_drop.dir_debugfs); 4518 dev->delay_drop.dir_debugfs = NULL; 4519 } 4520 4521 static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev) 4522 { 4523 dev->mdev_events.notifier_call = mlx5_ib_event; 4524 mlx5_notifier_register(dev->mdev, &dev->mdev_events); 4525 return 0; 4526 } 4527 4528 static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev) 4529 { 4530 mlx5_notifier_unregister(dev->mdev, &dev->mdev_events); 4531 } 4532 4533 void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 4534 const struct mlx5_ib_profile *profile, 4535 int stage) 4536 { 4537 dev->ib_active = false; 4538 4539 /* Number of stages to cleanup */ 4540 while (stage) { 4541 stage--; 4542 if (profile->stage[stage].cleanup) 4543 profile->stage[stage].cleanup(dev); 4544 } 4545 4546 kfree(dev->port); 4547 ib_dealloc_device(&dev->ib_dev); 4548 } 4549 4550 int __mlx5_ib_add(struct mlx5_ib_dev *dev, 4551 const struct mlx5_ib_profile *profile) 4552 { 4553 int err; 4554 int i; 4555 4556 dev->profile = profile; 4557 4558 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) { 4559 if (profile->stage[i].init) { 4560 err = profile->stage[i].init(dev); 4561 if (err) 4562 goto err_out; 4563 } 4564 } 4565 4566 dev->ib_active = true; 4567 return 0; 4568 4569 err_out: 4570 /* Clean up stages which were initialized */ 4571 while (i) { 4572 i--; 4573 if (profile->stage[i].cleanup) 4574 profile->stage[i].cleanup(dev); 4575 } 4576 return -ENOMEM; 4577 } 4578 4579 static const struct mlx5_ib_profile pf_profile = { 4580 STAGE_CREATE(MLX5_IB_STAGE_INIT, 4581 mlx5_ib_stage_init_init, 4582 mlx5_ib_stage_init_cleanup), 4583 STAGE_CREATE(MLX5_IB_STAGE_FS, 4584 mlx5_ib_fs_init, 4585 mlx5_ib_fs_cleanup), 4586 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 4587 mlx5_ib_stage_caps_init, 4588 mlx5_ib_stage_caps_cleanup), 4589 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 4590 mlx5_ib_stage_non_default_cb, 4591 NULL), 4592 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 4593 mlx5_ib_roce_init, 4594 mlx5_ib_roce_cleanup), 4595 STAGE_CREATE(MLX5_IB_STAGE_QP, 4596 mlx5_init_qp_table, 4597 mlx5_cleanup_qp_table), 4598 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 4599 mlx5_init_srq_table, 4600 mlx5_cleanup_srq_table), 4601 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 4602 mlx5_ib_dev_res_init, 4603 mlx5_ib_dev_res_cleanup), 4604 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 4605 mlx5_ib_stage_dev_notifier_init, 4606 mlx5_ib_stage_dev_notifier_cleanup), 4607 STAGE_CREATE(MLX5_IB_STAGE_ODP, 4608 mlx5_ib_odp_init_one, 4609 mlx5_ib_odp_cleanup_one), 4610 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 4611 mlx5_ib_counters_init, 4612 mlx5_ib_counters_cleanup), 4613 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 4614 mlx5_ib_stage_cong_debugfs_init, 4615 mlx5_ib_stage_cong_debugfs_cleanup), 4616 STAGE_CREATE(MLX5_IB_STAGE_UAR, 4617 mlx5_ib_stage_uar_init, 4618 mlx5_ib_stage_uar_cleanup), 4619 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 4620 mlx5_ib_stage_bfrag_init, 4621 mlx5_ib_stage_bfrag_cleanup), 4622 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 4623 NULL, 4624 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 4625 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 4626 mlx5_ib_devx_init, 4627 mlx5_ib_devx_cleanup), 4628 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 4629 mlx5_ib_stage_ib_reg_init, 4630 mlx5_ib_stage_ib_reg_cleanup), 4631 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 4632 mlx5_ib_stage_post_ib_reg_umr_init, 4633 NULL), 4634 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP, 4635 mlx5_ib_stage_delay_drop_init, 4636 mlx5_ib_stage_delay_drop_cleanup), 4637 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK, 4638 mlx5_ib_restrack_init, 4639 NULL), 4640 }; 4641 4642 const struct mlx5_ib_profile raw_eth_profile = { 4643 STAGE_CREATE(MLX5_IB_STAGE_INIT, 4644 mlx5_ib_stage_init_init, 4645 mlx5_ib_stage_init_cleanup), 4646 STAGE_CREATE(MLX5_IB_STAGE_FS, 4647 mlx5_ib_fs_init, 4648 mlx5_ib_fs_cleanup), 4649 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 4650 mlx5_ib_stage_caps_init, 4651 mlx5_ib_stage_caps_cleanup), 4652 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 4653 mlx5_ib_stage_raw_eth_non_default_cb, 4654 NULL), 4655 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 4656 mlx5_ib_roce_init, 4657 mlx5_ib_roce_cleanup), 4658 STAGE_CREATE(MLX5_IB_STAGE_QP, 4659 mlx5_init_qp_table, 4660 mlx5_cleanup_qp_table), 4661 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 4662 mlx5_init_srq_table, 4663 mlx5_cleanup_srq_table), 4664 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 4665 mlx5_ib_dev_res_init, 4666 mlx5_ib_dev_res_cleanup), 4667 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 4668 mlx5_ib_stage_dev_notifier_init, 4669 mlx5_ib_stage_dev_notifier_cleanup), 4670 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 4671 mlx5_ib_counters_init, 4672 mlx5_ib_counters_cleanup), 4673 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 4674 mlx5_ib_stage_cong_debugfs_init, 4675 mlx5_ib_stage_cong_debugfs_cleanup), 4676 STAGE_CREATE(MLX5_IB_STAGE_UAR, 4677 mlx5_ib_stage_uar_init, 4678 mlx5_ib_stage_uar_cleanup), 4679 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 4680 mlx5_ib_stage_bfrag_init, 4681 mlx5_ib_stage_bfrag_cleanup), 4682 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 4683 NULL, 4684 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 4685 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 4686 mlx5_ib_devx_init, 4687 mlx5_ib_devx_cleanup), 4688 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 4689 mlx5_ib_stage_ib_reg_init, 4690 mlx5_ib_stage_ib_reg_cleanup), 4691 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 4692 mlx5_ib_stage_post_ib_reg_umr_init, 4693 NULL), 4694 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK, 4695 mlx5_ib_restrack_init, 4696 NULL), 4697 }; 4698 4699 static int mlx5r_mp_probe(struct auxiliary_device *adev, 4700 const struct auxiliary_device_id *id) 4701 { 4702 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev); 4703 struct mlx5_core_dev *mdev = idev->mdev; 4704 struct mlx5_ib_multiport_info *mpi; 4705 struct mlx5_ib_dev *dev; 4706 bool bound = false; 4707 int err; 4708 4709 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 4710 if (!mpi) 4711 return -ENOMEM; 4712 4713 mpi->mdev = mdev; 4714 err = mlx5_query_nic_vport_system_image_guid(mdev, 4715 &mpi->sys_image_guid); 4716 if (err) { 4717 kfree(mpi); 4718 return err; 4719 } 4720 4721 mutex_lock(&mlx5_ib_multiport_mutex); 4722 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) { 4723 if (dev->sys_image_guid == mpi->sys_image_guid) 4724 bound = mlx5_ib_bind_slave_port(dev, mpi); 4725 4726 if (bound) { 4727 rdma_roce_rescan_device(&dev->ib_dev); 4728 break; 4729 } 4730 } 4731 4732 if (!bound) { 4733 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 4734 dev_dbg(mdev->device, 4735 "no suitable IB device found to bind to, added to unaffiliated list.\n"); 4736 } 4737 mutex_unlock(&mlx5_ib_multiport_mutex); 4738 4739 dev_set_drvdata(&adev->dev, mpi); 4740 return 0; 4741 } 4742 4743 static void mlx5r_mp_remove(struct auxiliary_device *adev) 4744 { 4745 struct mlx5_ib_multiport_info *mpi; 4746 4747 mpi = dev_get_drvdata(&adev->dev); 4748 mutex_lock(&mlx5_ib_multiport_mutex); 4749 if (mpi->ibdev) 4750 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi); 4751 list_del(&mpi->list); 4752 mutex_unlock(&mlx5_ib_multiport_mutex); 4753 kfree(mpi); 4754 } 4755 4756 static int mlx5r_probe(struct auxiliary_device *adev, 4757 const struct auxiliary_device_id *id) 4758 { 4759 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev); 4760 struct mlx5_core_dev *mdev = idev->mdev; 4761 const struct mlx5_ib_profile *profile; 4762 int port_type_cap, num_ports, ret; 4763 enum rdma_link_layer ll; 4764 struct mlx5_ib_dev *dev; 4765 4766 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4767 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4768 4769 num_ports = max(MLX5_CAP_GEN(mdev, num_ports), 4770 MLX5_CAP_GEN(mdev, num_vhca_ports)); 4771 dev = ib_alloc_device(mlx5_ib_dev, ib_dev); 4772 if (!dev) 4773 return -ENOMEM; 4774 dev->port = kcalloc(num_ports, sizeof(*dev->port), 4775 GFP_KERNEL); 4776 if (!dev->port) { 4777 ib_dealloc_device(&dev->ib_dev); 4778 return -ENOMEM; 4779 } 4780 4781 dev->mdev = mdev; 4782 dev->num_ports = num_ports; 4783 4784 if (ll == IB_LINK_LAYER_ETHERNET && !mlx5_is_roce_enabled(mdev)) 4785 profile = &raw_eth_profile; 4786 else 4787 profile = &pf_profile; 4788 4789 ret = __mlx5_ib_add(dev, profile); 4790 if (ret) { 4791 kfree(dev->port); 4792 ib_dealloc_device(&dev->ib_dev); 4793 return ret; 4794 } 4795 4796 dev_set_drvdata(&adev->dev, dev); 4797 return 0; 4798 } 4799 4800 static void mlx5r_remove(struct auxiliary_device *adev) 4801 { 4802 struct mlx5_ib_dev *dev; 4803 4804 dev = dev_get_drvdata(&adev->dev); 4805 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX); 4806 } 4807 4808 static const struct auxiliary_device_id mlx5r_mp_id_table[] = { 4809 { .name = MLX5_ADEV_NAME ".multiport", }, 4810 {}, 4811 }; 4812 4813 static const struct auxiliary_device_id mlx5r_id_table[] = { 4814 { .name = MLX5_ADEV_NAME ".rdma", }, 4815 {}, 4816 }; 4817 4818 MODULE_DEVICE_TABLE(auxiliary, mlx5r_mp_id_table); 4819 MODULE_DEVICE_TABLE(auxiliary, mlx5r_id_table); 4820 4821 static struct auxiliary_driver mlx5r_mp_driver = { 4822 .name = "multiport", 4823 .probe = mlx5r_mp_probe, 4824 .remove = mlx5r_mp_remove, 4825 .id_table = mlx5r_mp_id_table, 4826 }; 4827 4828 static struct auxiliary_driver mlx5r_driver = { 4829 .name = "rdma", 4830 .probe = mlx5r_probe, 4831 .remove = mlx5r_remove, 4832 .id_table = mlx5r_id_table, 4833 }; 4834 4835 static int __init mlx5_ib_init(void) 4836 { 4837 int ret; 4838 4839 xlt_emergency_page = (void *)__get_free_page(GFP_KERNEL); 4840 if (!xlt_emergency_page) 4841 return -ENOMEM; 4842 4843 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0); 4844 if (!mlx5_ib_event_wq) { 4845 free_page((unsigned long)xlt_emergency_page); 4846 return -ENOMEM; 4847 } 4848 4849 mlx5_ib_odp_init(); 4850 ret = mlx5r_rep_init(); 4851 if (ret) 4852 goto rep_err; 4853 ret = auxiliary_driver_register(&mlx5r_mp_driver); 4854 if (ret) 4855 goto mp_err; 4856 ret = auxiliary_driver_register(&mlx5r_driver); 4857 if (ret) 4858 goto drv_err; 4859 return 0; 4860 4861 drv_err: 4862 auxiliary_driver_unregister(&mlx5r_mp_driver); 4863 mp_err: 4864 mlx5r_rep_cleanup(); 4865 rep_err: 4866 destroy_workqueue(mlx5_ib_event_wq); 4867 free_page((unsigned long)xlt_emergency_page); 4868 return ret; 4869 } 4870 4871 static void __exit mlx5_ib_cleanup(void) 4872 { 4873 auxiliary_driver_unregister(&mlx5r_driver); 4874 auxiliary_driver_unregister(&mlx5r_mp_driver); 4875 mlx5r_rep_cleanup(); 4876 4877 destroy_workqueue(mlx5_ib_event_wq); 4878 free_page((unsigned long)xlt_emergency_page); 4879 } 4880 4881 module_init(mlx5_ib_init); 4882 module_exit(mlx5_ib_cleanup); 4883