1 /* 2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #include <linux/module.h> 35 #include <linux/init.h> 36 #include <linux/slab.h> 37 #include <linux/errno.h> 38 #include <linux/netdevice.h> 39 #include <linux/inetdevice.h> 40 #include <linux/rtnetlink.h> 41 #include <linux/if_vlan.h> 42 #include <linux/sched/mm.h> 43 #include <linux/sched/task.h> 44 45 #include <net/ipv6.h> 46 #include <net/addrconf.h> 47 #include <net/devlink.h> 48 49 #include <rdma/ib_smi.h> 50 #include <rdma/ib_user_verbs.h> 51 #include <rdma/ib_addr.h> 52 #include <rdma/ib_cache.h> 53 54 #include <net/bonding.h> 55 56 #include <linux/mlx4/driver.h> 57 #include <linux/mlx4/cmd.h> 58 #include <linux/mlx4/qp.h> 59 60 #include "mlx4_ib.h" 61 #include <rdma/mlx4-abi.h> 62 63 #define DRV_NAME MLX4_IB_DRV_NAME 64 #define DRV_VERSION "4.0-0" 65 66 #define MLX4_IB_FLOW_MAX_PRIO 0xFFF 67 #define MLX4_IB_FLOW_QPN_MASK 0xFFFFFF 68 #define MLX4_IB_CARD_REV_A0 0xA0 69 70 MODULE_AUTHOR("Roland Dreier"); 71 MODULE_DESCRIPTION("Mellanox ConnectX HCA InfiniBand driver"); 72 MODULE_LICENSE("Dual BSD/GPL"); 73 74 int mlx4_ib_sm_guid_assign = 0; 75 module_param_named(sm_guid_assign, mlx4_ib_sm_guid_assign, int, 0444); 76 MODULE_PARM_DESC(sm_guid_assign, "Enable SM alias_GUID assignment if sm_guid_assign > 0 (Default: 0)"); 77 78 static const char mlx4_ib_version[] = 79 DRV_NAME ": Mellanox ConnectX InfiniBand driver v" 80 DRV_VERSION "\n"; 81 82 static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init); 83 static enum rdma_link_layer mlx4_ib_port_link_layer(struct ib_device *device, 84 u8 port_num); 85 86 static struct workqueue_struct *wq; 87 88 static void init_query_mad(struct ib_smp *mad) 89 { 90 mad->base_version = 1; 91 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED; 92 mad->class_version = 1; 93 mad->method = IB_MGMT_METHOD_GET; 94 } 95 96 static int check_flow_steering_support(struct mlx4_dev *dev) 97 { 98 int eth_num_ports = 0; 99 int ib_num_ports = 0; 100 101 int dmfs = dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED; 102 103 if (dmfs) { 104 int i; 105 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) 106 eth_num_ports++; 107 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) 108 ib_num_ports++; 109 dmfs &= (!ib_num_ports || 110 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB)) && 111 (!eth_num_ports || 112 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN)); 113 if (ib_num_ports && mlx4_is_mfunc(dev)) { 114 pr_warn("Device managed flow steering is unavailable for IB port in multifunction env.\n"); 115 dmfs = 0; 116 } 117 } 118 return dmfs; 119 } 120 121 static int num_ib_ports(struct mlx4_dev *dev) 122 { 123 int ib_ports = 0; 124 int i; 125 126 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) 127 ib_ports++; 128 129 return ib_ports; 130 } 131 132 static struct net_device *mlx4_ib_get_netdev(struct ib_device *device, u8 port_num) 133 { 134 struct mlx4_ib_dev *ibdev = to_mdev(device); 135 struct net_device *dev; 136 137 rcu_read_lock(); 138 dev = mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port_num); 139 140 if (dev) { 141 if (mlx4_is_bonded(ibdev->dev)) { 142 struct net_device *upper = NULL; 143 144 upper = netdev_master_upper_dev_get_rcu(dev); 145 if (upper) { 146 struct net_device *active; 147 148 active = bond_option_active_slave_get_rcu(netdev_priv(upper)); 149 if (active) 150 dev = active; 151 } 152 } 153 } 154 if (dev) 155 dev_hold(dev); 156 157 rcu_read_unlock(); 158 return dev; 159 } 160 161 static int mlx4_ib_update_gids_v1(struct gid_entry *gids, 162 struct mlx4_ib_dev *ibdev, 163 u8 port_num) 164 { 165 struct mlx4_cmd_mailbox *mailbox; 166 int err; 167 struct mlx4_dev *dev = ibdev->dev; 168 int i; 169 union ib_gid *gid_tbl; 170 171 mailbox = mlx4_alloc_cmd_mailbox(dev); 172 if (IS_ERR(mailbox)) 173 return -ENOMEM; 174 175 gid_tbl = mailbox->buf; 176 177 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) 178 memcpy(&gid_tbl[i], &gids[i].gid, sizeof(union ib_gid)); 179 180 err = mlx4_cmd(dev, mailbox->dma, 181 MLX4_SET_PORT_GID_TABLE << 8 | port_num, 182 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 183 MLX4_CMD_WRAPPED); 184 if (mlx4_is_bonded(dev)) 185 err += mlx4_cmd(dev, mailbox->dma, 186 MLX4_SET_PORT_GID_TABLE << 8 | 2, 187 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 188 MLX4_CMD_WRAPPED); 189 190 mlx4_free_cmd_mailbox(dev, mailbox); 191 return err; 192 } 193 194 static int mlx4_ib_update_gids_v1_v2(struct gid_entry *gids, 195 struct mlx4_ib_dev *ibdev, 196 u8 port_num) 197 { 198 struct mlx4_cmd_mailbox *mailbox; 199 int err; 200 struct mlx4_dev *dev = ibdev->dev; 201 int i; 202 struct { 203 union ib_gid gid; 204 __be32 rsrvd1[2]; 205 __be16 rsrvd2; 206 u8 type; 207 u8 version; 208 __be32 rsrvd3; 209 } *gid_tbl; 210 211 mailbox = mlx4_alloc_cmd_mailbox(dev); 212 if (IS_ERR(mailbox)) 213 return -ENOMEM; 214 215 gid_tbl = mailbox->buf; 216 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) { 217 memcpy(&gid_tbl[i].gid, &gids[i].gid, sizeof(union ib_gid)); 218 if (gids[i].gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) { 219 gid_tbl[i].version = 2; 220 if (!ipv6_addr_v4mapped((struct in6_addr *)&gids[i].gid)) 221 gid_tbl[i].type = 1; 222 } 223 } 224 225 err = mlx4_cmd(dev, mailbox->dma, 226 MLX4_SET_PORT_ROCE_ADDR << 8 | port_num, 227 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 228 MLX4_CMD_WRAPPED); 229 if (mlx4_is_bonded(dev)) 230 err += mlx4_cmd(dev, mailbox->dma, 231 MLX4_SET_PORT_ROCE_ADDR << 8 | 2, 232 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 233 MLX4_CMD_WRAPPED); 234 235 mlx4_free_cmd_mailbox(dev, mailbox); 236 return err; 237 } 238 239 static int mlx4_ib_update_gids(struct gid_entry *gids, 240 struct mlx4_ib_dev *ibdev, 241 u8 port_num) 242 { 243 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) 244 return mlx4_ib_update_gids_v1_v2(gids, ibdev, port_num); 245 246 return mlx4_ib_update_gids_v1(gids, ibdev, port_num); 247 } 248 249 static int mlx4_ib_add_gid(const struct ib_gid_attr *attr, void **context) 250 { 251 struct mlx4_ib_dev *ibdev = to_mdev(attr->device); 252 struct mlx4_ib_iboe *iboe = &ibdev->iboe; 253 struct mlx4_port_gid_table *port_gid_table; 254 int free = -1, found = -1; 255 int ret = 0; 256 int hw_update = 0; 257 int i; 258 struct gid_entry *gids = NULL; 259 260 if (!rdma_cap_roce_gid_table(attr->device, attr->port_num)) 261 return -EINVAL; 262 263 if (attr->port_num > MLX4_MAX_PORTS) 264 return -EINVAL; 265 266 if (!context) 267 return -EINVAL; 268 269 port_gid_table = &iboe->gids[attr->port_num - 1]; 270 spin_lock_bh(&iboe->lock); 271 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) { 272 if (!memcmp(&port_gid_table->gids[i].gid, 273 &attr->gid, sizeof(attr->gid)) && 274 port_gid_table->gids[i].gid_type == attr->gid_type) { 275 found = i; 276 break; 277 } 278 if (free < 0 && rdma_is_zero_gid(&port_gid_table->gids[i].gid)) 279 free = i; /* HW has space */ 280 } 281 282 if (found < 0) { 283 if (free < 0) { 284 ret = -ENOSPC; 285 } else { 286 port_gid_table->gids[free].ctx = kmalloc(sizeof(*port_gid_table->gids[free].ctx), GFP_ATOMIC); 287 if (!port_gid_table->gids[free].ctx) { 288 ret = -ENOMEM; 289 } else { 290 *context = port_gid_table->gids[free].ctx; 291 memcpy(&port_gid_table->gids[free].gid, 292 &attr->gid, sizeof(attr->gid)); 293 port_gid_table->gids[free].gid_type = attr->gid_type; 294 port_gid_table->gids[free].ctx->real_index = free; 295 port_gid_table->gids[free].ctx->refcount = 1; 296 hw_update = 1; 297 } 298 } 299 } else { 300 struct gid_cache_context *ctx = port_gid_table->gids[found].ctx; 301 *context = ctx; 302 ctx->refcount++; 303 } 304 if (!ret && hw_update) { 305 gids = kmalloc_array(MLX4_MAX_PORT_GIDS, sizeof(*gids), 306 GFP_ATOMIC); 307 if (!gids) { 308 ret = -ENOMEM; 309 } else { 310 for (i = 0; i < MLX4_MAX_PORT_GIDS; i++) { 311 memcpy(&gids[i].gid, &port_gid_table->gids[i].gid, sizeof(union ib_gid)); 312 gids[i].gid_type = port_gid_table->gids[i].gid_type; 313 } 314 } 315 } 316 spin_unlock_bh(&iboe->lock); 317 318 if (!ret && hw_update) { 319 ret = mlx4_ib_update_gids(gids, ibdev, attr->port_num); 320 kfree(gids); 321 } 322 323 return ret; 324 } 325 326 static int mlx4_ib_del_gid(const struct ib_gid_attr *attr, void **context) 327 { 328 struct gid_cache_context *ctx = *context; 329 struct mlx4_ib_dev *ibdev = to_mdev(attr->device); 330 struct mlx4_ib_iboe *iboe = &ibdev->iboe; 331 struct mlx4_port_gid_table *port_gid_table; 332 int ret = 0; 333 int hw_update = 0; 334 struct gid_entry *gids = NULL; 335 336 if (!rdma_cap_roce_gid_table(attr->device, attr->port_num)) 337 return -EINVAL; 338 339 if (attr->port_num > MLX4_MAX_PORTS) 340 return -EINVAL; 341 342 port_gid_table = &iboe->gids[attr->port_num - 1]; 343 spin_lock_bh(&iboe->lock); 344 if (ctx) { 345 ctx->refcount--; 346 if (!ctx->refcount) { 347 unsigned int real_index = ctx->real_index; 348 349 memset(&port_gid_table->gids[real_index].gid, 0, 350 sizeof(port_gid_table->gids[real_index].gid)); 351 kfree(port_gid_table->gids[real_index].ctx); 352 port_gid_table->gids[real_index].ctx = NULL; 353 hw_update = 1; 354 } 355 } 356 if (!ret && hw_update) { 357 int i; 358 359 gids = kmalloc_array(MLX4_MAX_PORT_GIDS, sizeof(*gids), 360 GFP_ATOMIC); 361 if (!gids) { 362 ret = -ENOMEM; 363 } else { 364 for (i = 0; i < MLX4_MAX_PORT_GIDS; i++) { 365 memcpy(&gids[i].gid, 366 &port_gid_table->gids[i].gid, 367 sizeof(union ib_gid)); 368 gids[i].gid_type = 369 port_gid_table->gids[i].gid_type; 370 } 371 } 372 } 373 spin_unlock_bh(&iboe->lock); 374 375 if (!ret && hw_update) { 376 ret = mlx4_ib_update_gids(gids, ibdev, attr->port_num); 377 kfree(gids); 378 } 379 return ret; 380 } 381 382 int mlx4_ib_gid_index_to_real_index(struct mlx4_ib_dev *ibdev, 383 const struct ib_gid_attr *attr) 384 { 385 struct mlx4_ib_iboe *iboe = &ibdev->iboe; 386 struct gid_cache_context *ctx = NULL; 387 struct mlx4_port_gid_table *port_gid_table; 388 int real_index = -EINVAL; 389 int i; 390 unsigned long flags; 391 u8 port_num = attr->port_num; 392 393 if (port_num > MLX4_MAX_PORTS) 394 return -EINVAL; 395 396 if (mlx4_is_bonded(ibdev->dev)) 397 port_num = 1; 398 399 if (!rdma_cap_roce_gid_table(&ibdev->ib_dev, port_num)) 400 return attr->index; 401 402 spin_lock_irqsave(&iboe->lock, flags); 403 port_gid_table = &iboe->gids[port_num - 1]; 404 405 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) 406 if (!memcmp(&port_gid_table->gids[i].gid, 407 &attr->gid, sizeof(attr->gid)) && 408 attr->gid_type == port_gid_table->gids[i].gid_type) { 409 ctx = port_gid_table->gids[i].ctx; 410 break; 411 } 412 if (ctx) 413 real_index = ctx->real_index; 414 spin_unlock_irqrestore(&iboe->lock, flags); 415 return real_index; 416 } 417 418 #define field_avail(type, fld, sz) (offsetof(type, fld) + \ 419 sizeof(((type *)0)->fld) <= (sz)) 420 421 static int mlx4_ib_query_device(struct ib_device *ibdev, 422 struct ib_device_attr *props, 423 struct ib_udata *uhw) 424 { 425 struct mlx4_ib_dev *dev = to_mdev(ibdev); 426 struct ib_smp *in_mad = NULL; 427 struct ib_smp *out_mad = NULL; 428 int err; 429 int have_ib_ports; 430 struct mlx4_uverbs_ex_query_device cmd; 431 struct mlx4_uverbs_ex_query_device_resp resp = {.comp_mask = 0}; 432 struct mlx4_clock_params clock_params; 433 434 if (uhw->inlen) { 435 if (uhw->inlen < sizeof(cmd)) 436 return -EINVAL; 437 438 err = ib_copy_from_udata(&cmd, uhw, sizeof(cmd)); 439 if (err) 440 return err; 441 442 if (cmd.comp_mask) 443 return -EINVAL; 444 445 if (cmd.reserved) 446 return -EINVAL; 447 } 448 449 resp.response_length = offsetof(typeof(resp), response_length) + 450 sizeof(resp.response_length); 451 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); 452 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 453 err = -ENOMEM; 454 if (!in_mad || !out_mad) 455 goto out; 456 457 init_query_mad(in_mad); 458 in_mad->attr_id = IB_SMP_ATTR_NODE_INFO; 459 460 err = mlx4_MAD_IFC(to_mdev(ibdev), MLX4_MAD_IFC_IGNORE_KEYS, 461 1, NULL, NULL, in_mad, out_mad); 462 if (err) 463 goto out; 464 465 memset(props, 0, sizeof *props); 466 467 have_ib_ports = num_ib_ports(dev->dev); 468 469 props->fw_ver = dev->dev->caps.fw_ver; 470 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 471 IB_DEVICE_PORT_ACTIVE_EVENT | 472 IB_DEVICE_SYS_IMAGE_GUID | 473 IB_DEVICE_RC_RNR_NAK_GEN | 474 IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 475 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR) 476 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 477 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR) 478 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 479 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_APM && have_ib_ports) 480 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 481 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UD_AV_PORT) 482 props->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE; 483 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM) 484 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 485 if (dev->dev->caps.max_gso_sz && 486 (dev->dev->rev_id != MLX4_IB_CARD_REV_A0) && 487 (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BLH)) 488 props->device_cap_flags |= IB_DEVICE_UD_TSO; 489 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_RESERVED_LKEY) 490 props->device_cap_flags |= IB_DEVICE_LOCAL_DMA_LKEY; 491 if ((dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_LOCAL_INV) && 492 (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_REMOTE_INV) && 493 (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_FAST_REG_WR)) 494 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 495 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) 496 props->device_cap_flags |= IB_DEVICE_XRC; 497 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW) 498 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW; 499 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) { 500 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_WIN_TYPE_2B) 501 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2B; 502 else 503 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2A; 504 } 505 if (dev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED) 506 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 507 508 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 509 510 props->vendor_id = be32_to_cpup((__be32 *) (out_mad->data + 36)) & 511 0xffffff; 512 props->vendor_part_id = dev->dev->persist->pdev->device; 513 props->hw_ver = be32_to_cpup((__be32 *) (out_mad->data + 32)); 514 memcpy(&props->sys_image_guid, out_mad->data + 4, 8); 515 516 props->max_mr_size = ~0ull; 517 props->page_size_cap = dev->dev->caps.page_size_cap; 518 props->max_qp = dev->dev->quotas.qp; 519 props->max_qp_wr = dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE; 520 props->max_send_sge = dev->dev->caps.max_sq_sg; 521 props->max_recv_sge = dev->dev->caps.max_rq_sg; 522 props->max_sge_rd = MLX4_MAX_SGE_RD; 523 props->max_cq = dev->dev->quotas.cq; 524 props->max_cqe = dev->dev->caps.max_cqes; 525 props->max_mr = dev->dev->quotas.mpt; 526 props->max_pd = dev->dev->caps.num_pds - dev->dev->caps.reserved_pds; 527 props->max_qp_rd_atom = dev->dev->caps.max_qp_dest_rdma; 528 props->max_qp_init_rd_atom = dev->dev->caps.max_qp_init_rdma; 529 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 530 props->max_srq = dev->dev->quotas.srq; 531 props->max_srq_wr = dev->dev->caps.max_srq_wqes - 1; 532 props->max_srq_sge = dev->dev->caps.max_srq_sge; 533 props->max_fast_reg_page_list_len = MLX4_MAX_FAST_REG_PAGES; 534 props->local_ca_ack_delay = dev->dev->caps.local_ca_ack_delay; 535 props->atomic_cap = dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_ATOMIC ? 536 IB_ATOMIC_HCA : IB_ATOMIC_NONE; 537 props->masked_atomic_cap = props->atomic_cap; 538 props->max_pkeys = dev->dev->caps.pkey_table_len[1]; 539 props->max_mcast_grp = dev->dev->caps.num_mgms + dev->dev->caps.num_amgms; 540 props->max_mcast_qp_attach = dev->dev->caps.num_qp_per_mgm; 541 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 542 props->max_mcast_grp; 543 props->max_map_per_fmr = dev->dev->caps.max_fmr_maps; 544 props->hca_core_clock = dev->dev->caps.hca_core_clock * 1000UL; 545 props->timestamp_mask = 0xFFFFFFFFFFFFULL; 546 props->max_ah = INT_MAX; 547 548 if (mlx4_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET || 549 mlx4_ib_port_link_layer(ibdev, 2) == IB_LINK_LAYER_ETHERNET) { 550 if (dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS) { 551 props->rss_caps.max_rwq_indirection_tables = 552 props->max_qp; 553 props->rss_caps.max_rwq_indirection_table_size = 554 dev->dev->caps.max_rss_tbl_sz; 555 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 556 props->max_wq_type_rq = props->max_qp; 557 } 558 559 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) 560 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; 561 } 562 563 props->cq_caps.max_cq_moderation_count = MLX4_MAX_CQ_COUNT; 564 props->cq_caps.max_cq_moderation_period = MLX4_MAX_CQ_PERIOD; 565 566 if (!mlx4_is_slave(dev->dev)) 567 err = mlx4_get_internal_clock_params(dev->dev, &clock_params); 568 569 if (uhw->outlen >= resp.response_length + sizeof(resp.hca_core_clock_offset)) { 570 resp.response_length += sizeof(resp.hca_core_clock_offset); 571 if (!err && !mlx4_is_slave(dev->dev)) { 572 resp.comp_mask |= MLX4_IB_QUERY_DEV_RESP_MASK_CORE_CLOCK_OFFSET; 573 resp.hca_core_clock_offset = clock_params.offset % PAGE_SIZE; 574 } 575 } 576 577 if (uhw->outlen >= resp.response_length + 578 sizeof(resp.max_inl_recv_sz)) { 579 resp.response_length += sizeof(resp.max_inl_recv_sz); 580 resp.max_inl_recv_sz = dev->dev->caps.max_rq_sg * 581 sizeof(struct mlx4_wqe_data_seg); 582 } 583 584 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) { 585 if (props->rss_caps.supported_qpts) { 586 resp.rss_caps.rx_hash_function = 587 MLX4_IB_RX_HASH_FUNC_TOEPLITZ; 588 589 resp.rss_caps.rx_hash_fields_mask = 590 MLX4_IB_RX_HASH_SRC_IPV4 | 591 MLX4_IB_RX_HASH_DST_IPV4 | 592 MLX4_IB_RX_HASH_SRC_IPV6 | 593 MLX4_IB_RX_HASH_DST_IPV6 | 594 MLX4_IB_RX_HASH_SRC_PORT_TCP | 595 MLX4_IB_RX_HASH_DST_PORT_TCP | 596 MLX4_IB_RX_HASH_SRC_PORT_UDP | 597 MLX4_IB_RX_HASH_DST_PORT_UDP; 598 599 if (dev->dev->caps.tunnel_offload_mode == 600 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) 601 resp.rss_caps.rx_hash_fields_mask |= 602 MLX4_IB_RX_HASH_INNER; 603 } 604 resp.response_length = offsetof(typeof(resp), rss_caps) + 605 sizeof(resp.rss_caps); 606 } 607 608 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) { 609 if (dev->dev->caps.max_gso_sz && 610 ((mlx4_ib_port_link_layer(ibdev, 1) == 611 IB_LINK_LAYER_ETHERNET) || 612 (mlx4_ib_port_link_layer(ibdev, 2) == 613 IB_LINK_LAYER_ETHERNET))) { 614 resp.tso_caps.max_tso = dev->dev->caps.max_gso_sz; 615 resp.tso_caps.supported_qpts |= 616 1 << IB_QPT_RAW_PACKET; 617 } 618 resp.response_length = offsetof(typeof(resp), tso_caps) + 619 sizeof(resp.tso_caps); 620 } 621 622 if (uhw->outlen) { 623 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 624 if (err) 625 goto out; 626 } 627 out: 628 kfree(in_mad); 629 kfree(out_mad); 630 631 return err; 632 } 633 634 static enum rdma_link_layer 635 mlx4_ib_port_link_layer(struct ib_device *device, u8 port_num) 636 { 637 struct mlx4_dev *dev = to_mdev(device)->dev; 638 639 return dev->caps.port_mask[port_num] == MLX4_PORT_TYPE_IB ? 640 IB_LINK_LAYER_INFINIBAND : IB_LINK_LAYER_ETHERNET; 641 } 642 643 static int ib_link_query_port(struct ib_device *ibdev, u8 port, 644 struct ib_port_attr *props, int netw_view) 645 { 646 struct ib_smp *in_mad = NULL; 647 struct ib_smp *out_mad = NULL; 648 int ext_active_speed; 649 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; 650 int err = -ENOMEM; 651 652 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); 653 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 654 if (!in_mad || !out_mad) 655 goto out; 656 657 init_query_mad(in_mad); 658 in_mad->attr_id = IB_SMP_ATTR_PORT_INFO; 659 in_mad->attr_mod = cpu_to_be32(port); 660 661 if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view) 662 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; 663 664 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL, 665 in_mad, out_mad); 666 if (err) 667 goto out; 668 669 670 props->lid = be16_to_cpup((__be16 *) (out_mad->data + 16)); 671 props->lmc = out_mad->data[34] & 0x7; 672 props->sm_lid = be16_to_cpup((__be16 *) (out_mad->data + 18)); 673 props->sm_sl = out_mad->data[36] & 0xf; 674 props->state = out_mad->data[32] & 0xf; 675 props->phys_state = out_mad->data[33] >> 4; 676 props->port_cap_flags = be32_to_cpup((__be32 *) (out_mad->data + 20)); 677 if (netw_view) 678 props->gid_tbl_len = out_mad->data[50]; 679 else 680 props->gid_tbl_len = to_mdev(ibdev)->dev->caps.gid_table_len[port]; 681 props->max_msg_sz = to_mdev(ibdev)->dev->caps.max_msg_sz; 682 props->pkey_tbl_len = to_mdev(ibdev)->dev->caps.pkey_table_len[port]; 683 props->bad_pkey_cntr = be16_to_cpup((__be16 *) (out_mad->data + 46)); 684 props->qkey_viol_cntr = be16_to_cpup((__be16 *) (out_mad->data + 48)); 685 props->active_width = out_mad->data[31] & 0xf; 686 props->active_speed = out_mad->data[35] >> 4; 687 props->max_mtu = out_mad->data[41] & 0xf; 688 props->active_mtu = out_mad->data[36] >> 4; 689 props->subnet_timeout = out_mad->data[51] & 0x1f; 690 props->max_vl_num = out_mad->data[37] >> 4; 691 props->init_type_reply = out_mad->data[41] >> 4; 692 693 /* Check if extended speeds (EDR/FDR/...) are supported */ 694 if (props->port_cap_flags & IB_PORT_EXTENDED_SPEEDS_SUP) { 695 ext_active_speed = out_mad->data[62] >> 4; 696 697 switch (ext_active_speed) { 698 case 1: 699 props->active_speed = IB_SPEED_FDR; 700 break; 701 case 2: 702 props->active_speed = IB_SPEED_EDR; 703 break; 704 } 705 } 706 707 /* If reported active speed is QDR, check if is FDR-10 */ 708 if (props->active_speed == IB_SPEED_QDR) { 709 init_query_mad(in_mad); 710 in_mad->attr_id = MLX4_ATTR_EXTENDED_PORT_INFO; 711 in_mad->attr_mod = cpu_to_be32(port); 712 713 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, 714 NULL, NULL, in_mad, out_mad); 715 if (err) 716 goto out; 717 718 /* Checking LinkSpeedActive for FDR-10 */ 719 if (out_mad->data[15] & 0x1) 720 props->active_speed = IB_SPEED_FDR10; 721 } 722 723 /* Avoid wrong speed value returned by FW if the IB link is down. */ 724 if (props->state == IB_PORT_DOWN) 725 props->active_speed = IB_SPEED_SDR; 726 727 out: 728 kfree(in_mad); 729 kfree(out_mad); 730 return err; 731 } 732 733 static u8 state_to_phys_state(enum ib_port_state state) 734 { 735 return state == IB_PORT_ACTIVE ? 5 : 3; 736 } 737 738 static int eth_link_query_port(struct ib_device *ibdev, u8 port, 739 struct ib_port_attr *props) 740 { 741 742 struct mlx4_ib_dev *mdev = to_mdev(ibdev); 743 struct mlx4_ib_iboe *iboe = &mdev->iboe; 744 struct net_device *ndev; 745 enum ib_mtu tmp; 746 struct mlx4_cmd_mailbox *mailbox; 747 int err = 0; 748 int is_bonded = mlx4_is_bonded(mdev->dev); 749 750 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev); 751 if (IS_ERR(mailbox)) 752 return PTR_ERR(mailbox); 753 754 err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, port, 0, 755 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, 756 MLX4_CMD_WRAPPED); 757 if (err) 758 goto out; 759 760 props->active_width = (((u8 *)mailbox->buf)[5] == 0x40) || 761 (((u8 *)mailbox->buf)[5] == 0x20 /*56Gb*/) ? 762 IB_WIDTH_4X : IB_WIDTH_1X; 763 props->active_speed = (((u8 *)mailbox->buf)[5] == 0x20 /*56Gb*/) ? 764 IB_SPEED_FDR : IB_SPEED_QDR; 765 props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_IP_BASED_GIDS; 766 props->gid_tbl_len = mdev->dev->caps.gid_table_len[port]; 767 props->max_msg_sz = mdev->dev->caps.max_msg_sz; 768 props->pkey_tbl_len = 1; 769 props->max_mtu = IB_MTU_4096; 770 props->max_vl_num = 2; 771 props->state = IB_PORT_DOWN; 772 props->phys_state = state_to_phys_state(props->state); 773 props->active_mtu = IB_MTU_256; 774 spin_lock_bh(&iboe->lock); 775 ndev = iboe->netdevs[port - 1]; 776 if (ndev && is_bonded) { 777 rcu_read_lock(); /* required to get upper dev */ 778 ndev = netdev_master_upper_dev_get_rcu(ndev); 779 rcu_read_unlock(); 780 } 781 if (!ndev) 782 goto out_unlock; 783 784 tmp = iboe_get_mtu(ndev->mtu); 785 props->active_mtu = tmp ? min(props->max_mtu, tmp) : IB_MTU_256; 786 787 props->state = (netif_running(ndev) && netif_carrier_ok(ndev)) ? 788 IB_PORT_ACTIVE : IB_PORT_DOWN; 789 props->phys_state = state_to_phys_state(props->state); 790 out_unlock: 791 spin_unlock_bh(&iboe->lock); 792 out: 793 mlx4_free_cmd_mailbox(mdev->dev, mailbox); 794 return err; 795 } 796 797 int __mlx4_ib_query_port(struct ib_device *ibdev, u8 port, 798 struct ib_port_attr *props, int netw_view) 799 { 800 int err; 801 802 /* props being zeroed by the caller, avoid zeroing it here */ 803 804 err = mlx4_ib_port_link_layer(ibdev, port) == IB_LINK_LAYER_INFINIBAND ? 805 ib_link_query_port(ibdev, port, props, netw_view) : 806 eth_link_query_port(ibdev, port, props); 807 808 return err; 809 } 810 811 static int mlx4_ib_query_port(struct ib_device *ibdev, u8 port, 812 struct ib_port_attr *props) 813 { 814 /* returns host view */ 815 return __mlx4_ib_query_port(ibdev, port, props, 0); 816 } 817 818 int __mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 819 union ib_gid *gid, int netw_view) 820 { 821 struct ib_smp *in_mad = NULL; 822 struct ib_smp *out_mad = NULL; 823 int err = -ENOMEM; 824 struct mlx4_ib_dev *dev = to_mdev(ibdev); 825 int clear = 0; 826 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; 827 828 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); 829 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 830 if (!in_mad || !out_mad) 831 goto out; 832 833 init_query_mad(in_mad); 834 in_mad->attr_id = IB_SMP_ATTR_PORT_INFO; 835 in_mad->attr_mod = cpu_to_be32(port); 836 837 if (mlx4_is_mfunc(dev->dev) && netw_view) 838 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; 839 840 err = mlx4_MAD_IFC(dev, mad_ifc_flags, port, NULL, NULL, in_mad, out_mad); 841 if (err) 842 goto out; 843 844 memcpy(gid->raw, out_mad->data + 8, 8); 845 846 if (mlx4_is_mfunc(dev->dev) && !netw_view) { 847 if (index) { 848 /* For any index > 0, return the null guid */ 849 err = 0; 850 clear = 1; 851 goto out; 852 } 853 } 854 855 init_query_mad(in_mad); 856 in_mad->attr_id = IB_SMP_ATTR_GUID_INFO; 857 in_mad->attr_mod = cpu_to_be32(index / 8); 858 859 err = mlx4_MAD_IFC(dev, mad_ifc_flags, port, 860 NULL, NULL, in_mad, out_mad); 861 if (err) 862 goto out; 863 864 memcpy(gid->raw + 8, out_mad->data + (index % 8) * 8, 8); 865 866 out: 867 if (clear) 868 memset(gid->raw + 8, 0, 8); 869 kfree(in_mad); 870 kfree(out_mad); 871 return err; 872 } 873 874 static int mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 875 union ib_gid *gid) 876 { 877 if (rdma_protocol_ib(ibdev, port)) 878 return __mlx4_ib_query_gid(ibdev, port, index, gid, 0); 879 return 0; 880 } 881 882 static int mlx4_ib_query_sl2vl(struct ib_device *ibdev, u8 port, u64 *sl2vl_tbl) 883 { 884 union sl2vl_tbl_to_u64 sl2vl64; 885 struct ib_smp *in_mad = NULL; 886 struct ib_smp *out_mad = NULL; 887 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; 888 int err = -ENOMEM; 889 int jj; 890 891 if (mlx4_is_slave(to_mdev(ibdev)->dev)) { 892 *sl2vl_tbl = 0; 893 return 0; 894 } 895 896 in_mad = kzalloc(sizeof(*in_mad), GFP_KERNEL); 897 out_mad = kmalloc(sizeof(*out_mad), GFP_KERNEL); 898 if (!in_mad || !out_mad) 899 goto out; 900 901 init_query_mad(in_mad); 902 in_mad->attr_id = IB_SMP_ATTR_SL_TO_VL_TABLE; 903 in_mad->attr_mod = 0; 904 905 if (mlx4_is_mfunc(to_mdev(ibdev)->dev)) 906 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; 907 908 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL, 909 in_mad, out_mad); 910 if (err) 911 goto out; 912 913 for (jj = 0; jj < 8; jj++) 914 sl2vl64.sl8[jj] = ((struct ib_smp *)out_mad)->data[jj]; 915 *sl2vl_tbl = sl2vl64.sl64; 916 917 out: 918 kfree(in_mad); 919 kfree(out_mad); 920 return err; 921 } 922 923 static void mlx4_init_sl2vl_tbl(struct mlx4_ib_dev *mdev) 924 { 925 u64 sl2vl; 926 int i; 927 int err; 928 929 for (i = 1; i <= mdev->dev->caps.num_ports; i++) { 930 if (mdev->dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH) 931 continue; 932 err = mlx4_ib_query_sl2vl(&mdev->ib_dev, i, &sl2vl); 933 if (err) { 934 pr_err("Unable to get default sl to vl mapping for port %d. Using all zeroes (%d)\n", 935 i, err); 936 sl2vl = 0; 937 } 938 atomic64_set(&mdev->sl2vl[i - 1], sl2vl); 939 } 940 } 941 942 int __mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 943 u16 *pkey, int netw_view) 944 { 945 struct ib_smp *in_mad = NULL; 946 struct ib_smp *out_mad = NULL; 947 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; 948 int err = -ENOMEM; 949 950 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); 951 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 952 if (!in_mad || !out_mad) 953 goto out; 954 955 init_query_mad(in_mad); 956 in_mad->attr_id = IB_SMP_ATTR_PKEY_TABLE; 957 in_mad->attr_mod = cpu_to_be32(index / 32); 958 959 if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view) 960 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; 961 962 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL, 963 in_mad, out_mad); 964 if (err) 965 goto out; 966 967 *pkey = be16_to_cpu(((__be16 *) out_mad->data)[index % 32]); 968 969 out: 970 kfree(in_mad); 971 kfree(out_mad); 972 return err; 973 } 974 975 static int mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, u16 *pkey) 976 { 977 return __mlx4_ib_query_pkey(ibdev, port, index, pkey, 0); 978 } 979 980 static int mlx4_ib_modify_device(struct ib_device *ibdev, int mask, 981 struct ib_device_modify *props) 982 { 983 struct mlx4_cmd_mailbox *mailbox; 984 unsigned long flags; 985 986 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 987 return -EOPNOTSUPP; 988 989 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 990 return 0; 991 992 if (mlx4_is_slave(to_mdev(ibdev)->dev)) 993 return -EOPNOTSUPP; 994 995 spin_lock_irqsave(&to_mdev(ibdev)->sm_lock, flags); 996 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 997 spin_unlock_irqrestore(&to_mdev(ibdev)->sm_lock, flags); 998 999 /* 1000 * If possible, pass node desc to FW, so it can generate 1001 * a 144 trap. If cmd fails, just ignore. 1002 */ 1003 mailbox = mlx4_alloc_cmd_mailbox(to_mdev(ibdev)->dev); 1004 if (IS_ERR(mailbox)) 1005 return 0; 1006 1007 memcpy(mailbox->buf, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1008 mlx4_cmd(to_mdev(ibdev)->dev, mailbox->dma, 1, 0, 1009 MLX4_CMD_SET_NODE, MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1010 1011 mlx4_free_cmd_mailbox(to_mdev(ibdev)->dev, mailbox); 1012 1013 return 0; 1014 } 1015 1016 static int mlx4_ib_SET_PORT(struct mlx4_ib_dev *dev, u8 port, int reset_qkey_viols, 1017 u32 cap_mask) 1018 { 1019 struct mlx4_cmd_mailbox *mailbox; 1020 int err; 1021 1022 mailbox = mlx4_alloc_cmd_mailbox(dev->dev); 1023 if (IS_ERR(mailbox)) 1024 return PTR_ERR(mailbox); 1025 1026 if (dev->dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { 1027 *(u8 *) mailbox->buf = !!reset_qkey_viols << 6; 1028 ((__be32 *) mailbox->buf)[2] = cpu_to_be32(cap_mask); 1029 } else { 1030 ((u8 *) mailbox->buf)[3] = !!reset_qkey_viols; 1031 ((__be32 *) mailbox->buf)[1] = cpu_to_be32(cap_mask); 1032 } 1033 1034 err = mlx4_cmd(dev->dev, mailbox->dma, port, MLX4_SET_PORT_IB_OPCODE, 1035 MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 1036 MLX4_CMD_WRAPPED); 1037 1038 mlx4_free_cmd_mailbox(dev->dev, mailbox); 1039 return err; 1040 } 1041 1042 static int mlx4_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, 1043 struct ib_port_modify *props) 1044 { 1045 struct mlx4_ib_dev *mdev = to_mdev(ibdev); 1046 u8 is_eth = mdev->dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH; 1047 struct ib_port_attr attr; 1048 u32 cap_mask; 1049 int err; 1050 1051 /* return OK if this is RoCE. CM calls ib_modify_port() regardless 1052 * of whether port link layer is ETH or IB. For ETH ports, qkey 1053 * violations and port capabilities are not meaningful. 1054 */ 1055 if (is_eth) 1056 return 0; 1057 1058 mutex_lock(&mdev->cap_mask_mutex); 1059 1060 err = ib_query_port(ibdev, port, &attr); 1061 if (err) 1062 goto out; 1063 1064 cap_mask = (attr.port_cap_flags | props->set_port_cap_mask) & 1065 ~props->clr_port_cap_mask; 1066 1067 err = mlx4_ib_SET_PORT(mdev, port, 1068 !!(mask & IB_PORT_RESET_QKEY_CNTR), 1069 cap_mask); 1070 1071 out: 1072 mutex_unlock(&to_mdev(ibdev)->cap_mask_mutex); 1073 return err; 1074 } 1075 1076 static struct ib_ucontext *mlx4_ib_alloc_ucontext(struct ib_device *ibdev, 1077 struct ib_udata *udata) 1078 { 1079 struct mlx4_ib_dev *dev = to_mdev(ibdev); 1080 struct mlx4_ib_ucontext *context; 1081 struct mlx4_ib_alloc_ucontext_resp_v3 resp_v3; 1082 struct mlx4_ib_alloc_ucontext_resp resp; 1083 int err; 1084 1085 if (!dev->ib_active) 1086 return ERR_PTR(-EAGAIN); 1087 1088 if (ibdev->uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION) { 1089 resp_v3.qp_tab_size = dev->dev->caps.num_qps; 1090 resp_v3.bf_reg_size = dev->dev->caps.bf_reg_size; 1091 resp_v3.bf_regs_per_page = dev->dev->caps.bf_regs_per_page; 1092 } else { 1093 resp.dev_caps = dev->dev->caps.userspace_caps; 1094 resp.qp_tab_size = dev->dev->caps.num_qps; 1095 resp.bf_reg_size = dev->dev->caps.bf_reg_size; 1096 resp.bf_regs_per_page = dev->dev->caps.bf_regs_per_page; 1097 resp.cqe_size = dev->dev->caps.cqe_size; 1098 } 1099 1100 context = kzalloc(sizeof(*context), GFP_KERNEL); 1101 if (!context) 1102 return ERR_PTR(-ENOMEM); 1103 1104 err = mlx4_uar_alloc(to_mdev(ibdev)->dev, &context->uar); 1105 if (err) { 1106 kfree(context); 1107 return ERR_PTR(err); 1108 } 1109 1110 INIT_LIST_HEAD(&context->db_page_list); 1111 mutex_init(&context->db_page_mutex); 1112 1113 INIT_LIST_HEAD(&context->wqn_ranges_list); 1114 mutex_init(&context->wqn_ranges_mutex); 1115 1116 if (ibdev->uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION) 1117 err = ib_copy_to_udata(udata, &resp_v3, sizeof(resp_v3)); 1118 else 1119 err = ib_copy_to_udata(udata, &resp, sizeof(resp)); 1120 1121 if (err) { 1122 mlx4_uar_free(to_mdev(ibdev)->dev, &context->uar); 1123 kfree(context); 1124 return ERR_PTR(-EFAULT); 1125 } 1126 1127 return &context->ibucontext; 1128 } 1129 1130 static int mlx4_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1131 { 1132 struct mlx4_ib_ucontext *context = to_mucontext(ibcontext); 1133 1134 mlx4_uar_free(to_mdev(ibcontext->device)->dev, &context->uar); 1135 kfree(context); 1136 1137 return 0; 1138 } 1139 1140 static void mlx4_ib_vma_open(struct vm_area_struct *area) 1141 { 1142 /* vma_open is called when a new VMA is created on top of our VMA. 1143 * This is done through either mremap flow or split_vma (usually due 1144 * to mlock, madvise, munmap, etc.). We do not support a clone of the 1145 * vma, as this VMA is strongly hardware related. Therefore we set the 1146 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from 1147 * calling us again and trying to do incorrect actions. We assume that 1148 * the original vma size is exactly a single page that there will be no 1149 * "splitting" operations on. 1150 */ 1151 area->vm_ops = NULL; 1152 } 1153 1154 static void mlx4_ib_vma_close(struct vm_area_struct *area) 1155 { 1156 struct mlx4_ib_vma_private_data *mlx4_ib_vma_priv_data; 1157 1158 /* It's guaranteed that all VMAs opened on a FD are closed before the 1159 * file itself is closed, therefore no sync is needed with the regular 1160 * closing flow. (e.g. mlx4_ib_dealloc_ucontext) However need a sync 1161 * with accessing the vma as part of mlx4_ib_disassociate_ucontext. 1162 * The close operation is usually called under mm->mmap_sem except when 1163 * process is exiting. The exiting case is handled explicitly as part 1164 * of mlx4_ib_disassociate_ucontext. 1165 */ 1166 mlx4_ib_vma_priv_data = (struct mlx4_ib_vma_private_data *) 1167 area->vm_private_data; 1168 1169 /* set the vma context pointer to null in the mlx4_ib driver's private 1170 * data to protect against a race condition in mlx4_ib_dissassociate_ucontext(). 1171 */ 1172 mlx4_ib_vma_priv_data->vma = NULL; 1173 } 1174 1175 static const struct vm_operations_struct mlx4_ib_vm_ops = { 1176 .open = mlx4_ib_vma_open, 1177 .close = mlx4_ib_vma_close 1178 }; 1179 1180 static void mlx4_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 1181 { 1182 int i; 1183 struct vm_area_struct *vma; 1184 struct mlx4_ib_ucontext *context = to_mucontext(ibcontext); 1185 1186 /* need to protect from a race on closing the vma as part of 1187 * mlx4_ib_vma_close(). 1188 */ 1189 for (i = 0; i < HW_BAR_COUNT; i++) { 1190 vma = context->hw_bar_info[i].vma; 1191 if (!vma) 1192 continue; 1193 1194 zap_vma_ptes(context->hw_bar_info[i].vma, 1195 context->hw_bar_info[i].vma->vm_start, PAGE_SIZE); 1196 1197 context->hw_bar_info[i].vma->vm_flags &= 1198 ~(VM_SHARED | VM_MAYSHARE); 1199 /* context going to be destroyed, should not access ops any more */ 1200 context->hw_bar_info[i].vma->vm_ops = NULL; 1201 } 1202 } 1203 1204 static void mlx4_ib_set_vma_data(struct vm_area_struct *vma, 1205 struct mlx4_ib_vma_private_data *vma_private_data) 1206 { 1207 vma_private_data->vma = vma; 1208 vma->vm_private_data = vma_private_data; 1209 vma->vm_ops = &mlx4_ib_vm_ops; 1210 } 1211 1212 static int mlx4_ib_mmap(struct ib_ucontext *context, struct vm_area_struct *vma) 1213 { 1214 struct mlx4_ib_dev *dev = to_mdev(context->device); 1215 struct mlx4_ib_ucontext *mucontext = to_mucontext(context); 1216 1217 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1218 return -EINVAL; 1219 1220 if (vma->vm_pgoff == 0) { 1221 /* We prevent double mmaping on same context */ 1222 if (mucontext->hw_bar_info[HW_BAR_DB].vma) 1223 return -EINVAL; 1224 1225 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 1226 1227 if (io_remap_pfn_range(vma, vma->vm_start, 1228 to_mucontext(context)->uar.pfn, 1229 PAGE_SIZE, vma->vm_page_prot)) 1230 return -EAGAIN; 1231 1232 mlx4_ib_set_vma_data(vma, &mucontext->hw_bar_info[HW_BAR_DB]); 1233 1234 } else if (vma->vm_pgoff == 1 && dev->dev->caps.bf_reg_size != 0) { 1235 /* We prevent double mmaping on same context */ 1236 if (mucontext->hw_bar_info[HW_BAR_BF].vma) 1237 return -EINVAL; 1238 1239 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); 1240 1241 if (io_remap_pfn_range(vma, vma->vm_start, 1242 to_mucontext(context)->uar.pfn + 1243 dev->dev->caps.num_uars, 1244 PAGE_SIZE, vma->vm_page_prot)) 1245 return -EAGAIN; 1246 1247 mlx4_ib_set_vma_data(vma, &mucontext->hw_bar_info[HW_BAR_BF]); 1248 1249 } else if (vma->vm_pgoff == 3) { 1250 struct mlx4_clock_params params; 1251 int ret; 1252 1253 /* We prevent double mmaping on same context */ 1254 if (mucontext->hw_bar_info[HW_BAR_CLOCK].vma) 1255 return -EINVAL; 1256 1257 ret = mlx4_get_internal_clock_params(dev->dev, ¶ms); 1258 1259 if (ret) 1260 return ret; 1261 1262 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 1263 if (io_remap_pfn_range(vma, vma->vm_start, 1264 (pci_resource_start(dev->dev->persist->pdev, 1265 params.bar) + 1266 params.offset) 1267 >> PAGE_SHIFT, 1268 PAGE_SIZE, vma->vm_page_prot)) 1269 return -EAGAIN; 1270 1271 mlx4_ib_set_vma_data(vma, 1272 &mucontext->hw_bar_info[HW_BAR_CLOCK]); 1273 } else { 1274 return -EINVAL; 1275 } 1276 1277 return 0; 1278 } 1279 1280 static struct ib_pd *mlx4_ib_alloc_pd(struct ib_device *ibdev, 1281 struct ib_ucontext *context, 1282 struct ib_udata *udata) 1283 { 1284 struct mlx4_ib_pd *pd; 1285 int err; 1286 1287 pd = kzalloc(sizeof(*pd), GFP_KERNEL); 1288 if (!pd) 1289 return ERR_PTR(-ENOMEM); 1290 1291 err = mlx4_pd_alloc(to_mdev(ibdev)->dev, &pd->pdn); 1292 if (err) { 1293 kfree(pd); 1294 return ERR_PTR(err); 1295 } 1296 1297 if (context) 1298 if (ib_copy_to_udata(udata, &pd->pdn, sizeof (__u32))) { 1299 mlx4_pd_free(to_mdev(ibdev)->dev, pd->pdn); 1300 kfree(pd); 1301 return ERR_PTR(-EFAULT); 1302 } 1303 return &pd->ibpd; 1304 } 1305 1306 static int mlx4_ib_dealloc_pd(struct ib_pd *pd) 1307 { 1308 mlx4_pd_free(to_mdev(pd->device)->dev, to_mpd(pd)->pdn); 1309 kfree(pd); 1310 1311 return 0; 1312 } 1313 1314 static struct ib_xrcd *mlx4_ib_alloc_xrcd(struct ib_device *ibdev, 1315 struct ib_ucontext *context, 1316 struct ib_udata *udata) 1317 { 1318 struct mlx4_ib_xrcd *xrcd; 1319 struct ib_cq_init_attr cq_attr = {}; 1320 int err; 1321 1322 if (!(to_mdev(ibdev)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC)) 1323 return ERR_PTR(-ENOSYS); 1324 1325 xrcd = kmalloc(sizeof *xrcd, GFP_KERNEL); 1326 if (!xrcd) 1327 return ERR_PTR(-ENOMEM); 1328 1329 err = mlx4_xrcd_alloc(to_mdev(ibdev)->dev, &xrcd->xrcdn); 1330 if (err) 1331 goto err1; 1332 1333 xrcd->pd = ib_alloc_pd(ibdev, 0); 1334 if (IS_ERR(xrcd->pd)) { 1335 err = PTR_ERR(xrcd->pd); 1336 goto err2; 1337 } 1338 1339 cq_attr.cqe = 1; 1340 xrcd->cq = ib_create_cq(ibdev, NULL, NULL, xrcd, &cq_attr); 1341 if (IS_ERR(xrcd->cq)) { 1342 err = PTR_ERR(xrcd->cq); 1343 goto err3; 1344 } 1345 1346 return &xrcd->ibxrcd; 1347 1348 err3: 1349 ib_dealloc_pd(xrcd->pd); 1350 err2: 1351 mlx4_xrcd_free(to_mdev(ibdev)->dev, xrcd->xrcdn); 1352 err1: 1353 kfree(xrcd); 1354 return ERR_PTR(err); 1355 } 1356 1357 static int mlx4_ib_dealloc_xrcd(struct ib_xrcd *xrcd) 1358 { 1359 ib_destroy_cq(to_mxrcd(xrcd)->cq); 1360 ib_dealloc_pd(to_mxrcd(xrcd)->pd); 1361 mlx4_xrcd_free(to_mdev(xrcd->device)->dev, to_mxrcd(xrcd)->xrcdn); 1362 kfree(xrcd); 1363 1364 return 0; 1365 } 1366 1367 static int add_gid_entry(struct ib_qp *ibqp, union ib_gid *gid) 1368 { 1369 struct mlx4_ib_qp *mqp = to_mqp(ibqp); 1370 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); 1371 struct mlx4_ib_gid_entry *ge; 1372 1373 ge = kzalloc(sizeof *ge, GFP_KERNEL); 1374 if (!ge) 1375 return -ENOMEM; 1376 1377 ge->gid = *gid; 1378 if (mlx4_ib_add_mc(mdev, mqp, gid)) { 1379 ge->port = mqp->port; 1380 ge->added = 1; 1381 } 1382 1383 mutex_lock(&mqp->mutex); 1384 list_add_tail(&ge->list, &mqp->gid_list); 1385 mutex_unlock(&mqp->mutex); 1386 1387 return 0; 1388 } 1389 1390 static void mlx4_ib_delete_counters_table(struct mlx4_ib_dev *ibdev, 1391 struct mlx4_ib_counters *ctr_table) 1392 { 1393 struct counter_index *counter, *tmp_count; 1394 1395 mutex_lock(&ctr_table->mutex); 1396 list_for_each_entry_safe(counter, tmp_count, &ctr_table->counters_list, 1397 list) { 1398 if (counter->allocated) 1399 mlx4_counter_free(ibdev->dev, counter->index); 1400 list_del(&counter->list); 1401 kfree(counter); 1402 } 1403 mutex_unlock(&ctr_table->mutex); 1404 } 1405 1406 int mlx4_ib_add_mc(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp, 1407 union ib_gid *gid) 1408 { 1409 struct net_device *ndev; 1410 int ret = 0; 1411 1412 if (!mqp->port) 1413 return 0; 1414 1415 spin_lock_bh(&mdev->iboe.lock); 1416 ndev = mdev->iboe.netdevs[mqp->port - 1]; 1417 if (ndev) 1418 dev_hold(ndev); 1419 spin_unlock_bh(&mdev->iboe.lock); 1420 1421 if (ndev) { 1422 ret = 1; 1423 dev_put(ndev); 1424 } 1425 1426 return ret; 1427 } 1428 1429 struct mlx4_ib_steering { 1430 struct list_head list; 1431 struct mlx4_flow_reg_id reg_id; 1432 union ib_gid gid; 1433 }; 1434 1435 #define LAST_ETH_FIELD vlan_tag 1436 #define LAST_IB_FIELD sl 1437 #define LAST_IPV4_FIELD dst_ip 1438 #define LAST_TCP_UDP_FIELD src_port 1439 1440 /* Field is the last supported field */ 1441 #define FIELDS_NOT_SUPPORTED(filter, field)\ 1442 memchr_inv((void *)&filter.field +\ 1443 sizeof(filter.field), 0,\ 1444 sizeof(filter) -\ 1445 offsetof(typeof(filter), field) -\ 1446 sizeof(filter.field)) 1447 1448 static int parse_flow_attr(struct mlx4_dev *dev, 1449 u32 qp_num, 1450 union ib_flow_spec *ib_spec, 1451 struct _rule_hw *mlx4_spec) 1452 { 1453 enum mlx4_net_trans_rule_id type; 1454 1455 switch (ib_spec->type) { 1456 case IB_FLOW_SPEC_ETH: 1457 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD)) 1458 return -ENOTSUPP; 1459 1460 type = MLX4_NET_TRANS_RULE_ID_ETH; 1461 memcpy(mlx4_spec->eth.dst_mac, ib_spec->eth.val.dst_mac, 1462 ETH_ALEN); 1463 memcpy(mlx4_spec->eth.dst_mac_msk, ib_spec->eth.mask.dst_mac, 1464 ETH_ALEN); 1465 mlx4_spec->eth.vlan_tag = ib_spec->eth.val.vlan_tag; 1466 mlx4_spec->eth.vlan_tag_msk = ib_spec->eth.mask.vlan_tag; 1467 break; 1468 case IB_FLOW_SPEC_IB: 1469 if (FIELDS_NOT_SUPPORTED(ib_spec->ib.mask, LAST_IB_FIELD)) 1470 return -ENOTSUPP; 1471 1472 type = MLX4_NET_TRANS_RULE_ID_IB; 1473 mlx4_spec->ib.l3_qpn = 1474 cpu_to_be32(qp_num); 1475 mlx4_spec->ib.qpn_mask = 1476 cpu_to_be32(MLX4_IB_FLOW_QPN_MASK); 1477 break; 1478 1479 1480 case IB_FLOW_SPEC_IPV4: 1481 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD)) 1482 return -ENOTSUPP; 1483 1484 type = MLX4_NET_TRANS_RULE_ID_IPV4; 1485 mlx4_spec->ipv4.src_ip = ib_spec->ipv4.val.src_ip; 1486 mlx4_spec->ipv4.src_ip_msk = ib_spec->ipv4.mask.src_ip; 1487 mlx4_spec->ipv4.dst_ip = ib_spec->ipv4.val.dst_ip; 1488 mlx4_spec->ipv4.dst_ip_msk = ib_spec->ipv4.mask.dst_ip; 1489 break; 1490 1491 case IB_FLOW_SPEC_TCP: 1492 case IB_FLOW_SPEC_UDP: 1493 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, LAST_TCP_UDP_FIELD)) 1494 return -ENOTSUPP; 1495 1496 type = ib_spec->type == IB_FLOW_SPEC_TCP ? 1497 MLX4_NET_TRANS_RULE_ID_TCP : 1498 MLX4_NET_TRANS_RULE_ID_UDP; 1499 mlx4_spec->tcp_udp.dst_port = ib_spec->tcp_udp.val.dst_port; 1500 mlx4_spec->tcp_udp.dst_port_msk = ib_spec->tcp_udp.mask.dst_port; 1501 mlx4_spec->tcp_udp.src_port = ib_spec->tcp_udp.val.src_port; 1502 mlx4_spec->tcp_udp.src_port_msk = ib_spec->tcp_udp.mask.src_port; 1503 break; 1504 1505 default: 1506 return -EINVAL; 1507 } 1508 if (mlx4_map_sw_to_hw_steering_id(dev, type) < 0 || 1509 mlx4_hw_rule_sz(dev, type) < 0) 1510 return -EINVAL; 1511 mlx4_spec->id = cpu_to_be16(mlx4_map_sw_to_hw_steering_id(dev, type)); 1512 mlx4_spec->size = mlx4_hw_rule_sz(dev, type) >> 2; 1513 return mlx4_hw_rule_sz(dev, type); 1514 } 1515 1516 struct default_rules { 1517 __u32 mandatory_fields[IB_FLOW_SPEC_SUPPORT_LAYERS]; 1518 __u32 mandatory_not_fields[IB_FLOW_SPEC_SUPPORT_LAYERS]; 1519 __u32 rules_create_list[IB_FLOW_SPEC_SUPPORT_LAYERS]; 1520 __u8 link_layer; 1521 }; 1522 static const struct default_rules default_table[] = { 1523 { 1524 .mandatory_fields = {IB_FLOW_SPEC_IPV4}, 1525 .mandatory_not_fields = {IB_FLOW_SPEC_ETH}, 1526 .rules_create_list = {IB_FLOW_SPEC_IB}, 1527 .link_layer = IB_LINK_LAYER_INFINIBAND 1528 } 1529 }; 1530 1531 static int __mlx4_ib_default_rules_match(struct ib_qp *qp, 1532 struct ib_flow_attr *flow_attr) 1533 { 1534 int i, j, k; 1535 void *ib_flow; 1536 const struct default_rules *pdefault_rules = default_table; 1537 u8 link_layer = rdma_port_get_link_layer(qp->device, flow_attr->port); 1538 1539 for (i = 0; i < ARRAY_SIZE(default_table); i++, pdefault_rules++) { 1540 __u32 field_types[IB_FLOW_SPEC_SUPPORT_LAYERS]; 1541 memset(&field_types, 0, sizeof(field_types)); 1542 1543 if (link_layer != pdefault_rules->link_layer) 1544 continue; 1545 1546 ib_flow = flow_attr + 1; 1547 /* we assume the specs are sorted */ 1548 for (j = 0, k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS && 1549 j < flow_attr->num_of_specs; k++) { 1550 union ib_flow_spec *current_flow = 1551 (union ib_flow_spec *)ib_flow; 1552 1553 /* same layer but different type */ 1554 if (((current_flow->type & IB_FLOW_SPEC_LAYER_MASK) == 1555 (pdefault_rules->mandatory_fields[k] & 1556 IB_FLOW_SPEC_LAYER_MASK)) && 1557 (current_flow->type != 1558 pdefault_rules->mandatory_fields[k])) 1559 goto out; 1560 1561 /* same layer, try match next one */ 1562 if (current_flow->type == 1563 pdefault_rules->mandatory_fields[k]) { 1564 j++; 1565 ib_flow += 1566 ((union ib_flow_spec *)ib_flow)->size; 1567 } 1568 } 1569 1570 ib_flow = flow_attr + 1; 1571 for (j = 0; j < flow_attr->num_of_specs; 1572 j++, ib_flow += ((union ib_flow_spec *)ib_flow)->size) 1573 for (k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS; k++) 1574 /* same layer and same type */ 1575 if (((union ib_flow_spec *)ib_flow)->type == 1576 pdefault_rules->mandatory_not_fields[k]) 1577 goto out; 1578 1579 return i; 1580 } 1581 out: 1582 return -1; 1583 } 1584 1585 static int __mlx4_ib_create_default_rules( 1586 struct mlx4_ib_dev *mdev, 1587 struct ib_qp *qp, 1588 const struct default_rules *pdefault_rules, 1589 struct _rule_hw *mlx4_spec) { 1590 int size = 0; 1591 int i; 1592 1593 for (i = 0; i < ARRAY_SIZE(pdefault_rules->rules_create_list); i++) { 1594 int ret; 1595 union ib_flow_spec ib_spec; 1596 switch (pdefault_rules->rules_create_list[i]) { 1597 case 0: 1598 /* no rule */ 1599 continue; 1600 case IB_FLOW_SPEC_IB: 1601 ib_spec.type = IB_FLOW_SPEC_IB; 1602 ib_spec.size = sizeof(struct ib_flow_spec_ib); 1603 1604 break; 1605 default: 1606 /* invalid rule */ 1607 return -EINVAL; 1608 } 1609 /* We must put empty rule, qpn is being ignored */ 1610 ret = parse_flow_attr(mdev->dev, 0, &ib_spec, 1611 mlx4_spec); 1612 if (ret < 0) { 1613 pr_info("invalid parsing\n"); 1614 return -EINVAL; 1615 } 1616 1617 mlx4_spec = (void *)mlx4_spec + ret; 1618 size += ret; 1619 } 1620 return size; 1621 } 1622 1623 static int __mlx4_ib_create_flow(struct ib_qp *qp, struct ib_flow_attr *flow_attr, 1624 int domain, 1625 enum mlx4_net_trans_promisc_mode flow_type, 1626 u64 *reg_id) 1627 { 1628 int ret, i; 1629 int size = 0; 1630 void *ib_flow; 1631 struct mlx4_ib_dev *mdev = to_mdev(qp->device); 1632 struct mlx4_cmd_mailbox *mailbox; 1633 struct mlx4_net_trans_rule_hw_ctrl *ctrl; 1634 int default_flow; 1635 1636 static const u16 __mlx4_domain[] = { 1637 [IB_FLOW_DOMAIN_USER] = MLX4_DOMAIN_UVERBS, 1638 [IB_FLOW_DOMAIN_ETHTOOL] = MLX4_DOMAIN_ETHTOOL, 1639 [IB_FLOW_DOMAIN_RFS] = MLX4_DOMAIN_RFS, 1640 [IB_FLOW_DOMAIN_NIC] = MLX4_DOMAIN_NIC, 1641 }; 1642 1643 if (flow_attr->priority > MLX4_IB_FLOW_MAX_PRIO) { 1644 pr_err("Invalid priority value %d\n", flow_attr->priority); 1645 return -EINVAL; 1646 } 1647 1648 if (domain >= IB_FLOW_DOMAIN_NUM) { 1649 pr_err("Invalid domain value %d\n", domain); 1650 return -EINVAL; 1651 } 1652 1653 if (mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type) < 0) 1654 return -EINVAL; 1655 1656 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev); 1657 if (IS_ERR(mailbox)) 1658 return PTR_ERR(mailbox); 1659 ctrl = mailbox->buf; 1660 1661 ctrl->prio = cpu_to_be16(__mlx4_domain[domain] | 1662 flow_attr->priority); 1663 ctrl->type = mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type); 1664 ctrl->port = flow_attr->port; 1665 ctrl->qpn = cpu_to_be32(qp->qp_num); 1666 1667 ib_flow = flow_attr + 1; 1668 size += sizeof(struct mlx4_net_trans_rule_hw_ctrl); 1669 /* Add default flows */ 1670 default_flow = __mlx4_ib_default_rules_match(qp, flow_attr); 1671 if (default_flow >= 0) { 1672 ret = __mlx4_ib_create_default_rules( 1673 mdev, qp, default_table + default_flow, 1674 mailbox->buf + size); 1675 if (ret < 0) { 1676 mlx4_free_cmd_mailbox(mdev->dev, mailbox); 1677 return -EINVAL; 1678 } 1679 size += ret; 1680 } 1681 for (i = 0; i < flow_attr->num_of_specs; i++) { 1682 ret = parse_flow_attr(mdev->dev, qp->qp_num, ib_flow, 1683 mailbox->buf + size); 1684 if (ret < 0) { 1685 mlx4_free_cmd_mailbox(mdev->dev, mailbox); 1686 return -EINVAL; 1687 } 1688 ib_flow += ((union ib_flow_spec *) ib_flow)->size; 1689 size += ret; 1690 } 1691 1692 if (mlx4_is_master(mdev->dev) && flow_type == MLX4_FS_REGULAR && 1693 flow_attr->num_of_specs == 1) { 1694 struct _rule_hw *rule_header = (struct _rule_hw *)(ctrl + 1); 1695 enum ib_flow_spec_type header_spec = 1696 ((union ib_flow_spec *)(flow_attr + 1))->type; 1697 1698 if (header_spec == IB_FLOW_SPEC_ETH) 1699 mlx4_handle_eth_header_mcast_prio(ctrl, rule_header); 1700 } 1701 1702 ret = mlx4_cmd_imm(mdev->dev, mailbox->dma, reg_id, size >> 2, 0, 1703 MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A, 1704 MLX4_CMD_NATIVE); 1705 if (ret == -ENOMEM) 1706 pr_err("mcg table is full. Fail to register network rule.\n"); 1707 else if (ret == -ENXIO) 1708 pr_err("Device managed flow steering is disabled. Fail to register network rule.\n"); 1709 else if (ret) 1710 pr_err("Invalid argument. Fail to register network rule.\n"); 1711 1712 mlx4_free_cmd_mailbox(mdev->dev, mailbox); 1713 return ret; 1714 } 1715 1716 static int __mlx4_ib_destroy_flow(struct mlx4_dev *dev, u64 reg_id) 1717 { 1718 int err; 1719 err = mlx4_cmd(dev, reg_id, 0, 0, 1720 MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A, 1721 MLX4_CMD_NATIVE); 1722 if (err) 1723 pr_err("Fail to detach network rule. registration id = 0x%llx\n", 1724 reg_id); 1725 return err; 1726 } 1727 1728 static int mlx4_ib_tunnel_steer_add(struct ib_qp *qp, struct ib_flow_attr *flow_attr, 1729 u64 *reg_id) 1730 { 1731 void *ib_flow; 1732 union ib_flow_spec *ib_spec; 1733 struct mlx4_dev *dev = to_mdev(qp->device)->dev; 1734 int err = 0; 1735 1736 if (dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN || 1737 dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC) 1738 return 0; /* do nothing */ 1739 1740 ib_flow = flow_attr + 1; 1741 ib_spec = (union ib_flow_spec *)ib_flow; 1742 1743 if (ib_spec->type != IB_FLOW_SPEC_ETH || flow_attr->num_of_specs != 1) 1744 return 0; /* do nothing */ 1745 1746 err = mlx4_tunnel_steer_add(to_mdev(qp->device)->dev, ib_spec->eth.val.dst_mac, 1747 flow_attr->port, qp->qp_num, 1748 MLX4_DOMAIN_UVERBS | (flow_attr->priority & 0xff), 1749 reg_id); 1750 return err; 1751 } 1752 1753 static int mlx4_ib_add_dont_trap_rule(struct mlx4_dev *dev, 1754 struct ib_flow_attr *flow_attr, 1755 enum mlx4_net_trans_promisc_mode *type) 1756 { 1757 int err = 0; 1758 1759 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER) || 1760 (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC) || 1761 (flow_attr->num_of_specs > 1) || (flow_attr->priority != 0)) { 1762 return -EOPNOTSUPP; 1763 } 1764 1765 if (flow_attr->num_of_specs == 0) { 1766 type[0] = MLX4_FS_MC_SNIFFER; 1767 type[1] = MLX4_FS_UC_SNIFFER; 1768 } else { 1769 union ib_flow_spec *ib_spec; 1770 1771 ib_spec = (union ib_flow_spec *)(flow_attr + 1); 1772 if (ib_spec->type != IB_FLOW_SPEC_ETH) 1773 return -EINVAL; 1774 1775 /* if all is zero than MC and UC */ 1776 if (is_zero_ether_addr(ib_spec->eth.mask.dst_mac)) { 1777 type[0] = MLX4_FS_MC_SNIFFER; 1778 type[1] = MLX4_FS_UC_SNIFFER; 1779 } else { 1780 u8 mac[ETH_ALEN] = {ib_spec->eth.mask.dst_mac[0] ^ 0x01, 1781 ib_spec->eth.mask.dst_mac[1], 1782 ib_spec->eth.mask.dst_mac[2], 1783 ib_spec->eth.mask.dst_mac[3], 1784 ib_spec->eth.mask.dst_mac[4], 1785 ib_spec->eth.mask.dst_mac[5]}; 1786 1787 /* Above xor was only on MC bit, non empty mask is valid 1788 * only if this bit is set and rest are zero. 1789 */ 1790 if (!is_zero_ether_addr(&mac[0])) 1791 return -EINVAL; 1792 1793 if (is_multicast_ether_addr(ib_spec->eth.val.dst_mac)) 1794 type[0] = MLX4_FS_MC_SNIFFER; 1795 else 1796 type[0] = MLX4_FS_UC_SNIFFER; 1797 } 1798 } 1799 1800 return err; 1801 } 1802 1803 static struct ib_flow *mlx4_ib_create_flow(struct ib_qp *qp, 1804 struct ib_flow_attr *flow_attr, 1805 int domain, struct ib_udata *udata) 1806 { 1807 int err = 0, i = 0, j = 0; 1808 struct mlx4_ib_flow *mflow; 1809 enum mlx4_net_trans_promisc_mode type[2]; 1810 struct mlx4_dev *dev = (to_mdev(qp->device))->dev; 1811 int is_bonded = mlx4_is_bonded(dev); 1812 1813 if (flow_attr->port < 1 || flow_attr->port > qp->device->phys_port_cnt) 1814 return ERR_PTR(-EINVAL); 1815 1816 if (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP) 1817 return ERR_PTR(-EOPNOTSUPP); 1818 1819 if ((flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) && 1820 (flow_attr->type != IB_FLOW_ATTR_NORMAL)) 1821 return ERR_PTR(-EOPNOTSUPP); 1822 1823 if (udata && 1824 udata->inlen && !ib_is_udata_cleared(udata, 0, udata->inlen)) 1825 return ERR_PTR(-EOPNOTSUPP); 1826 1827 memset(type, 0, sizeof(type)); 1828 1829 mflow = kzalloc(sizeof(*mflow), GFP_KERNEL); 1830 if (!mflow) { 1831 err = -ENOMEM; 1832 goto err_free; 1833 } 1834 1835 switch (flow_attr->type) { 1836 case IB_FLOW_ATTR_NORMAL: 1837 /* If dont trap flag (continue match) is set, under specific 1838 * condition traffic be replicated to given qp, 1839 * without stealing it 1840 */ 1841 if (unlikely(flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)) { 1842 err = mlx4_ib_add_dont_trap_rule(dev, 1843 flow_attr, 1844 type); 1845 if (err) 1846 goto err_free; 1847 } else { 1848 type[0] = MLX4_FS_REGULAR; 1849 } 1850 break; 1851 1852 case IB_FLOW_ATTR_ALL_DEFAULT: 1853 type[0] = MLX4_FS_ALL_DEFAULT; 1854 break; 1855 1856 case IB_FLOW_ATTR_MC_DEFAULT: 1857 type[0] = MLX4_FS_MC_DEFAULT; 1858 break; 1859 1860 case IB_FLOW_ATTR_SNIFFER: 1861 type[0] = MLX4_FS_MIRROR_RX_PORT; 1862 type[1] = MLX4_FS_MIRROR_SX_PORT; 1863 break; 1864 1865 default: 1866 err = -EINVAL; 1867 goto err_free; 1868 } 1869 1870 while (i < ARRAY_SIZE(type) && type[i]) { 1871 err = __mlx4_ib_create_flow(qp, flow_attr, domain, type[i], 1872 &mflow->reg_id[i].id); 1873 if (err) 1874 goto err_create_flow; 1875 if (is_bonded) { 1876 /* Application always sees one port so the mirror rule 1877 * must be on port #2 1878 */ 1879 flow_attr->port = 2; 1880 err = __mlx4_ib_create_flow(qp, flow_attr, 1881 domain, type[j], 1882 &mflow->reg_id[j].mirror); 1883 flow_attr->port = 1; 1884 if (err) 1885 goto err_create_flow; 1886 j++; 1887 } 1888 1889 i++; 1890 } 1891 1892 if (i < ARRAY_SIZE(type) && flow_attr->type == IB_FLOW_ATTR_NORMAL) { 1893 err = mlx4_ib_tunnel_steer_add(qp, flow_attr, 1894 &mflow->reg_id[i].id); 1895 if (err) 1896 goto err_create_flow; 1897 1898 if (is_bonded) { 1899 flow_attr->port = 2; 1900 err = mlx4_ib_tunnel_steer_add(qp, flow_attr, 1901 &mflow->reg_id[j].mirror); 1902 flow_attr->port = 1; 1903 if (err) 1904 goto err_create_flow; 1905 j++; 1906 } 1907 /* function to create mirror rule */ 1908 i++; 1909 } 1910 1911 return &mflow->ibflow; 1912 1913 err_create_flow: 1914 while (i) { 1915 (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev, 1916 mflow->reg_id[i].id); 1917 i--; 1918 } 1919 1920 while (j) { 1921 (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev, 1922 mflow->reg_id[j].mirror); 1923 j--; 1924 } 1925 err_free: 1926 kfree(mflow); 1927 return ERR_PTR(err); 1928 } 1929 1930 static int mlx4_ib_destroy_flow(struct ib_flow *flow_id) 1931 { 1932 int err, ret = 0; 1933 int i = 0; 1934 struct mlx4_ib_dev *mdev = to_mdev(flow_id->qp->device); 1935 struct mlx4_ib_flow *mflow = to_mflow(flow_id); 1936 1937 while (i < ARRAY_SIZE(mflow->reg_id) && mflow->reg_id[i].id) { 1938 err = __mlx4_ib_destroy_flow(mdev->dev, mflow->reg_id[i].id); 1939 if (err) 1940 ret = err; 1941 if (mflow->reg_id[i].mirror) { 1942 err = __mlx4_ib_destroy_flow(mdev->dev, 1943 mflow->reg_id[i].mirror); 1944 if (err) 1945 ret = err; 1946 } 1947 i++; 1948 } 1949 1950 kfree(mflow); 1951 return ret; 1952 } 1953 1954 static int mlx4_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 1955 { 1956 int err; 1957 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); 1958 struct mlx4_dev *dev = mdev->dev; 1959 struct mlx4_ib_qp *mqp = to_mqp(ibqp); 1960 struct mlx4_ib_steering *ib_steering = NULL; 1961 enum mlx4_protocol prot = MLX4_PROT_IB_IPV6; 1962 struct mlx4_flow_reg_id reg_id; 1963 1964 if (mdev->dev->caps.steering_mode == 1965 MLX4_STEERING_MODE_DEVICE_MANAGED) { 1966 ib_steering = kmalloc(sizeof(*ib_steering), GFP_KERNEL); 1967 if (!ib_steering) 1968 return -ENOMEM; 1969 } 1970 1971 err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw, mqp->port, 1972 !!(mqp->flags & 1973 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK), 1974 prot, ®_id.id); 1975 if (err) { 1976 pr_err("multicast attach op failed, err %d\n", err); 1977 goto err_malloc; 1978 } 1979 1980 reg_id.mirror = 0; 1981 if (mlx4_is_bonded(dev)) { 1982 err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw, 1983 (mqp->port == 1) ? 2 : 1, 1984 !!(mqp->flags & 1985 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK), 1986 prot, ®_id.mirror); 1987 if (err) 1988 goto err_add; 1989 } 1990 1991 err = add_gid_entry(ibqp, gid); 1992 if (err) 1993 goto err_add; 1994 1995 if (ib_steering) { 1996 memcpy(ib_steering->gid.raw, gid->raw, 16); 1997 ib_steering->reg_id = reg_id; 1998 mutex_lock(&mqp->mutex); 1999 list_add(&ib_steering->list, &mqp->steering_rules); 2000 mutex_unlock(&mqp->mutex); 2001 } 2002 return 0; 2003 2004 err_add: 2005 mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw, 2006 prot, reg_id.id); 2007 if (reg_id.mirror) 2008 mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw, 2009 prot, reg_id.mirror); 2010 err_malloc: 2011 kfree(ib_steering); 2012 2013 return err; 2014 } 2015 2016 static struct mlx4_ib_gid_entry *find_gid_entry(struct mlx4_ib_qp *qp, u8 *raw) 2017 { 2018 struct mlx4_ib_gid_entry *ge; 2019 struct mlx4_ib_gid_entry *tmp; 2020 struct mlx4_ib_gid_entry *ret = NULL; 2021 2022 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) { 2023 if (!memcmp(raw, ge->gid.raw, 16)) { 2024 ret = ge; 2025 break; 2026 } 2027 } 2028 2029 return ret; 2030 } 2031 2032 static int mlx4_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2033 { 2034 int err; 2035 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); 2036 struct mlx4_dev *dev = mdev->dev; 2037 struct mlx4_ib_qp *mqp = to_mqp(ibqp); 2038 struct net_device *ndev; 2039 struct mlx4_ib_gid_entry *ge; 2040 struct mlx4_flow_reg_id reg_id = {0, 0}; 2041 enum mlx4_protocol prot = MLX4_PROT_IB_IPV6; 2042 2043 if (mdev->dev->caps.steering_mode == 2044 MLX4_STEERING_MODE_DEVICE_MANAGED) { 2045 struct mlx4_ib_steering *ib_steering; 2046 2047 mutex_lock(&mqp->mutex); 2048 list_for_each_entry(ib_steering, &mqp->steering_rules, list) { 2049 if (!memcmp(ib_steering->gid.raw, gid->raw, 16)) { 2050 list_del(&ib_steering->list); 2051 break; 2052 } 2053 } 2054 mutex_unlock(&mqp->mutex); 2055 if (&ib_steering->list == &mqp->steering_rules) { 2056 pr_err("Couldn't find reg_id for mgid. Steering rule is left attached\n"); 2057 return -EINVAL; 2058 } 2059 reg_id = ib_steering->reg_id; 2060 kfree(ib_steering); 2061 } 2062 2063 err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw, 2064 prot, reg_id.id); 2065 if (err) 2066 return err; 2067 2068 if (mlx4_is_bonded(dev)) { 2069 err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw, 2070 prot, reg_id.mirror); 2071 if (err) 2072 return err; 2073 } 2074 2075 mutex_lock(&mqp->mutex); 2076 ge = find_gid_entry(mqp, gid->raw); 2077 if (ge) { 2078 spin_lock_bh(&mdev->iboe.lock); 2079 ndev = ge->added ? mdev->iboe.netdevs[ge->port - 1] : NULL; 2080 if (ndev) 2081 dev_hold(ndev); 2082 spin_unlock_bh(&mdev->iboe.lock); 2083 if (ndev) 2084 dev_put(ndev); 2085 list_del(&ge->list); 2086 kfree(ge); 2087 } else 2088 pr_warn("could not find mgid entry\n"); 2089 2090 mutex_unlock(&mqp->mutex); 2091 2092 return 0; 2093 } 2094 2095 static int init_node_data(struct mlx4_ib_dev *dev) 2096 { 2097 struct ib_smp *in_mad = NULL; 2098 struct ib_smp *out_mad = NULL; 2099 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; 2100 int err = -ENOMEM; 2101 2102 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); 2103 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 2104 if (!in_mad || !out_mad) 2105 goto out; 2106 2107 init_query_mad(in_mad); 2108 in_mad->attr_id = IB_SMP_ATTR_NODE_DESC; 2109 if (mlx4_is_master(dev->dev)) 2110 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; 2111 2112 err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad); 2113 if (err) 2114 goto out; 2115 2116 memcpy(dev->ib_dev.node_desc, out_mad->data, IB_DEVICE_NODE_DESC_MAX); 2117 2118 in_mad->attr_id = IB_SMP_ATTR_NODE_INFO; 2119 2120 err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad); 2121 if (err) 2122 goto out; 2123 2124 dev->dev->rev_id = be32_to_cpup((__be32 *) (out_mad->data + 32)); 2125 memcpy(&dev->ib_dev.node_guid, out_mad->data + 12, 8); 2126 2127 out: 2128 kfree(in_mad); 2129 kfree(out_mad); 2130 return err; 2131 } 2132 2133 static ssize_t show_hca(struct device *device, struct device_attribute *attr, 2134 char *buf) 2135 { 2136 struct mlx4_ib_dev *dev = 2137 container_of(device, struct mlx4_ib_dev, ib_dev.dev); 2138 return sprintf(buf, "MT%d\n", dev->dev->persist->pdev->device); 2139 } 2140 2141 static ssize_t show_rev(struct device *device, struct device_attribute *attr, 2142 char *buf) 2143 { 2144 struct mlx4_ib_dev *dev = 2145 container_of(device, struct mlx4_ib_dev, ib_dev.dev); 2146 return sprintf(buf, "%x\n", dev->dev->rev_id); 2147 } 2148 2149 static ssize_t show_board(struct device *device, struct device_attribute *attr, 2150 char *buf) 2151 { 2152 struct mlx4_ib_dev *dev = 2153 container_of(device, struct mlx4_ib_dev, ib_dev.dev); 2154 return sprintf(buf, "%.*s\n", MLX4_BOARD_ID_LEN, 2155 dev->dev->board_id); 2156 } 2157 2158 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL); 2159 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL); 2160 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL); 2161 2162 static struct device_attribute *mlx4_class_attributes[] = { 2163 &dev_attr_hw_rev, 2164 &dev_attr_hca_type, 2165 &dev_attr_board_id 2166 }; 2167 2168 struct diag_counter { 2169 const char *name; 2170 u32 offset; 2171 }; 2172 2173 #define DIAG_COUNTER(_name, _offset) \ 2174 { .name = #_name, .offset = _offset } 2175 2176 static const struct diag_counter diag_basic[] = { 2177 DIAG_COUNTER(rq_num_lle, 0x00), 2178 DIAG_COUNTER(sq_num_lle, 0x04), 2179 DIAG_COUNTER(rq_num_lqpoe, 0x08), 2180 DIAG_COUNTER(sq_num_lqpoe, 0x0C), 2181 DIAG_COUNTER(rq_num_lpe, 0x18), 2182 DIAG_COUNTER(sq_num_lpe, 0x1C), 2183 DIAG_COUNTER(rq_num_wrfe, 0x20), 2184 DIAG_COUNTER(sq_num_wrfe, 0x24), 2185 DIAG_COUNTER(sq_num_mwbe, 0x2C), 2186 DIAG_COUNTER(sq_num_bre, 0x34), 2187 DIAG_COUNTER(sq_num_rire, 0x44), 2188 DIAG_COUNTER(rq_num_rire, 0x48), 2189 DIAG_COUNTER(sq_num_rae, 0x4C), 2190 DIAG_COUNTER(rq_num_rae, 0x50), 2191 DIAG_COUNTER(sq_num_roe, 0x54), 2192 DIAG_COUNTER(sq_num_tree, 0x5C), 2193 DIAG_COUNTER(sq_num_rree, 0x64), 2194 DIAG_COUNTER(rq_num_rnr, 0x68), 2195 DIAG_COUNTER(sq_num_rnr, 0x6C), 2196 DIAG_COUNTER(rq_num_oos, 0x100), 2197 DIAG_COUNTER(sq_num_oos, 0x104), 2198 }; 2199 2200 static const struct diag_counter diag_ext[] = { 2201 DIAG_COUNTER(rq_num_dup, 0x130), 2202 DIAG_COUNTER(sq_num_to, 0x134), 2203 }; 2204 2205 static const struct diag_counter diag_device_only[] = { 2206 DIAG_COUNTER(num_cqovf, 0x1A0), 2207 DIAG_COUNTER(rq_num_udsdprd, 0x118), 2208 }; 2209 2210 static struct rdma_hw_stats *mlx4_ib_alloc_hw_stats(struct ib_device *ibdev, 2211 u8 port_num) 2212 { 2213 struct mlx4_ib_dev *dev = to_mdev(ibdev); 2214 struct mlx4_ib_diag_counters *diag = dev->diag_counters; 2215 2216 if (!diag[!!port_num].name) 2217 return NULL; 2218 2219 return rdma_alloc_hw_stats_struct(diag[!!port_num].name, 2220 diag[!!port_num].num_counters, 2221 RDMA_HW_STATS_DEFAULT_LIFESPAN); 2222 } 2223 2224 static int mlx4_ib_get_hw_stats(struct ib_device *ibdev, 2225 struct rdma_hw_stats *stats, 2226 u8 port, int index) 2227 { 2228 struct mlx4_ib_dev *dev = to_mdev(ibdev); 2229 struct mlx4_ib_diag_counters *diag = dev->diag_counters; 2230 u32 hw_value[ARRAY_SIZE(diag_device_only) + 2231 ARRAY_SIZE(diag_ext) + ARRAY_SIZE(diag_basic)] = {}; 2232 int ret; 2233 int i; 2234 2235 ret = mlx4_query_diag_counters(dev->dev, 2236 MLX4_OP_MOD_QUERY_TRANSPORT_CI_ERRORS, 2237 diag[!!port].offset, hw_value, 2238 diag[!!port].num_counters, port); 2239 2240 if (ret) 2241 return ret; 2242 2243 for (i = 0; i < diag[!!port].num_counters; i++) 2244 stats->value[i] = hw_value[i]; 2245 2246 return diag[!!port].num_counters; 2247 } 2248 2249 static int __mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev *ibdev, 2250 const char ***name, 2251 u32 **offset, 2252 u32 *num, 2253 bool port) 2254 { 2255 u32 num_counters; 2256 2257 num_counters = ARRAY_SIZE(diag_basic); 2258 2259 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT) 2260 num_counters += ARRAY_SIZE(diag_ext); 2261 2262 if (!port) 2263 num_counters += ARRAY_SIZE(diag_device_only); 2264 2265 *name = kcalloc(num_counters, sizeof(**name), GFP_KERNEL); 2266 if (!*name) 2267 return -ENOMEM; 2268 2269 *offset = kcalloc(num_counters, sizeof(**offset), GFP_KERNEL); 2270 if (!*offset) 2271 goto err_name; 2272 2273 *num = num_counters; 2274 2275 return 0; 2276 2277 err_name: 2278 kfree(*name); 2279 return -ENOMEM; 2280 } 2281 2282 static void mlx4_ib_fill_diag_counters(struct mlx4_ib_dev *ibdev, 2283 const char **name, 2284 u32 *offset, 2285 bool port) 2286 { 2287 int i; 2288 int j; 2289 2290 for (i = 0, j = 0; i < ARRAY_SIZE(diag_basic); i++, j++) { 2291 name[i] = diag_basic[i].name; 2292 offset[i] = diag_basic[i].offset; 2293 } 2294 2295 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT) { 2296 for (i = 0; i < ARRAY_SIZE(diag_ext); i++, j++) { 2297 name[j] = diag_ext[i].name; 2298 offset[j] = diag_ext[i].offset; 2299 } 2300 } 2301 2302 if (!port) { 2303 for (i = 0; i < ARRAY_SIZE(diag_device_only); i++, j++) { 2304 name[j] = diag_device_only[i].name; 2305 offset[j] = diag_device_only[i].offset; 2306 } 2307 } 2308 } 2309 2310 static int mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev *ibdev) 2311 { 2312 struct mlx4_ib_diag_counters *diag = ibdev->diag_counters; 2313 int i; 2314 int ret; 2315 bool per_port = !!(ibdev->dev->caps.flags2 & 2316 MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT); 2317 2318 if (mlx4_is_slave(ibdev->dev)) 2319 return 0; 2320 2321 for (i = 0; i < MLX4_DIAG_COUNTERS_TYPES; i++) { 2322 /* i == 1 means we are building port counters */ 2323 if (i && !per_port) 2324 continue; 2325 2326 ret = __mlx4_ib_alloc_diag_counters(ibdev, &diag[i].name, 2327 &diag[i].offset, 2328 &diag[i].num_counters, i); 2329 if (ret) 2330 goto err_alloc; 2331 2332 mlx4_ib_fill_diag_counters(ibdev, diag[i].name, 2333 diag[i].offset, i); 2334 } 2335 2336 ibdev->ib_dev.get_hw_stats = mlx4_ib_get_hw_stats; 2337 ibdev->ib_dev.alloc_hw_stats = mlx4_ib_alloc_hw_stats; 2338 2339 return 0; 2340 2341 err_alloc: 2342 if (i) { 2343 kfree(diag[i - 1].name); 2344 kfree(diag[i - 1].offset); 2345 } 2346 2347 return ret; 2348 } 2349 2350 static void mlx4_ib_diag_cleanup(struct mlx4_ib_dev *ibdev) 2351 { 2352 int i; 2353 2354 for (i = 0; i < MLX4_DIAG_COUNTERS_TYPES; i++) { 2355 kfree(ibdev->diag_counters[i].offset); 2356 kfree(ibdev->diag_counters[i].name); 2357 } 2358 } 2359 2360 #define MLX4_IB_INVALID_MAC ((u64)-1) 2361 static void mlx4_ib_update_qps(struct mlx4_ib_dev *ibdev, 2362 struct net_device *dev, 2363 int port) 2364 { 2365 u64 new_smac = 0; 2366 u64 release_mac = MLX4_IB_INVALID_MAC; 2367 struct mlx4_ib_qp *qp; 2368 2369 read_lock(&dev_base_lock); 2370 new_smac = mlx4_mac_to_u64(dev->dev_addr); 2371 read_unlock(&dev_base_lock); 2372 2373 atomic64_set(&ibdev->iboe.mac[port - 1], new_smac); 2374 2375 /* no need for update QP1 and mac registration in non-SRIOV */ 2376 if (!mlx4_is_mfunc(ibdev->dev)) 2377 return; 2378 2379 mutex_lock(&ibdev->qp1_proxy_lock[port - 1]); 2380 qp = ibdev->qp1_proxy[port - 1]; 2381 if (qp) { 2382 int new_smac_index; 2383 u64 old_smac; 2384 struct mlx4_update_qp_params update_params; 2385 2386 mutex_lock(&qp->mutex); 2387 old_smac = qp->pri.smac; 2388 if (new_smac == old_smac) 2389 goto unlock; 2390 2391 new_smac_index = mlx4_register_mac(ibdev->dev, port, new_smac); 2392 2393 if (new_smac_index < 0) 2394 goto unlock; 2395 2396 update_params.smac_index = new_smac_index; 2397 if (mlx4_update_qp(ibdev->dev, qp->mqp.qpn, MLX4_UPDATE_QP_SMAC, 2398 &update_params)) { 2399 release_mac = new_smac; 2400 goto unlock; 2401 } 2402 /* if old port was zero, no mac was yet registered for this QP */ 2403 if (qp->pri.smac_port) 2404 release_mac = old_smac; 2405 qp->pri.smac = new_smac; 2406 qp->pri.smac_port = port; 2407 qp->pri.smac_index = new_smac_index; 2408 } 2409 2410 unlock: 2411 if (release_mac != MLX4_IB_INVALID_MAC) 2412 mlx4_unregister_mac(ibdev->dev, port, release_mac); 2413 if (qp) 2414 mutex_unlock(&qp->mutex); 2415 mutex_unlock(&ibdev->qp1_proxy_lock[port - 1]); 2416 } 2417 2418 static void mlx4_ib_scan_netdevs(struct mlx4_ib_dev *ibdev, 2419 struct net_device *dev, 2420 unsigned long event) 2421 2422 { 2423 struct mlx4_ib_iboe *iboe; 2424 int update_qps_port = -1; 2425 int port; 2426 2427 ASSERT_RTNL(); 2428 2429 iboe = &ibdev->iboe; 2430 2431 spin_lock_bh(&iboe->lock); 2432 mlx4_foreach_ib_transport_port(port, ibdev->dev) { 2433 2434 iboe->netdevs[port - 1] = 2435 mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port); 2436 2437 if (dev == iboe->netdevs[port - 1] && 2438 (event == NETDEV_CHANGEADDR || event == NETDEV_REGISTER || 2439 event == NETDEV_UP || event == NETDEV_CHANGE)) 2440 update_qps_port = port; 2441 2442 } 2443 spin_unlock_bh(&iboe->lock); 2444 2445 if (update_qps_port > 0) 2446 mlx4_ib_update_qps(ibdev, dev, update_qps_port); 2447 } 2448 2449 static int mlx4_ib_netdev_event(struct notifier_block *this, 2450 unsigned long event, void *ptr) 2451 { 2452 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 2453 struct mlx4_ib_dev *ibdev; 2454 2455 if (!net_eq(dev_net(dev), &init_net)) 2456 return NOTIFY_DONE; 2457 2458 ibdev = container_of(this, struct mlx4_ib_dev, iboe.nb); 2459 mlx4_ib_scan_netdevs(ibdev, dev, event); 2460 2461 return NOTIFY_DONE; 2462 } 2463 2464 static void init_pkeys(struct mlx4_ib_dev *ibdev) 2465 { 2466 int port; 2467 int slave; 2468 int i; 2469 2470 if (mlx4_is_master(ibdev->dev)) { 2471 for (slave = 0; slave <= ibdev->dev->persist->num_vfs; 2472 ++slave) { 2473 for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) { 2474 for (i = 0; 2475 i < ibdev->dev->phys_caps.pkey_phys_table_len[port]; 2476 ++i) { 2477 ibdev->pkeys.virt2phys_pkey[slave][port - 1][i] = 2478 /* master has the identity virt2phys pkey mapping */ 2479 (slave == mlx4_master_func_num(ibdev->dev) || !i) ? i : 2480 ibdev->dev->phys_caps.pkey_phys_table_len[port] - 1; 2481 mlx4_sync_pkey_table(ibdev->dev, slave, port, i, 2482 ibdev->pkeys.virt2phys_pkey[slave][port - 1][i]); 2483 } 2484 } 2485 } 2486 /* initialize pkey cache */ 2487 for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) { 2488 for (i = 0; 2489 i < ibdev->dev->phys_caps.pkey_phys_table_len[port]; 2490 ++i) 2491 ibdev->pkeys.phys_pkey_cache[port-1][i] = 2492 (i) ? 0 : 0xFFFF; 2493 } 2494 } 2495 } 2496 2497 static void mlx4_ib_alloc_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev) 2498 { 2499 int i, j, eq = 0, total_eqs = 0; 2500 2501 ibdev->eq_table = kcalloc(dev->caps.num_comp_vectors, 2502 sizeof(ibdev->eq_table[0]), GFP_KERNEL); 2503 if (!ibdev->eq_table) 2504 return; 2505 2506 for (i = 1; i <= dev->caps.num_ports; i++) { 2507 for (j = 0; j < mlx4_get_eqs_per_port(dev, i); 2508 j++, total_eqs++) { 2509 if (i > 1 && mlx4_is_eq_shared(dev, total_eqs)) 2510 continue; 2511 ibdev->eq_table[eq] = total_eqs; 2512 if (!mlx4_assign_eq(dev, i, 2513 &ibdev->eq_table[eq])) 2514 eq++; 2515 else 2516 ibdev->eq_table[eq] = -1; 2517 } 2518 } 2519 2520 for (i = eq; i < dev->caps.num_comp_vectors; 2521 ibdev->eq_table[i++] = -1) 2522 ; 2523 2524 /* Advertise the new number of EQs to clients */ 2525 ibdev->ib_dev.num_comp_vectors = eq; 2526 } 2527 2528 static void mlx4_ib_free_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev) 2529 { 2530 int i; 2531 int total_eqs = ibdev->ib_dev.num_comp_vectors; 2532 2533 /* no eqs were allocated */ 2534 if (!ibdev->eq_table) 2535 return; 2536 2537 /* Reset the advertised EQ number */ 2538 ibdev->ib_dev.num_comp_vectors = 0; 2539 2540 for (i = 0; i < total_eqs; i++) 2541 mlx4_release_eq(dev, ibdev->eq_table[i]); 2542 2543 kfree(ibdev->eq_table); 2544 ibdev->eq_table = NULL; 2545 } 2546 2547 static int mlx4_port_immutable(struct ib_device *ibdev, u8 port_num, 2548 struct ib_port_immutable *immutable) 2549 { 2550 struct ib_port_attr attr; 2551 struct mlx4_ib_dev *mdev = to_mdev(ibdev); 2552 int err; 2553 2554 if (mlx4_ib_port_link_layer(ibdev, port_num) == IB_LINK_LAYER_INFINIBAND) { 2555 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_IB; 2556 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 2557 } else { 2558 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE) 2559 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE; 2560 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) 2561 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE | 2562 RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 2563 immutable->core_cap_flags |= RDMA_CORE_PORT_RAW_PACKET; 2564 if (immutable->core_cap_flags & (RDMA_CORE_PORT_IBA_ROCE | 2565 RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP)) 2566 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 2567 } 2568 2569 err = ib_query_port(ibdev, port_num, &attr); 2570 if (err) 2571 return err; 2572 2573 immutable->pkey_tbl_len = attr.pkey_tbl_len; 2574 immutable->gid_tbl_len = attr.gid_tbl_len; 2575 2576 return 0; 2577 } 2578 2579 static void get_fw_ver_str(struct ib_device *device, char *str) 2580 { 2581 struct mlx4_ib_dev *dev = 2582 container_of(device, struct mlx4_ib_dev, ib_dev); 2583 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d", 2584 (int) (dev->dev->caps.fw_ver >> 32), 2585 (int) (dev->dev->caps.fw_ver >> 16) & 0xffff, 2586 (int) dev->dev->caps.fw_ver & 0xffff); 2587 } 2588 2589 static void *mlx4_ib_add(struct mlx4_dev *dev) 2590 { 2591 struct mlx4_ib_dev *ibdev; 2592 int num_ports = 0; 2593 int i, j; 2594 int err; 2595 struct mlx4_ib_iboe *iboe; 2596 int ib_num_ports = 0; 2597 int num_req_counters; 2598 int allocated; 2599 u32 counter_index; 2600 struct counter_index *new_counter_index = NULL; 2601 2602 pr_info_once("%s", mlx4_ib_version); 2603 2604 num_ports = 0; 2605 mlx4_foreach_ib_transport_port(i, dev) 2606 num_ports++; 2607 2608 /* No point in registering a device with no ports... */ 2609 if (num_ports == 0) 2610 return NULL; 2611 2612 ibdev = (struct mlx4_ib_dev *) ib_alloc_device(sizeof *ibdev); 2613 if (!ibdev) { 2614 dev_err(&dev->persist->pdev->dev, 2615 "Device struct alloc failed\n"); 2616 return NULL; 2617 } 2618 2619 iboe = &ibdev->iboe; 2620 2621 if (mlx4_pd_alloc(dev, &ibdev->priv_pdn)) 2622 goto err_dealloc; 2623 2624 if (mlx4_uar_alloc(dev, &ibdev->priv_uar)) 2625 goto err_pd; 2626 2627 ibdev->uar_map = ioremap((phys_addr_t) ibdev->priv_uar.pfn << PAGE_SHIFT, 2628 PAGE_SIZE); 2629 if (!ibdev->uar_map) 2630 goto err_uar; 2631 MLX4_INIT_DOORBELL_LOCK(&ibdev->uar_lock); 2632 2633 ibdev->dev = dev; 2634 ibdev->bond_next_port = 0; 2635 2636 strlcpy(ibdev->ib_dev.name, "mlx4_%d", IB_DEVICE_NAME_MAX); 2637 ibdev->ib_dev.owner = THIS_MODULE; 2638 ibdev->ib_dev.node_type = RDMA_NODE_IB_CA; 2639 ibdev->ib_dev.local_dma_lkey = dev->caps.reserved_lkey; 2640 ibdev->num_ports = num_ports; 2641 ibdev->ib_dev.phys_port_cnt = mlx4_is_bonded(dev) ? 2642 1 : ibdev->num_ports; 2643 ibdev->ib_dev.num_comp_vectors = dev->caps.num_comp_vectors; 2644 ibdev->ib_dev.dev.parent = &dev->persist->pdev->dev; 2645 ibdev->ib_dev.get_netdev = mlx4_ib_get_netdev; 2646 ibdev->ib_dev.add_gid = mlx4_ib_add_gid; 2647 ibdev->ib_dev.del_gid = mlx4_ib_del_gid; 2648 2649 if (dev->caps.userspace_caps) 2650 ibdev->ib_dev.uverbs_abi_ver = MLX4_IB_UVERBS_ABI_VERSION; 2651 else 2652 ibdev->ib_dev.uverbs_abi_ver = MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION; 2653 2654 ibdev->ib_dev.uverbs_cmd_mask = 2655 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | 2656 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | 2657 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | 2658 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | 2659 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | 2660 (1ull << IB_USER_VERBS_CMD_REG_MR) | 2661 (1ull << IB_USER_VERBS_CMD_REREG_MR) | 2662 (1ull << IB_USER_VERBS_CMD_DEREG_MR) | 2663 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 2664 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | 2665 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) | 2666 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | 2667 (1ull << IB_USER_VERBS_CMD_CREATE_QP) | 2668 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | 2669 (1ull << IB_USER_VERBS_CMD_QUERY_QP) | 2670 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | 2671 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) | 2672 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) | 2673 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | 2674 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | 2675 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | 2676 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | 2677 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) | 2678 (1ull << IB_USER_VERBS_CMD_OPEN_QP); 2679 2680 ibdev->ib_dev.query_device = mlx4_ib_query_device; 2681 ibdev->ib_dev.query_port = mlx4_ib_query_port; 2682 ibdev->ib_dev.get_link_layer = mlx4_ib_port_link_layer; 2683 ibdev->ib_dev.query_gid = mlx4_ib_query_gid; 2684 ibdev->ib_dev.query_pkey = mlx4_ib_query_pkey; 2685 ibdev->ib_dev.modify_device = mlx4_ib_modify_device; 2686 ibdev->ib_dev.modify_port = mlx4_ib_modify_port; 2687 ibdev->ib_dev.alloc_ucontext = mlx4_ib_alloc_ucontext; 2688 ibdev->ib_dev.dealloc_ucontext = mlx4_ib_dealloc_ucontext; 2689 ibdev->ib_dev.mmap = mlx4_ib_mmap; 2690 ibdev->ib_dev.alloc_pd = mlx4_ib_alloc_pd; 2691 ibdev->ib_dev.dealloc_pd = mlx4_ib_dealloc_pd; 2692 ibdev->ib_dev.create_ah = mlx4_ib_create_ah; 2693 ibdev->ib_dev.query_ah = mlx4_ib_query_ah; 2694 ibdev->ib_dev.destroy_ah = mlx4_ib_destroy_ah; 2695 ibdev->ib_dev.create_srq = mlx4_ib_create_srq; 2696 ibdev->ib_dev.modify_srq = mlx4_ib_modify_srq; 2697 ibdev->ib_dev.query_srq = mlx4_ib_query_srq; 2698 ibdev->ib_dev.destroy_srq = mlx4_ib_destroy_srq; 2699 ibdev->ib_dev.post_srq_recv = mlx4_ib_post_srq_recv; 2700 ibdev->ib_dev.create_qp = mlx4_ib_create_qp; 2701 ibdev->ib_dev.modify_qp = mlx4_ib_modify_qp; 2702 ibdev->ib_dev.query_qp = mlx4_ib_query_qp; 2703 ibdev->ib_dev.destroy_qp = mlx4_ib_destroy_qp; 2704 ibdev->ib_dev.post_send = mlx4_ib_post_send; 2705 ibdev->ib_dev.post_recv = mlx4_ib_post_recv; 2706 ibdev->ib_dev.create_cq = mlx4_ib_create_cq; 2707 ibdev->ib_dev.modify_cq = mlx4_ib_modify_cq; 2708 ibdev->ib_dev.resize_cq = mlx4_ib_resize_cq; 2709 ibdev->ib_dev.destroy_cq = mlx4_ib_destroy_cq; 2710 ibdev->ib_dev.poll_cq = mlx4_ib_poll_cq; 2711 ibdev->ib_dev.req_notify_cq = mlx4_ib_arm_cq; 2712 ibdev->ib_dev.get_dma_mr = mlx4_ib_get_dma_mr; 2713 ibdev->ib_dev.reg_user_mr = mlx4_ib_reg_user_mr; 2714 ibdev->ib_dev.rereg_user_mr = mlx4_ib_rereg_user_mr; 2715 ibdev->ib_dev.dereg_mr = mlx4_ib_dereg_mr; 2716 ibdev->ib_dev.alloc_mr = mlx4_ib_alloc_mr; 2717 ibdev->ib_dev.map_mr_sg = mlx4_ib_map_mr_sg; 2718 ibdev->ib_dev.attach_mcast = mlx4_ib_mcg_attach; 2719 ibdev->ib_dev.detach_mcast = mlx4_ib_mcg_detach; 2720 ibdev->ib_dev.process_mad = mlx4_ib_process_mad; 2721 ibdev->ib_dev.get_port_immutable = mlx4_port_immutable; 2722 ibdev->ib_dev.get_dev_fw_str = get_fw_ver_str; 2723 ibdev->ib_dev.disassociate_ucontext = mlx4_ib_disassociate_ucontext; 2724 2725 ibdev->ib_dev.uverbs_ex_cmd_mask |= 2726 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ); 2727 2728 if ((dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS) && 2729 ((mlx4_ib_port_link_layer(&ibdev->ib_dev, 1) == 2730 IB_LINK_LAYER_ETHERNET) || 2731 (mlx4_ib_port_link_layer(&ibdev->ib_dev, 2) == 2732 IB_LINK_LAYER_ETHERNET))) { 2733 ibdev->ib_dev.create_wq = mlx4_ib_create_wq; 2734 ibdev->ib_dev.modify_wq = mlx4_ib_modify_wq; 2735 ibdev->ib_dev.destroy_wq = mlx4_ib_destroy_wq; 2736 ibdev->ib_dev.create_rwq_ind_table = 2737 mlx4_ib_create_rwq_ind_table; 2738 ibdev->ib_dev.destroy_rwq_ind_table = 2739 mlx4_ib_destroy_rwq_ind_table; 2740 ibdev->ib_dev.uverbs_ex_cmd_mask |= 2741 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) | 2742 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) | 2743 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) | 2744 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) | 2745 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL); 2746 } 2747 2748 if (!mlx4_is_slave(ibdev->dev)) { 2749 ibdev->ib_dev.alloc_fmr = mlx4_ib_fmr_alloc; 2750 ibdev->ib_dev.map_phys_fmr = mlx4_ib_map_phys_fmr; 2751 ibdev->ib_dev.unmap_fmr = mlx4_ib_unmap_fmr; 2752 ibdev->ib_dev.dealloc_fmr = mlx4_ib_fmr_dealloc; 2753 } 2754 2755 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW || 2756 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) { 2757 ibdev->ib_dev.alloc_mw = mlx4_ib_alloc_mw; 2758 ibdev->ib_dev.dealloc_mw = mlx4_ib_dealloc_mw; 2759 2760 ibdev->ib_dev.uverbs_cmd_mask |= 2761 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) | 2762 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW); 2763 } 2764 2765 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) { 2766 ibdev->ib_dev.alloc_xrcd = mlx4_ib_alloc_xrcd; 2767 ibdev->ib_dev.dealloc_xrcd = mlx4_ib_dealloc_xrcd; 2768 ibdev->ib_dev.uverbs_cmd_mask |= 2769 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) | 2770 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD); 2771 } 2772 2773 if (check_flow_steering_support(dev)) { 2774 ibdev->steering_support = MLX4_STEERING_MODE_DEVICE_MANAGED; 2775 ibdev->ib_dev.create_flow = mlx4_ib_create_flow; 2776 ibdev->ib_dev.destroy_flow = mlx4_ib_destroy_flow; 2777 2778 ibdev->ib_dev.uverbs_ex_cmd_mask |= 2779 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) | 2780 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW); 2781 } 2782 2783 ibdev->ib_dev.uverbs_ex_cmd_mask |= 2784 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) | 2785 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) | 2786 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP); 2787 2788 mlx4_ib_alloc_eqs(dev, ibdev); 2789 2790 spin_lock_init(&iboe->lock); 2791 2792 if (init_node_data(ibdev)) 2793 goto err_map; 2794 mlx4_init_sl2vl_tbl(ibdev); 2795 2796 for (i = 0; i < ibdev->num_ports; ++i) { 2797 mutex_init(&ibdev->counters_table[i].mutex); 2798 INIT_LIST_HEAD(&ibdev->counters_table[i].counters_list); 2799 } 2800 2801 num_req_counters = mlx4_is_bonded(dev) ? 1 : ibdev->num_ports; 2802 for (i = 0; i < num_req_counters; ++i) { 2803 mutex_init(&ibdev->qp1_proxy_lock[i]); 2804 allocated = 0; 2805 if (mlx4_ib_port_link_layer(&ibdev->ib_dev, i + 1) == 2806 IB_LINK_LAYER_ETHERNET) { 2807 err = mlx4_counter_alloc(ibdev->dev, &counter_index, 2808 MLX4_RES_USAGE_DRIVER); 2809 /* if failed to allocate a new counter, use default */ 2810 if (err) 2811 counter_index = 2812 mlx4_get_default_counter_index(dev, 2813 i + 1); 2814 else 2815 allocated = 1; 2816 } else { /* IB_LINK_LAYER_INFINIBAND use the default counter */ 2817 counter_index = mlx4_get_default_counter_index(dev, 2818 i + 1); 2819 } 2820 new_counter_index = kmalloc(sizeof(*new_counter_index), 2821 GFP_KERNEL); 2822 if (!new_counter_index) { 2823 if (allocated) 2824 mlx4_counter_free(ibdev->dev, counter_index); 2825 goto err_counter; 2826 } 2827 new_counter_index->index = counter_index; 2828 new_counter_index->allocated = allocated; 2829 list_add_tail(&new_counter_index->list, 2830 &ibdev->counters_table[i].counters_list); 2831 ibdev->counters_table[i].default_counter = counter_index; 2832 pr_info("counter index %d for port %d allocated %d\n", 2833 counter_index, i + 1, allocated); 2834 } 2835 if (mlx4_is_bonded(dev)) 2836 for (i = 1; i < ibdev->num_ports ; ++i) { 2837 new_counter_index = 2838 kmalloc(sizeof(struct counter_index), 2839 GFP_KERNEL); 2840 if (!new_counter_index) 2841 goto err_counter; 2842 new_counter_index->index = counter_index; 2843 new_counter_index->allocated = 0; 2844 list_add_tail(&new_counter_index->list, 2845 &ibdev->counters_table[i].counters_list); 2846 ibdev->counters_table[i].default_counter = 2847 counter_index; 2848 } 2849 2850 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) 2851 ib_num_ports++; 2852 2853 spin_lock_init(&ibdev->sm_lock); 2854 mutex_init(&ibdev->cap_mask_mutex); 2855 INIT_LIST_HEAD(&ibdev->qp_list); 2856 spin_lock_init(&ibdev->reset_flow_resource_lock); 2857 2858 if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED && 2859 ib_num_ports) { 2860 ibdev->steer_qpn_count = MLX4_IB_UC_MAX_NUM_QPS; 2861 err = mlx4_qp_reserve_range(dev, ibdev->steer_qpn_count, 2862 MLX4_IB_UC_STEER_QPN_ALIGN, 2863 &ibdev->steer_qpn_base, 0, 2864 MLX4_RES_USAGE_DRIVER); 2865 if (err) 2866 goto err_counter; 2867 2868 ibdev->ib_uc_qpns_bitmap = 2869 kmalloc_array(BITS_TO_LONGS(ibdev->steer_qpn_count), 2870 sizeof(long), 2871 GFP_KERNEL); 2872 if (!ibdev->ib_uc_qpns_bitmap) 2873 goto err_steer_qp_release; 2874 2875 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB) { 2876 bitmap_zero(ibdev->ib_uc_qpns_bitmap, 2877 ibdev->steer_qpn_count); 2878 err = mlx4_FLOW_STEERING_IB_UC_QP_RANGE( 2879 dev, ibdev->steer_qpn_base, 2880 ibdev->steer_qpn_base + 2881 ibdev->steer_qpn_count - 1); 2882 if (err) 2883 goto err_steer_free_bitmap; 2884 } else { 2885 bitmap_fill(ibdev->ib_uc_qpns_bitmap, 2886 ibdev->steer_qpn_count); 2887 } 2888 } 2889 2890 for (j = 1; j <= ibdev->dev->caps.num_ports; j++) 2891 atomic64_set(&iboe->mac[j - 1], ibdev->dev->caps.def_mac[j]); 2892 2893 if (mlx4_ib_alloc_diag_counters(ibdev)) 2894 goto err_steer_free_bitmap; 2895 2896 ibdev->ib_dev.driver_id = RDMA_DRIVER_MLX4; 2897 if (ib_register_device(&ibdev->ib_dev, NULL)) 2898 goto err_diag_counters; 2899 2900 if (mlx4_ib_mad_init(ibdev)) 2901 goto err_reg; 2902 2903 if (mlx4_ib_init_sriov(ibdev)) 2904 goto err_mad; 2905 2906 if (!iboe->nb.notifier_call) { 2907 iboe->nb.notifier_call = mlx4_ib_netdev_event; 2908 err = register_netdevice_notifier(&iboe->nb); 2909 if (err) { 2910 iboe->nb.notifier_call = NULL; 2911 goto err_notif; 2912 } 2913 } 2914 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) { 2915 err = mlx4_config_roce_v2_port(dev, ROCE_V2_UDP_DPORT); 2916 if (err) 2917 goto err_notif; 2918 } 2919 2920 for (j = 0; j < ARRAY_SIZE(mlx4_class_attributes); ++j) { 2921 if (device_create_file(&ibdev->ib_dev.dev, 2922 mlx4_class_attributes[j])) 2923 goto err_notif; 2924 } 2925 2926 ibdev->ib_active = true; 2927 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) 2928 devlink_port_type_ib_set(mlx4_get_devlink_port(dev, i), 2929 &ibdev->ib_dev); 2930 2931 if (mlx4_is_mfunc(ibdev->dev)) 2932 init_pkeys(ibdev); 2933 2934 /* create paravirt contexts for any VFs which are active */ 2935 if (mlx4_is_master(ibdev->dev)) { 2936 for (j = 0; j < MLX4_MFUNC_MAX; j++) { 2937 if (j == mlx4_master_func_num(ibdev->dev)) 2938 continue; 2939 if (mlx4_is_slave_active(ibdev->dev, j)) 2940 do_slave_init(ibdev, j, 1); 2941 } 2942 } 2943 return ibdev; 2944 2945 err_notif: 2946 if (ibdev->iboe.nb.notifier_call) { 2947 if (unregister_netdevice_notifier(&ibdev->iboe.nb)) 2948 pr_warn("failure unregistering notifier\n"); 2949 ibdev->iboe.nb.notifier_call = NULL; 2950 } 2951 flush_workqueue(wq); 2952 2953 mlx4_ib_close_sriov(ibdev); 2954 2955 err_mad: 2956 mlx4_ib_mad_cleanup(ibdev); 2957 2958 err_reg: 2959 ib_unregister_device(&ibdev->ib_dev); 2960 2961 err_diag_counters: 2962 mlx4_ib_diag_cleanup(ibdev); 2963 2964 err_steer_free_bitmap: 2965 kfree(ibdev->ib_uc_qpns_bitmap); 2966 2967 err_steer_qp_release: 2968 mlx4_qp_release_range(dev, ibdev->steer_qpn_base, 2969 ibdev->steer_qpn_count); 2970 err_counter: 2971 for (i = 0; i < ibdev->num_ports; ++i) 2972 mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[i]); 2973 2974 err_map: 2975 mlx4_ib_free_eqs(dev, ibdev); 2976 iounmap(ibdev->uar_map); 2977 2978 err_uar: 2979 mlx4_uar_free(dev, &ibdev->priv_uar); 2980 2981 err_pd: 2982 mlx4_pd_free(dev, ibdev->priv_pdn); 2983 2984 err_dealloc: 2985 ib_dealloc_device(&ibdev->ib_dev); 2986 2987 return NULL; 2988 } 2989 2990 int mlx4_ib_steer_qp_alloc(struct mlx4_ib_dev *dev, int count, int *qpn) 2991 { 2992 int offset; 2993 2994 WARN_ON(!dev->ib_uc_qpns_bitmap); 2995 2996 offset = bitmap_find_free_region(dev->ib_uc_qpns_bitmap, 2997 dev->steer_qpn_count, 2998 get_count_order(count)); 2999 if (offset < 0) 3000 return offset; 3001 3002 *qpn = dev->steer_qpn_base + offset; 3003 return 0; 3004 } 3005 3006 void mlx4_ib_steer_qp_free(struct mlx4_ib_dev *dev, u32 qpn, int count) 3007 { 3008 if (!qpn || 3009 dev->steering_support != MLX4_STEERING_MODE_DEVICE_MANAGED) 3010 return; 3011 3012 if (WARN(qpn < dev->steer_qpn_base, "qpn = %u, steer_qpn_base = %u\n", 3013 qpn, dev->steer_qpn_base)) 3014 /* not supposed to be here */ 3015 return; 3016 3017 bitmap_release_region(dev->ib_uc_qpns_bitmap, 3018 qpn - dev->steer_qpn_base, 3019 get_count_order(count)); 3020 } 3021 3022 int mlx4_ib_steer_qp_reg(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp, 3023 int is_attach) 3024 { 3025 int err; 3026 size_t flow_size; 3027 struct ib_flow_attr *flow = NULL; 3028 struct ib_flow_spec_ib *ib_spec; 3029 3030 if (is_attach) { 3031 flow_size = sizeof(struct ib_flow_attr) + 3032 sizeof(struct ib_flow_spec_ib); 3033 flow = kzalloc(flow_size, GFP_KERNEL); 3034 if (!flow) 3035 return -ENOMEM; 3036 flow->port = mqp->port; 3037 flow->num_of_specs = 1; 3038 flow->size = flow_size; 3039 ib_spec = (struct ib_flow_spec_ib *)(flow + 1); 3040 ib_spec->type = IB_FLOW_SPEC_IB; 3041 ib_spec->size = sizeof(struct ib_flow_spec_ib); 3042 /* Add an empty rule for IB L2 */ 3043 memset(&ib_spec->mask, 0, sizeof(ib_spec->mask)); 3044 3045 err = __mlx4_ib_create_flow(&mqp->ibqp, flow, 3046 IB_FLOW_DOMAIN_NIC, 3047 MLX4_FS_REGULAR, 3048 &mqp->reg_id); 3049 } else { 3050 err = __mlx4_ib_destroy_flow(mdev->dev, mqp->reg_id); 3051 } 3052 kfree(flow); 3053 return err; 3054 } 3055 3056 static void mlx4_ib_remove(struct mlx4_dev *dev, void *ibdev_ptr) 3057 { 3058 struct mlx4_ib_dev *ibdev = ibdev_ptr; 3059 int p; 3060 int i; 3061 3062 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) 3063 devlink_port_type_clear(mlx4_get_devlink_port(dev, i)); 3064 ibdev->ib_active = false; 3065 flush_workqueue(wq); 3066 3067 mlx4_ib_close_sriov(ibdev); 3068 mlx4_ib_mad_cleanup(ibdev); 3069 ib_unregister_device(&ibdev->ib_dev); 3070 mlx4_ib_diag_cleanup(ibdev); 3071 if (ibdev->iboe.nb.notifier_call) { 3072 if (unregister_netdevice_notifier(&ibdev->iboe.nb)) 3073 pr_warn("failure unregistering notifier\n"); 3074 ibdev->iboe.nb.notifier_call = NULL; 3075 } 3076 3077 mlx4_qp_release_range(dev, ibdev->steer_qpn_base, 3078 ibdev->steer_qpn_count); 3079 kfree(ibdev->ib_uc_qpns_bitmap); 3080 3081 iounmap(ibdev->uar_map); 3082 for (p = 0; p < ibdev->num_ports; ++p) 3083 mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[p]); 3084 3085 mlx4_foreach_port(p, dev, MLX4_PORT_TYPE_IB) 3086 mlx4_CLOSE_PORT(dev, p); 3087 3088 mlx4_ib_free_eqs(dev, ibdev); 3089 3090 mlx4_uar_free(dev, &ibdev->priv_uar); 3091 mlx4_pd_free(dev, ibdev->priv_pdn); 3092 ib_dealloc_device(&ibdev->ib_dev); 3093 } 3094 3095 static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init) 3096 { 3097 struct mlx4_ib_demux_work **dm = NULL; 3098 struct mlx4_dev *dev = ibdev->dev; 3099 int i; 3100 unsigned long flags; 3101 struct mlx4_active_ports actv_ports; 3102 unsigned int ports; 3103 unsigned int first_port; 3104 3105 if (!mlx4_is_master(dev)) 3106 return; 3107 3108 actv_ports = mlx4_get_active_ports(dev, slave); 3109 ports = bitmap_weight(actv_ports.ports, dev->caps.num_ports); 3110 first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports); 3111 3112 dm = kcalloc(ports, sizeof(*dm), GFP_ATOMIC); 3113 if (!dm) 3114 return; 3115 3116 for (i = 0; i < ports; i++) { 3117 dm[i] = kmalloc(sizeof (struct mlx4_ib_demux_work), GFP_ATOMIC); 3118 if (!dm[i]) { 3119 while (--i >= 0) 3120 kfree(dm[i]); 3121 goto out; 3122 } 3123 INIT_WORK(&dm[i]->work, mlx4_ib_tunnels_update_work); 3124 dm[i]->port = first_port + i + 1; 3125 dm[i]->slave = slave; 3126 dm[i]->do_init = do_init; 3127 dm[i]->dev = ibdev; 3128 } 3129 /* initialize or tear down tunnel QPs for the slave */ 3130 spin_lock_irqsave(&ibdev->sriov.going_down_lock, flags); 3131 if (!ibdev->sriov.is_going_down) { 3132 for (i = 0; i < ports; i++) 3133 queue_work(ibdev->sriov.demux[i].ud_wq, &dm[i]->work); 3134 spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags); 3135 } else { 3136 spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags); 3137 for (i = 0; i < ports; i++) 3138 kfree(dm[i]); 3139 } 3140 out: 3141 kfree(dm); 3142 return; 3143 } 3144 3145 static void mlx4_ib_handle_catas_error(struct mlx4_ib_dev *ibdev) 3146 { 3147 struct mlx4_ib_qp *mqp; 3148 unsigned long flags_qp; 3149 unsigned long flags_cq; 3150 struct mlx4_ib_cq *send_mcq, *recv_mcq; 3151 struct list_head cq_notify_list; 3152 struct mlx4_cq *mcq; 3153 unsigned long flags; 3154 3155 pr_warn("mlx4_ib_handle_catas_error was started\n"); 3156 INIT_LIST_HEAD(&cq_notify_list); 3157 3158 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 3159 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 3160 3161 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 3162 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 3163 if (mqp->sq.tail != mqp->sq.head) { 3164 send_mcq = to_mcq(mqp->ibqp.send_cq); 3165 spin_lock_irqsave(&send_mcq->lock, flags_cq); 3166 if (send_mcq->mcq.comp && 3167 mqp->ibqp.send_cq->comp_handler) { 3168 if (!send_mcq->mcq.reset_notify_added) { 3169 send_mcq->mcq.reset_notify_added = 1; 3170 list_add_tail(&send_mcq->mcq.reset_notify, 3171 &cq_notify_list); 3172 } 3173 } 3174 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 3175 } 3176 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 3177 /* Now, handle the QP's receive queue */ 3178 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 3179 /* no handling is needed for SRQ */ 3180 if (!mqp->ibqp.srq) { 3181 if (mqp->rq.tail != mqp->rq.head) { 3182 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 3183 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 3184 if (recv_mcq->mcq.comp && 3185 mqp->ibqp.recv_cq->comp_handler) { 3186 if (!recv_mcq->mcq.reset_notify_added) { 3187 recv_mcq->mcq.reset_notify_added = 1; 3188 list_add_tail(&recv_mcq->mcq.reset_notify, 3189 &cq_notify_list); 3190 } 3191 } 3192 spin_unlock_irqrestore(&recv_mcq->lock, 3193 flags_cq); 3194 } 3195 } 3196 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 3197 } 3198 3199 list_for_each_entry(mcq, &cq_notify_list, reset_notify) { 3200 mcq->comp(mcq); 3201 } 3202 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 3203 pr_warn("mlx4_ib_handle_catas_error ended\n"); 3204 } 3205 3206 static void handle_bonded_port_state_event(struct work_struct *work) 3207 { 3208 struct ib_event_work *ew = 3209 container_of(work, struct ib_event_work, work); 3210 struct mlx4_ib_dev *ibdev = ew->ib_dev; 3211 enum ib_port_state bonded_port_state = IB_PORT_NOP; 3212 int i; 3213 struct ib_event ibev; 3214 3215 kfree(ew); 3216 spin_lock_bh(&ibdev->iboe.lock); 3217 for (i = 0; i < MLX4_MAX_PORTS; ++i) { 3218 struct net_device *curr_netdev = ibdev->iboe.netdevs[i]; 3219 enum ib_port_state curr_port_state; 3220 3221 if (!curr_netdev) 3222 continue; 3223 3224 curr_port_state = 3225 (netif_running(curr_netdev) && 3226 netif_carrier_ok(curr_netdev)) ? 3227 IB_PORT_ACTIVE : IB_PORT_DOWN; 3228 3229 bonded_port_state = (bonded_port_state != IB_PORT_ACTIVE) ? 3230 curr_port_state : IB_PORT_ACTIVE; 3231 } 3232 spin_unlock_bh(&ibdev->iboe.lock); 3233 3234 ibev.device = &ibdev->ib_dev; 3235 ibev.element.port_num = 1; 3236 ibev.event = (bonded_port_state == IB_PORT_ACTIVE) ? 3237 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 3238 3239 ib_dispatch_event(&ibev); 3240 } 3241 3242 void mlx4_ib_sl2vl_update(struct mlx4_ib_dev *mdev, int port) 3243 { 3244 u64 sl2vl; 3245 int err; 3246 3247 err = mlx4_ib_query_sl2vl(&mdev->ib_dev, port, &sl2vl); 3248 if (err) { 3249 pr_err("Unable to get current sl to vl mapping for port %d. Using all zeroes (%d)\n", 3250 port, err); 3251 sl2vl = 0; 3252 } 3253 atomic64_set(&mdev->sl2vl[port - 1], sl2vl); 3254 } 3255 3256 static void ib_sl2vl_update_work(struct work_struct *work) 3257 { 3258 struct ib_event_work *ew = container_of(work, struct ib_event_work, work); 3259 struct mlx4_ib_dev *mdev = ew->ib_dev; 3260 int port = ew->port; 3261 3262 mlx4_ib_sl2vl_update(mdev, port); 3263 3264 kfree(ew); 3265 } 3266 3267 void mlx4_sched_ib_sl2vl_update_work(struct mlx4_ib_dev *ibdev, 3268 int port) 3269 { 3270 struct ib_event_work *ew; 3271 3272 ew = kmalloc(sizeof(*ew), GFP_ATOMIC); 3273 if (ew) { 3274 INIT_WORK(&ew->work, ib_sl2vl_update_work); 3275 ew->port = port; 3276 ew->ib_dev = ibdev; 3277 queue_work(wq, &ew->work); 3278 } 3279 } 3280 3281 static void mlx4_ib_event(struct mlx4_dev *dev, void *ibdev_ptr, 3282 enum mlx4_dev_event event, unsigned long param) 3283 { 3284 struct ib_event ibev; 3285 struct mlx4_ib_dev *ibdev = to_mdev((struct ib_device *) ibdev_ptr); 3286 struct mlx4_eqe *eqe = NULL; 3287 struct ib_event_work *ew; 3288 int p = 0; 3289 3290 if (mlx4_is_bonded(dev) && 3291 ((event == MLX4_DEV_EVENT_PORT_UP) || 3292 (event == MLX4_DEV_EVENT_PORT_DOWN))) { 3293 ew = kmalloc(sizeof(*ew), GFP_ATOMIC); 3294 if (!ew) 3295 return; 3296 INIT_WORK(&ew->work, handle_bonded_port_state_event); 3297 ew->ib_dev = ibdev; 3298 queue_work(wq, &ew->work); 3299 return; 3300 } 3301 3302 if (event == MLX4_DEV_EVENT_PORT_MGMT_CHANGE) 3303 eqe = (struct mlx4_eqe *)param; 3304 else 3305 p = (int) param; 3306 3307 switch (event) { 3308 case MLX4_DEV_EVENT_PORT_UP: 3309 if (p > ibdev->num_ports) 3310 return; 3311 if (!mlx4_is_slave(dev) && 3312 rdma_port_get_link_layer(&ibdev->ib_dev, p) == 3313 IB_LINK_LAYER_INFINIBAND) { 3314 if (mlx4_is_master(dev)) 3315 mlx4_ib_invalidate_all_guid_record(ibdev, p); 3316 if (ibdev->dev->flags & MLX4_FLAG_SECURE_HOST && 3317 !(ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT)) 3318 mlx4_sched_ib_sl2vl_update_work(ibdev, p); 3319 } 3320 ibev.event = IB_EVENT_PORT_ACTIVE; 3321 break; 3322 3323 case MLX4_DEV_EVENT_PORT_DOWN: 3324 if (p > ibdev->num_ports) 3325 return; 3326 ibev.event = IB_EVENT_PORT_ERR; 3327 break; 3328 3329 case MLX4_DEV_EVENT_CATASTROPHIC_ERROR: 3330 ibdev->ib_active = false; 3331 ibev.event = IB_EVENT_DEVICE_FATAL; 3332 mlx4_ib_handle_catas_error(ibdev); 3333 break; 3334 3335 case MLX4_DEV_EVENT_PORT_MGMT_CHANGE: 3336 ew = kmalloc(sizeof *ew, GFP_ATOMIC); 3337 if (!ew) 3338 break; 3339 3340 INIT_WORK(&ew->work, handle_port_mgmt_change_event); 3341 memcpy(&ew->ib_eqe, eqe, sizeof *eqe); 3342 ew->ib_dev = ibdev; 3343 /* need to queue only for port owner, which uses GEN_EQE */ 3344 if (mlx4_is_master(dev)) 3345 queue_work(wq, &ew->work); 3346 else 3347 handle_port_mgmt_change_event(&ew->work); 3348 return; 3349 3350 case MLX4_DEV_EVENT_SLAVE_INIT: 3351 /* here, p is the slave id */ 3352 do_slave_init(ibdev, p, 1); 3353 if (mlx4_is_master(dev)) { 3354 int i; 3355 3356 for (i = 1; i <= ibdev->num_ports; i++) { 3357 if (rdma_port_get_link_layer(&ibdev->ib_dev, i) 3358 == IB_LINK_LAYER_INFINIBAND) 3359 mlx4_ib_slave_alias_guid_event(ibdev, 3360 p, i, 3361 1); 3362 } 3363 } 3364 return; 3365 3366 case MLX4_DEV_EVENT_SLAVE_SHUTDOWN: 3367 if (mlx4_is_master(dev)) { 3368 int i; 3369 3370 for (i = 1; i <= ibdev->num_ports; i++) { 3371 if (rdma_port_get_link_layer(&ibdev->ib_dev, i) 3372 == IB_LINK_LAYER_INFINIBAND) 3373 mlx4_ib_slave_alias_guid_event(ibdev, 3374 p, i, 3375 0); 3376 } 3377 } 3378 /* here, p is the slave id */ 3379 do_slave_init(ibdev, p, 0); 3380 return; 3381 3382 default: 3383 return; 3384 } 3385 3386 ibev.device = ibdev_ptr; 3387 ibev.element.port_num = mlx4_is_bonded(ibdev->dev) ? 1 : (u8)p; 3388 3389 ib_dispatch_event(&ibev); 3390 } 3391 3392 static struct mlx4_interface mlx4_ib_interface = { 3393 .add = mlx4_ib_add, 3394 .remove = mlx4_ib_remove, 3395 .event = mlx4_ib_event, 3396 .protocol = MLX4_PROT_IB_IPV6, 3397 .flags = MLX4_INTFF_BONDING 3398 }; 3399 3400 static int __init mlx4_ib_init(void) 3401 { 3402 int err; 3403 3404 wq = alloc_ordered_workqueue("mlx4_ib", WQ_MEM_RECLAIM); 3405 if (!wq) 3406 return -ENOMEM; 3407 3408 err = mlx4_ib_mcg_init(); 3409 if (err) 3410 goto clean_wq; 3411 3412 err = mlx4_register_interface(&mlx4_ib_interface); 3413 if (err) 3414 goto clean_mcg; 3415 3416 return 0; 3417 3418 clean_mcg: 3419 mlx4_ib_mcg_destroy(); 3420 3421 clean_wq: 3422 destroy_workqueue(wq); 3423 return err; 3424 } 3425 3426 static void __exit mlx4_ib_cleanup(void) 3427 { 3428 mlx4_unregister_interface(&mlx4_ib_interface); 3429 mlx4_ib_mcg_destroy(); 3430 destroy_workqueue(wq); 3431 } 3432 3433 module_init(mlx4_ib_init); 3434 module_exit(mlx4_ib_cleanup); 3435